1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[20];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 delim
= get_symbol_name (& name
);
2872 end_name
= input_line_pointer
;
2873 (void) restore_line_pointer (delim
);
2875 if (*input_line_pointer
!= ',')
2878 as_bad (_("expected comma after name \"%s\""), name
);
2880 ignore_rest_of_line ();
2884 input_line_pointer
++;
2887 if (name
[0] == '.' && name
[1] == '\0')
2889 /* XXX - this should not happen to .thumb_set. */
2893 if ((symbolP
= symbol_find (name
)) == NULL
2894 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2897 /* When doing symbol listings, play games with dummy fragments living
2898 outside the normal fragment chain to record the file and line info
2900 if (listing
& LISTING_SYMBOLS
)
2902 extern struct list_info_struct
* listing_tail
;
2903 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2905 memset (dummy_frag
, 0, sizeof (fragS
));
2906 dummy_frag
->fr_type
= rs_fill
;
2907 dummy_frag
->line
= listing_tail
;
2908 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2909 dummy_frag
->fr_symbol
= symbolP
;
2913 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2916 /* "set" symbols are local unless otherwise specified. */
2917 SF_SET_LOCAL (symbolP
);
2918 #endif /* OBJ_COFF */
2919 } /* Make a new symbol. */
2921 symbol_table_insert (symbolP
);
2926 && S_IS_DEFINED (symbolP
)
2927 && S_GET_SEGMENT (symbolP
) != reg_section
)
2928 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2930 pseudo_set (symbolP
);
2932 demand_empty_rest_of_line ();
2934 /* XXX Now we come to the Thumb specific bit of code. */
2936 THUMB_SET_FUNC (symbolP
, 1);
2937 ARM_SET_THUMB (symbolP
, 1);
2938 #if defined OBJ_ELF || defined OBJ_COFF
2939 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2943 /* Directives: Mode selection. */
2945 /* .syntax [unified|divided] - choose the new unified syntax
2946 (same for Arm and Thumb encoding, modulo slight differences in what
2947 can be represented) or the old divergent syntax for each mode. */
2949 s_syntax (int unused ATTRIBUTE_UNUSED
)
2953 delim
= get_symbol_name (& name
);
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 (void) restore_line_pointer (delim
);
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2971 s_bss (int ignore ATTRIBUTE_UNUSED
)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section
, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED
)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg
, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: CodeComposer Studio. */
2997 /* .ref (for CodeComposer Studio syntax only). */
2999 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3001 if (codecomposer_syntax
)
3002 ignore_rest_of_line ();
3004 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3007 /* If name is not NULL, then it is used for marking the beginning of a
3008 function, wherease if it is NULL then it means the function end. */
3010 asmfunc_debug (const char * name
)
3012 static const char * last_name
= NULL
;
3016 gas_assert (last_name
== NULL
);
3019 if (debug_type
== DEBUG_STABS
)
3020 stabs_generate_asm_func (name
, name
);
3024 gas_assert (last_name
!= NULL
);
3026 if (debug_type
== DEBUG_STABS
)
3027 stabs_generate_asm_endfunc (last_name
, last_name
);
3034 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3036 if (codecomposer_syntax
)
3038 switch (asmfunc_state
)
3040 case OUTSIDE_ASMFUNC
:
3041 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3044 case WAITING_ASMFUNC_NAME
:
3045 as_bad (_(".asmfunc repeated."));
3048 case WAITING_ENDASMFUNC
:
3049 as_bad (_(".asmfunc without function."));
3052 demand_empty_rest_of_line ();
3055 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3059 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3063 switch (asmfunc_state
)
3065 case OUTSIDE_ASMFUNC
:
3066 as_bad (_(".endasmfunc without a .asmfunc."));
3069 case WAITING_ASMFUNC_NAME
:
3070 as_bad (_(".endasmfunc without function."));
3073 case WAITING_ENDASMFUNC
:
3074 asmfunc_state
= OUTSIDE_ASMFUNC
;
3075 asmfunc_debug (NULL
);
3078 demand_empty_rest_of_line ();
3081 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3085 s_ccs_def (int name
)
3087 if (codecomposer_syntax
)
3090 as_bad (_(".def pseudo-op only available with -mccs flag."));
3093 /* Directives: Literal pools. */
3095 static literal_pool
*
3096 find_literal_pool (void)
3098 literal_pool
* pool
;
3100 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3102 if (pool
->section
== now_seg
3103 && pool
->sub_section
== now_subseg
)
3110 static literal_pool
*
3111 find_or_make_literal_pool (void)
3113 /* Next literal pool ID number. */
3114 static unsigned int latest_pool_num
= 1;
3115 literal_pool
* pool
;
3117 pool
= find_literal_pool ();
3121 /* Create a new pool. */
3122 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3126 pool
->next_free_entry
= 0;
3127 pool
->section
= now_seg
;
3128 pool
->sub_section
= now_subseg
;
3129 pool
->next
= list_of_pools
;
3130 pool
->symbol
= NULL
;
3131 pool
->alignment
= 2;
3133 /* Add it to the list. */
3134 list_of_pools
= pool
;
3137 /* New pools, and emptied pools, will have a NULL symbol. */
3138 if (pool
->symbol
== NULL
)
3140 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3141 (valueT
) 0, &zero_address_frag
);
3142 pool
->id
= latest_pool_num
++;
3149 /* Add the literal in the global 'inst'
3150 structure to the relevant literal pool. */
3153 add_to_lit_pool (unsigned int nbytes
)
3155 #define PADDING_SLOT 0x1
3156 #define LIT_ENTRY_SIZE_MASK 0xFF
3157 literal_pool
* pool
;
3158 unsigned int entry
, pool_size
= 0;
3159 bfd_boolean padding_slot_p
= FALSE
;
3165 imm1
= inst
.operands
[1].imm
;
3166 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3167 : inst
.reloc
.exp
.X_unsigned
? 0
3168 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3169 if (target_big_endian
)
3172 imm2
= inst
.operands
[1].imm
;
3176 pool
= find_or_make_literal_pool ();
3178 /* Check if this literal value is already in the pool. */
3179 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3183 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3184 && (inst
.reloc
.exp
.X_op
== O_constant
)
3185 && (pool
->literals
[entry
].X_add_number
3186 == inst
.reloc
.exp
.X_add_number
)
3187 && (pool
->literals
[entry
].X_md
== nbytes
)
3188 && (pool
->literals
[entry
].X_unsigned
3189 == inst
.reloc
.exp
.X_unsigned
))
3192 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3193 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3194 && (pool
->literals
[entry
].X_add_number
3195 == inst
.reloc
.exp
.X_add_number
)
3196 && (pool
->literals
[entry
].X_add_symbol
3197 == inst
.reloc
.exp
.X_add_symbol
)
3198 && (pool
->literals
[entry
].X_op_symbol
3199 == inst
.reloc
.exp
.X_op_symbol
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
))
3203 else if ((nbytes
== 8)
3204 && !(pool_size
& 0x7)
3205 && ((entry
+ 1) != pool
->next_free_entry
)
3206 && (pool
->literals
[entry
].X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3208 && (pool
->literals
[entry
].X_unsigned
3209 == inst
.reloc
.exp
.X_unsigned
)
3210 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3211 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3212 && (pool
->literals
[entry
+ 1].X_unsigned
3213 == inst
.reloc
.exp
.X_unsigned
))
3216 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3217 if (padding_slot_p
&& (nbytes
== 4))
3223 /* Do we need to create a new entry? */
3224 if (entry
== pool
->next_free_entry
)
3226 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3228 inst
.error
= _("literal pool overflow");
3234 /* For 8-byte entries, we align to an 8-byte boundary,
3235 and split it into two 4-byte entries, because on 32-bit
3236 host, 8-byte constants are treated as big num, thus
3237 saved in "generic_bignum" which will be overwritten
3238 by later assignments.
3240 We also need to make sure there is enough space for
3243 We also check to make sure the literal operand is a
3245 if (!(inst
.reloc
.exp
.X_op
== O_constant
3246 || inst
.reloc
.exp
.X_op
== O_big
))
3248 inst
.error
= _("invalid type for literal pool");
3251 else if (pool_size
& 0x7)
3253 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3259 pool
->literals
[entry
] = inst
.reloc
.exp
;
3260 pool
->literals
[entry
].X_add_number
= 0;
3261 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3262 pool
->next_free_entry
+= 1;
3265 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_op
= O_constant
;
3273 pool
->literals
[entry
].X_add_number
= imm1
;
3274 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3275 pool
->literals
[entry
++].X_md
= 4;
3276 pool
->literals
[entry
] = inst
.reloc
.exp
;
3277 pool
->literals
[entry
].X_op
= O_constant
;
3278 pool
->literals
[entry
].X_add_number
= imm2
;
3279 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3280 pool
->literals
[entry
].X_md
= 4;
3281 pool
->alignment
= 3;
3282 pool
->next_free_entry
+= 1;
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_md
= 4;
3291 /* PR ld/12974: Record the location of the first source line to reference
3292 this entry in the literal pool. If it turns out during linking that the
3293 symbol does not exist we will be able to give an accurate line number for
3294 the (first use of the) missing reference. */
3295 if (debug_type
== DEBUG_DWARF2
)
3296 dwarf2_where (pool
->locs
+ entry
);
3298 pool
->next_free_entry
+= 1;
3300 else if (padding_slot_p
)
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_md
= nbytes
;
3306 inst
.reloc
.exp
.X_op
= O_symbol
;
3307 inst
.reloc
.exp
.X_add_number
= pool_size
;
3308 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3314 tc_start_label_without_colon (void)
3316 bfd_boolean ret
= TRUE
;
3318 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3320 const char *label
= input_line_pointer
;
3322 while (!is_end_of_line
[(int) label
[-1]])
3327 as_bad (_("Invalid label '%s'"), label
);
3331 asmfunc_debug (label
);
3333 asmfunc_state
= WAITING_ENDASMFUNC
;
3339 /* Can't use symbol_new here, so have to create a symbol and then at
3340 a later date assign it a value. Thats what these functions do. */
3343 symbol_locate (symbolS
* symbolP
,
3344 const char * name
, /* It is copied, the caller can modify. */
3345 segT segment
, /* Segment identifier (SEG_<something>). */
3346 valueT valu
, /* Symbol value. */
3347 fragS
* frag
) /* Associated fragment. */
3350 char * preserved_copy_of_name
;
3352 name_length
= strlen (name
) + 1; /* +1 for \0. */
3353 obstack_grow (¬es
, name
, name_length
);
3354 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3356 #ifdef tc_canonicalize_symbol_name
3357 preserved_copy_of_name
=
3358 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3361 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3363 S_SET_SEGMENT (symbolP
, segment
);
3364 S_SET_VALUE (symbolP
, valu
);
3365 symbol_clear_list_pointers (symbolP
);
3367 symbol_set_frag (symbolP
, frag
);
3369 /* Link to end of symbol chain. */
3371 extern int symbol_table_frozen
;
3373 if (symbol_table_frozen
)
3377 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3379 obj_symbol_new_hook (symbolP
);
3381 #ifdef tc_symbol_new_hook
3382 tc_symbol_new_hook (symbolP
);
3386 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3387 #endif /* DEBUG_SYMS */
3391 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3394 literal_pool
* pool
;
3397 pool
= find_literal_pool ();
3399 || pool
->symbol
== NULL
3400 || pool
->next_free_entry
== 0)
3403 /* Align pool as you have word accesses.
3404 Only make a frag if we have to. */
3406 frag_align (pool
->alignment
, 0, 0);
3408 record_alignment (now_seg
, 2);
3411 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3412 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3414 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3416 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3417 (valueT
) frag_now_fix (), frag_now
);
3418 symbol_table_insert (pool
->symbol
);
3420 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3422 #if defined OBJ_COFF || defined OBJ_ELF
3423 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3426 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3429 if (debug_type
== DEBUG_DWARF2
)
3430 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3432 /* First output the expression in the instruction to the pool. */
3433 emit_expr (&(pool
->literals
[entry
]),
3434 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3437 /* Mark the pool as empty. */
3438 pool
->next_free_entry
= 0;
3439 pool
->symbol
= NULL
;
3443 /* Forward declarations for functions below, in the MD interface
3445 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3446 static valueT
create_unwind_entry (int);
3447 static void start_unwind_section (const segT
, int);
3448 static void add_unwind_opcode (valueT
, int);
3449 static void flush_pending_unwind (void);
3451 /* Directives: Data. */
3454 s_arm_elf_cons (int nbytes
)
3458 #ifdef md_flush_pending_output
3459 md_flush_pending_output ();
3462 if (is_it_end_of_statement ())
3464 demand_empty_rest_of_line ();
3468 #ifdef md_cons_align
3469 md_cons_align (nbytes
);
3472 mapping_state (MAP_DATA
);
3476 char *base
= input_line_pointer
;
3480 if (exp
.X_op
!= O_symbol
)
3481 emit_expr (&exp
, (unsigned int) nbytes
);
3484 char *before_reloc
= input_line_pointer
;
3485 reloc
= parse_reloc (&input_line_pointer
);
3488 as_bad (_("unrecognized relocation suffix"));
3489 ignore_rest_of_line ();
3492 else if (reloc
== BFD_RELOC_UNUSED
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 reloc_howto_type
*howto
= (reloc_howto_type
*)
3497 bfd_reloc_type_lookup (stdoutput
,
3498 (bfd_reloc_code_real_type
) reloc
);
3499 int size
= bfd_get_reloc_size (howto
);
3501 if (reloc
== BFD_RELOC_ARM_PLT32
)
3503 as_bad (_("(plt) is only valid on branch targets"));
3504 reloc
= BFD_RELOC_UNUSED
;
3509 as_bad (_("%s relocations do not fit in %d bytes"),
3510 howto
->name
, nbytes
);
3513 /* We've parsed an expression stopping at O_symbol.
3514 But there may be more expression left now that we
3515 have parsed the relocation marker. Parse it again.
3516 XXX Surely there is a cleaner way to do this. */
3517 char *p
= input_line_pointer
;
3519 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3520 memcpy (save_buf
, base
, input_line_pointer
- base
);
3521 memmove (base
+ (input_line_pointer
- before_reloc
),
3522 base
, before_reloc
- base
);
3524 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3526 memcpy (base
, save_buf
, p
- base
);
3528 offset
= nbytes
- size
;
3529 p
= frag_more (nbytes
);
3530 memset (p
, 0, nbytes
);
3531 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3532 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3537 while (*input_line_pointer
++ == ',');
3539 /* Put terminator back into stream. */
3540 input_line_pointer
--;
3541 demand_empty_rest_of_line ();
3544 /* Emit an expression containing a 32-bit thumb instruction.
3545 Implementation based on put_thumb32_insn. */
3548 emit_thumb32_expr (expressionS
* exp
)
3550 expressionS exp_high
= *exp
;
3552 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3553 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3554 exp
->X_add_number
&= 0xffff;
3555 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3558 /* Guess the instruction size based on the opcode. */
3561 thumb_insn_size (int opcode
)
3563 if ((unsigned int) opcode
< 0xe800u
)
3565 else if ((unsigned int) opcode
>= 0xe8000000u
)
3572 emit_insn (expressionS
*exp
, int nbytes
)
3576 if (exp
->X_op
== O_constant
)
3581 size
= thumb_insn_size (exp
->X_add_number
);
3585 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3587 as_bad (_(".inst.n operand too big. "\
3588 "Use .inst.w instead"));
3593 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3594 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3596 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3598 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3599 emit_thumb32_expr (exp
);
3601 emit_expr (exp
, (unsigned int) size
);
3603 it_fsm_post_encode ();
3607 as_bad (_("cannot determine Thumb instruction size. " \
3608 "Use .inst.n/.inst.w instead"));
3611 as_bad (_("constant expression required"));
3616 /* Like s_arm_elf_cons but do not use md_cons_align and
3617 set the mapping state to MAP_ARM/MAP_THUMB. */
3620 s_arm_elf_inst (int nbytes
)
3622 if (is_it_end_of_statement ())
3624 demand_empty_rest_of_line ();
3628 /* Calling mapping_state () here will not change ARM/THUMB,
3629 but will ensure not to be in DATA state. */
3632 mapping_state (MAP_THUMB
);
3637 as_bad (_("width suffixes are invalid in ARM mode"));
3638 ignore_rest_of_line ();
3644 mapping_state (MAP_ARM
);
3653 if (! emit_insn (& exp
, nbytes
))
3655 ignore_rest_of_line ();
3659 while (*input_line_pointer
++ == ',');
3661 /* Put terminator back into stream. */
3662 input_line_pointer
--;
3663 demand_empty_rest_of_line ();
3666 /* Parse a .rel31 directive. */
3669 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3676 if (*input_line_pointer
== '1')
3677 highbit
= 0x80000000;
3678 else if (*input_line_pointer
!= '0')
3679 as_bad (_("expected 0 or 1"));
3681 input_line_pointer
++;
3682 if (*input_line_pointer
!= ',')
3683 as_bad (_("missing comma"));
3684 input_line_pointer
++;
3686 #ifdef md_flush_pending_output
3687 md_flush_pending_output ();
3690 #ifdef md_cons_align
3694 mapping_state (MAP_DATA
);
3699 md_number_to_chars (p
, highbit
, 4);
3700 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3701 BFD_RELOC_ARM_PREL31
);
3703 demand_empty_rest_of_line ();
3706 /* Directives: AEABI stack-unwind tables. */
3708 /* Parse an unwind_fnstart directive. Simply records the current location. */
3711 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3713 demand_empty_rest_of_line ();
3714 if (unwind
.proc_start
)
3716 as_bad (_("duplicate .fnstart directive"));
3720 /* Mark the start of the function. */
3721 unwind
.proc_start
= expr_build_dot ();
3723 /* Reset the rest of the unwind info. */
3724 unwind
.opcode_count
= 0;
3725 unwind
.table_entry
= NULL
;
3726 unwind
.personality_routine
= NULL
;
3727 unwind
.personality_index
= -1;
3728 unwind
.frame_size
= 0;
3729 unwind
.fp_offset
= 0;
3730 unwind
.fp_reg
= REG_SP
;
3732 unwind
.sp_restored
= 0;
3736 /* Parse a handlerdata directive. Creates the exception handling table entry
3737 for the function. */
3740 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3742 demand_empty_rest_of_line ();
3743 if (!unwind
.proc_start
)
3744 as_bad (MISSING_FNSTART
);
3746 if (unwind
.table_entry
)
3747 as_bad (_("duplicate .handlerdata directive"));
3749 create_unwind_entry (1);
3752 /* Parse an unwind_fnend directive. Generates the index table entry. */
3755 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3760 unsigned int marked_pr_dependency
;
3762 demand_empty_rest_of_line ();
3764 if (!unwind
.proc_start
)
3766 as_bad (_(".fnend directive without .fnstart"));
3770 /* Add eh table entry. */
3771 if (unwind
.table_entry
== NULL
)
3772 val
= create_unwind_entry (0);
3776 /* Add index table entry. This is two words. */
3777 start_unwind_section (unwind
.saved_seg
, 1);
3778 frag_align (2, 0, 0);
3779 record_alignment (now_seg
, 2);
3781 ptr
= frag_more (8);
3783 where
= frag_now_fix () - 8;
3785 /* Self relative offset of the function start. */
3786 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3787 BFD_RELOC_ARM_PREL31
);
3789 /* Indicate dependency on EHABI-defined personality routines to the
3790 linker, if it hasn't been done already. */
3791 marked_pr_dependency
3792 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3793 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3794 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3796 static const char *const name
[] =
3798 "__aeabi_unwind_cpp_pr0",
3799 "__aeabi_unwind_cpp_pr1",
3800 "__aeabi_unwind_cpp_pr2"
3802 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3803 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3804 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3805 |= 1 << unwind
.personality_index
;
3809 /* Inline exception table entry. */
3810 md_number_to_chars (ptr
+ 4, val
, 4);
3812 /* Self relative offset of the table entry. */
3813 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3814 BFD_RELOC_ARM_PREL31
);
3816 /* Restore the original section. */
3817 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3819 unwind
.proc_start
= NULL
;
3823 /* Parse an unwind_cantunwind directive. */
3826 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3828 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3830 as_bad (MISSING_FNSTART
);
3832 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3833 as_bad (_("personality routine specified for cantunwind frame"));
3835 unwind
.personality_index
= -2;
3839 /* Parse a personalityindex directive. */
3842 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3846 if (!unwind
.proc_start
)
3847 as_bad (MISSING_FNSTART
);
3849 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3850 as_bad (_("duplicate .personalityindex directive"));
3854 if (exp
.X_op
!= O_constant
3855 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3857 as_bad (_("bad personality routine number"));
3858 ignore_rest_of_line ();
3862 unwind
.personality_index
= exp
.X_add_number
;
3864 demand_empty_rest_of_line ();
3868 /* Parse a personality directive. */
3871 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("duplicate .personality directive"));
3881 c
= get_symbol_name (& name
);
3882 p
= input_line_pointer
;
3884 ++ input_line_pointer
;
3885 unwind
.personality_routine
= symbol_find_or_make (name
);
3887 demand_empty_rest_of_line ();
3891 /* Parse a directive saving core registers. */
3894 s_arm_unwind_save_core (void)
3900 range
= parse_reg_list (&input_line_pointer
);
3903 as_bad (_("expected register list"));
3904 ignore_rest_of_line ();
3908 demand_empty_rest_of_line ();
3910 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3911 into .unwind_save {..., sp...}. We aren't bothered about the value of
3912 ip because it is clobbered by calls. */
3913 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3914 && (range
& 0x3000) == 0x1000)
3916 unwind
.opcode_count
--;
3917 unwind
.sp_restored
= 0;
3918 range
= (range
| 0x2000) & ~0x1000;
3919 unwind
.pending_offset
= 0;
3925 /* See if we can use the short opcodes. These pop a block of up to 8
3926 registers starting with r4, plus maybe r14. */
3927 for (n
= 0; n
< 8; n
++)
3929 /* Break at the first non-saved register. */
3930 if ((range
& (1 << (n
+ 4))) == 0)
3933 /* See if there are any other bits set. */
3934 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3936 /* Use the long form. */
3937 op
= 0x8000 | ((range
>> 4) & 0xfff);
3938 add_unwind_opcode (op
, 2);
3942 /* Use the short form. */
3944 op
= 0xa8; /* Pop r14. */
3946 op
= 0xa0; /* Do not pop r14. */
3948 add_unwind_opcode (op
, 1);
3955 op
= 0xb100 | (range
& 0xf);
3956 add_unwind_opcode (op
, 2);
3959 /* Record the number of bytes pushed. */
3960 for (n
= 0; n
< 16; n
++)
3962 if (range
& (1 << n
))
3963 unwind
.frame_size
+= 4;
3968 /* Parse a directive saving FPA registers. */
3971 s_arm_unwind_save_fpa (int reg
)
3977 /* Get Number of registers to transfer. */
3978 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3981 exp
.X_op
= O_illegal
;
3983 if (exp
.X_op
!= O_constant
)
3985 as_bad (_("expected , <constant>"));
3986 ignore_rest_of_line ();
3990 num_regs
= exp
.X_add_number
;
3992 if (num_regs
< 1 || num_regs
> 4)
3994 as_bad (_("number of registers must be in the range [1:4]"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4004 op
= 0xb4 | (num_regs
- 1);
4005 add_unwind_opcode (op
, 1);
4010 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4011 add_unwind_opcode (op
, 2);
4013 unwind
.frame_size
+= num_regs
* 12;
4017 /* Parse a directive saving VFP registers for ARMv6 and above. */
4020 s_arm_unwind_save_vfp_armv6 (void)
4025 int num_vfpv3_regs
= 0;
4026 int num_regs_below_16
;
4028 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4031 as_bad (_("expected register list"));
4032 ignore_rest_of_line ();
4036 demand_empty_rest_of_line ();
4038 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4039 than FSTMX/FLDMX-style ones). */
4041 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4043 num_vfpv3_regs
= count
;
4044 else if (start
+ count
> 16)
4045 num_vfpv3_regs
= start
+ count
- 16;
4047 if (num_vfpv3_regs
> 0)
4049 int start_offset
= start
> 16 ? start
- 16 : 0;
4050 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4054 /* Generate opcode for registers numbered in the range 0 .. 15. */
4055 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4056 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4057 if (num_regs_below_16
> 0)
4059 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4060 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= count
* 8;
4067 /* Parse a directive saving VFP registers for pre-ARMv6. */
4070 s_arm_unwind_save_vfp (void)
4076 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4089 op
= 0xb8 | (count
- 1);
4090 add_unwind_opcode (op
, 1);
4095 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4096 add_unwind_opcode (op
, 2);
4098 unwind
.frame_size
+= count
* 8 + 4;
4102 /* Parse a directive saving iWMMXt data registers. */
4105 s_arm_unwind_save_mmxwr (void)
4113 if (*input_line_pointer
== '{')
4114 input_line_pointer
++;
4118 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4122 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4127 as_tsktsk (_("register list not in ascending order"));
4130 if (*input_line_pointer
== '-')
4132 input_line_pointer
++;
4133 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4136 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 else if (reg
>= hi_reg
)
4141 as_bad (_("bad register range"));
4144 for (; reg
< hi_reg
; reg
++)
4148 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4150 skip_past_char (&input_line_pointer
, '}');
4152 demand_empty_rest_of_line ();
4154 /* Generate any deferred opcodes because we're going to be looking at
4156 flush_pending_unwind ();
4158 for (i
= 0; i
< 16; i
++)
4160 if (mask
& (1 << i
))
4161 unwind
.frame_size
+= 8;
4164 /* Attempt to combine with a previous opcode. We do this because gcc
4165 likes to output separate unwind directives for a single block of
4167 if (unwind
.opcode_count
> 0)
4169 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4170 if ((i
& 0xf8) == 0xc0)
4173 /* Only merge if the blocks are contiguous. */
4176 if ((mask
& 0xfe00) == (1 << 9))
4178 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4179 unwind
.opcode_count
--;
4182 else if (i
== 6 && unwind
.opcode_count
>= 2)
4184 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4188 op
= 0xffff << (reg
- 1);
4190 && ((mask
& op
) == (1u << (reg
- 1))))
4192 op
= (1 << (reg
+ i
+ 1)) - 1;
4193 op
&= ~((1 << reg
) - 1);
4195 unwind
.opcode_count
-= 2;
4202 /* We want to generate opcodes in the order the registers have been
4203 saved, ie. descending order. */
4204 for (reg
= 15; reg
>= -1; reg
--)
4206 /* Save registers in blocks. */
4208 || !(mask
& (1 << reg
)))
4210 /* We found an unsaved reg. Generate opcodes to save the
4217 op
= 0xc0 | (hi_reg
- 10);
4218 add_unwind_opcode (op
, 1);
4223 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4224 add_unwind_opcode (op
, 2);
4233 ignore_rest_of_line ();
4237 s_arm_unwind_save_mmxwcg (void)
4244 if (*input_line_pointer
== '{')
4245 input_line_pointer
++;
4247 skip_whitespace (input_line_pointer
);
4251 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4255 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4261 as_tsktsk (_("register list not in ascending order"));
4264 if (*input_line_pointer
== '-')
4266 input_line_pointer
++;
4267 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4270 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 else if (reg
>= hi_reg
)
4275 as_bad (_("bad register range"));
4278 for (; reg
< hi_reg
; reg
++)
4282 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4284 skip_past_char (&input_line_pointer
, '}');
4286 demand_empty_rest_of_line ();
4288 /* Generate any deferred opcodes because we're going to be looking at
4290 flush_pending_unwind ();
4292 for (reg
= 0; reg
< 16; reg
++)
4294 if (mask
& (1 << reg
))
4295 unwind
.frame_size
+= 4;
4298 add_unwind_opcode (op
, 2);
4301 ignore_rest_of_line ();
4305 /* Parse an unwind_save directive.
4306 If the argument is non-zero, this is a .vsave directive. */
4309 s_arm_unwind_save (int arch_v6
)
4312 struct reg_entry
*reg
;
4313 bfd_boolean had_brace
= FALSE
;
4315 if (!unwind
.proc_start
)
4316 as_bad (MISSING_FNSTART
);
4318 /* Figure out what sort of save we have. */
4319 peek
= input_line_pointer
;
4327 reg
= arm_reg_parse_multi (&peek
);
4331 as_bad (_("register expected"));
4332 ignore_rest_of_line ();
4341 as_bad (_("FPA .unwind_save does not take a register list"));
4342 ignore_rest_of_line ();
4345 input_line_pointer
= peek
;
4346 s_arm_unwind_save_fpa (reg
->number
);
4350 s_arm_unwind_save_core ();
4355 s_arm_unwind_save_vfp_armv6 ();
4357 s_arm_unwind_save_vfp ();
4360 case REG_TYPE_MMXWR
:
4361 s_arm_unwind_save_mmxwr ();
4364 case REG_TYPE_MMXWCG
:
4365 s_arm_unwind_save_mmxwcg ();
4369 as_bad (_(".unwind_save does not support this kind of register"));
4370 ignore_rest_of_line ();
4375 /* Parse an unwind_movsp directive. */
4378 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4391 ignore_rest_of_line ();
4395 /* Optional constant. */
4396 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4398 if (immediate_for_directive (&offset
) == FAIL
)
4404 demand_empty_rest_of_line ();
4406 if (reg
== REG_SP
|| reg
== REG_PC
)
4408 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4412 if (unwind
.fp_reg
!= REG_SP
)
4413 as_bad (_("unexpected .unwind_movsp directive"));
4415 /* Generate opcode to restore the value. */
4417 add_unwind_opcode (op
, 1);
4419 /* Record the information for later. */
4420 unwind
.fp_reg
= reg
;
4421 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4422 unwind
.sp_restored
= 1;
4425 /* Parse an unwind_pad directive. */
4428 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 if (immediate_for_directive (&offset
) == FAIL
)
4440 as_bad (_("stack increment must be multiple of 4"));
4441 ignore_rest_of_line ();
4445 /* Don't generate any opcodes, just record the details for later. */
4446 unwind
.frame_size
+= offset
;
4447 unwind
.pending_offset
+= offset
;
4449 demand_empty_rest_of_line ();
4452 /* Parse an unwind_setfp directive. */
4455 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4461 if (!unwind
.proc_start
)
4462 as_bad (MISSING_FNSTART
);
4464 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4465 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4468 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4472 as_bad (_("expected <reg>, <reg>"));
4473 ignore_rest_of_line ();
4477 /* Optional constant. */
4478 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4480 if (immediate_for_directive (&offset
) == FAIL
)
4486 demand_empty_rest_of_line ();
4488 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4490 as_bad (_("register must be either sp or set by a previous"
4491 "unwind_movsp directive"));
4495 /* Don't generate any opcodes, just record the information for later. */
4496 unwind
.fp_reg
= fp_reg
;
4498 if (sp_reg
== REG_SP
)
4499 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4501 unwind
.fp_offset
-= offset
;
4504 /* Parse an unwind_raw directive. */
4507 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4510 /* This is an arbitrary limit. */
4511 unsigned char op
[16];
4514 if (!unwind
.proc_start
)
4515 as_bad (MISSING_FNSTART
);
4518 if (exp
.X_op
== O_constant
4519 && skip_past_comma (&input_line_pointer
) != FAIL
)
4521 unwind
.frame_size
+= exp
.X_add_number
;
4525 exp
.X_op
= O_illegal
;
4527 if (exp
.X_op
!= O_constant
)
4529 as_bad (_("expected <offset>, <opcode>"));
4530 ignore_rest_of_line ();
4536 /* Parse the opcode. */
4541 as_bad (_("unwind opcode too long"));
4542 ignore_rest_of_line ();
4544 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4546 as_bad (_("invalid unwind opcode"));
4547 ignore_rest_of_line ();
4550 op
[count
++] = exp
.X_add_number
;
4552 /* Parse the next byte. */
4553 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 /* Add the opcode bytes in reverse order. */
4561 add_unwind_opcode (op
[count
], 1);
4563 demand_empty_rest_of_line ();
4567 /* Parse a .eabi_attribute directive. */
4570 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4572 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4574 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4575 attributes_set_explicitly
[tag
] = 1;
4578 /* Emit a tls fix for the symbol. */
4581 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4585 #ifdef md_flush_pending_output
4586 md_flush_pending_output ();
4589 #ifdef md_cons_align
4593 /* Since we're just labelling the code, there's no need to define a
4596 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4597 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4598 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4599 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4601 #endif /* OBJ_ELF */
4603 static void s_arm_arch (int);
4604 static void s_arm_object_arch (int);
4605 static void s_arm_cpu (int);
4606 static void s_arm_fpu (int);
4607 static void s_arm_arch_extension (int);
4612 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4619 if (exp
.X_op
== O_symbol
)
4620 exp
.X_op
= O_secrel
;
4622 emit_expr (&exp
, 4);
4624 while (*input_line_pointer
++ == ',');
4626 input_line_pointer
--;
4627 demand_empty_rest_of_line ();
4631 /* This table describes all the machine specific pseudo-ops the assembler
4632 has to support. The fields are:
4633 pseudo-op name without dot
4634 function to call to execute this pseudo-op
4635 Integer arg to pass to the function. */
4637 const pseudo_typeS md_pseudo_table
[] =
4639 /* Never called because '.req' does not start a line. */
4640 { "req", s_req
, 0 },
4641 /* Following two are likewise never called. */
4644 { "unreq", s_unreq
, 0 },
4645 { "bss", s_bss
, 0 },
4646 { "align", s_align_ptwo
, 2 },
4647 { "arm", s_arm
, 0 },
4648 { "thumb", s_thumb
, 0 },
4649 { "code", s_code
, 0 },
4650 { "force_thumb", s_force_thumb
, 0 },
4651 { "thumb_func", s_thumb_func
, 0 },
4652 { "thumb_set", s_thumb_set
, 0 },
4653 { "even", s_even
, 0 },
4654 { "ltorg", s_ltorg
, 0 },
4655 { "pool", s_ltorg
, 0 },
4656 { "syntax", s_syntax
, 0 },
4657 { "cpu", s_arm_cpu
, 0 },
4658 { "arch", s_arm_arch
, 0 },
4659 { "object_arch", s_arm_object_arch
, 0 },
4660 { "fpu", s_arm_fpu
, 0 },
4661 { "arch_extension", s_arm_arch_extension
, 0 },
4663 { "word", s_arm_elf_cons
, 4 },
4664 { "long", s_arm_elf_cons
, 4 },
4665 { "inst.n", s_arm_elf_inst
, 2 },
4666 { "inst.w", s_arm_elf_inst
, 4 },
4667 { "inst", s_arm_elf_inst
, 0 },
4668 { "rel31", s_arm_rel31
, 0 },
4669 { "fnstart", s_arm_unwind_fnstart
, 0 },
4670 { "fnend", s_arm_unwind_fnend
, 0 },
4671 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4672 { "personality", s_arm_unwind_personality
, 0 },
4673 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4674 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4675 { "save", s_arm_unwind_save
, 0 },
4676 { "vsave", s_arm_unwind_save
, 1 },
4677 { "movsp", s_arm_unwind_movsp
, 0 },
4678 { "pad", s_arm_unwind_pad
, 0 },
4679 { "setfp", s_arm_unwind_setfp
, 0 },
4680 { "unwind_raw", s_arm_unwind_raw
, 0 },
4681 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4682 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4686 /* These are used for dwarf. */
4690 /* These are used for dwarf2. */
4691 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4692 { "loc", dwarf2_directive_loc
, 0 },
4693 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4695 { "extend", float_cons
, 'x' },
4696 { "ldouble", float_cons
, 'x' },
4697 { "packed", float_cons
, 'p' },
4699 {"secrel32", pe_directive_secrel
, 0},
4702 /* These are for compatibility with CodeComposer Studio. */
4703 {"ref", s_ccs_ref
, 0},
4704 {"def", s_ccs_def
, 0},
4705 {"asmfunc", s_ccs_asmfunc
, 0},
4706 {"endasmfunc", s_ccs_endasmfunc
, 0},
4711 /* Parser functions used exclusively in instruction operands. */
4713 /* Generic immediate-value read function for use in insn parsing.
4714 STR points to the beginning of the immediate (the leading #);
4715 VAL receives the value; if the value is outside [MIN, MAX]
4716 issue an error. PREFIX_OPT is true if the immediate prefix is
4720 parse_immediate (char **str
, int *val
, int min
, int max
,
4721 bfd_boolean prefix_opt
)
4724 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4725 if (exp
.X_op
!= O_constant
)
4727 inst
.error
= _("constant expression required");
4731 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4733 inst
.error
= _("immediate value out of range");
4737 *val
= exp
.X_add_number
;
4741 /* Less-generic immediate-value read function with the possibility of loading a
4742 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4743 instructions. Puts the result directly in inst.operands[i]. */
4746 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4747 bfd_boolean allow_symbol_p
)
4750 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4753 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4755 if (exp_p
->X_op
== O_constant
)
4757 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4758 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4759 O_constant. We have to be careful not to break compilation for
4760 32-bit X_add_number, though. */
4761 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4763 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4764 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4766 inst
.operands
[i
].regisimm
= 1;
4769 else if (exp_p
->X_op
== O_big
4770 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4772 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4774 /* Bignums have their least significant bits in
4775 generic_bignum[0]. Make sure we put 32 bits in imm and
4776 32 bits in reg, in a (hopefully) portable way. */
4777 gas_assert (parts
!= 0);
4779 /* Make sure that the number is not too big.
4780 PR 11972: Bignums can now be sign-extended to the
4781 size of a .octa so check that the out of range bits
4782 are all zero or all one. */
4783 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4785 LITTLENUM_TYPE m
= -1;
4787 if (generic_bignum
[parts
* 2] != 0
4788 && generic_bignum
[parts
* 2] != m
)
4791 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4792 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4796 inst
.operands
[i
].imm
= 0;
4797 for (j
= 0; j
< parts
; j
++, idx
++)
4798 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4799 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4800 inst
.operands
[i
].reg
= 0;
4801 for (j
= 0; j
< parts
; j
++, idx
++)
4802 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4803 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4804 inst
.operands
[i
].regisimm
= 1;
4806 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4814 /* Returns the pseudo-register number of an FPA immediate constant,
4815 or FAIL if there isn't a valid constant here. */
4818 parse_fpa_immediate (char ** str
)
4820 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4826 /* First try and match exact strings, this is to guarantee
4827 that some formats will work even for cross assembly. */
4829 for (i
= 0; fp_const
[i
]; i
++)
4831 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4835 *str
+= strlen (fp_const
[i
]);
4836 if (is_end_of_line
[(unsigned char) **str
])
4842 /* Just because we didn't get a match doesn't mean that the constant
4843 isn't valid, just that it is in a format that we don't
4844 automatically recognize. Try parsing it with the standard
4845 expression routines. */
4847 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4849 /* Look for a raw floating point number. */
4850 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4851 && is_end_of_line
[(unsigned char) *save_in
])
4853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4855 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4857 if (words
[j
] != fp_values
[i
][j
])
4861 if (j
== MAX_LITTLENUMS
)
4869 /* Try and parse a more complex expression, this will probably fail
4870 unless the code uses a floating point prefix (eg "0f"). */
4871 save_in
= input_line_pointer
;
4872 input_line_pointer
= *str
;
4873 if (expression (&exp
) == absolute_section
4874 && exp
.X_op
== O_big
4875 && exp
.X_add_number
< 0)
4877 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4879 #define X_PRECISION 5
4880 #define E_PRECISION 15L
4881 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4893 *str
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4901 *str
= input_line_pointer
;
4902 input_line_pointer
= save_in
;
4903 inst
.error
= _("invalid FPA immediate expression");
4907 /* Returns 1 if a number has "quarter-precision" float format
4908 0baBbbbbbc defgh000 00000000 00000000. */
4911 is_quarter_float (unsigned imm
)
4913 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4914 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4918 /* Detect the presence of a floating point or integer zero constant,
4922 parse_ifimm_zero (char **in
)
4926 if (!is_immediate_prefix (**in
))
4931 /* Accept #0x0 as a synonym for #0. */
4932 if (strncmp (*in
, "0x", 2) == 0)
4935 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4940 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4941 &generic_floating_point_number
);
4944 && generic_floating_point_number
.sign
== '+'
4945 && (generic_floating_point_number
.low
4946 > generic_floating_point_number
.leader
))
4952 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4953 0baBbbbbbc defgh000 00000000 00000000.
4954 The zero and minus-zero cases need special handling, since they can't be
4955 encoded in the "quarter-precision" float format, but can nonetheless be
4956 loaded as integer constants. */
4959 parse_qfloat_immediate (char **ccp
, int *immed
)
4963 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4964 int found_fpchar
= 0;
4966 skip_past_char (&str
, '#');
4968 /* We must not accidentally parse an integer as a floating-point number. Make
4969 sure that the value we parse is not an integer by checking for special
4970 characters '.' or 'e'.
4971 FIXME: This is a horrible hack, but doing better is tricky because type
4972 information isn't in a very usable state at parse time. */
4974 skip_whitespace (fpnum
);
4976 if (strncmp (fpnum
, "0x", 2) == 0)
4980 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4981 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4991 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4993 unsigned fpword
= 0;
4996 /* Our FP word must be 32 bits (single-precision FP). */
4997 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4999 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5003 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5016 /* Shift operands. */
5019 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5022 struct asm_shift_name
5025 enum shift_kind kind
;
5028 /* Third argument to parse_shift. */
5029 enum parse_shift_mode
5031 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5032 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5033 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5034 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5035 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5038 /* Parse a <shift> specifier on an ARM data processing instruction.
5039 This has three forms:
5041 (LSL|LSR|ASL|ASR|ROR) Rs
5042 (LSL|LSR|ASL|ASR|ROR) #imm
5045 Note that ASL is assimilated to LSL in the instruction encoding, and
5046 RRX to ROR #0 (which cannot be written as such). */
5049 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5051 const struct asm_shift_name
*shift_name
;
5052 enum shift_kind shift
;
5057 for (p
= *str
; ISALPHA (*p
); p
++)
5062 inst
.error
= _("shift expression expected");
5066 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5069 if (shift_name
== NULL
)
5071 inst
.error
= _("shift expression expected");
5075 shift
= shift_name
->kind
;
5079 case NO_SHIFT_RESTRICT
:
5080 case SHIFT_IMMEDIATE
: break;
5082 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5083 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5085 inst
.error
= _("'LSL' or 'ASR' required");
5090 case SHIFT_LSL_IMMEDIATE
:
5091 if (shift
!= SHIFT_LSL
)
5093 inst
.error
= _("'LSL' required");
5098 case SHIFT_ASR_IMMEDIATE
:
5099 if (shift
!= SHIFT_ASR
)
5101 inst
.error
= _("'ASR' required");
5109 if (shift
!= SHIFT_RRX
)
5111 /* Whitespace can appear here if the next thing is a bare digit. */
5112 skip_whitespace (p
);
5114 if (mode
== NO_SHIFT_RESTRICT
5115 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5117 inst
.operands
[i
].imm
= reg
;
5118 inst
.operands
[i
].immisreg
= 1;
5120 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5123 inst
.operands
[i
].shift_kind
= shift
;
5124 inst
.operands
[i
].shifted
= 1;
5129 /* Parse a <shifter_operand> for an ARM data processing instruction:
5132 #<immediate>, <rotate>
5136 where <shift> is defined by parse_shift above, and <rotate> is a
5137 multiple of 2 between 0 and 30. Validation of immediate operands
5138 is deferred to md_apply_fix. */
5141 parse_shifter_operand (char **str
, int i
)
5146 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5148 inst
.operands
[i
].reg
= value
;
5149 inst
.operands
[i
].isreg
= 1;
5151 /* parse_shift will override this if appropriate */
5152 inst
.reloc
.exp
.X_op
= O_constant
;
5153 inst
.reloc
.exp
.X_add_number
= 0;
5155 if (skip_past_comma (str
) == FAIL
)
5158 /* Shift operation on register. */
5159 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5162 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5165 if (skip_past_comma (str
) == SUCCESS
)
5167 /* #x, y -- ie explicit rotation by Y. */
5168 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5171 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression expected");
5177 value
= exp
.X_add_number
;
5178 if (value
< 0 || value
> 30 || value
% 2 != 0)
5180 inst
.error
= _("invalid rotation");
5183 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5185 inst
.error
= _("invalid constant");
5189 /* Encode as specified. */
5190 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5194 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5195 inst
.reloc
.pc_rel
= 0;
5199 /* Group relocation information. Each entry in the table contains the
5200 textual name of the relocation as may appear in assembler source
5201 and must end with a colon.
5202 Along with this textual name are the relocation codes to be used if
5203 the corresponding instruction is an ALU instruction (ADD or SUB only),
5204 an LDR, an LDRS, or an LDC. */
5206 struct group_reloc_table_entry
5217 /* Varieties of non-ALU group relocation. */
5224 static struct group_reloc_table_entry group_reloc_table
[] =
5225 { /* Program counter relative: */
5227 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5232 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5233 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5234 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5235 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5237 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5242 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5243 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5244 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5245 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5247 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5248 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5249 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5250 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5251 /* Section base relative */
5253 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5258 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5259 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5260 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5261 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5263 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5268 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5269 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5270 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5271 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5273 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5274 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5277 /* Absolute thumb alu relocations. */
5279 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5284 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5289 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5294 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5299 /* Given the address of a pointer pointing to the textual name of a group
5300 relocation as may appear in assembler source, attempt to find its details
5301 in group_reloc_table. The pointer will be updated to the character after
5302 the trailing colon. On failure, FAIL will be returned; SUCCESS
5303 otherwise. On success, *entry will be updated to point at the relevant
5304 group_reloc_table entry. */
5307 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5310 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5312 int length
= strlen (group_reloc_table
[i
].name
);
5314 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5315 && (*str
)[length
] == ':')
5317 *out
= &group_reloc_table
[i
];
5318 *str
+= (length
+ 1);
5326 /* Parse a <shifter_operand> for an ARM data processing instruction
5327 (as for parse_shifter_operand) where group relocations are allowed:
5330 #<immediate>, <rotate>
5331 #:<group_reloc>:<expression>
5335 where <group_reloc> is one of the strings defined in group_reloc_table.
5336 The hashes are optional.
5338 Everything else is as for parse_shifter_operand. */
5340 static parse_operand_result
5341 parse_shifter_operand_group_reloc (char **str
, int i
)
5343 /* Determine if we have the sequence of characters #: or just :
5344 coming next. If we do, then we check for a group relocation.
5345 If we don't, punt the whole lot to parse_shifter_operand. */
5347 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5348 || (*str
)[0] == ':')
5350 struct group_reloc_table_entry
*entry
;
5352 if ((*str
)[0] == '#')
5357 /* Try to parse a group relocation. Anything else is an error. */
5358 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5360 inst
.error
= _("unknown group relocation");
5361 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5364 /* We now have the group relocation table entry corresponding to
5365 the name in the assembler source. Next, we parse the expression. */
5366 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5367 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5369 /* Record the relocation type (always the ALU variant here). */
5370 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5371 gas_assert (inst
.reloc
.type
!= 0);
5373 return PARSE_OPERAND_SUCCESS
;
5376 return parse_shifter_operand (str
, i
) == SUCCESS
5377 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5379 /* Never reached. */
5382 /* Parse a Neon alignment expression. Information is written to
5383 inst.operands[i]. We assume the initial ':' has been skipped.
5385 align .imm = align << 8, .immisalign=1, .preind=0 */
5386 static parse_operand_result
5387 parse_neon_alignment (char **str
, int i
)
5392 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5394 if (exp
.X_op
!= O_constant
)
5396 inst
.error
= _("alignment must be constant");
5397 return PARSE_OPERAND_FAIL
;
5400 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5401 inst
.operands
[i
].immisalign
= 1;
5402 /* Alignments are not pre-indexes. */
5403 inst
.operands
[i
].preind
= 0;
5406 return PARSE_OPERAND_SUCCESS
;
5409 /* Parse all forms of an ARM address expression. Information is written
5410 to inst.operands[i] and/or inst.reloc.
5412 Preindexed addressing (.preind=1):
5414 [Rn, #offset] .reg=Rn .reloc.exp=offset
5415 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5416 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5417 .shift_kind=shift .reloc.exp=shift_imm
5419 These three may have a trailing ! which causes .writeback to be set also.
5421 Postindexed addressing (.postind=1, .writeback=1):
5423 [Rn], #offset .reg=Rn .reloc.exp=offset
5424 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5425 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5426 .shift_kind=shift .reloc.exp=shift_imm
5428 Unindexed addressing (.preind=0, .postind=0):
5430 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5434 [Rn]{!} shorthand for [Rn,#0]{!}
5435 =immediate .isreg=0 .reloc.exp=immediate
5436 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5438 It is the caller's responsibility to check for addressing modes not
5439 supported by the instruction, and to set inst.reloc.type. */
5441 static parse_operand_result
5442 parse_address_main (char **str
, int i
, int group_relocations
,
5443 group_reloc_type group_type
)
5448 if (skip_past_char (&p
, '[') == FAIL
)
5450 if (skip_past_char (&p
, '=') == FAIL
)
5452 /* Bare address - translate to PC-relative offset. */
5453 inst
.reloc
.pc_rel
= 1;
5454 inst
.operands
[i
].reg
= REG_PC
;
5455 inst
.operands
[i
].isreg
= 1;
5456 inst
.operands
[i
].preind
= 1;
5458 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5459 return PARSE_OPERAND_FAIL
;
5461 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5462 /*allow_symbol_p=*/TRUE
))
5463 return PARSE_OPERAND_FAIL
;
5466 return PARSE_OPERAND_SUCCESS
;
5469 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5470 skip_whitespace (p
);
5472 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5474 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5475 return PARSE_OPERAND_FAIL
;
5477 inst
.operands
[i
].reg
= reg
;
5478 inst
.operands
[i
].isreg
= 1;
5480 if (skip_past_comma (&p
) == SUCCESS
)
5482 inst
.operands
[i
].preind
= 1;
5485 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5487 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5489 inst
.operands
[i
].imm
= reg
;
5490 inst
.operands
[i
].immisreg
= 1;
5492 if (skip_past_comma (&p
) == SUCCESS
)
5493 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5494 return PARSE_OPERAND_FAIL
;
5496 else if (skip_past_char (&p
, ':') == SUCCESS
)
5498 /* FIXME: '@' should be used here, but it's filtered out by generic
5499 code before we get to see it here. This may be subject to
5501 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5503 if (result
!= PARSE_OPERAND_SUCCESS
)
5508 if (inst
.operands
[i
].negative
)
5510 inst
.operands
[i
].negative
= 0;
5514 if (group_relocations
5515 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5517 struct group_reloc_table_entry
*entry
;
5519 /* Skip over the #: or : sequence. */
5525 /* Try to parse a group relocation. Anything else is an
5527 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5529 inst
.error
= _("unknown group relocation");
5530 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5533 /* We now have the group relocation table entry corresponding to
5534 the name in the assembler source. Next, we parse the
5536 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5537 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5539 /* Record the relocation type. */
5543 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5547 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5551 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5558 if (inst
.reloc
.type
== 0)
5560 inst
.error
= _("this group relocation is not allowed on this instruction");
5561 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5567 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5568 return PARSE_OPERAND_FAIL
;
5569 /* If the offset is 0, find out if it's a +0 or -0. */
5570 if (inst
.reloc
.exp
.X_op
== O_constant
5571 && inst
.reloc
.exp
.X_add_number
== 0)
5573 skip_whitespace (q
);
5577 skip_whitespace (q
);
5580 inst
.operands
[i
].negative
= 1;
5585 else if (skip_past_char (&p
, ':') == SUCCESS
)
5587 /* FIXME: '@' should be used here, but it's filtered out by generic code
5588 before we get to see it here. This may be subject to change. */
5589 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5591 if (result
!= PARSE_OPERAND_SUCCESS
)
5595 if (skip_past_char (&p
, ']') == FAIL
)
5597 inst
.error
= _("']' expected");
5598 return PARSE_OPERAND_FAIL
;
5601 if (skip_past_char (&p
, '!') == SUCCESS
)
5602 inst
.operands
[i
].writeback
= 1;
5604 else if (skip_past_comma (&p
) == SUCCESS
)
5606 if (skip_past_char (&p
, '{') == SUCCESS
)
5608 /* [Rn], {expr} - unindexed, with option */
5609 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5610 0, 255, TRUE
) == FAIL
)
5611 return PARSE_OPERAND_FAIL
;
5613 if (skip_past_char (&p
, '}') == FAIL
)
5615 inst
.error
= _("'}' expected at end of 'option' field");
5616 return PARSE_OPERAND_FAIL
;
5618 if (inst
.operands
[i
].preind
)
5620 inst
.error
= _("cannot combine index with option");
5621 return PARSE_OPERAND_FAIL
;
5624 return PARSE_OPERAND_SUCCESS
;
5628 inst
.operands
[i
].postind
= 1;
5629 inst
.operands
[i
].writeback
= 1;
5631 if (inst
.operands
[i
].preind
)
5633 inst
.error
= _("cannot combine pre- and post-indexing");
5634 return PARSE_OPERAND_FAIL
;
5638 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5640 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5642 /* We might be using the immediate for alignment already. If we
5643 are, OR the register number into the low-order bits. */
5644 if (inst
.operands
[i
].immisalign
)
5645 inst
.operands
[i
].imm
|= reg
;
5647 inst
.operands
[i
].imm
= reg
;
5648 inst
.operands
[i
].immisreg
= 1;
5650 if (skip_past_comma (&p
) == SUCCESS
)
5651 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5652 return PARSE_OPERAND_FAIL
;
5657 if (inst
.operands
[i
].negative
)
5659 inst
.operands
[i
].negative
= 0;
5662 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5663 return PARSE_OPERAND_FAIL
;
5664 /* If the offset is 0, find out if it's a +0 or -0. */
5665 if (inst
.reloc
.exp
.X_op
== O_constant
5666 && inst
.reloc
.exp
.X_add_number
== 0)
5668 skip_whitespace (q
);
5672 skip_whitespace (q
);
5675 inst
.operands
[i
].negative
= 1;
5681 /* If at this point neither .preind nor .postind is set, we have a
5682 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5683 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5685 inst
.operands
[i
].preind
= 1;
5686 inst
.reloc
.exp
.X_op
= O_constant
;
5687 inst
.reloc
.exp
.X_add_number
= 0;
5690 return PARSE_OPERAND_SUCCESS
;
5694 parse_address (char **str
, int i
)
5696 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5700 static parse_operand_result
5701 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5703 return parse_address_main (str
, i
, 1, type
);
5706 /* Parse an operand for a MOVW or MOVT instruction. */
5708 parse_half (char **str
)
5713 skip_past_char (&p
, '#');
5714 if (strncasecmp (p
, ":lower16:", 9) == 0)
5715 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5716 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5717 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5719 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5722 skip_whitespace (p
);
5725 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5728 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5730 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5732 inst
.error
= _("constant expression expected");
5735 if (inst
.reloc
.exp
.X_add_number
< 0
5736 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5738 inst
.error
= _("immediate value out of range");
5746 /* Miscellaneous. */
5748 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5749 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5751 parse_psr (char **str
, bfd_boolean lhs
)
5754 unsigned long psr_field
;
5755 const struct asm_psr
*psr
;
5757 bfd_boolean is_apsr
= FALSE
;
5758 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5760 /* PR gas/12698: If the user has specified -march=all then m_profile will
5761 be TRUE, but we want to ignore it in this case as we are building for any
5762 CPU type, including non-m variants. */
5763 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5766 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5767 feature for ease of use and backwards compatibility. */
5769 if (strncasecmp (p
, "SPSR", 4) == 0)
5772 goto unsupported_psr
;
5774 psr_field
= SPSR_BIT
;
5776 else if (strncasecmp (p
, "CPSR", 4) == 0)
5779 goto unsupported_psr
;
5783 else if (strncasecmp (p
, "APSR", 4) == 0)
5785 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5786 and ARMv7-R architecture CPUs. */
5795 while (ISALNUM (*p
) || *p
== '_');
5797 if (strncasecmp (start
, "iapsr", 5) == 0
5798 || strncasecmp (start
, "eapsr", 5) == 0
5799 || strncasecmp (start
, "xpsr", 4) == 0
5800 || strncasecmp (start
, "psr", 3) == 0)
5801 p
= start
+ strcspn (start
, "rR") + 1;
5803 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5809 /* If APSR is being written, a bitfield may be specified. Note that
5810 APSR itself is handled above. */
5811 if (psr
->field
<= 3)
5813 psr_field
= psr
->field
;
5819 /* M-profile MSR instructions have the mask field set to "10", except
5820 *PSR variants which modify APSR, which may use a different mask (and
5821 have been handled already). Do that by setting the PSR_f field
5823 return psr
->field
| (lhs
? PSR_f
: 0);
5826 goto unsupported_psr
;
5832 /* A suffix follows. */
5838 while (ISALNUM (*p
) || *p
== '_');
5842 /* APSR uses a notation for bits, rather than fields. */
5843 unsigned int nzcvq_bits
= 0;
5844 unsigned int g_bit
= 0;
5847 for (bit
= start
; bit
!= p
; bit
++)
5849 switch (TOLOWER (*bit
))
5852 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5856 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5860 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5864 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5868 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5872 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5876 inst
.error
= _("unexpected bit specified after APSR");
5881 if (nzcvq_bits
== 0x1f)
5886 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5888 inst
.error
= _("selected processor does not "
5889 "support DSP extension");
5896 if ((nzcvq_bits
& 0x20) != 0
5897 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5898 || (g_bit
& 0x2) != 0)
5900 inst
.error
= _("bad bitmask specified after APSR");
5906 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5911 psr_field
|= psr
->field
;
5917 goto error
; /* Garbage after "[CS]PSR". */
5919 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5920 is deprecated, but allow it anyway. */
5924 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5927 else if (!m_profile
)
5928 /* These bits are never right for M-profile devices: don't set them
5929 (only code paths which read/write APSR reach here). */
5930 psr_field
|= (PSR_c
| PSR_f
);
5936 inst
.error
= _("selected processor does not support requested special "
5937 "purpose register");
5941 inst
.error
= _("flag for {c}psr instruction expected");
5945 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5946 value suitable for splatting into the AIF field of the instruction. */
5949 parse_cps_flags (char **str
)
5958 case '\0': case ',':
5961 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5962 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5963 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5966 inst
.error
= _("unrecognized CPS flag");
5971 if (saw_a_flag
== 0)
5973 inst
.error
= _("missing CPS flags");
5981 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5982 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5985 parse_endian_specifier (char **str
)
5990 if (strncasecmp (s
, "BE", 2))
5992 else if (strncasecmp (s
, "LE", 2))
5996 inst
.error
= _("valid endian specifiers are be or le");
6000 if (ISALNUM (s
[2]) || s
[2] == '_')
6002 inst
.error
= _("valid endian specifiers are be or le");
6007 return little_endian
;
6010 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6011 value suitable for poking into the rotate field of an sxt or sxta
6012 instruction, or FAIL on error. */
6015 parse_ror (char **str
)
6020 if (strncasecmp (s
, "ROR", 3) == 0)
6024 inst
.error
= _("missing rotation field after comma");
6028 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6033 case 0: *str
= s
; return 0x0;
6034 case 8: *str
= s
; return 0x1;
6035 case 16: *str
= s
; return 0x2;
6036 case 24: *str
= s
; return 0x3;
6039 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6044 /* Parse a conditional code (from conds[] below). The value returned is in the
6045 range 0 .. 14, or FAIL. */
6047 parse_cond (char **str
)
6050 const struct asm_cond
*c
;
6052 /* Condition codes are always 2 characters, so matching up to
6053 3 characters is sufficient. */
6058 while (ISALPHA (*q
) && n
< 3)
6060 cond
[n
] = TOLOWER (*q
);
6065 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6068 inst
.error
= _("condition required");
6076 /* If the given feature available in the selected CPU, mark it as used.
6077 Returns TRUE iff feature is available. */
6079 mark_feature_used (const arm_feature_set
*feature
)
6081 /* Ensure the option is valid on the current architecture. */
6082 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6085 /* Add the appropriate architecture feature for the barrier option used.
6088 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6090 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6095 /* Parse an option for a barrier instruction. Returns the encoding for the
6098 parse_barrier (char **str
)
6101 const struct asm_barrier_opt
*o
;
6104 while (ISALPHA (*q
))
6107 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6112 if (!mark_feature_used (&o
->arch
))
6119 /* Parse the operands of a table branch instruction. Similar to a memory
6122 parse_tb (char **str
)
6127 if (skip_past_char (&p
, '[') == FAIL
)
6129 inst
.error
= _("'[' expected");
6133 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6135 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6138 inst
.operands
[0].reg
= reg
;
6140 if (skip_past_comma (&p
) == FAIL
)
6142 inst
.error
= _("',' expected");
6146 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6148 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6151 inst
.operands
[0].imm
= reg
;
6153 if (skip_past_comma (&p
) == SUCCESS
)
6155 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6157 if (inst
.reloc
.exp
.X_add_number
!= 1)
6159 inst
.error
= _("invalid shift");
6162 inst
.operands
[0].shifted
= 1;
6165 if (skip_past_char (&p
, ']') == FAIL
)
6167 inst
.error
= _("']' expected");
6174 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6175 information on the types the operands can take and how they are encoded.
6176 Up to four operands may be read; this function handles setting the
6177 ".present" field for each read operand itself.
6178 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6179 else returns FAIL. */
6182 parse_neon_mov (char **str
, int *which_operand
)
6184 int i
= *which_operand
, val
;
6185 enum arm_reg_type rtype
;
6187 struct neon_type_el optype
;
6189 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6191 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6192 inst
.operands
[i
].reg
= val
;
6193 inst
.operands
[i
].isscalar
= 1;
6194 inst
.operands
[i
].vectype
= optype
;
6195 inst
.operands
[i
++].present
= 1;
6197 if (skip_past_comma (&ptr
) == FAIL
)
6200 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6203 inst
.operands
[i
].reg
= val
;
6204 inst
.operands
[i
].isreg
= 1;
6205 inst
.operands
[i
].present
= 1;
6207 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6210 /* Cases 0, 1, 2, 3, 5 (D only). */
6211 if (skip_past_comma (&ptr
) == FAIL
)
6214 inst
.operands
[i
].reg
= val
;
6215 inst
.operands
[i
].isreg
= 1;
6216 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6217 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6218 inst
.operands
[i
].isvec
= 1;
6219 inst
.operands
[i
].vectype
= optype
;
6220 inst
.operands
[i
++].present
= 1;
6222 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6224 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6225 Case 13: VMOV <Sd>, <Rm> */
6226 inst
.operands
[i
].reg
= val
;
6227 inst
.operands
[i
].isreg
= 1;
6228 inst
.operands
[i
].present
= 1;
6230 if (rtype
== REG_TYPE_NQ
)
6232 first_error (_("can't use Neon quad register here"));
6235 else if (rtype
!= REG_TYPE_VFS
)
6238 if (skip_past_comma (&ptr
) == FAIL
)
6240 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6242 inst
.operands
[i
].reg
= val
;
6243 inst
.operands
[i
].isreg
= 1;
6244 inst
.operands
[i
].present
= 1;
6247 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6250 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6251 Case 1: VMOV<c><q> <Dd>, <Dm>
6252 Case 8: VMOV.F32 <Sd>, <Sm>
6253 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6255 inst
.operands
[i
].reg
= val
;
6256 inst
.operands
[i
].isreg
= 1;
6257 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6258 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6259 inst
.operands
[i
].isvec
= 1;
6260 inst
.operands
[i
].vectype
= optype
;
6261 inst
.operands
[i
].present
= 1;
6263 if (skip_past_comma (&ptr
) == SUCCESS
)
6268 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isreg
= 1;
6273 inst
.operands
[i
++].present
= 1;
6275 if (skip_past_comma (&ptr
) == FAIL
)
6278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6281 inst
.operands
[i
].reg
= val
;
6282 inst
.operands
[i
].isreg
= 1;
6283 inst
.operands
[i
].present
= 1;
6286 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6287 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6288 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6289 Case 10: VMOV.F32 <Sd>, #<imm>
6290 Case 11: VMOV.F64 <Dd>, #<imm> */
6291 inst
.operands
[i
].immisfloat
= 1;
6292 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6294 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6295 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6299 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6303 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6306 inst
.operands
[i
].reg
= val
;
6307 inst
.operands
[i
].isreg
= 1;
6308 inst
.operands
[i
++].present
= 1;
6310 if (skip_past_comma (&ptr
) == FAIL
)
6313 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6315 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6316 inst
.operands
[i
].reg
= val
;
6317 inst
.operands
[i
].isscalar
= 1;
6318 inst
.operands
[i
].present
= 1;
6319 inst
.operands
[i
].vectype
= optype
;
6321 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6323 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6324 inst
.operands
[i
].reg
= val
;
6325 inst
.operands
[i
].isreg
= 1;
6326 inst
.operands
[i
++].present
= 1;
6328 if (skip_past_comma (&ptr
) == FAIL
)
6331 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6334 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6338 inst
.operands
[i
].reg
= val
;
6339 inst
.operands
[i
].isreg
= 1;
6340 inst
.operands
[i
].isvec
= 1;
6341 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6342 inst
.operands
[i
].vectype
= optype
;
6343 inst
.operands
[i
].present
= 1;
6345 if (rtype
== REG_TYPE_VFS
)
6349 if (skip_past_comma (&ptr
) == FAIL
)
6351 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6354 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6357 inst
.operands
[i
].reg
= val
;
6358 inst
.operands
[i
].isreg
= 1;
6359 inst
.operands
[i
].isvec
= 1;
6360 inst
.operands
[i
].issingle
= 1;
6361 inst
.operands
[i
].vectype
= optype
;
6362 inst
.operands
[i
].present
= 1;
6365 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6369 inst
.operands
[i
].reg
= val
;
6370 inst
.operands
[i
].isreg
= 1;
6371 inst
.operands
[i
].isvec
= 1;
6372 inst
.operands
[i
].issingle
= 1;
6373 inst
.operands
[i
].vectype
= optype
;
6374 inst
.operands
[i
].present
= 1;
6379 first_error (_("parse error"));
6383 /* Successfully parsed the operands. Update args. */
6389 first_error (_("expected comma"));
6393 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6397 /* Use this macro when the operand constraints are different
6398 for ARM and THUMB (e.g. ldrd). */
6399 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6400 ((arm_operand) | ((thumb_operand) << 16))
6402 /* Matcher codes for parse_operands. */
6403 enum operand_parse_code
6405 OP_stop
, /* end of line */
6407 OP_RR
, /* ARM register */
6408 OP_RRnpc
, /* ARM register, not r15 */
6409 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6410 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6411 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6412 optional trailing ! */
6413 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6414 OP_RCP
, /* Coprocessor number */
6415 OP_RCN
, /* Coprocessor register */
6416 OP_RF
, /* FPA register */
6417 OP_RVS
, /* VFP single precision register */
6418 OP_RVD
, /* VFP double precision register (0..15) */
6419 OP_RND
, /* Neon double precision register (0..31) */
6420 OP_RNQ
, /* Neon quad precision register */
6421 OP_RVSD
, /* VFP single or double precision register */
6422 OP_RNDQ
, /* Neon double or quad precision register */
6423 OP_RNSDQ
, /* Neon single, double or quad precision register */
6424 OP_RNSC
, /* Neon scalar D[X] */
6425 OP_RVC
, /* VFP control register */
6426 OP_RMF
, /* Maverick F register */
6427 OP_RMD
, /* Maverick D register */
6428 OP_RMFX
, /* Maverick FX register */
6429 OP_RMDX
, /* Maverick DX register */
6430 OP_RMAX
, /* Maverick AX register */
6431 OP_RMDS
, /* Maverick DSPSC register */
6432 OP_RIWR
, /* iWMMXt wR register */
6433 OP_RIWC
, /* iWMMXt wC register */
6434 OP_RIWG
, /* iWMMXt wCG register */
6435 OP_RXA
, /* XScale accumulator register */
6437 OP_REGLST
, /* ARM register list */
6438 OP_VRSLST
, /* VFP single-precision register list */
6439 OP_VRDLST
, /* VFP double-precision register list */
6440 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6441 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6442 OP_NSTRLST
, /* Neon element/structure list */
6444 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6445 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6446 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6447 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6448 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6449 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6450 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6451 OP_VMOV
, /* Neon VMOV operands. */
6452 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6453 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6454 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6456 OP_I0
, /* immediate zero */
6457 OP_I7
, /* immediate value 0 .. 7 */
6458 OP_I15
, /* 0 .. 15 */
6459 OP_I16
, /* 1 .. 16 */
6460 OP_I16z
, /* 0 .. 16 */
6461 OP_I31
, /* 0 .. 31 */
6462 OP_I31w
, /* 0 .. 31, optional trailing ! */
6463 OP_I32
, /* 1 .. 32 */
6464 OP_I32z
, /* 0 .. 32 */
6465 OP_I63
, /* 0 .. 63 */
6466 OP_I63s
, /* -64 .. 63 */
6467 OP_I64
, /* 1 .. 64 */
6468 OP_I64z
, /* 0 .. 64 */
6469 OP_I255
, /* 0 .. 255 */
6471 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6472 OP_I7b
, /* 0 .. 7 */
6473 OP_I15b
, /* 0 .. 15 */
6474 OP_I31b
, /* 0 .. 31 */
6476 OP_SH
, /* shifter operand */
6477 OP_SHG
, /* shifter operand with possible group relocation */
6478 OP_ADDR
, /* Memory address expression (any mode) */
6479 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6480 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6481 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6482 OP_EXP
, /* arbitrary expression */
6483 OP_EXPi
, /* same, with optional immediate prefix */
6484 OP_EXPr
, /* same, with optional relocation suffix */
6485 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6487 OP_CPSF
, /* CPS flags */
6488 OP_ENDI
, /* Endianness specifier */
6489 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6490 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6491 OP_COND
, /* conditional code */
6492 OP_TB
, /* Table branch. */
6494 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6496 OP_RRnpc_I0
, /* ARM register or literal 0 */
6497 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6498 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6499 OP_RF_IF
, /* FPA register or immediate */
6500 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6501 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6503 /* Optional operands. */
6504 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6505 OP_oI31b
, /* 0 .. 31 */
6506 OP_oI32b
, /* 1 .. 32 */
6507 OP_oI32z
, /* 0 .. 32 */
6508 OP_oIffffb
, /* 0 .. 65535 */
6509 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6511 OP_oRR
, /* ARM register */
6512 OP_oRRnpc
, /* ARM register, not the PC */
6513 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6514 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6515 OP_oRND
, /* Optional Neon double precision register */
6516 OP_oRNQ
, /* Optional Neon quad precision register */
6517 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6518 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6519 OP_oSHll
, /* LSL immediate */
6520 OP_oSHar
, /* ASR immediate */
6521 OP_oSHllar
, /* LSL or ASR immediate */
6522 OP_oROR
, /* ROR 0/8/16/24 */
6523 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6525 /* Some pre-defined mixed (ARM/THUMB) operands. */
6526 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6527 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6528 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6530 OP_FIRST_OPTIONAL
= OP_oI7b
6533 /* Generic instruction operand parser. This does no encoding and no
6534 semantic validation; it merely squirrels values away in the inst
6535 structure. Returns SUCCESS or FAIL depending on whether the
6536 specified grammar matched. */
6538 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6540 unsigned const int *upat
= pattern
;
6541 char *backtrack_pos
= 0;
6542 const char *backtrack_error
= 0;
6543 int i
, val
= 0, backtrack_index
= 0;
6544 enum arm_reg_type rtype
;
6545 parse_operand_result result
;
6546 unsigned int op_parse_code
;
6548 #define po_char_or_fail(chr) \
6551 if (skip_past_char (&str, chr) == FAIL) \
6556 #define po_reg_or_fail(regtype) \
6559 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6560 & inst.operands[i].vectype); \
6563 first_error (_(reg_expected_msgs[regtype])); \
6566 inst.operands[i].reg = val; \
6567 inst.operands[i].isreg = 1; \
6568 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6569 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6570 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6571 || rtype == REG_TYPE_VFD \
6572 || rtype == REG_TYPE_NQ); \
6576 #define po_reg_or_goto(regtype, label) \
6579 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6580 & inst.operands[i].vectype); \
6584 inst.operands[i].reg = val; \
6585 inst.operands[i].isreg = 1; \
6586 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6587 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6588 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6589 || rtype == REG_TYPE_VFD \
6590 || rtype == REG_TYPE_NQ); \
6594 #define po_imm_or_fail(min, max, popt) \
6597 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6599 inst.operands[i].imm = val; \
6603 #define po_scalar_or_goto(elsz, label) \
6606 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6609 inst.operands[i].reg = val; \
6610 inst.operands[i].isscalar = 1; \
6614 #define po_misc_or_fail(expr) \
6622 #define po_misc_or_fail_no_backtrack(expr) \
6626 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6627 backtrack_pos = 0; \
6628 if (result != PARSE_OPERAND_SUCCESS) \
6633 #define po_barrier_or_imm(str) \
6636 val = parse_barrier (&str); \
6637 if (val == FAIL && ! ISALPHA (*str)) \
6640 /* ISB can only take SY as an option. */ \
6641 || ((inst.instruction & 0xf0) == 0x60 \
6644 inst.error = _("invalid barrier type"); \
6645 backtrack_pos = 0; \
6651 skip_whitespace (str
);
6653 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6655 op_parse_code
= upat
[i
];
6656 if (op_parse_code
>= 1<<16)
6657 op_parse_code
= thumb
? (op_parse_code
>> 16)
6658 : (op_parse_code
& ((1<<16)-1));
6660 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6662 /* Remember where we are in case we need to backtrack. */
6663 gas_assert (!backtrack_pos
);
6664 backtrack_pos
= str
;
6665 backtrack_error
= inst
.error
;
6666 backtrack_index
= i
;
6669 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6670 po_char_or_fail (',');
6672 switch (op_parse_code
)
6680 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6681 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6682 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6683 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6684 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6685 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6687 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6689 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6691 /* Also accept generic coprocessor regs for unknown registers. */
6693 po_reg_or_fail (REG_TYPE_CN
);
6695 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6696 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6697 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6698 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6699 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6700 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6701 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6702 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6703 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6704 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6706 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6708 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6709 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6711 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6713 /* Neon scalar. Using an element size of 8 means that some invalid
6714 scalars are accepted here, so deal with those in later code. */
6715 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6719 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6722 po_imm_or_fail (0, 0, TRUE
);
6727 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6732 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6735 if (parse_ifimm_zero (&str
))
6736 inst
.operands
[i
].imm
= 0;
6740 = _("only floating point zero is allowed as immediate value");
6748 po_scalar_or_goto (8, try_rr
);
6751 po_reg_or_fail (REG_TYPE_RN
);
6757 po_scalar_or_goto (8, try_nsdq
);
6760 po_reg_or_fail (REG_TYPE_NSDQ
);
6766 po_scalar_or_goto (8, try_ndq
);
6769 po_reg_or_fail (REG_TYPE_NDQ
);
6775 po_scalar_or_goto (8, try_vfd
);
6778 po_reg_or_fail (REG_TYPE_VFD
);
6783 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6784 not careful then bad things might happen. */
6785 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6790 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6793 /* There's a possibility of getting a 64-bit immediate here, so
6794 we need special handling. */
6795 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6798 inst
.error
= _("immediate value is out of range");
6806 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6809 po_imm_or_fail (0, 63, TRUE
);
6814 po_char_or_fail ('[');
6815 po_reg_or_fail (REG_TYPE_RN
);
6816 po_char_or_fail (']');
6822 po_reg_or_fail (REG_TYPE_RN
);
6823 if (skip_past_char (&str
, '!') == SUCCESS
)
6824 inst
.operands
[i
].writeback
= 1;
6828 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6829 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6830 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6831 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6832 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6833 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6834 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6835 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6836 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6837 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6838 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6839 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6841 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6843 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6844 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6846 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6847 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6848 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6849 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6851 /* Immediate variants */
6853 po_char_or_fail ('{');
6854 po_imm_or_fail (0, 255, TRUE
);
6855 po_char_or_fail ('}');
6859 /* The expression parser chokes on a trailing !, so we have
6860 to find it first and zap it. */
6863 while (*s
&& *s
!= ',')
6868 inst
.operands
[i
].writeback
= 1;
6870 po_imm_or_fail (0, 31, TRUE
);
6878 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6883 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6888 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6890 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6892 val
= parse_reloc (&str
);
6895 inst
.error
= _("unrecognized relocation suffix");
6898 else if (val
!= BFD_RELOC_UNUSED
)
6900 inst
.operands
[i
].imm
= val
;
6901 inst
.operands
[i
].hasreloc
= 1;
6906 /* Operand for MOVW or MOVT. */
6908 po_misc_or_fail (parse_half (&str
));
6911 /* Register or expression. */
6912 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6913 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6915 /* Register or immediate. */
6916 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6917 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6919 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6921 if (!is_immediate_prefix (*str
))
6924 val
= parse_fpa_immediate (&str
);
6927 /* FPA immediates are encoded as registers 8-15.
6928 parse_fpa_immediate has already applied the offset. */
6929 inst
.operands
[i
].reg
= val
;
6930 inst
.operands
[i
].isreg
= 1;
6933 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6934 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6936 /* Two kinds of register. */
6939 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6941 || (rege
->type
!= REG_TYPE_MMXWR
6942 && rege
->type
!= REG_TYPE_MMXWC
6943 && rege
->type
!= REG_TYPE_MMXWCG
))
6945 inst
.error
= _("iWMMXt data or control register expected");
6948 inst
.operands
[i
].reg
= rege
->number
;
6949 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6955 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6957 || (rege
->type
!= REG_TYPE_MMXWC
6958 && rege
->type
!= REG_TYPE_MMXWCG
))
6960 inst
.error
= _("iWMMXt control register expected");
6963 inst
.operands
[i
].reg
= rege
->number
;
6964 inst
.operands
[i
].isreg
= 1;
6969 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6970 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6971 case OP_oROR
: val
= parse_ror (&str
); break;
6972 case OP_COND
: val
= parse_cond (&str
); break;
6973 case OP_oBARRIER_I15
:
6974 po_barrier_or_imm (str
); break;
6976 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6982 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6983 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6985 inst
.error
= _("Banked registers are not available with this "
6991 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6995 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6998 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7000 if (strncasecmp (str
, "APSR_", 5) == 0)
7007 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7008 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7009 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7010 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7011 default: found
= 16;
7015 inst
.operands
[i
].isvec
= 1;
7016 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7017 inst
.operands
[i
].reg
= REG_PC
;
7024 po_misc_or_fail (parse_tb (&str
));
7027 /* Register lists. */
7029 val
= parse_reg_list (&str
);
7032 inst
.operands
[i
].writeback
= 1;
7038 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7042 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7046 /* Allow Q registers too. */
7047 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7052 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7054 inst
.operands
[i
].issingle
= 1;
7059 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7064 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7065 &inst
.operands
[i
].vectype
);
7068 /* Addressing modes */
7070 po_misc_or_fail (parse_address (&str
, i
));
7074 po_misc_or_fail_no_backtrack (
7075 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7079 po_misc_or_fail_no_backtrack (
7080 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7084 po_misc_or_fail_no_backtrack (
7085 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7089 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7093 po_misc_or_fail_no_backtrack (
7094 parse_shifter_operand_group_reloc (&str
, i
));
7098 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7102 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7106 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7110 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7113 /* Various value-based sanity checks and shared operations. We
7114 do not signal immediate failures for the register constraints;
7115 this allows a syntax error to take precedence. */
7116 switch (op_parse_code
)
7124 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7125 inst
.error
= BAD_PC
;
7130 if (inst
.operands
[i
].isreg
)
7132 if (inst
.operands
[i
].reg
== REG_PC
)
7133 inst
.error
= BAD_PC
;
7134 else if (inst
.operands
[i
].reg
== REG_SP
)
7135 inst
.error
= BAD_SP
;
7140 if (inst
.operands
[i
].isreg
7141 && inst
.operands
[i
].reg
== REG_PC
7142 && (inst
.operands
[i
].writeback
|| thumb
))
7143 inst
.error
= BAD_PC
;
7152 case OP_oBARRIER_I15
:
7161 inst
.operands
[i
].imm
= val
;
7168 /* If we get here, this operand was successfully parsed. */
7169 inst
.operands
[i
].present
= 1;
7173 inst
.error
= BAD_ARGS
;
7178 /* The parse routine should already have set inst.error, but set a
7179 default here just in case. */
7181 inst
.error
= _("syntax error");
7185 /* Do not backtrack over a trailing optional argument that
7186 absorbed some text. We will only fail again, with the
7187 'garbage following instruction' error message, which is
7188 probably less helpful than the current one. */
7189 if (backtrack_index
== i
&& backtrack_pos
!= str
7190 && upat
[i
+1] == OP_stop
)
7193 inst
.error
= _("syntax error");
7197 /* Try again, skipping the optional argument at backtrack_pos. */
7198 str
= backtrack_pos
;
7199 inst
.error
= backtrack_error
;
7200 inst
.operands
[backtrack_index
].present
= 0;
7201 i
= backtrack_index
;
7205 /* Check that we have parsed all the arguments. */
7206 if (*str
!= '\0' && !inst
.error
)
7207 inst
.error
= _("garbage following instruction");
7209 return inst
.error
? FAIL
: SUCCESS
;
7212 #undef po_char_or_fail
7213 #undef po_reg_or_fail
7214 #undef po_reg_or_goto
7215 #undef po_imm_or_fail
7216 #undef po_scalar_or_fail
7217 #undef po_barrier_or_imm
7219 /* Shorthand macro for instruction encoding functions issuing errors. */
7220 #define constraint(expr, err) \
7231 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7232 instructions are unpredictable if these registers are used. This
7233 is the BadReg predicate in ARM's Thumb-2 documentation. */
7234 #define reject_bad_reg(reg) \
7236 if (reg == REG_SP || reg == REG_PC) \
7238 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7243 /* If REG is R13 (the stack pointer), warn that its use is
7245 #define warn_deprecated_sp(reg) \
7247 if (warn_on_deprecated && reg == REG_SP) \
7248 as_tsktsk (_("use of r13 is deprecated")); \
7251 /* Functions for operand encoding. ARM, then Thumb. */
7253 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7255 /* If VAL can be encoded in the immediate field of an ARM instruction,
7256 return the encoded form. Otherwise, return FAIL. */
7259 encode_arm_immediate (unsigned int val
)
7263 for (i
= 0; i
< 32; i
+= 2)
7264 if ((a
= rotate_left (val
, i
)) <= 0xff)
7265 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7270 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7271 return the encoded form. Otherwise, return FAIL. */
7273 encode_thumb32_immediate (unsigned int val
)
7280 for (i
= 1; i
<= 24; i
++)
7283 if ((val
& ~(0xff << i
)) == 0)
7284 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7288 if (val
== ((a
<< 16) | a
))
7290 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7294 if (val
== ((a
<< 16) | a
))
7295 return 0x200 | (a
>> 8);
7299 /* Encode a VFP SP or DP register number into inst.instruction. */
7302 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7304 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7307 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7310 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7313 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7318 first_error (_("D register out of range for selected VFP version"));
7326 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7330 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7334 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7338 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7342 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7346 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7354 /* Encode a <shift> in an ARM-format instruction. The immediate,
7355 if any, is handled by md_apply_fix. */
7357 encode_arm_shift (int i
)
7359 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7360 inst
.instruction
|= SHIFT_ROR
<< 5;
7363 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7364 if (inst
.operands
[i
].immisreg
)
7366 inst
.instruction
|= SHIFT_BY_REG
;
7367 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7370 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7375 encode_arm_shifter_operand (int i
)
7377 if (inst
.operands
[i
].isreg
)
7379 inst
.instruction
|= inst
.operands
[i
].reg
;
7380 encode_arm_shift (i
);
7384 inst
.instruction
|= INST_IMMEDIATE
;
7385 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7386 inst
.instruction
|= inst
.operands
[i
].imm
;
7390 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7392 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7395 Generate an error if the operand is not a register. */
7396 constraint (!inst
.operands
[i
].isreg
,
7397 _("Instruction does not support =N addresses"));
7399 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7401 if (inst
.operands
[i
].preind
)
7405 inst
.error
= _("instruction does not accept preindexed addressing");
7408 inst
.instruction
|= PRE_INDEX
;
7409 if (inst
.operands
[i
].writeback
)
7410 inst
.instruction
|= WRITE_BACK
;
7413 else if (inst
.operands
[i
].postind
)
7415 gas_assert (inst
.operands
[i
].writeback
);
7417 inst
.instruction
|= WRITE_BACK
;
7419 else /* unindexed - only for coprocessor */
7421 inst
.error
= _("instruction does not accept unindexed addressing");
7425 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7426 && (((inst
.instruction
& 0x000f0000) >> 16)
7427 == ((inst
.instruction
& 0x0000f000) >> 12)))
7428 as_warn ((inst
.instruction
& LOAD_BIT
)
7429 ? _("destination register same as write-back base")
7430 : _("source register same as write-back base"));
7433 /* inst.operands[i] was set up by parse_address. Encode it into an
7434 ARM-format mode 2 load or store instruction. If is_t is true,
7435 reject forms that cannot be used with a T instruction (i.e. not
7438 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7440 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7442 encode_arm_addr_mode_common (i
, is_t
);
7444 if (inst
.operands
[i
].immisreg
)
7446 constraint ((inst
.operands
[i
].imm
== REG_PC
7447 || (is_pc
&& inst
.operands
[i
].writeback
)),
7449 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7450 inst
.instruction
|= inst
.operands
[i
].imm
;
7451 if (!inst
.operands
[i
].negative
)
7452 inst
.instruction
|= INDEX_UP
;
7453 if (inst
.operands
[i
].shifted
)
7455 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7456 inst
.instruction
|= SHIFT_ROR
<< 5;
7459 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7460 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7464 else /* immediate offset in inst.reloc */
7466 if (is_pc
&& !inst
.reloc
.pc_rel
)
7468 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7470 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7471 cannot use PC in addressing.
7472 PC cannot be used in writeback addressing, either. */
7473 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7476 /* Use of PC in str is deprecated for ARMv7. */
7477 if (warn_on_deprecated
7479 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7480 as_tsktsk (_("use of PC in this instruction is deprecated"));
7483 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7485 /* Prefer + for zero encoded value. */
7486 if (!inst
.operands
[i
].negative
)
7487 inst
.instruction
|= INDEX_UP
;
7488 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7493 /* inst.operands[i] was set up by parse_address. Encode it into an
7494 ARM-format mode 3 load or store instruction. Reject forms that
7495 cannot be used with such instructions. If is_t is true, reject
7496 forms that cannot be used with a T instruction (i.e. not
7499 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7501 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7503 inst
.error
= _("instruction does not accept scaled register index");
7507 encode_arm_addr_mode_common (i
, is_t
);
7509 if (inst
.operands
[i
].immisreg
)
7511 constraint ((inst
.operands
[i
].imm
== REG_PC
7512 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7514 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7516 inst
.instruction
|= inst
.operands
[i
].imm
;
7517 if (!inst
.operands
[i
].negative
)
7518 inst
.instruction
|= INDEX_UP
;
7520 else /* immediate offset in inst.reloc */
7522 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7523 && inst
.operands
[i
].writeback
),
7525 inst
.instruction
|= HWOFFSET_IMM
;
7526 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7528 /* Prefer + for zero encoded value. */
7529 if (!inst
.operands
[i
].negative
)
7530 inst
.instruction
|= INDEX_UP
;
7532 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7537 /* Write immediate bits [7:0] to the following locations:
7539 |28/24|23 19|18 16|15 4|3 0|
7540 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7542 This function is used by VMOV/VMVN/VORR/VBIC. */
7545 neon_write_immbits (unsigned immbits
)
7547 inst
.instruction
|= immbits
& 0xf;
7548 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7549 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7552 /* Invert low-order SIZE bits of XHI:XLO. */
7555 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7557 unsigned immlo
= xlo
? *xlo
: 0;
7558 unsigned immhi
= xhi
? *xhi
: 0;
7563 immlo
= (~immlo
) & 0xff;
7567 immlo
= (~immlo
) & 0xffff;
7571 immhi
= (~immhi
) & 0xffffffff;
7575 immlo
= (~immlo
) & 0xffffffff;
7589 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7593 neon_bits_same_in_bytes (unsigned imm
)
7595 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7596 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7597 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7598 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7601 /* For immediate of above form, return 0bABCD. */
7604 neon_squash_bits (unsigned imm
)
7606 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7607 | ((imm
& 0x01000000) >> 21);
7610 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7613 neon_qfloat_bits (unsigned imm
)
7615 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7618 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7619 the instruction. *OP is passed as the initial value of the op field, and
7620 may be set to a different value depending on the constant (i.e.
7621 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7622 MVN). If the immediate looks like a repeated pattern then also
7623 try smaller element sizes. */
7626 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7627 unsigned *immbits
, int *op
, int size
,
7628 enum neon_el_type type
)
7630 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7632 if (type
== NT_float
&& !float_p
)
7635 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7637 if (size
!= 32 || *op
== 1)
7639 *immbits
= neon_qfloat_bits (immlo
);
7645 if (neon_bits_same_in_bytes (immhi
)
7646 && neon_bits_same_in_bytes (immlo
))
7650 *immbits
= (neon_squash_bits (immhi
) << 4)
7651 | neon_squash_bits (immlo
);
7662 if (immlo
== (immlo
& 0x000000ff))
7667 else if (immlo
== (immlo
& 0x0000ff00))
7669 *immbits
= immlo
>> 8;
7672 else if (immlo
== (immlo
& 0x00ff0000))
7674 *immbits
= immlo
>> 16;
7677 else if (immlo
== (immlo
& 0xff000000))
7679 *immbits
= immlo
>> 24;
7682 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7684 *immbits
= (immlo
>> 8) & 0xff;
7687 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7689 *immbits
= (immlo
>> 16) & 0xff;
7693 if ((immlo
& 0xffff) != (immlo
>> 16))
7700 if (immlo
== (immlo
& 0x000000ff))
7705 else if (immlo
== (immlo
& 0x0000ff00))
7707 *immbits
= immlo
>> 8;
7711 if ((immlo
& 0xff) != (immlo
>> 8))
7716 if (immlo
== (immlo
& 0x000000ff))
7718 /* Don't allow MVN with 8-bit immediate. */
7728 #if defined BFD_HOST_64_BIT
7729 /* Returns TRUE if double precision value V may be cast
7730 to single precision without loss of accuracy. */
7733 is_double_a_single (bfd_int64_t v
)
7735 int exp
= (int)((v
>> 52) & 0x7FF);
7736 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7738 return (exp
== 0 || exp
== 0x7FF
7739 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7740 && (mantissa
& 0x1FFFFFFFl
) == 0;
7743 /* Returns a double precision value casted to single precision
7744 (ignoring the least significant bits in exponent and mantissa). */
7747 double_to_single (bfd_int64_t v
)
7749 int sign
= (int) ((v
>> 63) & 1l);
7750 int exp
= (int) ((v
>> 52) & 0x7FF);
7751 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7757 exp
= exp
- 1023 + 127;
7766 /* No denormalized numbers. */
7772 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7774 #endif /* BFD_HOST_64_BIT */
7783 static void do_vfp_nsyn_opcode (const char *);
7785 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7786 Determine whether it can be performed with a move instruction; if
7787 it can, convert inst.instruction to that move instruction and
7788 return TRUE; if it can't, convert inst.instruction to a literal-pool
7789 load and return FALSE. If this is not a valid thing to do in the
7790 current context, set inst.error and return TRUE.
7792 inst.operands[i] describes the destination register. */
7795 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7798 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7799 bfd_boolean arm_p
= (t
== CONST_ARM
);
7802 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7806 if ((inst
.instruction
& tbit
) == 0)
7808 inst
.error
= _("invalid pseudo operation");
7812 if (inst
.reloc
.exp
.X_op
!= O_constant
7813 && inst
.reloc
.exp
.X_op
!= O_symbol
7814 && inst
.reloc
.exp
.X_op
!= O_big
)
7816 inst
.error
= _("constant expression expected");
7820 if (inst
.reloc
.exp
.X_op
== O_constant
7821 || inst
.reloc
.exp
.X_op
== O_big
)
7823 #if defined BFD_HOST_64_BIT
7828 if (inst
.reloc
.exp
.X_op
== O_big
)
7830 LITTLENUM_TYPE w
[X_PRECISION
];
7833 if (inst
.reloc
.exp
.X_add_number
== -1)
7835 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7837 /* FIXME: Should we check words w[2..5] ? */
7842 #if defined BFD_HOST_64_BIT
7844 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7845 << LITTLENUM_NUMBER_OF_BITS
)
7846 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7847 << LITTLENUM_NUMBER_OF_BITS
)
7848 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7849 << LITTLENUM_NUMBER_OF_BITS
)
7850 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7852 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7853 | (l
[0] & LITTLENUM_MASK
);
7857 v
= inst
.reloc
.exp
.X_add_number
;
7859 if (!inst
.operands
[i
].issingle
)
7863 /* This can be encoded only for a low register. */
7864 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7866 /* This can be done with a mov(1) instruction. */
7867 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7868 inst
.instruction
|= v
;
7872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
7874 /* Check if on thumb2 it can be done with a mov.w or mvn.w
7876 unsigned int newimm
;
7877 bfd_boolean isNegated
;
7879 newimm
= encode_thumb32_immediate (v
);
7880 if (newimm
!= (unsigned int) FAIL
)
7884 newimm
= encode_thumb32_immediate (~v
);
7885 if (newimm
!= (unsigned int) FAIL
)
7889 if (newimm
!= (unsigned int) FAIL
)
7891 inst
.instruction
= (0xf04f0000
7892 | (inst
.operands
[i
].reg
<< 8));
7893 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7894 inst
.instruction
|= (newimm
& 0x800) << 15;
7895 inst
.instruction
|= (newimm
& 0x700) << 4;
7896 inst
.instruction
|= (newimm
& 0x0ff);
7899 else if ((v
& ~0xFFFF) == 0)
7901 /* The number can be loaded with a mov.w instruction. */
7902 int imm
= v
& 0xFFFF;
7904 inst
.instruction
= 0xf2400000; /* MOVW. */
7905 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7906 inst
.instruction
|= (imm
& 0xf000) << 4;
7907 inst
.instruction
|= (imm
& 0x0800) << 15;
7908 inst
.instruction
|= (imm
& 0x0700) << 4;
7909 inst
.instruction
|= (imm
& 0x00ff);
7916 int value
= encode_arm_immediate (v
);
7920 /* This can be done with a mov instruction. */
7921 inst
.instruction
&= LITERAL_MASK
;
7922 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7923 inst
.instruction
|= value
& 0xfff;
7927 value
= encode_arm_immediate (~ v
);
7930 /* This can be done with a mvn instruction. */
7931 inst
.instruction
&= LITERAL_MASK
;
7932 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7933 inst
.instruction
|= value
& 0xfff;
7937 else if (t
== CONST_VEC
)
7940 unsigned immbits
= 0;
7941 unsigned immlo
= inst
.operands
[1].imm
;
7942 unsigned immhi
= inst
.operands
[1].regisimm
7943 ? inst
.operands
[1].reg
7944 : inst
.reloc
.exp
.X_unsigned
7946 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7947 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7948 &op
, 64, NT_invtype
);
7952 neon_invert_size (&immlo
, &immhi
, 64);
7954 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7955 &op
, 64, NT_invtype
);
7960 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7966 /* Fill other bits in vmov encoding for both thumb and arm. */
7968 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7970 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7971 neon_write_immbits (immbits
);
7979 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7980 if (inst
.operands
[i
].issingle
7981 && is_quarter_float (inst
.operands
[1].imm
)
7982 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7984 inst
.operands
[1].imm
=
7985 neon_qfloat_bits (v
);
7986 do_vfp_nsyn_opcode ("fconsts");
7990 /* If our host does not support a 64-bit type then we cannot perform
7991 the following optimization. This mean that there will be a
7992 discrepancy between the output produced by an assembler built for
7993 a 32-bit-only host and the output produced from a 64-bit host, but
7994 this cannot be helped. */
7995 #if defined BFD_HOST_64_BIT
7996 else if (!inst
.operands
[1].issingle
7997 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
7999 if (is_double_a_single (v
)
8000 && is_quarter_float (double_to_single (v
)))
8002 inst
.operands
[1].imm
=
8003 neon_qfloat_bits (double_to_single (v
));
8004 do_vfp_nsyn_opcode ("fconstd");
8012 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8013 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8016 inst
.operands
[1].reg
= REG_PC
;
8017 inst
.operands
[1].isreg
= 1;
8018 inst
.operands
[1].preind
= 1;
8019 inst
.reloc
.pc_rel
= 1;
8020 inst
.reloc
.type
= (thumb_p
8021 ? BFD_RELOC_ARM_THUMB_OFFSET
8023 ? BFD_RELOC_ARM_HWLITERAL
8024 : BFD_RELOC_ARM_LITERAL
));
8028 /* inst.operands[i] was set up by parse_address. Encode it into an
8029 ARM-format instruction. Reject all forms which cannot be encoded
8030 into a coprocessor load/store instruction. If wb_ok is false,
8031 reject use of writeback; if unind_ok is false, reject use of
8032 unindexed addressing. If reloc_override is not 0, use it instead
8033 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8034 (in which case it is preserved). */
8037 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8039 if (!inst
.operands
[i
].isreg
)
8042 if (! inst
.operands
[0].isvec
)
8044 inst
.error
= _("invalid co-processor operand");
8047 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8051 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8053 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8055 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8057 gas_assert (!inst
.operands
[i
].writeback
);
8060 inst
.error
= _("instruction does not support unindexed addressing");
8063 inst
.instruction
|= inst
.operands
[i
].imm
;
8064 inst
.instruction
|= INDEX_UP
;
8068 if (inst
.operands
[i
].preind
)
8069 inst
.instruction
|= PRE_INDEX
;
8071 if (inst
.operands
[i
].writeback
)
8073 if (inst
.operands
[i
].reg
== REG_PC
)
8075 inst
.error
= _("pc may not be used with write-back");
8080 inst
.error
= _("instruction does not support writeback");
8083 inst
.instruction
|= WRITE_BACK
;
8087 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8088 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8089 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8090 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8093 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8095 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8098 /* Prefer + for zero encoded value. */
8099 if (!inst
.operands
[i
].negative
)
8100 inst
.instruction
|= INDEX_UP
;
8105 /* Functions for instruction encoding, sorted by sub-architecture.
8106 First some generics; their names are taken from the conventional
8107 bit positions for register arguments in ARM format instructions. */
8117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8124 inst
.instruction
|= inst
.operands
[1].reg
;
8130 inst
.instruction
|= inst
.operands
[0].reg
;
8131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8138 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8144 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8145 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8149 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8151 if (ARM_CPU_IS_ANY (cpu_variant
))
8153 as_tsktsk ("%s", msg
);
8156 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8168 unsigned Rn
= inst
.operands
[2].reg
;
8169 /* Enforce restrictions on SWP instruction. */
8170 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8172 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8173 _("Rn must not overlap other operands"));
8175 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8177 if (!check_obsolete (&arm_ext_v8
,
8178 _("swp{b} use is obsoleted for ARMv8 and later"))
8179 && warn_on_deprecated
8180 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8181 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[1].reg
;
8186 inst
.instruction
|= Rn
<< 16;
8192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8193 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8194 inst
.instruction
|= inst
.operands
[2].reg
;
8200 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8201 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8202 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8203 || inst
.reloc
.exp
.X_add_number
!= 0),
8205 inst
.instruction
|= inst
.operands
[0].reg
;
8206 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8207 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8213 inst
.instruction
|= inst
.operands
[0].imm
;
8219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8220 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8223 /* ARM instructions, in alphabetical order by function name (except
8224 that wrapper functions appear immediately after the function they
8227 /* This is a pseudo-op of the form "adr rd, label" to be converted
8228 into a relative address of the form "add rd, pc, #label-.-8". */
8233 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8235 /* Frag hacking will turn this into a sub instruction if the offset turns
8236 out to be negative. */
8237 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8238 inst
.reloc
.pc_rel
= 1;
8239 inst
.reloc
.exp
.X_add_number
-= 8;
8242 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8243 into a relative address of the form:
8244 add rd, pc, #low(label-.-8)"
8245 add rd, rd, #high(label-.-8)" */
8250 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8252 /* Frag hacking will turn this into a sub instruction if the offset turns
8253 out to be negative. */
8254 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8255 inst
.reloc
.pc_rel
= 1;
8256 inst
.size
= INSN_SIZE
* 2;
8257 inst
.reloc
.exp
.X_add_number
-= 8;
8263 if (!inst
.operands
[1].present
)
8264 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8266 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8267 encode_arm_shifter_operand (2);
8273 if (inst
.operands
[0].present
)
8274 inst
.instruction
|= inst
.operands
[0].imm
;
8276 inst
.instruction
|= 0xf;
8282 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8283 constraint (msb
> 32, _("bit-field extends past end of register"));
8284 /* The instruction encoding stores the LSB and MSB,
8285 not the LSB and width. */
8286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8287 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8288 inst
.instruction
|= (msb
- 1) << 16;
8296 /* #0 in second position is alternative syntax for bfc, which is
8297 the same instruction but with REG_PC in the Rm field. */
8298 if (!inst
.operands
[1].isreg
)
8299 inst
.operands
[1].reg
= REG_PC
;
8301 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8302 constraint (msb
> 32, _("bit-field extends past end of register"));
8303 /* The instruction encoding stores the LSB and MSB,
8304 not the LSB and width. */
8305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8306 inst
.instruction
|= inst
.operands
[1].reg
;
8307 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8308 inst
.instruction
|= (msb
- 1) << 16;
8314 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8315 _("bit-field extends past end of register"));
8316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8317 inst
.instruction
|= inst
.operands
[1].reg
;
8318 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8319 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8322 /* ARM V5 breakpoint instruction (argument parse)
8323 BKPT <16 bit unsigned immediate>
8324 Instruction is not conditional.
8325 The bit pattern given in insns[] has the COND_ALWAYS condition,
8326 and it is an error if the caller tried to override that. */
8331 /* Top 12 of 16 bits to bits 19:8. */
8332 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8334 /* Bottom 4 of 16 bits to bits 3:0. */
8335 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8339 encode_branch (int default_reloc
)
8341 if (inst
.operands
[0].hasreloc
)
8343 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8344 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8345 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8346 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8347 ? BFD_RELOC_ARM_PLT32
8348 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8351 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8352 inst
.reloc
.pc_rel
= 1;
8359 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8360 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8363 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8370 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8372 if (inst
.cond
== COND_ALWAYS
)
8373 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8375 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8379 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8382 /* ARM V5 branch-link-exchange instruction (argument parse)
8383 BLX <target_addr> ie BLX(1)
8384 BLX{<condition>} <Rm> ie BLX(2)
8385 Unfortunately, there are two different opcodes for this mnemonic.
8386 So, the insns[].value is not used, and the code here zaps values
8387 into inst.instruction.
8388 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8393 if (inst
.operands
[0].isreg
)
8395 /* Arg is a register; the opcode provided by insns[] is correct.
8396 It is not illegal to do "blx pc", just useless. */
8397 if (inst
.operands
[0].reg
== REG_PC
)
8398 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8400 inst
.instruction
|= inst
.operands
[0].reg
;
8404 /* Arg is an address; this instruction cannot be executed
8405 conditionally, and the opcode must be adjusted.
8406 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8407 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8408 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8409 inst
.instruction
= 0xfa000000;
8410 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8417 bfd_boolean want_reloc
;
8419 if (inst
.operands
[0].reg
== REG_PC
)
8420 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8422 inst
.instruction
|= inst
.operands
[0].reg
;
8423 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8424 it is for ARMv4t or earlier. */
8425 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8426 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8430 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8435 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8439 /* ARM v5TEJ. Jump to Jazelle code. */
8444 if (inst
.operands
[0].reg
== REG_PC
)
8445 as_tsktsk (_("use of r15 in bxj is not really useful"));
8447 inst
.instruction
|= inst
.operands
[0].reg
;
8450 /* Co-processor data operation:
8451 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8452 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8456 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8457 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8458 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8459 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8460 inst
.instruction
|= inst
.operands
[4].reg
;
8461 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8467 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8468 encode_arm_shifter_operand (1);
8471 /* Transfer between coprocessor and ARM registers.
8472 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8477 No special properties. */
8479 struct deprecated_coproc_regs_s
8486 arm_feature_set deprecated
;
8487 arm_feature_set obsoleted
;
8488 const char *dep_msg
;
8489 const char *obs_msg
;
8492 #define DEPR_ACCESS_V8 \
8493 N_("This coprocessor register access is deprecated in ARMv8")
8495 /* Table of all deprecated coprocessor registers. */
8496 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8498 {15, 0, 7, 10, 5, /* CP15DMB. */
8499 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8500 DEPR_ACCESS_V8
, NULL
},
8501 {15, 0, 7, 10, 4, /* CP15DSB. */
8502 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8503 DEPR_ACCESS_V8
, NULL
},
8504 {15, 0, 7, 5, 4, /* CP15ISB. */
8505 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8506 DEPR_ACCESS_V8
, NULL
},
8507 {14, 6, 1, 0, 0, /* TEEHBR. */
8508 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8509 DEPR_ACCESS_V8
, NULL
},
8510 {14, 6, 0, 0, 0, /* TEECR. */
8511 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8512 DEPR_ACCESS_V8
, NULL
},
8515 #undef DEPR_ACCESS_V8
8517 static const size_t deprecated_coproc_reg_count
=
8518 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8526 Rd
= inst
.operands
[2].reg
;
8529 if (inst
.instruction
== 0xee000010
8530 || inst
.instruction
== 0xfe000010)
8532 reject_bad_reg (Rd
);
8535 constraint (Rd
== REG_SP
, BAD_SP
);
8540 if (inst
.instruction
== 0xe000010)
8541 constraint (Rd
== REG_PC
, BAD_PC
);
8544 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8546 const struct deprecated_coproc_regs_s
*r
=
8547 deprecated_coproc_regs
+ i
;
8549 if (inst
.operands
[0].reg
== r
->cp
8550 && inst
.operands
[1].imm
== r
->opc1
8551 && inst
.operands
[3].reg
== r
->crn
8552 && inst
.operands
[4].reg
== r
->crm
8553 && inst
.operands
[5].imm
== r
->opc2
)
8555 if (! ARM_CPU_IS_ANY (cpu_variant
)
8556 && warn_on_deprecated
8557 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8558 as_tsktsk ("%s", r
->dep_msg
);
8562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8563 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8564 inst
.instruction
|= Rd
<< 12;
8565 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8566 inst
.instruction
|= inst
.operands
[4].reg
;
8567 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8570 /* Transfer between coprocessor register and pair of ARM registers.
8571 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8576 Two XScale instructions are special cases of these:
8578 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8579 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8581 Result unpredictable if Rd or Rn is R15. */
8588 Rd
= inst
.operands
[2].reg
;
8589 Rn
= inst
.operands
[3].reg
;
8593 reject_bad_reg (Rd
);
8594 reject_bad_reg (Rn
);
8598 constraint (Rd
== REG_PC
, BAD_PC
);
8599 constraint (Rn
== REG_PC
, BAD_PC
);
8602 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8603 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8604 inst
.instruction
|= Rd
<< 12;
8605 inst
.instruction
|= Rn
<< 16;
8606 inst
.instruction
|= inst
.operands
[4].reg
;
8612 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8613 if (inst
.operands
[1].present
)
8615 inst
.instruction
|= CPSI_MMOD
;
8616 inst
.instruction
|= inst
.operands
[1].imm
;
8623 inst
.instruction
|= inst
.operands
[0].imm
;
8629 unsigned Rd
, Rn
, Rm
;
8631 Rd
= inst
.operands
[0].reg
;
8632 Rn
= (inst
.operands
[1].present
8633 ? inst
.operands
[1].reg
: Rd
);
8634 Rm
= inst
.operands
[2].reg
;
8636 constraint ((Rd
== REG_PC
), BAD_PC
);
8637 constraint ((Rn
== REG_PC
), BAD_PC
);
8638 constraint ((Rm
== REG_PC
), BAD_PC
);
8640 inst
.instruction
|= Rd
<< 16;
8641 inst
.instruction
|= Rn
<< 0;
8642 inst
.instruction
|= Rm
<< 8;
8648 /* There is no IT instruction in ARM mode. We
8649 process it to do the validation as if in
8650 thumb mode, just in case the code gets
8651 assembled for thumb using the unified syntax. */
8656 set_it_insn_type (IT_INSN
);
8657 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8658 now_it
.cc
= inst
.operands
[0].imm
;
8662 /* If there is only one register in the register list,
8663 then return its register number. Otherwise return -1. */
8665 only_one_reg_in_list (int range
)
8667 int i
= ffs (range
) - 1;
8668 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8672 encode_ldmstm(int from_push_pop_mnem
)
8674 int base_reg
= inst
.operands
[0].reg
;
8675 int range
= inst
.operands
[1].imm
;
8678 inst
.instruction
|= base_reg
<< 16;
8679 inst
.instruction
|= range
;
8681 if (inst
.operands
[1].writeback
)
8682 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8684 if (inst
.operands
[0].writeback
)
8686 inst
.instruction
|= WRITE_BACK
;
8687 /* Check for unpredictable uses of writeback. */
8688 if (inst
.instruction
& LOAD_BIT
)
8690 /* Not allowed in LDM type 2. */
8691 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8692 && ((range
& (1 << REG_PC
)) == 0))
8693 as_warn (_("writeback of base register is UNPREDICTABLE"));
8694 /* Only allowed if base reg not in list for other types. */
8695 else if (range
& (1 << base_reg
))
8696 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8700 /* Not allowed for type 2. */
8701 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8702 as_warn (_("writeback of base register is UNPREDICTABLE"));
8703 /* Only allowed if base reg not in list, or first in list. */
8704 else if ((range
& (1 << base_reg
))
8705 && (range
& ((1 << base_reg
) - 1)))
8706 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8710 /* If PUSH/POP has only one register, then use the A2 encoding. */
8711 one_reg
= only_one_reg_in_list (range
);
8712 if (from_push_pop_mnem
&& one_reg
>= 0)
8714 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8716 inst
.instruction
&= A_COND_MASK
;
8717 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8718 inst
.instruction
|= one_reg
<< 12;
8725 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8728 /* ARMv5TE load-consecutive (argument parse)
8737 constraint (inst
.operands
[0].reg
% 2 != 0,
8738 _("first transfer register must be even"));
8739 constraint (inst
.operands
[1].present
8740 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8741 _("can only transfer two consecutive registers"));
8742 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8743 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8745 if (!inst
.operands
[1].present
)
8746 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8748 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8749 register and the first register written; we have to diagnose
8750 overlap between the base and the second register written here. */
8752 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8753 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8754 as_warn (_("base register written back, and overlaps "
8755 "second transfer register"));
8757 if (!(inst
.instruction
& V4_STR_BIT
))
8759 /* For an index-register load, the index register must not overlap the
8760 destination (even if not write-back). */
8761 if (inst
.operands
[2].immisreg
8762 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8763 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8764 as_warn (_("index register overlaps transfer register"));
8766 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8767 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8773 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8774 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8775 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8776 || inst
.operands
[1].negative
8777 /* This can arise if the programmer has written
8779 or if they have mistakenly used a register name as the last
8782 It is very difficult to distinguish between these two cases
8783 because "rX" might actually be a label. ie the register
8784 name has been occluded by a symbol of the same name. So we
8785 just generate a general 'bad addressing mode' type error
8786 message and leave it up to the programmer to discover the
8787 true cause and fix their mistake. */
8788 || (inst
.operands
[1].reg
== REG_PC
),
8791 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8792 || inst
.reloc
.exp
.X_add_number
!= 0,
8793 _("offset must be zero in ARM encoding"));
8795 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8797 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8798 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8799 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8805 constraint (inst
.operands
[0].reg
% 2 != 0,
8806 _("even register required"));
8807 constraint (inst
.operands
[1].present
8808 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8809 _("can only load two consecutive registers"));
8810 /* If op 1 were present and equal to PC, this function wouldn't
8811 have been called in the first place. */
8812 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8814 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8815 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8818 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8819 which is not a multiple of four is UNPREDICTABLE. */
8821 check_ldr_r15_aligned (void)
8823 constraint (!(inst
.operands
[1].immisreg
)
8824 && (inst
.operands
[0].reg
== REG_PC
8825 && inst
.operands
[1].reg
== REG_PC
8826 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8827 _("ldr to register 15 must be 4-byte alligned"));
8833 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8834 if (!inst
.operands
[1].isreg
)
8835 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8837 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8838 check_ldr_r15_aligned ();
8844 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8846 if (inst
.operands
[1].preind
)
8848 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8849 || inst
.reloc
.exp
.X_add_number
!= 0,
8850 _("this instruction requires a post-indexed address"));
8852 inst
.operands
[1].preind
= 0;
8853 inst
.operands
[1].postind
= 1;
8854 inst
.operands
[1].writeback
= 1;
8856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8857 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8860 /* Halfword and signed-byte load/store operations. */
8865 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8867 if (!inst
.operands
[1].isreg
)
8868 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8870 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8876 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8878 if (inst
.operands
[1].preind
)
8880 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8881 || inst
.reloc
.exp
.X_add_number
!= 0,
8882 _("this instruction requires a post-indexed address"));
8884 inst
.operands
[1].preind
= 0;
8885 inst
.operands
[1].postind
= 1;
8886 inst
.operands
[1].writeback
= 1;
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8889 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8892 /* Co-processor register load/store.
8893 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8898 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8899 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8905 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8906 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8907 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8908 && !(inst
.instruction
& 0x00400000))
8909 as_tsktsk (_("Rd and Rm should be different in mla"));
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8912 inst
.instruction
|= inst
.operands
[1].reg
;
8913 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8914 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8921 encode_arm_shifter_operand (1);
8924 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8931 top
= (inst
.instruction
& 0x00400000) != 0;
8932 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8933 _(":lower16: not allowed this instruction"));
8934 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8935 _(":upper16: not allowed instruction"));
8936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8937 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8939 imm
= inst
.reloc
.exp
.X_add_number
;
8940 /* The value is in two pieces: 0:11, 16:19. */
8941 inst
.instruction
|= (imm
& 0x00000fff);
8942 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8947 do_vfp_nsyn_mrs (void)
8949 if (inst
.operands
[0].isvec
)
8951 if (inst
.operands
[1].reg
!= 1)
8952 first_error (_("operand 1 must be FPSCR"));
8953 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8954 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8955 do_vfp_nsyn_opcode ("fmstat");
8957 else if (inst
.operands
[1].isvec
)
8958 do_vfp_nsyn_opcode ("fmrx");
8966 do_vfp_nsyn_msr (void)
8968 if (inst
.operands
[0].isvec
)
8969 do_vfp_nsyn_opcode ("fmxr");
8979 unsigned Rt
= inst
.operands
[0].reg
;
8981 if (thumb_mode
&& Rt
== REG_SP
)
8983 inst
.error
= BAD_SP
;
8987 /* APSR_ sets isvec. All other refs to PC are illegal. */
8988 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8990 inst
.error
= BAD_PC
;
8994 /* If we get through parsing the register name, we just insert the number
8995 generated into the instruction without further validation. */
8996 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8997 inst
.instruction
|= (Rt
<< 12);
9003 unsigned Rt
= inst
.operands
[1].reg
;
9006 reject_bad_reg (Rt
);
9007 else if (Rt
== REG_PC
)
9009 inst
.error
= BAD_PC
;
9013 /* If we get through parsing the register name, we just insert the number
9014 generated into the instruction without further validation. */
9015 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9016 inst
.instruction
|= (Rt
<< 12);
9024 if (do_vfp_nsyn_mrs () == SUCCESS
)
9027 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9030 if (inst
.operands
[1].isreg
)
9032 br
= inst
.operands
[1].reg
;
9033 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9034 as_bad (_("bad register for mrs"));
9038 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9039 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9041 _("'APSR', 'CPSR' or 'SPSR' expected"));
9042 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9045 inst
.instruction
|= br
;
9048 /* Two possible forms:
9049 "{C|S}PSR_<field>, Rm",
9050 "{C|S}PSR_f, #expression". */
9055 if (do_vfp_nsyn_msr () == SUCCESS
)
9058 inst
.instruction
|= inst
.operands
[0].imm
;
9059 if (inst
.operands
[1].isreg
)
9060 inst
.instruction
|= inst
.operands
[1].reg
;
9063 inst
.instruction
|= INST_IMMEDIATE
;
9064 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9065 inst
.reloc
.pc_rel
= 0;
9072 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9074 if (!inst
.operands
[2].present
)
9075 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9077 inst
.instruction
|= inst
.operands
[1].reg
;
9078 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9080 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9081 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9082 as_tsktsk (_("Rd and Rm should be different in mul"));
9085 /* Long Multiply Parser
9086 UMULL RdLo, RdHi, Rm, Rs
9087 SMULL RdLo, RdHi, Rm, Rs
9088 UMLAL RdLo, RdHi, Rm, Rs
9089 SMLAL RdLo, RdHi, Rm, Rs. */
9094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9095 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9096 inst
.instruction
|= inst
.operands
[2].reg
;
9097 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9099 /* rdhi and rdlo must be different. */
9100 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9101 as_tsktsk (_("rdhi and rdlo must be different"));
9103 /* rdhi, rdlo and rm must all be different before armv6. */
9104 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9105 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9106 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9107 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9113 if (inst
.operands
[0].present
9114 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9116 /* Architectural NOP hints are CPSR sets with no bits selected. */
9117 inst
.instruction
&= 0xf0000000;
9118 inst
.instruction
|= 0x0320f000;
9119 if (inst
.operands
[0].present
)
9120 inst
.instruction
|= inst
.operands
[0].imm
;
9124 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9125 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9126 Condition defaults to COND_ALWAYS.
9127 Error if Rd, Rn or Rm are R15. */
9132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9134 inst
.instruction
|= inst
.operands
[2].reg
;
9135 if (inst
.operands
[3].present
)
9136 encode_arm_shift (3);
9139 /* ARM V6 PKHTB (Argument Parse). */
9144 if (!inst
.operands
[3].present
)
9146 /* If the shift specifier is omitted, turn the instruction
9147 into pkhbt rd, rm, rn. */
9148 inst
.instruction
&= 0xfff00010;
9149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9150 inst
.instruction
|= inst
.operands
[1].reg
;
9151 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9156 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9157 inst
.instruction
|= inst
.operands
[2].reg
;
9158 encode_arm_shift (3);
9162 /* ARMv5TE: Preload-Cache
9163 MP Extensions: Preload for write
9167 Syntactically, like LDR with B=1, W=0, L=1. */
9172 constraint (!inst
.operands
[0].isreg
,
9173 _("'[' expected after PLD mnemonic"));
9174 constraint (inst
.operands
[0].postind
,
9175 _("post-indexed expression used in preload instruction"));
9176 constraint (inst
.operands
[0].writeback
,
9177 _("writeback used in preload instruction"));
9178 constraint (!inst
.operands
[0].preind
,
9179 _("unindexed addressing used in preload instruction"));
9180 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9183 /* ARMv7: PLI <addr_mode> */
9187 constraint (!inst
.operands
[0].isreg
,
9188 _("'[' expected after PLI mnemonic"));
9189 constraint (inst
.operands
[0].postind
,
9190 _("post-indexed expression used in preload instruction"));
9191 constraint (inst
.operands
[0].writeback
,
9192 _("writeback used in preload instruction"));
9193 constraint (!inst
.operands
[0].preind
,
9194 _("unindexed addressing used in preload instruction"));
9195 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9196 inst
.instruction
&= ~PRE_INDEX
;
9202 constraint (inst
.operands
[0].writeback
,
9203 _("push/pop do not support {reglist}^"));
9204 inst
.operands
[1] = inst
.operands
[0];
9205 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9206 inst
.operands
[0].isreg
= 1;
9207 inst
.operands
[0].writeback
= 1;
9208 inst
.operands
[0].reg
= REG_SP
;
9209 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9212 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9213 word at the specified address and the following word
9215 Unconditionally executed.
9216 Error if Rn is R15. */
9221 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9222 if (inst
.operands
[0].writeback
)
9223 inst
.instruction
|= WRITE_BACK
;
9226 /* ARM V6 ssat (argument parse). */
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9232 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9233 inst
.instruction
|= inst
.operands
[2].reg
;
9235 if (inst
.operands
[3].present
)
9236 encode_arm_shift (3);
9239 /* ARM V6 usat (argument parse). */
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9246 inst
.instruction
|= inst
.operands
[2].reg
;
9248 if (inst
.operands
[3].present
)
9249 encode_arm_shift (3);
9252 /* ARM V6 ssat16 (argument parse). */
9257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9258 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9259 inst
.instruction
|= inst
.operands
[2].reg
;
9265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9266 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9267 inst
.instruction
|= inst
.operands
[2].reg
;
9270 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9271 preserving the other bits.
9273 setend <endian_specifier>, where <endian_specifier> is either
9279 if (warn_on_deprecated
9280 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9281 as_tsktsk (_("setend use is deprecated for ARMv8"));
9283 if (inst
.operands
[0].imm
)
9284 inst
.instruction
|= 0x200;
9290 unsigned int Rm
= (inst
.operands
[1].present
9291 ? inst
.operands
[1].reg
9292 : inst
.operands
[0].reg
);
9294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9295 inst
.instruction
|= Rm
;
9296 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9298 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9299 inst
.instruction
|= SHIFT_BY_REG
;
9300 /* PR 12854: Error on extraneous shifts. */
9301 constraint (inst
.operands
[2].shifted
,
9302 _("extraneous shift as part of operand to shift insn"));
9305 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9311 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9312 inst
.reloc
.pc_rel
= 0;
9318 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9319 inst
.reloc
.pc_rel
= 0;
9325 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9326 inst
.reloc
.pc_rel
= 0;
9332 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9333 _("selected processor does not support SETPAN instruction"));
9335 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9341 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9342 _("selected processor does not support SETPAN instruction"));
9344 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9347 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9348 SMLAxy{cond} Rd,Rm,Rs,Rn
9349 SMLAWy{cond} Rd,Rm,Rs,Rn
9350 Error if any register is R15. */
9355 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9356 inst
.instruction
|= inst
.operands
[1].reg
;
9357 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9358 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9361 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9362 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9363 Error if any register is R15.
9364 Warning if Rdlo == Rdhi. */
9369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9370 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9371 inst
.instruction
|= inst
.operands
[2].reg
;
9372 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9374 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9375 as_tsktsk (_("rdhi and rdlo must be different"));
9378 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9379 SMULxy{cond} Rd,Rm,Rs
9380 Error if any register is R15. */
9385 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9386 inst
.instruction
|= inst
.operands
[1].reg
;
9387 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9390 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9391 the same for both ARM and Thumb-2. */
9398 if (inst
.operands
[0].present
)
9400 reg
= inst
.operands
[0].reg
;
9401 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9406 inst
.instruction
|= reg
<< 16;
9407 inst
.instruction
|= inst
.operands
[1].imm
;
9408 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9409 inst
.instruction
|= WRITE_BACK
;
9412 /* ARM V6 strex (argument parse). */
9417 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9418 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9419 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9420 || inst
.operands
[2].negative
9421 /* See comment in do_ldrex(). */
9422 || (inst
.operands
[2].reg
== REG_PC
),
9425 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9426 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9428 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9429 || inst
.reloc
.exp
.X_add_number
!= 0,
9430 _("offset must be zero in ARM encoding"));
9432 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9433 inst
.instruction
|= inst
.operands
[1].reg
;
9434 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9435 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9441 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9442 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9443 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9444 || inst
.operands
[2].negative
,
9447 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9448 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9456 constraint (inst
.operands
[1].reg
% 2 != 0,
9457 _("even register required"));
9458 constraint (inst
.operands
[2].present
9459 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9460 _("can only store two consecutive registers"));
9461 /* If op 2 were present and equal to PC, this function wouldn't
9462 have been called in the first place. */
9463 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9465 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9466 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9467 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9471 inst
.instruction
|= inst
.operands
[1].reg
;
9472 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9479 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9480 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9488 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9489 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9494 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9495 extends it to 32-bits, and adds the result to a value in another
9496 register. You can specify a rotation by 0, 8, 16, or 24 bits
9497 before extracting the 16-bit value.
9498 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9499 Condition defaults to COND_ALWAYS.
9500 Error if any register uses R15. */
9505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9506 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9507 inst
.instruction
|= inst
.operands
[2].reg
;
9508 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9513 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9514 Condition defaults to COND_ALWAYS.
9515 Error if any register uses R15. */
9520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9521 inst
.instruction
|= inst
.operands
[1].reg
;
9522 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9525 /* VFP instructions. In a logical order: SP variant first, monad
9526 before dyad, arithmetic then move then load/store. */
9529 do_vfp_sp_monadic (void)
9531 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9532 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9536 do_vfp_sp_dyadic (void)
9538 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9539 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9540 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9544 do_vfp_sp_compare_z (void)
9546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9550 do_vfp_dp_sp_cvt (void)
9552 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9553 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9557 do_vfp_sp_dp_cvt (void)
9559 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9560 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9564 do_vfp_reg_from_sp (void)
9566 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9567 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9571 do_vfp_reg2_from_sp2 (void)
9573 constraint (inst
.operands
[2].imm
!= 2,
9574 _("only two consecutive VFP SP registers allowed here"));
9575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9576 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9577 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9581 do_vfp_sp_from_reg (void)
9583 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9584 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9588 do_vfp_sp2_from_reg2 (void)
9590 constraint (inst
.operands
[0].imm
!= 2,
9591 _("only two consecutive VFP SP registers allowed here"));
9592 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9593 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9594 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9598 do_vfp_sp_ldst (void)
9600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9601 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9605 do_vfp_dp_ldst (void)
9607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9608 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9613 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9615 if (inst
.operands
[0].writeback
)
9616 inst
.instruction
|= WRITE_BACK
;
9618 constraint (ldstm_type
!= VFP_LDSTMIA
,
9619 _("this addressing mode requires base-register writeback"));
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9621 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9622 inst
.instruction
|= inst
.operands
[1].imm
;
9626 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9630 if (inst
.operands
[0].writeback
)
9631 inst
.instruction
|= WRITE_BACK
;
9633 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9634 _("this addressing mode requires base-register writeback"));
9636 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9637 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9639 count
= inst
.operands
[1].imm
<< 1;
9640 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9643 inst
.instruction
|= count
;
9647 do_vfp_sp_ldstmia (void)
9649 vfp_sp_ldstm (VFP_LDSTMIA
);
9653 do_vfp_sp_ldstmdb (void)
9655 vfp_sp_ldstm (VFP_LDSTMDB
);
9659 do_vfp_dp_ldstmia (void)
9661 vfp_dp_ldstm (VFP_LDSTMIA
);
9665 do_vfp_dp_ldstmdb (void)
9667 vfp_dp_ldstm (VFP_LDSTMDB
);
9671 do_vfp_xp_ldstmia (void)
9673 vfp_dp_ldstm (VFP_LDSTMIAX
);
9677 do_vfp_xp_ldstmdb (void)
9679 vfp_dp_ldstm (VFP_LDSTMDBX
);
9683 do_vfp_dp_rd_rm (void)
9685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9690 do_vfp_dp_rn_rd (void)
9692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9697 do_vfp_dp_rd_rn (void)
9699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9700 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9704 do_vfp_dp_rd_rn_rm (void)
9706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9707 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9708 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9714 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9718 do_vfp_dp_rm_rd_rn (void)
9720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9721 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9722 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9725 /* VFPv3 instructions. */
9727 do_vfp_sp_const (void)
9729 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9730 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9731 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9735 do_vfp_dp_const (void)
9737 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9738 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9739 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9743 vfp_conv (int srcsize
)
9745 int immbits
= srcsize
- inst
.operands
[1].imm
;
9747 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9749 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9750 i.e. immbits must be in range 0 - 16. */
9751 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9754 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9756 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9757 i.e. immbits must be in range 0 - 31. */
9758 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9762 inst
.instruction
|= (immbits
& 1) << 5;
9763 inst
.instruction
|= (immbits
>> 1);
9767 do_vfp_sp_conv_16 (void)
9769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9774 do_vfp_dp_conv_16 (void)
9776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9781 do_vfp_sp_conv_32 (void)
9783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9788 do_vfp_dp_conv_32 (void)
9790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9794 /* FPA instructions. Also in a logical order. */
9799 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9800 inst
.instruction
|= inst
.operands
[1].reg
;
9804 do_fpa_ldmstm (void)
9806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9807 switch (inst
.operands
[1].imm
)
9809 case 1: inst
.instruction
|= CP_T_X
; break;
9810 case 2: inst
.instruction
|= CP_T_Y
; break;
9811 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9816 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9818 /* The instruction specified "ea" or "fd", so we can only accept
9819 [Rn]{!}. The instruction does not really support stacking or
9820 unstacking, so we have to emulate these by setting appropriate
9821 bits and offsets. */
9822 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9823 || inst
.reloc
.exp
.X_add_number
!= 0,
9824 _("this instruction does not support indexing"));
9826 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9827 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9829 if (!(inst
.instruction
& INDEX_UP
))
9830 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9832 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9834 inst
.operands
[2].preind
= 0;
9835 inst
.operands
[2].postind
= 1;
9839 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9842 /* iWMMXt instructions: strictly in alphabetical order. */
9845 do_iwmmxt_tandorc (void)
9847 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9851 do_iwmmxt_textrc (void)
9853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9854 inst
.instruction
|= inst
.operands
[1].imm
;
9858 do_iwmmxt_textrm (void)
9860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9861 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9862 inst
.instruction
|= inst
.operands
[2].imm
;
9866 do_iwmmxt_tinsr (void)
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9869 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9870 inst
.instruction
|= inst
.operands
[2].imm
;
9874 do_iwmmxt_tmia (void)
9876 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9877 inst
.instruction
|= inst
.operands
[1].reg
;
9878 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9882 do_iwmmxt_waligni (void)
9884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9885 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9886 inst
.instruction
|= inst
.operands
[2].reg
;
9887 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9891 do_iwmmxt_wmerge (void)
9893 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9894 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9895 inst
.instruction
|= inst
.operands
[2].reg
;
9896 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9900 do_iwmmxt_wmov (void)
9902 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9904 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9905 inst
.instruction
|= inst
.operands
[1].reg
;
9909 do_iwmmxt_wldstbh (void)
9912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9914 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9916 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9917 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9921 do_iwmmxt_wldstw (void)
9923 /* RIWR_RIWC clears .isreg for a control register. */
9924 if (!inst
.operands
[0].isreg
)
9926 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9927 inst
.instruction
|= 0xf0000000;
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9931 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9935 do_iwmmxt_wldstd (void)
9937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9938 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9939 && inst
.operands
[1].immisreg
)
9941 inst
.instruction
&= ~0x1a000ff;
9942 inst
.instruction
|= (0xfU
<< 28);
9943 if (inst
.operands
[1].preind
)
9944 inst
.instruction
|= PRE_INDEX
;
9945 if (!inst
.operands
[1].negative
)
9946 inst
.instruction
|= INDEX_UP
;
9947 if (inst
.operands
[1].writeback
)
9948 inst
.instruction
|= WRITE_BACK
;
9949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9950 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9951 inst
.instruction
|= inst
.operands
[1].imm
;
9954 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9958 do_iwmmxt_wshufh (void)
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9961 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9962 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9963 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9967 do_iwmmxt_wzero (void)
9969 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9970 inst
.instruction
|= inst
.operands
[0].reg
;
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9976 do_iwmmxt_wrwrwr_or_imm5 (void)
9978 if (inst
.operands
[2].isreg
)
9981 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9982 _("immediate operand requires iWMMXt2"));
9984 if (inst
.operands
[2].imm
== 0)
9986 switch ((inst
.instruction
>> 20) & 0xf)
9992 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9993 inst
.operands
[2].imm
= 16;
9994 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10000 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10001 inst
.operands
[2].imm
= 32;
10002 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10009 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10011 wrn
= (inst
.instruction
>> 16) & 0xf;
10012 inst
.instruction
&= 0xff0fff0f;
10013 inst
.instruction
|= wrn
;
10014 /* Bail out here; the instruction is now assembled. */
10019 /* Map 32 -> 0, etc. */
10020 inst
.operands
[2].imm
&= 0x1f;
10021 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10025 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10026 operations first, then control, shift, and load/store. */
10028 /* Insns like "foo X,Y,Z". */
10031 do_mav_triple (void)
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10034 inst
.instruction
|= inst
.operands
[1].reg
;
10035 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10038 /* Insns like "foo W,X,Y,Z".
10039 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10045 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10046 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10047 inst
.instruction
|= inst
.operands
[3].reg
;
10050 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10052 do_mav_dspsc (void)
10054 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10057 /* Maverick shift immediate instructions.
10058 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10059 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10062 do_mav_shift (void)
10064 int imm
= inst
.operands
[2].imm
;
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10067 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10069 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10070 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10071 Bit 4 should be 0. */
10072 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10074 inst
.instruction
|= imm
;
10077 /* XScale instructions. Also sorted arithmetic before move. */
10079 /* Xscale multiply-accumulate (argument parse)
10082 MIAxycc acc0,Rm,Rs. */
10087 inst
.instruction
|= inst
.operands
[1].reg
;
10088 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10091 /* Xscale move-accumulator-register (argument parse)
10093 MARcc acc0,RdLo,RdHi. */
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10099 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10102 /* Xscale move-register-accumulator (argument parse)
10104 MRAcc RdLo,RdHi,acc0. */
10109 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10111 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10114 /* Encoding functions relevant only to Thumb. */
10116 /* inst.operands[i] is a shifted-register operand; encode
10117 it into inst.instruction in the format used by Thumb32. */
10120 encode_thumb32_shifted_operand (int i
)
10122 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10123 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10125 constraint (inst
.operands
[i
].immisreg
,
10126 _("shift by register not allowed in thumb mode"));
10127 inst
.instruction
|= inst
.operands
[i
].reg
;
10128 if (shift
== SHIFT_RRX
)
10129 inst
.instruction
|= SHIFT_ROR
<< 4;
10132 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10133 _("expression too complex"));
10135 constraint (value
> 32
10136 || (value
== 32 && (shift
== SHIFT_LSL
10137 || shift
== SHIFT_ROR
)),
10138 _("shift expression is too large"));
10142 else if (value
== 32)
10145 inst
.instruction
|= shift
<< 4;
10146 inst
.instruction
|= (value
& 0x1c) << 10;
10147 inst
.instruction
|= (value
& 0x03) << 6;
10152 /* inst.operands[i] was set up by parse_address. Encode it into a
10153 Thumb32 format load or store instruction. Reject forms that cannot
10154 be used with such instructions. If is_t is true, reject forms that
10155 cannot be used with a T instruction; if is_d is true, reject forms
10156 that cannot be used with a D instruction. If it is a store insn,
10157 reject PC in Rn. */
10160 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10162 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10164 constraint (!inst
.operands
[i
].isreg
,
10165 _("Instruction does not support =N addresses"));
10167 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10168 if (inst
.operands
[i
].immisreg
)
10170 constraint (is_pc
, BAD_PC_ADDRESSING
);
10171 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10172 constraint (inst
.operands
[i
].negative
,
10173 _("Thumb does not support negative register indexing"));
10174 constraint (inst
.operands
[i
].postind
,
10175 _("Thumb does not support register post-indexing"));
10176 constraint (inst
.operands
[i
].writeback
,
10177 _("Thumb does not support register indexing with writeback"));
10178 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10179 _("Thumb supports only LSL in shifted register indexing"));
10181 inst
.instruction
|= inst
.operands
[i
].imm
;
10182 if (inst
.operands
[i
].shifted
)
10184 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10185 _("expression too complex"));
10186 constraint (inst
.reloc
.exp
.X_add_number
< 0
10187 || inst
.reloc
.exp
.X_add_number
> 3,
10188 _("shift out of range"));
10189 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10191 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10193 else if (inst
.operands
[i
].preind
)
10195 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10196 constraint (is_t
&& inst
.operands
[i
].writeback
,
10197 _("cannot use writeback with this instruction"));
10198 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10199 BAD_PC_ADDRESSING
);
10203 inst
.instruction
|= 0x01000000;
10204 if (inst
.operands
[i
].writeback
)
10205 inst
.instruction
|= 0x00200000;
10209 inst
.instruction
|= 0x00000c00;
10210 if (inst
.operands
[i
].writeback
)
10211 inst
.instruction
|= 0x00000100;
10213 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10215 else if (inst
.operands
[i
].postind
)
10217 gas_assert (inst
.operands
[i
].writeback
);
10218 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10219 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10222 inst
.instruction
|= 0x00200000;
10224 inst
.instruction
|= 0x00000900;
10225 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10227 else /* unindexed - only for coprocessor */
10228 inst
.error
= _("instruction does not accept unindexed addressing");
10231 /* Table of Thumb instructions which exist in both 16- and 32-bit
10232 encodings (the latter only in post-V6T2 cores). The index is the
10233 value used in the insns table below. When there is more than one
10234 possible 16-bit encoding for the instruction, this table always
10236 Also contains several pseudo-instructions used during relaxation. */
10237 #define T16_32_TAB \
10238 X(_adc, 4140, eb400000), \
10239 X(_adcs, 4140, eb500000), \
10240 X(_add, 1c00, eb000000), \
10241 X(_adds, 1c00, eb100000), \
10242 X(_addi, 0000, f1000000), \
10243 X(_addis, 0000, f1100000), \
10244 X(_add_pc,000f, f20f0000), \
10245 X(_add_sp,000d, f10d0000), \
10246 X(_adr, 000f, f20f0000), \
10247 X(_and, 4000, ea000000), \
10248 X(_ands, 4000, ea100000), \
10249 X(_asr, 1000, fa40f000), \
10250 X(_asrs, 1000, fa50f000), \
10251 X(_b, e000, f000b000), \
10252 X(_bcond, d000, f0008000), \
10253 X(_bic, 4380, ea200000), \
10254 X(_bics, 4380, ea300000), \
10255 X(_cmn, 42c0, eb100f00), \
10256 X(_cmp, 2800, ebb00f00), \
10257 X(_cpsie, b660, f3af8400), \
10258 X(_cpsid, b670, f3af8600), \
10259 X(_cpy, 4600, ea4f0000), \
10260 X(_dec_sp,80dd, f1ad0d00), \
10261 X(_eor, 4040, ea800000), \
10262 X(_eors, 4040, ea900000), \
10263 X(_inc_sp,00dd, f10d0d00), \
10264 X(_ldmia, c800, e8900000), \
10265 X(_ldr, 6800, f8500000), \
10266 X(_ldrb, 7800, f8100000), \
10267 X(_ldrh, 8800, f8300000), \
10268 X(_ldrsb, 5600, f9100000), \
10269 X(_ldrsh, 5e00, f9300000), \
10270 X(_ldr_pc,4800, f85f0000), \
10271 X(_ldr_pc2,4800, f85f0000), \
10272 X(_ldr_sp,9800, f85d0000), \
10273 X(_lsl, 0000, fa00f000), \
10274 X(_lsls, 0000, fa10f000), \
10275 X(_lsr, 0800, fa20f000), \
10276 X(_lsrs, 0800, fa30f000), \
10277 X(_mov, 2000, ea4f0000), \
10278 X(_movs, 2000, ea5f0000), \
10279 X(_mul, 4340, fb00f000), \
10280 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10281 X(_mvn, 43c0, ea6f0000), \
10282 X(_mvns, 43c0, ea7f0000), \
10283 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10284 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10285 X(_orr, 4300, ea400000), \
10286 X(_orrs, 4300, ea500000), \
10287 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10288 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10289 X(_rev, ba00, fa90f080), \
10290 X(_rev16, ba40, fa90f090), \
10291 X(_revsh, bac0, fa90f0b0), \
10292 X(_ror, 41c0, fa60f000), \
10293 X(_rors, 41c0, fa70f000), \
10294 X(_sbc, 4180, eb600000), \
10295 X(_sbcs, 4180, eb700000), \
10296 X(_stmia, c000, e8800000), \
10297 X(_str, 6000, f8400000), \
10298 X(_strb, 7000, f8000000), \
10299 X(_strh, 8000, f8200000), \
10300 X(_str_sp,9000, f84d0000), \
10301 X(_sub, 1e00, eba00000), \
10302 X(_subs, 1e00, ebb00000), \
10303 X(_subi, 8000, f1a00000), \
10304 X(_subis, 8000, f1b00000), \
10305 X(_sxtb, b240, fa4ff080), \
10306 X(_sxth, b200, fa0ff080), \
10307 X(_tst, 4200, ea100f00), \
10308 X(_uxtb, b2c0, fa5ff080), \
10309 X(_uxth, b280, fa1ff080), \
10310 X(_nop, bf00, f3af8000), \
10311 X(_yield, bf10, f3af8001), \
10312 X(_wfe, bf20, f3af8002), \
10313 X(_wfi, bf30, f3af8003), \
10314 X(_sev, bf40, f3af8004), \
10315 X(_sevl, bf50, f3af8005), \
10316 X(_udf, de00, f7f0a000)
10318 /* To catch errors in encoding functions, the codes are all offset by
10319 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10320 as 16-bit instructions. */
10321 #define X(a,b,c) T_MNEM##a
10322 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10325 #define X(a,b,c) 0x##b
10326 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10327 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10330 #define X(a,b,c) 0x##c
10331 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10332 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10333 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10337 /* Thumb instruction encoders, in alphabetical order. */
10339 /* ADDW or SUBW. */
10342 do_t_add_sub_w (void)
10346 Rd
= inst
.operands
[0].reg
;
10347 Rn
= inst
.operands
[1].reg
;
10349 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10350 is the SP-{plus,minus}-immediate form of the instruction. */
10352 constraint (Rd
== REG_PC
, BAD_PC
);
10354 reject_bad_reg (Rd
);
10356 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10357 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10360 /* Parse an add or subtract instruction. We get here with inst.instruction
10361 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10364 do_t_add_sub (void)
10368 Rd
= inst
.operands
[0].reg
;
10369 Rs
= (inst
.operands
[1].present
10370 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10371 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10374 set_it_insn_type_last ();
10376 if (unified_syntax
)
10379 bfd_boolean narrow
;
10382 flags
= (inst
.instruction
== T_MNEM_adds
10383 || inst
.instruction
== T_MNEM_subs
);
10385 narrow
= !in_it_block ();
10387 narrow
= in_it_block ();
10388 if (!inst
.operands
[2].isreg
)
10392 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10394 add
= (inst
.instruction
== T_MNEM_add
10395 || inst
.instruction
== T_MNEM_adds
);
10397 if (inst
.size_req
!= 4)
10399 /* Attempt to use a narrow opcode, with relaxation if
10401 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10402 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10403 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10404 opcode
= T_MNEM_add_sp
;
10405 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10406 opcode
= T_MNEM_add_pc
;
10407 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10410 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10412 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10416 inst
.instruction
= THUMB_OP16(opcode
);
10417 inst
.instruction
|= (Rd
<< 4) | Rs
;
10418 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10419 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10420 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10421 if (inst
.size_req
!= 2)
10422 inst
.relax
= opcode
;
10425 constraint (inst
.size_req
== 2, BAD_HIREG
);
10427 if (inst
.size_req
== 4
10428 || (inst
.size_req
!= 2 && !opcode
))
10432 constraint (add
, BAD_PC
);
10433 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10434 _("only SUBS PC, LR, #const allowed"));
10435 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10436 _("expression too complex"));
10437 constraint (inst
.reloc
.exp
.X_add_number
< 0
10438 || inst
.reloc
.exp
.X_add_number
> 0xff,
10439 _("immediate value out of range"));
10440 inst
.instruction
= T2_SUBS_PC_LR
10441 | inst
.reloc
.exp
.X_add_number
;
10442 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10445 else if (Rs
== REG_PC
)
10447 /* Always use addw/subw. */
10448 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10449 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10453 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10454 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10457 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10459 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10461 inst
.instruction
|= Rd
<< 8;
10462 inst
.instruction
|= Rs
<< 16;
10467 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10468 unsigned int shift
= inst
.operands
[2].shift_kind
;
10470 Rn
= inst
.operands
[2].reg
;
10471 /* See if we can do this with a 16-bit instruction. */
10472 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10474 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10479 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10480 || inst
.instruction
== T_MNEM_add
)
10482 : T_OPCODE_SUB_R3
);
10483 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10487 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10489 /* Thumb-1 cores (except v6-M) require at least one high
10490 register in a narrow non flag setting add. */
10491 if (Rd
> 7 || Rn
> 7
10492 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10493 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10500 inst
.instruction
= T_OPCODE_ADD_HI
;
10501 inst
.instruction
|= (Rd
& 8) << 4;
10502 inst
.instruction
|= (Rd
& 7);
10503 inst
.instruction
|= Rn
<< 3;
10509 constraint (Rd
== REG_PC
, BAD_PC
);
10510 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10511 constraint (Rs
== REG_PC
, BAD_PC
);
10512 reject_bad_reg (Rn
);
10514 /* If we get here, it can't be done in 16 bits. */
10515 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10516 _("shift must be constant"));
10517 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10518 inst
.instruction
|= Rd
<< 8;
10519 inst
.instruction
|= Rs
<< 16;
10520 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10521 _("shift value over 3 not allowed in thumb mode"));
10522 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10523 _("only LSL shift allowed in thumb mode"));
10524 encode_thumb32_shifted_operand (2);
10529 constraint (inst
.instruction
== T_MNEM_adds
10530 || inst
.instruction
== T_MNEM_subs
,
10533 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10535 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10536 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10539 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10540 ? 0x0000 : 0x8000);
10541 inst
.instruction
|= (Rd
<< 4) | Rs
;
10542 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10546 Rn
= inst
.operands
[2].reg
;
10547 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10549 /* We now have Rd, Rs, and Rn set to registers. */
10550 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10552 /* Can't do this for SUB. */
10553 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10554 inst
.instruction
= T_OPCODE_ADD_HI
;
10555 inst
.instruction
|= (Rd
& 8) << 4;
10556 inst
.instruction
|= (Rd
& 7);
10558 inst
.instruction
|= Rn
<< 3;
10560 inst
.instruction
|= Rs
<< 3;
10562 constraint (1, _("dest must overlap one source register"));
10566 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10567 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10568 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10578 Rd
= inst
.operands
[0].reg
;
10579 reject_bad_reg (Rd
);
10581 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10583 /* Defer to section relaxation. */
10584 inst
.relax
= inst
.instruction
;
10585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10586 inst
.instruction
|= Rd
<< 4;
10588 else if (unified_syntax
&& inst
.size_req
!= 2)
10590 /* Generate a 32-bit opcode. */
10591 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10592 inst
.instruction
|= Rd
<< 8;
10593 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10594 inst
.reloc
.pc_rel
= 1;
10598 /* Generate a 16-bit opcode. */
10599 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10600 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10601 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10602 inst
.reloc
.pc_rel
= 1;
10604 inst
.instruction
|= Rd
<< 4;
10608 /* Arithmetic instructions for which there is just one 16-bit
10609 instruction encoding, and it allows only two low registers.
10610 For maximal compatibility with ARM syntax, we allow three register
10611 operands even when Thumb-32 instructions are not available, as long
10612 as the first two are identical. For instance, both "sbc r0,r1" and
10613 "sbc r0,r0,r1" are allowed. */
10619 Rd
= inst
.operands
[0].reg
;
10620 Rs
= (inst
.operands
[1].present
10621 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10622 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10623 Rn
= inst
.operands
[2].reg
;
10625 reject_bad_reg (Rd
);
10626 reject_bad_reg (Rs
);
10627 if (inst
.operands
[2].isreg
)
10628 reject_bad_reg (Rn
);
10630 if (unified_syntax
)
10632 if (!inst
.operands
[2].isreg
)
10634 /* For an immediate, we always generate a 32-bit opcode;
10635 section relaxation will shrink it later if possible. */
10636 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10637 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10638 inst
.instruction
|= Rd
<< 8;
10639 inst
.instruction
|= Rs
<< 16;
10640 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10644 bfd_boolean narrow
;
10646 /* See if we can do this with a 16-bit instruction. */
10647 if (THUMB_SETS_FLAGS (inst
.instruction
))
10648 narrow
= !in_it_block ();
10650 narrow
= in_it_block ();
10652 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10654 if (inst
.operands
[2].shifted
)
10656 if (inst
.size_req
== 4)
10662 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10663 inst
.instruction
|= Rd
;
10664 inst
.instruction
|= Rn
<< 3;
10668 /* If we get here, it can't be done in 16 bits. */
10669 constraint (inst
.operands
[2].shifted
10670 && inst
.operands
[2].immisreg
,
10671 _("shift must be constant"));
10672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10673 inst
.instruction
|= Rd
<< 8;
10674 inst
.instruction
|= Rs
<< 16;
10675 encode_thumb32_shifted_operand (2);
10680 /* On its face this is a lie - the instruction does set the
10681 flags. However, the only supported mnemonic in this mode
10682 says it doesn't. */
10683 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10685 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10686 _("unshifted register required"));
10687 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10688 constraint (Rd
!= Rs
,
10689 _("dest and source1 must be the same register"));
10691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10692 inst
.instruction
|= Rd
;
10693 inst
.instruction
|= Rn
<< 3;
10697 /* Similarly, but for instructions where the arithmetic operation is
10698 commutative, so we can allow either of them to be different from
10699 the destination operand in a 16-bit instruction. For instance, all
10700 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10707 Rd
= inst
.operands
[0].reg
;
10708 Rs
= (inst
.operands
[1].present
10709 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10710 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10711 Rn
= inst
.operands
[2].reg
;
10713 reject_bad_reg (Rd
);
10714 reject_bad_reg (Rs
);
10715 if (inst
.operands
[2].isreg
)
10716 reject_bad_reg (Rn
);
10718 if (unified_syntax
)
10720 if (!inst
.operands
[2].isreg
)
10722 /* For an immediate, we always generate a 32-bit opcode;
10723 section relaxation will shrink it later if possible. */
10724 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10725 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10726 inst
.instruction
|= Rd
<< 8;
10727 inst
.instruction
|= Rs
<< 16;
10728 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10732 bfd_boolean narrow
;
10734 /* See if we can do this with a 16-bit instruction. */
10735 if (THUMB_SETS_FLAGS (inst
.instruction
))
10736 narrow
= !in_it_block ();
10738 narrow
= in_it_block ();
10740 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10742 if (inst
.operands
[2].shifted
)
10744 if (inst
.size_req
== 4)
10751 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10752 inst
.instruction
|= Rd
;
10753 inst
.instruction
|= Rn
<< 3;
10758 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10759 inst
.instruction
|= Rd
;
10760 inst
.instruction
|= Rs
<< 3;
10765 /* If we get here, it can't be done in 16 bits. */
10766 constraint (inst
.operands
[2].shifted
10767 && inst
.operands
[2].immisreg
,
10768 _("shift must be constant"));
10769 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10770 inst
.instruction
|= Rd
<< 8;
10771 inst
.instruction
|= Rs
<< 16;
10772 encode_thumb32_shifted_operand (2);
10777 /* On its face this is a lie - the instruction does set the
10778 flags. However, the only supported mnemonic in this mode
10779 says it doesn't. */
10780 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10782 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10783 _("unshifted register required"));
10784 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10786 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10787 inst
.instruction
|= Rd
;
10790 inst
.instruction
|= Rn
<< 3;
10792 inst
.instruction
|= Rs
<< 3;
10794 constraint (1, _("dest must overlap one source register"));
10802 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10803 constraint (msb
> 32, _("bit-field extends past end of register"));
10804 /* The instruction encoding stores the LSB and MSB,
10805 not the LSB and width. */
10806 Rd
= inst
.operands
[0].reg
;
10807 reject_bad_reg (Rd
);
10808 inst
.instruction
|= Rd
<< 8;
10809 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10810 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10811 inst
.instruction
|= msb
- 1;
10820 Rd
= inst
.operands
[0].reg
;
10821 reject_bad_reg (Rd
);
10823 /* #0 in second position is alternative syntax for bfc, which is
10824 the same instruction but with REG_PC in the Rm field. */
10825 if (!inst
.operands
[1].isreg
)
10829 Rn
= inst
.operands
[1].reg
;
10830 reject_bad_reg (Rn
);
10833 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10834 constraint (msb
> 32, _("bit-field extends past end of register"));
10835 /* The instruction encoding stores the LSB and MSB,
10836 not the LSB and width. */
10837 inst
.instruction
|= Rd
<< 8;
10838 inst
.instruction
|= Rn
<< 16;
10839 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10840 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10841 inst
.instruction
|= msb
- 1;
10849 Rd
= inst
.operands
[0].reg
;
10850 Rn
= inst
.operands
[1].reg
;
10852 reject_bad_reg (Rd
);
10853 reject_bad_reg (Rn
);
10855 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10856 _("bit-field extends past end of register"));
10857 inst
.instruction
|= Rd
<< 8;
10858 inst
.instruction
|= Rn
<< 16;
10859 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10860 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10861 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10864 /* ARM V5 Thumb BLX (argument parse)
10865 BLX <target_addr> which is BLX(1)
10866 BLX <Rm> which is BLX(2)
10867 Unfortunately, there are two different opcodes for this mnemonic.
10868 So, the insns[].value is not used, and the code here zaps values
10869 into inst.instruction.
10871 ??? How to take advantage of the additional two bits of displacement
10872 available in Thumb32 mode? Need new relocation? */
10877 set_it_insn_type_last ();
10879 if (inst
.operands
[0].isreg
)
10881 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10882 /* We have a register, so this is BLX(2). */
10883 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10887 /* No register. This must be BLX(1). */
10888 inst
.instruction
= 0xf000e800;
10889 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10901 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10903 if (in_it_block ())
10905 /* Conditional branches inside IT blocks are encoded as unconditional
10907 cond
= COND_ALWAYS
;
10912 if (cond
!= COND_ALWAYS
)
10913 opcode
= T_MNEM_bcond
;
10915 opcode
= inst
.instruction
;
10918 && (inst
.size_req
== 4
10919 || (inst
.size_req
!= 2
10920 && (inst
.operands
[0].hasreloc
10921 || inst
.reloc
.exp
.X_op
== O_constant
))))
10923 inst
.instruction
= THUMB_OP32(opcode
);
10924 if (cond
== COND_ALWAYS
)
10925 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10928 gas_assert (cond
!= 0xF);
10929 inst
.instruction
|= cond
<< 22;
10930 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10935 inst
.instruction
= THUMB_OP16(opcode
);
10936 if (cond
== COND_ALWAYS
)
10937 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10940 inst
.instruction
|= cond
<< 8;
10941 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10943 /* Allow section relaxation. */
10944 if (unified_syntax
&& inst
.size_req
!= 2)
10945 inst
.relax
= opcode
;
10947 inst
.reloc
.type
= reloc
;
10948 inst
.reloc
.pc_rel
= 1;
10951 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10952 between the two is the maximum immediate allowed - which is passed in
10955 do_t_bkpt_hlt1 (int range
)
10957 constraint (inst
.cond
!= COND_ALWAYS
,
10958 _("instruction is always unconditional"));
10959 if (inst
.operands
[0].present
)
10961 constraint (inst
.operands
[0].imm
> range
,
10962 _("immediate value out of range"));
10963 inst
.instruction
|= inst
.operands
[0].imm
;
10966 set_it_insn_type (NEUTRAL_IT_INSN
);
10972 do_t_bkpt_hlt1 (63);
10978 do_t_bkpt_hlt1 (255);
10982 do_t_branch23 (void)
10984 set_it_insn_type_last ();
10985 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10987 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10988 this file. We used to simply ignore the PLT reloc type here --
10989 the branch encoding is now needed to deal with TLSCALL relocs.
10990 So if we see a PLT reloc now, put it back to how it used to be to
10991 keep the preexisting behaviour. */
10992 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10993 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10995 #if defined(OBJ_COFF)
10996 /* If the destination of the branch is a defined symbol which does not have
10997 the THUMB_FUNC attribute, then we must be calling a function which has
10998 the (interfacearm) attribute. We look for the Thumb entry point to that
10999 function and change the branch to refer to that function instead. */
11000 if ( inst
.reloc
.exp
.X_op
== O_symbol
11001 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11002 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11003 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11004 inst
.reloc
.exp
.X_add_symbol
=
11005 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11012 set_it_insn_type_last ();
11013 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11014 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11015 should cause the alignment to be checked once it is known. This is
11016 because BX PC only works if the instruction is word aligned. */
11024 set_it_insn_type_last ();
11025 Rm
= inst
.operands
[0].reg
;
11026 reject_bad_reg (Rm
);
11027 inst
.instruction
|= Rm
<< 16;
11036 Rd
= inst
.operands
[0].reg
;
11037 Rm
= inst
.operands
[1].reg
;
11039 reject_bad_reg (Rd
);
11040 reject_bad_reg (Rm
);
11042 inst
.instruction
|= Rd
<< 8;
11043 inst
.instruction
|= Rm
<< 16;
11044 inst
.instruction
|= Rm
;
11050 set_it_insn_type (OUTSIDE_IT_INSN
);
11051 inst
.instruction
|= inst
.operands
[0].imm
;
11057 set_it_insn_type (OUTSIDE_IT_INSN
);
11059 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11060 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11062 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11063 inst
.instruction
= 0xf3af8000;
11064 inst
.instruction
|= imod
<< 9;
11065 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11066 if (inst
.operands
[1].present
)
11067 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11071 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11072 && (inst
.operands
[0].imm
& 4),
11073 _("selected processor does not support 'A' form "
11074 "of this instruction"));
11075 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11076 _("Thumb does not support the 2-argument "
11077 "form of this instruction"));
11078 inst
.instruction
|= inst
.operands
[0].imm
;
11082 /* THUMB CPY instruction (argument parse). */
11087 if (inst
.size_req
== 4)
11089 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11090 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11091 inst
.instruction
|= inst
.operands
[1].reg
;
11095 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11096 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11097 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11104 set_it_insn_type (OUTSIDE_IT_INSN
);
11105 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11106 inst
.instruction
|= inst
.operands
[0].reg
;
11107 inst
.reloc
.pc_rel
= 1;
11108 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11114 inst
.instruction
|= inst
.operands
[0].imm
;
11120 unsigned Rd
, Rn
, Rm
;
11122 Rd
= inst
.operands
[0].reg
;
11123 Rn
= (inst
.operands
[1].present
11124 ? inst
.operands
[1].reg
: Rd
);
11125 Rm
= inst
.operands
[2].reg
;
11127 reject_bad_reg (Rd
);
11128 reject_bad_reg (Rn
);
11129 reject_bad_reg (Rm
);
11131 inst
.instruction
|= Rd
<< 8;
11132 inst
.instruction
|= Rn
<< 16;
11133 inst
.instruction
|= Rm
;
11139 if (unified_syntax
&& inst
.size_req
== 4)
11140 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11142 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11148 unsigned int cond
= inst
.operands
[0].imm
;
11150 set_it_insn_type (IT_INSN
);
11151 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11153 now_it
.warn_deprecated
= FALSE
;
11155 /* If the condition is a negative condition, invert the mask. */
11156 if ((cond
& 0x1) == 0x0)
11158 unsigned int mask
= inst
.instruction
& 0x000f;
11160 if ((mask
& 0x7) == 0)
11162 /* No conversion needed. */
11163 now_it
.block_length
= 1;
11165 else if ((mask
& 0x3) == 0)
11168 now_it
.block_length
= 2;
11170 else if ((mask
& 0x1) == 0)
11173 now_it
.block_length
= 3;
11178 now_it
.block_length
= 4;
11181 inst
.instruction
&= 0xfff0;
11182 inst
.instruction
|= mask
;
11185 inst
.instruction
|= cond
<< 4;
11188 /* Helper function used for both push/pop and ldm/stm. */
11190 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11194 load
= (inst
.instruction
& (1 << 20)) != 0;
11196 if (mask
& (1 << 13))
11197 inst
.error
= _("SP not allowed in register list");
11199 if ((mask
& (1 << base
)) != 0
11201 inst
.error
= _("having the base register in the register list when "
11202 "using write back is UNPREDICTABLE");
11206 if (mask
& (1 << 15))
11208 if (mask
& (1 << 14))
11209 inst
.error
= _("LR and PC should not both be in register list");
11211 set_it_insn_type_last ();
11216 if (mask
& (1 << 15))
11217 inst
.error
= _("PC not allowed in register list");
11220 if ((mask
& (mask
- 1)) == 0)
11222 /* Single register transfers implemented as str/ldr. */
11225 if (inst
.instruction
& (1 << 23))
11226 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11228 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11232 if (inst
.instruction
& (1 << 23))
11233 inst
.instruction
= 0x00800000; /* ia -> [base] */
11235 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11238 inst
.instruction
|= 0xf8400000;
11240 inst
.instruction
|= 0x00100000;
11242 mask
= ffs (mask
) - 1;
11245 else if (writeback
)
11246 inst
.instruction
|= WRITE_BACK
;
11248 inst
.instruction
|= mask
;
11249 inst
.instruction
|= base
<< 16;
11255 /* This really doesn't seem worth it. */
11256 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11257 _("expression too complex"));
11258 constraint (inst
.operands
[1].writeback
,
11259 _("Thumb load/store multiple does not support {reglist}^"));
11261 if (unified_syntax
)
11263 bfd_boolean narrow
;
11267 /* See if we can use a 16-bit instruction. */
11268 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11269 && inst
.size_req
!= 4
11270 && !(inst
.operands
[1].imm
& ~0xff))
11272 mask
= 1 << inst
.operands
[0].reg
;
11274 if (inst
.operands
[0].reg
<= 7)
11276 if (inst
.instruction
== T_MNEM_stmia
11277 ? inst
.operands
[0].writeback
11278 : (inst
.operands
[0].writeback
11279 == !(inst
.operands
[1].imm
& mask
)))
11281 if (inst
.instruction
== T_MNEM_stmia
11282 && (inst
.operands
[1].imm
& mask
)
11283 && (inst
.operands
[1].imm
& (mask
- 1)))
11284 as_warn (_("value stored for r%d is UNKNOWN"),
11285 inst
.operands
[0].reg
);
11287 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11288 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11289 inst
.instruction
|= inst
.operands
[1].imm
;
11292 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11294 /* This means 1 register in reg list one of 3 situations:
11295 1. Instruction is stmia, but without writeback.
11296 2. lmdia without writeback, but with Rn not in
11298 3. ldmia with writeback, but with Rn in reglist.
11299 Case 3 is UNPREDICTABLE behaviour, so we handle
11300 case 1 and 2 which can be converted into a 16-bit
11301 str or ldr. The SP cases are handled below. */
11302 unsigned long opcode
;
11303 /* First, record an error for Case 3. */
11304 if (inst
.operands
[1].imm
& mask
11305 && inst
.operands
[0].writeback
)
11307 _("having the base register in the register list when "
11308 "using write back is UNPREDICTABLE");
11310 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11312 inst
.instruction
= THUMB_OP16 (opcode
);
11313 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11314 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11318 else if (inst
.operands
[0] .reg
== REG_SP
)
11320 if (inst
.operands
[0].writeback
)
11323 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11324 ? T_MNEM_push
: T_MNEM_pop
);
11325 inst
.instruction
|= inst
.operands
[1].imm
;
11328 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11331 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11332 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11333 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11341 if (inst
.instruction
< 0xffff)
11342 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11344 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11345 inst
.operands
[0].writeback
);
11350 constraint (inst
.operands
[0].reg
> 7
11351 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11352 constraint (inst
.instruction
!= T_MNEM_ldmia
11353 && inst
.instruction
!= T_MNEM_stmia
,
11354 _("Thumb-2 instruction only valid in unified syntax"));
11355 if (inst
.instruction
== T_MNEM_stmia
)
11357 if (!inst
.operands
[0].writeback
)
11358 as_warn (_("this instruction will write back the base register"));
11359 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11360 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11361 as_warn (_("value stored for r%d is UNKNOWN"),
11362 inst
.operands
[0].reg
);
11366 if (!inst
.operands
[0].writeback
11367 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11368 as_warn (_("this instruction will write back the base register"));
11369 else if (inst
.operands
[0].writeback
11370 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11371 as_warn (_("this instruction will not write back the base register"));
11374 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11375 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11376 inst
.instruction
|= inst
.operands
[1].imm
;
11383 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11384 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11385 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11386 || inst
.operands
[1].negative
,
11389 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11392 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11393 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11399 if (!inst
.operands
[1].present
)
11401 constraint (inst
.operands
[0].reg
== REG_LR
,
11402 _("r14 not allowed as first register "
11403 "when second register is omitted"));
11404 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11406 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11409 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11410 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11411 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11417 unsigned long opcode
;
11420 if (inst
.operands
[0].isreg
11421 && !inst
.operands
[0].preind
11422 && inst
.operands
[0].reg
== REG_PC
)
11423 set_it_insn_type_last ();
11425 opcode
= inst
.instruction
;
11426 if (unified_syntax
)
11428 if (!inst
.operands
[1].isreg
)
11430 if (opcode
<= 0xffff)
11431 inst
.instruction
= THUMB_OP32 (opcode
);
11432 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11435 if (inst
.operands
[1].isreg
11436 && !inst
.operands
[1].writeback
11437 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11438 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11439 && opcode
<= 0xffff
11440 && inst
.size_req
!= 4)
11442 /* Insn may have a 16-bit form. */
11443 Rn
= inst
.operands
[1].reg
;
11444 if (inst
.operands
[1].immisreg
)
11446 inst
.instruction
= THUMB_OP16 (opcode
);
11448 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11450 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11451 reject_bad_reg (inst
.operands
[1].imm
);
11453 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11454 && opcode
!= T_MNEM_ldrsb
)
11455 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11456 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11463 if (inst
.reloc
.pc_rel
)
11464 opcode
= T_MNEM_ldr_pc2
;
11466 opcode
= T_MNEM_ldr_pc
;
11470 if (opcode
== T_MNEM_ldr
)
11471 opcode
= T_MNEM_ldr_sp
;
11473 opcode
= T_MNEM_str_sp
;
11475 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11479 inst
.instruction
= inst
.operands
[0].reg
;
11480 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11482 inst
.instruction
|= THUMB_OP16 (opcode
);
11483 if (inst
.size_req
== 2)
11484 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11486 inst
.relax
= opcode
;
11490 /* Definitely a 32-bit variant. */
11492 /* Warning for Erratum 752419. */
11493 if (opcode
== T_MNEM_ldr
11494 && inst
.operands
[0].reg
== REG_SP
11495 && inst
.operands
[1].writeback
== 1
11496 && !inst
.operands
[1].immisreg
)
11498 if (no_cpu_selected ()
11499 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11500 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11501 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11502 as_warn (_("This instruction may be unpredictable "
11503 "if executed on M-profile cores "
11504 "with interrupts enabled."));
11507 /* Do some validations regarding addressing modes. */
11508 if (inst
.operands
[1].immisreg
)
11509 reject_bad_reg (inst
.operands
[1].imm
);
11511 constraint (inst
.operands
[1].writeback
== 1
11512 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11515 inst
.instruction
= THUMB_OP32 (opcode
);
11516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11517 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11518 check_ldr_r15_aligned ();
11522 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11524 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11526 /* Only [Rn,Rm] is acceptable. */
11527 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11528 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11529 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11530 || inst
.operands
[1].negative
,
11531 _("Thumb does not support this addressing mode"));
11532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11536 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11537 if (!inst
.operands
[1].isreg
)
11538 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11541 constraint (!inst
.operands
[1].preind
11542 || inst
.operands
[1].shifted
11543 || inst
.operands
[1].writeback
,
11544 _("Thumb does not support this addressing mode"));
11545 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11547 constraint (inst
.instruction
& 0x0600,
11548 _("byte or halfword not valid for base register"));
11549 constraint (inst
.operands
[1].reg
== REG_PC
11550 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11551 _("r15 based store not allowed"));
11552 constraint (inst
.operands
[1].immisreg
,
11553 _("invalid base register for register offset"));
11555 if (inst
.operands
[1].reg
== REG_PC
)
11556 inst
.instruction
= T_OPCODE_LDR_PC
;
11557 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11558 inst
.instruction
= T_OPCODE_LDR_SP
;
11560 inst
.instruction
= T_OPCODE_STR_SP
;
11562 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11563 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11567 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11568 if (!inst
.operands
[1].immisreg
)
11570 /* Immediate offset. */
11571 inst
.instruction
|= inst
.operands
[0].reg
;
11572 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11573 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11577 /* Register offset. */
11578 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11579 constraint (inst
.operands
[1].negative
,
11580 _("Thumb does not support this addressing mode"));
11583 switch (inst
.instruction
)
11585 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11586 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11587 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11588 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11589 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11590 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11591 case 0x5600 /* ldrsb */:
11592 case 0x5e00 /* ldrsh */: break;
11596 inst
.instruction
|= inst
.operands
[0].reg
;
11597 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11598 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11604 if (!inst
.operands
[1].present
)
11606 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11607 constraint (inst
.operands
[0].reg
== REG_LR
,
11608 _("r14 not allowed here"));
11609 constraint (inst
.operands
[0].reg
== REG_R12
,
11610 _("r12 not allowed here"));
11613 if (inst
.operands
[2].writeback
11614 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11615 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11616 as_warn (_("base register written back, and overlaps "
11617 "one of transfer registers"));
11619 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11620 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11621 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11627 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11628 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11634 unsigned Rd
, Rn
, Rm
, Ra
;
11636 Rd
= inst
.operands
[0].reg
;
11637 Rn
= inst
.operands
[1].reg
;
11638 Rm
= inst
.operands
[2].reg
;
11639 Ra
= inst
.operands
[3].reg
;
11641 reject_bad_reg (Rd
);
11642 reject_bad_reg (Rn
);
11643 reject_bad_reg (Rm
);
11644 reject_bad_reg (Ra
);
11646 inst
.instruction
|= Rd
<< 8;
11647 inst
.instruction
|= Rn
<< 16;
11648 inst
.instruction
|= Rm
;
11649 inst
.instruction
|= Ra
<< 12;
11655 unsigned RdLo
, RdHi
, Rn
, Rm
;
11657 RdLo
= inst
.operands
[0].reg
;
11658 RdHi
= inst
.operands
[1].reg
;
11659 Rn
= inst
.operands
[2].reg
;
11660 Rm
= inst
.operands
[3].reg
;
11662 reject_bad_reg (RdLo
);
11663 reject_bad_reg (RdHi
);
11664 reject_bad_reg (Rn
);
11665 reject_bad_reg (Rm
);
11667 inst
.instruction
|= RdLo
<< 12;
11668 inst
.instruction
|= RdHi
<< 8;
11669 inst
.instruction
|= Rn
<< 16;
11670 inst
.instruction
|= Rm
;
11674 do_t_mov_cmp (void)
11678 Rn
= inst
.operands
[0].reg
;
11679 Rm
= inst
.operands
[1].reg
;
11682 set_it_insn_type_last ();
11684 if (unified_syntax
)
11686 int r0off
= (inst
.instruction
== T_MNEM_mov
11687 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11688 unsigned long opcode
;
11689 bfd_boolean narrow
;
11690 bfd_boolean low_regs
;
11692 low_regs
= (Rn
<= 7 && Rm
<= 7);
11693 opcode
= inst
.instruction
;
11694 if (in_it_block ())
11695 narrow
= opcode
!= T_MNEM_movs
;
11697 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11698 if (inst
.size_req
== 4
11699 || inst
.operands
[1].shifted
)
11702 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11703 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11704 && !inst
.operands
[1].shifted
11708 inst
.instruction
= T2_SUBS_PC_LR
;
11712 if (opcode
== T_MNEM_cmp
)
11714 constraint (Rn
== REG_PC
, BAD_PC
);
11717 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11719 warn_deprecated_sp (Rm
);
11720 /* R15 was documented as a valid choice for Rm in ARMv6,
11721 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11722 tools reject R15, so we do too. */
11723 constraint (Rm
== REG_PC
, BAD_PC
);
11726 reject_bad_reg (Rm
);
11728 else if (opcode
== T_MNEM_mov
11729 || opcode
== T_MNEM_movs
)
11731 if (inst
.operands
[1].isreg
)
11733 if (opcode
== T_MNEM_movs
)
11735 reject_bad_reg (Rn
);
11736 reject_bad_reg (Rm
);
11740 /* This is mov.n. */
11741 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11742 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11744 as_tsktsk (_("Use of r%u as a source register is "
11745 "deprecated when r%u is the destination "
11746 "register."), Rm
, Rn
);
11751 /* This is mov.w. */
11752 constraint (Rn
== REG_PC
, BAD_PC
);
11753 constraint (Rm
== REG_PC
, BAD_PC
);
11754 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11758 reject_bad_reg (Rn
);
11761 if (!inst
.operands
[1].isreg
)
11763 /* Immediate operand. */
11764 if (!in_it_block () && opcode
== T_MNEM_mov
)
11766 if (low_regs
&& narrow
)
11768 inst
.instruction
= THUMB_OP16 (opcode
);
11769 inst
.instruction
|= Rn
<< 8;
11770 if (inst
.size_req
== 2)
11772 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11773 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11774 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11777 inst
.relax
= opcode
;
11781 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11782 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11783 inst
.instruction
|= Rn
<< r0off
;
11784 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11787 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11788 && (inst
.instruction
== T_MNEM_mov
11789 || inst
.instruction
== T_MNEM_movs
))
11791 /* Register shifts are encoded as separate shift instructions. */
11792 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11794 if (in_it_block ())
11799 if (inst
.size_req
== 4)
11802 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11808 switch (inst
.operands
[1].shift_kind
)
11811 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11814 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11817 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11820 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11826 inst
.instruction
= opcode
;
11829 inst
.instruction
|= Rn
;
11830 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11835 inst
.instruction
|= CONDS_BIT
;
11837 inst
.instruction
|= Rn
<< 8;
11838 inst
.instruction
|= Rm
<< 16;
11839 inst
.instruction
|= inst
.operands
[1].imm
;
11844 /* Some mov with immediate shift have narrow variants.
11845 Register shifts are handled above. */
11846 if (low_regs
&& inst
.operands
[1].shifted
11847 && (inst
.instruction
== T_MNEM_mov
11848 || inst
.instruction
== T_MNEM_movs
))
11850 if (in_it_block ())
11851 narrow
= (inst
.instruction
== T_MNEM_mov
);
11853 narrow
= (inst
.instruction
== T_MNEM_movs
);
11858 switch (inst
.operands
[1].shift_kind
)
11860 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11861 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11862 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11863 default: narrow
= FALSE
; break;
11869 inst
.instruction
|= Rn
;
11870 inst
.instruction
|= Rm
<< 3;
11871 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11875 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11876 inst
.instruction
|= Rn
<< r0off
;
11877 encode_thumb32_shifted_operand (1);
11881 switch (inst
.instruction
)
11884 /* In v4t or v5t a move of two lowregs produces unpredictable
11885 results. Don't allow this. */
11888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11889 "MOV Rd, Rs with two low registers is not "
11890 "permitted on this architecture");
11891 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11895 inst
.instruction
= T_OPCODE_MOV_HR
;
11896 inst
.instruction
|= (Rn
& 0x8) << 4;
11897 inst
.instruction
|= (Rn
& 0x7);
11898 inst
.instruction
|= Rm
<< 3;
11902 /* We know we have low registers at this point.
11903 Generate LSLS Rd, Rs, #0. */
11904 inst
.instruction
= T_OPCODE_LSL_I
;
11905 inst
.instruction
|= Rn
;
11906 inst
.instruction
|= Rm
<< 3;
11912 inst
.instruction
= T_OPCODE_CMP_LR
;
11913 inst
.instruction
|= Rn
;
11914 inst
.instruction
|= Rm
<< 3;
11918 inst
.instruction
= T_OPCODE_CMP_HR
;
11919 inst
.instruction
|= (Rn
& 0x8) << 4;
11920 inst
.instruction
|= (Rn
& 0x7);
11921 inst
.instruction
|= Rm
<< 3;
11928 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11930 /* PR 10443: Do not silently ignore shifted operands. */
11931 constraint (inst
.operands
[1].shifted
,
11932 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11934 if (inst
.operands
[1].isreg
)
11936 if (Rn
< 8 && Rm
< 8)
11938 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11939 since a MOV instruction produces unpredictable results. */
11940 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11941 inst
.instruction
= T_OPCODE_ADD_I3
;
11943 inst
.instruction
= T_OPCODE_CMP_LR
;
11945 inst
.instruction
|= Rn
;
11946 inst
.instruction
|= Rm
<< 3;
11950 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11951 inst
.instruction
= T_OPCODE_MOV_HR
;
11953 inst
.instruction
= T_OPCODE_CMP_HR
;
11959 constraint (Rn
> 7,
11960 _("only lo regs allowed with immediate"));
11961 inst
.instruction
|= Rn
<< 8;
11962 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11973 top
= (inst
.instruction
& 0x00800000) != 0;
11974 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11976 constraint (top
, _(":lower16: not allowed this instruction"));
11977 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11979 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11981 constraint (!top
, _(":upper16: not allowed this instruction"));
11982 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11985 Rd
= inst
.operands
[0].reg
;
11986 reject_bad_reg (Rd
);
11988 inst
.instruction
|= Rd
<< 8;
11989 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11991 imm
= inst
.reloc
.exp
.X_add_number
;
11992 inst
.instruction
|= (imm
& 0xf000) << 4;
11993 inst
.instruction
|= (imm
& 0x0800) << 15;
11994 inst
.instruction
|= (imm
& 0x0700) << 4;
11995 inst
.instruction
|= (imm
& 0x00ff);
12000 do_t_mvn_tst (void)
12004 Rn
= inst
.operands
[0].reg
;
12005 Rm
= inst
.operands
[1].reg
;
12007 if (inst
.instruction
== T_MNEM_cmp
12008 || inst
.instruction
== T_MNEM_cmn
)
12009 constraint (Rn
== REG_PC
, BAD_PC
);
12011 reject_bad_reg (Rn
);
12012 reject_bad_reg (Rm
);
12014 if (unified_syntax
)
12016 int r0off
= (inst
.instruction
== T_MNEM_mvn
12017 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12018 bfd_boolean narrow
;
12020 if (inst
.size_req
== 4
12021 || inst
.instruction
> 0xffff
12022 || inst
.operands
[1].shifted
12023 || Rn
> 7 || Rm
> 7)
12025 else if (inst
.instruction
== T_MNEM_cmn
12026 || inst
.instruction
== T_MNEM_tst
)
12028 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12029 narrow
= !in_it_block ();
12031 narrow
= in_it_block ();
12033 if (!inst
.operands
[1].isreg
)
12035 /* For an immediate, we always generate a 32-bit opcode;
12036 section relaxation will shrink it later if possible. */
12037 if (inst
.instruction
< 0xffff)
12038 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12039 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12040 inst
.instruction
|= Rn
<< r0off
;
12041 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12045 /* See if we can do this with a 16-bit instruction. */
12048 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12049 inst
.instruction
|= Rn
;
12050 inst
.instruction
|= Rm
<< 3;
12054 constraint (inst
.operands
[1].shifted
12055 && inst
.operands
[1].immisreg
,
12056 _("shift must be constant"));
12057 if (inst
.instruction
< 0xffff)
12058 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12059 inst
.instruction
|= Rn
<< r0off
;
12060 encode_thumb32_shifted_operand (1);
12066 constraint (inst
.instruction
> 0xffff
12067 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12068 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12069 _("unshifted register required"));
12070 constraint (Rn
> 7 || Rm
> 7,
12073 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12074 inst
.instruction
|= Rn
;
12075 inst
.instruction
|= Rm
<< 3;
12084 if (do_vfp_nsyn_mrs () == SUCCESS
)
12087 Rd
= inst
.operands
[0].reg
;
12088 reject_bad_reg (Rd
);
12089 inst
.instruction
|= Rd
<< 8;
12091 if (inst
.operands
[1].isreg
)
12093 unsigned br
= inst
.operands
[1].reg
;
12094 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12095 as_bad (_("bad register for mrs"));
12097 inst
.instruction
|= br
& (0xf << 16);
12098 inst
.instruction
|= (br
& 0x300) >> 4;
12099 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12103 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12105 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12107 /* PR gas/12698: The constraint is only applied for m_profile.
12108 If the user has specified -march=all, we want to ignore it as
12109 we are building for any CPU type, including non-m variants. */
12110 bfd_boolean m_profile
=
12111 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12112 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12113 "not support requested special purpose register"));
12116 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12118 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12119 _("'APSR', 'CPSR' or 'SPSR' expected"));
12121 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12122 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12123 inst
.instruction
|= 0xf0000;
12133 if (do_vfp_nsyn_msr () == SUCCESS
)
12136 constraint (!inst
.operands
[1].isreg
,
12137 _("Thumb encoding does not support an immediate here"));
12139 if (inst
.operands
[0].isreg
)
12140 flags
= (int)(inst
.operands
[0].reg
);
12142 flags
= inst
.operands
[0].imm
;
12144 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12146 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12148 /* PR gas/12698: The constraint is only applied for m_profile.
12149 If the user has specified -march=all, we want to ignore it as
12150 we are building for any CPU type, including non-m variants. */
12151 bfd_boolean m_profile
=
12152 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12153 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12154 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12155 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12156 && bits
!= PSR_f
)) && m_profile
,
12157 _("selected processor does not support requested special "
12158 "purpose register"));
12161 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12162 "requested special purpose register"));
12164 Rn
= inst
.operands
[1].reg
;
12165 reject_bad_reg (Rn
);
12167 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12168 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12169 inst
.instruction
|= (flags
& 0x300) >> 4;
12170 inst
.instruction
|= (flags
& 0xff);
12171 inst
.instruction
|= Rn
<< 16;
12177 bfd_boolean narrow
;
12178 unsigned Rd
, Rn
, Rm
;
12180 if (!inst
.operands
[2].present
)
12181 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12183 Rd
= inst
.operands
[0].reg
;
12184 Rn
= inst
.operands
[1].reg
;
12185 Rm
= inst
.operands
[2].reg
;
12187 if (unified_syntax
)
12189 if (inst
.size_req
== 4
12195 else if (inst
.instruction
== T_MNEM_muls
)
12196 narrow
= !in_it_block ();
12198 narrow
= in_it_block ();
12202 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12203 constraint (Rn
> 7 || Rm
> 7,
12210 /* 16-bit MULS/Conditional MUL. */
12211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12212 inst
.instruction
|= Rd
;
12215 inst
.instruction
|= Rm
<< 3;
12217 inst
.instruction
|= Rn
<< 3;
12219 constraint (1, _("dest must overlap one source register"));
12223 constraint (inst
.instruction
!= T_MNEM_mul
,
12224 _("Thumb-2 MUL must not set flags"));
12226 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12227 inst
.instruction
|= Rd
<< 8;
12228 inst
.instruction
|= Rn
<< 16;
12229 inst
.instruction
|= Rm
<< 0;
12231 reject_bad_reg (Rd
);
12232 reject_bad_reg (Rn
);
12233 reject_bad_reg (Rm
);
12240 unsigned RdLo
, RdHi
, Rn
, Rm
;
12242 RdLo
= inst
.operands
[0].reg
;
12243 RdHi
= inst
.operands
[1].reg
;
12244 Rn
= inst
.operands
[2].reg
;
12245 Rm
= inst
.operands
[3].reg
;
12247 reject_bad_reg (RdLo
);
12248 reject_bad_reg (RdHi
);
12249 reject_bad_reg (Rn
);
12250 reject_bad_reg (Rm
);
12252 inst
.instruction
|= RdLo
<< 12;
12253 inst
.instruction
|= RdHi
<< 8;
12254 inst
.instruction
|= Rn
<< 16;
12255 inst
.instruction
|= Rm
;
12258 as_tsktsk (_("rdhi and rdlo must be different"));
12264 set_it_insn_type (NEUTRAL_IT_INSN
);
12266 if (unified_syntax
)
12268 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12270 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12271 inst
.instruction
|= inst
.operands
[0].imm
;
12275 /* PR9722: Check for Thumb2 availability before
12276 generating a thumb2 nop instruction. */
12277 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12279 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12280 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12283 inst
.instruction
= 0x46c0;
12288 constraint (inst
.operands
[0].present
,
12289 _("Thumb does not support NOP with hints"));
12290 inst
.instruction
= 0x46c0;
12297 if (unified_syntax
)
12299 bfd_boolean narrow
;
12301 if (THUMB_SETS_FLAGS (inst
.instruction
))
12302 narrow
= !in_it_block ();
12304 narrow
= in_it_block ();
12305 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12307 if (inst
.size_req
== 4)
12312 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12313 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12314 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12318 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12319 inst
.instruction
|= inst
.operands
[0].reg
;
12320 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12325 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12327 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12330 inst
.instruction
|= inst
.operands
[0].reg
;
12331 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12340 Rd
= inst
.operands
[0].reg
;
12341 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12343 reject_bad_reg (Rd
);
12344 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12345 reject_bad_reg (Rn
);
12347 inst
.instruction
|= Rd
<< 8;
12348 inst
.instruction
|= Rn
<< 16;
12350 if (!inst
.operands
[2].isreg
)
12352 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12353 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12359 Rm
= inst
.operands
[2].reg
;
12360 reject_bad_reg (Rm
);
12362 constraint (inst
.operands
[2].shifted
12363 && inst
.operands
[2].immisreg
,
12364 _("shift must be constant"));
12365 encode_thumb32_shifted_operand (2);
12372 unsigned Rd
, Rn
, Rm
;
12374 Rd
= inst
.operands
[0].reg
;
12375 Rn
= inst
.operands
[1].reg
;
12376 Rm
= inst
.operands
[2].reg
;
12378 reject_bad_reg (Rd
);
12379 reject_bad_reg (Rn
);
12380 reject_bad_reg (Rm
);
12382 inst
.instruction
|= Rd
<< 8;
12383 inst
.instruction
|= Rn
<< 16;
12384 inst
.instruction
|= Rm
;
12385 if (inst
.operands
[3].present
)
12387 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12388 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12389 _("expression too complex"));
12390 inst
.instruction
|= (val
& 0x1c) << 10;
12391 inst
.instruction
|= (val
& 0x03) << 6;
12398 if (!inst
.operands
[3].present
)
12402 inst
.instruction
&= ~0x00000020;
12404 /* PR 10168. Swap the Rm and Rn registers. */
12405 Rtmp
= inst
.operands
[1].reg
;
12406 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12407 inst
.operands
[2].reg
= Rtmp
;
12415 if (inst
.operands
[0].immisreg
)
12416 reject_bad_reg (inst
.operands
[0].imm
);
12418 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12422 do_t_push_pop (void)
12426 constraint (inst
.operands
[0].writeback
,
12427 _("push/pop do not support {reglist}^"));
12428 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12429 _("expression too complex"));
12431 mask
= inst
.operands
[0].imm
;
12432 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12433 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12434 else if (inst
.size_req
!= 4
12435 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12436 ? REG_LR
: REG_PC
)))
12438 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12439 inst
.instruction
|= THUMB_PP_PC_LR
;
12440 inst
.instruction
|= mask
& 0xff;
12442 else if (unified_syntax
)
12444 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12445 encode_thumb2_ldmstm (13, mask
, TRUE
);
12449 inst
.error
= _("invalid register list to push/pop instruction");
12459 Rd
= inst
.operands
[0].reg
;
12460 Rm
= inst
.operands
[1].reg
;
12462 reject_bad_reg (Rd
);
12463 reject_bad_reg (Rm
);
12465 inst
.instruction
|= Rd
<< 8;
12466 inst
.instruction
|= Rm
<< 16;
12467 inst
.instruction
|= Rm
;
12475 Rd
= inst
.operands
[0].reg
;
12476 Rm
= inst
.operands
[1].reg
;
12478 reject_bad_reg (Rd
);
12479 reject_bad_reg (Rm
);
12481 if (Rd
<= 7 && Rm
<= 7
12482 && inst
.size_req
!= 4)
12484 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12485 inst
.instruction
|= Rd
;
12486 inst
.instruction
|= Rm
<< 3;
12488 else if (unified_syntax
)
12490 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12491 inst
.instruction
|= Rd
<< 8;
12492 inst
.instruction
|= Rm
<< 16;
12493 inst
.instruction
|= Rm
;
12496 inst
.error
= BAD_HIREG
;
12504 Rd
= inst
.operands
[0].reg
;
12505 Rm
= inst
.operands
[1].reg
;
12507 reject_bad_reg (Rd
);
12508 reject_bad_reg (Rm
);
12510 inst
.instruction
|= Rd
<< 8;
12511 inst
.instruction
|= Rm
;
12519 Rd
= inst
.operands
[0].reg
;
12520 Rs
= (inst
.operands
[1].present
12521 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12522 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12524 reject_bad_reg (Rd
);
12525 reject_bad_reg (Rs
);
12526 if (inst
.operands
[2].isreg
)
12527 reject_bad_reg (inst
.operands
[2].reg
);
12529 inst
.instruction
|= Rd
<< 8;
12530 inst
.instruction
|= Rs
<< 16;
12531 if (!inst
.operands
[2].isreg
)
12533 bfd_boolean narrow
;
12535 if ((inst
.instruction
& 0x00100000) != 0)
12536 narrow
= !in_it_block ();
12538 narrow
= in_it_block ();
12540 if (Rd
> 7 || Rs
> 7)
12543 if (inst
.size_req
== 4 || !unified_syntax
)
12546 if (inst
.reloc
.exp
.X_op
!= O_constant
12547 || inst
.reloc
.exp
.X_add_number
!= 0)
12550 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12551 relaxation, but it doesn't seem worth the hassle. */
12554 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12555 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12556 inst
.instruction
|= Rs
<< 3;
12557 inst
.instruction
|= Rd
;
12561 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12562 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12566 encode_thumb32_shifted_operand (2);
12572 if (warn_on_deprecated
12573 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12574 as_tsktsk (_("setend use is deprecated for ARMv8"));
12576 set_it_insn_type (OUTSIDE_IT_INSN
);
12577 if (inst
.operands
[0].imm
)
12578 inst
.instruction
|= 0x8;
12584 if (!inst
.operands
[1].present
)
12585 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12587 if (unified_syntax
)
12589 bfd_boolean narrow
;
12592 switch (inst
.instruction
)
12595 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12597 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12599 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12601 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12605 if (THUMB_SETS_FLAGS (inst
.instruction
))
12606 narrow
= !in_it_block ();
12608 narrow
= in_it_block ();
12609 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12611 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12613 if (inst
.operands
[2].isreg
12614 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12615 || inst
.operands
[2].reg
> 7))
12617 if (inst
.size_req
== 4)
12620 reject_bad_reg (inst
.operands
[0].reg
);
12621 reject_bad_reg (inst
.operands
[1].reg
);
12625 if (inst
.operands
[2].isreg
)
12627 reject_bad_reg (inst
.operands
[2].reg
);
12628 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12629 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12631 inst
.instruction
|= inst
.operands
[2].reg
;
12633 /* PR 12854: Error on extraneous shifts. */
12634 constraint (inst
.operands
[2].shifted
,
12635 _("extraneous shift as part of operand to shift insn"));
12639 inst
.operands
[1].shifted
= 1;
12640 inst
.operands
[1].shift_kind
= shift_kind
;
12641 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12642 ? T_MNEM_movs
: T_MNEM_mov
);
12643 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12644 encode_thumb32_shifted_operand (1);
12645 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12646 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12651 if (inst
.operands
[2].isreg
)
12653 switch (shift_kind
)
12655 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12656 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12657 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12658 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12662 inst
.instruction
|= inst
.operands
[0].reg
;
12663 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12665 /* PR 12854: Error on extraneous shifts. */
12666 constraint (inst
.operands
[2].shifted
,
12667 _("extraneous shift as part of operand to shift insn"));
12671 switch (shift_kind
)
12673 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12674 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12675 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12678 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12679 inst
.instruction
|= inst
.operands
[0].reg
;
12680 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12686 constraint (inst
.operands
[0].reg
> 7
12687 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12688 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12690 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12692 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12693 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12694 _("source1 and dest must be same register"));
12696 switch (inst
.instruction
)
12698 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12699 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12700 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12701 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12705 inst
.instruction
|= inst
.operands
[0].reg
;
12706 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12708 /* PR 12854: Error on extraneous shifts. */
12709 constraint (inst
.operands
[2].shifted
,
12710 _("extraneous shift as part of operand to shift insn"));
12714 switch (inst
.instruction
)
12716 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12717 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12718 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12719 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12722 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12723 inst
.instruction
|= inst
.operands
[0].reg
;
12724 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12732 unsigned Rd
, Rn
, Rm
;
12734 Rd
= inst
.operands
[0].reg
;
12735 Rn
= inst
.operands
[1].reg
;
12736 Rm
= inst
.operands
[2].reg
;
12738 reject_bad_reg (Rd
);
12739 reject_bad_reg (Rn
);
12740 reject_bad_reg (Rm
);
12742 inst
.instruction
|= Rd
<< 8;
12743 inst
.instruction
|= Rn
<< 16;
12744 inst
.instruction
|= Rm
;
12750 unsigned Rd
, Rn
, Rm
;
12752 Rd
= inst
.operands
[0].reg
;
12753 Rm
= inst
.operands
[1].reg
;
12754 Rn
= inst
.operands
[2].reg
;
12756 reject_bad_reg (Rd
);
12757 reject_bad_reg (Rn
);
12758 reject_bad_reg (Rm
);
12760 inst
.instruction
|= Rd
<< 8;
12761 inst
.instruction
|= Rn
<< 16;
12762 inst
.instruction
|= Rm
;
12768 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12769 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12770 _("SMC is not permitted on this architecture"));
12771 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12772 _("expression too complex"));
12773 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12774 inst
.instruction
|= (value
& 0xf000) >> 12;
12775 inst
.instruction
|= (value
& 0x0ff0);
12776 inst
.instruction
|= (value
& 0x000f) << 16;
12777 /* PR gas/15623: SMC instructions must be last in an IT block. */
12778 set_it_insn_type_last ();
12784 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12786 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12787 inst
.instruction
|= (value
& 0x0fff);
12788 inst
.instruction
|= (value
& 0xf000) << 4;
12792 do_t_ssat_usat (int bias
)
12796 Rd
= inst
.operands
[0].reg
;
12797 Rn
= inst
.operands
[2].reg
;
12799 reject_bad_reg (Rd
);
12800 reject_bad_reg (Rn
);
12802 inst
.instruction
|= Rd
<< 8;
12803 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12804 inst
.instruction
|= Rn
<< 16;
12806 if (inst
.operands
[3].present
)
12808 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12810 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12812 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12813 _("expression too complex"));
12815 if (shift_amount
!= 0)
12817 constraint (shift_amount
> 31,
12818 _("shift expression is too large"));
12820 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12821 inst
.instruction
|= 0x00200000; /* sh bit. */
12823 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12824 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12832 do_t_ssat_usat (1);
12840 Rd
= inst
.operands
[0].reg
;
12841 Rn
= inst
.operands
[2].reg
;
12843 reject_bad_reg (Rd
);
12844 reject_bad_reg (Rn
);
12846 inst
.instruction
|= Rd
<< 8;
12847 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12848 inst
.instruction
|= Rn
<< 16;
12854 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12855 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12856 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12857 || inst
.operands
[2].negative
,
12860 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12862 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12863 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12864 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12865 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12871 if (!inst
.operands
[2].present
)
12872 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12874 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12875 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12876 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12879 inst
.instruction
|= inst
.operands
[0].reg
;
12880 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12881 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12882 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12888 unsigned Rd
, Rn
, Rm
;
12890 Rd
= inst
.operands
[0].reg
;
12891 Rn
= inst
.operands
[1].reg
;
12892 Rm
= inst
.operands
[2].reg
;
12894 reject_bad_reg (Rd
);
12895 reject_bad_reg (Rn
);
12896 reject_bad_reg (Rm
);
12898 inst
.instruction
|= Rd
<< 8;
12899 inst
.instruction
|= Rn
<< 16;
12900 inst
.instruction
|= Rm
;
12901 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12909 Rd
= inst
.operands
[0].reg
;
12910 Rm
= inst
.operands
[1].reg
;
12912 reject_bad_reg (Rd
);
12913 reject_bad_reg (Rm
);
12915 if (inst
.instruction
<= 0xffff
12916 && inst
.size_req
!= 4
12917 && Rd
<= 7 && Rm
<= 7
12918 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12920 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12921 inst
.instruction
|= Rd
;
12922 inst
.instruction
|= Rm
<< 3;
12924 else if (unified_syntax
)
12926 if (inst
.instruction
<= 0xffff)
12927 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12928 inst
.instruction
|= Rd
<< 8;
12929 inst
.instruction
|= Rm
;
12930 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12934 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12935 _("Thumb encoding does not support rotation"));
12936 constraint (1, BAD_HIREG
);
12943 /* We have to do the following check manually as ARM_EXT_OS only applies
12945 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12947 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12948 /* This only applies to the v6m howver, not later architectures. */
12949 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12950 as_bad (_("SVC is not permitted on this architecture"));
12951 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12954 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12963 half
= (inst
.instruction
& 0x10) != 0;
12964 set_it_insn_type_last ();
12965 constraint (inst
.operands
[0].immisreg
,
12966 _("instruction requires register index"));
12968 Rn
= inst
.operands
[0].reg
;
12969 Rm
= inst
.operands
[0].imm
;
12971 constraint (Rn
== REG_SP
, BAD_SP
);
12972 reject_bad_reg (Rm
);
12974 constraint (!half
&& inst
.operands
[0].shifted
,
12975 _("instruction does not allow shifted index"));
12976 inst
.instruction
|= (Rn
<< 16) | Rm
;
12982 if (!inst
.operands
[0].present
)
12983 inst
.operands
[0].imm
= 0;
12985 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12987 constraint (inst
.size_req
== 2,
12988 _("immediate value out of range"));
12989 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12990 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12991 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12995 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12996 inst
.instruction
|= inst
.operands
[0].imm
;
12999 set_it_insn_type (NEUTRAL_IT_INSN
);
13006 do_t_ssat_usat (0);
13014 Rd
= inst
.operands
[0].reg
;
13015 Rn
= inst
.operands
[2].reg
;
13017 reject_bad_reg (Rd
);
13018 reject_bad_reg (Rn
);
13020 inst
.instruction
|= Rd
<< 8;
13021 inst
.instruction
|= inst
.operands
[1].imm
;
13022 inst
.instruction
|= Rn
<< 16;
13025 /* Neon instruction encoder helpers. */
13027 /* Encodings for the different types for various Neon opcodes. */
13029 /* An "invalid" code for the following tables. */
13032 struct neon_tab_entry
13035 unsigned float_or_poly
;
13036 unsigned scalar_or_imm
;
13039 /* Map overloaded Neon opcodes to their respective encodings. */
13040 #define NEON_ENC_TAB \
13041 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13042 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13043 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13044 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13045 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13046 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13047 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13048 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13049 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13050 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13051 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13052 /* Register variants of the following two instructions are encoded as
13053 vcge / vcgt with the operands reversed. */ \
13054 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13055 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13056 X(vfma, N_INV, 0x0000c10, N_INV), \
13057 X(vfms, N_INV, 0x0200c10, N_INV), \
13058 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13059 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13060 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13061 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13062 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13063 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13064 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13065 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13066 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13067 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13068 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13069 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13070 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13071 X(vshl, 0x0000400, N_INV, 0x0800510), \
13072 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13073 X(vand, 0x0000110, N_INV, 0x0800030), \
13074 X(vbic, 0x0100110, N_INV, 0x0800030), \
13075 X(veor, 0x1000110, N_INV, N_INV), \
13076 X(vorn, 0x0300110, N_INV, 0x0800010), \
13077 X(vorr, 0x0200110, N_INV, 0x0800010), \
13078 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13079 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13080 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13081 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13082 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13083 X(vst1, 0x0000000, 0x0800000, N_INV), \
13084 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13085 X(vst2, 0x0000100, 0x0800100, N_INV), \
13086 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13087 X(vst3, 0x0000200, 0x0800200, N_INV), \
13088 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13089 X(vst4, 0x0000300, 0x0800300, N_INV), \
13090 X(vmovn, 0x1b20200, N_INV, N_INV), \
13091 X(vtrn, 0x1b20080, N_INV, N_INV), \
13092 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13093 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13094 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13095 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13096 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13097 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13098 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13099 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13100 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13101 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13102 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13103 X(vseleq, 0xe000a00, N_INV, N_INV), \
13104 X(vselvs, 0xe100a00, N_INV, N_INV), \
13105 X(vselge, 0xe200a00, N_INV, N_INV), \
13106 X(vselgt, 0xe300a00, N_INV, N_INV), \
13107 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13108 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13109 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13110 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13111 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13112 X(aes, 0x3b00300, N_INV, N_INV), \
13113 X(sha3op, 0x2000c00, N_INV, N_INV), \
13114 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13115 X(sha2op, 0x3ba0380, N_INV, N_INV)
13119 #define X(OPC,I,F,S) N_MNEM_##OPC
13124 static const struct neon_tab_entry neon_enc_tab
[] =
13126 #define X(OPC,I,F,S) { (I), (F), (S) }
13131 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13132 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13133 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13134 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13135 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13136 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13137 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13138 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13139 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13140 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13141 #define NEON_ENC_SINGLE_(X) \
13142 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13143 #define NEON_ENC_DOUBLE_(X) \
13144 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13145 #define NEON_ENC_FPV8_(X) \
13146 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13148 #define NEON_ENCODE(type, inst) \
13151 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13152 inst.is_neon = 1; \
13156 #define check_neon_suffixes \
13159 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13161 as_bad (_("invalid neon suffix for non neon instruction")); \
13167 /* Define shapes for instruction operands. The following mnemonic characters
13168 are used in this table:
13170 F - VFP S<n> register
13171 D - Neon D<n> register
13172 Q - Neon Q<n> register
13176 L - D<n> register list
13178 This table is used to generate various data:
13179 - enumerations of the form NS_DDR to be used as arguments to
13181 - a table classifying shapes into single, double, quad, mixed.
13182 - a table used to drive neon_select_shape. */
13184 #define NEON_SHAPE_DEF \
13185 X(3, (D, D, D), DOUBLE), \
13186 X(3, (Q, Q, Q), QUAD), \
13187 X(3, (D, D, I), DOUBLE), \
13188 X(3, (Q, Q, I), QUAD), \
13189 X(3, (D, D, S), DOUBLE), \
13190 X(3, (Q, Q, S), QUAD), \
13191 X(2, (D, D), DOUBLE), \
13192 X(2, (Q, Q), QUAD), \
13193 X(2, (D, S), DOUBLE), \
13194 X(2, (Q, S), QUAD), \
13195 X(2, (D, R), DOUBLE), \
13196 X(2, (Q, R), QUAD), \
13197 X(2, (D, I), DOUBLE), \
13198 X(2, (Q, I), QUAD), \
13199 X(3, (D, L, D), DOUBLE), \
13200 X(2, (D, Q), MIXED), \
13201 X(2, (Q, D), MIXED), \
13202 X(3, (D, Q, I), MIXED), \
13203 X(3, (Q, D, I), MIXED), \
13204 X(3, (Q, D, D), MIXED), \
13205 X(3, (D, Q, Q), MIXED), \
13206 X(3, (Q, Q, D), MIXED), \
13207 X(3, (Q, D, S), MIXED), \
13208 X(3, (D, Q, S), MIXED), \
13209 X(4, (D, D, D, I), DOUBLE), \
13210 X(4, (Q, Q, Q, I), QUAD), \
13211 X(2, (F, F), SINGLE), \
13212 X(3, (F, F, F), SINGLE), \
13213 X(2, (F, I), SINGLE), \
13214 X(2, (F, D), MIXED), \
13215 X(2, (D, F), MIXED), \
13216 X(3, (F, F, I), MIXED), \
13217 X(4, (R, R, F, F), SINGLE), \
13218 X(4, (F, F, R, R), SINGLE), \
13219 X(3, (D, R, R), DOUBLE), \
13220 X(3, (R, R, D), DOUBLE), \
13221 X(2, (S, R), SINGLE), \
13222 X(2, (R, S), SINGLE), \
13223 X(2, (F, R), SINGLE), \
13224 X(2, (R, F), SINGLE)
13226 #define S2(A,B) NS_##A##B
13227 #define S3(A,B,C) NS_##A##B##C
13228 #define S4(A,B,C,D) NS_##A##B##C##D
13230 #define X(N, L, C) S##N L
13243 enum neon_shape_class
13251 #define X(N, L, C) SC_##C
13253 static enum neon_shape_class neon_shape_class
[] =
13271 /* Register widths of above. */
13272 static unsigned neon_shape_el_size
[] =
13283 struct neon_shape_info
13286 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13289 #define S2(A,B) { SE_##A, SE_##B }
13290 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13291 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13293 #define X(N, L, C) { N, S##N L }
13295 static struct neon_shape_info neon_shape_tab
[] =
13305 /* Bit masks used in type checking given instructions.
13306 'N_EQK' means the type must be the same as (or based on in some way) the key
13307 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13308 set, various other bits can be set as well in order to modify the meaning of
13309 the type constraint. */
13311 enum neon_type_mask
13335 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13336 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13337 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13338 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13339 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13340 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13341 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13342 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13343 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13344 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13345 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13347 N_MAX_NONSPECIAL
= N_P64
13350 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13352 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13353 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13354 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13355 #define N_SUF_32 (N_SU_32 | N_F32)
13356 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13357 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13359 /* Pass this as the first type argument to neon_check_type to ignore types
13361 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13363 /* Select a "shape" for the current instruction (describing register types or
13364 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13365 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13366 function of operand parsing, so this function doesn't need to be called.
13367 Shapes should be listed in order of decreasing length. */
13369 static enum neon_shape
13370 neon_select_shape (enum neon_shape shape
, ...)
13373 enum neon_shape first_shape
= shape
;
13375 /* Fix missing optional operands. FIXME: we don't know at this point how
13376 many arguments we should have, so this makes the assumption that we have
13377 > 1. This is true of all current Neon opcodes, I think, but may not be
13378 true in the future. */
13379 if (!inst
.operands
[1].present
)
13380 inst
.operands
[1] = inst
.operands
[0];
13382 va_start (ap
, shape
);
13384 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13389 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13391 if (!inst
.operands
[j
].present
)
13397 switch (neon_shape_tab
[shape
].el
[j
])
13400 if (!(inst
.operands
[j
].isreg
13401 && inst
.operands
[j
].isvec
13402 && inst
.operands
[j
].issingle
13403 && !inst
.operands
[j
].isquad
))
13408 if (!(inst
.operands
[j
].isreg
13409 && inst
.operands
[j
].isvec
13410 && !inst
.operands
[j
].isquad
13411 && !inst
.operands
[j
].issingle
))
13416 if (!(inst
.operands
[j
].isreg
13417 && !inst
.operands
[j
].isvec
))
13422 if (!(inst
.operands
[j
].isreg
13423 && inst
.operands
[j
].isvec
13424 && inst
.operands
[j
].isquad
13425 && !inst
.operands
[j
].issingle
))
13430 if (!(!inst
.operands
[j
].isreg
13431 && !inst
.operands
[j
].isscalar
))
13436 if (!(!inst
.operands
[j
].isreg
13437 && inst
.operands
[j
].isscalar
))
13447 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13448 /* We've matched all the entries in the shape table, and we don't
13449 have any left over operands which have not been matched. */
13455 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13456 first_error (_("invalid instruction shape"));
13461 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13462 means the Q bit should be set). */
13465 neon_quad (enum neon_shape shape
)
13467 return neon_shape_class
[shape
] == SC_QUAD
;
13471 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13474 /* Allow modification to be made to types which are constrained to be
13475 based on the key element, based on bits set alongside N_EQK. */
13476 if ((typebits
& N_EQK
) != 0)
13478 if ((typebits
& N_HLF
) != 0)
13480 else if ((typebits
& N_DBL
) != 0)
13482 if ((typebits
& N_SGN
) != 0)
13483 *g_type
= NT_signed
;
13484 else if ((typebits
& N_UNS
) != 0)
13485 *g_type
= NT_unsigned
;
13486 else if ((typebits
& N_INT
) != 0)
13487 *g_type
= NT_integer
;
13488 else if ((typebits
& N_FLT
) != 0)
13489 *g_type
= NT_float
;
13490 else if ((typebits
& N_SIZ
) != 0)
13491 *g_type
= NT_untyped
;
13495 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13496 operand type, i.e. the single type specified in a Neon instruction when it
13497 is the only one given. */
13499 static struct neon_type_el
13500 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13502 struct neon_type_el dest
= *key
;
13504 gas_assert ((thisarg
& N_EQK
) != 0);
13506 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13511 /* Convert Neon type and size into compact bitmask representation. */
13513 static enum neon_type_mask
13514 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13521 case 8: return N_8
;
13522 case 16: return N_16
;
13523 case 32: return N_32
;
13524 case 64: return N_64
;
13532 case 8: return N_I8
;
13533 case 16: return N_I16
;
13534 case 32: return N_I32
;
13535 case 64: return N_I64
;
13543 case 16: return N_F16
;
13544 case 32: return N_F32
;
13545 case 64: return N_F64
;
13553 case 8: return N_P8
;
13554 case 16: return N_P16
;
13555 case 64: return N_P64
;
13563 case 8: return N_S8
;
13564 case 16: return N_S16
;
13565 case 32: return N_S32
;
13566 case 64: return N_S64
;
13574 case 8: return N_U8
;
13575 case 16: return N_U16
;
13576 case 32: return N_U32
;
13577 case 64: return N_U64
;
13588 /* Convert compact Neon bitmask type representation to a type and size. Only
13589 handles the case where a single bit is set in the mask. */
13592 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13593 enum neon_type_mask mask
)
13595 if ((mask
& N_EQK
) != 0)
13598 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13600 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13602 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13604 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13609 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13611 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13612 *type
= NT_unsigned
;
13613 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13614 *type
= NT_integer
;
13615 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13616 *type
= NT_untyped
;
13617 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13619 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13627 /* Modify a bitmask of allowed types. This is only needed for type
13631 modify_types_allowed (unsigned allowed
, unsigned mods
)
13634 enum neon_el_type type
;
13640 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13642 if (el_type_of_type_chk (&type
, &size
,
13643 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13645 neon_modify_type_size (mods
, &type
, &size
);
13646 destmask
|= type_chk_of_el_type (type
, size
);
13653 /* Check type and return type classification.
13654 The manual states (paraphrase): If one datatype is given, it indicates the
13656 - the second operand, if there is one
13657 - the operand, if there is no second operand
13658 - the result, if there are no operands.
13659 This isn't quite good enough though, so we use a concept of a "key" datatype
13660 which is set on a per-instruction basis, which is the one which matters when
13661 only one data type is written.
13662 Note: this function has side-effects (e.g. filling in missing operands). All
13663 Neon instructions should call it before performing bit encoding. */
13665 static struct neon_type_el
13666 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13669 unsigned i
, pass
, key_el
= 0;
13670 unsigned types
[NEON_MAX_TYPE_ELS
];
13671 enum neon_el_type k_type
= NT_invtype
;
13672 unsigned k_size
= -1u;
13673 struct neon_type_el badtype
= {NT_invtype
, -1};
13674 unsigned key_allowed
= 0;
13676 /* Optional registers in Neon instructions are always (not) in operand 1.
13677 Fill in the missing operand here, if it was omitted. */
13678 if (els
> 1 && !inst
.operands
[1].present
)
13679 inst
.operands
[1] = inst
.operands
[0];
13681 /* Suck up all the varargs. */
13683 for (i
= 0; i
< els
; i
++)
13685 unsigned thisarg
= va_arg (ap
, unsigned);
13686 if (thisarg
== N_IGNORE_TYPE
)
13691 types
[i
] = thisarg
;
13692 if ((thisarg
& N_KEY
) != 0)
13697 if (inst
.vectype
.elems
> 0)
13698 for (i
= 0; i
< els
; i
++)
13699 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13701 first_error (_("types specified in both the mnemonic and operands"));
13705 /* Duplicate inst.vectype elements here as necessary.
13706 FIXME: No idea if this is exactly the same as the ARM assembler,
13707 particularly when an insn takes one register and one non-register
13709 if (inst
.vectype
.elems
== 1 && els
> 1)
13712 inst
.vectype
.elems
= els
;
13713 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13714 for (j
= 0; j
< els
; j
++)
13716 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13719 else if (inst
.vectype
.elems
== 0 && els
> 0)
13722 /* No types were given after the mnemonic, so look for types specified
13723 after each operand. We allow some flexibility here; as long as the
13724 "key" operand has a type, we can infer the others. */
13725 for (j
= 0; j
< els
; j
++)
13726 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13727 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13729 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13731 for (j
= 0; j
< els
; j
++)
13732 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13733 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13738 first_error (_("operand types can't be inferred"));
13742 else if (inst
.vectype
.elems
!= els
)
13744 first_error (_("type specifier has the wrong number of parts"));
13748 for (pass
= 0; pass
< 2; pass
++)
13750 for (i
= 0; i
< els
; i
++)
13752 unsigned thisarg
= types
[i
];
13753 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13754 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13755 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13756 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13758 /* Decay more-specific signed & unsigned types to sign-insensitive
13759 integer types if sign-specific variants are unavailable. */
13760 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13761 && (types_allowed
& N_SU_ALL
) == 0)
13762 g_type
= NT_integer
;
13764 /* If only untyped args are allowed, decay any more specific types to
13765 them. Some instructions only care about signs for some element
13766 sizes, so handle that properly. */
13767 if (((types_allowed
& N_UNT
) == 0)
13768 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13769 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13770 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13771 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13772 g_type
= NT_untyped
;
13776 if ((thisarg
& N_KEY
) != 0)
13780 key_allowed
= thisarg
& ~N_KEY
;
13785 if ((thisarg
& N_VFP
) != 0)
13787 enum neon_shape_el regshape
;
13788 unsigned regwidth
, match
;
13790 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13793 first_error (_("invalid instruction shape"));
13796 regshape
= neon_shape_tab
[ns
].el
[i
];
13797 regwidth
= neon_shape_el_size
[regshape
];
13799 /* In VFP mode, operands must match register widths. If we
13800 have a key operand, use its width, else use the width of
13801 the current operand. */
13807 if (regwidth
!= match
)
13809 first_error (_("operand size must match register width"));
13814 if ((thisarg
& N_EQK
) == 0)
13816 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13818 if ((given_type
& types_allowed
) == 0)
13820 first_error (_("bad type in Neon instruction"));
13826 enum neon_el_type mod_k_type
= k_type
;
13827 unsigned mod_k_size
= k_size
;
13828 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13829 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13831 first_error (_("inconsistent types in Neon instruction"));
13839 return inst
.vectype
.el
[key_el
];
13842 /* Neon-style VFP instruction forwarding. */
13844 /* Thumb VFP instructions have 0xE in the condition field. */
13847 do_vfp_cond_or_thumb (void)
13852 inst
.instruction
|= 0xe0000000;
13854 inst
.instruction
|= inst
.cond
<< 28;
13857 /* Look up and encode a simple mnemonic, for use as a helper function for the
13858 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13859 etc. It is assumed that operand parsing has already been done, and that the
13860 operands are in the form expected by the given opcode (this isn't necessarily
13861 the same as the form in which they were parsed, hence some massaging must
13862 take place before this function is called).
13863 Checks current arch version against that in the looked-up opcode. */
13866 do_vfp_nsyn_opcode (const char *opname
)
13868 const struct asm_opcode
*opcode
;
13870 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13875 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13876 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13883 inst
.instruction
= opcode
->tvalue
;
13884 opcode
->tencode ();
13888 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13889 opcode
->aencode ();
13894 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13896 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13901 do_vfp_nsyn_opcode ("fadds");
13903 do_vfp_nsyn_opcode ("fsubs");
13908 do_vfp_nsyn_opcode ("faddd");
13910 do_vfp_nsyn_opcode ("fsubd");
13914 /* Check operand types to see if this is a VFP instruction, and if so call
13918 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13920 enum neon_shape rs
;
13921 struct neon_type_el et
;
13926 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13927 et
= neon_check_type (2, rs
,
13928 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13932 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13933 et
= neon_check_type (3, rs
,
13934 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13941 if (et
.type
!= NT_invtype
)
13952 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13954 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13959 do_vfp_nsyn_opcode ("fmacs");
13961 do_vfp_nsyn_opcode ("fnmacs");
13966 do_vfp_nsyn_opcode ("fmacd");
13968 do_vfp_nsyn_opcode ("fnmacd");
13973 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13975 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13980 do_vfp_nsyn_opcode ("ffmas");
13982 do_vfp_nsyn_opcode ("ffnmas");
13987 do_vfp_nsyn_opcode ("ffmad");
13989 do_vfp_nsyn_opcode ("ffnmad");
13994 do_vfp_nsyn_mul (enum neon_shape rs
)
13997 do_vfp_nsyn_opcode ("fmuls");
13999 do_vfp_nsyn_opcode ("fmuld");
14003 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14005 int is_neg
= (inst
.instruction
& 0x80) != 0;
14006 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
14011 do_vfp_nsyn_opcode ("fnegs");
14013 do_vfp_nsyn_opcode ("fabss");
14018 do_vfp_nsyn_opcode ("fnegd");
14020 do_vfp_nsyn_opcode ("fabsd");
14024 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14025 insns belong to Neon, and are handled elsewhere. */
14028 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14030 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14034 do_vfp_nsyn_opcode ("fldmdbs");
14036 do_vfp_nsyn_opcode ("fldmias");
14041 do_vfp_nsyn_opcode ("fstmdbs");
14043 do_vfp_nsyn_opcode ("fstmias");
14048 do_vfp_nsyn_sqrt (void)
14050 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14051 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14054 do_vfp_nsyn_opcode ("fsqrts");
14056 do_vfp_nsyn_opcode ("fsqrtd");
14060 do_vfp_nsyn_div (void)
14062 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14063 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14064 N_F32
| N_F64
| N_KEY
| N_VFP
);
14067 do_vfp_nsyn_opcode ("fdivs");
14069 do_vfp_nsyn_opcode ("fdivd");
14073 do_vfp_nsyn_nmul (void)
14075 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14076 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14077 N_F32
| N_F64
| N_KEY
| N_VFP
);
14081 NEON_ENCODE (SINGLE
, inst
);
14082 do_vfp_sp_dyadic ();
14086 NEON_ENCODE (DOUBLE
, inst
);
14087 do_vfp_dp_rd_rn_rm ();
14089 do_vfp_cond_or_thumb ();
14093 do_vfp_nsyn_cmp (void)
14095 if (inst
.operands
[1].isreg
)
14097 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14098 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14102 NEON_ENCODE (SINGLE
, inst
);
14103 do_vfp_sp_monadic ();
14107 NEON_ENCODE (DOUBLE
, inst
);
14108 do_vfp_dp_rd_rm ();
14113 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14114 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14116 switch (inst
.instruction
& 0x0fffffff)
14119 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14122 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14130 NEON_ENCODE (SINGLE
, inst
);
14131 do_vfp_sp_compare_z ();
14135 NEON_ENCODE (DOUBLE
, inst
);
14139 do_vfp_cond_or_thumb ();
14143 nsyn_insert_sp (void)
14145 inst
.operands
[1] = inst
.operands
[0];
14146 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14147 inst
.operands
[0].reg
= REG_SP
;
14148 inst
.operands
[0].isreg
= 1;
14149 inst
.operands
[0].writeback
= 1;
14150 inst
.operands
[0].present
= 1;
14154 do_vfp_nsyn_push (void)
14157 if (inst
.operands
[1].issingle
)
14158 do_vfp_nsyn_opcode ("fstmdbs");
14160 do_vfp_nsyn_opcode ("fstmdbd");
14164 do_vfp_nsyn_pop (void)
14167 if (inst
.operands
[1].issingle
)
14168 do_vfp_nsyn_opcode ("fldmias");
14170 do_vfp_nsyn_opcode ("fldmiad");
14173 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14174 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14177 neon_dp_fixup (struct arm_it
* insn
)
14179 unsigned int i
= insn
->instruction
;
14184 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14195 insn
->instruction
= i
;
14198 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14202 neon_logbits (unsigned x
)
14204 return ffs (x
) - 4;
14207 #define LOW4(R) ((R) & 0xf)
14208 #define HI1(R) (((R) >> 4) & 1)
14210 /* Encode insns with bit pattern:
14212 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14213 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14215 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14216 different meaning for some instruction. */
14219 neon_three_same (int isquad
, int ubit
, int size
)
14221 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14222 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14223 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14224 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14225 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14226 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14227 inst
.instruction
|= (isquad
!= 0) << 6;
14228 inst
.instruction
|= (ubit
!= 0) << 24;
14230 inst
.instruction
|= neon_logbits (size
) << 20;
14232 neon_dp_fixup (&inst
);
14235 /* Encode instructions of the form:
14237 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14238 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14240 Don't write size if SIZE == -1. */
14243 neon_two_same (int qbit
, int ubit
, int size
)
14245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14248 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14249 inst
.instruction
|= (qbit
!= 0) << 6;
14250 inst
.instruction
|= (ubit
!= 0) << 24;
14253 inst
.instruction
|= neon_logbits (size
) << 18;
14255 neon_dp_fixup (&inst
);
14258 /* Neon instruction encoders, in approximate order of appearance. */
14261 do_neon_dyadic_i_su (void)
14263 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14264 struct neon_type_el et
= neon_check_type (3, rs
,
14265 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14266 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14270 do_neon_dyadic_i64_su (void)
14272 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14273 struct neon_type_el et
= neon_check_type (3, rs
,
14274 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14275 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14279 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14282 unsigned size
= et
.size
>> 3;
14283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14287 inst
.instruction
|= (isquad
!= 0) << 6;
14288 inst
.instruction
|= immbits
<< 16;
14289 inst
.instruction
|= (size
>> 3) << 7;
14290 inst
.instruction
|= (size
& 0x7) << 19;
14292 inst
.instruction
|= (uval
!= 0) << 24;
14294 neon_dp_fixup (&inst
);
14298 do_neon_shl_imm (void)
14300 if (!inst
.operands
[2].isreg
)
14302 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14303 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14304 int imm
= inst
.operands
[2].imm
;
14306 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14307 _("immediate out of range for shift"));
14308 NEON_ENCODE (IMMED
, inst
);
14309 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14313 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14314 struct neon_type_el et
= neon_check_type (3, rs
,
14315 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14318 /* VSHL/VQSHL 3-register variants have syntax such as:
14320 whereas other 3-register operations encoded by neon_three_same have
14323 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14325 tmp
= inst
.operands
[2].reg
;
14326 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14327 inst
.operands
[1].reg
= tmp
;
14328 NEON_ENCODE (INTEGER
, inst
);
14329 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14334 do_neon_qshl_imm (void)
14336 if (!inst
.operands
[2].isreg
)
14338 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14339 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14340 int imm
= inst
.operands
[2].imm
;
14342 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14343 _("immediate out of range for shift"));
14344 NEON_ENCODE (IMMED
, inst
);
14345 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14349 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14350 struct neon_type_el et
= neon_check_type (3, rs
,
14351 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14354 /* See note in do_neon_shl_imm. */
14355 tmp
= inst
.operands
[2].reg
;
14356 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14357 inst
.operands
[1].reg
= tmp
;
14358 NEON_ENCODE (INTEGER
, inst
);
14359 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14364 do_neon_rshl (void)
14366 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14367 struct neon_type_el et
= neon_check_type (3, rs
,
14368 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14371 tmp
= inst
.operands
[2].reg
;
14372 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14373 inst
.operands
[1].reg
= tmp
;
14374 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14378 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14380 /* Handle .I8 pseudo-instructions. */
14383 /* Unfortunately, this will make everything apart from zero out-of-range.
14384 FIXME is this the intended semantics? There doesn't seem much point in
14385 accepting .I8 if so. */
14386 immediate
|= immediate
<< 8;
14392 if (immediate
== (immediate
& 0x000000ff))
14394 *immbits
= immediate
;
14397 else if (immediate
== (immediate
& 0x0000ff00))
14399 *immbits
= immediate
>> 8;
14402 else if (immediate
== (immediate
& 0x00ff0000))
14404 *immbits
= immediate
>> 16;
14407 else if (immediate
== (immediate
& 0xff000000))
14409 *immbits
= immediate
>> 24;
14412 if ((immediate
& 0xffff) != (immediate
>> 16))
14413 goto bad_immediate
;
14414 immediate
&= 0xffff;
14417 if (immediate
== (immediate
& 0x000000ff))
14419 *immbits
= immediate
;
14422 else if (immediate
== (immediate
& 0x0000ff00))
14424 *immbits
= immediate
>> 8;
14429 first_error (_("immediate value out of range"));
14434 do_neon_logic (void)
14436 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14438 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14439 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14440 /* U bit and size field were set as part of the bitmask. */
14441 NEON_ENCODE (INTEGER
, inst
);
14442 neon_three_same (neon_quad (rs
), 0, -1);
14446 const int three_ops_form
= (inst
.operands
[2].present
14447 && !inst
.operands
[2].isreg
);
14448 const int immoperand
= (three_ops_form
? 2 : 1);
14449 enum neon_shape rs
= (three_ops_form
14450 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14451 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14452 struct neon_type_el et
= neon_check_type (2, rs
,
14453 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14454 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14458 if (et
.type
== NT_invtype
)
14461 if (three_ops_form
)
14462 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14463 _("first and second operands shall be the same register"));
14465 NEON_ENCODE (IMMED
, inst
);
14467 immbits
= inst
.operands
[immoperand
].imm
;
14470 /* .i64 is a pseudo-op, so the immediate must be a repeating
14472 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14473 inst
.operands
[immoperand
].reg
: 0))
14475 /* Set immbits to an invalid constant. */
14476 immbits
= 0xdeadbeef;
14483 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14487 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14491 /* Pseudo-instruction for VBIC. */
14492 neon_invert_size (&immbits
, 0, et
.size
);
14493 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14497 /* Pseudo-instruction for VORR. */
14498 neon_invert_size (&immbits
, 0, et
.size
);
14499 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14509 inst
.instruction
|= neon_quad (rs
) << 6;
14510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14512 inst
.instruction
|= cmode
<< 8;
14513 neon_write_immbits (immbits
);
14515 neon_dp_fixup (&inst
);
14520 do_neon_bitfield (void)
14522 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14523 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14524 neon_three_same (neon_quad (rs
), 0, -1);
14528 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14531 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14532 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14534 if (et
.type
== NT_float
)
14536 NEON_ENCODE (FLOAT
, inst
);
14537 neon_three_same (neon_quad (rs
), 0, -1);
14541 NEON_ENCODE (INTEGER
, inst
);
14542 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14547 do_neon_dyadic_if_su (void)
14549 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14553 do_neon_dyadic_if_su_d (void)
14555 /* This version only allow D registers, but that constraint is enforced during
14556 operand parsing so we don't need to do anything extra here. */
14557 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14561 do_neon_dyadic_if_i_d (void)
14563 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14564 affected if we specify unsigned args. */
14565 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14568 enum vfp_or_neon_is_neon_bits
14571 NEON_CHECK_ARCH
= 2,
14572 NEON_CHECK_ARCH8
= 4
14575 /* Call this function if an instruction which may have belonged to the VFP or
14576 Neon instruction sets, but turned out to be a Neon instruction (due to the
14577 operand types involved, etc.). We have to check and/or fix-up a couple of
14580 - Make sure the user hasn't attempted to make a Neon instruction
14582 - Alter the value in the condition code field if necessary.
14583 - Make sure that the arch supports Neon instructions.
14585 Which of these operations take place depends on bits from enum
14586 vfp_or_neon_is_neon_bits.
14588 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14589 current instruction's condition is COND_ALWAYS, the condition field is
14590 changed to inst.uncond_value. This is necessary because instructions shared
14591 between VFP and Neon may be conditional for the VFP variants only, and the
14592 unconditional Neon version must have, e.g., 0xF in the condition field. */
14595 vfp_or_neon_is_neon (unsigned check
)
14597 /* Conditions are always legal in Thumb mode (IT blocks). */
14598 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14600 if (inst
.cond
!= COND_ALWAYS
)
14602 first_error (_(BAD_COND
));
14605 if (inst
.uncond_value
!= -1)
14606 inst
.instruction
|= inst
.uncond_value
<< 28;
14609 if ((check
& NEON_CHECK_ARCH
)
14610 && !mark_feature_used (&fpu_neon_ext_v1
))
14612 first_error (_(BAD_FPU
));
14616 if ((check
& NEON_CHECK_ARCH8
)
14617 && !mark_feature_used (&fpu_neon_ext_armv8
))
14619 first_error (_(BAD_FPU
));
14627 do_neon_addsub_if_i (void)
14629 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14632 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14635 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14636 affected if we specify unsigned args. */
14637 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14640 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14642 V<op> A,B (A is operand 0, B is operand 2)
14647 so handle that case specially. */
14650 neon_exchange_operands (void)
14652 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14653 if (inst
.operands
[1].present
)
14655 /* Swap operands[1] and operands[2]. */
14656 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14657 inst
.operands
[1] = inst
.operands
[2];
14658 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14662 inst
.operands
[1] = inst
.operands
[2];
14663 inst
.operands
[2] = inst
.operands
[0];
14668 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14670 if (inst
.operands
[2].isreg
)
14673 neon_exchange_operands ();
14674 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14678 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14679 struct neon_type_el et
= neon_check_type (2, rs
,
14680 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14682 NEON_ENCODE (IMMED
, inst
);
14683 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14684 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14685 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14686 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14687 inst
.instruction
|= neon_quad (rs
) << 6;
14688 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14689 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14691 neon_dp_fixup (&inst
);
14698 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14702 do_neon_cmp_inv (void)
14704 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14710 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14713 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14714 scalars, which are encoded in 5 bits, M : Rm.
14715 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14716 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14720 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14722 unsigned regno
= NEON_SCALAR_REG (scalar
);
14723 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14728 if (regno
> 7 || elno
> 3)
14730 return regno
| (elno
<< 3);
14733 if (regno
> 15 || elno
> 1)
14735 return regno
| (elno
<< 4);
14739 first_error (_("scalar out of range for multiply instruction"));
14745 /* Encode multiply / multiply-accumulate scalar instructions. */
14748 neon_mul_mac (struct neon_type_el et
, int ubit
)
14752 /* Give a more helpful error message if we have an invalid type. */
14753 if (et
.type
== NT_invtype
)
14756 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14761 inst
.instruction
|= LOW4 (scalar
);
14762 inst
.instruction
|= HI1 (scalar
) << 5;
14763 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14764 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14765 inst
.instruction
|= (ubit
!= 0) << 24;
14767 neon_dp_fixup (&inst
);
14771 do_neon_mac_maybe_scalar (void)
14773 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14776 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14779 if (inst
.operands
[2].isscalar
)
14781 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14782 struct neon_type_el et
= neon_check_type (3, rs
,
14783 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14784 NEON_ENCODE (SCALAR
, inst
);
14785 neon_mul_mac (et
, neon_quad (rs
));
14789 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14790 affected if we specify unsigned args. */
14791 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14796 do_neon_fmac (void)
14798 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14801 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14804 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14810 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14811 struct neon_type_el et
= neon_check_type (3, rs
,
14812 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14813 neon_three_same (neon_quad (rs
), 0, et
.size
);
14816 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14817 same types as the MAC equivalents. The polynomial type for this instruction
14818 is encoded the same as the integer type. */
14823 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14826 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14829 if (inst
.operands
[2].isscalar
)
14830 do_neon_mac_maybe_scalar ();
14832 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14836 do_neon_qdmulh (void)
14838 if (inst
.operands
[2].isscalar
)
14840 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14841 struct neon_type_el et
= neon_check_type (3, rs
,
14842 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14843 NEON_ENCODE (SCALAR
, inst
);
14844 neon_mul_mac (et
, neon_quad (rs
));
14848 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14849 struct neon_type_el et
= neon_check_type (3, rs
,
14850 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14851 NEON_ENCODE (INTEGER
, inst
);
14852 /* The U bit (rounding) comes from bit mask. */
14853 neon_three_same (neon_quad (rs
), 0, et
.size
);
14858 do_neon_fcmp_absolute (void)
14860 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14861 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14862 /* Size field comes from bit mask. */
14863 neon_three_same (neon_quad (rs
), 1, -1);
14867 do_neon_fcmp_absolute_inv (void)
14869 neon_exchange_operands ();
14870 do_neon_fcmp_absolute ();
14874 do_neon_step (void)
14876 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14877 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14878 neon_three_same (neon_quad (rs
), 0, -1);
14882 do_neon_abs_neg (void)
14884 enum neon_shape rs
;
14885 struct neon_type_el et
;
14887 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14890 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14893 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14894 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14896 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14897 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14898 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14899 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14900 inst
.instruction
|= neon_quad (rs
) << 6;
14901 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14902 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14904 neon_dp_fixup (&inst
);
14910 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14911 struct neon_type_el et
= neon_check_type (2, rs
,
14912 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14913 int imm
= inst
.operands
[2].imm
;
14914 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14915 _("immediate out of range for insert"));
14916 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14922 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14923 struct neon_type_el et
= neon_check_type (2, rs
,
14924 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14925 int imm
= inst
.operands
[2].imm
;
14926 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14927 _("immediate out of range for insert"));
14928 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14932 do_neon_qshlu_imm (void)
14934 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14935 struct neon_type_el et
= neon_check_type (2, rs
,
14936 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14937 int imm
= inst
.operands
[2].imm
;
14938 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14939 _("immediate out of range for shift"));
14940 /* Only encodes the 'U present' variant of the instruction.
14941 In this case, signed types have OP (bit 8) set to 0.
14942 Unsigned types have OP set to 1. */
14943 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14944 /* The rest of the bits are the same as other immediate shifts. */
14945 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14949 do_neon_qmovn (void)
14951 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14952 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14953 /* Saturating move where operands can be signed or unsigned, and the
14954 destination has the same signedness. */
14955 NEON_ENCODE (INTEGER
, inst
);
14956 if (et
.type
== NT_unsigned
)
14957 inst
.instruction
|= 0xc0;
14959 inst
.instruction
|= 0x80;
14960 neon_two_same (0, 1, et
.size
/ 2);
14964 do_neon_qmovun (void)
14966 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14967 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14968 /* Saturating move with unsigned results. Operands must be signed. */
14969 NEON_ENCODE (INTEGER
, inst
);
14970 neon_two_same (0, 1, et
.size
/ 2);
14974 do_neon_rshift_sat_narrow (void)
14976 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14977 or unsigned. If operands are unsigned, results must also be unsigned. */
14978 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14979 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14980 int imm
= inst
.operands
[2].imm
;
14981 /* This gets the bounds check, size encoding and immediate bits calculation
14985 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14986 VQMOVN.I<size> <Dd>, <Qm>. */
14989 inst
.operands
[2].present
= 0;
14990 inst
.instruction
= N_MNEM_vqmovn
;
14995 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14996 _("immediate out of range"));
14997 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15001 do_neon_rshift_sat_narrow_u (void)
15003 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15004 or unsigned. If operands are unsigned, results must also be unsigned. */
15005 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15006 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15007 int imm
= inst
.operands
[2].imm
;
15008 /* This gets the bounds check, size encoding and immediate bits calculation
15012 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15013 VQMOVUN.I<size> <Dd>, <Qm>. */
15016 inst
.operands
[2].present
= 0;
15017 inst
.instruction
= N_MNEM_vqmovun
;
15022 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15023 _("immediate out of range"));
15024 /* FIXME: The manual is kind of unclear about what value U should have in
15025 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15027 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15031 do_neon_movn (void)
15033 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15034 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15035 NEON_ENCODE (INTEGER
, inst
);
15036 neon_two_same (0, 1, et
.size
/ 2);
15040 do_neon_rshift_narrow (void)
15042 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15043 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15044 int imm
= inst
.operands
[2].imm
;
15045 /* This gets the bounds check, size encoding and immediate bits calculation
15049 /* If immediate is zero then we are a pseudo-instruction for
15050 VMOVN.I<size> <Dd>, <Qm> */
15053 inst
.operands
[2].present
= 0;
15054 inst
.instruction
= N_MNEM_vmovn
;
15059 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15060 _("immediate out of range for narrowing operation"));
15061 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15065 do_neon_shll (void)
15067 /* FIXME: Type checking when lengthening. */
15068 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15069 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15070 unsigned imm
= inst
.operands
[2].imm
;
15072 if (imm
== et
.size
)
15074 /* Maximum shift variant. */
15075 NEON_ENCODE (INTEGER
, inst
);
15076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15080 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15082 neon_dp_fixup (&inst
);
15086 /* A more-specific type check for non-max versions. */
15087 et
= neon_check_type (2, NS_QDI
,
15088 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15089 NEON_ENCODE (IMMED
, inst
);
15090 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15094 /* Check the various types for the VCVT instruction, and return which version
15095 the current instruction is. */
15097 #define CVT_FLAVOUR_VAR \
15098 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15099 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15100 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15101 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15102 /* Half-precision conversions. */ \
15103 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15104 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15105 /* VFP instructions. */ \
15106 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15107 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15108 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15109 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15110 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15111 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15112 /* VFP instructions with bitshift. */ \
15113 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15114 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15115 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15116 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15117 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15118 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15119 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15120 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15122 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15123 neon_cvt_flavour_##C,
15125 /* The different types of conversions we can do. */
15126 enum neon_cvt_flavour
15129 neon_cvt_flavour_invalid
,
15130 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15135 static enum neon_cvt_flavour
15136 get_neon_cvt_flavour (enum neon_shape rs
)
15138 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15139 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15140 if (et.type != NT_invtype) \
15142 inst.error = NULL; \
15143 return (neon_cvt_flavour_##C); \
15146 struct neon_type_el et
;
15147 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15148 || rs
== NS_FF
) ? N_VFP
: 0;
15149 /* The instruction versions which take an immediate take one register
15150 argument, which is extended to the width of the full register. Thus the
15151 "source" and "destination" registers must have the same width. Hack that
15152 here by making the size equal to the key (wider, in this case) operand. */
15153 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15157 return neon_cvt_flavour_invalid
;
15172 /* Neon-syntax VFP conversions. */
15175 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15177 const char *opname
= 0;
15179 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15181 /* Conversions with immediate bitshift. */
15182 const char *enc
[] =
15184 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15190 if (flavour
< (int) ARRAY_SIZE (enc
))
15192 opname
= enc
[flavour
];
15193 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15194 _("operands 0 and 1 must be the same register"));
15195 inst
.operands
[1] = inst
.operands
[2];
15196 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15201 /* Conversions without bitshift. */
15202 const char *enc
[] =
15204 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15210 if (flavour
< (int) ARRAY_SIZE (enc
))
15211 opname
= enc
[flavour
];
15215 do_vfp_nsyn_opcode (opname
);
15219 do_vfp_nsyn_cvtz (void)
15221 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15222 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15223 const char *enc
[] =
15225 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15231 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15232 do_vfp_nsyn_opcode (enc
[flavour
]);
15236 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15237 enum neon_cvt_mode mode
)
15242 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15243 D register operands. */
15244 if (flavour
== neon_cvt_flavour_s32_f64
15245 || flavour
== neon_cvt_flavour_u32_f64
)
15246 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15249 set_it_insn_type (OUTSIDE_IT_INSN
);
15253 case neon_cvt_flavour_s32_f64
:
15257 case neon_cvt_flavour_s32_f32
:
15261 case neon_cvt_flavour_u32_f64
:
15265 case neon_cvt_flavour_u32_f32
:
15270 first_error (_("invalid instruction shape"));
15276 case neon_cvt_mode_a
: rm
= 0; break;
15277 case neon_cvt_mode_n
: rm
= 1; break;
15278 case neon_cvt_mode_p
: rm
= 2; break;
15279 case neon_cvt_mode_m
: rm
= 3; break;
15280 default: first_error (_("invalid rounding mode")); return;
15283 NEON_ENCODE (FPV8
, inst
);
15284 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15285 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15286 inst
.instruction
|= sz
<< 8;
15287 inst
.instruction
|= op
<< 7;
15288 inst
.instruction
|= rm
<< 16;
15289 inst
.instruction
|= 0xf0000000;
15290 inst
.is_neon
= TRUE
;
15294 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15296 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15297 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15298 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15300 /* PR11109: Handle round-to-zero for VCVT conversions. */
15301 if (mode
== neon_cvt_mode_z
15302 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15303 && (flavour
== neon_cvt_flavour_s32_f32
15304 || flavour
== neon_cvt_flavour_u32_f32
15305 || flavour
== neon_cvt_flavour_s32_f64
15306 || flavour
== neon_cvt_flavour_u32_f64
)
15307 && (rs
== NS_FD
|| rs
== NS_FF
))
15309 do_vfp_nsyn_cvtz ();
15313 /* VFP rather than Neon conversions. */
15314 if (flavour
>= neon_cvt_flavour_first_fp
)
15316 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15317 do_vfp_nsyn_cvt (rs
, flavour
);
15319 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15330 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15332 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15335 /* Fixed-point conversion with #0 immediate is encoded as an
15336 integer conversion. */
15337 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15339 immbits
= 32 - inst
.operands
[2].imm
;
15340 NEON_ENCODE (IMMED
, inst
);
15341 if (flavour
!= neon_cvt_flavour_invalid
)
15342 inst
.instruction
|= enctab
[flavour
];
15343 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15344 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15345 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15346 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15347 inst
.instruction
|= neon_quad (rs
) << 6;
15348 inst
.instruction
|= 1 << 21;
15349 inst
.instruction
|= immbits
<< 16;
15351 neon_dp_fixup (&inst
);
15357 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15359 NEON_ENCODE (FLOAT
, inst
);
15360 set_it_insn_type (OUTSIDE_IT_INSN
);
15362 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15365 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15367 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15369 inst
.instruction
|= neon_quad (rs
) << 6;
15370 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15371 inst
.instruction
|= mode
<< 8;
15373 inst
.instruction
|= 0xfc000000;
15375 inst
.instruction
|= 0xf0000000;
15381 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15383 NEON_ENCODE (INTEGER
, inst
);
15385 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15388 if (flavour
!= neon_cvt_flavour_invalid
)
15389 inst
.instruction
|= enctab
[flavour
];
15391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15393 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15394 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15395 inst
.instruction
|= neon_quad (rs
) << 6;
15396 inst
.instruction
|= 2 << 18;
15398 neon_dp_fixup (&inst
);
15403 /* Half-precision conversions for Advanced SIMD -- neon. */
15408 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15410 as_bad (_("operand size must match register width"));
15415 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15417 as_bad (_("operand size must match register width"));
15422 inst
.instruction
= 0x3b60600;
15424 inst
.instruction
= 0x3b60700;
15426 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15427 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15428 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15429 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15430 neon_dp_fixup (&inst
);
15434 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15435 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15436 do_vfp_nsyn_cvt (rs
, flavour
);
15438 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15443 do_neon_cvtr (void)
15445 do_neon_cvt_1 (neon_cvt_mode_x
);
15451 do_neon_cvt_1 (neon_cvt_mode_z
);
15455 do_neon_cvta (void)
15457 do_neon_cvt_1 (neon_cvt_mode_a
);
15461 do_neon_cvtn (void)
15463 do_neon_cvt_1 (neon_cvt_mode_n
);
15467 do_neon_cvtp (void)
15469 do_neon_cvt_1 (neon_cvt_mode_p
);
15473 do_neon_cvtm (void)
15475 do_neon_cvt_1 (neon_cvt_mode_m
);
15479 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15482 mark_feature_used (&fpu_vfp_ext_armv8
);
15484 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15485 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15486 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15487 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15488 inst
.instruction
|= to
? 0x10000 : 0;
15489 inst
.instruction
|= t
? 0x80 : 0;
15490 inst
.instruction
|= is_double
? 0x100 : 0;
15491 do_vfp_cond_or_thumb ();
15495 do_neon_cvttb_1 (bfd_boolean t
)
15497 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15501 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15504 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15506 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15509 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15511 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15513 /* The VCVTB and VCVTT instructions with D-register operands
15514 don't work for SP only targets. */
15515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15519 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15521 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15523 /* The VCVTB and VCVTT instructions with D-register operands
15524 don't work for SP only targets. */
15525 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15529 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15536 do_neon_cvtb (void)
15538 do_neon_cvttb_1 (FALSE
);
15543 do_neon_cvtt (void)
15545 do_neon_cvttb_1 (TRUE
);
15549 neon_move_immediate (void)
15551 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15552 struct neon_type_el et
= neon_check_type (2, rs
,
15553 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15554 unsigned immlo
, immhi
= 0, immbits
;
15555 int op
, cmode
, float_p
;
15557 constraint (et
.type
== NT_invtype
,
15558 _("operand size must be specified for immediate VMOV"));
15560 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15561 op
= (inst
.instruction
& (1 << 5)) != 0;
15563 immlo
= inst
.operands
[1].imm
;
15564 if (inst
.operands
[1].regisimm
)
15565 immhi
= inst
.operands
[1].reg
;
15567 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15568 _("immediate has bits set outside the operand size"));
15570 float_p
= inst
.operands
[1].immisfloat
;
15572 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15573 et
.size
, et
.type
)) == FAIL
)
15575 /* Invert relevant bits only. */
15576 neon_invert_size (&immlo
, &immhi
, et
.size
);
15577 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15578 with one or the other; those cases are caught by
15579 neon_cmode_for_move_imm. */
15581 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15582 &op
, et
.size
, et
.type
)) == FAIL
)
15584 first_error (_("immediate out of range"));
15589 inst
.instruction
&= ~(1 << 5);
15590 inst
.instruction
|= op
<< 5;
15592 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15593 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15594 inst
.instruction
|= neon_quad (rs
) << 6;
15595 inst
.instruction
|= cmode
<< 8;
15597 neon_write_immbits (immbits
);
15603 if (inst
.operands
[1].isreg
)
15605 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15607 NEON_ENCODE (INTEGER
, inst
);
15608 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15609 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15610 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15611 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15612 inst
.instruction
|= neon_quad (rs
) << 6;
15616 NEON_ENCODE (IMMED
, inst
);
15617 neon_move_immediate ();
15620 neon_dp_fixup (&inst
);
15623 /* Encode instructions of form:
15625 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15626 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15629 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15631 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15632 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15635 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15636 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15637 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15638 inst
.instruction
|= neon_logbits (size
) << 20;
15640 neon_dp_fixup (&inst
);
15644 do_neon_dyadic_long (void)
15646 /* FIXME: Type checking for lengthening op. */
15647 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15648 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15649 neon_mixed_length (et
, et
.size
);
15653 do_neon_abal (void)
15655 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15656 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15657 neon_mixed_length (et
, et
.size
);
15661 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15663 if (inst
.operands
[2].isscalar
)
15665 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15666 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15667 NEON_ENCODE (SCALAR
, inst
);
15668 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15672 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15673 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15674 NEON_ENCODE (INTEGER
, inst
);
15675 neon_mixed_length (et
, et
.size
);
15680 do_neon_mac_maybe_scalar_long (void)
15682 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15686 do_neon_dyadic_wide (void)
15688 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15689 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15690 neon_mixed_length (et
, et
.size
);
15694 do_neon_dyadic_narrow (void)
15696 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15697 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15698 /* Operand sign is unimportant, and the U bit is part of the opcode,
15699 so force the operand type to integer. */
15700 et
.type
= NT_integer
;
15701 neon_mixed_length (et
, et
.size
/ 2);
15705 do_neon_mul_sat_scalar_long (void)
15707 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15711 do_neon_vmull (void)
15713 if (inst
.operands
[2].isscalar
)
15714 do_neon_mac_maybe_scalar_long ();
15717 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15718 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15720 if (et
.type
== NT_poly
)
15721 NEON_ENCODE (POLY
, inst
);
15723 NEON_ENCODE (INTEGER
, inst
);
15725 /* For polynomial encoding the U bit must be zero, and the size must
15726 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15727 obviously, as 0b10). */
15730 /* Check we're on the correct architecture. */
15731 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15733 _("Instruction form not available on this architecture.");
15738 neon_mixed_length (et
, et
.size
);
15745 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15746 struct neon_type_el et
= neon_check_type (3, rs
,
15747 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15748 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15750 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15751 _("shift out of range"));
15752 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15753 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15754 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15755 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15756 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15757 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15758 inst
.instruction
|= neon_quad (rs
) << 6;
15759 inst
.instruction
|= imm
<< 8;
15761 neon_dp_fixup (&inst
);
15767 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15768 struct neon_type_el et
= neon_check_type (2, rs
,
15769 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15770 unsigned op
= (inst
.instruction
>> 7) & 3;
15771 /* N (width of reversed regions) is encoded as part of the bitmask. We
15772 extract it here to check the elements to be reversed are smaller.
15773 Otherwise we'd get a reserved instruction. */
15774 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15775 gas_assert (elsize
!= 0);
15776 constraint (et
.size
>= elsize
,
15777 _("elements must be smaller than reversal region"));
15778 neon_two_same (neon_quad (rs
), 1, et
.size
);
15784 if (inst
.operands
[1].isscalar
)
15786 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15787 struct neon_type_el et
= neon_check_type (2, rs
,
15788 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15789 unsigned sizebits
= et
.size
>> 3;
15790 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15791 int logsize
= neon_logbits (et
.size
);
15792 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15794 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15797 NEON_ENCODE (SCALAR
, inst
);
15798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15800 inst
.instruction
|= LOW4 (dm
);
15801 inst
.instruction
|= HI1 (dm
) << 5;
15802 inst
.instruction
|= neon_quad (rs
) << 6;
15803 inst
.instruction
|= x
<< 17;
15804 inst
.instruction
|= sizebits
<< 16;
15806 neon_dp_fixup (&inst
);
15810 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15811 struct neon_type_el et
= neon_check_type (2, rs
,
15812 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15813 /* Duplicate ARM register to lanes of vector. */
15814 NEON_ENCODE (ARMREG
, inst
);
15817 case 8: inst
.instruction
|= 0x400000; break;
15818 case 16: inst
.instruction
|= 0x000020; break;
15819 case 32: inst
.instruction
|= 0x000000; break;
15822 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15823 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15824 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15825 inst
.instruction
|= neon_quad (rs
) << 21;
15826 /* The encoding for this instruction is identical for the ARM and Thumb
15827 variants, except for the condition field. */
15828 do_vfp_cond_or_thumb ();
15832 /* VMOV has particularly many variations. It can be one of:
15833 0. VMOV<c><q> <Qd>, <Qm>
15834 1. VMOV<c><q> <Dd>, <Dm>
15835 (Register operations, which are VORR with Rm = Rn.)
15836 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15837 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15839 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15840 (ARM register to scalar.)
15841 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15842 (Two ARM registers to vector.)
15843 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15844 (Scalar to ARM register.)
15845 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15846 (Vector to two ARM registers.)
15847 8. VMOV.F32 <Sd>, <Sm>
15848 9. VMOV.F64 <Dd>, <Dm>
15849 (VFP register moves.)
15850 10. VMOV.F32 <Sd>, #imm
15851 11. VMOV.F64 <Dd>, #imm
15852 (VFP float immediate load.)
15853 12. VMOV <Rd>, <Sm>
15854 (VFP single to ARM reg.)
15855 13. VMOV <Sd>, <Rm>
15856 (ARM reg to VFP single.)
15857 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15858 (Two ARM regs to two VFP singles.)
15859 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15860 (Two VFP singles to two ARM regs.)
15862 These cases can be disambiguated using neon_select_shape, except cases 1/9
15863 and 3/11 which depend on the operand type too.
15865 All the encoded bits are hardcoded by this function.
15867 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15868 Cases 5, 7 may be used with VFPv2 and above.
15870 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15871 can specify a type where it doesn't make sense to, and is ignored). */
15876 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15877 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15879 struct neon_type_el et
;
15880 const char *ldconst
= 0;
15884 case NS_DD
: /* case 1/9. */
15885 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15886 /* It is not an error here if no type is given. */
15888 if (et
.type
== NT_float
&& et
.size
== 64)
15890 do_vfp_nsyn_opcode ("fcpyd");
15893 /* fall through. */
15895 case NS_QQ
: /* case 0/1. */
15897 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15899 /* The architecture manual I have doesn't explicitly state which
15900 value the U bit should have for register->register moves, but
15901 the equivalent VORR instruction has U = 0, so do that. */
15902 inst
.instruction
= 0x0200110;
15903 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15904 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15905 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15907 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15908 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15909 inst
.instruction
|= neon_quad (rs
) << 6;
15911 neon_dp_fixup (&inst
);
15915 case NS_DI
: /* case 3/11. */
15916 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15918 if (et
.type
== NT_float
&& et
.size
== 64)
15920 /* case 11 (fconstd). */
15921 ldconst
= "fconstd";
15922 goto encode_fconstd
;
15924 /* fall through. */
15926 case NS_QI
: /* case 2/3. */
15927 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15929 inst
.instruction
= 0x0800010;
15930 neon_move_immediate ();
15931 neon_dp_fixup (&inst
);
15934 case NS_SR
: /* case 4. */
15936 unsigned bcdebits
= 0;
15938 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15939 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15941 /* .<size> is optional here, defaulting to .32. */
15942 if (inst
.vectype
.elems
== 0
15943 && inst
.operands
[0].vectype
.type
== NT_invtype
15944 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15946 inst
.vectype
.el
[0].type
= NT_untyped
;
15947 inst
.vectype
.el
[0].size
= 32;
15948 inst
.vectype
.elems
= 1;
15951 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15952 logsize
= neon_logbits (et
.size
);
15954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15956 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15957 && et
.size
!= 32, _(BAD_FPU
));
15958 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15959 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15963 case 8: bcdebits
= 0x8; break;
15964 case 16: bcdebits
= 0x1; break;
15965 case 32: bcdebits
= 0x0; break;
15969 bcdebits
|= x
<< logsize
;
15971 inst
.instruction
= 0xe000b10;
15972 do_vfp_cond_or_thumb ();
15973 inst
.instruction
|= LOW4 (dn
) << 16;
15974 inst
.instruction
|= HI1 (dn
) << 7;
15975 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15976 inst
.instruction
|= (bcdebits
& 3) << 5;
15977 inst
.instruction
|= (bcdebits
>> 2) << 21;
15981 case NS_DRR
: /* case 5 (fmdrr). */
15982 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15985 inst
.instruction
= 0xc400b10;
15986 do_vfp_cond_or_thumb ();
15987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15989 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15990 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15993 case NS_RS
: /* case 6. */
15996 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15997 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15998 unsigned abcdebits
= 0;
16000 /* .<dt> is optional here, defaulting to .32. */
16001 if (inst
.vectype
.elems
== 0
16002 && inst
.operands
[0].vectype
.type
== NT_invtype
16003 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16005 inst
.vectype
.el
[0].type
= NT_untyped
;
16006 inst
.vectype
.el
[0].size
= 32;
16007 inst
.vectype
.elems
= 1;
16010 et
= neon_check_type (2, NS_NULL
,
16011 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16012 logsize
= neon_logbits (et
.size
);
16014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16017 && et
.size
!= 32, _(BAD_FPU
));
16018 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16019 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16023 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16024 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16025 case 32: abcdebits
= 0x00; break;
16029 abcdebits
|= x
<< logsize
;
16030 inst
.instruction
= 0xe100b10;
16031 do_vfp_cond_or_thumb ();
16032 inst
.instruction
|= LOW4 (dn
) << 16;
16033 inst
.instruction
|= HI1 (dn
) << 7;
16034 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16035 inst
.instruction
|= (abcdebits
& 3) << 5;
16036 inst
.instruction
|= (abcdebits
>> 2) << 21;
16040 case NS_RRD
: /* case 7 (fmrrd). */
16041 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16044 inst
.instruction
= 0xc500b10;
16045 do_vfp_cond_or_thumb ();
16046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16048 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16049 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16052 case NS_FF
: /* case 8 (fcpys). */
16053 do_vfp_nsyn_opcode ("fcpys");
16056 case NS_FI
: /* case 10 (fconsts). */
16057 ldconst
= "fconsts";
16059 if (is_quarter_float (inst
.operands
[1].imm
))
16061 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16062 do_vfp_nsyn_opcode (ldconst
);
16065 first_error (_("immediate out of range"));
16068 case NS_RF
: /* case 12 (fmrs). */
16069 do_vfp_nsyn_opcode ("fmrs");
16072 case NS_FR
: /* case 13 (fmsr). */
16073 do_vfp_nsyn_opcode ("fmsr");
16076 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16077 (one of which is a list), but we have parsed four. Do some fiddling to
16078 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16080 case NS_RRFF
: /* case 14 (fmrrs). */
16081 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16082 _("VFP registers must be adjacent"));
16083 inst
.operands
[2].imm
= 2;
16084 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16085 do_vfp_nsyn_opcode ("fmrrs");
16088 case NS_FFRR
: /* case 15 (fmsrr). */
16089 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16090 _("VFP registers must be adjacent"));
16091 inst
.operands
[1] = inst
.operands
[2];
16092 inst
.operands
[2] = inst
.operands
[3];
16093 inst
.operands
[0].imm
= 2;
16094 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16095 do_vfp_nsyn_opcode ("fmsrr");
16099 /* neon_select_shape has determined that the instruction
16100 shape is wrong and has already set the error message. */
16109 do_neon_rshift_round_imm (void)
16111 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16112 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16113 int imm
= inst
.operands
[2].imm
;
16115 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16118 inst
.operands
[2].present
= 0;
16123 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16124 _("immediate out of range for shift"));
16125 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16130 do_neon_movl (void)
16132 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16133 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16134 unsigned sizebits
= et
.size
>> 3;
16135 inst
.instruction
|= sizebits
<< 19;
16136 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16142 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16143 struct neon_type_el et
= neon_check_type (2, rs
,
16144 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16145 NEON_ENCODE (INTEGER
, inst
);
16146 neon_two_same (neon_quad (rs
), 1, et
.size
);
16150 do_neon_zip_uzp (void)
16152 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16153 struct neon_type_el et
= neon_check_type (2, rs
,
16154 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16155 if (rs
== NS_DD
&& et
.size
== 32)
16157 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16158 inst
.instruction
= N_MNEM_vtrn
;
16162 neon_two_same (neon_quad (rs
), 1, et
.size
);
16166 do_neon_sat_abs_neg (void)
16168 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16169 struct neon_type_el et
= neon_check_type (2, rs
,
16170 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16171 neon_two_same (neon_quad (rs
), 1, et
.size
);
16175 do_neon_pair_long (void)
16177 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16178 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16179 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16180 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16181 neon_two_same (neon_quad (rs
), 1, et
.size
);
16185 do_neon_recip_est (void)
16187 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16188 struct neon_type_el et
= neon_check_type (2, rs
,
16189 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16190 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16191 neon_two_same (neon_quad (rs
), 1, et
.size
);
16197 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16198 struct neon_type_el et
= neon_check_type (2, rs
,
16199 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16200 neon_two_same (neon_quad (rs
), 1, et
.size
);
16206 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16207 struct neon_type_el et
= neon_check_type (2, rs
,
16208 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16209 neon_two_same (neon_quad (rs
), 1, et
.size
);
16215 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16216 struct neon_type_el et
= neon_check_type (2, rs
,
16217 N_EQK
| N_INT
, N_8
| N_KEY
);
16218 neon_two_same (neon_quad (rs
), 1, et
.size
);
16224 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16225 neon_two_same (neon_quad (rs
), 1, -1);
16229 do_neon_tbl_tbx (void)
16231 unsigned listlenbits
;
16232 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16234 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16236 first_error (_("bad list length for table lookup"));
16240 listlenbits
= inst
.operands
[1].imm
- 1;
16241 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16242 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16243 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16244 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16245 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16246 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16247 inst
.instruction
|= listlenbits
<< 8;
16249 neon_dp_fixup (&inst
);
16253 do_neon_ldm_stm (void)
16255 /* P, U and L bits are part of bitmask. */
16256 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16257 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16259 if (inst
.operands
[1].issingle
)
16261 do_vfp_nsyn_ldm_stm (is_dbmode
);
16265 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16266 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16268 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16269 _("register list must contain at least 1 and at most 16 "
16272 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16273 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16274 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16275 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16277 inst
.instruction
|= offsetbits
;
16279 do_vfp_cond_or_thumb ();
16283 do_neon_ldr_str (void)
16285 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16287 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16288 And is UNPREDICTABLE in thumb mode. */
16290 && inst
.operands
[1].reg
== REG_PC
16291 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16294 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16295 else if (warn_on_deprecated
)
16296 as_tsktsk (_("Use of PC here is deprecated"));
16299 if (inst
.operands
[0].issingle
)
16302 do_vfp_nsyn_opcode ("flds");
16304 do_vfp_nsyn_opcode ("fsts");
16309 do_vfp_nsyn_opcode ("fldd");
16311 do_vfp_nsyn_opcode ("fstd");
16315 /* "interleave" version also handles non-interleaving register VLD1/VST1
16319 do_neon_ld_st_interleave (void)
16321 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16322 N_8
| N_16
| N_32
| N_64
);
16323 unsigned alignbits
= 0;
16325 /* The bits in this table go:
16326 0: register stride of one (0) or two (1)
16327 1,2: register list length, minus one (1, 2, 3, 4).
16328 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16329 We use -1 for invalid entries. */
16330 const int typetable
[] =
16332 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16333 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16334 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16335 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16339 if (et
.type
== NT_invtype
)
16342 if (inst
.operands
[1].immisalign
)
16343 switch (inst
.operands
[1].imm
>> 8)
16345 case 64: alignbits
= 1; break;
16347 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16348 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16349 goto bad_alignment
;
16353 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16354 goto bad_alignment
;
16359 first_error (_("bad alignment"));
16363 inst
.instruction
|= alignbits
<< 4;
16364 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16366 /* Bits [4:6] of the immediate in a list specifier encode register stride
16367 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16368 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16369 up the right value for "type" in a table based on this value and the given
16370 list style, then stick it back. */
16371 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16372 | (((inst
.instruction
>> 8) & 3) << 3);
16374 typebits
= typetable
[idx
];
16376 constraint (typebits
== -1, _("bad list type for instruction"));
16377 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16378 _("bad element type for instruction"));
16380 inst
.instruction
&= ~0xf00;
16381 inst
.instruction
|= typebits
<< 8;
16384 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16385 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16386 otherwise. The variable arguments are a list of pairs of legal (size, align)
16387 values, terminated with -1. */
16390 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16393 int result
= FAIL
, thissize
, thisalign
;
16395 if (!inst
.operands
[1].immisalign
)
16401 va_start (ap
, do_align
);
16405 thissize
= va_arg (ap
, int);
16406 if (thissize
== -1)
16408 thisalign
= va_arg (ap
, int);
16410 if (size
== thissize
&& align
== thisalign
)
16413 while (result
!= SUCCESS
);
16417 if (result
== SUCCESS
)
16420 first_error (_("unsupported alignment for instruction"));
16426 do_neon_ld_st_lane (void)
16428 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16429 int align_good
, do_align
= 0;
16430 int logsize
= neon_logbits (et
.size
);
16431 int align
= inst
.operands
[1].imm
>> 8;
16432 int n
= (inst
.instruction
>> 8) & 3;
16433 int max_el
= 64 / et
.size
;
16435 if (et
.type
== NT_invtype
)
16438 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16439 _("bad list length"));
16440 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16441 _("scalar index out of range"));
16442 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16444 _("stride of 2 unavailable when element size is 8"));
16448 case 0: /* VLD1 / VST1. */
16449 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16451 if (align_good
== FAIL
)
16455 unsigned alignbits
= 0;
16458 case 16: alignbits
= 0x1; break;
16459 case 32: alignbits
= 0x3; break;
16462 inst
.instruction
|= alignbits
<< 4;
16466 case 1: /* VLD2 / VST2. */
16467 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16469 if (align_good
== FAIL
)
16472 inst
.instruction
|= 1 << 4;
16475 case 2: /* VLD3 / VST3. */
16476 constraint (inst
.operands
[1].immisalign
,
16477 _("can't use alignment with this instruction"));
16480 case 3: /* VLD4 / VST4. */
16481 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16482 16, 64, 32, 64, 32, 128, -1);
16483 if (align_good
== FAIL
)
16487 unsigned alignbits
= 0;
16490 case 8: alignbits
= 0x1; break;
16491 case 16: alignbits
= 0x1; break;
16492 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16495 inst
.instruction
|= alignbits
<< 4;
16502 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16503 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16504 inst
.instruction
|= 1 << (4 + logsize
);
16506 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16507 inst
.instruction
|= logsize
<< 10;
16510 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16513 do_neon_ld_dup (void)
16515 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16516 int align_good
, do_align
= 0;
16518 if (et
.type
== NT_invtype
)
16521 switch ((inst
.instruction
>> 8) & 3)
16523 case 0: /* VLD1. */
16524 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16525 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16526 &do_align
, 16, 16, 32, 32, -1);
16527 if (align_good
== FAIL
)
16529 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16532 case 2: inst
.instruction
|= 1 << 5; break;
16533 default: first_error (_("bad list length")); return;
16535 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16538 case 1: /* VLD2. */
16539 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16540 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16541 if (align_good
== FAIL
)
16543 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16544 _("bad list length"));
16545 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16546 inst
.instruction
|= 1 << 5;
16547 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16550 case 2: /* VLD3. */
16551 constraint (inst
.operands
[1].immisalign
,
16552 _("can't use alignment with this instruction"));
16553 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16554 _("bad list length"));
16555 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16556 inst
.instruction
|= 1 << 5;
16557 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16560 case 3: /* VLD4. */
16562 int align
= inst
.operands
[1].imm
>> 8;
16563 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16564 16, 64, 32, 64, 32, 128, -1);
16565 if (align_good
== FAIL
)
16567 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16568 _("bad list length"));
16569 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16570 inst
.instruction
|= 1 << 5;
16571 if (et
.size
== 32 && align
== 128)
16572 inst
.instruction
|= 0x3 << 6;
16574 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16581 inst
.instruction
|= do_align
<< 4;
16584 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16585 apart from bits [11:4]. */
16588 do_neon_ldx_stx (void)
16590 if (inst
.operands
[1].isreg
)
16591 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16593 switch (NEON_LANE (inst
.operands
[0].imm
))
16595 case NEON_INTERLEAVE_LANES
:
16596 NEON_ENCODE (INTERLV
, inst
);
16597 do_neon_ld_st_interleave ();
16600 case NEON_ALL_LANES
:
16601 NEON_ENCODE (DUP
, inst
);
16602 if (inst
.instruction
== N_INV
)
16604 first_error ("only loads support such operands");
16611 NEON_ENCODE (LANE
, inst
);
16612 do_neon_ld_st_lane ();
16615 /* L bit comes from bit mask. */
16616 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16617 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16618 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16620 if (inst
.operands
[1].postind
)
16622 int postreg
= inst
.operands
[1].imm
& 0xf;
16623 constraint (!inst
.operands
[1].immisreg
,
16624 _("post-index must be a register"));
16625 constraint (postreg
== 0xd || postreg
== 0xf,
16626 _("bad register for post-index"));
16627 inst
.instruction
|= postreg
;
16631 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16632 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16633 || inst
.reloc
.exp
.X_add_number
!= 0,
16636 if (inst
.operands
[1].writeback
)
16638 inst
.instruction
|= 0xd;
16641 inst
.instruction
|= 0xf;
16645 inst
.instruction
|= 0xf9000000;
16647 inst
.instruction
|= 0xf4000000;
16652 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16654 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16655 D register operands. */
16656 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16657 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16660 NEON_ENCODE (FPV8
, inst
);
16663 do_vfp_sp_dyadic ();
16665 do_vfp_dp_rd_rn_rm ();
16668 inst
.instruction
|= 0x100;
16670 inst
.instruction
|= 0xf0000000;
16676 set_it_insn_type (OUTSIDE_IT_INSN
);
16678 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16679 first_error (_("invalid instruction shape"));
16685 set_it_insn_type (OUTSIDE_IT_INSN
);
16687 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16690 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16693 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16697 do_vrint_1 (enum neon_cvt_mode mode
)
16699 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16700 struct neon_type_el et
;
16705 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16706 D register operands. */
16707 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16711 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16712 if (et
.type
!= NT_invtype
)
16714 /* VFP encodings. */
16715 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16716 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16717 set_it_insn_type (OUTSIDE_IT_INSN
);
16719 NEON_ENCODE (FPV8
, inst
);
16721 do_vfp_sp_monadic ();
16723 do_vfp_dp_rd_rm ();
16727 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16728 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16729 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16730 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16731 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16732 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16733 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16737 inst
.instruction
|= (rs
== NS_DD
) << 8;
16738 do_vfp_cond_or_thumb ();
16742 /* Neon encodings (or something broken...). */
16744 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16746 if (et
.type
== NT_invtype
)
16749 set_it_insn_type (OUTSIDE_IT_INSN
);
16750 NEON_ENCODE (FLOAT
, inst
);
16752 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16757 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16759 inst
.instruction
|= neon_quad (rs
) << 6;
16762 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16763 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16764 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16765 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16766 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16767 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16768 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16773 inst
.instruction
|= 0xfc000000;
16775 inst
.instruction
|= 0xf0000000;
16782 do_vrint_1 (neon_cvt_mode_x
);
16788 do_vrint_1 (neon_cvt_mode_z
);
16794 do_vrint_1 (neon_cvt_mode_r
);
16800 do_vrint_1 (neon_cvt_mode_a
);
16806 do_vrint_1 (neon_cvt_mode_n
);
16812 do_vrint_1 (neon_cvt_mode_p
);
16818 do_vrint_1 (neon_cvt_mode_m
);
16821 /* Crypto v1 instructions. */
16823 do_crypto_2op_1 (unsigned elttype
, int op
)
16825 set_it_insn_type (OUTSIDE_IT_INSN
);
16827 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16833 NEON_ENCODE (INTEGER
, inst
);
16834 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16835 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16836 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16837 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16839 inst
.instruction
|= op
<< 6;
16842 inst
.instruction
|= 0xfc000000;
16844 inst
.instruction
|= 0xf0000000;
16848 do_crypto_3op_1 (int u
, int op
)
16850 set_it_insn_type (OUTSIDE_IT_INSN
);
16852 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16853 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16858 NEON_ENCODE (INTEGER
, inst
);
16859 neon_three_same (1, u
, 8 << op
);
16865 do_crypto_2op_1 (N_8
, 0);
16871 do_crypto_2op_1 (N_8
, 1);
16877 do_crypto_2op_1 (N_8
, 2);
16883 do_crypto_2op_1 (N_8
, 3);
16889 do_crypto_3op_1 (0, 0);
16895 do_crypto_3op_1 (0, 1);
16901 do_crypto_3op_1 (0, 2);
16907 do_crypto_3op_1 (0, 3);
16913 do_crypto_3op_1 (1, 0);
16919 do_crypto_3op_1 (1, 1);
16923 do_sha256su1 (void)
16925 do_crypto_3op_1 (1, 2);
16931 do_crypto_2op_1 (N_32
, -1);
16937 do_crypto_2op_1 (N_32
, 0);
16941 do_sha256su0 (void)
16943 do_crypto_2op_1 (N_32
, 1);
16947 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16949 unsigned int Rd
= inst
.operands
[0].reg
;
16950 unsigned int Rn
= inst
.operands
[1].reg
;
16951 unsigned int Rm
= inst
.operands
[2].reg
;
16953 set_it_insn_type (OUTSIDE_IT_INSN
);
16954 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16955 inst
.instruction
|= LOW4 (Rn
) << 16;
16956 inst
.instruction
|= LOW4 (Rm
);
16957 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16958 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16960 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16961 as_warn (UNPRED_REG ("r15"));
16962 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16963 as_warn (UNPRED_REG ("r13"));
17003 /* Overall per-instruction processing. */
17005 /* We need to be able to fix up arbitrary expressions in some statements.
17006 This is so that we can handle symbols that are an arbitrary distance from
17007 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17008 which returns part of an address in a form which will be valid for
17009 a data instruction. We do this by pushing the expression into a symbol
17010 in the expr_section, and creating a fix for that. */
17013 fix_new_arm (fragS
* frag
,
17027 /* Create an absolute valued symbol, so we have something to
17028 refer to in the object file. Unfortunately for us, gas's
17029 generic expression parsing will already have folded out
17030 any use of .set foo/.type foo %function that may have
17031 been used to set type information of the target location,
17032 that's being specified symbolically. We have to presume
17033 the user knows what they are doing. */
17037 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17039 symbol
= symbol_find_or_make (name
);
17040 S_SET_SEGMENT (symbol
, absolute_section
);
17041 symbol_set_frag (symbol
, &zero_address_frag
);
17042 S_SET_VALUE (symbol
, exp
->X_add_number
);
17043 exp
->X_op
= O_symbol
;
17044 exp
->X_add_symbol
= symbol
;
17045 exp
->X_add_number
= 0;
17051 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17052 (enum bfd_reloc_code_real
) reloc
);
17056 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17057 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17061 /* Mark whether the fix is to a THUMB instruction, or an ARM
17063 new_fix
->tc_fix_data
= thumb_mode
;
17066 /* Create a frg for an instruction requiring relaxation. */
17068 output_relax_insn (void)
17074 /* The size of the instruction is unknown, so tie the debug info to the
17075 start of the instruction. */
17076 dwarf2_emit_insn (0);
17078 switch (inst
.reloc
.exp
.X_op
)
17081 sym
= inst
.reloc
.exp
.X_add_symbol
;
17082 offset
= inst
.reloc
.exp
.X_add_number
;
17086 offset
= inst
.reloc
.exp
.X_add_number
;
17089 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17093 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17094 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17095 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17098 /* Write a 32-bit thumb instruction to buf. */
17100 put_thumb32_insn (char * buf
, unsigned long insn
)
17102 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17103 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17107 output_inst (const char * str
)
17113 as_bad ("%s -- `%s'", inst
.error
, str
);
17118 output_relax_insn ();
17121 if (inst
.size
== 0)
17124 to
= frag_more (inst
.size
);
17125 /* PR 9814: Record the thumb mode into the current frag so that we know
17126 what type of NOP padding to use, if necessary. We override any previous
17127 setting so that if the mode has changed then the NOPS that we use will
17128 match the encoding of the last instruction in the frag. */
17129 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17131 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17133 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17134 put_thumb32_insn (to
, inst
.instruction
);
17136 else if (inst
.size
> INSN_SIZE
)
17138 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17139 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17140 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17143 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17145 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17146 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17147 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17150 dwarf2_emit_insn (inst
.size
);
17154 output_it_inst (int cond
, int mask
, char * to
)
17156 unsigned long instruction
= 0xbf00;
17159 instruction
|= mask
;
17160 instruction
|= cond
<< 4;
17164 to
= frag_more (2);
17166 dwarf2_emit_insn (2);
17170 md_number_to_chars (to
, instruction
, 2);
17175 /* Tag values used in struct asm_opcode's tag field. */
17178 OT_unconditional
, /* Instruction cannot be conditionalized.
17179 The ARM condition field is still 0xE. */
17180 OT_unconditionalF
, /* Instruction cannot be conditionalized
17181 and carries 0xF in its ARM condition field. */
17182 OT_csuffix
, /* Instruction takes a conditional suffix. */
17183 OT_csuffixF
, /* Some forms of the instruction take a conditional
17184 suffix, others place 0xF where the condition field
17186 OT_cinfix3
, /* Instruction takes a conditional infix,
17187 beginning at character index 3. (In
17188 unified mode, it becomes a suffix.) */
17189 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17190 tsts, cmps, cmns, and teqs. */
17191 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17192 character index 3, even in unified mode. Used for
17193 legacy instructions where suffix and infix forms
17194 may be ambiguous. */
17195 OT_csuf_or_in3
, /* Instruction takes either a conditional
17196 suffix or an infix at character index 3. */
17197 OT_odd_infix_unc
, /* This is the unconditional variant of an
17198 instruction that takes a conditional infix
17199 at an unusual position. In unified mode,
17200 this variant will accept a suffix. */
17201 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17202 are the conditional variants of instructions that
17203 take conditional infixes in unusual positions.
17204 The infix appears at character index
17205 (tag - OT_odd_infix_0). These are not accepted
17206 in unified mode. */
17209 /* Subroutine of md_assemble, responsible for looking up the primary
17210 opcode from the mnemonic the user wrote. STR points to the
17211 beginning of the mnemonic.
17213 This is not simply a hash table lookup, because of conditional
17214 variants. Most instructions have conditional variants, which are
17215 expressed with a _conditional affix_ to the mnemonic. If we were
17216 to encode each conditional variant as a literal string in the opcode
17217 table, it would have approximately 20,000 entries.
17219 Most mnemonics take this affix as a suffix, and in unified syntax,
17220 'most' is upgraded to 'all'. However, in the divided syntax, some
17221 instructions take the affix as an infix, notably the s-variants of
17222 the arithmetic instructions. Of those instructions, all but six
17223 have the infix appear after the third character of the mnemonic.
17225 Accordingly, the algorithm for looking up primary opcodes given
17228 1. Look up the identifier in the opcode table.
17229 If we find a match, go to step U.
17231 2. Look up the last two characters of the identifier in the
17232 conditions table. If we find a match, look up the first N-2
17233 characters of the identifier in the opcode table. If we
17234 find a match, go to step CE.
17236 3. Look up the fourth and fifth characters of the identifier in
17237 the conditions table. If we find a match, extract those
17238 characters from the identifier, and look up the remaining
17239 characters in the opcode table. If we find a match, go
17244 U. Examine the tag field of the opcode structure, in case this is
17245 one of the six instructions with its conditional infix in an
17246 unusual place. If it is, the tag tells us where to find the
17247 infix; look it up in the conditions table and set inst.cond
17248 accordingly. Otherwise, this is an unconditional instruction.
17249 Again set inst.cond accordingly. Return the opcode structure.
17251 CE. Examine the tag field to make sure this is an instruction that
17252 should receive a conditional suffix. If it is not, fail.
17253 Otherwise, set inst.cond from the suffix we already looked up,
17254 and return the opcode structure.
17256 CM. Examine the tag field to make sure this is an instruction that
17257 should receive a conditional infix after the third character.
17258 If it is not, fail. Otherwise, undo the edits to the current
17259 line of input and proceed as for case CE. */
17261 static const struct asm_opcode
*
17262 opcode_lookup (char **str
)
17266 const struct asm_opcode
*opcode
;
17267 const struct asm_cond
*cond
;
17270 /* Scan up to the end of the mnemonic, which must end in white space,
17271 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17272 for (base
= end
= *str
; *end
!= '\0'; end
++)
17273 if (*end
== ' ' || *end
== '.')
17279 /* Handle a possible width suffix and/or Neon type suffix. */
17284 /* The .w and .n suffixes are only valid if the unified syntax is in
17286 if (unified_syntax
&& end
[1] == 'w')
17288 else if (unified_syntax
&& end
[1] == 'n')
17293 inst
.vectype
.elems
= 0;
17295 *str
= end
+ offset
;
17297 if (end
[offset
] == '.')
17299 /* See if we have a Neon type suffix (possible in either unified or
17300 non-unified ARM syntax mode). */
17301 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17304 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17310 /* Look for unaffixed or special-case affixed mnemonic. */
17311 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17316 if (opcode
->tag
< OT_odd_infix_0
)
17318 inst
.cond
= COND_ALWAYS
;
17322 if (warn_on_deprecated
&& unified_syntax
)
17323 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17324 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17325 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17328 inst
.cond
= cond
->value
;
17332 /* Cannot have a conditional suffix on a mnemonic of less than two
17334 if (end
- base
< 3)
17337 /* Look for suffixed mnemonic. */
17339 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17340 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17342 if (opcode
&& cond
)
17345 switch (opcode
->tag
)
17347 case OT_cinfix3_legacy
:
17348 /* Ignore conditional suffixes matched on infix only mnemonics. */
17352 case OT_cinfix3_deprecated
:
17353 case OT_odd_infix_unc
:
17354 if (!unified_syntax
)
17356 /* else fall through */
17360 case OT_csuf_or_in3
:
17361 inst
.cond
= cond
->value
;
17364 case OT_unconditional
:
17365 case OT_unconditionalF
:
17367 inst
.cond
= cond
->value
;
17370 /* Delayed diagnostic. */
17371 inst
.error
= BAD_COND
;
17372 inst
.cond
= COND_ALWAYS
;
17381 /* Cannot have a usual-position infix on a mnemonic of less than
17382 six characters (five would be a suffix). */
17383 if (end
- base
< 6)
17386 /* Look for infixed mnemonic in the usual position. */
17388 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17392 memcpy (save
, affix
, 2);
17393 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17394 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17396 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17397 memcpy (affix
, save
, 2);
17400 && (opcode
->tag
== OT_cinfix3
17401 || opcode
->tag
== OT_cinfix3_deprecated
17402 || opcode
->tag
== OT_csuf_or_in3
17403 || opcode
->tag
== OT_cinfix3_legacy
))
17406 if (warn_on_deprecated
&& unified_syntax
17407 && (opcode
->tag
== OT_cinfix3
17408 || opcode
->tag
== OT_cinfix3_deprecated
))
17409 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17411 inst
.cond
= cond
->value
;
17418 /* This function generates an initial IT instruction, leaving its block
17419 virtually open for the new instructions. Eventually,
17420 the mask will be updated by now_it_add_mask () each time
17421 a new instruction needs to be included in the IT block.
17422 Finally, the block is closed with close_automatic_it_block ().
17423 The block closure can be requested either from md_assemble (),
17424 a tencode (), or due to a label hook. */
17427 new_automatic_it_block (int cond
)
17429 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17430 now_it
.mask
= 0x18;
17432 now_it
.block_length
= 1;
17433 mapping_state (MAP_THUMB
);
17434 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17435 now_it
.warn_deprecated
= FALSE
;
17436 now_it
.insn_cond
= TRUE
;
17439 /* Close an automatic IT block.
17440 See comments in new_automatic_it_block (). */
17443 close_automatic_it_block (void)
17445 now_it
.mask
= 0x10;
17446 now_it
.block_length
= 0;
17449 /* Update the mask of the current automatically-generated IT
17450 instruction. See comments in new_automatic_it_block (). */
17453 now_it_add_mask (int cond
)
17455 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17456 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17457 | ((bitvalue) << (nbit)))
17458 const int resulting_bit
= (cond
& 1);
17460 now_it
.mask
&= 0xf;
17461 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17463 (5 - now_it
.block_length
));
17464 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17466 ((5 - now_it
.block_length
) - 1) );
17467 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17470 #undef SET_BIT_VALUE
17473 /* The IT blocks handling machinery is accessed through the these functions:
17474 it_fsm_pre_encode () from md_assemble ()
17475 set_it_insn_type () optional, from the tencode functions
17476 set_it_insn_type_last () ditto
17477 in_it_block () ditto
17478 it_fsm_post_encode () from md_assemble ()
17479 force_automatic_it_block_close () from label habdling functions
17482 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17483 initializing the IT insn type with a generic initial value depending
17484 on the inst.condition.
17485 2) During the tencode function, two things may happen:
17486 a) The tencode function overrides the IT insn type by
17487 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17488 b) The tencode function queries the IT block state by
17489 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17491 Both set_it_insn_type and in_it_block run the internal FSM state
17492 handling function (handle_it_state), because: a) setting the IT insn
17493 type may incur in an invalid state (exiting the function),
17494 and b) querying the state requires the FSM to be updated.
17495 Specifically we want to avoid creating an IT block for conditional
17496 branches, so it_fsm_pre_encode is actually a guess and we can't
17497 determine whether an IT block is required until the tencode () routine
17498 has decided what type of instruction this actually it.
17499 Because of this, if set_it_insn_type and in_it_block have to be used,
17500 set_it_insn_type has to be called first.
17502 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17503 determines the insn IT type depending on the inst.cond code.
17504 When a tencode () routine encodes an instruction that can be
17505 either outside an IT block, or, in the case of being inside, has to be
17506 the last one, set_it_insn_type_last () will determine the proper
17507 IT instruction type based on the inst.cond code. Otherwise,
17508 set_it_insn_type can be called for overriding that logic or
17509 for covering other cases.
17511 Calling handle_it_state () may not transition the IT block state to
17512 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17513 still queried. Instead, if the FSM determines that the state should
17514 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17515 after the tencode () function: that's what it_fsm_post_encode () does.
17517 Since in_it_block () calls the state handling function to get an
17518 updated state, an error may occur (due to invalid insns combination).
17519 In that case, inst.error is set.
17520 Therefore, inst.error has to be checked after the execution of
17521 the tencode () routine.
17523 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17524 any pending state change (if any) that didn't take place in
17525 handle_it_state () as explained above. */
17528 it_fsm_pre_encode (void)
17530 if (inst
.cond
!= COND_ALWAYS
)
17531 inst
.it_insn_type
= INSIDE_IT_INSN
;
17533 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17535 now_it
.state_handled
= 0;
17538 /* IT state FSM handling function. */
17541 handle_it_state (void)
17543 now_it
.state_handled
= 1;
17544 now_it
.insn_cond
= FALSE
;
17546 switch (now_it
.state
)
17548 case OUTSIDE_IT_BLOCK
:
17549 switch (inst
.it_insn_type
)
17551 case OUTSIDE_IT_INSN
:
17554 case INSIDE_IT_INSN
:
17555 case INSIDE_IT_LAST_INSN
:
17556 if (thumb_mode
== 0)
17559 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17560 as_tsktsk (_("Warning: conditional outside an IT block"\
17565 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17566 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17568 /* Automatically generate the IT instruction. */
17569 new_automatic_it_block (inst
.cond
);
17570 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17571 close_automatic_it_block ();
17575 inst
.error
= BAD_OUT_IT
;
17581 case IF_INSIDE_IT_LAST_INSN
:
17582 case NEUTRAL_IT_INSN
:
17586 now_it
.state
= MANUAL_IT_BLOCK
;
17587 now_it
.block_length
= 0;
17592 case AUTOMATIC_IT_BLOCK
:
17593 /* Three things may happen now:
17594 a) We should increment current it block size;
17595 b) We should close current it block (closing insn or 4 insns);
17596 c) We should close current it block and start a new one (due
17597 to incompatible conditions or
17598 4 insns-length block reached). */
17600 switch (inst
.it_insn_type
)
17602 case OUTSIDE_IT_INSN
:
17603 /* The closure of the block shall happen immediatelly,
17604 so any in_it_block () call reports the block as closed. */
17605 force_automatic_it_block_close ();
17608 case INSIDE_IT_INSN
:
17609 case INSIDE_IT_LAST_INSN
:
17610 case IF_INSIDE_IT_LAST_INSN
:
17611 now_it
.block_length
++;
17613 if (now_it
.block_length
> 4
17614 || !now_it_compatible (inst
.cond
))
17616 force_automatic_it_block_close ();
17617 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17618 new_automatic_it_block (inst
.cond
);
17622 now_it
.insn_cond
= TRUE
;
17623 now_it_add_mask (inst
.cond
);
17626 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17627 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17628 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17629 close_automatic_it_block ();
17632 case NEUTRAL_IT_INSN
:
17633 now_it
.block_length
++;
17634 now_it
.insn_cond
= TRUE
;
17636 if (now_it
.block_length
> 4)
17637 force_automatic_it_block_close ();
17639 now_it_add_mask (now_it
.cc
& 1);
17643 close_automatic_it_block ();
17644 now_it
.state
= MANUAL_IT_BLOCK
;
17649 case MANUAL_IT_BLOCK
:
17651 /* Check conditional suffixes. */
17652 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17655 now_it
.mask
&= 0x1f;
17656 is_last
= (now_it
.mask
== 0x10);
17657 now_it
.insn_cond
= TRUE
;
17659 switch (inst
.it_insn_type
)
17661 case OUTSIDE_IT_INSN
:
17662 inst
.error
= BAD_NOT_IT
;
17665 case INSIDE_IT_INSN
:
17666 if (cond
!= inst
.cond
)
17668 inst
.error
= BAD_IT_COND
;
17673 case INSIDE_IT_LAST_INSN
:
17674 case IF_INSIDE_IT_LAST_INSN
:
17675 if (cond
!= inst
.cond
)
17677 inst
.error
= BAD_IT_COND
;
17682 inst
.error
= BAD_BRANCH
;
17687 case NEUTRAL_IT_INSN
:
17688 /* The BKPT instruction is unconditional even in an IT block. */
17692 inst
.error
= BAD_IT_IT
;
17702 struct depr_insn_mask
17704 unsigned long pattern
;
17705 unsigned long mask
;
17706 const char* description
;
17709 /* List of 16-bit instruction patterns deprecated in an IT block in
17711 static const struct depr_insn_mask depr_it_insns
[] = {
17712 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17713 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17714 { 0xa000, 0xb800, N_("ADR") },
17715 { 0x4800, 0xf800, N_("Literal loads") },
17716 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17717 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17718 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17719 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17720 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17725 it_fsm_post_encode (void)
17729 if (!now_it
.state_handled
)
17730 handle_it_state ();
17732 if (now_it
.insn_cond
17733 && !now_it
.warn_deprecated
17734 && warn_on_deprecated
17735 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17737 if (inst
.instruction
>= 0x10000)
17739 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17740 "deprecated in ARMv8"));
17741 now_it
.warn_deprecated
= TRUE
;
17745 const struct depr_insn_mask
*p
= depr_it_insns
;
17747 while (p
->mask
!= 0)
17749 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17751 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17752 "of the following class are deprecated in ARMv8: "
17753 "%s"), p
->description
);
17754 now_it
.warn_deprecated
= TRUE
;
17762 if (now_it
.block_length
> 1)
17764 as_tsktsk (_("IT blocks containing more than one conditional "
17765 "instruction are deprecated in ARMv8"));
17766 now_it
.warn_deprecated
= TRUE
;
17770 is_last
= (now_it
.mask
== 0x10);
17773 now_it
.state
= OUTSIDE_IT_BLOCK
;
17779 force_automatic_it_block_close (void)
17781 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17783 close_automatic_it_block ();
17784 now_it
.state
= OUTSIDE_IT_BLOCK
;
17792 if (!now_it
.state_handled
)
17793 handle_it_state ();
17795 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17799 md_assemble (char *str
)
17802 const struct asm_opcode
* opcode
;
17804 /* Align the previous label if needed. */
17805 if (last_label_seen
!= NULL
)
17807 symbol_set_frag (last_label_seen
, frag_now
);
17808 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17809 S_SET_SEGMENT (last_label_seen
, now_seg
);
17812 memset (&inst
, '\0', sizeof (inst
));
17813 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17815 opcode
= opcode_lookup (&p
);
17818 /* It wasn't an instruction, but it might be a register alias of
17819 the form alias .req reg, or a Neon .dn/.qn directive. */
17820 if (! create_register_alias (str
, p
)
17821 && ! create_neon_reg_alias (str
, p
))
17822 as_bad (_("bad instruction `%s'"), str
);
17827 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17828 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17830 /* The value which unconditional instructions should have in place of the
17831 condition field. */
17832 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17836 arm_feature_set variant
;
17838 variant
= cpu_variant
;
17839 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17840 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17841 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17842 /* Check that this instruction is supported for this CPU. */
17843 if (!opcode
->tvariant
17844 || (thumb_mode
== 1
17845 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17847 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17850 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17851 && opcode
->tencode
!= do_t_branch
)
17853 as_bad (_("Thumb does not support conditional execution"));
17857 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17859 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17860 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17861 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17863 /* Two things are addressed here.
17864 1) Implicit require narrow instructions on Thumb-1.
17865 This avoids relaxation accidentally introducing Thumb-2
17867 2) Reject wide instructions in non Thumb-2 cores. */
17868 if (inst
.size_req
== 0)
17870 else if (inst
.size_req
== 4)
17872 as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str
);
17878 inst
.instruction
= opcode
->tvalue
;
17880 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17882 /* Prepare the it_insn_type for those encodings that don't set
17884 it_fsm_pre_encode ();
17886 opcode
->tencode ();
17888 it_fsm_post_encode ();
17891 if (!(inst
.error
|| inst
.relax
))
17893 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17894 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17895 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17897 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17902 /* Something has gone badly wrong if we try to relax a fixed size
17904 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17906 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17907 *opcode
->tvariant
);
17908 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17909 set those bits when Thumb-2 32-bit instructions are seen. ie.
17910 anything other than bl/blx and v6-M instructions.
17911 The impact of relaxable instructions will be considered later after we
17912 finish all relaxation. */
17913 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17914 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17915 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17916 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17919 check_neon_suffixes
;
17923 mapping_state (MAP_THUMB
);
17926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17930 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17931 is_bx
= (opcode
->aencode
== do_bx
);
17933 /* Check that this instruction is supported for this CPU. */
17934 if (!(is_bx
&& fix_v4bx
)
17935 && !(opcode
->avariant
&&
17936 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17938 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17943 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17947 inst
.instruction
= opcode
->avalue
;
17948 if (opcode
->tag
== OT_unconditionalF
)
17949 inst
.instruction
|= 0xFU
<< 28;
17951 inst
.instruction
|= inst
.cond
<< 28;
17952 inst
.size
= INSN_SIZE
;
17953 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17955 it_fsm_pre_encode ();
17956 opcode
->aencode ();
17957 it_fsm_post_encode ();
17959 /* Arm mode bx is marked as both v4T and v5 because it's still required
17960 on a hypothetical non-thumb v5 core. */
17962 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17964 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17965 *opcode
->avariant
);
17967 check_neon_suffixes
;
17971 mapping_state (MAP_ARM
);
17976 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17984 check_it_blocks_finished (void)
17989 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17990 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17991 == MANUAL_IT_BLOCK
)
17993 as_warn (_("section '%s' finished with an open IT block."),
17997 if (now_it
.state
== MANUAL_IT_BLOCK
)
17998 as_warn (_("file finished with an open IT block."));
18002 /* Various frobbings of labels and their addresses. */
18005 arm_start_line_hook (void)
18007 last_label_seen
= NULL
;
18011 arm_frob_label (symbolS
* sym
)
18013 last_label_seen
= sym
;
18015 ARM_SET_THUMB (sym
, thumb_mode
);
18017 #if defined OBJ_COFF || defined OBJ_ELF
18018 ARM_SET_INTERWORK (sym
, support_interwork
);
18021 force_automatic_it_block_close ();
18023 /* Note - do not allow local symbols (.Lxxx) to be labelled
18024 as Thumb functions. This is because these labels, whilst
18025 they exist inside Thumb code, are not the entry points for
18026 possible ARM->Thumb calls. Also, these labels can be used
18027 as part of a computed goto or switch statement. eg gcc
18028 can generate code that looks like this:
18030 ldr r2, [pc, .Laaa]
18040 The first instruction loads the address of the jump table.
18041 The second instruction converts a table index into a byte offset.
18042 The third instruction gets the jump address out of the table.
18043 The fourth instruction performs the jump.
18045 If the address stored at .Laaa is that of a symbol which has the
18046 Thumb_Func bit set, then the linker will arrange for this address
18047 to have the bottom bit set, which in turn would mean that the
18048 address computation performed by the third instruction would end
18049 up with the bottom bit set. Since the ARM is capable of unaligned
18050 word loads, the instruction would then load the incorrect address
18051 out of the jump table, and chaos would ensue. */
18052 if (label_is_thumb_function_name
18053 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18054 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18056 /* When the address of a Thumb function is taken the bottom
18057 bit of that address should be set. This will allow
18058 interworking between Arm and Thumb functions to work
18061 THUMB_SET_FUNC (sym
, 1);
18063 label_is_thumb_function_name
= FALSE
;
18066 dwarf2_emit_label (sym
);
18070 arm_data_in_code (void)
18072 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18074 *input_line_pointer
= '/';
18075 input_line_pointer
+= 5;
18076 *input_line_pointer
= 0;
18084 arm_canonicalize_symbol_name (char * name
)
18088 if (thumb_mode
&& (len
= strlen (name
)) > 5
18089 && streq (name
+ len
- 5, "/data"))
18090 *(name
+ len
- 5) = 0;
18095 /* Table of all register names defined by default. The user can
18096 define additional names with .req. Note that all register names
18097 should appear in both upper and lowercase variants. Some registers
18098 also have mixed-case names. */
18100 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18101 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18102 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18103 #define REGSET(p,t) \
18104 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18105 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18106 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18107 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18108 #define REGSETH(p,t) \
18109 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18110 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18111 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18112 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18113 #define REGSET2(p,t) \
18114 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18115 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18116 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18117 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18118 #define SPLRBANK(base,bank,t) \
18119 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18120 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18121 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18122 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18123 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18124 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18126 static const struct reg_entry reg_names
[] =
18128 /* ARM integer registers. */
18129 REGSET(r
, RN
), REGSET(R
, RN
),
18131 /* ATPCS synonyms. */
18132 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18133 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18134 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18136 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18137 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18138 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18140 /* Well-known aliases. */
18141 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18142 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18144 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18145 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18147 /* Coprocessor numbers. */
18148 REGSET(p
, CP
), REGSET(P
, CP
),
18150 /* Coprocessor register numbers. The "cr" variants are for backward
18152 REGSET(c
, CN
), REGSET(C
, CN
),
18153 REGSET(cr
, CN
), REGSET(CR
, CN
),
18155 /* ARM banked registers. */
18156 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18157 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18158 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18159 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18160 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18161 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18162 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18164 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18165 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18166 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18167 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18168 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18169 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18170 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18171 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18173 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18174 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18175 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18176 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18177 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18178 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18179 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18180 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18181 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18183 /* FPA registers. */
18184 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18185 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18187 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18188 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18190 /* VFP SP registers. */
18191 REGSET(s
,VFS
), REGSET(S
,VFS
),
18192 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18194 /* VFP DP Registers. */
18195 REGSET(d
,VFD
), REGSET(D
,VFD
),
18196 /* Extra Neon DP registers. */
18197 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18199 /* Neon QP registers. */
18200 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18202 /* VFP control registers. */
18203 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18204 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18205 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18206 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18207 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18208 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18210 /* Maverick DSP coprocessor registers. */
18211 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18212 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18214 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18215 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18216 REGDEF(dspsc
,0,DSPSC
),
18218 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18219 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18220 REGDEF(DSPSC
,0,DSPSC
),
18222 /* iWMMXt data registers - p0, c0-15. */
18223 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18225 /* iWMMXt control registers - p1, c0-3. */
18226 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18227 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18228 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18229 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18231 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18232 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18233 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18234 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18235 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18237 /* XScale accumulator registers. */
18238 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18244 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18245 within psr_required_here. */
18246 static const struct asm_psr psrs
[] =
18248 /* Backward compatibility notation. Note that "all" is no longer
18249 truly all possible PSR bits. */
18250 {"all", PSR_c
| PSR_f
},
18254 /* Individual flags. */
18260 /* Combinations of flags. */
18261 {"fs", PSR_f
| PSR_s
},
18262 {"fx", PSR_f
| PSR_x
},
18263 {"fc", PSR_f
| PSR_c
},
18264 {"sf", PSR_s
| PSR_f
},
18265 {"sx", PSR_s
| PSR_x
},
18266 {"sc", PSR_s
| PSR_c
},
18267 {"xf", PSR_x
| PSR_f
},
18268 {"xs", PSR_x
| PSR_s
},
18269 {"xc", PSR_x
| PSR_c
},
18270 {"cf", PSR_c
| PSR_f
},
18271 {"cs", PSR_c
| PSR_s
},
18272 {"cx", PSR_c
| PSR_x
},
18273 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18274 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18275 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18276 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18277 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18278 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18279 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18280 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18281 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18282 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18283 {"scf", PSR_s
| PSR_c
| PSR_f
},
18284 {"scx", PSR_s
| PSR_c
| PSR_x
},
18285 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18286 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18287 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18288 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18289 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18290 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18291 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18292 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18293 {"csf", PSR_c
| PSR_s
| PSR_f
},
18294 {"csx", PSR_c
| PSR_s
| PSR_x
},
18295 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18296 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18297 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18298 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18299 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18300 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18301 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18302 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18303 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18304 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18305 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18306 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18307 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18308 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18309 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18310 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18311 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18312 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18313 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18314 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18315 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18316 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18317 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18318 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18319 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18320 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18323 /* Table of V7M psr names. */
18324 static const struct asm_psr v7m_psrs
[] =
18326 {"apsr", 0 }, {"APSR", 0 },
18327 {"iapsr", 1 }, {"IAPSR", 1 },
18328 {"eapsr", 2 }, {"EAPSR", 2 },
18329 {"psr", 3 }, {"PSR", 3 },
18330 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18331 {"ipsr", 5 }, {"IPSR", 5 },
18332 {"epsr", 6 }, {"EPSR", 6 },
18333 {"iepsr", 7 }, {"IEPSR", 7 },
18334 {"msp", 8 }, {"MSP", 8 },
18335 {"psp", 9 }, {"PSP", 9 },
18336 {"primask", 16}, {"PRIMASK", 16},
18337 {"basepri", 17}, {"BASEPRI", 17},
18338 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18339 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18340 {"faultmask", 19}, {"FAULTMASK", 19},
18341 {"control", 20}, {"CONTROL", 20}
18344 /* Table of all shift-in-operand names. */
18345 static const struct asm_shift_name shift_names
[] =
18347 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18348 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18349 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18350 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18351 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18352 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18355 /* Table of all explicit relocation names. */
18357 static struct reloc_entry reloc_names
[] =
18359 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18360 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18361 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18362 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18363 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18364 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18365 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18366 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18367 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18368 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18369 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18370 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18371 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18372 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18373 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18374 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18375 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18376 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18380 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18381 static const struct asm_cond conds
[] =
18385 {"cs", 0x2}, {"hs", 0x2},
18386 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18400 #define UL_BARRIER(L,U,CODE,FEAT) \
18401 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18402 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18404 static struct asm_barrier_opt barrier_opt_names
[] =
18406 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18407 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18408 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18409 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18410 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18411 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18412 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18413 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18414 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18415 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18416 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18417 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18418 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18419 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18420 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18421 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18426 /* Table of ARM-format instructions. */
18428 /* Macros for gluing together operand strings. N.B. In all cases
18429 other than OPS0, the trailing OP_stop comes from default
18430 zero-initialization of the unspecified elements of the array. */
18431 #define OPS0() { OP_stop, }
18432 #define OPS1(a) { OP_##a, }
18433 #define OPS2(a,b) { OP_##a,OP_##b, }
18434 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18435 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18436 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18437 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18439 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18440 This is useful when mixing operands for ARM and THUMB, i.e. using the
18441 MIX_ARM_THUMB_OPERANDS macro.
18442 In order to use these macros, prefix the number of operands with _
18444 #define OPS_1(a) { a, }
18445 #define OPS_2(a,b) { a,b, }
18446 #define OPS_3(a,b,c) { a,b,c, }
18447 #define OPS_4(a,b,c,d) { a,b,c,d, }
18448 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18449 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18451 /* These macros abstract out the exact format of the mnemonic table and
18452 save some repeated characters. */
18454 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18455 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18456 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18457 THUMB_VARIANT, do_##ae, do_##te }
18459 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18460 a T_MNEM_xyz enumerator. */
18461 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18462 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18463 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18464 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18466 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18467 infix after the third character. */
18468 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18469 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18470 THUMB_VARIANT, do_##ae, do_##te }
18471 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18472 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18473 THUMB_VARIANT, do_##ae, do_##te }
18474 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18475 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18476 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18477 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18478 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18479 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18480 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18481 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18483 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18484 field is still 0xE. Many of the Thumb variants can be executed
18485 conditionally, so this is checked separately. */
18486 #define TUE(mnem, op, top, nops, ops, ae, te) \
18487 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18488 THUMB_VARIANT, do_##ae, do_##te }
18490 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18491 Used by mnemonics that have very minimal differences in the encoding for
18492 ARM and Thumb variants and can be handled in a common function. */
18493 #define TUEc(mnem, op, top, nops, ops, en) \
18494 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18495 THUMB_VARIANT, do_##en, do_##en }
18497 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18498 condition code field. */
18499 #define TUF(mnem, op, top, nops, ops, ae, te) \
18500 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18501 THUMB_VARIANT, do_##ae, do_##te }
18503 /* ARM-only variants of all the above. */
18504 #define CE(mnem, op, nops, ops, ae) \
18505 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18507 #define C3(mnem, op, nops, ops, ae) \
18508 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18510 /* Legacy mnemonics that always have conditional infix after the third
18512 #define CL(mnem, op, nops, ops, ae) \
18513 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18514 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18516 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18517 #define cCE(mnem, op, nops, ops, ae) \
18518 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18520 /* Legacy coprocessor instructions where conditional infix and conditional
18521 suffix are ambiguous. For consistency this includes all FPA instructions,
18522 not just the potentially ambiguous ones. */
18523 #define cCL(mnem, op, nops, ops, ae) \
18524 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18525 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18527 /* Coprocessor, takes either a suffix or a position-3 infix
18528 (for an FPA corner case). */
18529 #define C3E(mnem, op, nops, ops, ae) \
18530 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18531 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18533 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18534 { m1 #m2 m3, OPS##nops ops, \
18535 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18536 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18538 #define CM(m1, m2, op, nops, ops, ae) \
18539 xCM_ (m1, , m2, op, nops, ops, ae), \
18540 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18541 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18542 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18543 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18544 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18545 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18546 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18547 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18548 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18549 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18550 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18551 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18552 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18553 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18554 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18555 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18556 xCM_ (m1, le, m2, op, nops, ops, ae), \
18557 xCM_ (m1, al, m2, op, nops, ops, ae)
18559 #define UE(mnem, op, nops, ops, ae) \
18560 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18562 #define UF(mnem, op, nops, ops, ae) \
18563 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18565 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18566 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18567 use the same encoding function for each. */
18568 #define NUF(mnem, op, nops, ops, enc) \
18569 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18570 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18572 /* Neon data processing, version which indirects through neon_enc_tab for
18573 the various overloaded versions of opcodes. */
18574 #define nUF(mnem, op, nops, ops, enc) \
18575 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18576 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18578 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18580 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18581 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18582 THUMB_VARIANT, do_##enc, do_##enc }
18584 #define NCE(mnem, op, nops, ops, enc) \
18585 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18587 #define NCEF(mnem, op, nops, ops, enc) \
18588 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18590 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18591 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18592 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18593 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18595 #define nCE(mnem, op, nops, ops, enc) \
18596 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18598 #define nCEF(mnem, op, nops, ops, enc) \
18599 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18603 static const struct asm_opcode insns
[] =
18605 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18606 #define THUMB_VARIANT & arm_ext_v4t
18607 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18608 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18609 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18610 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18611 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18612 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18613 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18614 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18615 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18616 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18617 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18618 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18619 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18620 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18621 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18622 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18624 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18625 for setting PSR flag bits. They are obsolete in V6 and do not
18626 have Thumb equivalents. */
18627 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18628 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18629 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18630 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18631 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18632 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18633 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18634 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18635 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18637 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18638 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
18639 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18640 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18642 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18643 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18644 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18646 OP_ADDRGLDR
),ldst
, t_ldst
),
18647 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18649 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18650 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18651 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18652 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18653 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18654 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18656 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18657 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18658 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18659 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18662 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18663 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18664 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18665 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18667 /* Thumb-compatibility pseudo ops. */
18668 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18669 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18670 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18671 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18672 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18673 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18674 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18675 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18676 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18677 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18678 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18679 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18681 /* These may simplify to neg. */
18682 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18683 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18685 #undef THUMB_VARIANT
18686 #define THUMB_VARIANT & arm_ext_v6
18688 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18690 /* V1 instructions with no Thumb analogue prior to V6T2. */
18691 #undef THUMB_VARIANT
18692 #define THUMB_VARIANT & arm_ext_v6t2
18694 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18695 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18696 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18698 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18699 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18700 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18701 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18703 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18704 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18706 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18707 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18709 /* V1 instructions with no Thumb analogue at all. */
18710 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18711 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18713 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18714 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18715 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18716 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18717 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18718 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18719 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18720 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18723 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18724 #undef THUMB_VARIANT
18725 #define THUMB_VARIANT & arm_ext_v4t
18727 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18728 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18730 #undef THUMB_VARIANT
18731 #define THUMB_VARIANT & arm_ext_v6t2
18733 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18734 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18736 /* Generic coprocessor instructions. */
18737 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18738 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18739 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18740 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18741 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18742 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18743 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18746 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18748 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18749 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18752 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18753 #undef THUMB_VARIANT
18754 #define THUMB_VARIANT & arm_ext_msr
18756 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18757 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18760 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18761 #undef THUMB_VARIANT
18762 #define THUMB_VARIANT & arm_ext_v6t2
18764 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18765 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18766 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18767 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18768 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18769 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18770 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18771 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18774 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18775 #undef THUMB_VARIANT
18776 #define THUMB_VARIANT & arm_ext_v4t
18778 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18779 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18780 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18781 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18782 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18783 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18786 #define ARM_VARIANT & arm_ext_v4t_5
18788 /* ARM Architecture 4T. */
18789 /* Note: bx (and blx) are required on V5, even if the processor does
18790 not support Thumb. */
18791 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18794 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18795 #undef THUMB_VARIANT
18796 #define THUMB_VARIANT & arm_ext_v5t
18798 /* Note: blx has 2 variants; the .value coded here is for
18799 BLX(2). Only this variant has conditional execution. */
18800 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18801 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18803 #undef THUMB_VARIANT
18804 #define THUMB_VARIANT & arm_ext_v6t2
18806 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18807 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18808 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18809 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18810 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18811 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18812 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18813 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18816 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18817 #undef THUMB_VARIANT
18818 #define THUMB_VARIANT & arm_ext_v5exp
18820 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18821 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18822 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18823 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18825 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18826 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18828 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18829 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18830 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18831 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18833 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18834 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18835 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18836 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18838 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18839 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18841 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18842 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18843 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18844 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18847 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18848 #undef THUMB_VARIANT
18849 #define THUMB_VARIANT & arm_ext_v6t2
18851 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18852 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18854 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18855 ADDRGLDRS
), ldrd
, t_ldstd
),
18857 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18858 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18861 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18863 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18866 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18867 #undef THUMB_VARIANT
18868 #define THUMB_VARIANT & arm_ext_v6
18870 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18871 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18872 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18873 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18874 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18875 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18876 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18877 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18878 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18879 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18881 #undef THUMB_VARIANT
18882 #define THUMB_VARIANT & arm_ext_v6t2
18884 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18885 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18887 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18888 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18890 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18891 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18893 /* ARM V6 not included in V7M. */
18894 #undef THUMB_VARIANT
18895 #define THUMB_VARIANT & arm_ext_v6_notm
18896 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18897 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18898 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18899 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18900 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18901 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18902 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18903 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18904 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18905 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18906 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18907 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18908 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18909 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18910 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18911 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18912 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18913 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18914 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18916 /* ARM V6 not included in V7M (eg. integer SIMD). */
18917 #undef THUMB_VARIANT
18918 #define THUMB_VARIANT & arm_ext_v6_dsp
18919 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18920 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18921 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18922 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18923 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18924 /* Old name for QASX. */
18925 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18926 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18927 /* Old name for QSAX. */
18928 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18929 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18930 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18932 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18933 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 /* Old name for SASX. */
18935 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18936 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18937 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 /* Old name for SHASX. */
18940 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18941 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18942 /* Old name for SHSAX. */
18943 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18944 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18945 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 /* Old name for SSAX. */
18948 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18951 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18954 /* Old name for UASX. */
18955 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18956 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18957 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18959 /* Old name for UHASX. */
18960 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18961 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 /* Old name for UHSAX. */
18963 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18964 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18965 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18966 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18967 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18968 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18969 /* Old name for UQASX. */
18970 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18971 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18972 /* Old name for UQSAX. */
18973 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18974 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18975 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18976 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18977 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18978 /* Old name for USAX. */
18979 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18980 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18981 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18982 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18983 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18984 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18985 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18986 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18987 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18988 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18989 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18990 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18991 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18992 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18993 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18994 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18995 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18996 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18997 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18998 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18999 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19000 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19001 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19002 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19003 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19004 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19005 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19006 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19007 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19008 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19009 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19010 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19011 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19012 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19015 #define ARM_VARIANT & arm_ext_v6k
19016 #undef THUMB_VARIANT
19017 #define THUMB_VARIANT & arm_ext_v6k
19019 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19020 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19021 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19022 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19024 #undef THUMB_VARIANT
19025 #define THUMB_VARIANT & arm_ext_v6_notm
19026 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19028 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19029 RRnpcb
), strexd
, t_strexd
),
19031 #undef THUMB_VARIANT
19032 #define THUMB_VARIANT & arm_ext_v6t2
19033 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19035 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19037 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19039 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19041 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19044 #define ARM_VARIANT & arm_ext_sec
19045 #undef THUMB_VARIANT
19046 #define THUMB_VARIANT & arm_ext_sec
19048 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19051 #define ARM_VARIANT & arm_ext_virt
19052 #undef THUMB_VARIANT
19053 #define THUMB_VARIANT & arm_ext_virt
19055 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19056 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19059 #define ARM_VARIANT & arm_ext_pan
19060 #undef THUMB_VARIANT
19061 #define THUMB_VARIANT & arm_ext_pan
19063 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19066 #define ARM_VARIANT & arm_ext_v6t2
19067 #undef THUMB_VARIANT
19068 #define THUMB_VARIANT & arm_ext_v6t2
19070 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19071 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19072 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19073 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19075 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19076 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19077 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19078 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19080 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19081 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19082 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19083 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19085 /* Thumb-only instructions. */
19087 #define ARM_VARIANT NULL
19088 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19089 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19091 /* ARM does not really have an IT instruction, so always allow it.
19092 The opcode is copied from Thumb in order to allow warnings in
19093 -mimplicit-it=[never | arm] modes. */
19095 #define ARM_VARIANT & arm_ext_v1
19097 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19098 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19099 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19100 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19101 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19102 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19103 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19104 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19105 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19106 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19107 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19108 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19109 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19110 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19111 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19112 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19113 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19114 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19116 /* Thumb2 only instructions. */
19118 #define ARM_VARIANT NULL
19120 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19121 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19122 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19123 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19124 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19125 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19127 /* Hardware division instructions. */
19129 #define ARM_VARIANT & arm_ext_adiv
19130 #undef THUMB_VARIANT
19131 #define THUMB_VARIANT & arm_ext_div
19133 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19134 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19136 /* ARM V6M/V7 instructions. */
19138 #define ARM_VARIANT & arm_ext_barrier
19139 #undef THUMB_VARIANT
19140 #define THUMB_VARIANT & arm_ext_barrier
19142 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19143 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19144 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19146 /* ARM V7 instructions. */
19148 #define ARM_VARIANT & arm_ext_v7
19149 #undef THUMB_VARIANT
19150 #define THUMB_VARIANT & arm_ext_v7
19152 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19153 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19156 #define ARM_VARIANT & arm_ext_mp
19157 #undef THUMB_VARIANT
19158 #define THUMB_VARIANT & arm_ext_mp
19160 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19162 /* AArchv8 instructions. */
19164 #define ARM_VARIANT & arm_ext_v8
19165 #undef THUMB_VARIANT
19166 #define THUMB_VARIANT & arm_ext_v8
19168 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19169 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19170 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19171 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19173 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19174 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19175 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19177 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19179 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19181 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19183 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19184 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19185 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19186 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19187 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19188 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19190 /* ARMv8 T32 only. */
19192 #define ARM_VARIANT NULL
19193 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19194 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19195 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19197 /* FP for ARMv8. */
19199 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19200 #undef THUMB_VARIANT
19201 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19203 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19204 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19205 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19206 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19207 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19208 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19209 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19210 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19211 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19212 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19213 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19214 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19215 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19216 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19217 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19218 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19219 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19221 /* Crypto v1 extensions. */
19223 #define ARM_VARIANT & fpu_crypto_ext_armv8
19224 #undef THUMB_VARIANT
19225 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19227 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19228 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19229 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19230 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19231 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19232 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19233 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19234 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19235 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19236 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19237 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19238 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19239 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19240 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19243 #define ARM_VARIANT & crc_ext_armv8
19244 #undef THUMB_VARIANT
19245 #define THUMB_VARIANT & crc_ext_armv8
19246 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19247 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19248 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19249 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19250 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19251 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19254 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19255 #undef THUMB_VARIANT
19256 #define THUMB_VARIANT NULL
19258 cCE("wfs", e200110
, 1, (RR
), rd
),
19259 cCE("rfs", e300110
, 1, (RR
), rd
),
19260 cCE("wfc", e400110
, 1, (RR
), rd
),
19261 cCE("rfc", e500110
, 1, (RR
), rd
),
19263 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19264 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19265 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19266 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19268 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19269 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19270 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19271 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19273 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19457 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19459 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19461 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19462 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19463 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19464 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19465 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19466 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19468 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19469 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19470 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19471 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19472 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19473 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19474 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19475 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19476 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19477 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19478 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19479 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19481 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19484 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19626 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19628 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19630 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19631 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19632 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19633 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19634 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19635 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19637 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19638 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19639 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19640 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19641 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19642 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19643 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19644 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19645 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19646 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19647 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19648 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19650 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19651 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19652 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19653 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19655 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19656 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19657 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19658 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19659 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19660 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19661 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19662 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19663 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19664 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19665 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19666 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19668 /* The implementation of the FIX instruction is broken on some
19669 assemblers, in that it accepts a precision specifier as well as a
19670 rounding specifier, despite the fact that this is meaningless.
19671 To be more compatible, we accept it as well, though of course it
19672 does not set any bits. */
19673 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19674 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19675 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19676 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19677 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19678 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19679 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19680 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19681 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19682 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19683 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19684 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19685 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19687 /* Instructions that were new with the real FPA, call them V2. */
19689 #define ARM_VARIANT & fpu_fpa_ext_v2
19691 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19692 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19693 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19694 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19695 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19696 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19699 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19701 /* Moves and type conversions. */
19702 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19703 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19704 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19705 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19706 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19707 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19708 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19709 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19710 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19711 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19712 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19713 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19714 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19715 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19717 /* Memory operations. */
19718 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19719 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19720 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19721 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19722 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19723 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19724 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19725 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19726 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19727 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19728 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19729 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19730 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19731 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19732 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19733 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19734 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19735 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19737 /* Monadic operations. */
19738 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19739 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19740 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19742 /* Dyadic operations. */
19743 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19744 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19745 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19746 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19747 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19748 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19749 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19750 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19751 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19754 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19755 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19756 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19757 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19759 /* Double precision load/store are still present on single precision
19760 implementations. */
19761 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19762 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19763 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19764 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19765 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19766 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19767 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19768 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19769 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19770 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19773 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19775 /* Moves and type conversions. */
19776 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19777 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19778 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19779 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19780 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19781 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19782 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19783 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19784 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19785 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19786 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19787 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19788 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19790 /* Monadic operations. */
19791 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19792 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19793 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19795 /* Dyadic operations. */
19796 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19797 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19798 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19799 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19800 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19801 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19802 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19803 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19804 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19807 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19808 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19809 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19810 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19813 #define ARM_VARIANT & fpu_vfp_ext_v2
19815 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19816 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19817 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19818 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19820 /* Instructions which may belong to either the Neon or VFP instruction sets.
19821 Individual encoder functions perform additional architecture checks. */
19823 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19824 #undef THUMB_VARIANT
19825 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19827 /* These mnemonics are unique to VFP. */
19828 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19829 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19830 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19831 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19832 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19833 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19834 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19835 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19836 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19837 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19839 /* Mnemonics shared by Neon and VFP. */
19840 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19841 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19842 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19844 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19845 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19847 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19848 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19850 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19851 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19852 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19853 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19854 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19855 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19856 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19857 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19859 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19860 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19861 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19862 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19865 /* NOTE: All VMOV encoding is special-cased! */
19866 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19867 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19869 #undef THUMB_VARIANT
19870 #define THUMB_VARIANT & fpu_neon_ext_v1
19872 #define ARM_VARIANT & fpu_neon_ext_v1
19874 /* Data processing with three registers of the same length. */
19875 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19876 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19877 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19878 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19879 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19880 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19881 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19882 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19883 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19884 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19885 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19886 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19887 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19888 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19889 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19890 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19891 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19892 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19893 /* If not immediate, fall back to neon_dyadic_i64_su.
19894 shl_imm should accept I8 I16 I32 I64,
19895 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19896 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19897 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19898 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19899 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19900 /* Logic ops, types optional & ignored. */
19901 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19902 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19903 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19904 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19905 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19906 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19907 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19908 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19909 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19910 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19911 /* Bitfield ops, untyped. */
19912 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19913 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19914 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19915 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19916 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19917 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19918 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19919 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19920 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19921 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19922 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19923 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19924 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19925 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19926 back to neon_dyadic_if_su. */
19927 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19928 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19929 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19930 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19931 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19932 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19933 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19934 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19935 /* Comparison. Type I8 I16 I32 F32. */
19936 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19937 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19938 /* As above, D registers only. */
19939 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19940 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19941 /* Int and float variants, signedness unimportant. */
19942 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19943 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19944 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19945 /* Add/sub take types I8 I16 I32 I64 F32. */
19946 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19947 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19948 /* vtst takes sizes 8, 16, 32. */
19949 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19950 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19951 /* VMUL takes I8 I16 I32 F32 P8. */
19952 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19953 /* VQD{R}MULH takes S16 S32. */
19954 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19955 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19956 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19957 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19958 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19959 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19960 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19961 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19962 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19963 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19964 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19965 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19966 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19967 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19968 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19969 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19970 /* ARM v8.1 extension. */
19971 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19972 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19973 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19974 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19976 /* Two address, int/float. Types S8 S16 S32 F32. */
19977 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19978 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19980 /* Data processing with two registers and a shift amount. */
19981 /* Right shifts, and variants with rounding.
19982 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19983 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19984 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19985 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19986 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19987 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19988 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19989 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19990 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19991 /* Shift and insert. Sizes accepted 8 16 32 64. */
19992 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19993 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19994 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19995 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19996 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19997 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19998 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19999 /* Right shift immediate, saturating & narrowing, with rounding variants.
20000 Types accepted S16 S32 S64 U16 U32 U64. */
20001 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20002 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20003 /* As above, unsigned. Types accepted S16 S32 S64. */
20004 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20005 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20006 /* Right shift narrowing. Types accepted I16 I32 I64. */
20007 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20008 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20009 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20010 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20011 /* CVT with optional immediate for fixed-point variant. */
20012 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20014 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20015 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20017 /* Data processing, three registers of different lengths. */
20018 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20019 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20020 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20021 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20022 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20023 /* If not scalar, fall back to neon_dyadic_long.
20024 Vector types as above, scalar types S16 S32 U16 U32. */
20025 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20026 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20027 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20028 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20029 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20030 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20031 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20032 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20033 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20034 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20035 /* Saturating doubling multiplies. Types S16 S32. */
20036 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20037 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20038 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20039 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20040 S16 S32 U16 U32. */
20041 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20043 /* Extract. Size 8. */
20044 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20045 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20047 /* Two registers, miscellaneous. */
20048 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20049 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20050 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20051 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20052 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20053 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20054 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20055 /* Vector replicate. Sizes 8 16 32. */
20056 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20057 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20058 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20059 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20060 /* VMOVN. Types I16 I32 I64. */
20061 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20062 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20063 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20064 /* VQMOVUN. Types S16 S32 S64. */
20065 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20066 /* VZIP / VUZP. Sizes 8 16 32. */
20067 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20068 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20069 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20070 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20071 /* VQABS / VQNEG. Types S8 S16 S32. */
20072 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20073 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20074 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20075 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20076 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20077 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20078 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20079 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20080 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20081 /* Reciprocal estimates. Types U32 F32. */
20082 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20083 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20084 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20085 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20086 /* VCLS. Types S8 S16 S32. */
20087 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20088 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20089 /* VCLZ. Types I8 I16 I32. */
20090 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20091 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20092 /* VCNT. Size 8. */
20093 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20094 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20095 /* Two address, untyped. */
20096 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20097 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20098 /* VTRN. Sizes 8 16 32. */
20099 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20100 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20102 /* Table lookup. Size 8. */
20103 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20104 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20106 #undef THUMB_VARIANT
20107 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20109 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20111 /* Neon element/structure load/store. */
20112 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20113 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20114 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20115 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20116 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20117 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20118 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20119 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20121 #undef THUMB_VARIANT
20122 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20124 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20125 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20126 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20127 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20128 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20129 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20130 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20131 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20132 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20133 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20135 #undef THUMB_VARIANT
20136 #define THUMB_VARIANT & fpu_vfp_ext_v3
20138 #define ARM_VARIANT & fpu_vfp_ext_v3
20140 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20141 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20142 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20143 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20144 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20145 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20146 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20147 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20148 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20151 #define ARM_VARIANT & fpu_vfp_ext_fma
20152 #undef THUMB_VARIANT
20153 #define THUMB_VARIANT & fpu_vfp_ext_fma
20154 /* Mnemonics shared by Neon and VFP. These are included in the
20155 VFP FMA variant; NEON and VFP FMA always includes the NEON
20156 FMA instructions. */
20157 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20158 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20159 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20160 the v form should always be used. */
20161 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20162 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20163 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20164 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20165 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20166 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20168 #undef THUMB_VARIANT
20170 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20172 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20173 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20174 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20175 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20176 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20177 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20178 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20179 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20182 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20184 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20185 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20186 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20187 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20188 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20189 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20190 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20191 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20192 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20193 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20194 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20195 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20196 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20197 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20198 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20199 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20200 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20201 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20202 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20203 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20204 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20205 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20206 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20207 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20208 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20209 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20210 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20211 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20212 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20213 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20214 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20215 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20216 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20217 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20218 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20219 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20220 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20221 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20223 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20224 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20225 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20226 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20231 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20233 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20234 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20235 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20236 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20251 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20252 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20253 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20254 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20258 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20259 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20260 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20267 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20268 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20269 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20270 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20271 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20272 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20273 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20276 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20277 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20278 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20279 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20280 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20281 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20282 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20283 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20284 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20285 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20286 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20287 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20288 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20289 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20290 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20291 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20292 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20293 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20294 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20295 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20296 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20297 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20298 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20299 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20300 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20301 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20302 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20303 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20304 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20305 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20306 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20307 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20308 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20309 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20310 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20311 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20312 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20313 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20314 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20315 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20316 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20317 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20318 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20319 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20320 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20321 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20322 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20323 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20324 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20325 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20326 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20327 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20328 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20329 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20330 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20331 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20332 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20333 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20334 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20335 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20336 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20337 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20338 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20339 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20340 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20341 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20343 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20344 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20345 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20348 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20350 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20351 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20352 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20353 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20354 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20355 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20356 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20357 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20371 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20380 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20383 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20384 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20385 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20387 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20388 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20389 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20390 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20391 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20392 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20393 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20394 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20395 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20396 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20397 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20398 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20399 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20400 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20401 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20402 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20403 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20404 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20405 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20406 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20409 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20411 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20412 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20413 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20414 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20415 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20416 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20417 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20418 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20419 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20420 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20421 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20422 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20423 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20424 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20425 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20426 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20427 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20428 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20429 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20430 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20431 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20432 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20433 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20434 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20435 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20436 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20437 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20438 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20439 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20440 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20441 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20442 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20443 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20444 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20445 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20446 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20447 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20448 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20449 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20450 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20451 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20452 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20453 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20454 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20455 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20456 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20457 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20458 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20459 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20460 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20461 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20462 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20463 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20464 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20465 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20466 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20467 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20468 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20469 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20470 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20471 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20472 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20473 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20474 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20475 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20476 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20477 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20478 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20479 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20480 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20481 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20482 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20483 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20484 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20485 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20486 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20489 #undef THUMB_VARIANT
20515 /* MD interface: bits in the object file. */
20517 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20518 for use in the a.out file, and stores them in the array pointed to by buf.
20519 This knows about the endian-ness of the target machine and does
20520 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20521 2 (short) and 4 (long) Floating numbers are put out as a series of
20522 LITTLENUMS (shorts, here at least). */
20525 md_number_to_chars (char * buf
, valueT val
, int n
)
20527 if (target_big_endian
)
20528 number_to_chars_bigendian (buf
, val
, n
);
20530 number_to_chars_littleendian (buf
, val
, n
);
20534 md_chars_to_number (char * buf
, int n
)
20537 unsigned char * where
= (unsigned char *) buf
;
20539 if (target_big_endian
)
20544 result
|= (*where
++ & 255);
20552 result
|= (where
[n
] & 255);
20559 /* MD interface: Sections. */
20561 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20562 that an rs_machine_dependent frag may reach. */
20565 arm_frag_max_var (fragS
*fragp
)
20567 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20568 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20570 Note that we generate relaxable instructions even for cases that don't
20571 really need it, like an immediate that's a trivial constant. So we're
20572 overestimating the instruction size for some of those cases. Rather
20573 than putting more intelligence here, it would probably be better to
20574 avoid generating a relaxation frag in the first place when it can be
20575 determined up front that a short instruction will suffice. */
20577 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20581 /* Estimate the size of a frag before relaxing. Assume everything fits in
20585 md_estimate_size_before_relax (fragS
* fragp
,
20586 segT segtype ATTRIBUTE_UNUSED
)
20592 /* Convert a machine dependent frag. */
20595 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20597 unsigned long insn
;
20598 unsigned long old_op
;
20606 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20608 old_op
= bfd_get_16(abfd
, buf
);
20609 if (fragp
->fr_symbol
)
20611 exp
.X_op
= O_symbol
;
20612 exp
.X_add_symbol
= fragp
->fr_symbol
;
20616 exp
.X_op
= O_constant
;
20618 exp
.X_add_number
= fragp
->fr_offset
;
20619 opcode
= fragp
->fr_subtype
;
20622 case T_MNEM_ldr_pc
:
20623 case T_MNEM_ldr_pc2
:
20624 case T_MNEM_ldr_sp
:
20625 case T_MNEM_str_sp
:
20632 if (fragp
->fr_var
== 4)
20634 insn
= THUMB_OP32 (opcode
);
20635 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20637 insn
|= (old_op
& 0x700) << 4;
20641 insn
|= (old_op
& 7) << 12;
20642 insn
|= (old_op
& 0x38) << 13;
20644 insn
|= 0x00000c00;
20645 put_thumb32_insn (buf
, insn
);
20646 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20650 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20652 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20655 if (fragp
->fr_var
== 4)
20657 insn
= THUMB_OP32 (opcode
);
20658 insn
|= (old_op
& 0xf0) << 4;
20659 put_thumb32_insn (buf
, insn
);
20660 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20664 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20665 exp
.X_add_number
-= 4;
20673 if (fragp
->fr_var
== 4)
20675 int r0off
= (opcode
== T_MNEM_mov
20676 || opcode
== T_MNEM_movs
) ? 0 : 8;
20677 insn
= THUMB_OP32 (opcode
);
20678 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20679 insn
|= (old_op
& 0x700) << r0off
;
20680 put_thumb32_insn (buf
, insn
);
20681 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20685 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20690 if (fragp
->fr_var
== 4)
20692 insn
= THUMB_OP32(opcode
);
20693 put_thumb32_insn (buf
, insn
);
20694 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20697 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20701 if (fragp
->fr_var
== 4)
20703 insn
= THUMB_OP32(opcode
);
20704 insn
|= (old_op
& 0xf00) << 14;
20705 put_thumb32_insn (buf
, insn
);
20706 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20709 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20712 case T_MNEM_add_sp
:
20713 case T_MNEM_add_pc
:
20714 case T_MNEM_inc_sp
:
20715 case T_MNEM_dec_sp
:
20716 if (fragp
->fr_var
== 4)
20718 /* ??? Choose between add and addw. */
20719 insn
= THUMB_OP32 (opcode
);
20720 insn
|= (old_op
& 0xf0) << 4;
20721 put_thumb32_insn (buf
, insn
);
20722 if (opcode
== T_MNEM_add_pc
)
20723 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20725 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20728 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20736 if (fragp
->fr_var
== 4)
20738 insn
= THUMB_OP32 (opcode
);
20739 insn
|= (old_op
& 0xf0) << 4;
20740 insn
|= (old_op
& 0xf) << 16;
20741 put_thumb32_insn (buf
, insn
);
20742 if (insn
& (1 << 20))
20743 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20745 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20748 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20754 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20755 (enum bfd_reloc_code_real
) reloc_type
);
20756 fixp
->fx_file
= fragp
->fr_file
;
20757 fixp
->fx_line
= fragp
->fr_line
;
20758 fragp
->fr_fix
+= fragp
->fr_var
;
20760 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20761 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20762 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20763 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20766 /* Return the size of a relaxable immediate operand instruction.
20767 SHIFT and SIZE specify the form of the allowable immediate. */
20769 relax_immediate (fragS
*fragp
, int size
, int shift
)
20775 /* ??? Should be able to do better than this. */
20776 if (fragp
->fr_symbol
)
20779 low
= (1 << shift
) - 1;
20780 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20781 offset
= fragp
->fr_offset
;
20782 /* Force misaligned offsets to 32-bit variant. */
20785 if (offset
& ~mask
)
20790 /* Get the address of a symbol during relaxation. */
20792 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20798 sym
= fragp
->fr_symbol
;
20799 sym_frag
= symbol_get_frag (sym
);
20800 know (S_GET_SEGMENT (sym
) != absolute_section
20801 || sym_frag
== &zero_address_frag
);
20802 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20804 /* If frag has yet to be reached on this pass, assume it will
20805 move by STRETCH just as we did. If this is not so, it will
20806 be because some frag between grows, and that will force
20810 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20814 /* Adjust stretch for any alignment frag. Note that if have
20815 been expanding the earlier code, the symbol may be
20816 defined in what appears to be an earlier frag. FIXME:
20817 This doesn't handle the fr_subtype field, which specifies
20818 a maximum number of bytes to skip when doing an
20820 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20822 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20825 stretch
= - ((- stretch
)
20826 & ~ ((1 << (int) f
->fr_offset
) - 1));
20828 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20840 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20843 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20848 /* Assume worst case for symbols not known to be in the same section. */
20849 if (fragp
->fr_symbol
== NULL
20850 || !S_IS_DEFINED (fragp
->fr_symbol
)
20851 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20852 || S_IS_WEAK (fragp
->fr_symbol
))
20855 val
= relaxed_symbol_addr (fragp
, stretch
);
20856 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20857 addr
= (addr
+ 4) & ~3;
20858 /* Force misaligned targets to 32-bit variant. */
20862 if (val
< 0 || val
> 1020)
20867 /* Return the size of a relaxable add/sub immediate instruction. */
20869 relax_addsub (fragS
*fragp
, asection
*sec
)
20874 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20875 op
= bfd_get_16(sec
->owner
, buf
);
20876 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20877 return relax_immediate (fragp
, 8, 0);
20879 return relax_immediate (fragp
, 3, 0);
20882 /* Return TRUE iff the definition of symbol S could be pre-empted
20883 (overridden) at link or load time. */
20885 symbol_preemptible (symbolS
*s
)
20887 /* Weak symbols can always be pre-empted. */
20891 /* Non-global symbols cannot be pre-empted. */
20892 if (! S_IS_EXTERNAL (s
))
20896 /* In ELF, a global symbol can be marked protected, or private. In that
20897 case it can't be pre-empted (other definitions in the same link unit
20898 would violate the ODR). */
20899 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20903 /* Other global symbols might be pre-empted. */
20907 /* Return the size of a relaxable branch instruction. BITS is the
20908 size of the offset field in the narrow instruction. */
20911 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20917 /* Assume worst case for symbols not known to be in the same section. */
20918 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20919 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20920 || S_IS_WEAK (fragp
->fr_symbol
))
20924 /* A branch to a function in ARM state will require interworking. */
20925 if (S_IS_DEFINED (fragp
->fr_symbol
)
20926 && ARM_IS_FUNC (fragp
->fr_symbol
))
20930 if (symbol_preemptible (fragp
->fr_symbol
))
20933 val
= relaxed_symbol_addr (fragp
, stretch
);
20934 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20937 /* Offset is a signed value *2 */
20939 if (val
>= limit
|| val
< -limit
)
20945 /* Relax a machine dependent frag. This returns the amount by which
20946 the current size of the frag should change. */
20949 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20954 oldsize
= fragp
->fr_var
;
20955 switch (fragp
->fr_subtype
)
20957 case T_MNEM_ldr_pc2
:
20958 newsize
= relax_adr (fragp
, sec
, stretch
);
20960 case T_MNEM_ldr_pc
:
20961 case T_MNEM_ldr_sp
:
20962 case T_MNEM_str_sp
:
20963 newsize
= relax_immediate (fragp
, 8, 2);
20967 newsize
= relax_immediate (fragp
, 5, 2);
20971 newsize
= relax_immediate (fragp
, 5, 1);
20975 newsize
= relax_immediate (fragp
, 5, 0);
20978 newsize
= relax_adr (fragp
, sec
, stretch
);
20984 newsize
= relax_immediate (fragp
, 8, 0);
20987 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20990 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20992 case T_MNEM_add_sp
:
20993 case T_MNEM_add_pc
:
20994 newsize
= relax_immediate (fragp
, 8, 2);
20996 case T_MNEM_inc_sp
:
20997 case T_MNEM_dec_sp
:
20998 newsize
= relax_immediate (fragp
, 7, 2);
21004 newsize
= relax_addsub (fragp
, sec
);
21010 fragp
->fr_var
= newsize
;
21011 /* Freeze wide instructions that are at or before the same location as
21012 in the previous pass. This avoids infinite loops.
21013 Don't freeze them unconditionally because targets may be artificially
21014 misaligned by the expansion of preceding frags. */
21015 if (stretch
<= 0 && newsize
> 2)
21017 md_convert_frag (sec
->owner
, sec
, fragp
);
21021 return newsize
- oldsize
;
21024 /* Round up a section size to the appropriate boundary. */
21027 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21030 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21031 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21033 /* For a.out, force the section size to be aligned. If we don't do
21034 this, BFD will align it for us, but it will not write out the
21035 final bytes of the section. This may be a bug in BFD, but it is
21036 easier to fix it here since that is how the other a.out targets
21040 align
= bfd_get_section_alignment (stdoutput
, segment
);
21041 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21048 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21049 of an rs_align_code fragment. */
21052 arm_handle_align (fragS
* fragP
)
21054 static char const arm_noop
[2][2][4] =
21057 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21058 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21061 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21062 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21065 static char const thumb_noop
[2][2][2] =
21068 {0xc0, 0x46}, /* LE */
21069 {0x46, 0xc0}, /* BE */
21072 {0x00, 0xbf}, /* LE */
21073 {0xbf, 0x00} /* BE */
21076 static char const wide_thumb_noop
[2][4] =
21077 { /* Wide Thumb-2 */
21078 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21079 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21082 unsigned bytes
, fix
, noop_size
;
21085 const char *narrow_noop
= NULL
;
21090 if (fragP
->fr_type
!= rs_align_code
)
21093 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21094 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21097 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21098 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21100 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21102 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21104 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21105 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21107 narrow_noop
= thumb_noop
[1][target_big_endian
];
21108 noop
= wide_thumb_noop
[target_big_endian
];
21111 noop
= thumb_noop
[0][target_big_endian
];
21119 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21120 ? selected_cpu
: arm_arch_none
,
21122 [target_big_endian
];
21129 fragP
->fr_var
= noop_size
;
21131 if (bytes
& (noop_size
- 1))
21133 fix
= bytes
& (noop_size
- 1);
21135 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21137 memset (p
, 0, fix
);
21144 if (bytes
& noop_size
)
21146 /* Insert a narrow noop. */
21147 memcpy (p
, narrow_noop
, noop_size
);
21149 bytes
-= noop_size
;
21153 /* Use wide noops for the remainder */
21157 while (bytes
>= noop_size
)
21159 memcpy (p
, noop
, noop_size
);
21161 bytes
-= noop_size
;
21165 fragP
->fr_fix
+= fix
;
21168 /* Called from md_do_align. Used to create an alignment
21169 frag in a code section. */
21172 arm_frag_align_code (int n
, int max
)
21176 /* We assume that there will never be a requirement
21177 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21178 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21183 _("alignments greater than %d bytes not supported in .text sections."),
21184 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21185 as_fatal ("%s", err_msg
);
21188 p
= frag_var (rs_align_code
,
21189 MAX_MEM_FOR_RS_ALIGN_CODE
,
21191 (relax_substateT
) max
,
21198 /* Perform target specific initialisation of a frag.
21199 Note - despite the name this initialisation is not done when the frag
21200 is created, but only when its type is assigned. A frag can be created
21201 and used a long time before its type is set, so beware of assuming that
21202 this initialisationis performed first. */
21206 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21208 /* Record whether this frag is in an ARM or a THUMB area. */
21209 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21212 #else /* OBJ_ELF is defined. */
21214 arm_init_frag (fragS
* fragP
, int max_chars
)
21216 int frag_thumb_mode
;
21218 /* If the current ARM vs THUMB mode has not already
21219 been recorded into this frag then do so now. */
21220 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21221 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21223 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21225 /* Record a mapping symbol for alignment frags. We will delete this
21226 later if the alignment ends up empty. */
21227 switch (fragP
->fr_type
)
21230 case rs_align_test
:
21232 mapping_state_2 (MAP_DATA
, max_chars
);
21234 case rs_align_code
:
21235 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21242 /* When we change sections we need to issue a new mapping symbol. */
21245 arm_elf_change_section (void)
21247 /* Link an unlinked unwind index table section to the .text section. */
21248 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21249 && elf_linked_to_section (now_seg
) == NULL
)
21250 elf_linked_to_section (now_seg
) = text_section
;
21254 arm_elf_section_type (const char * str
, size_t len
)
21256 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21257 return SHT_ARM_EXIDX
;
21262 /* Code to deal with unwinding tables. */
21264 static void add_unwind_adjustsp (offsetT
);
21266 /* Generate any deferred unwind frame offset. */
21269 flush_pending_unwind (void)
21273 offset
= unwind
.pending_offset
;
21274 unwind
.pending_offset
= 0;
21276 add_unwind_adjustsp (offset
);
21279 /* Add an opcode to this list for this function. Two-byte opcodes should
21280 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21284 add_unwind_opcode (valueT op
, int length
)
21286 /* Add any deferred stack adjustment. */
21287 if (unwind
.pending_offset
)
21288 flush_pending_unwind ();
21290 unwind
.sp_restored
= 0;
21292 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21294 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21295 if (unwind
.opcodes
)
21296 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21297 unwind
.opcode_alloc
);
21299 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21304 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21306 unwind
.opcode_count
++;
21310 /* Add unwind opcodes to adjust the stack pointer. */
21313 add_unwind_adjustsp (offsetT offset
)
21317 if (offset
> 0x200)
21319 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21324 /* Long form: 0xb2, uleb128. */
21325 /* This might not fit in a word so add the individual bytes,
21326 remembering the list is built in reverse order. */
21327 o
= (valueT
) ((offset
- 0x204) >> 2);
21329 add_unwind_opcode (0, 1);
21331 /* Calculate the uleb128 encoding of the offset. */
21335 bytes
[n
] = o
& 0x7f;
21341 /* Add the insn. */
21343 add_unwind_opcode (bytes
[n
- 1], 1);
21344 add_unwind_opcode (0xb2, 1);
21346 else if (offset
> 0x100)
21348 /* Two short opcodes. */
21349 add_unwind_opcode (0x3f, 1);
21350 op
= (offset
- 0x104) >> 2;
21351 add_unwind_opcode (op
, 1);
21353 else if (offset
> 0)
21355 /* Short opcode. */
21356 op
= (offset
- 4) >> 2;
21357 add_unwind_opcode (op
, 1);
21359 else if (offset
< 0)
21362 while (offset
> 0x100)
21364 add_unwind_opcode (0x7f, 1);
21367 op
= ((offset
- 4) >> 2) | 0x40;
21368 add_unwind_opcode (op
, 1);
21372 /* Finish the list of unwind opcodes for this function. */
21374 finish_unwind_opcodes (void)
21378 if (unwind
.fp_used
)
21380 /* Adjust sp as necessary. */
21381 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21382 flush_pending_unwind ();
21384 /* After restoring sp from the frame pointer. */
21385 op
= 0x90 | unwind
.fp_reg
;
21386 add_unwind_opcode (op
, 1);
21389 flush_pending_unwind ();
21393 /* Start an exception table entry. If idx is nonzero this is an index table
21397 start_unwind_section (const segT text_seg
, int idx
)
21399 const char * text_name
;
21400 const char * prefix
;
21401 const char * prefix_once
;
21402 const char * group_name
;
21406 size_t sec_name_len
;
21413 prefix
= ELF_STRING_ARM_unwind
;
21414 prefix_once
= ELF_STRING_ARM_unwind_once
;
21415 type
= SHT_ARM_EXIDX
;
21419 prefix
= ELF_STRING_ARM_unwind_info
;
21420 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21421 type
= SHT_PROGBITS
;
21424 text_name
= segment_name (text_seg
);
21425 if (streq (text_name
, ".text"))
21428 if (strncmp (text_name
, ".gnu.linkonce.t.",
21429 strlen (".gnu.linkonce.t.")) == 0)
21431 prefix
= prefix_once
;
21432 text_name
+= strlen (".gnu.linkonce.t.");
21435 prefix_len
= strlen (prefix
);
21436 text_len
= strlen (text_name
);
21437 sec_name_len
= prefix_len
+ text_len
;
21438 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21439 memcpy (sec_name
, prefix
, prefix_len
);
21440 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21441 sec_name
[prefix_len
+ text_len
] = '\0';
21447 /* Handle COMDAT group. */
21448 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21450 group_name
= elf_group_name (text_seg
);
21451 if (group_name
== NULL
)
21453 as_bad (_("Group section `%s' has no group signature"),
21454 segment_name (text_seg
));
21455 ignore_rest_of_line ();
21458 flags
|= SHF_GROUP
;
21462 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21464 /* Set the section link for index tables. */
21466 elf_linked_to_section (now_seg
) = text_seg
;
21470 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21471 personality routine data. Returns zero, or the index table value for
21472 an inline entry. */
21475 create_unwind_entry (int have_data
)
21480 /* The current word of data. */
21482 /* The number of bytes left in this word. */
21485 finish_unwind_opcodes ();
21487 /* Remember the current text section. */
21488 unwind
.saved_seg
= now_seg
;
21489 unwind
.saved_subseg
= now_subseg
;
21491 start_unwind_section (now_seg
, 0);
21493 if (unwind
.personality_routine
== NULL
)
21495 if (unwind
.personality_index
== -2)
21498 as_bad (_("handlerdata in cantunwind frame"));
21499 return 1; /* EXIDX_CANTUNWIND. */
21502 /* Use a default personality routine if none is specified. */
21503 if (unwind
.personality_index
== -1)
21505 if (unwind
.opcode_count
> 3)
21506 unwind
.personality_index
= 1;
21508 unwind
.personality_index
= 0;
21511 /* Space for the personality routine entry. */
21512 if (unwind
.personality_index
== 0)
21514 if (unwind
.opcode_count
> 3)
21515 as_bad (_("too many unwind opcodes for personality routine 0"));
21519 /* All the data is inline in the index table. */
21522 while (unwind
.opcode_count
> 0)
21524 unwind
.opcode_count
--;
21525 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21529 /* Pad with "finish" opcodes. */
21531 data
= (data
<< 8) | 0xb0;
21538 /* We get two opcodes "free" in the first word. */
21539 size
= unwind
.opcode_count
- 2;
21543 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21544 if (unwind
.personality_index
!= -1)
21546 as_bad (_("attempt to recreate an unwind entry"));
21550 /* An extra byte is required for the opcode count. */
21551 size
= unwind
.opcode_count
+ 1;
21554 size
= (size
+ 3) >> 2;
21556 as_bad (_("too many unwind opcodes"));
21558 frag_align (2, 0, 0);
21559 record_alignment (now_seg
, 2);
21560 unwind
.table_entry
= expr_build_dot ();
21562 /* Allocate the table entry. */
21563 ptr
= frag_more ((size
<< 2) + 4);
21564 /* PR 13449: Zero the table entries in case some of them are not used. */
21565 memset (ptr
, 0, (size
<< 2) + 4);
21566 where
= frag_now_fix () - ((size
<< 2) + 4);
21568 switch (unwind
.personality_index
)
21571 /* ??? Should this be a PLT generating relocation? */
21572 /* Custom personality routine. */
21573 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21574 BFD_RELOC_ARM_PREL31
);
21579 /* Set the first byte to the number of additional words. */
21580 data
= size
> 0 ? size
- 1 : 0;
21584 /* ABI defined personality routines. */
21586 /* Three opcodes bytes are packed into the first word. */
21593 /* The size and first two opcode bytes go in the first word. */
21594 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21599 /* Should never happen. */
21603 /* Pack the opcodes into words (MSB first), reversing the list at the same
21605 while (unwind
.opcode_count
> 0)
21609 md_number_to_chars (ptr
, data
, 4);
21614 unwind
.opcode_count
--;
21616 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21619 /* Finish off the last word. */
21622 /* Pad with "finish" opcodes. */
21624 data
= (data
<< 8) | 0xb0;
21626 md_number_to_chars (ptr
, data
, 4);
21631 /* Add an empty descriptor if there is no user-specified data. */
21632 ptr
= frag_more (4);
21633 md_number_to_chars (ptr
, 0, 4);
21640 /* Initialize the DWARF-2 unwind information for this procedure. */
21643 tc_arm_frame_initial_instructions (void)
21645 cfi_add_CFA_def_cfa (REG_SP
, 0);
21647 #endif /* OBJ_ELF */
21649 /* Convert REGNAME to a DWARF-2 register number. */
21652 tc_arm_regname_to_dw2regnum (char *regname
)
21654 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21658 /* PR 16694: Allow VFP registers as well. */
21659 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21663 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21672 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21676 exp
.X_op
= O_secrel
;
21677 exp
.X_add_symbol
= symbol
;
21678 exp
.X_add_number
= 0;
21679 emit_expr (&exp
, size
);
21683 /* MD interface: Symbol and relocation handling. */
21685 /* Return the address within the segment that a PC-relative fixup is
21686 relative to. For ARM, PC-relative fixups applied to instructions
21687 are generally relative to the location of the fixup plus 8 bytes.
21688 Thumb branches are offset by 4, and Thumb loads relative to PC
21689 require special handling. */
21692 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21694 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21696 /* If this is pc-relative and we are going to emit a relocation
21697 then we just want to put out any pipeline compensation that the linker
21698 will need. Otherwise we want to use the calculated base.
21699 For WinCE we skip the bias for externals as well, since this
21700 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21702 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21703 || (arm_force_relocation (fixP
)
21705 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21711 switch (fixP
->fx_r_type
)
21713 /* PC relative addressing on the Thumb is slightly odd as the
21714 bottom two bits of the PC are forced to zero for the
21715 calculation. This happens *after* application of the
21716 pipeline offset. However, Thumb adrl already adjusts for
21717 this, so we need not do it again. */
21718 case BFD_RELOC_ARM_THUMB_ADD
:
21721 case BFD_RELOC_ARM_THUMB_OFFSET
:
21722 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21723 case BFD_RELOC_ARM_T32_ADD_PC12
:
21724 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21725 return (base
+ 4) & ~3;
21727 /* Thumb branches are simply offset by +4. */
21728 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21729 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21730 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21731 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21732 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21735 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21737 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21738 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21739 && ARM_IS_FUNC (fixP
->fx_addsy
)
21740 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21741 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21744 /* BLX is like branches above, but forces the low two bits of PC to
21746 case BFD_RELOC_THUMB_PCREL_BLX
:
21748 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21749 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21750 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21751 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21752 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21753 return (base
+ 4) & ~3;
21755 /* ARM mode branches are offset by +8. However, the Windows CE
21756 loader expects the relocation not to take this into account. */
21757 case BFD_RELOC_ARM_PCREL_BLX
:
21759 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21760 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21761 && ARM_IS_FUNC (fixP
->fx_addsy
)
21762 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21763 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21766 case BFD_RELOC_ARM_PCREL_CALL
:
21768 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21769 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21770 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21771 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21772 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21775 case BFD_RELOC_ARM_PCREL_BRANCH
:
21776 case BFD_RELOC_ARM_PCREL_JUMP
:
21777 case BFD_RELOC_ARM_PLT32
:
21779 /* When handling fixups immediately, because we have already
21780 discovered the value of a symbol, or the address of the frag involved
21781 we must account for the offset by +8, as the OS loader will never see the reloc.
21782 see fixup_segment() in write.c
21783 The S_IS_EXTERNAL test handles the case of global symbols.
21784 Those need the calculated base, not just the pipe compensation the linker will need. */
21786 && fixP
->fx_addsy
!= NULL
21787 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21788 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21796 /* ARM mode loads relative to PC are also offset by +8. Unlike
21797 branches, the Windows CE loader *does* expect the relocation
21798 to take this into account. */
21799 case BFD_RELOC_ARM_OFFSET_IMM
:
21800 case BFD_RELOC_ARM_OFFSET_IMM8
:
21801 case BFD_RELOC_ARM_HWLITERAL
:
21802 case BFD_RELOC_ARM_LITERAL
:
21803 case BFD_RELOC_ARM_CP_OFF_IMM
:
21807 /* Other PC-relative relocations are un-offset. */
21813 static bfd_boolean flag_warn_syms
= TRUE
;
21816 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21818 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21819 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21820 does mean that the resulting code might be very confusing to the reader.
21821 Also this warning can be triggered if the user omits an operand before
21822 an immediate address, eg:
21826 GAS treats this as an assignment of the value of the symbol foo to a
21827 symbol LDR, and so (without this code) it will not issue any kind of
21828 warning or error message.
21830 Note - ARM instructions are case-insensitive but the strings in the hash
21831 table are all stored in lower case, so we must first ensure that name is
21833 if (flag_warn_syms
&& arm_ops_hsh
)
21835 char * nbuf
= strdup (name
);
21838 for (p
= nbuf
; *p
; p
++)
21840 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21842 static struct hash_control
* already_warned
= NULL
;
21844 if (already_warned
== NULL
)
21845 already_warned
= hash_new ();
21846 /* Only warn about the symbol once. To keep the code
21847 simple we let hash_insert do the lookup for us. */
21848 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21849 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21858 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21859 Otherwise we have no need to default values of symbols. */
21862 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21865 if (name
[0] == '_' && name
[1] == 'G'
21866 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21870 if (symbol_find (name
))
21871 as_bad (_("GOT already in the symbol table"));
21873 GOT_symbol
= symbol_new (name
, undefined_section
,
21874 (valueT
) 0, & zero_address_frag
);
21884 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21885 computed as two separate immediate values, added together. We
21886 already know that this value cannot be computed by just one ARM
21889 static unsigned int
21890 validate_immediate_twopart (unsigned int val
,
21891 unsigned int * highpart
)
21896 for (i
= 0; i
< 32; i
+= 2)
21897 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21903 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21905 else if (a
& 0xff0000)
21907 if (a
& 0xff000000)
21909 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21913 gas_assert (a
& 0xff000000);
21914 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21917 return (a
& 0xff) | (i
<< 7);
21924 validate_offset_imm (unsigned int val
, int hwse
)
21926 if ((hwse
&& val
> 255) || val
> 4095)
21931 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21932 negative immediate constant by altering the instruction. A bit of
21937 by inverting the second operand, and
21940 by negating the second operand. */
21943 negate_data_op (unsigned long * instruction
,
21944 unsigned long value
)
21947 unsigned long negated
, inverted
;
21949 negated
= encode_arm_immediate (-value
);
21950 inverted
= encode_arm_immediate (~value
);
21952 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21955 /* First negates. */
21956 case OPCODE_SUB
: /* ADD <-> SUB */
21957 new_inst
= OPCODE_ADD
;
21962 new_inst
= OPCODE_SUB
;
21966 case OPCODE_CMP
: /* CMP <-> CMN */
21967 new_inst
= OPCODE_CMN
;
21972 new_inst
= OPCODE_CMP
;
21976 /* Now Inverted ops. */
21977 case OPCODE_MOV
: /* MOV <-> MVN */
21978 new_inst
= OPCODE_MVN
;
21983 new_inst
= OPCODE_MOV
;
21987 case OPCODE_AND
: /* AND <-> BIC */
21988 new_inst
= OPCODE_BIC
;
21993 new_inst
= OPCODE_AND
;
21997 case OPCODE_ADC
: /* ADC <-> SBC */
21998 new_inst
= OPCODE_SBC
;
22003 new_inst
= OPCODE_ADC
;
22007 /* We cannot do anything. */
22012 if (value
== (unsigned) FAIL
)
22015 *instruction
&= OPCODE_MASK
;
22016 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22020 /* Like negate_data_op, but for Thumb-2. */
22022 static unsigned int
22023 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22027 unsigned int negated
, inverted
;
22029 negated
= encode_thumb32_immediate (-value
);
22030 inverted
= encode_thumb32_immediate (~value
);
22032 rd
= (*instruction
>> 8) & 0xf;
22033 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22036 /* ADD <-> SUB. Includes CMP <-> CMN. */
22037 case T2_OPCODE_SUB
:
22038 new_inst
= T2_OPCODE_ADD
;
22042 case T2_OPCODE_ADD
:
22043 new_inst
= T2_OPCODE_SUB
;
22047 /* ORR <-> ORN. Includes MOV <-> MVN. */
22048 case T2_OPCODE_ORR
:
22049 new_inst
= T2_OPCODE_ORN
;
22053 case T2_OPCODE_ORN
:
22054 new_inst
= T2_OPCODE_ORR
;
22058 /* AND <-> BIC. TST has no inverted equivalent. */
22059 case T2_OPCODE_AND
:
22060 new_inst
= T2_OPCODE_BIC
;
22067 case T2_OPCODE_BIC
:
22068 new_inst
= T2_OPCODE_AND
;
22073 case T2_OPCODE_ADC
:
22074 new_inst
= T2_OPCODE_SBC
;
22078 case T2_OPCODE_SBC
:
22079 new_inst
= T2_OPCODE_ADC
;
22083 /* We cannot do anything. */
22088 if (value
== (unsigned int)FAIL
)
22091 *instruction
&= T2_OPCODE_MASK
;
22092 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22096 /* Read a 32-bit thumb instruction from buf. */
22097 static unsigned long
22098 get_thumb32_insn (char * buf
)
22100 unsigned long insn
;
22101 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22102 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22108 /* We usually want to set the low bit on the address of thumb function
22109 symbols. In particular .word foo - . should have the low bit set.
22110 Generic code tries to fold the difference of two symbols to
22111 a constant. Prevent this and force a relocation when the first symbols
22112 is a thumb function. */
22115 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22117 if (op
== O_subtract
22118 && l
->X_op
== O_symbol
22119 && r
->X_op
== O_symbol
22120 && THUMB_IS_FUNC (l
->X_add_symbol
))
22122 l
->X_op
= O_subtract
;
22123 l
->X_op_symbol
= r
->X_add_symbol
;
22124 l
->X_add_number
-= r
->X_add_number
;
22128 /* Process as normal. */
22132 /* Encode Thumb2 unconditional branches and calls. The encoding
22133 for the 2 are identical for the immediate values. */
22136 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22138 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22141 addressT S
, I1
, I2
, lo
, hi
;
22143 S
= (value
>> 24) & 0x01;
22144 I1
= (value
>> 23) & 0x01;
22145 I2
= (value
>> 22) & 0x01;
22146 hi
= (value
>> 12) & 0x3ff;
22147 lo
= (value
>> 1) & 0x7ff;
22148 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22149 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22150 newval
|= (S
<< 10) | hi
;
22151 newval2
&= ~T2I1I2MASK
;
22152 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22153 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22154 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22158 md_apply_fix (fixS
* fixP
,
22162 offsetT value
= * valP
;
22164 unsigned int newimm
;
22165 unsigned long temp
;
22167 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22169 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22171 /* Note whether this will delete the relocation. */
22173 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22176 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22177 consistency with the behaviour on 32-bit hosts. Remember value
22179 value
&= 0xffffffff;
22180 value
^= 0x80000000;
22181 value
-= 0x80000000;
22184 fixP
->fx_addnumber
= value
;
22186 /* Same treatment for fixP->fx_offset. */
22187 fixP
->fx_offset
&= 0xffffffff;
22188 fixP
->fx_offset
^= 0x80000000;
22189 fixP
->fx_offset
-= 0x80000000;
22191 switch (fixP
->fx_r_type
)
22193 case BFD_RELOC_NONE
:
22194 /* This will need to go in the object file. */
22198 case BFD_RELOC_ARM_IMMEDIATE
:
22199 /* We claim that this fixup has been processed here,
22200 even if in fact we generate an error because we do
22201 not have a reloc for it, so tc_gen_reloc will reject it. */
22204 if (fixP
->fx_addsy
)
22206 const char *msg
= 0;
22208 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22209 msg
= _("undefined symbol %s used as an immediate value");
22210 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22211 msg
= _("symbol %s is in a different section");
22212 else if (S_IS_WEAK (fixP
->fx_addsy
))
22213 msg
= _("symbol %s is weak and may be overridden later");
22217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22218 msg
, S_GET_NAME (fixP
->fx_addsy
));
22223 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22225 /* If the offset is negative, we should use encoding A2 for ADR. */
22226 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22227 newimm
= negate_data_op (&temp
, value
);
22230 newimm
= encode_arm_immediate (value
);
22232 /* If the instruction will fail, see if we can fix things up by
22233 changing the opcode. */
22234 if (newimm
== (unsigned int) FAIL
)
22235 newimm
= negate_data_op (&temp
, value
);
22238 if (newimm
== (unsigned int) FAIL
)
22240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22241 _("invalid constant (%lx) after fixup"),
22242 (unsigned long) value
);
22246 newimm
|= (temp
& 0xfffff000);
22247 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22250 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22252 unsigned int highpart
= 0;
22253 unsigned int newinsn
= 0xe1a00000; /* nop. */
22255 if (fixP
->fx_addsy
)
22257 const char *msg
= 0;
22259 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22260 msg
= _("undefined symbol %s used as an immediate value");
22261 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22262 msg
= _("symbol %s is in a different section");
22263 else if (S_IS_WEAK (fixP
->fx_addsy
))
22264 msg
= _("symbol %s is weak and may be overridden later");
22268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22269 msg
, S_GET_NAME (fixP
->fx_addsy
));
22274 newimm
= encode_arm_immediate (value
);
22275 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22277 /* If the instruction will fail, see if we can fix things up by
22278 changing the opcode. */
22279 if (newimm
== (unsigned int) FAIL
22280 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22282 /* No ? OK - try using two ADD instructions to generate
22284 newimm
= validate_immediate_twopart (value
, & highpart
);
22286 /* Yes - then make sure that the second instruction is
22288 if (newimm
!= (unsigned int) FAIL
)
22290 /* Still No ? Try using a negated value. */
22291 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22292 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22293 /* Otherwise - give up. */
22296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22297 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22302 /* Replace the first operand in the 2nd instruction (which
22303 is the PC) with the destination register. We have
22304 already added in the PC in the first instruction and we
22305 do not want to do it again. */
22306 newinsn
&= ~ 0xf0000;
22307 newinsn
|= ((newinsn
& 0x0f000) << 4);
22310 newimm
|= (temp
& 0xfffff000);
22311 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22313 highpart
|= (newinsn
& 0xfffff000);
22314 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22318 case BFD_RELOC_ARM_OFFSET_IMM
:
22319 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22322 case BFD_RELOC_ARM_LITERAL
:
22328 if (validate_offset_imm (value
, 0) == FAIL
)
22330 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22332 _("invalid literal constant: pool needs to be closer"));
22334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22335 _("bad immediate value for offset (%ld)"),
22340 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22342 newval
&= 0xfffff000;
22345 newval
&= 0xff7ff000;
22346 newval
|= value
| (sign
? INDEX_UP
: 0);
22348 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22351 case BFD_RELOC_ARM_OFFSET_IMM8
:
22352 case BFD_RELOC_ARM_HWLITERAL
:
22358 if (validate_offset_imm (value
, 1) == FAIL
)
22360 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22362 _("invalid literal constant: pool needs to be closer"));
22364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22365 _("bad immediate value for 8-bit offset (%ld)"),
22370 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22372 newval
&= 0xfffff0f0;
22375 newval
&= 0xff7ff0f0;
22376 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22378 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22381 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22382 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22384 _("bad immediate value for offset (%ld)"), (long) value
);
22387 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22389 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22392 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22393 /* This is a complicated relocation used for all varieties of Thumb32
22394 load/store instruction with immediate offset:
22396 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22397 *4, optional writeback(W)
22398 (doubleword load/store)
22400 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22401 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22402 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22403 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22404 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22406 Uppercase letters indicate bits that are already encoded at
22407 this point. Lowercase letters are our problem. For the
22408 second block of instructions, the secondary opcode nybble
22409 (bits 8..11) is present, and bit 23 is zero, even if this is
22410 a PC-relative operation. */
22411 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22413 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22415 if ((newval
& 0xf0000000) == 0xe0000000)
22417 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22419 newval
|= (1 << 23);
22422 if (value
% 4 != 0)
22424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22425 _("offset not a multiple of 4"));
22431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22432 _("offset out of range"));
22437 else if ((newval
& 0x000f0000) == 0x000f0000)
22439 /* PC-relative, 12-bit offset. */
22441 newval
|= (1 << 23);
22446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22447 _("offset out of range"));
22452 else if ((newval
& 0x00000100) == 0x00000100)
22454 /* Writeback: 8-bit, +/- offset. */
22456 newval
|= (1 << 9);
22461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22462 _("offset out of range"));
22467 else if ((newval
& 0x00000f00) == 0x00000e00)
22469 /* T-instruction: positive 8-bit offset. */
22470 if (value
< 0 || value
> 0xff)
22472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22473 _("offset out of range"));
22481 /* Positive 12-bit or negative 8-bit offset. */
22485 newval
|= (1 << 23);
22495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22496 _("offset out of range"));
22503 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22504 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22507 case BFD_RELOC_ARM_SHIFT_IMM
:
22508 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22509 if (((unsigned long) value
) > 32
22511 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22514 _("shift expression is too large"));
22519 /* Shifts of zero must be done as lsl. */
22521 else if (value
== 32)
22523 newval
&= 0xfffff07f;
22524 newval
|= (value
& 0x1f) << 7;
22525 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22528 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22529 case BFD_RELOC_ARM_T32_ADD_IMM
:
22530 case BFD_RELOC_ARM_T32_IMM12
:
22531 case BFD_RELOC_ARM_T32_ADD_PC12
:
22532 /* We claim that this fixup has been processed here,
22533 even if in fact we generate an error because we do
22534 not have a reloc for it, so tc_gen_reloc will reject it. */
22538 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22541 _("undefined symbol %s used as an immediate value"),
22542 S_GET_NAME (fixP
->fx_addsy
));
22546 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22548 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22551 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22552 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22554 newimm
= encode_thumb32_immediate (value
);
22555 if (newimm
== (unsigned int) FAIL
)
22556 newimm
= thumb32_negate_data_op (&newval
, value
);
22558 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22559 && newimm
== (unsigned int) FAIL
)
22561 /* Turn add/sum into addw/subw. */
22562 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22563 newval
= (newval
& 0xfeffffff) | 0x02000000;
22564 /* No flat 12-bit imm encoding for addsw/subsw. */
22565 if ((newval
& 0x00100000) == 0)
22567 /* 12 bit immediate for addw/subw. */
22571 newval
^= 0x00a00000;
22574 newimm
= (unsigned int) FAIL
;
22580 if (newimm
== (unsigned int)FAIL
)
22582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22583 _("invalid constant (%lx) after fixup"),
22584 (unsigned long) value
);
22588 newval
|= (newimm
& 0x800) << 15;
22589 newval
|= (newimm
& 0x700) << 4;
22590 newval
|= (newimm
& 0x0ff);
22592 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22593 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22596 case BFD_RELOC_ARM_SMC
:
22597 if (((unsigned long) value
) > 0xffff)
22598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22599 _("invalid smc expression"));
22600 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22601 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22602 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22605 case BFD_RELOC_ARM_HVC
:
22606 if (((unsigned long) value
) > 0xffff)
22607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22608 _("invalid hvc expression"));
22609 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22610 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22611 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22614 case BFD_RELOC_ARM_SWI
:
22615 if (fixP
->tc_fix_data
!= 0)
22617 if (((unsigned long) value
) > 0xff)
22618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22619 _("invalid swi expression"));
22620 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22622 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22626 if (((unsigned long) value
) > 0x00ffffff)
22627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22628 _("invalid swi expression"));
22629 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22631 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22635 case BFD_RELOC_ARM_MULTI
:
22636 if (((unsigned long) value
) > 0xffff)
22637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22638 _("invalid expression in load/store multiple"));
22639 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22640 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22644 case BFD_RELOC_ARM_PCREL_CALL
:
22646 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22648 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22649 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22650 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22651 /* Flip the bl to blx. This is a simple flip
22652 bit here because we generate PCREL_CALL for
22653 unconditional bls. */
22655 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22656 newval
= newval
| 0x10000000;
22657 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22663 goto arm_branch_common
;
22665 case BFD_RELOC_ARM_PCREL_JUMP
:
22666 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22668 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22669 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22670 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22672 /* This would map to a bl<cond>, b<cond>,
22673 b<always> to a Thumb function. We
22674 need to force a relocation for this particular
22676 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22680 case BFD_RELOC_ARM_PLT32
:
22682 case BFD_RELOC_ARM_PCREL_BRANCH
:
22684 goto arm_branch_common
;
22686 case BFD_RELOC_ARM_PCREL_BLX
:
22689 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22691 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22692 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22693 && ARM_IS_FUNC (fixP
->fx_addsy
))
22695 /* Flip the blx to a bl and warn. */
22696 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22697 newval
= 0xeb000000;
22698 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22699 _("blx to '%s' an ARM ISA state function changed to bl"),
22701 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22707 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22708 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22712 /* We are going to store value (shifted right by two) in the
22713 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22714 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22715 also be be clear. */
22717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22718 _("misaligned branch destination"));
22719 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22720 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22723 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22725 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22726 newval
|= (value
>> 2) & 0x00ffffff;
22727 /* Set the H bit on BLX instructions. */
22731 newval
|= 0x01000000;
22733 newval
&= ~0x01000000;
22735 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22739 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22740 /* CBZ can only branch forward. */
22742 /* Attempts to use CBZ to branch to the next instruction
22743 (which, strictly speaking, are prohibited) will be turned into
22746 FIXME: It may be better to remove the instruction completely and
22747 perform relaxation. */
22750 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22751 newval
= 0xbf00; /* NOP encoding T1 */
22752 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22759 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22761 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22762 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22763 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22768 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22769 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22772 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22774 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22775 newval
|= (value
& 0x1ff) >> 1;
22776 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22780 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22781 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22784 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22786 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22787 newval
|= (value
& 0xfff) >> 1;
22788 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22792 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22794 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22795 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22796 && ARM_IS_FUNC (fixP
->fx_addsy
)
22797 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22799 /* Force a relocation for a branch 20 bits wide. */
22802 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22804 _("conditional branch out of range"));
22806 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22809 addressT S
, J1
, J2
, lo
, hi
;
22811 S
= (value
& 0x00100000) >> 20;
22812 J2
= (value
& 0x00080000) >> 19;
22813 J1
= (value
& 0x00040000) >> 18;
22814 hi
= (value
& 0x0003f000) >> 12;
22815 lo
= (value
& 0x00000ffe) >> 1;
22817 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22818 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22819 newval
|= (S
<< 10) | hi
;
22820 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22821 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22822 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22826 case BFD_RELOC_THUMB_PCREL_BLX
:
22827 /* If there is a blx from a thumb state function to
22828 another thumb function flip this to a bl and warn
22832 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22833 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22834 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22836 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22837 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22838 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22840 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22841 newval
= newval
| 0x1000;
22842 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22843 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22848 goto thumb_bl_common
;
22850 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22851 /* A bl from Thumb state ISA to an internal ARM state function
22852 is converted to a blx. */
22854 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22855 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22856 && ARM_IS_FUNC (fixP
->fx_addsy
)
22857 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22859 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22860 newval
= newval
& ~0x1000;
22861 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22862 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22868 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22869 /* For a BLX instruction, make sure that the relocation is rounded up
22870 to a word boundary. This follows the semantics of the instruction
22871 which specifies that bit 1 of the target address will come from bit
22872 1 of the base address. */
22873 value
= (value
+ 3) & ~ 3;
22876 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22877 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22878 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22881 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22883 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22885 else if ((value
& ~0x1ffffff)
22886 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22888 _("Thumb2 branch out of range"));
22891 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22892 encode_thumb2_b_bl_offset (buf
, value
);
22896 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22897 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22900 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22901 encode_thumb2_b_bl_offset (buf
, value
);
22906 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22912 md_number_to_chars (buf
, value
, 2);
22916 case BFD_RELOC_ARM_TLS_CALL
:
22917 case BFD_RELOC_ARM_THM_TLS_CALL
:
22918 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22919 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22920 case BFD_RELOC_ARM_TLS_GOTDESC
:
22921 case BFD_RELOC_ARM_TLS_GD32
:
22922 case BFD_RELOC_ARM_TLS_LE32
:
22923 case BFD_RELOC_ARM_TLS_IE32
:
22924 case BFD_RELOC_ARM_TLS_LDM32
:
22925 case BFD_RELOC_ARM_TLS_LDO32
:
22926 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22929 case BFD_RELOC_ARM_GOT32
:
22930 case BFD_RELOC_ARM_GOTOFF
:
22933 case BFD_RELOC_ARM_GOT_PREL
:
22934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22935 md_number_to_chars (buf
, value
, 4);
22938 case BFD_RELOC_ARM_TARGET2
:
22939 /* TARGET2 is not partial-inplace, so we need to write the
22940 addend here for REL targets, because it won't be written out
22941 during reloc processing later. */
22942 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22943 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22947 case BFD_RELOC_RVA
:
22949 case BFD_RELOC_ARM_TARGET1
:
22950 case BFD_RELOC_ARM_ROSEGREL32
:
22951 case BFD_RELOC_ARM_SBREL32
:
22952 case BFD_RELOC_32_PCREL
:
22954 case BFD_RELOC_32_SECREL
:
22956 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22958 /* For WinCE we only do this for pcrel fixups. */
22959 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22961 md_number_to_chars (buf
, value
, 4);
22965 case BFD_RELOC_ARM_PREL31
:
22966 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22968 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22969 if ((value
^ (value
>> 1)) & 0x40000000)
22971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22972 _("rel31 relocation overflow"));
22974 newval
|= value
& 0x7fffffff;
22975 md_number_to_chars (buf
, newval
, 4);
22980 case BFD_RELOC_ARM_CP_OFF_IMM
:
22981 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22982 if (value
< -1023 || value
> 1023 || (value
& 3))
22983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22984 _("co-processor offset out of range"));
22989 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22990 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22991 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22993 newval
= get_thumb32_insn (buf
);
22995 newval
&= 0xffffff00;
22998 newval
&= 0xff7fff00;
22999 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23001 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23002 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23003 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23005 put_thumb32_insn (buf
, newval
);
23008 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23009 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23010 if (value
< -255 || value
> 255)
23011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23012 _("co-processor offset out of range"));
23014 goto cp_off_common
;
23016 case BFD_RELOC_ARM_THUMB_OFFSET
:
23017 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23018 /* Exactly what ranges, and where the offset is inserted depends
23019 on the type of instruction, we can establish this from the
23021 switch (newval
>> 12)
23023 case 4: /* PC load. */
23024 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23025 forced to zero for these loads; md_pcrel_from has already
23026 compensated for this. */
23028 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23029 _("invalid offset, target not word aligned (0x%08lX)"),
23030 (((unsigned long) fixP
->fx_frag
->fr_address
23031 + (unsigned long) fixP
->fx_where
) & ~3)
23032 + (unsigned long) value
);
23034 if (value
& ~0x3fc)
23035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23036 _("invalid offset, value too big (0x%08lX)"),
23039 newval
|= value
>> 2;
23042 case 9: /* SP load/store. */
23043 if (value
& ~0x3fc)
23044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23045 _("invalid offset, value too big (0x%08lX)"),
23047 newval
|= value
>> 2;
23050 case 6: /* Word load/store. */
23052 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23053 _("invalid offset, value too big (0x%08lX)"),
23055 newval
|= value
<< 4; /* 6 - 2. */
23058 case 7: /* Byte load/store. */
23060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23061 _("invalid offset, value too big (0x%08lX)"),
23063 newval
|= value
<< 6;
23066 case 8: /* Halfword load/store. */
23068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23069 _("invalid offset, value too big (0x%08lX)"),
23071 newval
|= value
<< 5; /* 6 - 1. */
23075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23076 "Unable to process relocation for thumb opcode: %lx",
23077 (unsigned long) newval
);
23080 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23083 case BFD_RELOC_ARM_THUMB_ADD
:
23084 /* This is a complicated relocation, since we use it for all of
23085 the following immediate relocations:
23089 9bit ADD/SUB SP word-aligned
23090 10bit ADD PC/SP word-aligned
23092 The type of instruction being processed is encoded in the
23099 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23101 int rd
= (newval
>> 4) & 0xf;
23102 int rs
= newval
& 0xf;
23103 int subtract
= !!(newval
& 0x8000);
23105 /* Check for HI regs, only very restricted cases allowed:
23106 Adjusting SP, and using PC or SP to get an address. */
23107 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23108 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23110 _("invalid Hi register with immediate"));
23112 /* If value is negative, choose the opposite instruction. */
23116 subtract
= !subtract
;
23118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23119 _("immediate value out of range"));
23124 if (value
& ~0x1fc)
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("invalid immediate for stack address calculation"));
23127 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23128 newval
|= value
>> 2;
23130 else if (rs
== REG_PC
|| rs
== REG_SP
)
23132 /* PR gas/18541. If the addition is for a defined symbol
23133 within range of an ADR instruction then accept it. */
23136 && fixP
->fx_addsy
!= NULL
)
23140 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23141 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23142 || S_IS_WEAK (fixP
->fx_addsy
))
23144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23145 _("address calculation needs a strongly defined nearby symbol"));
23149 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23151 /* Round up to the next 4-byte boundary. */
23156 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23161 _("symbol too far away"));
23171 if (subtract
|| value
& ~0x3fc)
23172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23173 _("invalid immediate for address calculation (value = 0x%08lX)"),
23174 (unsigned long) (subtract
? - value
: value
));
23175 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23177 newval
|= value
>> 2;
23182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23183 _("immediate value out of range"));
23184 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23185 newval
|= (rd
<< 8) | value
;
23190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23191 _("immediate value out of range"));
23192 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23193 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23196 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23199 case BFD_RELOC_ARM_THUMB_IMM
:
23200 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23201 if (value
< 0 || value
> 255)
23202 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23203 _("invalid immediate: %ld is out of range"),
23206 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23209 case BFD_RELOC_ARM_THUMB_SHIFT
:
23210 /* 5bit shift value (0..32). LSL cannot take 32. */
23211 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23212 temp
= newval
& 0xf800;
23213 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23215 _("invalid shift value: %ld"), (long) value
);
23216 /* Shifts of zero must be encoded as LSL. */
23218 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23219 /* Shifts of 32 are encoded as zero. */
23220 else if (value
== 32)
23222 newval
|= value
<< 6;
23223 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23226 case BFD_RELOC_VTABLE_INHERIT
:
23227 case BFD_RELOC_VTABLE_ENTRY
:
23231 case BFD_RELOC_ARM_MOVW
:
23232 case BFD_RELOC_ARM_MOVT
:
23233 case BFD_RELOC_ARM_THUMB_MOVW
:
23234 case BFD_RELOC_ARM_THUMB_MOVT
:
23235 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23237 /* REL format relocations are limited to a 16-bit addend. */
23238 if (!fixP
->fx_done
)
23240 if (value
< -0x8000 || value
> 0x7fff)
23241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23242 _("offset out of range"));
23244 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23245 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23250 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23251 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23253 newval
= get_thumb32_insn (buf
);
23254 newval
&= 0xfbf08f00;
23255 newval
|= (value
& 0xf000) << 4;
23256 newval
|= (value
& 0x0800) << 15;
23257 newval
|= (value
& 0x0700) << 4;
23258 newval
|= (value
& 0x00ff);
23259 put_thumb32_insn (buf
, newval
);
23263 newval
= md_chars_to_number (buf
, 4);
23264 newval
&= 0xfff0f000;
23265 newval
|= value
& 0x0fff;
23266 newval
|= (value
& 0xf000) << 4;
23267 md_number_to_chars (buf
, newval
, 4);
23272 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23273 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23274 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23275 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23276 gas_assert (!fixP
->fx_done
);
23279 bfd_boolean is_mov
;
23280 bfd_vma encoded_addend
= value
;
23282 /* Check that addend can be encoded in instruction. */
23283 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23285 _("the offset 0x%08lX is not representable"),
23286 (unsigned long) encoded_addend
);
23288 /* Extract the instruction. */
23289 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23290 is_mov
= (insn
& 0xf800) == 0x2000;
23295 if (!seg
->use_rela_p
)
23296 insn
|= encoded_addend
;
23302 /* Extract the instruction. */
23303 /* Encoding is the following
23308 /* The following conditions must be true :
23313 rd
= (insn
>> 4) & 0xf;
23315 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23317 _("Unable to process relocation for thumb opcode: %lx"),
23318 (unsigned long) insn
);
23320 /* Encode as ADD immediate8 thumb 1 code. */
23321 insn
= 0x3000 | (rd
<< 8);
23323 /* Place the encoded addend into the first 8 bits of the
23325 if (!seg
->use_rela_p
)
23326 insn
|= encoded_addend
;
23329 /* Update the instruction. */
23330 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23334 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23335 case BFD_RELOC_ARM_ALU_PC_G0
:
23336 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23337 case BFD_RELOC_ARM_ALU_PC_G1
:
23338 case BFD_RELOC_ARM_ALU_PC_G2
:
23339 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23340 case BFD_RELOC_ARM_ALU_SB_G0
:
23341 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23342 case BFD_RELOC_ARM_ALU_SB_G1
:
23343 case BFD_RELOC_ARM_ALU_SB_G2
:
23344 gas_assert (!fixP
->fx_done
);
23345 if (!seg
->use_rela_p
)
23348 bfd_vma encoded_addend
;
23349 bfd_vma addend_abs
= abs (value
);
23351 /* Check that the absolute value of the addend can be
23352 expressed as an 8-bit constant plus a rotation. */
23353 encoded_addend
= encode_arm_immediate (addend_abs
);
23354 if (encoded_addend
== (unsigned int) FAIL
)
23355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23356 _("the offset 0x%08lX is not representable"),
23357 (unsigned long) addend_abs
);
23359 /* Extract the instruction. */
23360 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23362 /* If the addend is positive, use an ADD instruction.
23363 Otherwise use a SUB. Take care not to destroy the S bit. */
23364 insn
&= 0xff1fffff;
23370 /* Place the encoded addend into the first 12 bits of the
23372 insn
&= 0xfffff000;
23373 insn
|= encoded_addend
;
23375 /* Update the instruction. */
23376 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23380 case BFD_RELOC_ARM_LDR_PC_G0
:
23381 case BFD_RELOC_ARM_LDR_PC_G1
:
23382 case BFD_RELOC_ARM_LDR_PC_G2
:
23383 case BFD_RELOC_ARM_LDR_SB_G0
:
23384 case BFD_RELOC_ARM_LDR_SB_G1
:
23385 case BFD_RELOC_ARM_LDR_SB_G2
:
23386 gas_assert (!fixP
->fx_done
);
23387 if (!seg
->use_rela_p
)
23390 bfd_vma addend_abs
= abs (value
);
23392 /* Check that the absolute value of the addend can be
23393 encoded in 12 bits. */
23394 if (addend_abs
>= 0x1000)
23395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23396 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23397 (unsigned long) addend_abs
);
23399 /* Extract the instruction. */
23400 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23402 /* If the addend is negative, clear bit 23 of the instruction.
23403 Otherwise set it. */
23405 insn
&= ~(1 << 23);
23409 /* Place the absolute value of the addend into the first 12 bits
23410 of the instruction. */
23411 insn
&= 0xfffff000;
23412 insn
|= addend_abs
;
23414 /* Update the instruction. */
23415 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23419 case BFD_RELOC_ARM_LDRS_PC_G0
:
23420 case BFD_RELOC_ARM_LDRS_PC_G1
:
23421 case BFD_RELOC_ARM_LDRS_PC_G2
:
23422 case BFD_RELOC_ARM_LDRS_SB_G0
:
23423 case BFD_RELOC_ARM_LDRS_SB_G1
:
23424 case BFD_RELOC_ARM_LDRS_SB_G2
:
23425 gas_assert (!fixP
->fx_done
);
23426 if (!seg
->use_rela_p
)
23429 bfd_vma addend_abs
= abs (value
);
23431 /* Check that the absolute value of the addend can be
23432 encoded in 8 bits. */
23433 if (addend_abs
>= 0x100)
23434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23435 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23436 (unsigned long) addend_abs
);
23438 /* Extract the instruction. */
23439 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23441 /* If the addend is negative, clear bit 23 of the instruction.
23442 Otherwise set it. */
23444 insn
&= ~(1 << 23);
23448 /* Place the first four bits of the absolute value of the addend
23449 into the first 4 bits of the instruction, and the remaining
23450 four into bits 8 .. 11. */
23451 insn
&= 0xfffff0f0;
23452 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23454 /* Update the instruction. */
23455 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23459 case BFD_RELOC_ARM_LDC_PC_G0
:
23460 case BFD_RELOC_ARM_LDC_PC_G1
:
23461 case BFD_RELOC_ARM_LDC_PC_G2
:
23462 case BFD_RELOC_ARM_LDC_SB_G0
:
23463 case BFD_RELOC_ARM_LDC_SB_G1
:
23464 case BFD_RELOC_ARM_LDC_SB_G2
:
23465 gas_assert (!fixP
->fx_done
);
23466 if (!seg
->use_rela_p
)
23469 bfd_vma addend_abs
= abs (value
);
23471 /* Check that the absolute value of the addend is a multiple of
23472 four and, when divided by four, fits in 8 bits. */
23473 if (addend_abs
& 0x3)
23474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23475 _("bad offset 0x%08lX (must be word-aligned)"),
23476 (unsigned long) addend_abs
);
23478 if ((addend_abs
>> 2) > 0xff)
23479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23480 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23481 (unsigned long) addend_abs
);
23483 /* Extract the instruction. */
23484 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23486 /* If the addend is negative, clear bit 23 of the instruction.
23487 Otherwise set it. */
23489 insn
&= ~(1 << 23);
23493 /* Place the addend (divided by four) into the first eight
23494 bits of the instruction. */
23495 insn
&= 0xfffffff0;
23496 insn
|= addend_abs
>> 2;
23498 /* Update the instruction. */
23499 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23503 case BFD_RELOC_ARM_V4BX
:
23504 /* This will need to go in the object file. */
23508 case BFD_RELOC_UNUSED
:
23510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23511 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23515 /* Translate internal representation of relocation info to BFD target
23519 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23522 bfd_reloc_code_real_type code
;
23524 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23526 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23527 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23528 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23530 if (fixp
->fx_pcrel
)
23532 if (section
->use_rela_p
)
23533 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23535 fixp
->fx_offset
= reloc
->address
;
23537 reloc
->addend
= fixp
->fx_offset
;
23539 switch (fixp
->fx_r_type
)
23542 if (fixp
->fx_pcrel
)
23544 code
= BFD_RELOC_8_PCREL
;
23549 if (fixp
->fx_pcrel
)
23551 code
= BFD_RELOC_16_PCREL
;
23556 if (fixp
->fx_pcrel
)
23558 code
= BFD_RELOC_32_PCREL
;
23562 case BFD_RELOC_ARM_MOVW
:
23563 if (fixp
->fx_pcrel
)
23565 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23569 case BFD_RELOC_ARM_MOVT
:
23570 if (fixp
->fx_pcrel
)
23572 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23576 case BFD_RELOC_ARM_THUMB_MOVW
:
23577 if (fixp
->fx_pcrel
)
23579 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23583 case BFD_RELOC_ARM_THUMB_MOVT
:
23584 if (fixp
->fx_pcrel
)
23586 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23590 case BFD_RELOC_NONE
:
23591 case BFD_RELOC_ARM_PCREL_BRANCH
:
23592 case BFD_RELOC_ARM_PCREL_BLX
:
23593 case BFD_RELOC_RVA
:
23594 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23595 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23596 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23597 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23598 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23599 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23600 case BFD_RELOC_VTABLE_ENTRY
:
23601 case BFD_RELOC_VTABLE_INHERIT
:
23603 case BFD_RELOC_32_SECREL
:
23605 code
= fixp
->fx_r_type
;
23608 case BFD_RELOC_THUMB_PCREL_BLX
:
23610 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23611 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23614 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23617 case BFD_RELOC_ARM_LITERAL
:
23618 case BFD_RELOC_ARM_HWLITERAL
:
23619 /* If this is called then the a literal has
23620 been referenced across a section boundary. */
23621 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23622 _("literal referenced across section boundary"));
23626 case BFD_RELOC_ARM_TLS_CALL
:
23627 case BFD_RELOC_ARM_THM_TLS_CALL
:
23628 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23629 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23630 case BFD_RELOC_ARM_GOT32
:
23631 case BFD_RELOC_ARM_GOTOFF
:
23632 case BFD_RELOC_ARM_GOT_PREL
:
23633 case BFD_RELOC_ARM_PLT32
:
23634 case BFD_RELOC_ARM_TARGET1
:
23635 case BFD_RELOC_ARM_ROSEGREL32
:
23636 case BFD_RELOC_ARM_SBREL32
:
23637 case BFD_RELOC_ARM_PREL31
:
23638 case BFD_RELOC_ARM_TARGET2
:
23639 case BFD_RELOC_ARM_TLS_LDO32
:
23640 case BFD_RELOC_ARM_PCREL_CALL
:
23641 case BFD_RELOC_ARM_PCREL_JUMP
:
23642 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23643 case BFD_RELOC_ARM_ALU_PC_G0
:
23644 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23645 case BFD_RELOC_ARM_ALU_PC_G1
:
23646 case BFD_RELOC_ARM_ALU_PC_G2
:
23647 case BFD_RELOC_ARM_LDR_PC_G0
:
23648 case BFD_RELOC_ARM_LDR_PC_G1
:
23649 case BFD_RELOC_ARM_LDR_PC_G2
:
23650 case BFD_RELOC_ARM_LDRS_PC_G0
:
23651 case BFD_RELOC_ARM_LDRS_PC_G1
:
23652 case BFD_RELOC_ARM_LDRS_PC_G2
:
23653 case BFD_RELOC_ARM_LDC_PC_G0
:
23654 case BFD_RELOC_ARM_LDC_PC_G1
:
23655 case BFD_RELOC_ARM_LDC_PC_G2
:
23656 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23657 case BFD_RELOC_ARM_ALU_SB_G0
:
23658 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23659 case BFD_RELOC_ARM_ALU_SB_G1
:
23660 case BFD_RELOC_ARM_ALU_SB_G2
:
23661 case BFD_RELOC_ARM_LDR_SB_G0
:
23662 case BFD_RELOC_ARM_LDR_SB_G1
:
23663 case BFD_RELOC_ARM_LDR_SB_G2
:
23664 case BFD_RELOC_ARM_LDRS_SB_G0
:
23665 case BFD_RELOC_ARM_LDRS_SB_G1
:
23666 case BFD_RELOC_ARM_LDRS_SB_G2
:
23667 case BFD_RELOC_ARM_LDC_SB_G0
:
23668 case BFD_RELOC_ARM_LDC_SB_G1
:
23669 case BFD_RELOC_ARM_LDC_SB_G2
:
23670 case BFD_RELOC_ARM_V4BX
:
23671 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23672 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23673 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23674 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23675 code
= fixp
->fx_r_type
;
23678 case BFD_RELOC_ARM_TLS_GOTDESC
:
23679 case BFD_RELOC_ARM_TLS_GD32
:
23680 case BFD_RELOC_ARM_TLS_LE32
:
23681 case BFD_RELOC_ARM_TLS_IE32
:
23682 case BFD_RELOC_ARM_TLS_LDM32
:
23683 /* BFD will include the symbol's address in the addend.
23684 But we don't want that, so subtract it out again here. */
23685 if (!S_IS_COMMON (fixp
->fx_addsy
))
23686 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23687 code
= fixp
->fx_r_type
;
23691 case BFD_RELOC_ARM_IMMEDIATE
:
23692 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23693 _("internal relocation (type: IMMEDIATE) not fixed up"));
23696 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23697 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23698 _("ADRL used for a symbol not defined in the same file"));
23701 case BFD_RELOC_ARM_OFFSET_IMM
:
23702 if (section
->use_rela_p
)
23704 code
= fixp
->fx_r_type
;
23708 if (fixp
->fx_addsy
!= NULL
23709 && !S_IS_DEFINED (fixp
->fx_addsy
)
23710 && S_IS_LOCAL (fixp
->fx_addsy
))
23712 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23713 _("undefined local label `%s'"),
23714 S_GET_NAME (fixp
->fx_addsy
));
23718 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23719 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23726 switch (fixp
->fx_r_type
)
23728 case BFD_RELOC_NONE
: type
= "NONE"; break;
23729 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23730 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23731 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23732 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23733 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23734 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23735 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23736 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23737 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23738 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23739 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23740 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23741 default: type
= _("<unknown>"); break;
23743 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23744 _("cannot represent %s relocation in this object file format"),
23751 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23753 && fixp
->fx_addsy
== GOT_symbol
)
23755 code
= BFD_RELOC_ARM_GOTPC
;
23756 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23760 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23762 if (reloc
->howto
== NULL
)
23764 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23765 _("cannot represent %s relocation in this object file format"),
23766 bfd_get_reloc_code_name (code
));
23770 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23771 vtable entry to be used in the relocation's section offset. */
23772 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23773 reloc
->address
= fixp
->fx_offset
;
23778 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23781 cons_fix_new_arm (fragS
* frag
,
23785 bfd_reloc_code_real_type reloc
)
23790 FIXME: @@ Should look at CPU word size. */
23794 reloc
= BFD_RELOC_8
;
23797 reloc
= BFD_RELOC_16
;
23801 reloc
= BFD_RELOC_32
;
23804 reloc
= BFD_RELOC_64
;
23809 if (exp
->X_op
== O_secrel
)
23811 exp
->X_op
= O_symbol
;
23812 reloc
= BFD_RELOC_32_SECREL
;
23816 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23819 #if defined (OBJ_COFF)
23821 arm_validate_fix (fixS
* fixP
)
23823 /* If the destination of the branch is a defined symbol which does not have
23824 the THUMB_FUNC attribute, then we must be calling a function which has
23825 the (interfacearm) attribute. We look for the Thumb entry point to that
23826 function and change the branch to refer to that function instead. */
23827 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23828 && fixP
->fx_addsy
!= NULL
23829 && S_IS_DEFINED (fixP
->fx_addsy
)
23830 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23832 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23839 arm_force_relocation (struct fix
* fixp
)
23841 #if defined (OBJ_COFF) && defined (TE_PE)
23842 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23846 /* In case we have a call or a branch to a function in ARM ISA mode from
23847 a thumb function or vice-versa force the relocation. These relocations
23848 are cleared off for some cores that might have blx and simple transformations
23852 switch (fixp
->fx_r_type
)
23854 case BFD_RELOC_ARM_PCREL_JUMP
:
23855 case BFD_RELOC_ARM_PCREL_CALL
:
23856 case BFD_RELOC_THUMB_PCREL_BLX
:
23857 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23861 case BFD_RELOC_ARM_PCREL_BLX
:
23862 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23863 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23864 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23865 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23874 /* Resolve these relocations even if the symbol is extern or weak.
23875 Technically this is probably wrong due to symbol preemption.
23876 In practice these relocations do not have enough range to be useful
23877 at dynamic link time, and some code (e.g. in the Linux kernel)
23878 expects these references to be resolved. */
23879 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23880 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23881 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23882 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23883 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23884 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23885 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23886 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23887 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23888 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23889 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23890 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23891 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23892 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23895 /* Always leave these relocations for the linker. */
23896 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23897 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23898 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23901 /* Always generate relocations against function symbols. */
23902 if (fixp
->fx_r_type
== BFD_RELOC_32
23904 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23907 return generic_force_reloc (fixp
);
23910 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23911 /* Relocations against function names must be left unadjusted,
23912 so that the linker can use this information to generate interworking
23913 stubs. The MIPS version of this function
23914 also prevents relocations that are mips-16 specific, but I do not
23915 know why it does this.
23918 There is one other problem that ought to be addressed here, but
23919 which currently is not: Taking the address of a label (rather
23920 than a function) and then later jumping to that address. Such
23921 addresses also ought to have their bottom bit set (assuming that
23922 they reside in Thumb code), but at the moment they will not. */
23925 arm_fix_adjustable (fixS
* fixP
)
23927 if (fixP
->fx_addsy
== NULL
)
23930 /* Preserve relocations against symbols with function type. */
23931 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23934 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23935 && fixP
->fx_subsy
== NULL
)
23938 /* We need the symbol name for the VTABLE entries. */
23939 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23940 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23943 /* Don't allow symbols to be discarded on GOT related relocs. */
23944 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23945 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23946 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23947 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23948 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23949 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23950 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23951 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23952 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23953 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23954 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23955 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23956 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23957 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23960 /* Similarly for group relocations. */
23961 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23962 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23963 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23966 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23967 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23968 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23969 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23970 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23971 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23972 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23973 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23974 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23977 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
23978 offsets, so keep these symbols. */
23979 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
23980 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
23985 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23990 elf32_arm_target_format (void)
23993 return (target_big_endian
23994 ? "elf32-bigarm-symbian"
23995 : "elf32-littlearm-symbian");
23996 #elif defined (TE_VXWORKS)
23997 return (target_big_endian
23998 ? "elf32-bigarm-vxworks"
23999 : "elf32-littlearm-vxworks");
24000 #elif defined (TE_NACL)
24001 return (target_big_endian
24002 ? "elf32-bigarm-nacl"
24003 : "elf32-littlearm-nacl");
24005 if (target_big_endian
)
24006 return "elf32-bigarm";
24008 return "elf32-littlearm";
24013 armelf_frob_symbol (symbolS
* symp
,
24016 elf_frob_symbol (symp
, puntp
);
24020 /* MD interface: Finalization. */
24025 literal_pool
* pool
;
24027 /* Ensure that all the IT blocks are properly closed. */
24028 check_it_blocks_finished ();
24030 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24032 /* Put it at the end of the relevant section. */
24033 subseg_set (pool
->section
, pool
->sub_section
);
24035 arm_elf_change_section ();
24042 /* Remove any excess mapping symbols generated for alignment frags in
24043 SEC. We may have created a mapping symbol before a zero byte
24044 alignment; remove it if there's a mapping symbol after the
24047 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24048 void *dummy ATTRIBUTE_UNUSED
)
24050 segment_info_type
*seginfo
= seg_info (sec
);
24053 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24056 for (fragp
= seginfo
->frchainP
->frch_root
;
24058 fragp
= fragp
->fr_next
)
24060 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24061 fragS
*next
= fragp
->fr_next
;
24063 /* Variable-sized frags have been converted to fixed size by
24064 this point. But if this was variable-sized to start with,
24065 there will be a fixed-size frag after it. So don't handle
24067 if (sym
== NULL
|| next
== NULL
)
24070 if (S_GET_VALUE (sym
) < next
->fr_address
)
24071 /* Not at the end of this frag. */
24073 know (S_GET_VALUE (sym
) == next
->fr_address
);
24077 if (next
->tc_frag_data
.first_map
!= NULL
)
24079 /* Next frag starts with a mapping symbol. Discard this
24081 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24085 if (next
->fr_next
== NULL
)
24087 /* This mapping symbol is at the end of the section. Discard
24089 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24090 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24094 /* As long as we have empty frags without any mapping symbols,
24096 /* If the next frag is non-empty and does not start with a
24097 mapping symbol, then this mapping symbol is required. */
24098 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24101 next
= next
->fr_next
;
24103 while (next
!= NULL
);
24108 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24112 arm_adjust_symtab (void)
24117 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24119 if (ARM_IS_THUMB (sym
))
24121 if (THUMB_IS_FUNC (sym
))
24123 /* Mark the symbol as a Thumb function. */
24124 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24125 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24126 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24128 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24129 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24131 as_bad (_("%s: unexpected function type: %d"),
24132 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24134 else switch (S_GET_STORAGE_CLASS (sym
))
24137 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24140 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24143 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24151 if (ARM_IS_INTERWORK (sym
))
24152 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24159 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24161 if (ARM_IS_THUMB (sym
))
24163 elf_symbol_type
* elf_sym
;
24165 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24166 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24168 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24169 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24171 /* If it's a .thumb_func, declare it as so,
24172 otherwise tag label as .code 16. */
24173 if (THUMB_IS_FUNC (sym
))
24174 elf_sym
->internal_elf_sym
.st_target_internal
24175 = ST_BRANCH_TO_THUMB
;
24176 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24177 elf_sym
->internal_elf_sym
.st_info
=
24178 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24183 /* Remove any overlapping mapping symbols generated by alignment frags. */
24184 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24185 /* Now do generic ELF adjustments. */
24186 elf_adjust_symtab ();
24190 /* MD interface: Initialization. */
24193 set_constant_flonums (void)
24197 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24198 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24202 /* Auto-select Thumb mode if it's the only available instruction set for the
24203 given architecture. */
24206 autoselect_thumb_from_cpu_variant (void)
24208 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24209 opcode_select (16);
24218 if ( (arm_ops_hsh
= hash_new ()) == NULL
24219 || (arm_cond_hsh
= hash_new ()) == NULL
24220 || (arm_shift_hsh
= hash_new ()) == NULL
24221 || (arm_psr_hsh
= hash_new ()) == NULL
24222 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24223 || (arm_reg_hsh
= hash_new ()) == NULL
24224 || (arm_reloc_hsh
= hash_new ()) == NULL
24225 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24226 as_fatal (_("virtual memory exhausted"));
24228 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24229 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24230 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24231 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24232 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24233 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24234 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24235 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24236 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24237 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24238 (void *) (v7m_psrs
+ i
));
24239 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24240 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24242 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24244 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24245 (void *) (barrier_opt_names
+ i
));
24247 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24249 struct reloc_entry
* entry
= reloc_names
+ i
;
24251 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24252 /* This makes encode_branch() use the EABI versions of this relocation. */
24253 entry
->reloc
= BFD_RELOC_UNUSED
;
24255 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24259 set_constant_flonums ();
24261 /* Set the cpu variant based on the command-line options. We prefer
24262 -mcpu= over -march= if both are set (as for GCC); and we prefer
24263 -mfpu= over any other way of setting the floating point unit.
24264 Use of legacy options with new options are faulted. */
24267 if (mcpu_cpu_opt
|| march_cpu_opt
)
24268 as_bad (_("use of old and new-style options to set CPU type"));
24270 mcpu_cpu_opt
= legacy_cpu
;
24272 else if (!mcpu_cpu_opt
)
24273 mcpu_cpu_opt
= march_cpu_opt
;
24278 as_bad (_("use of old and new-style options to set FPU type"));
24280 mfpu_opt
= legacy_fpu
;
24282 else if (!mfpu_opt
)
24284 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24285 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24286 /* Some environments specify a default FPU. If they don't, infer it
24287 from the processor. */
24289 mfpu_opt
= mcpu_fpu_opt
;
24291 mfpu_opt
= march_fpu_opt
;
24293 mfpu_opt
= &fpu_default
;
24299 if (mcpu_cpu_opt
!= NULL
)
24300 mfpu_opt
= &fpu_default
;
24301 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24302 mfpu_opt
= &fpu_arch_vfp_v2
;
24304 mfpu_opt
= &fpu_arch_fpa
;
24310 mcpu_cpu_opt
= &cpu_default
;
24311 selected_cpu
= cpu_default
;
24313 else if (no_cpu_selected ())
24314 selected_cpu
= cpu_default
;
24317 selected_cpu
= *mcpu_cpu_opt
;
24319 mcpu_cpu_opt
= &arm_arch_any
;
24322 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24324 autoselect_thumb_from_cpu_variant ();
24326 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24328 #if defined OBJ_COFF || defined OBJ_ELF
24330 unsigned int flags
= 0;
24332 #if defined OBJ_ELF
24333 flags
= meabi_flags
;
24335 switch (meabi_flags
)
24337 case EF_ARM_EABI_UNKNOWN
:
24339 /* Set the flags in the private structure. */
24340 if (uses_apcs_26
) flags
|= F_APCS26
;
24341 if (support_interwork
) flags
|= F_INTERWORK
;
24342 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24343 if (pic_code
) flags
|= F_PIC
;
24344 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24345 flags
|= F_SOFT_FLOAT
;
24347 switch (mfloat_abi_opt
)
24349 case ARM_FLOAT_ABI_SOFT
:
24350 case ARM_FLOAT_ABI_SOFTFP
:
24351 flags
|= F_SOFT_FLOAT
;
24354 case ARM_FLOAT_ABI_HARD
:
24355 if (flags
& F_SOFT_FLOAT
)
24356 as_bad (_("hard-float conflicts with specified fpu"));
24360 /* Using pure-endian doubles (even if soft-float). */
24361 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24362 flags
|= F_VFP_FLOAT
;
24364 #if defined OBJ_ELF
24365 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24366 flags
|= EF_ARM_MAVERICK_FLOAT
;
24369 case EF_ARM_EABI_VER4
:
24370 case EF_ARM_EABI_VER5
:
24371 /* No additional flags to set. */
24378 bfd_set_private_flags (stdoutput
, flags
);
24380 /* We have run out flags in the COFF header to encode the
24381 status of ATPCS support, so instead we create a dummy,
24382 empty, debug section called .arm.atpcs. */
24387 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24391 bfd_set_section_flags
24392 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24393 bfd_set_section_size (stdoutput
, sec
, 0);
24394 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24400 /* Record the CPU type as well. */
24401 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24402 mach
= bfd_mach_arm_iWMMXt2
;
24403 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24404 mach
= bfd_mach_arm_iWMMXt
;
24405 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24406 mach
= bfd_mach_arm_XScale
;
24407 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24408 mach
= bfd_mach_arm_ep9312
;
24409 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24410 mach
= bfd_mach_arm_5TE
;
24411 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24413 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24414 mach
= bfd_mach_arm_5T
;
24416 mach
= bfd_mach_arm_5
;
24418 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24420 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24421 mach
= bfd_mach_arm_4T
;
24423 mach
= bfd_mach_arm_4
;
24425 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24426 mach
= bfd_mach_arm_3M
;
24427 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24428 mach
= bfd_mach_arm_3
;
24429 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24430 mach
= bfd_mach_arm_2a
;
24431 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24432 mach
= bfd_mach_arm_2
;
24434 mach
= bfd_mach_arm_unknown
;
24436 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24439 /* Command line processing. */
24442 Invocation line includes a switch not recognized by the base assembler.
24443 See if it's a processor-specific option.
24445 This routine is somewhat complicated by the need for backwards
24446 compatibility (since older releases of gcc can't be changed).
24447 The new options try to make the interface as compatible as
24450 New options (supported) are:
24452 -mcpu=<cpu name> Assemble for selected processor
24453 -march=<architecture name> Assemble for selected architecture
24454 -mfpu=<fpu architecture> Assemble for selected FPU.
24455 -EB/-mbig-endian Big-endian
24456 -EL/-mlittle-endian Little-endian
24457 -k Generate PIC code
24458 -mthumb Start in Thumb mode
24459 -mthumb-interwork Code supports ARM/Thumb interworking
24461 -m[no-]warn-deprecated Warn about deprecated features
24462 -m[no-]warn-syms Warn when symbols match instructions
24464 For now we will also provide support for:
24466 -mapcs-32 32-bit Program counter
24467 -mapcs-26 26-bit Program counter
24468 -macps-float Floats passed in FP registers
24469 -mapcs-reentrant Reentrant code
24471 (sometime these will probably be replaced with -mapcs=<list of options>
24472 and -matpcs=<list of options>)
24474 The remaining options are only supported for back-wards compatibility.
24475 Cpu variants, the arm part is optional:
24476 -m[arm]1 Currently not supported.
24477 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24478 -m[arm]3 Arm 3 processor
24479 -m[arm]6[xx], Arm 6 processors
24480 -m[arm]7[xx][t][[d]m] Arm 7 processors
24481 -m[arm]8[10] Arm 8 processors
24482 -m[arm]9[20][tdmi] Arm 9 processors
24483 -mstrongarm[110[0]] StrongARM processors
24484 -mxscale XScale processors
24485 -m[arm]v[2345[t[e]]] Arm architectures
24486 -mall All (except the ARM1)
24488 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24489 -mfpe-old (No float load/store multiples)
24490 -mvfpxd VFP Single precision
24492 -mno-fpu Disable all floating point instructions
24494 The following CPU names are recognized:
24495 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24496 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24497 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24498 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24499 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24500 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24501 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24505 const char * md_shortopts
= "m:k";
24507 #ifdef ARM_BI_ENDIAN
24508 #define OPTION_EB (OPTION_MD_BASE + 0)
24509 #define OPTION_EL (OPTION_MD_BASE + 1)
24511 #if TARGET_BYTES_BIG_ENDIAN
24512 #define OPTION_EB (OPTION_MD_BASE + 0)
24514 #define OPTION_EL (OPTION_MD_BASE + 1)
24517 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24519 struct option md_longopts
[] =
24522 {"EB", no_argument
, NULL
, OPTION_EB
},
24525 {"EL", no_argument
, NULL
, OPTION_EL
},
24527 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24528 {NULL
, no_argument
, NULL
, 0}
24532 size_t md_longopts_size
= sizeof (md_longopts
);
24534 struct arm_option_table
24536 char *option
; /* Option name to match. */
24537 char *help
; /* Help information. */
24538 int *var
; /* Variable to change. */
24539 int value
; /* What to change it to. */
24540 char *deprecated
; /* If non-null, print this message. */
24543 struct arm_option_table arm_opts
[] =
24545 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24546 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24547 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24548 &support_interwork
, 1, NULL
},
24549 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24550 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24551 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24553 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24554 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24555 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24556 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24559 /* These are recognized by the assembler, but have no affect on code. */
24560 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24561 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24563 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24564 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24565 &warn_on_deprecated
, 0, NULL
},
24566 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24567 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24568 {NULL
, NULL
, NULL
, 0, NULL
}
24571 struct arm_legacy_option_table
24573 char *option
; /* Option name to match. */
24574 const arm_feature_set
**var
; /* Variable to change. */
24575 const arm_feature_set value
; /* What to change it to. */
24576 char *deprecated
; /* If non-null, print this message. */
24579 const struct arm_legacy_option_table arm_legacy_opts
[] =
24581 /* DON'T add any new processors to this list -- we want the whole list
24582 to go away... Add them to the processors table instead. */
24583 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24584 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24585 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24586 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24587 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24588 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24589 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24590 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24591 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24592 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24593 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24594 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24595 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24596 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24597 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24598 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24599 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24600 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24601 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24602 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24603 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24604 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24605 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24606 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24607 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24608 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24609 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24610 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24611 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24612 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24613 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24614 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24615 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24616 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24617 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24618 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24619 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24620 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24621 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24622 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24623 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24624 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24625 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24626 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24627 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24628 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24629 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24630 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24631 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24632 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24633 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24634 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24635 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24636 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24637 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24638 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24639 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24640 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24641 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24642 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24643 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24644 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24645 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24646 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24647 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24648 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24649 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24650 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24651 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24652 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24653 N_("use -mcpu=strongarm110")},
24654 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24655 N_("use -mcpu=strongarm1100")},
24656 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24657 N_("use -mcpu=strongarm1110")},
24658 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24659 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24660 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24662 /* Architecture variants -- don't add any more to this list either. */
24663 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24664 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24665 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24666 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24667 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24668 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24669 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24670 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24671 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24672 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24673 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24674 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24675 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24676 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24677 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24678 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24679 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24680 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24682 /* Floating point variants -- don't add any more to this list either. */
24683 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24684 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24685 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24686 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24687 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24689 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24692 struct arm_cpu_option_table
24696 const arm_feature_set value
;
24697 /* For some CPUs we assume an FPU unless the user explicitly sets
24699 const arm_feature_set default_fpu
;
24700 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24702 const char *canonical_name
;
24705 /* This list should, at a minimum, contain all the cpu names
24706 recognized by GCC. */
24707 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24708 static const struct arm_cpu_option_table arm_cpus
[] =
24710 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24711 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24712 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24713 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24714 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24715 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24716 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24717 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24718 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24719 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24720 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24721 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24722 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24723 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24724 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24725 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24726 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24727 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24728 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24729 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24730 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24731 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24732 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24733 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24734 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24735 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24736 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24737 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24738 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24739 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24740 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24741 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24742 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24743 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24744 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24745 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24746 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24747 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24748 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24749 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24750 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24751 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24752 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24753 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24754 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24755 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24756 /* For V5 or later processors we default to using VFP; but the user
24757 should really set the FPU type explicitly. */
24758 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24759 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24760 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24761 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24762 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24763 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24764 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24765 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24766 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24767 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24768 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24769 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24770 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24771 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24772 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24773 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24774 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24775 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24776 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24777 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24779 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24780 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24781 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24782 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24783 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24784 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24785 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24786 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24787 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24789 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24790 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24791 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24792 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24793 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24794 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24795 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24796 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24797 FPU_NONE
, "Cortex-A5"),
24798 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24800 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24801 ARM_FEATURE_COPROC (FPU_VFP_V3
24802 | FPU_NEON_EXT_V1
),
24804 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24805 ARM_FEATURE_COPROC (FPU_VFP_V3
24806 | FPU_NEON_EXT_V1
),
24808 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24810 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24812 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24814 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24816 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24818 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24820 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24822 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24823 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24825 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24826 FPU_NONE
, "Cortex-R5"),
24827 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24828 FPU_ARCH_VFP_V3D16
,
24830 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24831 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24832 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24833 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24834 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24835 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24836 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24839 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24843 /* ??? XSCALE is really an architecture. */
24844 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24845 /* ??? iwmmxt is not a processor. */
24846 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24847 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24848 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24850 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24851 FPU_ARCH_MAVERICK
, "ARM920T"),
24852 /* Marvell processors. */
24853 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24855 FPU_ARCH_VFP_V3D16
, NULL
),
24856 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24858 FPU_ARCH_NEON_VFP_V4
, NULL
),
24859 /* APM X-Gene family. */
24860 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24862 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24865 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24869 struct arm_arch_option_table
24873 const arm_feature_set value
;
24874 const arm_feature_set default_fpu
;
24877 /* This list should, at a minimum, contain all the architecture names
24878 recognized by GCC. */
24879 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24880 static const struct arm_arch_option_table arm_archs
[] =
24882 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24883 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24884 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24885 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24886 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24887 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24888 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24889 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24890 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24891 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24892 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24893 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24894 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24895 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24896 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24897 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24898 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24899 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24900 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24901 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24902 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24903 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24904 kept to preserve existing behaviour. */
24905 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24906 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24907 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24908 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24909 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24910 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24911 kept to preserve existing behaviour. */
24912 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24913 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24914 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24915 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24916 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24917 /* The official spelling of the ARMv7 profile variants is the dashed form.
24918 Accept the non-dashed form for compatibility with old toolchains. */
24919 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24920 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24921 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24922 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24923 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24924 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24925 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24926 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24927 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24928 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24929 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
24930 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24931 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24932 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24933 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24935 #undef ARM_ARCH_OPT
24937 /* ISA extensions in the co-processor and main instruction set space. */
24938 struct arm_option_extension_value_table
24942 const arm_feature_set merge_value
;
24943 const arm_feature_set clear_value
;
24944 const arm_feature_set allowed_archs
;
24947 /* The following table must be in alphabetical order with a NULL last entry.
24949 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24950 static const struct arm_option_extension_value_table arm_extensions
[] =
24952 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24953 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24954 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24955 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24956 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24957 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24958 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24959 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24960 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24961 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24962 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24963 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24964 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24965 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24966 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24967 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24968 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24969 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24970 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24971 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24972 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24973 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24974 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24975 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24976 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24977 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24978 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24979 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24980 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24981 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24982 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24983 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24985 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24986 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24987 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24988 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24989 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24990 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24991 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24992 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24996 /* ISA floating-point and Advanced SIMD extensions. */
24997 struct arm_option_fpu_value_table
25000 const arm_feature_set value
;
25003 /* This list should, at a minimum, contain all the fpu names
25004 recognized by GCC. */
25005 static const struct arm_option_fpu_value_table arm_fpus
[] =
25007 {"softfpa", FPU_NONE
},
25008 {"fpe", FPU_ARCH_FPE
},
25009 {"fpe2", FPU_ARCH_FPE
},
25010 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25011 {"fpa", FPU_ARCH_FPA
},
25012 {"fpa10", FPU_ARCH_FPA
},
25013 {"fpa11", FPU_ARCH_FPA
},
25014 {"arm7500fe", FPU_ARCH_FPA
},
25015 {"softvfp", FPU_ARCH_VFP
},
25016 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25017 {"vfp", FPU_ARCH_VFP_V2
},
25018 {"vfp9", FPU_ARCH_VFP_V2
},
25019 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25020 {"vfp10", FPU_ARCH_VFP_V2
},
25021 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25022 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25023 {"vfpv2", FPU_ARCH_VFP_V2
},
25024 {"vfpv3", FPU_ARCH_VFP_V3
},
25025 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25026 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25027 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25028 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25029 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25030 {"arm1020t", FPU_ARCH_VFP_V1
},
25031 {"arm1020e", FPU_ARCH_VFP_V2
},
25032 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25033 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25034 {"maverick", FPU_ARCH_MAVERICK
},
25035 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25036 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25037 {"vfpv4", FPU_ARCH_VFP_V4
},
25038 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25039 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25040 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25041 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25042 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25043 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25044 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25045 {"crypto-neon-fp-armv8",
25046 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25047 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25048 {"crypto-neon-fp-armv8.1",
25049 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25050 {NULL
, ARM_ARCH_NONE
}
25053 struct arm_option_value_table
25059 static const struct arm_option_value_table arm_float_abis
[] =
25061 {"hard", ARM_FLOAT_ABI_HARD
},
25062 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25063 {"soft", ARM_FLOAT_ABI_SOFT
},
25068 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25069 static const struct arm_option_value_table arm_eabis
[] =
25071 {"gnu", EF_ARM_EABI_UNKNOWN
},
25072 {"4", EF_ARM_EABI_VER4
},
25073 {"5", EF_ARM_EABI_VER5
},
25078 struct arm_long_option_table
25080 char * option
; /* Substring to match. */
25081 char * help
; /* Help information. */
25082 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25083 char * deprecated
; /* If non-null, print this message. */
25087 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25089 arm_feature_set
*ext_set
= (arm_feature_set
*)
25090 xmalloc (sizeof (arm_feature_set
));
25092 /* We insist on extensions being specified in alphabetical order, and with
25093 extensions being added before being removed. We achieve this by having
25094 the global ARM_EXTENSIONS table in alphabetical order, and using the
25095 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25096 or removing it (0) and only allowing it to change in the order
25098 const struct arm_option_extension_value_table
* opt
= NULL
;
25099 int adding_value
= -1;
25101 /* Copy the feature set, so that we can modify it. */
25102 *ext_set
= **opt_p
;
25105 while (str
!= NULL
&& *str
!= 0)
25112 as_bad (_("invalid architectural extension"));
25117 ext
= strchr (str
, '+');
25122 len
= strlen (str
);
25124 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25126 if (adding_value
!= 0)
25129 opt
= arm_extensions
;
25137 if (adding_value
== -1)
25140 opt
= arm_extensions
;
25142 else if (adding_value
!= 1)
25144 as_bad (_("must specify extensions to add before specifying "
25145 "those to remove"));
25152 as_bad (_("missing architectural extension"));
25156 gas_assert (adding_value
!= -1);
25157 gas_assert (opt
!= NULL
);
25159 /* Scan over the options table trying to find an exact match. */
25160 for (; opt
->name
!= NULL
; opt
++)
25161 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25163 /* Check we can apply the extension to this architecture. */
25164 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25166 as_bad (_("extension does not apply to the base architecture"));
25170 /* Add or remove the extension. */
25172 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25174 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25179 if (opt
->name
== NULL
)
25181 /* Did we fail to find an extension because it wasn't specified in
25182 alphabetical order, or because it does not exist? */
25184 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25185 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25188 if (opt
->name
== NULL
)
25189 as_bad (_("unknown architectural extension `%s'"), str
);
25191 as_bad (_("architectural extensions must be specified in "
25192 "alphabetical order"));
25198 /* We should skip the extension we've just matched the next time
25210 arm_parse_cpu (char *str
)
25212 const struct arm_cpu_option_table
*opt
;
25213 char *ext
= strchr (str
, '+');
25219 len
= strlen (str
);
25223 as_bad (_("missing cpu name `%s'"), str
);
25227 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25228 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25230 mcpu_cpu_opt
= &opt
->value
;
25231 mcpu_fpu_opt
= &opt
->default_fpu
;
25232 if (opt
->canonical_name
)
25234 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25235 strcpy (selected_cpu_name
, opt
->canonical_name
);
25241 if (len
>= sizeof selected_cpu_name
)
25242 len
= (sizeof selected_cpu_name
) - 1;
25244 for (i
= 0; i
< len
; i
++)
25245 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25246 selected_cpu_name
[i
] = 0;
25250 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25255 as_bad (_("unknown cpu `%s'"), str
);
25260 arm_parse_arch (char *str
)
25262 const struct arm_arch_option_table
*opt
;
25263 char *ext
= strchr (str
, '+');
25269 len
= strlen (str
);
25273 as_bad (_("missing architecture name `%s'"), str
);
25277 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25278 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25280 march_cpu_opt
= &opt
->value
;
25281 march_fpu_opt
= &opt
->default_fpu
;
25282 strcpy (selected_cpu_name
, opt
->name
);
25285 return arm_parse_extension (ext
, &march_cpu_opt
);
25290 as_bad (_("unknown architecture `%s'\n"), str
);
25295 arm_parse_fpu (char * str
)
25297 const struct arm_option_fpu_value_table
* opt
;
25299 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25300 if (streq (opt
->name
, str
))
25302 mfpu_opt
= &opt
->value
;
25306 as_bad (_("unknown floating point format `%s'\n"), str
);
25311 arm_parse_float_abi (char * str
)
25313 const struct arm_option_value_table
* opt
;
25315 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25316 if (streq (opt
->name
, str
))
25318 mfloat_abi_opt
= opt
->value
;
25322 as_bad (_("unknown floating point abi `%s'\n"), str
);
25328 arm_parse_eabi (char * str
)
25330 const struct arm_option_value_table
*opt
;
25332 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25333 if (streq (opt
->name
, str
))
25335 meabi_flags
= opt
->value
;
25338 as_bad (_("unknown EABI `%s'\n"), str
);
25344 arm_parse_it_mode (char * str
)
25346 bfd_boolean ret
= TRUE
;
25348 if (streq ("arm", str
))
25349 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25350 else if (streq ("thumb", str
))
25351 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25352 else if (streq ("always", str
))
25353 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25354 else if (streq ("never", str
))
25355 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25358 as_bad (_("unknown implicit IT mode `%s', should be "\
25359 "arm, thumb, always, or never."), str
);
25367 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25369 codecomposer_syntax
= TRUE
;
25370 arm_comment_chars
[0] = ';';
25371 arm_line_separator_chars
[0] = 0;
25375 struct arm_long_option_table arm_long_opts
[] =
25377 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25378 arm_parse_cpu
, NULL
},
25379 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25380 arm_parse_arch
, NULL
},
25381 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25382 arm_parse_fpu
, NULL
},
25383 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25384 arm_parse_float_abi
, NULL
},
25386 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25387 arm_parse_eabi
, NULL
},
25389 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25390 arm_parse_it_mode
, NULL
},
25391 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25392 arm_ccs_mode
, NULL
},
25393 {NULL
, NULL
, 0, NULL
}
25397 md_parse_option (int c
, char * arg
)
25399 struct arm_option_table
*opt
;
25400 const struct arm_legacy_option_table
*fopt
;
25401 struct arm_long_option_table
*lopt
;
25407 target_big_endian
= 1;
25413 target_big_endian
= 0;
25417 case OPTION_FIX_V4BX
:
25422 /* Listing option. Just ignore these, we don't support additional
25427 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25429 if (c
== opt
->option
[0]
25430 && ((arg
== NULL
&& opt
->option
[1] == 0)
25431 || streq (arg
, opt
->option
+ 1)))
25433 /* If the option is deprecated, tell the user. */
25434 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25435 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25436 arg
? arg
: "", _(opt
->deprecated
));
25438 if (opt
->var
!= NULL
)
25439 *opt
->var
= opt
->value
;
25445 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25447 if (c
== fopt
->option
[0]
25448 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25449 || streq (arg
, fopt
->option
+ 1)))
25451 /* If the option is deprecated, tell the user. */
25452 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25453 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25454 arg
? arg
: "", _(fopt
->deprecated
));
25456 if (fopt
->var
!= NULL
)
25457 *fopt
->var
= &fopt
->value
;
25463 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25465 /* These options are expected to have an argument. */
25466 if (c
== lopt
->option
[0]
25468 && strncmp (arg
, lopt
->option
+ 1,
25469 strlen (lopt
->option
+ 1)) == 0)
25471 /* If the option is deprecated, tell the user. */
25472 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25473 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25474 _(lopt
->deprecated
));
25476 /* Call the sup-option parser. */
25477 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25488 md_show_usage (FILE * fp
)
25490 struct arm_option_table
*opt
;
25491 struct arm_long_option_table
*lopt
;
25493 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25495 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25496 if (opt
->help
!= NULL
)
25497 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25499 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25500 if (lopt
->help
!= NULL
)
25501 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25505 -EB assemble code for a big-endian cpu\n"));
25510 -EL assemble code for a little-endian cpu\n"));
25514 --fix-v4bx Allow BX in ARMv4 code\n"));
25522 arm_feature_set flags
;
25523 } cpu_arch_ver_table
;
25525 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25526 least features first. */
25527 static const cpu_arch_ver_table cpu_arch_ver
[] =
25533 {4, ARM_ARCH_V5TE
},
25534 {5, ARM_ARCH_V5TEJ
},
25538 {11, ARM_ARCH_V6M
},
25539 {12, ARM_ARCH_V6SM
},
25540 {8, ARM_ARCH_V6T2
},
25541 {10, ARM_ARCH_V7VE
},
25542 {10, ARM_ARCH_V7R
},
25543 {10, ARM_ARCH_V7M
},
25544 {14, ARM_ARCH_V8A
},
25548 /* Set an attribute if it has not already been set by the user. */
25550 aeabi_set_attribute_int (int tag
, int value
)
25553 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25554 || !attributes_set_explicitly
[tag
])
25555 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25559 aeabi_set_attribute_string (int tag
, const char *value
)
25562 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25563 || !attributes_set_explicitly
[tag
])
25564 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25567 /* Set the public EABI object attributes. */
25569 aeabi_set_public_attributes (void)
25574 int fp16_optional
= 0;
25575 arm_feature_set flags
;
25576 arm_feature_set tmp
;
25577 const cpu_arch_ver_table
*p
;
25579 /* Choose the architecture based on the capabilities of the requested cpu
25580 (if any) and/or the instructions actually used. */
25581 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25582 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25583 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25585 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25586 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25588 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25589 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25591 selected_cpu
= flags
;
25593 /* Allow the user to override the reported architecture. */
25596 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25597 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25600 /* We need to make sure that the attributes do not identify us as v6S-M
25601 when the only v6S-M feature in use is the Operating System Extensions. */
25602 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25603 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25604 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25608 for (p
= cpu_arch_ver
; p
->val
; p
++)
25610 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25613 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25617 /* The table lookup above finds the last architecture to contribute
25618 a new feature. Unfortunately, Tag13 is a subset of the union of
25619 v6T2 and v7-M, so it is never seen as contributing a new feature.
25620 We can not search for the last entry which is entirely used,
25621 because if no CPU is specified we build up only those flags
25622 actually used. Perhaps we should separate out the specified
25623 and implicit cases. Avoid taking this path for -march=all by
25624 checking for contradictory v7-A / v7-M features. */
25626 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25627 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25628 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25631 /* Tag_CPU_name. */
25632 if (selected_cpu_name
[0])
25636 q
= selected_cpu_name
;
25637 if (strncmp (q
, "armv", 4) == 0)
25642 for (i
= 0; q
[i
]; i
++)
25643 q
[i
] = TOUPPER (q
[i
]);
25645 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25648 /* Tag_CPU_arch. */
25649 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25651 /* Tag_CPU_arch_profile. */
25652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25654 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25656 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25661 if (profile
!= '\0')
25662 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25664 /* Tag_ARM_ISA_use. */
25665 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25667 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25669 /* Tag_THUMB_ISA_use. */
25670 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25672 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25673 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25675 /* Tag_VFP_arch. */
25676 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25677 aeabi_set_attribute_int (Tag_VFP_arch
,
25678 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25680 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25681 aeabi_set_attribute_int (Tag_VFP_arch
,
25682 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25684 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25687 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25689 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25691 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25694 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25695 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25696 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25697 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25698 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25700 /* Tag_ABI_HardFP_use. */
25701 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25702 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25703 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25705 /* Tag_WMMX_arch. */
25706 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25707 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25708 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25709 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25711 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25712 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25713 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25714 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25716 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25718 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25722 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25727 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25728 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25729 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25733 We set Tag_DIV_use to two when integer divide instructions have been used
25734 in ARM state, or when Thumb integer divide instructions have been used,
25735 but we have no architecture profile set, nor have we any ARM instructions.
25737 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25740 For new architectures we will have to check these tests. */
25741 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25742 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25743 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25744 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25745 || (profile
== '\0'
25746 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25747 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25748 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25750 /* Tag_MP_extension_use. */
25751 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25752 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25754 /* Tag Virtualization_use. */
25755 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25757 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25760 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25763 /* Add the default contents for the .ARM.attributes section. */
25767 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25770 aeabi_set_public_attributes ();
25772 #endif /* OBJ_ELF */
25775 /* Parse a .cpu directive. */
25778 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25780 const struct arm_cpu_option_table
*opt
;
25784 name
= input_line_pointer
;
25785 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25786 input_line_pointer
++;
25787 saved_char
= *input_line_pointer
;
25788 *input_line_pointer
= 0;
25790 /* Skip the first "all" entry. */
25791 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25792 if (streq (opt
->name
, name
))
25794 mcpu_cpu_opt
= &opt
->value
;
25795 selected_cpu
= opt
->value
;
25796 if (opt
->canonical_name
)
25797 strcpy (selected_cpu_name
, opt
->canonical_name
);
25801 for (i
= 0; opt
->name
[i
]; i
++)
25802 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25804 selected_cpu_name
[i
] = 0;
25806 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25807 *input_line_pointer
= saved_char
;
25808 demand_empty_rest_of_line ();
25811 as_bad (_("unknown cpu `%s'"), name
);
25812 *input_line_pointer
= saved_char
;
25813 ignore_rest_of_line ();
25817 /* Parse a .arch directive. */
25820 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25822 const struct arm_arch_option_table
*opt
;
25826 name
= input_line_pointer
;
25827 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25828 input_line_pointer
++;
25829 saved_char
= *input_line_pointer
;
25830 *input_line_pointer
= 0;
25832 /* Skip the first "all" entry. */
25833 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25834 if (streq (opt
->name
, name
))
25836 mcpu_cpu_opt
= &opt
->value
;
25837 selected_cpu
= opt
->value
;
25838 strcpy (selected_cpu_name
, opt
->name
);
25839 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25840 *input_line_pointer
= saved_char
;
25841 demand_empty_rest_of_line ();
25845 as_bad (_("unknown architecture `%s'\n"), name
);
25846 *input_line_pointer
= saved_char
;
25847 ignore_rest_of_line ();
25851 /* Parse a .object_arch directive. */
25854 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25856 const struct arm_arch_option_table
*opt
;
25860 name
= input_line_pointer
;
25861 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25862 input_line_pointer
++;
25863 saved_char
= *input_line_pointer
;
25864 *input_line_pointer
= 0;
25866 /* Skip the first "all" entry. */
25867 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25868 if (streq (opt
->name
, name
))
25870 object_arch
= &opt
->value
;
25871 *input_line_pointer
= saved_char
;
25872 demand_empty_rest_of_line ();
25876 as_bad (_("unknown architecture `%s'\n"), name
);
25877 *input_line_pointer
= saved_char
;
25878 ignore_rest_of_line ();
25881 /* Parse a .arch_extension directive. */
25884 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25886 const struct arm_option_extension_value_table
*opt
;
25889 int adding_value
= 1;
25891 name
= input_line_pointer
;
25892 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25893 input_line_pointer
++;
25894 saved_char
= *input_line_pointer
;
25895 *input_line_pointer
= 0;
25897 if (strlen (name
) >= 2
25898 && strncmp (name
, "no", 2) == 0)
25904 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25905 if (streq (opt
->name
, name
))
25907 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25909 as_bad (_("architectural extension `%s' is not allowed for the "
25910 "current base architecture"), name
);
25915 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25918 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25920 mcpu_cpu_opt
= &selected_cpu
;
25921 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25922 *input_line_pointer
= saved_char
;
25923 demand_empty_rest_of_line ();
25927 if (opt
->name
== NULL
)
25928 as_bad (_("unknown architecture extension `%s'\n"), name
);
25930 *input_line_pointer
= saved_char
;
25931 ignore_rest_of_line ();
25934 /* Parse a .fpu directive. */
25937 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25939 const struct arm_option_fpu_value_table
*opt
;
25943 name
= input_line_pointer
;
25944 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25945 input_line_pointer
++;
25946 saved_char
= *input_line_pointer
;
25947 *input_line_pointer
= 0;
25949 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25950 if (streq (opt
->name
, name
))
25952 mfpu_opt
= &opt
->value
;
25953 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25954 *input_line_pointer
= saved_char
;
25955 demand_empty_rest_of_line ();
25959 as_bad (_("unknown floating point format `%s'\n"), name
);
25960 *input_line_pointer
= saved_char
;
25961 ignore_rest_of_line ();
25964 /* Copy symbol information. */
25967 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25969 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25973 /* Given a symbolic attribute NAME, return the proper integer value.
25974 Returns -1 if the attribute is not known. */
25977 arm_convert_symbolic_attribute (const char *name
)
25979 static const struct
25984 attribute_table
[] =
25986 /* When you modify this table you should
25987 also modify the list in doc/c-arm.texi. */
25988 #define T(tag) {#tag, tag}
25989 T (Tag_CPU_raw_name
),
25992 T (Tag_CPU_arch_profile
),
25993 T (Tag_ARM_ISA_use
),
25994 T (Tag_THUMB_ISA_use
),
25998 T (Tag_Advanced_SIMD_arch
),
25999 T (Tag_PCS_config
),
26000 T (Tag_ABI_PCS_R9_use
),
26001 T (Tag_ABI_PCS_RW_data
),
26002 T (Tag_ABI_PCS_RO_data
),
26003 T (Tag_ABI_PCS_GOT_use
),
26004 T (Tag_ABI_PCS_wchar_t
),
26005 T (Tag_ABI_FP_rounding
),
26006 T (Tag_ABI_FP_denormal
),
26007 T (Tag_ABI_FP_exceptions
),
26008 T (Tag_ABI_FP_user_exceptions
),
26009 T (Tag_ABI_FP_number_model
),
26010 T (Tag_ABI_align_needed
),
26011 T (Tag_ABI_align8_needed
),
26012 T (Tag_ABI_align_preserved
),
26013 T (Tag_ABI_align8_preserved
),
26014 T (Tag_ABI_enum_size
),
26015 T (Tag_ABI_HardFP_use
),
26016 T (Tag_ABI_VFP_args
),
26017 T (Tag_ABI_WMMX_args
),
26018 T (Tag_ABI_optimization_goals
),
26019 T (Tag_ABI_FP_optimization_goals
),
26020 T (Tag_compatibility
),
26021 T (Tag_CPU_unaligned_access
),
26022 T (Tag_FP_HP_extension
),
26023 T (Tag_VFP_HP_extension
),
26024 T (Tag_ABI_FP_16bit_format
),
26025 T (Tag_MPextension_use
),
26027 T (Tag_nodefaults
),
26028 T (Tag_also_compatible_with
),
26029 T (Tag_conformance
),
26031 T (Tag_Virtualization_use
),
26032 /* We deliberately do not include Tag_MPextension_use_legacy. */
26040 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26041 if (streq (name
, attribute_table
[i
].name
))
26042 return attribute_table
[i
].tag
;
26048 /* Apply sym value for relocations only in the case that they are for
26049 local symbols in the same segment as the fixup and you have the
26050 respective architectural feature for blx and simple switches. */
26052 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26055 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26056 /* PR 17444: If the local symbol is in a different section then a reloc
26057 will always be generated for it, so applying the symbol value now
26058 will result in a double offset being stored in the relocation. */
26059 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26060 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26062 switch (fixP
->fx_r_type
)
26064 case BFD_RELOC_ARM_PCREL_BLX
:
26065 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26066 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26070 case BFD_RELOC_ARM_PCREL_CALL
:
26071 case BFD_RELOC_THUMB_PCREL_BLX
:
26072 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26083 #endif /* OBJ_ELF */