1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
* legacy_cpu
= NULL
;
147 static const arm_feature_set
* legacy_fpu
= NULL
;
149 static const arm_feature_set
* mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
* dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
* mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
* march_cpu_opt
= NULL
;
153 static arm_feature_set
* dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
* march_fpu_opt
= NULL
;
155 static const arm_feature_set
* mfpu_opt
= NULL
;
156 static const arm_feature_set
* object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_fp16_fml
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
240 static const arm_feature_set arm_ext_v8_2
=
241 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
242 static const arm_feature_set arm_ext_v8_3
=
243 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
245 static const arm_feature_set arm_arch_any
= ARM_ANY
;
247 static const arm_feature_set fpu_any
= FPU_ANY
;
249 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
250 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
251 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
253 static const arm_feature_set arm_cext_iwmmxt2
=
254 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
255 static const arm_feature_set arm_cext_iwmmxt
=
256 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
257 static const arm_feature_set arm_cext_xscale
=
258 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
259 static const arm_feature_set arm_cext_maverick
=
260 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
261 static const arm_feature_set fpu_fpa_ext_v1
=
262 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
263 static const arm_feature_set fpu_fpa_ext_v2
=
264 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
265 static const arm_feature_set fpu_vfp_ext_v1xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
267 static const arm_feature_set fpu_vfp_ext_v1
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
269 static const arm_feature_set fpu_vfp_ext_v2
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
271 static const arm_feature_set fpu_vfp_ext_v3xd
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
273 static const arm_feature_set fpu_vfp_ext_v3
=
274 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
275 static const arm_feature_set fpu_vfp_ext_d32
=
276 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
277 static const arm_feature_set fpu_neon_ext_v1
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
279 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
280 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
282 static const arm_feature_set fpu_vfp_fp16
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
284 static const arm_feature_set fpu_neon_ext_fma
=
285 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
287 static const arm_feature_set fpu_vfp_ext_fma
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
289 static const arm_feature_set fpu_vfp_ext_armv8
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
291 static const arm_feature_set fpu_vfp_ext_armv8xd
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
293 static const arm_feature_set fpu_neon_ext_armv8
=
294 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
295 static const arm_feature_set fpu_crypto_ext_armv8
=
296 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
297 static const arm_feature_set crc_ext_armv8
=
298 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
299 static const arm_feature_set fpu_neon_ext_v8_1
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
301 static const arm_feature_set fpu_neon_ext_dotprod
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
304 static int mfloat_abi_opt
= -1;
305 /* Record user cpu selection for object attributes. */
306 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
307 /* Must be long enough to hold any of the names in arm_cpus. */
308 static char selected_cpu_name
[20];
310 extern FLONUM_TYPE generic_floating_point_number
;
312 /* Return if no cpu was selected on command-line. */
314 no_cpu_selected (void)
316 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
321 static int meabi_flags
= EABI_DEFAULT
;
323 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
326 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
331 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
336 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
337 symbolS
* GOT_symbol
;
340 /* 0: assemble for ARM,
341 1: assemble for Thumb,
342 2: assemble for Thumb even though target CPU does not support thumb
344 static int thumb_mode
= 0;
345 /* A value distinct from the possible values for thumb_mode that we
346 can use to record whether thumb_mode has been copied into the
347 tc_frag_data field of a frag. */
348 #define MODE_RECORDED (1 << 4)
350 /* Specifies the intrinsic IT insn behavior mode. */
351 enum implicit_it_mode
353 IMPLICIT_IT_MODE_NEVER
= 0x00,
354 IMPLICIT_IT_MODE_ARM
= 0x01,
355 IMPLICIT_IT_MODE_THUMB
= 0x02,
356 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
358 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
360 /* If unified_syntax is true, we are processing the new unified
361 ARM/Thumb syntax. Important differences from the old ARM mode:
363 - Immediate operands do not require a # prefix.
364 - Conditional affixes always appear at the end of the
365 instruction. (For backward compatibility, those instructions
366 that formerly had them in the middle, continue to accept them
368 - The IT instruction may appear, and if it does is validated
369 against subsequent conditional affixes. It does not generate
372 Important differences from the old Thumb mode:
374 - Immediate operands do not require a # prefix.
375 - Most of the V6T2 instructions are only available in unified mode.
376 - The .N and .W suffixes are recognized and honored (it is an error
377 if they cannot be honored).
378 - All instructions set the flags if and only if they have an 's' affix.
379 - Conditional affixes may be used. They are validated against
380 preceding IT instructions. Unlike ARM mode, you cannot use a
381 conditional affix except in the scope of an IT instruction. */
383 static bfd_boolean unified_syntax
= FALSE
;
385 /* An immediate operand can start with #, and ld*, st*, pld operands
386 can contain [ and ]. We need to tell APP not to elide whitespace
387 before a [, which can appear as the first operand for pld.
388 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
389 const char arm_symbol_chars
[] = "#[]{}";
404 enum neon_el_type type
;
408 #define NEON_MAX_TYPE_ELS 4
412 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
416 enum it_instruction_type
421 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
422 if inside, should be the last one. */
423 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
424 i.e. BKPT and NOP. */
425 IT_INSN
/* The IT insn has been parsed. */
428 /* The maximum number of operands we need. */
429 #define ARM_IT_MAX_OPERANDS 6
434 unsigned long instruction
;
438 /* "uncond_value" is set to the value in place of the conditional field in
439 unconditional versions of the instruction, or -1 if nothing is
442 struct neon_type vectype
;
443 /* This does not indicate an actual NEON instruction, only that
444 the mnemonic accepts neon-style type suffixes. */
446 /* Set to the opcode if the instruction needs relaxation.
447 Zero if the instruction is not relaxed. */
451 bfd_reloc_code_real_type type
;
456 enum it_instruction_type it_insn_type
;
462 struct neon_type_el vectype
;
463 unsigned present
: 1; /* Operand present. */
464 unsigned isreg
: 1; /* Operand was a register. */
465 unsigned immisreg
: 1; /* .imm field is a second register. */
466 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
467 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
468 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
469 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
470 instructions. This allows us to disambiguate ARM <-> vector insns. */
471 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
472 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
473 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
474 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
475 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
476 unsigned writeback
: 1; /* Operand has trailing ! */
477 unsigned preind
: 1; /* Preindexed address. */
478 unsigned postind
: 1; /* Postindexed address. */
479 unsigned negative
: 1; /* Index register was negated. */
480 unsigned shifted
: 1; /* Shift applied to operation. */
481 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
482 } operands
[ARM_IT_MAX_OPERANDS
];
485 static struct arm_it inst
;
487 #define NUM_FLOAT_VALS 8
489 const char * fp_const
[] =
491 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
494 /* Number of littlenums required to hold an extended precision number. */
495 #define MAX_LITTLENUMS 6
497 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
507 #define CP_T_X 0x00008000
508 #define CP_T_Y 0x00400000
510 #define CONDS_BIT 0x00100000
511 #define LOAD_BIT 0x00100000
513 #define DOUBLE_LOAD_FLAG 0x00000001
517 const char * template_name
;
521 #define COND_ALWAYS 0xE
525 const char * template_name
;
529 struct asm_barrier_opt
531 const char * template_name
;
533 const arm_feature_set arch
;
536 /* The bit that distinguishes CPSR and SPSR. */
537 #define SPSR_BIT (1 << 22)
539 /* The individual PSR flag bits. */
540 #define PSR_c (1 << 16)
541 #define PSR_x (1 << 17)
542 #define PSR_s (1 << 18)
543 #define PSR_f (1 << 19)
548 bfd_reloc_code_real_type reloc
;
553 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
554 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
559 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
562 /* Bits for DEFINED field in neon_typed_alias. */
563 #define NTA_HASTYPE 1
564 #define NTA_HASINDEX 2
566 struct neon_typed_alias
568 unsigned char defined
;
570 struct neon_type_el eltype
;
573 /* ARM register categories. This includes coprocessor numbers and various
574 architecture extensions' registers. Each entry should have an error message
575 in reg_expected_msgs below. */
603 /* Structure for a hash table entry for a register.
604 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
605 information which states whether a vector type or index is specified (for a
606 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
612 unsigned char builtin
;
613 struct neon_typed_alias
* neon
;
616 /* Diagnostics used when we don't get a register of the expected type. */
617 const char * const reg_expected_msgs
[] =
619 [REG_TYPE_RN
] = N_("ARM register expected"),
620 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
621 [REG_TYPE_CN
] = N_("co-processor register expected"),
622 [REG_TYPE_FN
] = N_("FPA register expected"),
623 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
624 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
625 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
626 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
627 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
628 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
629 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
631 [REG_TYPE_VFC
] = N_("VFP system register expected"),
632 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
633 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
634 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
635 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
636 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
637 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
638 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
639 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
640 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
641 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
642 [REG_TYPE_RNB
] = N_("")
645 /* Some well known registers that we refer to directly elsewhere. */
651 /* ARM instructions take 4bytes in the object file, Thumb instructions
657 /* Basic string to match. */
658 const char * template_name
;
660 /* Parameters to instruction. */
661 unsigned int operands
[8];
663 /* Conditional tag - see opcode_lookup. */
664 unsigned int tag
: 4;
666 /* Basic instruction code. */
667 unsigned int avalue
: 28;
669 /* Thumb-format instruction code. */
672 /* Which architecture variant provides this instruction. */
673 const arm_feature_set
* avariant
;
674 const arm_feature_set
* tvariant
;
676 /* Function to call to encode instruction in ARM format. */
677 void (* aencode
) (void);
679 /* Function to call to encode instruction in Thumb format. */
680 void (* tencode
) (void);
683 /* Defines for various bits that we will want to toggle. */
684 #define INST_IMMEDIATE 0x02000000
685 #define OFFSET_REG 0x02000000
686 #define HWOFFSET_IMM 0x00400000
687 #define SHIFT_BY_REG 0x00000010
688 #define PRE_INDEX 0x01000000
689 #define INDEX_UP 0x00800000
690 #define WRITE_BACK 0x00200000
691 #define LDM_TYPE_2_OR_3 0x00400000
692 #define CPSI_MMOD 0x00020000
694 #define LITERAL_MASK 0xf000f000
695 #define OPCODE_MASK 0xfe1fffff
696 #define V4_STR_BIT 0x00000020
697 #define VLDR_VMOV_SAME 0x0040f000
699 #define T2_SUBS_PC_LR 0xf3de8f00
701 #define DATA_OP_SHIFT 21
702 #define SBIT_SHIFT 20
704 #define T2_OPCODE_MASK 0xfe1fffff
705 #define T2_DATA_OP_SHIFT 21
706 #define T2_SBIT_SHIFT 20
708 #define A_COND_MASK 0xf0000000
709 #define A_PUSH_POP_OP_MASK 0x0fff0000
711 /* Opcodes for pushing/poping registers to/from the stack. */
712 #define A1_OPCODE_PUSH 0x092d0000
713 #define A2_OPCODE_PUSH 0x052d0004
714 #define A2_OPCODE_POP 0x049d0004
716 /* Codes to distinguish the arithmetic instructions. */
727 #define OPCODE_CMP 10
728 #define OPCODE_CMN 11
729 #define OPCODE_ORR 12
730 #define OPCODE_MOV 13
731 #define OPCODE_BIC 14
732 #define OPCODE_MVN 15
734 #define T2_OPCODE_AND 0
735 #define T2_OPCODE_BIC 1
736 #define T2_OPCODE_ORR 2
737 #define T2_OPCODE_ORN 3
738 #define T2_OPCODE_EOR 4
739 #define T2_OPCODE_ADD 8
740 #define T2_OPCODE_ADC 10
741 #define T2_OPCODE_SBC 11
742 #define T2_OPCODE_SUB 13
743 #define T2_OPCODE_RSB 14
745 #define T_OPCODE_MUL 0x4340
746 #define T_OPCODE_TST 0x4200
747 #define T_OPCODE_CMN 0x42c0
748 #define T_OPCODE_NEG 0x4240
749 #define T_OPCODE_MVN 0x43c0
751 #define T_OPCODE_ADD_R3 0x1800
752 #define T_OPCODE_SUB_R3 0x1a00
753 #define T_OPCODE_ADD_HI 0x4400
754 #define T_OPCODE_ADD_ST 0xb000
755 #define T_OPCODE_SUB_ST 0xb080
756 #define T_OPCODE_ADD_SP 0xa800
757 #define T_OPCODE_ADD_PC 0xa000
758 #define T_OPCODE_ADD_I8 0x3000
759 #define T_OPCODE_SUB_I8 0x3800
760 #define T_OPCODE_ADD_I3 0x1c00
761 #define T_OPCODE_SUB_I3 0x1e00
763 #define T_OPCODE_ASR_R 0x4100
764 #define T_OPCODE_LSL_R 0x4080
765 #define T_OPCODE_LSR_R 0x40c0
766 #define T_OPCODE_ROR_R 0x41c0
767 #define T_OPCODE_ASR_I 0x1000
768 #define T_OPCODE_LSL_I 0x0000
769 #define T_OPCODE_LSR_I 0x0800
771 #define T_OPCODE_MOV_I8 0x2000
772 #define T_OPCODE_CMP_I8 0x2800
773 #define T_OPCODE_CMP_LR 0x4280
774 #define T_OPCODE_MOV_HR 0x4600
775 #define T_OPCODE_CMP_HR 0x4500
777 #define T_OPCODE_LDR_PC 0x4800
778 #define T_OPCODE_LDR_SP 0x9800
779 #define T_OPCODE_STR_SP 0x9000
780 #define T_OPCODE_LDR_IW 0x6800
781 #define T_OPCODE_STR_IW 0x6000
782 #define T_OPCODE_LDR_IH 0x8800
783 #define T_OPCODE_STR_IH 0x8000
784 #define T_OPCODE_LDR_IB 0x7800
785 #define T_OPCODE_STR_IB 0x7000
786 #define T_OPCODE_LDR_RW 0x5800
787 #define T_OPCODE_STR_RW 0x5000
788 #define T_OPCODE_LDR_RH 0x5a00
789 #define T_OPCODE_STR_RH 0x5200
790 #define T_OPCODE_LDR_RB 0x5c00
791 #define T_OPCODE_STR_RB 0x5400
793 #define T_OPCODE_PUSH 0xb400
794 #define T_OPCODE_POP 0xbc00
796 #define T_OPCODE_BRANCH 0xe000
798 #define THUMB_SIZE 2 /* Size of thumb instruction. */
799 #define THUMB_PP_PC_LR 0x0100
800 #define THUMB_LOAD_BIT 0x0800
801 #define THUMB2_LOAD_BIT 0x00100000
803 #define BAD_ARGS _("bad arguments to instruction")
804 #define BAD_SP _("r13 not allowed here")
805 #define BAD_PC _("r15 not allowed here")
806 #define BAD_COND _("instruction cannot be conditional")
807 #define BAD_OVERLAP _("registers may not be the same")
808 #define BAD_HIREG _("lo register required")
809 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
810 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
811 #define BAD_BRANCH _("branch must be last instruction in IT block")
812 #define BAD_NOT_IT _("instruction not allowed in IT block")
813 #define BAD_FPU _("selected FPU does not support instruction")
814 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
815 #define BAD_IT_COND _("incorrect condition in IT block")
816 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
817 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
818 #define BAD_PC_ADDRESSING \
819 _("cannot use register index with PC-relative addressing")
820 #define BAD_PC_WRITEBACK \
821 _("cannot use writeback with PC-relative addressing")
822 #define BAD_RANGE _("branch out of range")
823 #define BAD_FP16 _("selected processor does not support fp16 instruction")
824 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
825 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
827 static struct hash_control
* arm_ops_hsh
;
828 static struct hash_control
* arm_cond_hsh
;
829 static struct hash_control
* arm_shift_hsh
;
830 static struct hash_control
* arm_psr_hsh
;
831 static struct hash_control
* arm_v7m_psr_hsh
;
832 static struct hash_control
* arm_reg_hsh
;
833 static struct hash_control
* arm_reloc_hsh
;
834 static struct hash_control
* arm_barrier_opt_hsh
;
836 /* Stuff needed to resolve the label ambiguity
845 symbolS
* last_label_seen
;
846 static int label_is_thumb_function_name
= FALSE
;
848 /* Literal pool structure. Held on a per-section
849 and per-sub-section basis. */
851 #define MAX_LITERAL_POOL_SIZE 1024
852 typedef struct literal_pool
854 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
855 unsigned int next_free_entry
;
861 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
863 struct literal_pool
* next
;
864 unsigned int alignment
;
867 /* Pointer to a linked list of literal pools. */
868 literal_pool
* list_of_pools
= NULL
;
870 typedef enum asmfunc_states
873 WAITING_ASMFUNC_NAME
,
877 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
880 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
882 static struct current_it now_it
;
886 now_it_compatible (int cond
)
888 return (cond
& ~1) == (now_it
.cc
& ~1);
892 conditional_insn (void)
894 return inst
.cond
!= COND_ALWAYS
;
897 static int in_it_block (void);
899 static int handle_it_state (void);
901 static void force_automatic_it_block_close (void);
903 static void it_fsm_post_encode (void);
905 #define set_it_insn_type(type) \
908 inst.it_insn_type = type; \
909 if (handle_it_state () == FAIL) \
914 #define set_it_insn_type_nonvoid(type, failret) \
917 inst.it_insn_type = type; \
918 if (handle_it_state () == FAIL) \
923 #define set_it_insn_type_last() \
926 if (inst.cond == COND_ALWAYS) \
927 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
929 set_it_insn_type (INSIDE_IT_LAST_INSN); \
935 /* This array holds the chars that always start a comment. If the
936 pre-processor is disabled, these aren't very useful. */
937 char arm_comment_chars
[] = "@";
939 /* This array holds the chars that only start a comment at the beginning of
940 a line. If the line seems to have the form '# 123 filename'
941 .line and .file directives will appear in the pre-processed output. */
942 /* Note that input_file.c hand checks for '#' at the beginning of the
943 first line of the input file. This is because the compiler outputs
944 #NO_APP at the beginning of its output. */
945 /* Also note that comments like this one will always work. */
946 const char line_comment_chars
[] = "#";
948 char arm_line_separator_chars
[] = ";";
950 /* Chars that can be used to separate mant
951 from exp in floating point numbers. */
952 const char EXP_CHARS
[] = "eE";
954 /* Chars that mean this number is a floating point constant. */
958 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
960 /* Prefix characters that indicate the start of an immediate
962 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
964 /* Separator character handling. */
966 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
969 skip_past_char (char ** str
, char c
)
971 /* PR gas/14987: Allow for whitespace before the expected character. */
972 skip_whitespace (*str
);
983 #define skip_past_comma(str) skip_past_char (str, ',')
985 /* Arithmetic expressions (possibly involving symbols). */
987 /* Return TRUE if anything in the expression is a bignum. */
990 walk_no_bignums (symbolS
* sp
)
992 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
995 if (symbol_get_value_expression (sp
)->X_add_symbol
)
997 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
998 || (symbol_get_value_expression (sp
)->X_op_symbol
999 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1005 static bfd_boolean in_my_get_expression
= FALSE
;
1007 /* Third argument to my_get_expression. */
1008 #define GE_NO_PREFIX 0
1009 #define GE_IMM_PREFIX 1
1010 #define GE_OPT_PREFIX 2
1011 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1012 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1013 #define GE_OPT_PREFIX_BIG 3
1016 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1021 /* In unified syntax, all prefixes are optional. */
1023 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1026 switch (prefix_mode
)
1028 case GE_NO_PREFIX
: break;
1030 if (!is_immediate_prefix (**str
))
1032 inst
.error
= _("immediate expression requires a # prefix");
1038 case GE_OPT_PREFIX_BIG
:
1039 if (is_immediate_prefix (**str
))
1046 memset (ep
, 0, sizeof (expressionS
));
1048 save_in
= input_line_pointer
;
1049 input_line_pointer
= *str
;
1050 in_my_get_expression
= TRUE
;
1051 seg
= expression (ep
);
1052 in_my_get_expression
= FALSE
;
1054 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1056 /* We found a bad or missing expression in md_operand(). */
1057 *str
= input_line_pointer
;
1058 input_line_pointer
= save_in
;
1059 if (inst
.error
== NULL
)
1060 inst
.error
= (ep
->X_op
== O_absent
1061 ? _("missing expression") :_("bad expression"));
1066 if (seg
!= absolute_section
1067 && seg
!= text_section
1068 && seg
!= data_section
1069 && seg
!= bss_section
1070 && seg
!= undefined_section
)
1072 inst
.error
= _("bad segment");
1073 *str
= input_line_pointer
;
1074 input_line_pointer
= save_in
;
1081 /* Get rid of any bignums now, so that we don't generate an error for which
1082 we can't establish a line number later on. Big numbers are never valid
1083 in instructions, which is where this routine is always called. */
1084 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1085 && (ep
->X_op
== O_big
1086 || (ep
->X_add_symbol
1087 && (walk_no_bignums (ep
->X_add_symbol
)
1089 && walk_no_bignums (ep
->X_op_symbol
))))))
1091 inst
.error
= _("invalid constant");
1092 *str
= input_line_pointer
;
1093 input_line_pointer
= save_in
;
1097 *str
= input_line_pointer
;
1098 input_line_pointer
= save_in
;
1102 /* Turn a string in input_line_pointer into a floating point constant
1103 of type TYPE, and store the appropriate bytes in *LITP. The number
1104 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1105 returned, or NULL on OK.
1107 Note that fp constants aren't represent in the normal way on the ARM.
1108 In big endian mode, things are as expected. However, in little endian
1109 mode fp constants are big-endian word-wise, and little-endian byte-wise
1110 within the words. For example, (double) 1.1 in big endian mode is
1111 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1112 the byte sequence 99 99 f1 3f 9a 99 99 99.
1114 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1117 md_atof (int type
, char * litP
, int * sizeP
)
1120 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1152 return _("Unrecognized or unsupported floating point constant");
1155 t
= atof_ieee (input_line_pointer
, type
, words
);
1157 input_line_pointer
= t
;
1158 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1160 if (target_big_endian
)
1162 for (i
= 0; i
< prec
; i
++)
1164 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1165 litP
+= sizeof (LITTLENUM_TYPE
);
1170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1171 for (i
= prec
- 1; i
>= 0; i
--)
1173 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1174 litP
+= sizeof (LITTLENUM_TYPE
);
1177 /* For a 4 byte float the order of elements in `words' is 1 0.
1178 For an 8 byte float the order is 1 0 3 2. */
1179 for (i
= 0; i
< prec
; i
+= 2)
1181 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1182 sizeof (LITTLENUM_TYPE
));
1183 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1184 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1185 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1192 /* We handle all bad expressions here, so that we can report the faulty
1193 instruction in the error message. */
1196 md_operand (expressionS
* exp
)
1198 if (in_my_get_expression
)
1199 exp
->X_op
= O_illegal
;
1202 /* Immediate values. */
1205 /* Generic immediate-value read function for use in directives.
1206 Accepts anything that 'expression' can fold to a constant.
1207 *val receives the number. */
1210 immediate_for_directive (int *val
)
1213 exp
.X_op
= O_illegal
;
1215 if (is_immediate_prefix (*input_line_pointer
))
1217 input_line_pointer
++;
1221 if (exp
.X_op
!= O_constant
)
1223 as_bad (_("expected #constant"));
1224 ignore_rest_of_line ();
1227 *val
= exp
.X_add_number
;
1232 /* Register parsing. */
1234 /* Generic register parser. CCP points to what should be the
1235 beginning of a register name. If it is indeed a valid register
1236 name, advance CCP over it and return the reg_entry structure;
1237 otherwise return NULL. Does not issue diagnostics. */
1239 static struct reg_entry
*
1240 arm_reg_parse_multi (char **ccp
)
1244 struct reg_entry
*reg
;
1246 skip_whitespace (start
);
1248 #ifdef REGISTER_PREFIX
1249 if (*start
!= REGISTER_PREFIX
)
1253 #ifdef OPTIONAL_REGISTER_PREFIX
1254 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1259 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1264 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1266 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1276 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1277 enum arm_reg_type type
)
1279 /* Alternative syntaxes are accepted for a few register classes. */
1286 /* Generic coprocessor register names are allowed for these. */
1287 if (reg
&& reg
->type
== REG_TYPE_CN
)
1292 /* For backward compatibility, a bare number is valid here. */
1294 unsigned long processor
= strtoul (start
, ccp
, 10);
1295 if (*ccp
!= start
&& processor
<= 15)
1300 case REG_TYPE_MMXWC
:
1301 /* WC includes WCG. ??? I'm not sure this is true for all
1302 instructions that take WC registers. */
1303 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1314 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1315 return value is the register number or FAIL. */
1318 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1321 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1324 /* Do not allow a scalar (reg+index) to parse as a register. */
1325 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1328 if (reg
&& reg
->type
== type
)
1331 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1338 /* Parse a Neon type specifier. *STR should point at the leading '.'
1339 character. Does no verification at this stage that the type fits the opcode
1346 Can all be legally parsed by this function.
1348 Fills in neon_type struct pointer with parsed information, and updates STR
1349 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1350 type, FAIL if not. */
1353 parse_neon_type (struct neon_type
*type
, char **str
)
1360 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1362 enum neon_el_type thistype
= NT_untyped
;
1363 unsigned thissize
= -1u;
1370 /* Just a size without an explicit type. */
1374 switch (TOLOWER (*ptr
))
1376 case 'i': thistype
= NT_integer
; break;
1377 case 'f': thistype
= NT_float
; break;
1378 case 'p': thistype
= NT_poly
; break;
1379 case 's': thistype
= NT_signed
; break;
1380 case 'u': thistype
= NT_unsigned
; break;
1382 thistype
= NT_float
;
1387 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1393 /* .f is an abbreviation for .f32. */
1394 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1399 thissize
= strtoul (ptr
, &ptr
, 10);
1401 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1404 as_bad (_("bad size %d in type specifier"), thissize
);
1412 type
->el
[type
->elems
].type
= thistype
;
1413 type
->el
[type
->elems
].size
= thissize
;
1418 /* Empty/missing type is not a successful parse. */
1419 if (type
->elems
== 0)
1427 /* Errors may be set multiple times during parsing or bit encoding
1428 (particularly in the Neon bits), but usually the earliest error which is set
1429 will be the most meaningful. Avoid overwriting it with later (cascading)
1430 errors by calling this function. */
1433 first_error (const char *err
)
1439 /* Parse a single type, e.g. ".s32", leading period included. */
1441 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1444 struct neon_type optype
;
1448 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1450 if (optype
.elems
== 1)
1451 *vectype
= optype
.el
[0];
1454 first_error (_("only one type should be specified for operand"));
1460 first_error (_("vector type expected"));
1472 /* Special meanings for indices (which have a range of 0-7), which will fit into
1475 #define NEON_ALL_LANES 15
1476 #define NEON_INTERLEAVE_LANES 14
1478 /* Parse either a register or a scalar, with an optional type. Return the
1479 register number, and optionally fill in the actual type of the register
1480 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1481 type/index information in *TYPEINFO. */
1484 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1485 enum arm_reg_type
*rtype
,
1486 struct neon_typed_alias
*typeinfo
)
1489 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1490 struct neon_typed_alias atype
;
1491 struct neon_type_el parsetype
;
1495 atype
.eltype
.type
= NT_invtype
;
1496 atype
.eltype
.size
= -1;
1498 /* Try alternate syntax for some types of register. Note these are mutually
1499 exclusive with the Neon syntax extensions. */
1502 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1510 /* Undo polymorphism when a set of register types may be accepted. */
1511 if ((type
== REG_TYPE_NDQ
1512 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1513 || (type
== REG_TYPE_VFSD
1514 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1515 || (type
== REG_TYPE_NSDQ
1516 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1517 || reg
->type
== REG_TYPE_NQ
))
1518 || (type
== REG_TYPE_NSD
1519 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1520 || (type
== REG_TYPE_MMXWC
1521 && (reg
->type
== REG_TYPE_MMXWCG
)))
1522 type
= (enum arm_reg_type
) reg
->type
;
1524 if (type
!= reg
->type
)
1530 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1532 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1534 first_error (_("can't redefine type for operand"));
1537 atype
.defined
|= NTA_HASTYPE
;
1538 atype
.eltype
= parsetype
;
1541 if (skip_past_char (&str
, '[') == SUCCESS
)
1543 if (type
!= REG_TYPE_VFD
1544 && !(type
== REG_TYPE_VFS
1545 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1547 first_error (_("only D registers may be indexed"));
1551 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1553 first_error (_("can't change index for operand"));
1557 atype
.defined
|= NTA_HASINDEX
;
1559 if (skip_past_char (&str
, ']') == SUCCESS
)
1560 atype
.index
= NEON_ALL_LANES
;
1565 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1567 if (exp
.X_op
!= O_constant
)
1569 first_error (_("constant expression required"));
1573 if (skip_past_char (&str
, ']') == FAIL
)
1576 atype
.index
= exp
.X_add_number
;
1591 /* Like arm_reg_parse, but allow allow the following extra features:
1592 - If RTYPE is non-zero, return the (possibly restricted) type of the
1593 register (e.g. Neon double or quad reg when either has been requested).
1594 - If this is a Neon vector type with additional type information, fill
1595 in the struct pointed to by VECTYPE (if non-NULL).
1596 This function will fault on encountering a scalar. */
1599 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1600 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1602 struct neon_typed_alias atype
;
1604 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1609 /* Do not allow regname(... to parse as a register. */
1613 /* Do not allow a scalar (reg+index) to parse as a register. */
1614 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1616 first_error (_("register operand expected, but got scalar"));
1621 *vectype
= atype
.eltype
;
1628 #define NEON_SCALAR_REG(X) ((X) >> 4)
1629 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1631 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1632 have enough information to be able to do a good job bounds-checking. So, we
1633 just do easy checks here, and do further checks later. */
1636 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1640 struct neon_typed_alias atype
;
1641 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1644 reg_type
= REG_TYPE_VFS
;
1646 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1648 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1651 if (atype
.index
== NEON_ALL_LANES
)
1653 first_error (_("scalar must have an index"));
1656 else if (atype
.index
>= 64 / elsize
)
1658 first_error (_("scalar index out of range"));
1663 *type
= atype
.eltype
;
1667 return reg
* 16 + atype
.index
;
1670 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1673 parse_reg_list (char ** strp
)
1675 char * str
= * strp
;
1679 /* We come back here if we get ranges concatenated by '+' or '|'. */
1682 skip_whitespace (str
);
1696 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1698 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1708 first_error (_("bad range in register list"));
1712 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1714 if (range
& (1 << i
))
1716 (_("Warning: duplicated register (r%d) in register list"),
1724 if (range
& (1 << reg
))
1725 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1727 else if (reg
<= cur_reg
)
1728 as_tsktsk (_("Warning: register range not in ascending order"));
1733 while (skip_past_comma (&str
) != FAIL
1734 || (in_range
= 1, *str
++ == '-'));
1737 if (skip_past_char (&str
, '}') == FAIL
)
1739 first_error (_("missing `}'"));
1747 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1750 if (exp
.X_op
== O_constant
)
1752 if (exp
.X_add_number
1753 != (exp
.X_add_number
& 0x0000ffff))
1755 inst
.error
= _("invalid register mask");
1759 if ((range
& exp
.X_add_number
) != 0)
1761 int regno
= range
& exp
.X_add_number
;
1764 regno
= (1 << regno
) - 1;
1766 (_("Warning: duplicated register (r%d) in register list"),
1770 range
|= exp
.X_add_number
;
1774 if (inst
.reloc
.type
!= 0)
1776 inst
.error
= _("expression too complex");
1780 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1781 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1782 inst
.reloc
.pc_rel
= 0;
1786 if (*str
== '|' || *str
== '+')
1792 while (another_range
);
1798 /* Types of registers in a list. */
1807 /* Parse a VFP register list. If the string is invalid return FAIL.
1808 Otherwise return the number of registers, and set PBASE to the first
1809 register. Parses registers of type ETYPE.
1810 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1811 - Q registers can be used to specify pairs of D registers
1812 - { } can be omitted from around a singleton register list
1813 FIXME: This is not implemented, as it would require backtracking in
1816 This could be done (the meaning isn't really ambiguous), but doesn't
1817 fit in well with the current parsing framework.
1818 - 32 D registers may be used (also true for VFPv3).
1819 FIXME: Types are ignored in these register lists, which is probably a
1823 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1828 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1832 unsigned long mask
= 0;
1835 if (skip_past_char (&str
, '{') == FAIL
)
1837 inst
.error
= _("expecting {");
1844 regtype
= REG_TYPE_VFS
;
1849 regtype
= REG_TYPE_VFD
;
1852 case REGLIST_NEON_D
:
1853 regtype
= REG_TYPE_NDQ
;
1857 if (etype
!= REGLIST_VFP_S
)
1859 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1860 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1864 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1867 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1874 base_reg
= max_regs
;
1878 int setmask
= 1, addregs
= 1;
1880 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1882 if (new_base
== FAIL
)
1884 first_error (_(reg_expected_msgs
[regtype
]));
1888 if (new_base
>= max_regs
)
1890 first_error (_("register out of range in list"));
1894 /* Note: a value of 2 * n is returned for the register Q<n>. */
1895 if (regtype
== REG_TYPE_NQ
)
1901 if (new_base
< base_reg
)
1902 base_reg
= new_base
;
1904 if (mask
& (setmask
<< new_base
))
1906 first_error (_("invalid register list"));
1910 if ((mask
>> new_base
) != 0 && ! warned
)
1912 as_tsktsk (_("register list not in ascending order"));
1916 mask
|= setmask
<< new_base
;
1919 if (*str
== '-') /* We have the start of a range expression */
1925 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1928 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1932 if (high_range
>= max_regs
)
1934 first_error (_("register out of range in list"));
1938 if (regtype
== REG_TYPE_NQ
)
1939 high_range
= high_range
+ 1;
1941 if (high_range
<= new_base
)
1943 inst
.error
= _("register range not in ascending order");
1947 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1949 if (mask
& (setmask
<< new_base
))
1951 inst
.error
= _("invalid register list");
1955 mask
|= setmask
<< new_base
;
1960 while (skip_past_comma (&str
) != FAIL
);
1964 /* Sanity check -- should have raised a parse error above. */
1965 if (count
== 0 || count
> max_regs
)
1970 /* Final test -- the registers must be consecutive. */
1972 for (i
= 0; i
< count
; i
++)
1974 if ((mask
& (1u << i
)) == 0)
1976 inst
.error
= _("non-contiguous register range");
1986 /* True if two alias types are the same. */
1989 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1997 if (a
->defined
!= b
->defined
)
2000 if ((a
->defined
& NTA_HASTYPE
) != 0
2001 && (a
->eltype
.type
!= b
->eltype
.type
2002 || a
->eltype
.size
!= b
->eltype
.size
))
2005 if ((a
->defined
& NTA_HASINDEX
) != 0
2006 && (a
->index
!= b
->index
))
2012 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2013 The base register is put in *PBASE.
2014 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2016 The register stride (minus one) is put in bit 4 of the return value.
2017 Bits [6:5] encode the list length (minus one).
2018 The type of the list elements is put in *ELTYPE, if non-NULL. */
2020 #define NEON_LANE(X) ((X) & 0xf)
2021 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2022 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2025 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2026 struct neon_type_el
*eltype
)
2033 int leading_brace
= 0;
2034 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2035 const char *const incr_error
= _("register stride must be 1 or 2");
2036 const char *const type_error
= _("mismatched element/structure types in list");
2037 struct neon_typed_alias firsttype
;
2038 firsttype
.defined
= 0;
2039 firsttype
.eltype
.type
= NT_invtype
;
2040 firsttype
.eltype
.size
= -1;
2041 firsttype
.index
= -1;
2043 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2048 struct neon_typed_alias atype
;
2049 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2053 first_error (_(reg_expected_msgs
[rtype
]));
2060 if (rtype
== REG_TYPE_NQ
)
2066 else if (reg_incr
== -1)
2068 reg_incr
= getreg
- base_reg
;
2069 if (reg_incr
< 1 || reg_incr
> 2)
2071 first_error (_(incr_error
));
2075 else if (getreg
!= base_reg
+ reg_incr
* count
)
2077 first_error (_(incr_error
));
2081 if (! neon_alias_types_same (&atype
, &firsttype
))
2083 first_error (_(type_error
));
2087 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2091 struct neon_typed_alias htype
;
2092 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2094 lane
= NEON_INTERLEAVE_LANES
;
2095 else if (lane
!= NEON_INTERLEAVE_LANES
)
2097 first_error (_(type_error
));
2102 else if (reg_incr
!= 1)
2104 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2108 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2111 first_error (_(reg_expected_msgs
[rtype
]));
2114 if (! neon_alias_types_same (&htype
, &firsttype
))
2116 first_error (_(type_error
));
2119 count
+= hireg
+ dregs
- getreg
;
2123 /* If we're using Q registers, we can't use [] or [n] syntax. */
2124 if (rtype
== REG_TYPE_NQ
)
2130 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2134 else if (lane
!= atype
.index
)
2136 first_error (_(type_error
));
2140 else if (lane
== -1)
2141 lane
= NEON_INTERLEAVE_LANES
;
2142 else if (lane
!= NEON_INTERLEAVE_LANES
)
2144 first_error (_(type_error
));
2149 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2151 /* No lane set by [x]. We must be interleaving structures. */
2153 lane
= NEON_INTERLEAVE_LANES
;
2156 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2157 || (count
> 1 && reg_incr
== -1))
2159 first_error (_("error parsing element/structure list"));
2163 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2165 first_error (_("expected }"));
2173 *eltype
= firsttype
.eltype
;
2178 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2181 /* Parse an explicit relocation suffix on an expression. This is
2182 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2183 arm_reloc_hsh contains no entries, so this function can only
2184 succeed if there is no () after the word. Returns -1 on error,
2185 BFD_RELOC_UNUSED if there wasn't any suffix. */
2188 parse_reloc (char **str
)
2190 struct reloc_entry
*r
;
2194 return BFD_RELOC_UNUSED
;
2199 while (*q
&& *q
!= ')' && *q
!= ',')
2204 if ((r
= (struct reloc_entry
*)
2205 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2212 /* Directives: register aliases. */
2214 static struct reg_entry
*
2215 insert_reg_alias (char *str
, unsigned number
, int type
)
2217 struct reg_entry
*new_reg
;
2220 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2222 if (new_reg
->builtin
)
2223 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2225 /* Only warn about a redefinition if it's not defined as the
2227 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2228 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2233 name
= xstrdup (str
);
2234 new_reg
= XNEW (struct reg_entry
);
2236 new_reg
->name
= name
;
2237 new_reg
->number
= number
;
2238 new_reg
->type
= type
;
2239 new_reg
->builtin
= FALSE
;
2240 new_reg
->neon
= NULL
;
2242 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2249 insert_neon_reg_alias (char *str
, int number
, int type
,
2250 struct neon_typed_alias
*atype
)
2252 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2256 first_error (_("attempt to redefine typed alias"));
2262 reg
->neon
= XNEW (struct neon_typed_alias
);
2263 *reg
->neon
= *atype
;
2267 /* Look for the .req directive. This is of the form:
2269 new_register_name .req existing_register_name
2271 If we find one, or if it looks sufficiently like one that we want to
2272 handle any error here, return TRUE. Otherwise return FALSE. */
2275 create_register_alias (char * newname
, char *p
)
2277 struct reg_entry
*old
;
2278 char *oldname
, *nbuf
;
2281 /* The input scrubber ensures that whitespace after the mnemonic is
2282 collapsed to single spaces. */
2284 if (strncmp (oldname
, " .req ", 6) != 0)
2288 if (*oldname
== '\0')
2291 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2294 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2298 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2299 the desired alias name, and p points to its end. If not, then
2300 the desired alias name is in the global original_case_string. */
2301 #ifdef TC_CASE_SENSITIVE
2304 newname
= original_case_string
;
2305 nlen
= strlen (newname
);
2308 nbuf
= xmemdup0 (newname
, nlen
);
2310 /* Create aliases under the new name as stated; an all-lowercase
2311 version of the new name; and an all-uppercase version of the new
2313 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2315 for (p
= nbuf
; *p
; p
++)
2318 if (strncmp (nbuf
, newname
, nlen
))
2320 /* If this attempt to create an additional alias fails, do not bother
2321 trying to create the all-lower case alias. We will fail and issue
2322 a second, duplicate error message. This situation arises when the
2323 programmer does something like:
2326 The second .req creates the "Foo" alias but then fails to create
2327 the artificial FOO alias because it has already been created by the
2329 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2336 for (p
= nbuf
; *p
; p
++)
2339 if (strncmp (nbuf
, newname
, nlen
))
2340 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2347 /* Create a Neon typed/indexed register alias using directives, e.g.:
2352 These typed registers can be used instead of the types specified after the
2353 Neon mnemonic, so long as all operands given have types. Types can also be
2354 specified directly, e.g.:
2355 vadd d0.s32, d1.s32, d2.s32 */
2358 create_neon_reg_alias (char *newname
, char *p
)
2360 enum arm_reg_type basetype
;
2361 struct reg_entry
*basereg
;
2362 struct reg_entry mybasereg
;
2363 struct neon_type ntype
;
2364 struct neon_typed_alias typeinfo
;
2365 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2368 typeinfo
.defined
= 0;
2369 typeinfo
.eltype
.type
= NT_invtype
;
2370 typeinfo
.eltype
.size
= -1;
2371 typeinfo
.index
= -1;
2375 if (strncmp (p
, " .dn ", 5) == 0)
2376 basetype
= REG_TYPE_VFD
;
2377 else if (strncmp (p
, " .qn ", 5) == 0)
2378 basetype
= REG_TYPE_NQ
;
2387 basereg
= arm_reg_parse_multi (&p
);
2389 if (basereg
&& basereg
->type
!= basetype
)
2391 as_bad (_("bad type for register"));
2395 if (basereg
== NULL
)
2398 /* Try parsing as an integer. */
2399 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2400 if (exp
.X_op
!= O_constant
)
2402 as_bad (_("expression must be constant"));
2405 basereg
= &mybasereg
;
2406 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2412 typeinfo
= *basereg
->neon
;
2414 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2416 /* We got a type. */
2417 if (typeinfo
.defined
& NTA_HASTYPE
)
2419 as_bad (_("can't redefine the type of a register alias"));
2423 typeinfo
.defined
|= NTA_HASTYPE
;
2424 if (ntype
.elems
!= 1)
2426 as_bad (_("you must specify a single type only"));
2429 typeinfo
.eltype
= ntype
.el
[0];
2432 if (skip_past_char (&p
, '[') == SUCCESS
)
2435 /* We got a scalar index. */
2437 if (typeinfo
.defined
& NTA_HASINDEX
)
2439 as_bad (_("can't redefine the index of a scalar alias"));
2443 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2445 if (exp
.X_op
!= O_constant
)
2447 as_bad (_("scalar index must be constant"));
2451 typeinfo
.defined
|= NTA_HASINDEX
;
2452 typeinfo
.index
= exp
.X_add_number
;
2454 if (skip_past_char (&p
, ']') == FAIL
)
2456 as_bad (_("expecting ]"));
2461 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2462 the desired alias name, and p points to its end. If not, then
2463 the desired alias name is in the global original_case_string. */
2464 #ifdef TC_CASE_SENSITIVE
2465 namelen
= nameend
- newname
;
2467 newname
= original_case_string
;
2468 namelen
= strlen (newname
);
2471 namebuf
= xmemdup0 (newname
, namelen
);
2473 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2474 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2476 /* Insert name in all uppercase. */
2477 for (p
= namebuf
; *p
; p
++)
2480 if (strncmp (namebuf
, newname
, namelen
))
2481 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2482 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2484 /* Insert name in all lowercase. */
2485 for (p
= namebuf
; *p
; p
++)
2488 if (strncmp (namebuf
, newname
, namelen
))
2489 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2490 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2496 /* Should never be called, as .req goes between the alias and the
2497 register name, not at the beginning of the line. */
2500 s_req (int a ATTRIBUTE_UNUSED
)
2502 as_bad (_("invalid syntax for .req directive"));
2506 s_dn (int a ATTRIBUTE_UNUSED
)
2508 as_bad (_("invalid syntax for .dn directive"));
2512 s_qn (int a ATTRIBUTE_UNUSED
)
2514 as_bad (_("invalid syntax for .qn directive"));
2517 /* The .unreq directive deletes an alias which was previously defined
2518 by .req. For example:
2524 s_unreq (int a ATTRIBUTE_UNUSED
)
2529 name
= input_line_pointer
;
2531 while (*input_line_pointer
!= 0
2532 && *input_line_pointer
!= ' '
2533 && *input_line_pointer
!= '\n')
2534 ++input_line_pointer
;
2536 saved_char
= *input_line_pointer
;
2537 *input_line_pointer
= 0;
2540 as_bad (_("invalid syntax for .unreq directive"));
2543 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2547 as_bad (_("unknown register alias '%s'"), name
);
2548 else if (reg
->builtin
)
2549 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2556 hash_delete (arm_reg_hsh
, name
, FALSE
);
2557 free ((char *) reg
->name
);
2562 /* Also locate the all upper case and all lower case versions.
2563 Do not complain if we cannot find one or the other as it
2564 was probably deleted above. */
2566 nbuf
= strdup (name
);
2567 for (p
= nbuf
; *p
; p
++)
2569 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2572 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2573 free ((char *) reg
->name
);
2579 for (p
= nbuf
; *p
; p
++)
2581 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2584 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2585 free ((char *) reg
->name
);
2595 *input_line_pointer
= saved_char
;
2596 demand_empty_rest_of_line ();
2599 /* Directives: Instruction set selection. */
2602 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2603 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2604 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2605 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2607 /* Create a new mapping symbol for the transition to STATE. */
2610 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2613 const char * symname
;
2620 type
= BSF_NO_FLAGS
;
2624 type
= BSF_NO_FLAGS
;
2628 type
= BSF_NO_FLAGS
;
2634 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2635 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2640 THUMB_SET_FUNC (symbolP
, 0);
2641 ARM_SET_THUMB (symbolP
, 0);
2642 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2646 THUMB_SET_FUNC (symbolP
, 1);
2647 ARM_SET_THUMB (symbolP
, 1);
2648 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2656 /* Save the mapping symbols for future reference. Also check that
2657 we do not place two mapping symbols at the same offset within a
2658 frag. We'll handle overlap between frags in
2659 check_mapping_symbols.
2661 If .fill or other data filling directive generates zero sized data,
2662 the mapping symbol for the following code will have the same value
2663 as the one generated for the data filling directive. In this case,
2664 we replace the old symbol with the new one at the same address. */
2667 if (frag
->tc_frag_data
.first_map
!= NULL
)
2669 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2670 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2672 frag
->tc_frag_data
.first_map
= symbolP
;
2674 if (frag
->tc_frag_data
.last_map
!= NULL
)
2676 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2677 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2678 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2680 frag
->tc_frag_data
.last_map
= symbolP
;
2683 /* We must sometimes convert a region marked as code to data during
2684 code alignment, if an odd number of bytes have to be padded. The
2685 code mapping symbol is pushed to an aligned address. */
2688 insert_data_mapping_symbol (enum mstate state
,
2689 valueT value
, fragS
*frag
, offsetT bytes
)
2691 /* If there was already a mapping symbol, remove it. */
2692 if (frag
->tc_frag_data
.last_map
!= NULL
2693 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2695 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2699 know (frag
->tc_frag_data
.first_map
== symp
);
2700 frag
->tc_frag_data
.first_map
= NULL
;
2702 frag
->tc_frag_data
.last_map
= NULL
;
2703 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2706 make_mapping_symbol (MAP_DATA
, value
, frag
);
2707 make_mapping_symbol (state
, value
+ bytes
, frag
);
2710 static void mapping_state_2 (enum mstate state
, int max_chars
);
2712 /* Set the mapping state to STATE. Only call this when about to
2713 emit some STATE bytes to the file. */
2715 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2717 mapping_state (enum mstate state
)
2719 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2721 if (mapstate
== state
)
2722 /* The mapping symbol has already been emitted.
2723 There is nothing else to do. */
2726 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2728 All ARM instructions require 4-byte alignment.
2729 (Almost) all Thumb instructions require 2-byte alignment.
2731 When emitting instructions into any section, mark the section
2734 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2735 but themselves require 2-byte alignment; this applies to some
2736 PC- relative forms. However, these cases will involve implicit
2737 literal pool generation or an explicit .align >=2, both of
2738 which will cause the section to me marked with sufficient
2739 alignment. Thus, we don't handle those cases here. */
2740 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2742 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2743 /* This case will be evaluated later. */
2746 mapping_state_2 (state
, 0);
2749 /* Same as mapping_state, but MAX_CHARS bytes have already been
2750 allocated. Put the mapping symbol that far back. */
2753 mapping_state_2 (enum mstate state
, int max_chars
)
2755 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2757 if (!SEG_NORMAL (now_seg
))
2760 if (mapstate
== state
)
2761 /* The mapping symbol has already been emitted.
2762 There is nothing else to do. */
2765 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2766 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2768 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2769 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2772 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2775 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2776 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2780 #define mapping_state(x) ((void)0)
2781 #define mapping_state_2(x, y) ((void)0)
2784 /* Find the real, Thumb encoded start of a Thumb function. */
2788 find_real_start (symbolS
* symbolP
)
2791 const char * name
= S_GET_NAME (symbolP
);
2792 symbolS
* new_target
;
2794 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2795 #define STUB_NAME ".real_start_of"
2800 /* The compiler may generate BL instructions to local labels because
2801 it needs to perform a branch to a far away location. These labels
2802 do not have a corresponding ".real_start_of" label. We check
2803 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2804 the ".real_start_of" convention for nonlocal branches. */
2805 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2808 real_start
= concat (STUB_NAME
, name
, NULL
);
2809 new_target
= symbol_find (real_start
);
2812 if (new_target
== NULL
)
2814 as_warn (_("Failed to find real start of function: %s\n"), name
);
2815 new_target
= symbolP
;
2823 opcode_select (int width
)
2830 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2831 as_bad (_("selected processor does not support THUMB opcodes"));
2834 /* No need to force the alignment, since we will have been
2835 coming from ARM mode, which is word-aligned. */
2836 record_alignment (now_seg
, 1);
2843 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2844 as_bad (_("selected processor does not support ARM opcodes"));
2849 frag_align (2, 0, 0);
2851 record_alignment (now_seg
, 1);
2856 as_bad (_("invalid instruction size selected (%d)"), width
);
2861 s_arm (int ignore ATTRIBUTE_UNUSED
)
2864 demand_empty_rest_of_line ();
2868 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2871 demand_empty_rest_of_line ();
2875 s_code (int unused ATTRIBUTE_UNUSED
)
2879 temp
= get_absolute_expression ();
2884 opcode_select (temp
);
2888 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2893 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2895 /* If we are not already in thumb mode go into it, EVEN if
2896 the target processor does not support thumb instructions.
2897 This is used by gcc/config/arm/lib1funcs.asm for example
2898 to compile interworking support functions even if the
2899 target processor should not support interworking. */
2903 record_alignment (now_seg
, 1);
2906 demand_empty_rest_of_line ();
2910 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2914 /* The following label is the name/address of the start of a Thumb function.
2915 We need to know this for the interworking support. */
2916 label_is_thumb_function_name
= TRUE
;
2919 /* Perform a .set directive, but also mark the alias as
2920 being a thumb function. */
2923 s_thumb_set (int equiv
)
2925 /* XXX the following is a duplicate of the code for s_set() in read.c
2926 We cannot just call that code as we need to get at the symbol that
2933 /* Especial apologies for the random logic:
2934 This just grew, and could be parsed much more simply!
2936 delim
= get_symbol_name (& name
);
2937 end_name
= input_line_pointer
;
2938 (void) restore_line_pointer (delim
);
2940 if (*input_line_pointer
!= ',')
2943 as_bad (_("expected comma after name \"%s\""), name
);
2945 ignore_rest_of_line ();
2949 input_line_pointer
++;
2952 if (name
[0] == '.' && name
[1] == '\0')
2954 /* XXX - this should not happen to .thumb_set. */
2958 if ((symbolP
= symbol_find (name
)) == NULL
2959 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2962 /* When doing symbol listings, play games with dummy fragments living
2963 outside the normal fragment chain to record the file and line info
2965 if (listing
& LISTING_SYMBOLS
)
2967 extern struct list_info_struct
* listing_tail
;
2968 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2970 memset (dummy_frag
, 0, sizeof (fragS
));
2971 dummy_frag
->fr_type
= rs_fill
;
2972 dummy_frag
->line
= listing_tail
;
2973 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2974 dummy_frag
->fr_symbol
= symbolP
;
2978 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2981 /* "set" symbols are local unless otherwise specified. */
2982 SF_SET_LOCAL (symbolP
);
2983 #endif /* OBJ_COFF */
2984 } /* Make a new symbol. */
2986 symbol_table_insert (symbolP
);
2991 && S_IS_DEFINED (symbolP
)
2992 && S_GET_SEGMENT (symbolP
) != reg_section
)
2993 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2995 pseudo_set (symbolP
);
2997 demand_empty_rest_of_line ();
2999 /* XXX Now we come to the Thumb specific bit of code. */
3001 THUMB_SET_FUNC (symbolP
, 1);
3002 ARM_SET_THUMB (symbolP
, 1);
3003 #if defined OBJ_ELF || defined OBJ_COFF
3004 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3008 /* Directives: Mode selection. */
3010 /* .syntax [unified|divided] - choose the new unified syntax
3011 (same for Arm and Thumb encoding, modulo slight differences in what
3012 can be represented) or the old divergent syntax for each mode. */
3014 s_syntax (int unused ATTRIBUTE_UNUSED
)
3018 delim
= get_symbol_name (& name
);
3020 if (!strcasecmp (name
, "unified"))
3021 unified_syntax
= TRUE
;
3022 else if (!strcasecmp (name
, "divided"))
3023 unified_syntax
= FALSE
;
3026 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3029 (void) restore_line_pointer (delim
);
3030 demand_empty_rest_of_line ();
3033 /* Directives: sectioning and alignment. */
3036 s_bss (int ignore ATTRIBUTE_UNUSED
)
3038 /* We don't support putting frags in the BSS segment, we fake it by
3039 marking in_bss, then looking at s_skip for clues. */
3040 subseg_set (bss_section
, 0);
3041 demand_empty_rest_of_line ();
3043 #ifdef md_elf_section_change_hook
3044 md_elf_section_change_hook ();
3049 s_even (int ignore ATTRIBUTE_UNUSED
)
3051 /* Never make frag if expect extra pass. */
3053 frag_align (1, 0, 0);
3055 record_alignment (now_seg
, 1);
3057 demand_empty_rest_of_line ();
3060 /* Directives: CodeComposer Studio. */
3062 /* .ref (for CodeComposer Studio syntax only). */
3064 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3066 if (codecomposer_syntax
)
3067 ignore_rest_of_line ();
3069 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3072 /* If name is not NULL, then it is used for marking the beginning of a
3073 function, whereas if it is NULL then it means the function end. */
3075 asmfunc_debug (const char * name
)
3077 static const char * last_name
= NULL
;
3081 gas_assert (last_name
== NULL
);
3084 if (debug_type
== DEBUG_STABS
)
3085 stabs_generate_asm_func (name
, name
);
3089 gas_assert (last_name
!= NULL
);
3091 if (debug_type
== DEBUG_STABS
)
3092 stabs_generate_asm_endfunc (last_name
, last_name
);
3099 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3101 if (codecomposer_syntax
)
3103 switch (asmfunc_state
)
3105 case OUTSIDE_ASMFUNC
:
3106 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3109 case WAITING_ASMFUNC_NAME
:
3110 as_bad (_(".asmfunc repeated."));
3113 case WAITING_ENDASMFUNC
:
3114 as_bad (_(".asmfunc without function."));
3117 demand_empty_rest_of_line ();
3120 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3124 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3126 if (codecomposer_syntax
)
3128 switch (asmfunc_state
)
3130 case OUTSIDE_ASMFUNC
:
3131 as_bad (_(".endasmfunc without a .asmfunc."));
3134 case WAITING_ASMFUNC_NAME
:
3135 as_bad (_(".endasmfunc without function."));
3138 case WAITING_ENDASMFUNC
:
3139 asmfunc_state
= OUTSIDE_ASMFUNC
;
3140 asmfunc_debug (NULL
);
3143 demand_empty_rest_of_line ();
3146 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3150 s_ccs_def (int name
)
3152 if (codecomposer_syntax
)
3155 as_bad (_(".def pseudo-op only available with -mccs flag."));
3158 /* Directives: Literal pools. */
3160 static literal_pool
*
3161 find_literal_pool (void)
3163 literal_pool
* pool
;
3165 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3167 if (pool
->section
== now_seg
3168 && pool
->sub_section
== now_subseg
)
3175 static literal_pool
*
3176 find_or_make_literal_pool (void)
3178 /* Next literal pool ID number. */
3179 static unsigned int latest_pool_num
= 1;
3180 literal_pool
* pool
;
3182 pool
= find_literal_pool ();
3186 /* Create a new pool. */
3187 pool
= XNEW (literal_pool
);
3191 pool
->next_free_entry
= 0;
3192 pool
->section
= now_seg
;
3193 pool
->sub_section
= now_subseg
;
3194 pool
->next
= list_of_pools
;
3195 pool
->symbol
= NULL
;
3196 pool
->alignment
= 2;
3198 /* Add it to the list. */
3199 list_of_pools
= pool
;
3202 /* New pools, and emptied pools, will have a NULL symbol. */
3203 if (pool
->symbol
== NULL
)
3205 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3206 (valueT
) 0, &zero_address_frag
);
3207 pool
->id
= latest_pool_num
++;
3214 /* Add the literal in the global 'inst'
3215 structure to the relevant literal pool. */
3218 add_to_lit_pool (unsigned int nbytes
)
3220 #define PADDING_SLOT 0x1
3221 #define LIT_ENTRY_SIZE_MASK 0xFF
3222 literal_pool
* pool
;
3223 unsigned int entry
, pool_size
= 0;
3224 bfd_boolean padding_slot_p
= FALSE
;
3230 imm1
= inst
.operands
[1].imm
;
3231 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3232 : inst
.reloc
.exp
.X_unsigned
? 0
3233 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3234 if (target_big_endian
)
3237 imm2
= inst
.operands
[1].imm
;
3241 pool
= find_or_make_literal_pool ();
3243 /* Check if this literal value is already in the pool. */
3244 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3248 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3249 && (inst
.reloc
.exp
.X_op
== O_constant
)
3250 && (pool
->literals
[entry
].X_add_number
3251 == inst
.reloc
.exp
.X_add_number
)
3252 && (pool
->literals
[entry
].X_md
== nbytes
)
3253 && (pool
->literals
[entry
].X_unsigned
3254 == inst
.reloc
.exp
.X_unsigned
))
3257 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3258 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3259 && (pool
->literals
[entry
].X_add_number
3260 == inst
.reloc
.exp
.X_add_number
)
3261 && (pool
->literals
[entry
].X_add_symbol
3262 == inst
.reloc
.exp
.X_add_symbol
)
3263 && (pool
->literals
[entry
].X_op_symbol
3264 == inst
.reloc
.exp
.X_op_symbol
)
3265 && (pool
->literals
[entry
].X_md
== nbytes
))
3268 else if ((nbytes
== 8)
3269 && !(pool_size
& 0x7)
3270 && ((entry
+ 1) != pool
->next_free_entry
)
3271 && (pool
->literals
[entry
].X_op
== O_constant
)
3272 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3273 && (pool
->literals
[entry
].X_unsigned
3274 == inst
.reloc
.exp
.X_unsigned
)
3275 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3276 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3277 && (pool
->literals
[entry
+ 1].X_unsigned
3278 == inst
.reloc
.exp
.X_unsigned
))
3281 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3282 if (padding_slot_p
&& (nbytes
== 4))
3288 /* Do we need to create a new entry? */
3289 if (entry
== pool
->next_free_entry
)
3291 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3293 inst
.error
= _("literal pool overflow");
3299 /* For 8-byte entries, we align to an 8-byte boundary,
3300 and split it into two 4-byte entries, because on 32-bit
3301 host, 8-byte constants are treated as big num, thus
3302 saved in "generic_bignum" which will be overwritten
3303 by later assignments.
3305 We also need to make sure there is enough space for
3308 We also check to make sure the literal operand is a
3310 if (!(inst
.reloc
.exp
.X_op
== O_constant
3311 || inst
.reloc
.exp
.X_op
== O_big
))
3313 inst
.error
= _("invalid type for literal pool");
3316 else if (pool_size
& 0x7)
3318 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3320 inst
.error
= _("literal pool overflow");
3324 pool
->literals
[entry
] = inst
.reloc
.exp
;
3325 pool
->literals
[entry
].X_op
= O_constant
;
3326 pool
->literals
[entry
].X_add_number
= 0;
3327 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3328 pool
->next_free_entry
+= 1;
3331 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3333 inst
.error
= _("literal pool overflow");
3337 pool
->literals
[entry
] = inst
.reloc
.exp
;
3338 pool
->literals
[entry
].X_op
= O_constant
;
3339 pool
->literals
[entry
].X_add_number
= imm1
;
3340 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3341 pool
->literals
[entry
++].X_md
= 4;
3342 pool
->literals
[entry
] = inst
.reloc
.exp
;
3343 pool
->literals
[entry
].X_op
= O_constant
;
3344 pool
->literals
[entry
].X_add_number
= imm2
;
3345 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3346 pool
->literals
[entry
].X_md
= 4;
3347 pool
->alignment
= 3;
3348 pool
->next_free_entry
+= 1;
3352 pool
->literals
[entry
] = inst
.reloc
.exp
;
3353 pool
->literals
[entry
].X_md
= 4;
3357 /* PR ld/12974: Record the location of the first source line to reference
3358 this entry in the literal pool. If it turns out during linking that the
3359 symbol does not exist we will be able to give an accurate line number for
3360 the (first use of the) missing reference. */
3361 if (debug_type
== DEBUG_DWARF2
)
3362 dwarf2_where (pool
->locs
+ entry
);
3364 pool
->next_free_entry
+= 1;
3366 else if (padding_slot_p
)
3368 pool
->literals
[entry
] = inst
.reloc
.exp
;
3369 pool
->literals
[entry
].X_md
= nbytes
;
3372 inst
.reloc
.exp
.X_op
= O_symbol
;
3373 inst
.reloc
.exp
.X_add_number
= pool_size
;
3374 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3380 tc_start_label_without_colon (void)
3382 bfd_boolean ret
= TRUE
;
3384 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3386 const char *label
= input_line_pointer
;
3388 while (!is_end_of_line
[(int) label
[-1]])
3393 as_bad (_("Invalid label '%s'"), label
);
3397 asmfunc_debug (label
);
3399 asmfunc_state
= WAITING_ENDASMFUNC
;
3405 /* Can't use symbol_new here, so have to create a symbol and then at
3406 a later date assign it a value. That's what these functions do. */
3409 symbol_locate (symbolS
* symbolP
,
3410 const char * name
, /* It is copied, the caller can modify. */
3411 segT segment
, /* Segment identifier (SEG_<something>). */
3412 valueT valu
, /* Symbol value. */
3413 fragS
* frag
) /* Associated fragment. */
3416 char * preserved_copy_of_name
;
3418 name_length
= strlen (name
) + 1; /* +1 for \0. */
3419 obstack_grow (¬es
, name
, name_length
);
3420 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3422 #ifdef tc_canonicalize_symbol_name
3423 preserved_copy_of_name
=
3424 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3427 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3429 S_SET_SEGMENT (symbolP
, segment
);
3430 S_SET_VALUE (symbolP
, valu
);
3431 symbol_clear_list_pointers (symbolP
);
3433 symbol_set_frag (symbolP
, frag
);
3435 /* Link to end of symbol chain. */
3437 extern int symbol_table_frozen
;
3439 if (symbol_table_frozen
)
3443 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3445 obj_symbol_new_hook (symbolP
);
3447 #ifdef tc_symbol_new_hook
3448 tc_symbol_new_hook (symbolP
);
3452 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3453 #endif /* DEBUG_SYMS */
3457 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3460 literal_pool
* pool
;
3463 pool
= find_literal_pool ();
3465 || pool
->symbol
== NULL
3466 || pool
->next_free_entry
== 0)
3469 /* Align pool as you have word accesses.
3470 Only make a frag if we have to. */
3472 frag_align (pool
->alignment
, 0, 0);
3474 record_alignment (now_seg
, 2);
3477 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3478 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3480 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3482 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3483 (valueT
) frag_now_fix (), frag_now
);
3484 symbol_table_insert (pool
->symbol
);
3486 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3488 #if defined OBJ_COFF || defined OBJ_ELF
3489 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3492 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3495 if (debug_type
== DEBUG_DWARF2
)
3496 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3498 /* First output the expression in the instruction to the pool. */
3499 emit_expr (&(pool
->literals
[entry
]),
3500 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3503 /* Mark the pool as empty. */
3504 pool
->next_free_entry
= 0;
3505 pool
->symbol
= NULL
;
3509 /* Forward declarations for functions below, in the MD interface
3511 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3512 static valueT
create_unwind_entry (int);
3513 static void start_unwind_section (const segT
, int);
3514 static void add_unwind_opcode (valueT
, int);
3515 static void flush_pending_unwind (void);
3517 /* Directives: Data. */
3520 s_arm_elf_cons (int nbytes
)
3524 #ifdef md_flush_pending_output
3525 md_flush_pending_output ();
3528 if (is_it_end_of_statement ())
3530 demand_empty_rest_of_line ();
3534 #ifdef md_cons_align
3535 md_cons_align (nbytes
);
3538 mapping_state (MAP_DATA
);
3542 char *base
= input_line_pointer
;
3546 if (exp
.X_op
!= O_symbol
)
3547 emit_expr (&exp
, (unsigned int) nbytes
);
3550 char *before_reloc
= input_line_pointer
;
3551 reloc
= parse_reloc (&input_line_pointer
);
3554 as_bad (_("unrecognized relocation suffix"));
3555 ignore_rest_of_line ();
3558 else if (reloc
== BFD_RELOC_UNUSED
)
3559 emit_expr (&exp
, (unsigned int) nbytes
);
3562 reloc_howto_type
*howto
= (reloc_howto_type
*)
3563 bfd_reloc_type_lookup (stdoutput
,
3564 (bfd_reloc_code_real_type
) reloc
);
3565 int size
= bfd_get_reloc_size (howto
);
3567 if (reloc
== BFD_RELOC_ARM_PLT32
)
3569 as_bad (_("(plt) is only valid on branch targets"));
3570 reloc
= BFD_RELOC_UNUSED
;
3575 as_bad (ngettext ("%s relocations do not fit in %d byte",
3576 "%s relocations do not fit in %d bytes",
3578 howto
->name
, nbytes
);
3581 /* We've parsed an expression stopping at O_symbol.
3582 But there may be more expression left now that we
3583 have parsed the relocation marker. Parse it again.
3584 XXX Surely there is a cleaner way to do this. */
3585 char *p
= input_line_pointer
;
3587 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3589 memcpy (save_buf
, base
, input_line_pointer
- base
);
3590 memmove (base
+ (input_line_pointer
- before_reloc
),
3591 base
, before_reloc
- base
);
3593 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3595 memcpy (base
, save_buf
, p
- base
);
3597 offset
= nbytes
- size
;
3598 p
= frag_more (nbytes
);
3599 memset (p
, 0, nbytes
);
3600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3601 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3607 while (*input_line_pointer
++ == ',');
3609 /* Put terminator back into stream. */
3610 input_line_pointer
--;
3611 demand_empty_rest_of_line ();
3614 /* Emit an expression containing a 32-bit thumb instruction.
3615 Implementation based on put_thumb32_insn. */
3618 emit_thumb32_expr (expressionS
* exp
)
3620 expressionS exp_high
= *exp
;
3622 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3623 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3624 exp
->X_add_number
&= 0xffff;
3625 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3628 /* Guess the instruction size based on the opcode. */
3631 thumb_insn_size (int opcode
)
3633 if ((unsigned int) opcode
< 0xe800u
)
3635 else if ((unsigned int) opcode
>= 0xe8000000u
)
3642 emit_insn (expressionS
*exp
, int nbytes
)
3646 if (exp
->X_op
== O_constant
)
3651 size
= thumb_insn_size (exp
->X_add_number
);
3655 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3657 as_bad (_(".inst.n operand too big. "\
3658 "Use .inst.w instead"));
3663 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3664 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3666 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3668 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3669 emit_thumb32_expr (exp
);
3671 emit_expr (exp
, (unsigned int) size
);
3673 it_fsm_post_encode ();
3677 as_bad (_("cannot determine Thumb instruction size. " \
3678 "Use .inst.n/.inst.w instead"));
3681 as_bad (_("constant expression required"));
3686 /* Like s_arm_elf_cons but do not use md_cons_align and
3687 set the mapping state to MAP_ARM/MAP_THUMB. */
3690 s_arm_elf_inst (int nbytes
)
3692 if (is_it_end_of_statement ())
3694 demand_empty_rest_of_line ();
3698 /* Calling mapping_state () here will not change ARM/THUMB,
3699 but will ensure not to be in DATA state. */
3702 mapping_state (MAP_THUMB
);
3707 as_bad (_("width suffixes are invalid in ARM mode"));
3708 ignore_rest_of_line ();
3714 mapping_state (MAP_ARM
);
3723 if (! emit_insn (& exp
, nbytes
))
3725 ignore_rest_of_line ();
3729 while (*input_line_pointer
++ == ',');
3731 /* Put terminator back into stream. */
3732 input_line_pointer
--;
3733 demand_empty_rest_of_line ();
3736 /* Parse a .rel31 directive. */
3739 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3746 if (*input_line_pointer
== '1')
3747 highbit
= 0x80000000;
3748 else if (*input_line_pointer
!= '0')
3749 as_bad (_("expected 0 or 1"));
3751 input_line_pointer
++;
3752 if (*input_line_pointer
!= ',')
3753 as_bad (_("missing comma"));
3754 input_line_pointer
++;
3756 #ifdef md_flush_pending_output
3757 md_flush_pending_output ();
3760 #ifdef md_cons_align
3764 mapping_state (MAP_DATA
);
3769 md_number_to_chars (p
, highbit
, 4);
3770 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3771 BFD_RELOC_ARM_PREL31
);
3773 demand_empty_rest_of_line ();
3776 /* Directives: AEABI stack-unwind tables. */
3778 /* Parse an unwind_fnstart directive. Simply records the current location. */
3781 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3783 demand_empty_rest_of_line ();
3784 if (unwind
.proc_start
)
3786 as_bad (_("duplicate .fnstart directive"));
3790 /* Mark the start of the function. */
3791 unwind
.proc_start
= expr_build_dot ();
3793 /* Reset the rest of the unwind info. */
3794 unwind
.opcode_count
= 0;
3795 unwind
.table_entry
= NULL
;
3796 unwind
.personality_routine
= NULL
;
3797 unwind
.personality_index
= -1;
3798 unwind
.frame_size
= 0;
3799 unwind
.fp_offset
= 0;
3800 unwind
.fp_reg
= REG_SP
;
3802 unwind
.sp_restored
= 0;
3806 /* Parse a handlerdata directive. Creates the exception handling table entry
3807 for the function. */
3810 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3812 demand_empty_rest_of_line ();
3813 if (!unwind
.proc_start
)
3814 as_bad (MISSING_FNSTART
);
3816 if (unwind
.table_entry
)
3817 as_bad (_("duplicate .handlerdata directive"));
3819 create_unwind_entry (1);
3822 /* Parse an unwind_fnend directive. Generates the index table entry. */
3825 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3830 unsigned int marked_pr_dependency
;
3832 demand_empty_rest_of_line ();
3834 if (!unwind
.proc_start
)
3836 as_bad (_(".fnend directive without .fnstart"));
3840 /* Add eh table entry. */
3841 if (unwind
.table_entry
== NULL
)
3842 val
= create_unwind_entry (0);
3846 /* Add index table entry. This is two words. */
3847 start_unwind_section (unwind
.saved_seg
, 1);
3848 frag_align (2, 0, 0);
3849 record_alignment (now_seg
, 2);
3851 ptr
= frag_more (8);
3853 where
= frag_now_fix () - 8;
3855 /* Self relative offset of the function start. */
3856 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3857 BFD_RELOC_ARM_PREL31
);
3859 /* Indicate dependency on EHABI-defined personality routines to the
3860 linker, if it hasn't been done already. */
3861 marked_pr_dependency
3862 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3863 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3864 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3866 static const char *const name
[] =
3868 "__aeabi_unwind_cpp_pr0",
3869 "__aeabi_unwind_cpp_pr1",
3870 "__aeabi_unwind_cpp_pr2"
3872 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3873 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3874 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3875 |= 1 << unwind
.personality_index
;
3879 /* Inline exception table entry. */
3880 md_number_to_chars (ptr
+ 4, val
, 4);
3882 /* Self relative offset of the table entry. */
3883 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3884 BFD_RELOC_ARM_PREL31
);
3886 /* Restore the original section. */
3887 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3889 unwind
.proc_start
= NULL
;
3893 /* Parse an unwind_cantunwind directive. */
3896 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3898 demand_empty_rest_of_line ();
3899 if (!unwind
.proc_start
)
3900 as_bad (MISSING_FNSTART
);
3902 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3903 as_bad (_("personality routine specified for cantunwind frame"));
3905 unwind
.personality_index
= -2;
3909 /* Parse a personalityindex directive. */
3912 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3916 if (!unwind
.proc_start
)
3917 as_bad (MISSING_FNSTART
);
3919 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3920 as_bad (_("duplicate .personalityindex directive"));
3924 if (exp
.X_op
!= O_constant
3925 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3927 as_bad (_("bad personality routine number"));
3928 ignore_rest_of_line ();
3932 unwind
.personality_index
= exp
.X_add_number
;
3934 demand_empty_rest_of_line ();
3938 /* Parse a personality directive. */
3941 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3945 if (!unwind
.proc_start
)
3946 as_bad (MISSING_FNSTART
);
3948 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3949 as_bad (_("duplicate .personality directive"));
3951 c
= get_symbol_name (& name
);
3952 p
= input_line_pointer
;
3954 ++ input_line_pointer
;
3955 unwind
.personality_routine
= symbol_find_or_make (name
);
3957 demand_empty_rest_of_line ();
3961 /* Parse a directive saving core registers. */
3964 s_arm_unwind_save_core (void)
3970 range
= parse_reg_list (&input_line_pointer
);
3973 as_bad (_("expected register list"));
3974 ignore_rest_of_line ();
3978 demand_empty_rest_of_line ();
3980 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3981 into .unwind_save {..., sp...}. We aren't bothered about the value of
3982 ip because it is clobbered by calls. */
3983 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3984 && (range
& 0x3000) == 0x1000)
3986 unwind
.opcode_count
--;
3987 unwind
.sp_restored
= 0;
3988 range
= (range
| 0x2000) & ~0x1000;
3989 unwind
.pending_offset
= 0;
3995 /* See if we can use the short opcodes. These pop a block of up to 8
3996 registers starting with r4, plus maybe r14. */
3997 for (n
= 0; n
< 8; n
++)
3999 /* Break at the first non-saved register. */
4000 if ((range
& (1 << (n
+ 4))) == 0)
4003 /* See if there are any other bits set. */
4004 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4006 /* Use the long form. */
4007 op
= 0x8000 | ((range
>> 4) & 0xfff);
4008 add_unwind_opcode (op
, 2);
4012 /* Use the short form. */
4014 op
= 0xa8; /* Pop r14. */
4016 op
= 0xa0; /* Do not pop r14. */
4018 add_unwind_opcode (op
, 1);
4025 op
= 0xb100 | (range
& 0xf);
4026 add_unwind_opcode (op
, 2);
4029 /* Record the number of bytes pushed. */
4030 for (n
= 0; n
< 16; n
++)
4032 if (range
& (1 << n
))
4033 unwind
.frame_size
+= 4;
4038 /* Parse a directive saving FPA registers. */
4041 s_arm_unwind_save_fpa (int reg
)
4047 /* Get Number of registers to transfer. */
4048 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4051 exp
.X_op
= O_illegal
;
4053 if (exp
.X_op
!= O_constant
)
4055 as_bad (_("expected , <constant>"));
4056 ignore_rest_of_line ();
4060 num_regs
= exp
.X_add_number
;
4062 if (num_regs
< 1 || num_regs
> 4)
4064 as_bad (_("number of registers must be in the range [1:4]"));
4065 ignore_rest_of_line ();
4069 demand_empty_rest_of_line ();
4074 op
= 0xb4 | (num_regs
- 1);
4075 add_unwind_opcode (op
, 1);
4080 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4081 add_unwind_opcode (op
, 2);
4083 unwind
.frame_size
+= num_regs
* 12;
4087 /* Parse a directive saving VFP registers for ARMv6 and above. */
4090 s_arm_unwind_save_vfp_armv6 (void)
4095 int num_vfpv3_regs
= 0;
4096 int num_regs_below_16
;
4098 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4101 as_bad (_("expected register list"));
4102 ignore_rest_of_line ();
4106 demand_empty_rest_of_line ();
4108 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4109 than FSTMX/FLDMX-style ones). */
4111 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4113 num_vfpv3_regs
= count
;
4114 else if (start
+ count
> 16)
4115 num_vfpv3_regs
= start
+ count
- 16;
4117 if (num_vfpv3_regs
> 0)
4119 int start_offset
= start
> 16 ? start
- 16 : 0;
4120 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4121 add_unwind_opcode (op
, 2);
4124 /* Generate opcode for registers numbered in the range 0 .. 15. */
4125 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4126 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4127 if (num_regs_below_16
> 0)
4129 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4130 add_unwind_opcode (op
, 2);
4133 unwind
.frame_size
+= count
* 8;
4137 /* Parse a directive saving VFP registers for pre-ARMv6. */
4140 s_arm_unwind_save_vfp (void)
4146 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4149 as_bad (_("expected register list"));
4150 ignore_rest_of_line ();
4154 demand_empty_rest_of_line ();
4159 op
= 0xb8 | (count
- 1);
4160 add_unwind_opcode (op
, 1);
4165 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4166 add_unwind_opcode (op
, 2);
4168 unwind
.frame_size
+= count
* 8 + 4;
4172 /* Parse a directive saving iWMMXt data registers. */
4175 s_arm_unwind_save_mmxwr (void)
4183 if (*input_line_pointer
== '{')
4184 input_line_pointer
++;
4188 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4192 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4197 as_tsktsk (_("register list not in ascending order"));
4200 if (*input_line_pointer
== '-')
4202 input_line_pointer
++;
4203 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4206 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4209 else if (reg
>= hi_reg
)
4211 as_bad (_("bad register range"));
4214 for (; reg
< hi_reg
; reg
++)
4218 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4220 skip_past_char (&input_line_pointer
, '}');
4222 demand_empty_rest_of_line ();
4224 /* Generate any deferred opcodes because we're going to be looking at
4226 flush_pending_unwind ();
4228 for (i
= 0; i
< 16; i
++)
4230 if (mask
& (1 << i
))
4231 unwind
.frame_size
+= 8;
4234 /* Attempt to combine with a previous opcode. We do this because gcc
4235 likes to output separate unwind directives for a single block of
4237 if (unwind
.opcode_count
> 0)
4239 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4240 if ((i
& 0xf8) == 0xc0)
4243 /* Only merge if the blocks are contiguous. */
4246 if ((mask
& 0xfe00) == (1 << 9))
4248 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4249 unwind
.opcode_count
--;
4252 else if (i
== 6 && unwind
.opcode_count
>= 2)
4254 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4258 op
= 0xffff << (reg
- 1);
4260 && ((mask
& op
) == (1u << (reg
- 1))))
4262 op
= (1 << (reg
+ i
+ 1)) - 1;
4263 op
&= ~((1 << reg
) - 1);
4265 unwind
.opcode_count
-= 2;
4272 /* We want to generate opcodes in the order the registers have been
4273 saved, ie. descending order. */
4274 for (reg
= 15; reg
>= -1; reg
--)
4276 /* Save registers in blocks. */
4278 || !(mask
& (1 << reg
)))
4280 /* We found an unsaved reg. Generate opcodes to save the
4287 op
= 0xc0 | (hi_reg
- 10);
4288 add_unwind_opcode (op
, 1);
4293 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4294 add_unwind_opcode (op
, 2);
4303 ignore_rest_of_line ();
4307 s_arm_unwind_save_mmxwcg (void)
4314 if (*input_line_pointer
== '{')
4315 input_line_pointer
++;
4317 skip_whitespace (input_line_pointer
);
4321 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4325 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4331 as_tsktsk (_("register list not in ascending order"));
4334 if (*input_line_pointer
== '-')
4336 input_line_pointer
++;
4337 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4340 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4343 else if (reg
>= hi_reg
)
4345 as_bad (_("bad register range"));
4348 for (; reg
< hi_reg
; reg
++)
4352 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4354 skip_past_char (&input_line_pointer
, '}');
4356 demand_empty_rest_of_line ();
4358 /* Generate any deferred opcodes because we're going to be looking at
4360 flush_pending_unwind ();
4362 for (reg
= 0; reg
< 16; reg
++)
4364 if (mask
& (1 << reg
))
4365 unwind
.frame_size
+= 4;
4368 add_unwind_opcode (op
, 2);
4371 ignore_rest_of_line ();
4375 /* Parse an unwind_save directive.
4376 If the argument is non-zero, this is a .vsave directive. */
4379 s_arm_unwind_save (int arch_v6
)
4382 struct reg_entry
*reg
;
4383 bfd_boolean had_brace
= FALSE
;
4385 if (!unwind
.proc_start
)
4386 as_bad (MISSING_FNSTART
);
4388 /* Figure out what sort of save we have. */
4389 peek
= input_line_pointer
;
4397 reg
= arm_reg_parse_multi (&peek
);
4401 as_bad (_("register expected"));
4402 ignore_rest_of_line ();
4411 as_bad (_("FPA .unwind_save does not take a register list"));
4412 ignore_rest_of_line ();
4415 input_line_pointer
= peek
;
4416 s_arm_unwind_save_fpa (reg
->number
);
4420 s_arm_unwind_save_core ();
4425 s_arm_unwind_save_vfp_armv6 ();
4427 s_arm_unwind_save_vfp ();
4430 case REG_TYPE_MMXWR
:
4431 s_arm_unwind_save_mmxwr ();
4434 case REG_TYPE_MMXWCG
:
4435 s_arm_unwind_save_mmxwcg ();
4439 as_bad (_(".unwind_save does not support this kind of register"));
4440 ignore_rest_of_line ();
4445 /* Parse an unwind_movsp directive. */
4448 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4454 if (!unwind
.proc_start
)
4455 as_bad (MISSING_FNSTART
);
4457 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4460 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4461 ignore_rest_of_line ();
4465 /* Optional constant. */
4466 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4468 if (immediate_for_directive (&offset
) == FAIL
)
4474 demand_empty_rest_of_line ();
4476 if (reg
== REG_SP
|| reg
== REG_PC
)
4478 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4482 if (unwind
.fp_reg
!= REG_SP
)
4483 as_bad (_("unexpected .unwind_movsp directive"));
4485 /* Generate opcode to restore the value. */
4487 add_unwind_opcode (op
, 1);
4489 /* Record the information for later. */
4490 unwind
.fp_reg
= reg
;
4491 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4492 unwind
.sp_restored
= 1;
4495 /* Parse an unwind_pad directive. */
4498 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4502 if (!unwind
.proc_start
)
4503 as_bad (MISSING_FNSTART
);
4505 if (immediate_for_directive (&offset
) == FAIL
)
4510 as_bad (_("stack increment must be multiple of 4"));
4511 ignore_rest_of_line ();
4515 /* Don't generate any opcodes, just record the details for later. */
4516 unwind
.frame_size
+= offset
;
4517 unwind
.pending_offset
+= offset
;
4519 demand_empty_rest_of_line ();
4522 /* Parse an unwind_setfp directive. */
4525 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4531 if (!unwind
.proc_start
)
4532 as_bad (MISSING_FNSTART
);
4534 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4535 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4538 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4540 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4542 as_bad (_("expected <reg>, <reg>"));
4543 ignore_rest_of_line ();
4547 /* Optional constant. */
4548 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4550 if (immediate_for_directive (&offset
) == FAIL
)
4556 demand_empty_rest_of_line ();
4558 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4560 as_bad (_("register must be either sp or set by a previous"
4561 "unwind_movsp directive"));
4565 /* Don't generate any opcodes, just record the information for later. */
4566 unwind
.fp_reg
= fp_reg
;
4568 if (sp_reg
== REG_SP
)
4569 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4571 unwind
.fp_offset
-= offset
;
4574 /* Parse an unwind_raw directive. */
4577 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4580 /* This is an arbitrary limit. */
4581 unsigned char op
[16];
4584 if (!unwind
.proc_start
)
4585 as_bad (MISSING_FNSTART
);
4588 if (exp
.X_op
== O_constant
4589 && skip_past_comma (&input_line_pointer
) != FAIL
)
4591 unwind
.frame_size
+= exp
.X_add_number
;
4595 exp
.X_op
= O_illegal
;
4597 if (exp
.X_op
!= O_constant
)
4599 as_bad (_("expected <offset>, <opcode>"));
4600 ignore_rest_of_line ();
4606 /* Parse the opcode. */
4611 as_bad (_("unwind opcode too long"));
4612 ignore_rest_of_line ();
4614 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4616 as_bad (_("invalid unwind opcode"));
4617 ignore_rest_of_line ();
4620 op
[count
++] = exp
.X_add_number
;
4622 /* Parse the next byte. */
4623 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4629 /* Add the opcode bytes in reverse order. */
4631 add_unwind_opcode (op
[count
], 1);
4633 demand_empty_rest_of_line ();
4637 /* Parse a .eabi_attribute directive. */
4640 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4642 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4644 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4645 attributes_set_explicitly
[tag
] = 1;
4648 /* Emit a tls fix for the symbol. */
4651 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4655 #ifdef md_flush_pending_output
4656 md_flush_pending_output ();
4659 #ifdef md_cons_align
4663 /* Since we're just labelling the code, there's no need to define a
4666 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4667 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4668 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4669 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4671 #endif /* OBJ_ELF */
4673 static void s_arm_arch (int);
4674 static void s_arm_object_arch (int);
4675 static void s_arm_cpu (int);
4676 static void s_arm_fpu (int);
4677 static void s_arm_arch_extension (int);
4682 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4689 if (exp
.X_op
== O_symbol
)
4690 exp
.X_op
= O_secrel
;
4692 emit_expr (&exp
, 4);
4694 while (*input_line_pointer
++ == ',');
4696 input_line_pointer
--;
4697 demand_empty_rest_of_line ();
4701 /* This table describes all the machine specific pseudo-ops the assembler
4702 has to support. The fields are:
4703 pseudo-op name without dot
4704 function to call to execute this pseudo-op
4705 Integer arg to pass to the function. */
4707 const pseudo_typeS md_pseudo_table
[] =
4709 /* Never called because '.req' does not start a line. */
4710 { "req", s_req
, 0 },
4711 /* Following two are likewise never called. */
4714 { "unreq", s_unreq
, 0 },
4715 { "bss", s_bss
, 0 },
4716 { "align", s_align_ptwo
, 2 },
4717 { "arm", s_arm
, 0 },
4718 { "thumb", s_thumb
, 0 },
4719 { "code", s_code
, 0 },
4720 { "force_thumb", s_force_thumb
, 0 },
4721 { "thumb_func", s_thumb_func
, 0 },
4722 { "thumb_set", s_thumb_set
, 0 },
4723 { "even", s_even
, 0 },
4724 { "ltorg", s_ltorg
, 0 },
4725 { "pool", s_ltorg
, 0 },
4726 { "syntax", s_syntax
, 0 },
4727 { "cpu", s_arm_cpu
, 0 },
4728 { "arch", s_arm_arch
, 0 },
4729 { "object_arch", s_arm_object_arch
, 0 },
4730 { "fpu", s_arm_fpu
, 0 },
4731 { "arch_extension", s_arm_arch_extension
, 0 },
4733 { "word", s_arm_elf_cons
, 4 },
4734 { "long", s_arm_elf_cons
, 4 },
4735 { "inst.n", s_arm_elf_inst
, 2 },
4736 { "inst.w", s_arm_elf_inst
, 4 },
4737 { "inst", s_arm_elf_inst
, 0 },
4738 { "rel31", s_arm_rel31
, 0 },
4739 { "fnstart", s_arm_unwind_fnstart
, 0 },
4740 { "fnend", s_arm_unwind_fnend
, 0 },
4741 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4742 { "personality", s_arm_unwind_personality
, 0 },
4743 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4744 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4745 { "save", s_arm_unwind_save
, 0 },
4746 { "vsave", s_arm_unwind_save
, 1 },
4747 { "movsp", s_arm_unwind_movsp
, 0 },
4748 { "pad", s_arm_unwind_pad
, 0 },
4749 { "setfp", s_arm_unwind_setfp
, 0 },
4750 { "unwind_raw", s_arm_unwind_raw
, 0 },
4751 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4752 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4756 /* These are used for dwarf. */
4760 /* These are used for dwarf2. */
4761 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4762 { "loc", dwarf2_directive_loc
, 0 },
4763 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4765 { "extend", float_cons
, 'x' },
4766 { "ldouble", float_cons
, 'x' },
4767 { "packed", float_cons
, 'p' },
4769 {"secrel32", pe_directive_secrel
, 0},
4772 /* These are for compatibility with CodeComposer Studio. */
4773 {"ref", s_ccs_ref
, 0},
4774 {"def", s_ccs_def
, 0},
4775 {"asmfunc", s_ccs_asmfunc
, 0},
4776 {"endasmfunc", s_ccs_endasmfunc
, 0},
4781 /* Parser functions used exclusively in instruction operands. */
4783 /* Generic immediate-value read function for use in insn parsing.
4784 STR points to the beginning of the immediate (the leading #);
4785 VAL receives the value; if the value is outside [MIN, MAX]
4786 issue an error. PREFIX_OPT is true if the immediate prefix is
4790 parse_immediate (char **str
, int *val
, int min
, int max
,
4791 bfd_boolean prefix_opt
)
4795 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4796 if (exp
.X_op
!= O_constant
)
4798 inst
.error
= _("constant expression required");
4802 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4804 inst
.error
= _("immediate value out of range");
4808 *val
= exp
.X_add_number
;
4812 /* Less-generic immediate-value read function with the possibility of loading a
4813 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4814 instructions. Puts the result directly in inst.operands[i]. */
4817 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4818 bfd_boolean allow_symbol_p
)
4821 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4824 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4826 if (exp_p
->X_op
== O_constant
)
4828 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4829 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4830 O_constant. We have to be careful not to break compilation for
4831 32-bit X_add_number, though. */
4832 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4834 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4835 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4837 inst
.operands
[i
].regisimm
= 1;
4840 else if (exp_p
->X_op
== O_big
4841 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4843 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4845 /* Bignums have their least significant bits in
4846 generic_bignum[0]. Make sure we put 32 bits in imm and
4847 32 bits in reg, in a (hopefully) portable way. */
4848 gas_assert (parts
!= 0);
4850 /* Make sure that the number is not too big.
4851 PR 11972: Bignums can now be sign-extended to the
4852 size of a .octa so check that the out of range bits
4853 are all zero or all one. */
4854 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4856 LITTLENUM_TYPE m
= -1;
4858 if (generic_bignum
[parts
* 2] != 0
4859 && generic_bignum
[parts
* 2] != m
)
4862 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4863 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4867 inst
.operands
[i
].imm
= 0;
4868 for (j
= 0; j
< parts
; j
++, idx
++)
4869 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4870 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4871 inst
.operands
[i
].reg
= 0;
4872 for (j
= 0; j
< parts
; j
++, idx
++)
4873 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4874 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4875 inst
.operands
[i
].regisimm
= 1;
4877 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4885 /* Returns the pseudo-register number of an FPA immediate constant,
4886 or FAIL if there isn't a valid constant here. */
4889 parse_fpa_immediate (char ** str
)
4891 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4897 /* First try and match exact strings, this is to guarantee
4898 that some formats will work even for cross assembly. */
4900 for (i
= 0; fp_const
[i
]; i
++)
4902 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4906 *str
+= strlen (fp_const
[i
]);
4907 if (is_end_of_line
[(unsigned char) **str
])
4913 /* Just because we didn't get a match doesn't mean that the constant
4914 isn't valid, just that it is in a format that we don't
4915 automatically recognize. Try parsing it with the standard
4916 expression routines. */
4918 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4920 /* Look for a raw floating point number. */
4921 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4922 && is_end_of_line
[(unsigned char) *save_in
])
4924 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4926 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4928 if (words
[j
] != fp_values
[i
][j
])
4932 if (j
== MAX_LITTLENUMS
)
4940 /* Try and parse a more complex expression, this will probably fail
4941 unless the code uses a floating point prefix (eg "0f"). */
4942 save_in
= input_line_pointer
;
4943 input_line_pointer
= *str
;
4944 if (expression (&exp
) == absolute_section
4945 && exp
.X_op
== O_big
4946 && exp
.X_add_number
< 0)
4948 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4950 #define X_PRECISION 5
4951 #define E_PRECISION 15L
4952 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4954 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4956 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4958 if (words
[j
] != fp_values
[i
][j
])
4962 if (j
== MAX_LITTLENUMS
)
4964 *str
= input_line_pointer
;
4965 input_line_pointer
= save_in
;
4972 *str
= input_line_pointer
;
4973 input_line_pointer
= save_in
;
4974 inst
.error
= _("invalid FPA immediate expression");
4978 /* Returns 1 if a number has "quarter-precision" float format
4979 0baBbbbbbc defgh000 00000000 00000000. */
4982 is_quarter_float (unsigned imm
)
4984 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4985 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4989 /* Detect the presence of a floating point or integer zero constant,
4993 parse_ifimm_zero (char **in
)
4997 if (!is_immediate_prefix (**in
))
4999 /* In unified syntax, all prefixes are optional. */
5000 if (!unified_syntax
)
5006 /* Accept #0x0 as a synonym for #0. */
5007 if (strncmp (*in
, "0x", 2) == 0)
5010 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5015 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5016 &generic_floating_point_number
);
5019 && generic_floating_point_number
.sign
== '+'
5020 && (generic_floating_point_number
.low
5021 > generic_floating_point_number
.leader
))
5027 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5028 0baBbbbbbc defgh000 00000000 00000000.
5029 The zero and minus-zero cases need special handling, since they can't be
5030 encoded in the "quarter-precision" float format, but can nonetheless be
5031 loaded as integer constants. */
5034 parse_qfloat_immediate (char **ccp
, int *immed
)
5038 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5039 int found_fpchar
= 0;
5041 skip_past_char (&str
, '#');
5043 /* We must not accidentally parse an integer as a floating-point number. Make
5044 sure that the value we parse is not an integer by checking for special
5045 characters '.' or 'e'.
5046 FIXME: This is a horrible hack, but doing better is tricky because type
5047 information isn't in a very usable state at parse time. */
5049 skip_whitespace (fpnum
);
5051 if (strncmp (fpnum
, "0x", 2) == 0)
5055 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5056 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5066 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5068 unsigned fpword
= 0;
5071 /* Our FP word must be 32 bits (single-precision FP). */
5072 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5074 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5078 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5091 /* Shift operands. */
5094 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5097 struct asm_shift_name
5100 enum shift_kind kind
;
5103 /* Third argument to parse_shift. */
5104 enum parse_shift_mode
5106 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5107 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5108 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5109 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5110 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5113 /* Parse a <shift> specifier on an ARM data processing instruction.
5114 This has three forms:
5116 (LSL|LSR|ASL|ASR|ROR) Rs
5117 (LSL|LSR|ASL|ASR|ROR) #imm
5120 Note that ASL is assimilated to LSL in the instruction encoding, and
5121 RRX to ROR #0 (which cannot be written as such). */
5124 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5126 const struct asm_shift_name
*shift_name
;
5127 enum shift_kind shift
;
5132 for (p
= *str
; ISALPHA (*p
); p
++)
5137 inst
.error
= _("shift expression expected");
5141 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5144 if (shift_name
== NULL
)
5146 inst
.error
= _("shift expression expected");
5150 shift
= shift_name
->kind
;
5154 case NO_SHIFT_RESTRICT
:
5155 case SHIFT_IMMEDIATE
: break;
5157 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5158 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5160 inst
.error
= _("'LSL' or 'ASR' required");
5165 case SHIFT_LSL_IMMEDIATE
:
5166 if (shift
!= SHIFT_LSL
)
5168 inst
.error
= _("'LSL' required");
5173 case SHIFT_ASR_IMMEDIATE
:
5174 if (shift
!= SHIFT_ASR
)
5176 inst
.error
= _("'ASR' required");
5184 if (shift
!= SHIFT_RRX
)
5186 /* Whitespace can appear here if the next thing is a bare digit. */
5187 skip_whitespace (p
);
5189 if (mode
== NO_SHIFT_RESTRICT
5190 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5192 inst
.operands
[i
].imm
= reg
;
5193 inst
.operands
[i
].immisreg
= 1;
5195 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5198 inst
.operands
[i
].shift_kind
= shift
;
5199 inst
.operands
[i
].shifted
= 1;
5204 /* Parse a <shifter_operand> for an ARM data processing instruction:
5207 #<immediate>, <rotate>
5211 where <shift> is defined by parse_shift above, and <rotate> is a
5212 multiple of 2 between 0 and 30. Validation of immediate operands
5213 is deferred to md_apply_fix. */
5216 parse_shifter_operand (char **str
, int i
)
5221 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5223 inst
.operands
[i
].reg
= value
;
5224 inst
.operands
[i
].isreg
= 1;
5226 /* parse_shift will override this if appropriate */
5227 inst
.reloc
.exp
.X_op
= O_constant
;
5228 inst
.reloc
.exp
.X_add_number
= 0;
5230 if (skip_past_comma (str
) == FAIL
)
5233 /* Shift operation on register. */
5234 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5237 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5240 if (skip_past_comma (str
) == SUCCESS
)
5242 /* #x, y -- ie explicit rotation by Y. */
5243 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5246 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5248 inst
.error
= _("constant expression expected");
5252 value
= exp
.X_add_number
;
5253 if (value
< 0 || value
> 30 || value
% 2 != 0)
5255 inst
.error
= _("invalid rotation");
5258 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5260 inst
.error
= _("invalid constant");
5264 /* Encode as specified. */
5265 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5269 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5270 inst
.reloc
.pc_rel
= 0;
5274 /* Group relocation information. Each entry in the table contains the
5275 textual name of the relocation as may appear in assembler source
5276 and must end with a colon.
5277 Along with this textual name are the relocation codes to be used if
5278 the corresponding instruction is an ALU instruction (ADD or SUB only),
5279 an LDR, an LDRS, or an LDC. */
5281 struct group_reloc_table_entry
5292 /* Varieties of non-ALU group relocation. */
5299 static struct group_reloc_table_entry group_reloc_table
[] =
5300 { /* Program counter relative: */
5302 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5307 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5308 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5309 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5310 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5312 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5318 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5323 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5324 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5325 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5326 /* Section base relative */
5328 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5333 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5334 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5335 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5336 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5338 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5343 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5344 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5345 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5346 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5348 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5349 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5350 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5351 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5352 /* Absolute thumb alu relocations. */
5354 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5359 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5364 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5369 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5374 /* Given the address of a pointer pointing to the textual name of a group
5375 relocation as may appear in assembler source, attempt to find its details
5376 in group_reloc_table. The pointer will be updated to the character after
5377 the trailing colon. On failure, FAIL will be returned; SUCCESS
5378 otherwise. On success, *entry will be updated to point at the relevant
5379 group_reloc_table entry. */
5382 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5385 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5387 int length
= strlen (group_reloc_table
[i
].name
);
5389 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5390 && (*str
)[length
] == ':')
5392 *out
= &group_reloc_table
[i
];
5393 *str
+= (length
+ 1);
5401 /* Parse a <shifter_operand> for an ARM data processing instruction
5402 (as for parse_shifter_operand) where group relocations are allowed:
5405 #<immediate>, <rotate>
5406 #:<group_reloc>:<expression>
5410 where <group_reloc> is one of the strings defined in group_reloc_table.
5411 The hashes are optional.
5413 Everything else is as for parse_shifter_operand. */
5415 static parse_operand_result
5416 parse_shifter_operand_group_reloc (char **str
, int i
)
5418 /* Determine if we have the sequence of characters #: or just :
5419 coming next. If we do, then we check for a group relocation.
5420 If we don't, punt the whole lot to parse_shifter_operand. */
5422 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5423 || (*str
)[0] == ':')
5425 struct group_reloc_table_entry
*entry
;
5427 if ((*str
)[0] == '#')
5432 /* Try to parse a group relocation. Anything else is an error. */
5433 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5435 inst
.error
= _("unknown group relocation");
5436 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5439 /* We now have the group relocation table entry corresponding to
5440 the name in the assembler source. Next, we parse the expression. */
5441 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5442 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5444 /* Record the relocation type (always the ALU variant here). */
5445 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5446 gas_assert (inst
.reloc
.type
!= 0);
5448 return PARSE_OPERAND_SUCCESS
;
5451 return parse_shifter_operand (str
, i
) == SUCCESS
5452 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5454 /* Never reached. */
5457 /* Parse a Neon alignment expression. Information is written to
5458 inst.operands[i]. We assume the initial ':' has been skipped.
5460 align .imm = align << 8, .immisalign=1, .preind=0 */
5461 static parse_operand_result
5462 parse_neon_alignment (char **str
, int i
)
5467 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5469 if (exp
.X_op
!= O_constant
)
5471 inst
.error
= _("alignment must be constant");
5472 return PARSE_OPERAND_FAIL
;
5475 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5476 inst
.operands
[i
].immisalign
= 1;
5477 /* Alignments are not pre-indexes. */
5478 inst
.operands
[i
].preind
= 0;
5481 return PARSE_OPERAND_SUCCESS
;
5484 /* Parse all forms of an ARM address expression. Information is written
5485 to inst.operands[i] and/or inst.reloc.
5487 Preindexed addressing (.preind=1):
5489 [Rn, #offset] .reg=Rn .reloc.exp=offset
5490 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5491 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5492 .shift_kind=shift .reloc.exp=shift_imm
5494 These three may have a trailing ! which causes .writeback to be set also.
5496 Postindexed addressing (.postind=1, .writeback=1):
5498 [Rn], #offset .reg=Rn .reloc.exp=offset
5499 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5500 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5501 .shift_kind=shift .reloc.exp=shift_imm
5503 Unindexed addressing (.preind=0, .postind=0):
5505 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5509 [Rn]{!} shorthand for [Rn,#0]{!}
5510 =immediate .isreg=0 .reloc.exp=immediate
5511 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5513 It is the caller's responsibility to check for addressing modes not
5514 supported by the instruction, and to set inst.reloc.type. */
5516 static parse_operand_result
5517 parse_address_main (char **str
, int i
, int group_relocations
,
5518 group_reloc_type group_type
)
5523 if (skip_past_char (&p
, '[') == FAIL
)
5525 if (skip_past_char (&p
, '=') == FAIL
)
5527 /* Bare address - translate to PC-relative offset. */
5528 inst
.reloc
.pc_rel
= 1;
5529 inst
.operands
[i
].reg
= REG_PC
;
5530 inst
.operands
[i
].isreg
= 1;
5531 inst
.operands
[i
].preind
= 1;
5533 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5534 return PARSE_OPERAND_FAIL
;
5536 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5537 /*allow_symbol_p=*/TRUE
))
5538 return PARSE_OPERAND_FAIL
;
5541 return PARSE_OPERAND_SUCCESS
;
5544 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5545 skip_whitespace (p
);
5547 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5549 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5550 return PARSE_OPERAND_FAIL
;
5552 inst
.operands
[i
].reg
= reg
;
5553 inst
.operands
[i
].isreg
= 1;
5555 if (skip_past_comma (&p
) == SUCCESS
)
5557 inst
.operands
[i
].preind
= 1;
5560 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5562 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5564 inst
.operands
[i
].imm
= reg
;
5565 inst
.operands
[i
].immisreg
= 1;
5567 if (skip_past_comma (&p
) == SUCCESS
)
5568 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5569 return PARSE_OPERAND_FAIL
;
5571 else if (skip_past_char (&p
, ':') == SUCCESS
)
5573 /* FIXME: '@' should be used here, but it's filtered out by generic
5574 code before we get to see it here. This may be subject to
5576 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5578 if (result
!= PARSE_OPERAND_SUCCESS
)
5583 if (inst
.operands
[i
].negative
)
5585 inst
.operands
[i
].negative
= 0;
5589 if (group_relocations
5590 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5592 struct group_reloc_table_entry
*entry
;
5594 /* Skip over the #: or : sequence. */
5600 /* Try to parse a group relocation. Anything else is an
5602 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5604 inst
.error
= _("unknown group relocation");
5605 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5608 /* We now have the group relocation table entry corresponding to
5609 the name in the assembler source. Next, we parse the
5611 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5612 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5614 /* Record the relocation type. */
5618 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5622 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5626 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5633 if (inst
.reloc
.type
== 0)
5635 inst
.error
= _("this group relocation is not allowed on this instruction");
5636 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5643 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5644 return PARSE_OPERAND_FAIL
;
5645 /* If the offset is 0, find out if it's a +0 or -0. */
5646 if (inst
.reloc
.exp
.X_op
== O_constant
5647 && inst
.reloc
.exp
.X_add_number
== 0)
5649 skip_whitespace (q
);
5653 skip_whitespace (q
);
5656 inst
.operands
[i
].negative
= 1;
5661 else if (skip_past_char (&p
, ':') == SUCCESS
)
5663 /* FIXME: '@' should be used here, but it's filtered out by generic code
5664 before we get to see it here. This may be subject to change. */
5665 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5667 if (result
!= PARSE_OPERAND_SUCCESS
)
5671 if (skip_past_char (&p
, ']') == FAIL
)
5673 inst
.error
= _("']' expected");
5674 return PARSE_OPERAND_FAIL
;
5677 if (skip_past_char (&p
, '!') == SUCCESS
)
5678 inst
.operands
[i
].writeback
= 1;
5680 else if (skip_past_comma (&p
) == SUCCESS
)
5682 if (skip_past_char (&p
, '{') == SUCCESS
)
5684 /* [Rn], {expr} - unindexed, with option */
5685 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5686 0, 255, TRUE
) == FAIL
)
5687 return PARSE_OPERAND_FAIL
;
5689 if (skip_past_char (&p
, '}') == FAIL
)
5691 inst
.error
= _("'}' expected at end of 'option' field");
5692 return PARSE_OPERAND_FAIL
;
5694 if (inst
.operands
[i
].preind
)
5696 inst
.error
= _("cannot combine index with option");
5697 return PARSE_OPERAND_FAIL
;
5700 return PARSE_OPERAND_SUCCESS
;
5704 inst
.operands
[i
].postind
= 1;
5705 inst
.operands
[i
].writeback
= 1;
5707 if (inst
.operands
[i
].preind
)
5709 inst
.error
= _("cannot combine pre- and post-indexing");
5710 return PARSE_OPERAND_FAIL
;
5714 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5716 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5718 /* We might be using the immediate for alignment already. If we
5719 are, OR the register number into the low-order bits. */
5720 if (inst
.operands
[i
].immisalign
)
5721 inst
.operands
[i
].imm
|= reg
;
5723 inst
.operands
[i
].imm
= reg
;
5724 inst
.operands
[i
].immisreg
= 1;
5726 if (skip_past_comma (&p
) == SUCCESS
)
5727 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5728 return PARSE_OPERAND_FAIL
;
5734 if (inst
.operands
[i
].negative
)
5736 inst
.operands
[i
].negative
= 0;
5739 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5740 return PARSE_OPERAND_FAIL
;
5741 /* If the offset is 0, find out if it's a +0 or -0. */
5742 if (inst
.reloc
.exp
.X_op
== O_constant
5743 && inst
.reloc
.exp
.X_add_number
== 0)
5745 skip_whitespace (q
);
5749 skip_whitespace (q
);
5752 inst
.operands
[i
].negative
= 1;
5758 /* If at this point neither .preind nor .postind is set, we have a
5759 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5760 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5762 inst
.operands
[i
].preind
= 1;
5763 inst
.reloc
.exp
.X_op
= O_constant
;
5764 inst
.reloc
.exp
.X_add_number
= 0;
5767 return PARSE_OPERAND_SUCCESS
;
5771 parse_address (char **str
, int i
)
5773 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5777 static parse_operand_result
5778 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5780 return parse_address_main (str
, i
, 1, type
);
5783 /* Parse an operand for a MOVW or MOVT instruction. */
5785 parse_half (char **str
)
5790 skip_past_char (&p
, '#');
5791 if (strncasecmp (p
, ":lower16:", 9) == 0)
5792 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5793 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5794 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5796 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5799 skip_whitespace (p
);
5802 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5805 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5807 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5809 inst
.error
= _("constant expression expected");
5812 if (inst
.reloc
.exp
.X_add_number
< 0
5813 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5815 inst
.error
= _("immediate value out of range");
5823 /* Miscellaneous. */
5825 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5826 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5828 parse_psr (char **str
, bfd_boolean lhs
)
5831 unsigned long psr_field
;
5832 const struct asm_psr
*psr
;
5834 bfd_boolean is_apsr
= FALSE
;
5835 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5837 /* PR gas/12698: If the user has specified -march=all then m_profile will
5838 be TRUE, but we want to ignore it in this case as we are building for any
5839 CPU type, including non-m variants. */
5840 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5843 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5844 feature for ease of use and backwards compatibility. */
5846 if (strncasecmp (p
, "SPSR", 4) == 0)
5849 goto unsupported_psr
;
5851 psr_field
= SPSR_BIT
;
5853 else if (strncasecmp (p
, "CPSR", 4) == 0)
5856 goto unsupported_psr
;
5860 else if (strncasecmp (p
, "APSR", 4) == 0)
5862 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5863 and ARMv7-R architecture CPUs. */
5872 while (ISALNUM (*p
) || *p
== '_');
5874 if (strncasecmp (start
, "iapsr", 5) == 0
5875 || strncasecmp (start
, "eapsr", 5) == 0
5876 || strncasecmp (start
, "xpsr", 4) == 0
5877 || strncasecmp (start
, "psr", 3) == 0)
5878 p
= start
+ strcspn (start
, "rR") + 1;
5880 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5886 /* If APSR is being written, a bitfield may be specified. Note that
5887 APSR itself is handled above. */
5888 if (psr
->field
<= 3)
5890 psr_field
= psr
->field
;
5896 /* M-profile MSR instructions have the mask field set to "10", except
5897 *PSR variants which modify APSR, which may use a different mask (and
5898 have been handled already). Do that by setting the PSR_f field
5900 return psr
->field
| (lhs
? PSR_f
: 0);
5903 goto unsupported_psr
;
5909 /* A suffix follows. */
5915 while (ISALNUM (*p
) || *p
== '_');
5919 /* APSR uses a notation for bits, rather than fields. */
5920 unsigned int nzcvq_bits
= 0;
5921 unsigned int g_bit
= 0;
5924 for (bit
= start
; bit
!= p
; bit
++)
5926 switch (TOLOWER (*bit
))
5929 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5933 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5937 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5941 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5945 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5949 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5953 inst
.error
= _("unexpected bit specified after APSR");
5958 if (nzcvq_bits
== 0x1f)
5963 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5965 inst
.error
= _("selected processor does not "
5966 "support DSP extension");
5973 if ((nzcvq_bits
& 0x20) != 0
5974 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5975 || (g_bit
& 0x2) != 0)
5977 inst
.error
= _("bad bitmask specified after APSR");
5983 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5988 psr_field
|= psr
->field
;
5994 goto error
; /* Garbage after "[CS]PSR". */
5996 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5997 is deprecated, but allow it anyway. */
6001 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6004 else if (!m_profile
)
6005 /* These bits are never right for M-profile devices: don't set them
6006 (only code paths which read/write APSR reach here). */
6007 psr_field
|= (PSR_c
| PSR_f
);
6013 inst
.error
= _("selected processor does not support requested special "
6014 "purpose register");
6018 inst
.error
= _("flag for {c}psr instruction expected");
6022 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6023 value suitable for splatting into the AIF field of the instruction. */
6026 parse_cps_flags (char **str
)
6035 case '\0': case ',':
6038 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6039 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6040 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6043 inst
.error
= _("unrecognized CPS flag");
6048 if (saw_a_flag
== 0)
6050 inst
.error
= _("missing CPS flags");
6058 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6059 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6062 parse_endian_specifier (char **str
)
6067 if (strncasecmp (s
, "BE", 2))
6069 else if (strncasecmp (s
, "LE", 2))
6073 inst
.error
= _("valid endian specifiers are be or le");
6077 if (ISALNUM (s
[2]) || s
[2] == '_')
6079 inst
.error
= _("valid endian specifiers are be or le");
6084 return little_endian
;
6087 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6088 value suitable for poking into the rotate field of an sxt or sxta
6089 instruction, or FAIL on error. */
6092 parse_ror (char **str
)
6097 if (strncasecmp (s
, "ROR", 3) == 0)
6101 inst
.error
= _("missing rotation field after comma");
6105 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6110 case 0: *str
= s
; return 0x0;
6111 case 8: *str
= s
; return 0x1;
6112 case 16: *str
= s
; return 0x2;
6113 case 24: *str
= s
; return 0x3;
6116 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6121 /* Parse a conditional code (from conds[] below). The value returned is in the
6122 range 0 .. 14, or FAIL. */
6124 parse_cond (char **str
)
6127 const struct asm_cond
*c
;
6129 /* Condition codes are always 2 characters, so matching up to
6130 3 characters is sufficient. */
6135 while (ISALPHA (*q
) && n
< 3)
6137 cond
[n
] = TOLOWER (*q
);
6142 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6145 inst
.error
= _("condition required");
6153 /* Record a use of the given feature. */
6155 record_feature_use (const arm_feature_set
*feature
)
6158 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6160 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6163 /* If the given feature available in the selected CPU, mark it as used.
6164 Returns TRUE iff feature is available. */
6166 mark_feature_used (const arm_feature_set
*feature
)
6168 /* Ensure the option is valid on the current architecture. */
6169 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6172 /* Add the appropriate architecture feature for the barrier option used.
6174 record_feature_use (feature
);
6179 /* Parse an option for a barrier instruction. Returns the encoding for the
6182 parse_barrier (char **str
)
6185 const struct asm_barrier_opt
*o
;
6188 while (ISALPHA (*q
))
6191 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6196 if (!mark_feature_used (&o
->arch
))
6203 /* Parse the operands of a table branch instruction. Similar to a memory
6206 parse_tb (char **str
)
6211 if (skip_past_char (&p
, '[') == FAIL
)
6213 inst
.error
= _("'[' expected");
6217 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6219 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6222 inst
.operands
[0].reg
= reg
;
6224 if (skip_past_comma (&p
) == FAIL
)
6226 inst
.error
= _("',' expected");
6230 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6232 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6235 inst
.operands
[0].imm
= reg
;
6237 if (skip_past_comma (&p
) == SUCCESS
)
6239 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6241 if (inst
.reloc
.exp
.X_add_number
!= 1)
6243 inst
.error
= _("invalid shift");
6246 inst
.operands
[0].shifted
= 1;
6249 if (skip_past_char (&p
, ']') == FAIL
)
6251 inst
.error
= _("']' expected");
6258 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6259 information on the types the operands can take and how they are encoded.
6260 Up to four operands may be read; this function handles setting the
6261 ".present" field for each read operand itself.
6262 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6263 else returns FAIL. */
6266 parse_neon_mov (char **str
, int *which_operand
)
6268 int i
= *which_operand
, val
;
6269 enum arm_reg_type rtype
;
6271 struct neon_type_el optype
;
6273 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6275 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6276 inst
.operands
[i
].reg
= val
;
6277 inst
.operands
[i
].isscalar
= 1;
6278 inst
.operands
[i
].vectype
= optype
;
6279 inst
.operands
[i
++].present
= 1;
6281 if (skip_past_comma (&ptr
) == FAIL
)
6284 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6287 inst
.operands
[i
].reg
= val
;
6288 inst
.operands
[i
].isreg
= 1;
6289 inst
.operands
[i
].present
= 1;
6291 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6294 /* Cases 0, 1, 2, 3, 5 (D only). */
6295 if (skip_past_comma (&ptr
) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6301 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6302 inst
.operands
[i
].isvec
= 1;
6303 inst
.operands
[i
].vectype
= optype
;
6304 inst
.operands
[i
++].present
= 1;
6306 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6308 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6309 Case 13: VMOV <Sd>, <Rm> */
6310 inst
.operands
[i
].reg
= val
;
6311 inst
.operands
[i
].isreg
= 1;
6312 inst
.operands
[i
].present
= 1;
6314 if (rtype
== REG_TYPE_NQ
)
6316 first_error (_("can't use Neon quad register here"));
6319 else if (rtype
!= REG_TYPE_VFS
)
6322 if (skip_past_comma (&ptr
) == FAIL
)
6324 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
].present
= 1;
6331 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6334 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6335 Case 1: VMOV<c><q> <Dd>, <Dm>
6336 Case 8: VMOV.F32 <Sd>, <Sm>
6337 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6339 inst
.operands
[i
].reg
= val
;
6340 inst
.operands
[i
].isreg
= 1;
6341 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6342 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6343 inst
.operands
[i
].isvec
= 1;
6344 inst
.operands
[i
].vectype
= optype
;
6345 inst
.operands
[i
].present
= 1;
6347 if (skip_past_comma (&ptr
) == SUCCESS
)
6352 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6355 inst
.operands
[i
].reg
= val
;
6356 inst
.operands
[i
].isreg
= 1;
6357 inst
.operands
[i
++].present
= 1;
6359 if (skip_past_comma (&ptr
) == FAIL
)
6362 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
].present
= 1;
6370 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6371 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6372 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6373 Case 10: VMOV.F32 <Sd>, #<imm>
6374 Case 11: VMOV.F64 <Dd>, #<imm> */
6375 inst
.operands
[i
].immisfloat
= 1;
6376 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6378 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6379 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6383 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6387 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6390 inst
.operands
[i
].reg
= val
;
6391 inst
.operands
[i
].isreg
= 1;
6392 inst
.operands
[i
++].present
= 1;
6394 if (skip_past_comma (&ptr
) == FAIL
)
6397 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6399 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6400 inst
.operands
[i
].reg
= val
;
6401 inst
.operands
[i
].isscalar
= 1;
6402 inst
.operands
[i
].present
= 1;
6403 inst
.operands
[i
].vectype
= optype
;
6405 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6407 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6408 inst
.operands
[i
].reg
= val
;
6409 inst
.operands
[i
].isreg
= 1;
6410 inst
.operands
[i
++].present
= 1;
6412 if (skip_past_comma (&ptr
) == FAIL
)
6415 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6418 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6422 inst
.operands
[i
].reg
= val
;
6423 inst
.operands
[i
].isreg
= 1;
6424 inst
.operands
[i
].isvec
= 1;
6425 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6426 inst
.operands
[i
].vectype
= optype
;
6427 inst
.operands
[i
].present
= 1;
6429 if (rtype
== REG_TYPE_VFS
)
6433 if (skip_past_comma (&ptr
) == FAIL
)
6435 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6438 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6441 inst
.operands
[i
].reg
= val
;
6442 inst
.operands
[i
].isreg
= 1;
6443 inst
.operands
[i
].isvec
= 1;
6444 inst
.operands
[i
].issingle
= 1;
6445 inst
.operands
[i
].vectype
= optype
;
6446 inst
.operands
[i
].present
= 1;
6449 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6453 inst
.operands
[i
].reg
= val
;
6454 inst
.operands
[i
].isreg
= 1;
6455 inst
.operands
[i
].isvec
= 1;
6456 inst
.operands
[i
].issingle
= 1;
6457 inst
.operands
[i
].vectype
= optype
;
6458 inst
.operands
[i
].present
= 1;
6463 first_error (_("parse error"));
6467 /* Successfully parsed the operands. Update args. */
6473 first_error (_("expected comma"));
6477 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6481 /* Use this macro when the operand constraints are different
6482 for ARM and THUMB (e.g. ldrd). */
6483 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6484 ((arm_operand) | ((thumb_operand) << 16))
6486 /* Matcher codes for parse_operands. */
6487 enum operand_parse_code
6489 OP_stop
, /* end of line */
6491 OP_RR
, /* ARM register */
6492 OP_RRnpc
, /* ARM register, not r15 */
6493 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6494 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6495 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6496 optional trailing ! */
6497 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6498 OP_RCP
, /* Coprocessor number */
6499 OP_RCN
, /* Coprocessor register */
6500 OP_RF
, /* FPA register */
6501 OP_RVS
, /* VFP single precision register */
6502 OP_RVD
, /* VFP double precision register (0..15) */
6503 OP_RND
, /* Neon double precision register (0..31) */
6504 OP_RNQ
, /* Neon quad precision register */
6505 OP_RVSD
, /* VFP single or double precision register */
6506 OP_RNSD
, /* Neon single or double precision register */
6507 OP_RNDQ
, /* Neon double or quad precision register */
6508 OP_RNSDQ
, /* Neon single, double or quad precision register */
6509 OP_RNSC
, /* Neon scalar D[X] */
6510 OP_RVC
, /* VFP control register */
6511 OP_RMF
, /* Maverick F register */
6512 OP_RMD
, /* Maverick D register */
6513 OP_RMFX
, /* Maverick FX register */
6514 OP_RMDX
, /* Maverick DX register */
6515 OP_RMAX
, /* Maverick AX register */
6516 OP_RMDS
, /* Maverick DSPSC register */
6517 OP_RIWR
, /* iWMMXt wR register */
6518 OP_RIWC
, /* iWMMXt wC register */
6519 OP_RIWG
, /* iWMMXt wCG register */
6520 OP_RXA
, /* XScale accumulator register */
6522 OP_REGLST
, /* ARM register list */
6523 OP_VRSLST
, /* VFP single-precision register list */
6524 OP_VRDLST
, /* VFP double-precision register list */
6525 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6526 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6527 OP_NSTRLST
, /* Neon element/structure list */
6529 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6530 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6531 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6532 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6533 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6534 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6535 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6536 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6537 OP_VMOV
, /* Neon VMOV operands. */
6538 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6539 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6540 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6542 OP_I0
, /* immediate zero */
6543 OP_I7
, /* immediate value 0 .. 7 */
6544 OP_I15
, /* 0 .. 15 */
6545 OP_I16
, /* 1 .. 16 */
6546 OP_I16z
, /* 0 .. 16 */
6547 OP_I31
, /* 0 .. 31 */
6548 OP_I31w
, /* 0 .. 31, optional trailing ! */
6549 OP_I32
, /* 1 .. 32 */
6550 OP_I32z
, /* 0 .. 32 */
6551 OP_I63
, /* 0 .. 63 */
6552 OP_I63s
, /* -64 .. 63 */
6553 OP_I64
, /* 1 .. 64 */
6554 OP_I64z
, /* 0 .. 64 */
6555 OP_I255
, /* 0 .. 255 */
6557 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6558 OP_I7b
, /* 0 .. 7 */
6559 OP_I15b
, /* 0 .. 15 */
6560 OP_I31b
, /* 0 .. 31 */
6562 OP_SH
, /* shifter operand */
6563 OP_SHG
, /* shifter operand with possible group relocation */
6564 OP_ADDR
, /* Memory address expression (any mode) */
6565 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6566 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6567 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6568 OP_EXP
, /* arbitrary expression */
6569 OP_EXPi
, /* same, with optional immediate prefix */
6570 OP_EXPr
, /* same, with optional relocation suffix */
6571 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6572 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6573 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6575 OP_CPSF
, /* CPS flags */
6576 OP_ENDI
, /* Endianness specifier */
6577 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6578 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6579 OP_COND
, /* conditional code */
6580 OP_TB
, /* Table branch. */
6582 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6584 OP_RRnpc_I0
, /* ARM register or literal 0 */
6585 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6586 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6587 OP_RF_IF
, /* FPA register or immediate */
6588 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6589 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6591 /* Optional operands. */
6592 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6593 OP_oI31b
, /* 0 .. 31 */
6594 OP_oI32b
, /* 1 .. 32 */
6595 OP_oI32z
, /* 0 .. 32 */
6596 OP_oIffffb
, /* 0 .. 65535 */
6597 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6599 OP_oRR
, /* ARM register */
6600 OP_oRRnpc
, /* ARM register, not the PC */
6601 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6602 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6603 OP_oRND
, /* Optional Neon double precision register */
6604 OP_oRNQ
, /* Optional Neon quad precision register */
6605 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6606 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6607 OP_oSHll
, /* LSL immediate */
6608 OP_oSHar
, /* ASR immediate */
6609 OP_oSHllar
, /* LSL or ASR immediate */
6610 OP_oROR
, /* ROR 0/8/16/24 */
6611 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6613 /* Some pre-defined mixed (ARM/THUMB) operands. */
6614 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6615 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6616 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6618 OP_FIRST_OPTIONAL
= OP_oI7b
6621 /* Generic instruction operand parser. This does no encoding and no
6622 semantic validation; it merely squirrels values away in the inst
6623 structure. Returns SUCCESS or FAIL depending on whether the
6624 specified grammar matched. */
6626 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6628 unsigned const int *upat
= pattern
;
6629 char *backtrack_pos
= 0;
6630 const char *backtrack_error
= 0;
6631 int i
, val
= 0, backtrack_index
= 0;
6632 enum arm_reg_type rtype
;
6633 parse_operand_result result
;
6634 unsigned int op_parse_code
;
6636 #define po_char_or_fail(chr) \
6639 if (skip_past_char (&str, chr) == FAIL) \
6644 #define po_reg_or_fail(regtype) \
6647 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6648 & inst.operands[i].vectype); \
6651 first_error (_(reg_expected_msgs[regtype])); \
6654 inst.operands[i].reg = val; \
6655 inst.operands[i].isreg = 1; \
6656 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6657 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6658 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6659 || rtype == REG_TYPE_VFD \
6660 || rtype == REG_TYPE_NQ); \
6664 #define po_reg_or_goto(regtype, label) \
6667 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6668 & inst.operands[i].vectype); \
6672 inst.operands[i].reg = val; \
6673 inst.operands[i].isreg = 1; \
6674 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6675 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6676 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6677 || rtype == REG_TYPE_VFD \
6678 || rtype == REG_TYPE_NQ); \
6682 #define po_imm_or_fail(min, max, popt) \
6685 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6687 inst.operands[i].imm = val; \
6691 #define po_scalar_or_goto(elsz, label) \
6694 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6697 inst.operands[i].reg = val; \
6698 inst.operands[i].isscalar = 1; \
6702 #define po_misc_or_fail(expr) \
6710 #define po_misc_or_fail_no_backtrack(expr) \
6714 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6715 backtrack_pos = 0; \
6716 if (result != PARSE_OPERAND_SUCCESS) \
6721 #define po_barrier_or_imm(str) \
6724 val = parse_barrier (&str); \
6725 if (val == FAIL && ! ISALPHA (*str)) \
6728 /* ISB can only take SY as an option. */ \
6729 || ((inst.instruction & 0xf0) == 0x60 \
6732 inst.error = _("invalid barrier type"); \
6733 backtrack_pos = 0; \
6739 skip_whitespace (str
);
6741 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6743 op_parse_code
= upat
[i
];
6744 if (op_parse_code
>= 1<<16)
6745 op_parse_code
= thumb
? (op_parse_code
>> 16)
6746 : (op_parse_code
& ((1<<16)-1));
6748 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6750 /* Remember where we are in case we need to backtrack. */
6751 gas_assert (!backtrack_pos
);
6752 backtrack_pos
= str
;
6753 backtrack_error
= inst
.error
;
6754 backtrack_index
= i
;
6757 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6758 po_char_or_fail (',');
6760 switch (op_parse_code
)
6768 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6769 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6770 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6771 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6772 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6773 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6775 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6777 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6779 /* Also accept generic coprocessor regs for unknown registers. */
6781 po_reg_or_fail (REG_TYPE_CN
);
6783 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6784 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6785 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6786 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6787 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6788 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6789 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6790 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6791 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6792 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6794 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6795 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6797 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6798 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6800 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6802 /* Neon scalar. Using an element size of 8 means that some invalid
6803 scalars are accepted here, so deal with those in later code. */
6804 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6808 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6811 po_imm_or_fail (0, 0, TRUE
);
6816 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6821 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6824 if (parse_ifimm_zero (&str
))
6825 inst
.operands
[i
].imm
= 0;
6829 = _("only floating point zero is allowed as immediate value");
6837 po_scalar_or_goto (8, try_rr
);
6840 po_reg_or_fail (REG_TYPE_RN
);
6846 po_scalar_or_goto (8, try_nsdq
);
6849 po_reg_or_fail (REG_TYPE_NSDQ
);
6855 po_scalar_or_goto (8, try_s_scalar
);
6858 po_scalar_or_goto (4, try_nsd
);
6861 po_reg_or_fail (REG_TYPE_NSD
);
6867 po_scalar_or_goto (8, try_ndq
);
6870 po_reg_or_fail (REG_TYPE_NDQ
);
6876 po_scalar_or_goto (8, try_vfd
);
6879 po_reg_or_fail (REG_TYPE_VFD
);
6884 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6885 not careful then bad things might happen. */
6886 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6891 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6894 /* There's a possibility of getting a 64-bit immediate here, so
6895 we need special handling. */
6896 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6899 inst
.error
= _("immediate value is out of range");
6907 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6910 po_imm_or_fail (0, 63, TRUE
);
6915 po_char_or_fail ('[');
6916 po_reg_or_fail (REG_TYPE_RN
);
6917 po_char_or_fail (']');
6923 po_reg_or_fail (REG_TYPE_RN
);
6924 if (skip_past_char (&str
, '!') == SUCCESS
)
6925 inst
.operands
[i
].writeback
= 1;
6929 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6930 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6931 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6932 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6933 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6934 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6935 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6936 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6937 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6938 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6939 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6940 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6942 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6944 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6945 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6947 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6948 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6949 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6950 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6952 /* Immediate variants */
6954 po_char_or_fail ('{');
6955 po_imm_or_fail (0, 255, TRUE
);
6956 po_char_or_fail ('}');
6960 /* The expression parser chokes on a trailing !, so we have
6961 to find it first and zap it. */
6964 while (*s
&& *s
!= ',')
6969 inst
.operands
[i
].writeback
= 1;
6971 po_imm_or_fail (0, 31, TRUE
);
6979 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6984 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6989 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6991 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6993 val
= parse_reloc (&str
);
6996 inst
.error
= _("unrecognized relocation suffix");
6999 else if (val
!= BFD_RELOC_UNUSED
)
7001 inst
.operands
[i
].imm
= val
;
7002 inst
.operands
[i
].hasreloc
= 1;
7007 /* Operand for MOVW or MOVT. */
7009 po_misc_or_fail (parse_half (&str
));
7012 /* Register or expression. */
7013 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7014 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7016 /* Register or immediate. */
7017 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7018 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7020 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7022 if (!is_immediate_prefix (*str
))
7025 val
= parse_fpa_immediate (&str
);
7028 /* FPA immediates are encoded as registers 8-15.
7029 parse_fpa_immediate has already applied the offset. */
7030 inst
.operands
[i
].reg
= val
;
7031 inst
.operands
[i
].isreg
= 1;
7034 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7035 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7037 /* Two kinds of register. */
7040 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7042 || (rege
->type
!= REG_TYPE_MMXWR
7043 && rege
->type
!= REG_TYPE_MMXWC
7044 && rege
->type
!= REG_TYPE_MMXWCG
))
7046 inst
.error
= _("iWMMXt data or control register expected");
7049 inst
.operands
[i
].reg
= rege
->number
;
7050 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7056 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7058 || (rege
->type
!= REG_TYPE_MMXWC
7059 && rege
->type
!= REG_TYPE_MMXWCG
))
7061 inst
.error
= _("iWMMXt control register expected");
7064 inst
.operands
[i
].reg
= rege
->number
;
7065 inst
.operands
[i
].isreg
= 1;
7070 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7071 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7072 case OP_oROR
: val
= parse_ror (&str
); break;
7073 case OP_COND
: val
= parse_cond (&str
); break;
7074 case OP_oBARRIER_I15
:
7075 po_barrier_or_imm (str
); break;
7077 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7083 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7084 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7086 inst
.error
= _("Banked registers are not available with this "
7092 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7096 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7099 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7101 if (strncasecmp (str
, "APSR_", 5) == 0)
7108 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7109 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7110 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7111 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7112 default: found
= 16;
7116 inst
.operands
[i
].isvec
= 1;
7117 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7118 inst
.operands
[i
].reg
= REG_PC
;
7125 po_misc_or_fail (parse_tb (&str
));
7128 /* Register lists. */
7130 val
= parse_reg_list (&str
);
7133 inst
.operands
[i
].writeback
= 1;
7139 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7143 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7147 /* Allow Q registers too. */
7148 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7153 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7155 inst
.operands
[i
].issingle
= 1;
7160 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7165 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7166 &inst
.operands
[i
].vectype
);
7169 /* Addressing modes */
7171 po_misc_or_fail (parse_address (&str
, i
));
7175 po_misc_or_fail_no_backtrack (
7176 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7180 po_misc_or_fail_no_backtrack (
7181 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7185 po_misc_or_fail_no_backtrack (
7186 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7190 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7194 po_misc_or_fail_no_backtrack (
7195 parse_shifter_operand_group_reloc (&str
, i
));
7199 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7203 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7207 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7211 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7214 /* Various value-based sanity checks and shared operations. We
7215 do not signal immediate failures for the register constraints;
7216 this allows a syntax error to take precedence. */
7217 switch (op_parse_code
)
7225 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7226 inst
.error
= BAD_PC
;
7231 if (inst
.operands
[i
].isreg
)
7233 if (inst
.operands
[i
].reg
== REG_PC
)
7234 inst
.error
= BAD_PC
;
7235 else if (inst
.operands
[i
].reg
== REG_SP
7236 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7237 relaxed since ARMv8-A. */
7238 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7241 inst
.error
= BAD_SP
;
7247 if (inst
.operands
[i
].isreg
7248 && inst
.operands
[i
].reg
== REG_PC
7249 && (inst
.operands
[i
].writeback
|| thumb
))
7250 inst
.error
= BAD_PC
;
7259 case OP_oBARRIER_I15
:
7268 inst
.operands
[i
].imm
= val
;
7275 /* If we get here, this operand was successfully parsed. */
7276 inst
.operands
[i
].present
= 1;
7280 inst
.error
= BAD_ARGS
;
7285 /* The parse routine should already have set inst.error, but set a
7286 default here just in case. */
7288 inst
.error
= _("syntax error");
7292 /* Do not backtrack over a trailing optional argument that
7293 absorbed some text. We will only fail again, with the
7294 'garbage following instruction' error message, which is
7295 probably less helpful than the current one. */
7296 if (backtrack_index
== i
&& backtrack_pos
!= str
7297 && upat
[i
+1] == OP_stop
)
7300 inst
.error
= _("syntax error");
7304 /* Try again, skipping the optional argument at backtrack_pos. */
7305 str
= backtrack_pos
;
7306 inst
.error
= backtrack_error
;
7307 inst
.operands
[backtrack_index
].present
= 0;
7308 i
= backtrack_index
;
7312 /* Check that we have parsed all the arguments. */
7313 if (*str
!= '\0' && !inst
.error
)
7314 inst
.error
= _("garbage following instruction");
7316 return inst
.error
? FAIL
: SUCCESS
;
7319 #undef po_char_or_fail
7320 #undef po_reg_or_fail
7321 #undef po_reg_or_goto
7322 #undef po_imm_or_fail
7323 #undef po_scalar_or_fail
7324 #undef po_barrier_or_imm
7326 /* Shorthand macro for instruction encoding functions issuing errors. */
7327 #define constraint(expr, err) \
7338 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7339 instructions are unpredictable if these registers are used. This
7340 is the BadReg predicate in ARM's Thumb-2 documentation.
7342 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7343 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7344 #define reject_bad_reg(reg) \
7346 if (reg == REG_PC) \
7348 inst.error = BAD_PC; \
7351 else if (reg == REG_SP \
7352 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7354 inst.error = BAD_SP; \
7359 /* If REG is R13 (the stack pointer), warn that its use is
7361 #define warn_deprecated_sp(reg) \
7363 if (warn_on_deprecated && reg == REG_SP) \
7364 as_tsktsk (_("use of r13 is deprecated")); \
7367 /* Functions for operand encoding. ARM, then Thumb. */
7369 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7371 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7373 The only binary encoding difference is the Coprocessor number. Coprocessor
7374 9 is used for half-precision calculations or conversions. The format of the
7375 instruction is the same as the equivalent Coprocessor 10 instruction that
7376 exists for Single-Precision operation. */
7379 do_scalar_fp16_v82_encode (void)
7381 if (inst
.cond
!= COND_ALWAYS
)
7382 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7383 " the behaviour is UNPREDICTABLE"));
7384 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7387 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7388 mark_feature_used (&arm_ext_fp16
);
7391 /* If VAL can be encoded in the immediate field of an ARM instruction,
7392 return the encoded form. Otherwise, return FAIL. */
7395 encode_arm_immediate (unsigned int val
)
7402 for (i
= 2; i
< 32; i
+= 2)
7403 if ((a
= rotate_left (val
, i
)) <= 0xff)
7404 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7409 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7410 return the encoded form. Otherwise, return FAIL. */
7412 encode_thumb32_immediate (unsigned int val
)
7419 for (i
= 1; i
<= 24; i
++)
7422 if ((val
& ~(0xff << i
)) == 0)
7423 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7427 if (val
== ((a
<< 16) | a
))
7429 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7433 if (val
== ((a
<< 16) | a
))
7434 return 0x200 | (a
>> 8);
7438 /* Encode a VFP SP or DP register number into inst.instruction. */
7441 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7443 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7446 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7449 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7452 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7457 first_error (_("D register out of range for selected VFP version"));
7465 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7469 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7473 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7477 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7481 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7485 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7493 /* Encode a <shift> in an ARM-format instruction. The immediate,
7494 if any, is handled by md_apply_fix. */
7496 encode_arm_shift (int i
)
7498 /* register-shifted register. */
7499 if (inst
.operands
[i
].immisreg
)
7502 for (op_index
= 0; op_index
<= i
; ++op_index
)
7504 /* Check the operand only when it's presented. In pre-UAL syntax,
7505 if the destination register is the same as the first operand, two
7506 register form of the instruction can be used. */
7507 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7508 && inst
.operands
[op_index
].reg
== REG_PC
)
7509 as_warn (UNPRED_REG ("r15"));
7512 if (inst
.operands
[i
].imm
== REG_PC
)
7513 as_warn (UNPRED_REG ("r15"));
7516 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7517 inst
.instruction
|= SHIFT_ROR
<< 5;
7520 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7521 if (inst
.operands
[i
].immisreg
)
7523 inst
.instruction
|= SHIFT_BY_REG
;
7524 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7527 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7532 encode_arm_shifter_operand (int i
)
7534 if (inst
.operands
[i
].isreg
)
7536 inst
.instruction
|= inst
.operands
[i
].reg
;
7537 encode_arm_shift (i
);
7541 inst
.instruction
|= INST_IMMEDIATE
;
7542 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7543 inst
.instruction
|= inst
.operands
[i
].imm
;
7547 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7549 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7552 Generate an error if the operand is not a register. */
7553 constraint (!inst
.operands
[i
].isreg
,
7554 _("Instruction does not support =N addresses"));
7556 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7558 if (inst
.operands
[i
].preind
)
7562 inst
.error
= _("instruction does not accept preindexed addressing");
7565 inst
.instruction
|= PRE_INDEX
;
7566 if (inst
.operands
[i
].writeback
)
7567 inst
.instruction
|= WRITE_BACK
;
7570 else if (inst
.operands
[i
].postind
)
7572 gas_assert (inst
.operands
[i
].writeback
);
7574 inst
.instruction
|= WRITE_BACK
;
7576 else /* unindexed - only for coprocessor */
7578 inst
.error
= _("instruction does not accept unindexed addressing");
7582 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7583 && (((inst
.instruction
& 0x000f0000) >> 16)
7584 == ((inst
.instruction
& 0x0000f000) >> 12)))
7585 as_warn ((inst
.instruction
& LOAD_BIT
)
7586 ? _("destination register same as write-back base")
7587 : _("source register same as write-back base"));
7590 /* inst.operands[i] was set up by parse_address. Encode it into an
7591 ARM-format mode 2 load or store instruction. If is_t is true,
7592 reject forms that cannot be used with a T instruction (i.e. not
7595 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7597 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7599 encode_arm_addr_mode_common (i
, is_t
);
7601 if (inst
.operands
[i
].immisreg
)
7603 constraint ((inst
.operands
[i
].imm
== REG_PC
7604 || (is_pc
&& inst
.operands
[i
].writeback
)),
7606 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7607 inst
.instruction
|= inst
.operands
[i
].imm
;
7608 if (!inst
.operands
[i
].negative
)
7609 inst
.instruction
|= INDEX_UP
;
7610 if (inst
.operands
[i
].shifted
)
7612 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7613 inst
.instruction
|= SHIFT_ROR
<< 5;
7616 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7617 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7621 else /* immediate offset in inst.reloc */
7623 if (is_pc
&& !inst
.reloc
.pc_rel
)
7625 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7627 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7628 cannot use PC in addressing.
7629 PC cannot be used in writeback addressing, either. */
7630 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7633 /* Use of PC in str is deprecated for ARMv7. */
7634 if (warn_on_deprecated
7636 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7637 as_tsktsk (_("use of PC in this instruction is deprecated"));
7640 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7642 /* Prefer + for zero encoded value. */
7643 if (!inst
.operands
[i
].negative
)
7644 inst
.instruction
|= INDEX_UP
;
7645 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7650 /* inst.operands[i] was set up by parse_address. Encode it into an
7651 ARM-format mode 3 load or store instruction. Reject forms that
7652 cannot be used with such instructions. If is_t is true, reject
7653 forms that cannot be used with a T instruction (i.e. not
7656 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7658 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7660 inst
.error
= _("instruction does not accept scaled register index");
7664 encode_arm_addr_mode_common (i
, is_t
);
7666 if (inst
.operands
[i
].immisreg
)
7668 constraint ((inst
.operands
[i
].imm
== REG_PC
7669 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7671 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7673 inst
.instruction
|= inst
.operands
[i
].imm
;
7674 if (!inst
.operands
[i
].negative
)
7675 inst
.instruction
|= INDEX_UP
;
7677 else /* immediate offset in inst.reloc */
7679 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7680 && inst
.operands
[i
].writeback
),
7682 inst
.instruction
|= HWOFFSET_IMM
;
7683 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7685 /* Prefer + for zero encoded value. */
7686 if (!inst
.operands
[i
].negative
)
7687 inst
.instruction
|= INDEX_UP
;
7689 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7694 /* Write immediate bits [7:0] to the following locations:
7696 |28/24|23 19|18 16|15 4|3 0|
7697 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7699 This function is used by VMOV/VMVN/VORR/VBIC. */
7702 neon_write_immbits (unsigned immbits
)
7704 inst
.instruction
|= immbits
& 0xf;
7705 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7706 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7709 /* Invert low-order SIZE bits of XHI:XLO. */
7712 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7714 unsigned immlo
= xlo
? *xlo
: 0;
7715 unsigned immhi
= xhi
? *xhi
: 0;
7720 immlo
= (~immlo
) & 0xff;
7724 immlo
= (~immlo
) & 0xffff;
7728 immhi
= (~immhi
) & 0xffffffff;
7732 immlo
= (~immlo
) & 0xffffffff;
7746 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7750 neon_bits_same_in_bytes (unsigned imm
)
7752 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7753 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7754 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7755 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7758 /* For immediate of above form, return 0bABCD. */
7761 neon_squash_bits (unsigned imm
)
7763 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7764 | ((imm
& 0x01000000) >> 21);
7767 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7770 neon_qfloat_bits (unsigned imm
)
7772 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7775 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7776 the instruction. *OP is passed as the initial value of the op field, and
7777 may be set to a different value depending on the constant (i.e.
7778 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7779 MVN). If the immediate looks like a repeated pattern then also
7780 try smaller element sizes. */
7783 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7784 unsigned *immbits
, int *op
, int size
,
7785 enum neon_el_type type
)
7787 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7789 if (type
== NT_float
&& !float_p
)
7792 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7794 if (size
!= 32 || *op
== 1)
7796 *immbits
= neon_qfloat_bits (immlo
);
7802 if (neon_bits_same_in_bytes (immhi
)
7803 && neon_bits_same_in_bytes (immlo
))
7807 *immbits
= (neon_squash_bits (immhi
) << 4)
7808 | neon_squash_bits (immlo
);
7819 if (immlo
== (immlo
& 0x000000ff))
7824 else if (immlo
== (immlo
& 0x0000ff00))
7826 *immbits
= immlo
>> 8;
7829 else if (immlo
== (immlo
& 0x00ff0000))
7831 *immbits
= immlo
>> 16;
7834 else if (immlo
== (immlo
& 0xff000000))
7836 *immbits
= immlo
>> 24;
7839 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7841 *immbits
= (immlo
>> 8) & 0xff;
7844 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7846 *immbits
= (immlo
>> 16) & 0xff;
7850 if ((immlo
& 0xffff) != (immlo
>> 16))
7857 if (immlo
== (immlo
& 0x000000ff))
7862 else if (immlo
== (immlo
& 0x0000ff00))
7864 *immbits
= immlo
>> 8;
7868 if ((immlo
& 0xff) != (immlo
>> 8))
7873 if (immlo
== (immlo
& 0x000000ff))
7875 /* Don't allow MVN with 8-bit immediate. */
7885 #if defined BFD_HOST_64_BIT
7886 /* Returns TRUE if double precision value V may be cast
7887 to single precision without loss of accuracy. */
7890 is_double_a_single (bfd_int64_t v
)
7892 int exp
= (int)((v
>> 52) & 0x7FF);
7893 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7895 return (exp
== 0 || exp
== 0x7FF
7896 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7897 && (mantissa
& 0x1FFFFFFFl
) == 0;
7900 /* Returns a double precision value casted to single precision
7901 (ignoring the least significant bits in exponent and mantissa). */
7904 double_to_single (bfd_int64_t v
)
7906 int sign
= (int) ((v
>> 63) & 1l);
7907 int exp
= (int) ((v
>> 52) & 0x7FF);
7908 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7914 exp
= exp
- 1023 + 127;
7923 /* No denormalized numbers. */
7929 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7931 #endif /* BFD_HOST_64_BIT */
7940 static void do_vfp_nsyn_opcode (const char *);
7942 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7943 Determine whether it can be performed with a move instruction; if
7944 it can, convert inst.instruction to that move instruction and
7945 return TRUE; if it can't, convert inst.instruction to a literal-pool
7946 load and return FALSE. If this is not a valid thing to do in the
7947 current context, set inst.error and return TRUE.
7949 inst.operands[i] describes the destination register. */
7952 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7955 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7956 bfd_boolean arm_p
= (t
== CONST_ARM
);
7959 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7963 if ((inst
.instruction
& tbit
) == 0)
7965 inst
.error
= _("invalid pseudo operation");
7969 if (inst
.reloc
.exp
.X_op
!= O_constant
7970 && inst
.reloc
.exp
.X_op
!= O_symbol
7971 && inst
.reloc
.exp
.X_op
!= O_big
)
7973 inst
.error
= _("constant expression expected");
7977 if (inst
.reloc
.exp
.X_op
== O_constant
7978 || inst
.reloc
.exp
.X_op
== O_big
)
7980 #if defined BFD_HOST_64_BIT
7985 if (inst
.reloc
.exp
.X_op
== O_big
)
7987 LITTLENUM_TYPE w
[X_PRECISION
];
7990 if (inst
.reloc
.exp
.X_add_number
== -1)
7992 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7994 /* FIXME: Should we check words w[2..5] ? */
7999 #if defined BFD_HOST_64_BIT
8001 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8002 << LITTLENUM_NUMBER_OF_BITS
)
8003 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8004 << LITTLENUM_NUMBER_OF_BITS
)
8005 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8006 << LITTLENUM_NUMBER_OF_BITS
)
8007 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8009 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8010 | (l
[0] & LITTLENUM_MASK
);
8014 v
= inst
.reloc
.exp
.X_add_number
;
8016 if (!inst
.operands
[i
].issingle
)
8020 /* LDR should not use lead in a flag-setting instruction being
8021 chosen so we do not check whether movs can be used. */
8023 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8024 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8025 && inst
.operands
[i
].reg
!= 13
8026 && inst
.operands
[i
].reg
!= 15)
8028 /* Check if on thumb2 it can be done with a mov.w, mvn or
8029 movw instruction. */
8030 unsigned int newimm
;
8031 bfd_boolean isNegated
;
8033 newimm
= encode_thumb32_immediate (v
);
8034 if (newimm
!= (unsigned int) FAIL
)
8038 newimm
= encode_thumb32_immediate (~v
);
8039 if (newimm
!= (unsigned int) FAIL
)
8043 /* The number can be loaded with a mov.w or mvn
8045 if (newimm
!= (unsigned int) FAIL
8046 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8048 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8049 | (inst
.operands
[i
].reg
<< 8));
8050 /* Change to MOVN. */
8051 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8052 inst
.instruction
|= (newimm
& 0x800) << 15;
8053 inst
.instruction
|= (newimm
& 0x700) << 4;
8054 inst
.instruction
|= (newimm
& 0x0ff);
8057 /* The number can be loaded with a movw instruction. */
8058 else if ((v
& ~0xFFFF) == 0
8059 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8061 int imm
= v
& 0xFFFF;
8063 inst
.instruction
= 0xf2400000; /* MOVW. */
8064 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8065 inst
.instruction
|= (imm
& 0xf000) << 4;
8066 inst
.instruction
|= (imm
& 0x0800) << 15;
8067 inst
.instruction
|= (imm
& 0x0700) << 4;
8068 inst
.instruction
|= (imm
& 0x00ff);
8075 int value
= encode_arm_immediate (v
);
8079 /* This can be done with a mov instruction. */
8080 inst
.instruction
&= LITERAL_MASK
;
8081 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8082 inst
.instruction
|= value
& 0xfff;
8086 value
= encode_arm_immediate (~ v
);
8089 /* This can be done with a mvn instruction. */
8090 inst
.instruction
&= LITERAL_MASK
;
8091 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8092 inst
.instruction
|= value
& 0xfff;
8096 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8099 unsigned immbits
= 0;
8100 unsigned immlo
= inst
.operands
[1].imm
;
8101 unsigned immhi
= inst
.operands
[1].regisimm
8102 ? inst
.operands
[1].reg
8103 : inst
.reloc
.exp
.X_unsigned
8105 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8106 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8107 &op
, 64, NT_invtype
);
8111 neon_invert_size (&immlo
, &immhi
, 64);
8113 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8114 &op
, 64, NT_invtype
);
8119 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8125 /* Fill other bits in vmov encoding for both thumb and arm. */
8127 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8129 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8130 neon_write_immbits (immbits
);
8138 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8139 if (inst
.operands
[i
].issingle
8140 && is_quarter_float (inst
.operands
[1].imm
)
8141 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8143 inst
.operands
[1].imm
=
8144 neon_qfloat_bits (v
);
8145 do_vfp_nsyn_opcode ("fconsts");
8149 /* If our host does not support a 64-bit type then we cannot perform
8150 the following optimization. This mean that there will be a
8151 discrepancy between the output produced by an assembler built for
8152 a 32-bit-only host and the output produced from a 64-bit host, but
8153 this cannot be helped. */
8154 #if defined BFD_HOST_64_BIT
8155 else if (!inst
.operands
[1].issingle
8156 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8158 if (is_double_a_single (v
)
8159 && is_quarter_float (double_to_single (v
)))
8161 inst
.operands
[1].imm
=
8162 neon_qfloat_bits (double_to_single (v
));
8163 do_vfp_nsyn_opcode ("fconstd");
8171 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8172 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8175 inst
.operands
[1].reg
= REG_PC
;
8176 inst
.operands
[1].isreg
= 1;
8177 inst
.operands
[1].preind
= 1;
8178 inst
.reloc
.pc_rel
= 1;
8179 inst
.reloc
.type
= (thumb_p
8180 ? BFD_RELOC_ARM_THUMB_OFFSET
8182 ? BFD_RELOC_ARM_HWLITERAL
8183 : BFD_RELOC_ARM_LITERAL
));
8187 /* inst.operands[i] was set up by parse_address. Encode it into an
8188 ARM-format instruction. Reject all forms which cannot be encoded
8189 into a coprocessor load/store instruction. If wb_ok is false,
8190 reject use of writeback; if unind_ok is false, reject use of
8191 unindexed addressing. If reloc_override is not 0, use it instead
8192 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8193 (in which case it is preserved). */
8196 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8198 if (!inst
.operands
[i
].isreg
)
8201 if (! inst
.operands
[0].isvec
)
8203 inst
.error
= _("invalid co-processor operand");
8206 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8210 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8212 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8214 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8216 gas_assert (!inst
.operands
[i
].writeback
);
8219 inst
.error
= _("instruction does not support unindexed addressing");
8222 inst
.instruction
|= inst
.operands
[i
].imm
;
8223 inst
.instruction
|= INDEX_UP
;
8227 if (inst
.operands
[i
].preind
)
8228 inst
.instruction
|= PRE_INDEX
;
8230 if (inst
.operands
[i
].writeback
)
8232 if (inst
.operands
[i
].reg
== REG_PC
)
8234 inst
.error
= _("pc may not be used with write-back");
8239 inst
.error
= _("instruction does not support writeback");
8242 inst
.instruction
|= WRITE_BACK
;
8246 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8247 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8248 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8249 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8252 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8254 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8257 /* Prefer + for zero encoded value. */
8258 if (!inst
.operands
[i
].negative
)
8259 inst
.instruction
|= INDEX_UP
;
8264 /* Functions for instruction encoding, sorted by sub-architecture.
8265 First some generics; their names are taken from the conventional
8266 bit positions for register arguments in ARM format instructions. */
8276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8282 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8289 inst
.instruction
|= inst
.operands
[1].reg
;
8295 inst
.instruction
|= inst
.operands
[0].reg
;
8296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8309 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8310 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8316 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8321 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8323 if (ARM_CPU_IS_ANY (cpu_variant
))
8325 as_tsktsk ("%s", msg
);
8328 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8340 unsigned Rn
= inst
.operands
[2].reg
;
8341 /* Enforce restrictions on SWP instruction. */
8342 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8344 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8345 _("Rn must not overlap other operands"));
8347 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8349 if (!check_obsolete (&arm_ext_v8
,
8350 _("swp{b} use is obsoleted for ARMv8 and later"))
8351 && warn_on_deprecated
8352 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8353 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 inst
.instruction
|= inst
.operands
[1].reg
;
8358 inst
.instruction
|= Rn
<< 16;
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8365 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8366 inst
.instruction
|= inst
.operands
[2].reg
;
8372 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8373 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8374 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8375 || inst
.reloc
.exp
.X_add_number
!= 0),
8377 inst
.instruction
|= inst
.operands
[0].reg
;
8378 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8379 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8385 inst
.instruction
|= inst
.operands
[0].imm
;
8391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8392 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8395 /* ARM instructions, in alphabetical order by function name (except
8396 that wrapper functions appear immediately after the function they
8399 /* This is a pseudo-op of the form "adr rd, label" to be converted
8400 into a relative address of the form "add rd, pc, #label-.-8". */
8405 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8407 /* Frag hacking will turn this into a sub instruction if the offset turns
8408 out to be negative. */
8409 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8410 inst
.reloc
.pc_rel
= 1;
8411 inst
.reloc
.exp
.X_add_number
-= 8;
8413 if (inst
.reloc
.exp
.X_op
== O_symbol
8414 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8415 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8416 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8417 inst
.reloc
.exp
.X_add_number
+= 1;
8420 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8421 into a relative address of the form:
8422 add rd, pc, #low(label-.-8)"
8423 add rd, rd, #high(label-.-8)" */
8428 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8430 /* Frag hacking will turn this into a sub instruction if the offset turns
8431 out to be negative. */
8432 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8433 inst
.reloc
.pc_rel
= 1;
8434 inst
.size
= INSN_SIZE
* 2;
8435 inst
.reloc
.exp
.X_add_number
-= 8;
8437 if (inst
.reloc
.exp
.X_op
== O_symbol
8438 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8439 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8440 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8441 inst
.reloc
.exp
.X_add_number
+= 1;
8447 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8448 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8450 if (!inst
.operands
[1].present
)
8451 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8453 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8454 encode_arm_shifter_operand (2);
8460 if (inst
.operands
[0].present
)
8461 inst
.instruction
|= inst
.operands
[0].imm
;
8463 inst
.instruction
|= 0xf;
8469 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8470 constraint (msb
> 32, _("bit-field extends past end of register"));
8471 /* The instruction encoding stores the LSB and MSB,
8472 not the LSB and width. */
8473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8474 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8475 inst
.instruction
|= (msb
- 1) << 16;
8483 /* #0 in second position is alternative syntax for bfc, which is
8484 the same instruction but with REG_PC in the Rm field. */
8485 if (!inst
.operands
[1].isreg
)
8486 inst
.operands
[1].reg
= REG_PC
;
8488 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8489 constraint (msb
> 32, _("bit-field extends past end of register"));
8490 /* The instruction encoding stores the LSB and MSB,
8491 not the LSB and width. */
8492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8493 inst
.instruction
|= inst
.operands
[1].reg
;
8494 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8495 inst
.instruction
|= (msb
- 1) << 16;
8501 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8502 _("bit-field extends past end of register"));
8503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8504 inst
.instruction
|= inst
.operands
[1].reg
;
8505 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8506 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8509 /* ARM V5 breakpoint instruction (argument parse)
8510 BKPT <16 bit unsigned immediate>
8511 Instruction is not conditional.
8512 The bit pattern given in insns[] has the COND_ALWAYS condition,
8513 and it is an error if the caller tried to override that. */
8518 /* Top 12 of 16 bits to bits 19:8. */
8519 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8521 /* Bottom 4 of 16 bits to bits 3:0. */
8522 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8526 encode_branch (int default_reloc
)
8528 if (inst
.operands
[0].hasreloc
)
8530 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8531 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8532 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8533 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8534 ? BFD_RELOC_ARM_PLT32
8535 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8538 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8539 inst
.reloc
.pc_rel
= 1;
8546 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8547 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8550 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8557 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8559 if (inst
.cond
== COND_ALWAYS
)
8560 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8562 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8566 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8569 /* ARM V5 branch-link-exchange instruction (argument parse)
8570 BLX <target_addr> ie BLX(1)
8571 BLX{<condition>} <Rm> ie BLX(2)
8572 Unfortunately, there are two different opcodes for this mnemonic.
8573 So, the insns[].value is not used, and the code here zaps values
8574 into inst.instruction.
8575 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8580 if (inst
.operands
[0].isreg
)
8582 /* Arg is a register; the opcode provided by insns[] is correct.
8583 It is not illegal to do "blx pc", just useless. */
8584 if (inst
.operands
[0].reg
== REG_PC
)
8585 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8587 inst
.instruction
|= inst
.operands
[0].reg
;
8591 /* Arg is an address; this instruction cannot be executed
8592 conditionally, and the opcode must be adjusted.
8593 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8594 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8595 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8596 inst
.instruction
= 0xfa000000;
8597 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8604 bfd_boolean want_reloc
;
8606 if (inst
.operands
[0].reg
== REG_PC
)
8607 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8609 inst
.instruction
|= inst
.operands
[0].reg
;
8610 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8611 it is for ARMv4t or earlier. */
8612 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8613 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8617 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8622 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8626 /* ARM v5TEJ. Jump to Jazelle code. */
8631 if (inst
.operands
[0].reg
== REG_PC
)
8632 as_tsktsk (_("use of r15 in bxj is not really useful"));
8634 inst
.instruction
|= inst
.operands
[0].reg
;
8637 /* Co-processor data operation:
8638 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8639 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8644 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8645 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8646 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8647 inst
.instruction
|= inst
.operands
[4].reg
;
8648 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8655 encode_arm_shifter_operand (1);
8658 /* Transfer between coprocessor and ARM registers.
8659 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8664 No special properties. */
8666 struct deprecated_coproc_regs_s
8673 arm_feature_set deprecated
;
8674 arm_feature_set obsoleted
;
8675 const char *dep_msg
;
8676 const char *obs_msg
;
8679 #define DEPR_ACCESS_V8 \
8680 N_("This coprocessor register access is deprecated in ARMv8")
8682 /* Table of all deprecated coprocessor registers. */
8683 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8685 {15, 0, 7, 10, 5, /* CP15DMB. */
8686 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8687 DEPR_ACCESS_V8
, NULL
},
8688 {15, 0, 7, 10, 4, /* CP15DSB. */
8689 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8690 DEPR_ACCESS_V8
, NULL
},
8691 {15, 0, 7, 5, 4, /* CP15ISB. */
8692 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8693 DEPR_ACCESS_V8
, NULL
},
8694 {14, 6, 1, 0, 0, /* TEEHBR. */
8695 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8696 DEPR_ACCESS_V8
, NULL
},
8697 {14, 6, 0, 0, 0, /* TEECR. */
8698 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8699 DEPR_ACCESS_V8
, NULL
},
8702 #undef DEPR_ACCESS_V8
8704 static const size_t deprecated_coproc_reg_count
=
8705 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8713 Rd
= inst
.operands
[2].reg
;
8716 if (inst
.instruction
== 0xee000010
8717 || inst
.instruction
== 0xfe000010)
8719 reject_bad_reg (Rd
);
8720 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8722 constraint (Rd
== REG_SP
, BAD_SP
);
8727 if (inst
.instruction
== 0xe000010)
8728 constraint (Rd
== REG_PC
, BAD_PC
);
8731 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8733 const struct deprecated_coproc_regs_s
*r
=
8734 deprecated_coproc_regs
+ i
;
8736 if (inst
.operands
[0].reg
== r
->cp
8737 && inst
.operands
[1].imm
== r
->opc1
8738 && inst
.operands
[3].reg
== r
->crn
8739 && inst
.operands
[4].reg
== r
->crm
8740 && inst
.operands
[5].imm
== r
->opc2
)
8742 if (! ARM_CPU_IS_ANY (cpu_variant
)
8743 && warn_on_deprecated
8744 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8745 as_tsktsk ("%s", r
->dep_msg
);
8749 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8750 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8751 inst
.instruction
|= Rd
<< 12;
8752 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8753 inst
.instruction
|= inst
.operands
[4].reg
;
8754 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8757 /* Transfer between coprocessor register and pair of ARM registers.
8758 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8763 Two XScale instructions are special cases of these:
8765 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8766 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8768 Result unpredictable if Rd or Rn is R15. */
8775 Rd
= inst
.operands
[2].reg
;
8776 Rn
= inst
.operands
[3].reg
;
8780 reject_bad_reg (Rd
);
8781 reject_bad_reg (Rn
);
8785 constraint (Rd
== REG_PC
, BAD_PC
);
8786 constraint (Rn
== REG_PC
, BAD_PC
);
8789 /* Only check the MRRC{2} variants. */
8790 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8792 /* If Rd == Rn, error that the operation is
8793 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8794 constraint (Rd
== Rn
, BAD_OVERLAP
);
8797 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8798 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8799 inst
.instruction
|= Rd
<< 12;
8800 inst
.instruction
|= Rn
<< 16;
8801 inst
.instruction
|= inst
.operands
[4].reg
;
8807 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8808 if (inst
.operands
[1].present
)
8810 inst
.instruction
|= CPSI_MMOD
;
8811 inst
.instruction
|= inst
.operands
[1].imm
;
8818 inst
.instruction
|= inst
.operands
[0].imm
;
8824 unsigned Rd
, Rn
, Rm
;
8826 Rd
= inst
.operands
[0].reg
;
8827 Rn
= (inst
.operands
[1].present
8828 ? inst
.operands
[1].reg
: Rd
);
8829 Rm
= inst
.operands
[2].reg
;
8831 constraint ((Rd
== REG_PC
), BAD_PC
);
8832 constraint ((Rn
== REG_PC
), BAD_PC
);
8833 constraint ((Rm
== REG_PC
), BAD_PC
);
8835 inst
.instruction
|= Rd
<< 16;
8836 inst
.instruction
|= Rn
<< 0;
8837 inst
.instruction
|= Rm
<< 8;
8843 /* There is no IT instruction in ARM mode. We
8844 process it to do the validation as if in
8845 thumb mode, just in case the code gets
8846 assembled for thumb using the unified syntax. */
8851 set_it_insn_type (IT_INSN
);
8852 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8853 now_it
.cc
= inst
.operands
[0].imm
;
8857 /* If there is only one register in the register list,
8858 then return its register number. Otherwise return -1. */
8860 only_one_reg_in_list (int range
)
8862 int i
= ffs (range
) - 1;
8863 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8867 encode_ldmstm(int from_push_pop_mnem
)
8869 int base_reg
= inst
.operands
[0].reg
;
8870 int range
= inst
.operands
[1].imm
;
8873 inst
.instruction
|= base_reg
<< 16;
8874 inst
.instruction
|= range
;
8876 if (inst
.operands
[1].writeback
)
8877 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8879 if (inst
.operands
[0].writeback
)
8881 inst
.instruction
|= WRITE_BACK
;
8882 /* Check for unpredictable uses of writeback. */
8883 if (inst
.instruction
& LOAD_BIT
)
8885 /* Not allowed in LDM type 2. */
8886 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8887 && ((range
& (1 << REG_PC
)) == 0))
8888 as_warn (_("writeback of base register is UNPREDICTABLE"));
8889 /* Only allowed if base reg not in list for other types. */
8890 else if (range
& (1 << base_reg
))
8891 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8895 /* Not allowed for type 2. */
8896 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8897 as_warn (_("writeback of base register is UNPREDICTABLE"));
8898 /* Only allowed if base reg not in list, or first in list. */
8899 else if ((range
& (1 << base_reg
))
8900 && (range
& ((1 << base_reg
) - 1)))
8901 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8905 /* If PUSH/POP has only one register, then use the A2 encoding. */
8906 one_reg
= only_one_reg_in_list (range
);
8907 if (from_push_pop_mnem
&& one_reg
>= 0)
8909 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8911 if (is_push
&& one_reg
== 13 /* SP */)
8912 /* PR 22483: The A2 encoding cannot be used when
8913 pushing the stack pointer as this is UNPREDICTABLE. */
8916 inst
.instruction
&= A_COND_MASK
;
8917 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8918 inst
.instruction
|= one_reg
<< 12;
8925 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8928 /* ARMv5TE load-consecutive (argument parse)
8937 constraint (inst
.operands
[0].reg
% 2 != 0,
8938 _("first transfer register must be even"));
8939 constraint (inst
.operands
[1].present
8940 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8941 _("can only transfer two consecutive registers"));
8942 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8943 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8945 if (!inst
.operands
[1].present
)
8946 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8948 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8949 register and the first register written; we have to diagnose
8950 overlap between the base and the second register written here. */
8952 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8953 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8954 as_warn (_("base register written back, and overlaps "
8955 "second transfer register"));
8957 if (!(inst
.instruction
& V4_STR_BIT
))
8959 /* For an index-register load, the index register must not overlap the
8960 destination (even if not write-back). */
8961 if (inst
.operands
[2].immisreg
8962 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8963 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8964 as_warn (_("index register overlaps transfer register"));
8966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8967 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8973 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8974 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8975 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8976 || inst
.operands
[1].negative
8977 /* This can arise if the programmer has written
8979 or if they have mistakenly used a register name as the last
8982 It is very difficult to distinguish between these two cases
8983 because "rX" might actually be a label. ie the register
8984 name has been occluded by a symbol of the same name. So we
8985 just generate a general 'bad addressing mode' type error
8986 message and leave it up to the programmer to discover the
8987 true cause and fix their mistake. */
8988 || (inst
.operands
[1].reg
== REG_PC
),
8991 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8992 || inst
.reloc
.exp
.X_add_number
!= 0,
8993 _("offset must be zero in ARM encoding"));
8995 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8999 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9005 constraint (inst
.operands
[0].reg
% 2 != 0,
9006 _("even register required"));
9007 constraint (inst
.operands
[1].present
9008 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9009 _("can only load two consecutive registers"));
9010 /* If op 1 were present and equal to PC, this function wouldn't
9011 have been called in the first place. */
9012 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9015 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9018 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9019 which is not a multiple of four is UNPREDICTABLE. */
9021 check_ldr_r15_aligned (void)
9023 constraint (!(inst
.operands
[1].immisreg
)
9024 && (inst
.operands
[0].reg
== REG_PC
9025 && inst
.operands
[1].reg
== REG_PC
9026 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9027 _("ldr to register 15 must be 4-byte aligned"));
9033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9034 if (!inst
.operands
[1].isreg
)
9035 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9037 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9038 check_ldr_r15_aligned ();
9044 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9046 if (inst
.operands
[1].preind
)
9048 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9049 || inst
.reloc
.exp
.X_add_number
!= 0,
9050 _("this instruction requires a post-indexed address"));
9052 inst
.operands
[1].preind
= 0;
9053 inst
.operands
[1].postind
= 1;
9054 inst
.operands
[1].writeback
= 1;
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9057 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9060 /* Halfword and signed-byte load/store operations. */
9065 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9067 if (!inst
.operands
[1].isreg
)
9068 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9070 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9076 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9078 if (inst
.operands
[1].preind
)
9080 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9081 || inst
.reloc
.exp
.X_add_number
!= 0,
9082 _("this instruction requires a post-indexed address"));
9084 inst
.operands
[1].preind
= 0;
9085 inst
.operands
[1].postind
= 1;
9086 inst
.operands
[1].writeback
= 1;
9088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9089 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9092 /* Co-processor register load/store.
9093 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9097 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9098 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9099 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9105 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9106 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9107 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9108 && !(inst
.instruction
& 0x00400000))
9109 as_tsktsk (_("Rd and Rm should be different in mla"));
9111 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9112 inst
.instruction
|= inst
.operands
[1].reg
;
9113 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9114 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9120 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9121 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9124 encode_arm_shifter_operand (1);
9127 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9134 top
= (inst
.instruction
& 0x00400000) != 0;
9135 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9136 _(":lower16: not allowed in this instruction"));
9137 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9138 _(":upper16: not allowed in this instruction"));
9139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9140 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9142 imm
= inst
.reloc
.exp
.X_add_number
;
9143 /* The value is in two pieces: 0:11, 16:19. */
9144 inst
.instruction
|= (imm
& 0x00000fff);
9145 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9150 do_vfp_nsyn_mrs (void)
9152 if (inst
.operands
[0].isvec
)
9154 if (inst
.operands
[1].reg
!= 1)
9155 first_error (_("operand 1 must be FPSCR"));
9156 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9157 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9158 do_vfp_nsyn_opcode ("fmstat");
9160 else if (inst
.operands
[1].isvec
)
9161 do_vfp_nsyn_opcode ("fmrx");
9169 do_vfp_nsyn_msr (void)
9171 if (inst
.operands
[0].isvec
)
9172 do_vfp_nsyn_opcode ("fmxr");
9182 unsigned Rt
= inst
.operands
[0].reg
;
9184 if (thumb_mode
&& Rt
== REG_SP
)
9186 inst
.error
= BAD_SP
;
9190 /* MVFR2 is only valid at ARMv8-A. */
9191 if (inst
.operands
[1].reg
== 5)
9192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9195 /* APSR_ sets isvec. All other refs to PC are illegal. */
9196 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9198 inst
.error
= BAD_PC
;
9202 /* If we get through parsing the register name, we just insert the number
9203 generated into the instruction without further validation. */
9204 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9205 inst
.instruction
|= (Rt
<< 12);
9211 unsigned Rt
= inst
.operands
[1].reg
;
9214 reject_bad_reg (Rt
);
9215 else if (Rt
== REG_PC
)
9217 inst
.error
= BAD_PC
;
9221 /* MVFR2 is only valid for ARMv8-A. */
9222 if (inst
.operands
[0].reg
== 5)
9223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9226 /* If we get through parsing the register name, we just insert the number
9227 generated into the instruction without further validation. */
9228 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9229 inst
.instruction
|= (Rt
<< 12);
9237 if (do_vfp_nsyn_mrs () == SUCCESS
)
9240 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9243 if (inst
.operands
[1].isreg
)
9245 br
= inst
.operands
[1].reg
;
9246 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9247 as_bad (_("bad register for mrs"));
9251 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9252 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9254 _("'APSR', 'CPSR' or 'SPSR' expected"));
9255 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9258 inst
.instruction
|= br
;
9261 /* Two possible forms:
9262 "{C|S}PSR_<field>, Rm",
9263 "{C|S}PSR_f, #expression". */
9268 if (do_vfp_nsyn_msr () == SUCCESS
)
9271 inst
.instruction
|= inst
.operands
[0].imm
;
9272 if (inst
.operands
[1].isreg
)
9273 inst
.instruction
|= inst
.operands
[1].reg
;
9276 inst
.instruction
|= INST_IMMEDIATE
;
9277 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9278 inst
.reloc
.pc_rel
= 0;
9285 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9287 if (!inst
.operands
[2].present
)
9288 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9289 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9290 inst
.instruction
|= inst
.operands
[1].reg
;
9291 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9293 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9294 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9295 as_tsktsk (_("Rd and Rm should be different in mul"));
9298 /* Long Multiply Parser
9299 UMULL RdLo, RdHi, Rm, Rs
9300 SMULL RdLo, RdHi, Rm, Rs
9301 UMLAL RdLo, RdHi, Rm, Rs
9302 SMLAL RdLo, RdHi, Rm, Rs. */
9307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9308 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9309 inst
.instruction
|= inst
.operands
[2].reg
;
9310 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9312 /* rdhi and rdlo must be different. */
9313 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9314 as_tsktsk (_("rdhi and rdlo must be different"));
9316 /* rdhi, rdlo and rm must all be different before armv6. */
9317 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9318 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9319 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9320 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9326 if (inst
.operands
[0].present
9327 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9329 /* Architectural NOP hints are CPSR sets with no bits selected. */
9330 inst
.instruction
&= 0xf0000000;
9331 inst
.instruction
|= 0x0320f000;
9332 if (inst
.operands
[0].present
)
9333 inst
.instruction
|= inst
.operands
[0].imm
;
9337 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9338 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9339 Condition defaults to COND_ALWAYS.
9340 Error if Rd, Rn or Rm are R15. */
9345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9346 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9347 inst
.instruction
|= inst
.operands
[2].reg
;
9348 if (inst
.operands
[3].present
)
9349 encode_arm_shift (3);
9352 /* ARM V6 PKHTB (Argument Parse). */
9357 if (!inst
.operands
[3].present
)
9359 /* If the shift specifier is omitted, turn the instruction
9360 into pkhbt rd, rm, rn. */
9361 inst
.instruction
&= 0xfff00010;
9362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9363 inst
.instruction
|= inst
.operands
[1].reg
;
9364 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9369 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9370 inst
.instruction
|= inst
.operands
[2].reg
;
9371 encode_arm_shift (3);
9375 /* ARMv5TE: Preload-Cache
9376 MP Extensions: Preload for write
9380 Syntactically, like LDR with B=1, W=0, L=1. */
9385 constraint (!inst
.operands
[0].isreg
,
9386 _("'[' expected after PLD mnemonic"));
9387 constraint (inst
.operands
[0].postind
,
9388 _("post-indexed expression used in preload instruction"));
9389 constraint (inst
.operands
[0].writeback
,
9390 _("writeback used in preload instruction"));
9391 constraint (!inst
.operands
[0].preind
,
9392 _("unindexed addressing used in preload instruction"));
9393 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9396 /* ARMv7: PLI <addr_mode> */
9400 constraint (!inst
.operands
[0].isreg
,
9401 _("'[' expected after PLI mnemonic"));
9402 constraint (inst
.operands
[0].postind
,
9403 _("post-indexed expression used in preload instruction"));
9404 constraint (inst
.operands
[0].writeback
,
9405 _("writeback used in preload instruction"));
9406 constraint (!inst
.operands
[0].preind
,
9407 _("unindexed addressing used in preload instruction"));
9408 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9409 inst
.instruction
&= ~PRE_INDEX
;
9415 constraint (inst
.operands
[0].writeback
,
9416 _("push/pop do not support {reglist}^"));
9417 inst
.operands
[1] = inst
.operands
[0];
9418 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9419 inst
.operands
[0].isreg
= 1;
9420 inst
.operands
[0].writeback
= 1;
9421 inst
.operands
[0].reg
= REG_SP
;
9422 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9425 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9426 word at the specified address and the following word
9428 Unconditionally executed.
9429 Error if Rn is R15. */
9434 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9435 if (inst
.operands
[0].writeback
)
9436 inst
.instruction
|= WRITE_BACK
;
9439 /* ARM V6 ssat (argument parse). */
9444 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9445 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9446 inst
.instruction
|= inst
.operands
[2].reg
;
9448 if (inst
.operands
[3].present
)
9449 encode_arm_shift (3);
9452 /* ARM V6 usat (argument parse). */
9457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9458 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9459 inst
.instruction
|= inst
.operands
[2].reg
;
9461 if (inst
.operands
[3].present
)
9462 encode_arm_shift (3);
9465 /* ARM V6 ssat16 (argument parse). */
9470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9471 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9472 inst
.instruction
|= inst
.operands
[2].reg
;
9478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9479 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9480 inst
.instruction
|= inst
.operands
[2].reg
;
9483 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9484 preserving the other bits.
9486 setend <endian_specifier>, where <endian_specifier> is either
9492 if (warn_on_deprecated
9493 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9494 as_tsktsk (_("setend use is deprecated for ARMv8"));
9496 if (inst
.operands
[0].imm
)
9497 inst
.instruction
|= 0x200;
9503 unsigned int Rm
= (inst
.operands
[1].present
9504 ? inst
.operands
[1].reg
9505 : inst
.operands
[0].reg
);
9507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9508 inst
.instruction
|= Rm
;
9509 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9511 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9512 inst
.instruction
|= SHIFT_BY_REG
;
9513 /* PR 12854: Error on extraneous shifts. */
9514 constraint (inst
.operands
[2].shifted
,
9515 _("extraneous shift as part of operand to shift insn"));
9518 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9524 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9525 inst
.reloc
.pc_rel
= 0;
9531 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9532 inst
.reloc
.pc_rel
= 0;
9538 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9539 inst
.reloc
.pc_rel
= 0;
9545 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9546 _("selected processor does not support SETPAN instruction"));
9548 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9554 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9555 _("selected processor does not support SETPAN instruction"));
9557 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9560 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9561 SMLAxy{cond} Rd,Rm,Rs,Rn
9562 SMLAWy{cond} Rd,Rm,Rs,Rn
9563 Error if any register is R15. */
9568 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9569 inst
.instruction
|= inst
.operands
[1].reg
;
9570 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9571 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9574 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9575 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9576 Error if any register is R15.
9577 Warning if Rdlo == Rdhi. */
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9583 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9584 inst
.instruction
|= inst
.operands
[2].reg
;
9585 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9587 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9588 as_tsktsk (_("rdhi and rdlo must be different"));
9591 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9592 SMULxy{cond} Rd,Rm,Rs
9593 Error if any register is R15. */
9598 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9599 inst
.instruction
|= inst
.operands
[1].reg
;
9600 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9603 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9604 the same for both ARM and Thumb-2. */
9611 if (inst
.operands
[0].present
)
9613 reg
= inst
.operands
[0].reg
;
9614 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9619 inst
.instruction
|= reg
<< 16;
9620 inst
.instruction
|= inst
.operands
[1].imm
;
9621 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9622 inst
.instruction
|= WRITE_BACK
;
9625 /* ARM V6 strex (argument parse). */
9630 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9631 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9632 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9633 || inst
.operands
[2].negative
9634 /* See comment in do_ldrex(). */
9635 || (inst
.operands
[2].reg
== REG_PC
),
9638 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9639 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9641 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9642 || inst
.reloc
.exp
.X_add_number
!= 0,
9643 _("offset must be zero in ARM encoding"));
9645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9646 inst
.instruction
|= inst
.operands
[1].reg
;
9647 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9648 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9654 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9655 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9656 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9657 || inst
.operands
[2].negative
,
9660 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9661 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9669 constraint (inst
.operands
[1].reg
% 2 != 0,
9670 _("even register required"));
9671 constraint (inst
.operands
[2].present
9672 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9673 _("can only store two consecutive registers"));
9674 /* If op 2 were present and equal to PC, this function wouldn't
9675 have been called in the first place. */
9676 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9678 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9679 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9680 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9683 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9684 inst
.instruction
|= inst
.operands
[1].reg
;
9685 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9692 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9693 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9701 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9702 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9707 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9708 extends it to 32-bits, and adds the result to a value in another
9709 register. You can specify a rotation by 0, 8, 16, or 24 bits
9710 before extracting the 16-bit value.
9711 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9712 Condition defaults to COND_ALWAYS.
9713 Error if any register uses R15. */
9718 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9719 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9720 inst
.instruction
|= inst
.operands
[2].reg
;
9721 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9726 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9727 Condition defaults to COND_ALWAYS.
9728 Error if any register uses R15. */
9733 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9734 inst
.instruction
|= inst
.operands
[1].reg
;
9735 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9738 /* VFP instructions. In a logical order: SP variant first, monad
9739 before dyad, arithmetic then move then load/store. */
9742 do_vfp_sp_monadic (void)
9744 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9745 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9749 do_vfp_sp_dyadic (void)
9751 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9752 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9753 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9757 do_vfp_sp_compare_z (void)
9759 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9763 do_vfp_dp_sp_cvt (void)
9765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9766 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9770 do_vfp_sp_dp_cvt (void)
9772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9777 do_vfp_reg_from_sp (void)
9779 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9780 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9784 do_vfp_reg2_from_sp2 (void)
9786 constraint (inst
.operands
[2].imm
!= 2,
9787 _("only two consecutive VFP SP registers allowed here"));
9788 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9789 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9790 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9794 do_vfp_sp_from_reg (void)
9796 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9797 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9801 do_vfp_sp2_from_reg2 (void)
9803 constraint (inst
.operands
[0].imm
!= 2,
9804 _("only two consecutive VFP SP registers allowed here"));
9805 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9806 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9807 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9811 do_vfp_sp_ldst (void)
9813 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9814 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9818 do_vfp_dp_ldst (void)
9820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9821 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9826 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9828 if (inst
.operands
[0].writeback
)
9829 inst
.instruction
|= WRITE_BACK
;
9831 constraint (ldstm_type
!= VFP_LDSTMIA
,
9832 _("this addressing mode requires base-register writeback"));
9833 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9834 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9835 inst
.instruction
|= inst
.operands
[1].imm
;
9839 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9843 if (inst
.operands
[0].writeback
)
9844 inst
.instruction
|= WRITE_BACK
;
9846 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9847 _("this addressing mode requires base-register writeback"));
9849 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9850 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9852 count
= inst
.operands
[1].imm
<< 1;
9853 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9856 inst
.instruction
|= count
;
9860 do_vfp_sp_ldstmia (void)
9862 vfp_sp_ldstm (VFP_LDSTMIA
);
9866 do_vfp_sp_ldstmdb (void)
9868 vfp_sp_ldstm (VFP_LDSTMDB
);
9872 do_vfp_dp_ldstmia (void)
9874 vfp_dp_ldstm (VFP_LDSTMIA
);
9878 do_vfp_dp_ldstmdb (void)
9880 vfp_dp_ldstm (VFP_LDSTMDB
);
9884 do_vfp_xp_ldstmia (void)
9886 vfp_dp_ldstm (VFP_LDSTMIAX
);
9890 do_vfp_xp_ldstmdb (void)
9892 vfp_dp_ldstm (VFP_LDSTMDBX
);
9896 do_vfp_dp_rd_rm (void)
9898 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9899 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9903 do_vfp_dp_rn_rd (void)
9905 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9906 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9910 do_vfp_dp_rd_rn (void)
9912 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9913 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9917 do_vfp_dp_rd_rn_rm (void)
9919 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9920 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9921 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9927 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9931 do_vfp_dp_rm_rd_rn (void)
9933 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9934 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9935 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9938 /* VFPv3 instructions. */
9940 do_vfp_sp_const (void)
9942 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9943 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9944 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9948 do_vfp_dp_const (void)
9950 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9951 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9952 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9956 vfp_conv (int srcsize
)
9958 int immbits
= srcsize
- inst
.operands
[1].imm
;
9960 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9962 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9963 i.e. immbits must be in range 0 - 16. */
9964 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9967 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9969 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9970 i.e. immbits must be in range 0 - 31. */
9971 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9975 inst
.instruction
|= (immbits
& 1) << 5;
9976 inst
.instruction
|= (immbits
>> 1);
9980 do_vfp_sp_conv_16 (void)
9982 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9987 do_vfp_dp_conv_16 (void)
9989 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9994 do_vfp_sp_conv_32 (void)
9996 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10001 do_vfp_dp_conv_32 (void)
10003 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10007 /* FPA instructions. Also in a logical order. */
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10013 inst
.instruction
|= inst
.operands
[1].reg
;
10017 do_fpa_ldmstm (void)
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10020 switch (inst
.operands
[1].imm
)
10022 case 1: inst
.instruction
|= CP_T_X
; break;
10023 case 2: inst
.instruction
|= CP_T_Y
; break;
10024 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10029 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10031 /* The instruction specified "ea" or "fd", so we can only accept
10032 [Rn]{!}. The instruction does not really support stacking or
10033 unstacking, so we have to emulate these by setting appropriate
10034 bits and offsets. */
10035 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10036 || inst
.reloc
.exp
.X_add_number
!= 0,
10037 _("this instruction does not support indexing"));
10039 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10040 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10042 if (!(inst
.instruction
& INDEX_UP
))
10043 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10045 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10047 inst
.operands
[2].preind
= 0;
10048 inst
.operands
[2].postind
= 1;
10052 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10055 /* iWMMXt instructions: strictly in alphabetical order. */
10058 do_iwmmxt_tandorc (void)
10060 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10064 do_iwmmxt_textrc (void)
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10067 inst
.instruction
|= inst
.operands
[1].imm
;
10071 do_iwmmxt_textrm (void)
10073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10074 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10075 inst
.instruction
|= inst
.operands
[2].imm
;
10079 do_iwmmxt_tinsr (void)
10081 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10082 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10083 inst
.instruction
|= inst
.operands
[2].imm
;
10087 do_iwmmxt_tmia (void)
10089 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10090 inst
.instruction
|= inst
.operands
[1].reg
;
10091 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10095 do_iwmmxt_waligni (void)
10097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10099 inst
.instruction
|= inst
.operands
[2].reg
;
10100 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10104 do_iwmmxt_wmerge (void)
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10108 inst
.instruction
|= inst
.operands
[2].reg
;
10109 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10113 do_iwmmxt_wmov (void)
10115 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10118 inst
.instruction
|= inst
.operands
[1].reg
;
10122 do_iwmmxt_wldstbh (void)
10125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10127 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10129 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10130 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10134 do_iwmmxt_wldstw (void)
10136 /* RIWR_RIWC clears .isreg for a control register. */
10137 if (!inst
.operands
[0].isreg
)
10139 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10140 inst
.instruction
|= 0xf0000000;
10143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10144 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10148 do_iwmmxt_wldstd (void)
10150 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10151 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10152 && inst
.operands
[1].immisreg
)
10154 inst
.instruction
&= ~0x1a000ff;
10155 inst
.instruction
|= (0xfU
<< 28);
10156 if (inst
.operands
[1].preind
)
10157 inst
.instruction
|= PRE_INDEX
;
10158 if (!inst
.operands
[1].negative
)
10159 inst
.instruction
|= INDEX_UP
;
10160 if (inst
.operands
[1].writeback
)
10161 inst
.instruction
|= WRITE_BACK
;
10162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10163 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10164 inst
.instruction
|= inst
.operands
[1].imm
;
10167 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10171 do_iwmmxt_wshufh (void)
10173 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10174 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10175 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10176 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10180 do_iwmmxt_wzero (void)
10182 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10183 inst
.instruction
|= inst
.operands
[0].reg
;
10184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10189 do_iwmmxt_wrwrwr_or_imm5 (void)
10191 if (inst
.operands
[2].isreg
)
10194 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10195 _("immediate operand requires iWMMXt2"));
10197 if (inst
.operands
[2].imm
== 0)
10199 switch ((inst
.instruction
>> 20) & 0xf)
10205 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10206 inst
.operands
[2].imm
= 16;
10207 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10213 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10214 inst
.operands
[2].imm
= 32;
10215 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10222 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10224 wrn
= (inst
.instruction
>> 16) & 0xf;
10225 inst
.instruction
&= 0xff0fff0f;
10226 inst
.instruction
|= wrn
;
10227 /* Bail out here; the instruction is now assembled. */
10232 /* Map 32 -> 0, etc. */
10233 inst
.operands
[2].imm
&= 0x1f;
10234 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10238 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10239 operations first, then control, shift, and load/store. */
10241 /* Insns like "foo X,Y,Z". */
10244 do_mav_triple (void)
10246 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10247 inst
.instruction
|= inst
.operands
[1].reg
;
10248 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10251 /* Insns like "foo W,X,Y,Z".
10252 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10257 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10258 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10259 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10260 inst
.instruction
|= inst
.operands
[3].reg
;
10263 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10265 do_mav_dspsc (void)
10267 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10270 /* Maverick shift immediate instructions.
10271 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10272 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10275 do_mav_shift (void)
10277 int imm
= inst
.operands
[2].imm
;
10279 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10280 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10282 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10283 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10284 Bit 4 should be 0. */
10285 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10287 inst
.instruction
|= imm
;
10290 /* XScale instructions. Also sorted arithmetic before move. */
10292 /* Xscale multiply-accumulate (argument parse)
10295 MIAxycc acc0,Rm,Rs. */
10300 inst
.instruction
|= inst
.operands
[1].reg
;
10301 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10304 /* Xscale move-accumulator-register (argument parse)
10306 MARcc acc0,RdLo,RdHi. */
10311 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10312 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10315 /* Xscale move-register-accumulator (argument parse)
10317 MRAcc RdLo,RdHi,acc0. */
10322 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10323 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10324 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10327 /* Encoding functions relevant only to Thumb. */
10329 /* inst.operands[i] is a shifted-register operand; encode
10330 it into inst.instruction in the format used by Thumb32. */
10333 encode_thumb32_shifted_operand (int i
)
10335 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10336 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10338 constraint (inst
.operands
[i
].immisreg
,
10339 _("shift by register not allowed in thumb mode"));
10340 inst
.instruction
|= inst
.operands
[i
].reg
;
10341 if (shift
== SHIFT_RRX
)
10342 inst
.instruction
|= SHIFT_ROR
<< 4;
10345 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10346 _("expression too complex"));
10348 constraint (value
> 32
10349 || (value
== 32 && (shift
== SHIFT_LSL
10350 || shift
== SHIFT_ROR
)),
10351 _("shift expression is too large"));
10355 else if (value
== 32)
10358 inst
.instruction
|= shift
<< 4;
10359 inst
.instruction
|= (value
& 0x1c) << 10;
10360 inst
.instruction
|= (value
& 0x03) << 6;
10365 /* inst.operands[i] was set up by parse_address. Encode it into a
10366 Thumb32 format load or store instruction. Reject forms that cannot
10367 be used with such instructions. If is_t is true, reject forms that
10368 cannot be used with a T instruction; if is_d is true, reject forms
10369 that cannot be used with a D instruction. If it is a store insn,
10370 reject PC in Rn. */
10373 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10375 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10377 constraint (!inst
.operands
[i
].isreg
,
10378 _("Instruction does not support =N addresses"));
10380 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10381 if (inst
.operands
[i
].immisreg
)
10383 constraint (is_pc
, BAD_PC_ADDRESSING
);
10384 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10385 constraint (inst
.operands
[i
].negative
,
10386 _("Thumb does not support negative register indexing"));
10387 constraint (inst
.operands
[i
].postind
,
10388 _("Thumb does not support register post-indexing"));
10389 constraint (inst
.operands
[i
].writeback
,
10390 _("Thumb does not support register indexing with writeback"));
10391 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10392 _("Thumb supports only LSL in shifted register indexing"));
10394 inst
.instruction
|= inst
.operands
[i
].imm
;
10395 if (inst
.operands
[i
].shifted
)
10397 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10398 _("expression too complex"));
10399 constraint (inst
.reloc
.exp
.X_add_number
< 0
10400 || inst
.reloc
.exp
.X_add_number
> 3,
10401 _("shift out of range"));
10402 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10404 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10406 else if (inst
.operands
[i
].preind
)
10408 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10409 constraint (is_t
&& inst
.operands
[i
].writeback
,
10410 _("cannot use writeback with this instruction"));
10411 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10412 BAD_PC_ADDRESSING
);
10416 inst
.instruction
|= 0x01000000;
10417 if (inst
.operands
[i
].writeback
)
10418 inst
.instruction
|= 0x00200000;
10422 inst
.instruction
|= 0x00000c00;
10423 if (inst
.operands
[i
].writeback
)
10424 inst
.instruction
|= 0x00000100;
10426 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10428 else if (inst
.operands
[i
].postind
)
10430 gas_assert (inst
.operands
[i
].writeback
);
10431 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10432 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10435 inst
.instruction
|= 0x00200000;
10437 inst
.instruction
|= 0x00000900;
10438 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10440 else /* unindexed - only for coprocessor */
10441 inst
.error
= _("instruction does not accept unindexed addressing");
10444 /* Table of Thumb instructions which exist in both 16- and 32-bit
10445 encodings (the latter only in post-V6T2 cores). The index is the
10446 value used in the insns table below. When there is more than one
10447 possible 16-bit encoding for the instruction, this table always
10449 Also contains several pseudo-instructions used during relaxation. */
10450 #define T16_32_TAB \
10451 X(_adc, 4140, eb400000), \
10452 X(_adcs, 4140, eb500000), \
10453 X(_add, 1c00, eb000000), \
10454 X(_adds, 1c00, eb100000), \
10455 X(_addi, 0000, f1000000), \
10456 X(_addis, 0000, f1100000), \
10457 X(_add_pc,000f, f20f0000), \
10458 X(_add_sp,000d, f10d0000), \
10459 X(_adr, 000f, f20f0000), \
10460 X(_and, 4000, ea000000), \
10461 X(_ands, 4000, ea100000), \
10462 X(_asr, 1000, fa40f000), \
10463 X(_asrs, 1000, fa50f000), \
10464 X(_b, e000, f000b000), \
10465 X(_bcond, d000, f0008000), \
10466 X(_bic, 4380, ea200000), \
10467 X(_bics, 4380, ea300000), \
10468 X(_cmn, 42c0, eb100f00), \
10469 X(_cmp, 2800, ebb00f00), \
10470 X(_cpsie, b660, f3af8400), \
10471 X(_cpsid, b670, f3af8600), \
10472 X(_cpy, 4600, ea4f0000), \
10473 X(_dec_sp,80dd, f1ad0d00), \
10474 X(_eor, 4040, ea800000), \
10475 X(_eors, 4040, ea900000), \
10476 X(_inc_sp,00dd, f10d0d00), \
10477 X(_ldmia, c800, e8900000), \
10478 X(_ldr, 6800, f8500000), \
10479 X(_ldrb, 7800, f8100000), \
10480 X(_ldrh, 8800, f8300000), \
10481 X(_ldrsb, 5600, f9100000), \
10482 X(_ldrsh, 5e00, f9300000), \
10483 X(_ldr_pc,4800, f85f0000), \
10484 X(_ldr_pc2,4800, f85f0000), \
10485 X(_ldr_sp,9800, f85d0000), \
10486 X(_lsl, 0000, fa00f000), \
10487 X(_lsls, 0000, fa10f000), \
10488 X(_lsr, 0800, fa20f000), \
10489 X(_lsrs, 0800, fa30f000), \
10490 X(_mov, 2000, ea4f0000), \
10491 X(_movs, 2000, ea5f0000), \
10492 X(_mul, 4340, fb00f000), \
10493 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10494 X(_mvn, 43c0, ea6f0000), \
10495 X(_mvns, 43c0, ea7f0000), \
10496 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10497 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10498 X(_orr, 4300, ea400000), \
10499 X(_orrs, 4300, ea500000), \
10500 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10501 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10502 X(_rev, ba00, fa90f080), \
10503 X(_rev16, ba40, fa90f090), \
10504 X(_revsh, bac0, fa90f0b0), \
10505 X(_ror, 41c0, fa60f000), \
10506 X(_rors, 41c0, fa70f000), \
10507 X(_sbc, 4180, eb600000), \
10508 X(_sbcs, 4180, eb700000), \
10509 X(_stmia, c000, e8800000), \
10510 X(_str, 6000, f8400000), \
10511 X(_strb, 7000, f8000000), \
10512 X(_strh, 8000, f8200000), \
10513 X(_str_sp,9000, f84d0000), \
10514 X(_sub, 1e00, eba00000), \
10515 X(_subs, 1e00, ebb00000), \
10516 X(_subi, 8000, f1a00000), \
10517 X(_subis, 8000, f1b00000), \
10518 X(_sxtb, b240, fa4ff080), \
10519 X(_sxth, b200, fa0ff080), \
10520 X(_tst, 4200, ea100f00), \
10521 X(_uxtb, b2c0, fa5ff080), \
10522 X(_uxth, b280, fa1ff080), \
10523 X(_nop, bf00, f3af8000), \
10524 X(_yield, bf10, f3af8001), \
10525 X(_wfe, bf20, f3af8002), \
10526 X(_wfi, bf30, f3af8003), \
10527 X(_sev, bf40, f3af8004), \
10528 X(_sevl, bf50, f3af8005), \
10529 X(_udf, de00, f7f0a000)
10531 /* To catch errors in encoding functions, the codes are all offset by
10532 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10533 as 16-bit instructions. */
10534 #define X(a,b,c) T_MNEM##a
10535 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10538 #define X(a,b,c) 0x##b
10539 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10540 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10543 #define X(a,b,c) 0x##c
10544 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10545 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10546 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10550 /* Thumb instruction encoders, in alphabetical order. */
10552 /* ADDW or SUBW. */
10555 do_t_add_sub_w (void)
10559 Rd
= inst
.operands
[0].reg
;
10560 Rn
= inst
.operands
[1].reg
;
10562 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10563 is the SP-{plus,minus}-immediate form of the instruction. */
10565 constraint (Rd
== REG_PC
, BAD_PC
);
10567 reject_bad_reg (Rd
);
10569 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10570 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10573 /* Parse an add or subtract instruction. We get here with inst.instruction
10574 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10577 do_t_add_sub (void)
10581 Rd
= inst
.operands
[0].reg
;
10582 Rs
= (inst
.operands
[1].present
10583 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10584 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10587 set_it_insn_type_last ();
10589 if (unified_syntax
)
10592 bfd_boolean narrow
;
10595 flags
= (inst
.instruction
== T_MNEM_adds
10596 || inst
.instruction
== T_MNEM_subs
);
10598 narrow
= !in_it_block ();
10600 narrow
= in_it_block ();
10601 if (!inst
.operands
[2].isreg
)
10605 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10606 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10608 add
= (inst
.instruction
== T_MNEM_add
10609 || inst
.instruction
== T_MNEM_adds
);
10611 if (inst
.size_req
!= 4)
10613 /* Attempt to use a narrow opcode, with relaxation if
10615 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10616 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10617 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10618 opcode
= T_MNEM_add_sp
;
10619 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10620 opcode
= T_MNEM_add_pc
;
10621 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10624 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10626 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10630 inst
.instruction
= THUMB_OP16(opcode
);
10631 inst
.instruction
|= (Rd
<< 4) | Rs
;
10632 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10633 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10635 if (inst
.size_req
== 2)
10636 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10638 inst
.relax
= opcode
;
10642 constraint (inst
.size_req
== 2, BAD_HIREG
);
10644 if (inst
.size_req
== 4
10645 || (inst
.size_req
!= 2 && !opcode
))
10647 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10648 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10649 THUMB1_RELOC_ONLY
);
10652 constraint (add
, BAD_PC
);
10653 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10654 _("only SUBS PC, LR, #const allowed"));
10655 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10656 _("expression too complex"));
10657 constraint (inst
.reloc
.exp
.X_add_number
< 0
10658 || inst
.reloc
.exp
.X_add_number
> 0xff,
10659 _("immediate value out of range"));
10660 inst
.instruction
= T2_SUBS_PC_LR
10661 | inst
.reloc
.exp
.X_add_number
;
10662 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10665 else if (Rs
== REG_PC
)
10667 /* Always use addw/subw. */
10668 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10669 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10673 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10674 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10677 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10679 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10681 inst
.instruction
|= Rd
<< 8;
10682 inst
.instruction
|= Rs
<< 16;
10687 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10688 unsigned int shift
= inst
.operands
[2].shift_kind
;
10690 Rn
= inst
.operands
[2].reg
;
10691 /* See if we can do this with a 16-bit instruction. */
10692 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10694 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10699 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10700 || inst
.instruction
== T_MNEM_add
)
10702 : T_OPCODE_SUB_R3
);
10703 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10707 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10709 /* Thumb-1 cores (except v6-M) require at least one high
10710 register in a narrow non flag setting add. */
10711 if (Rd
> 7 || Rn
> 7
10712 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10713 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10720 inst
.instruction
= T_OPCODE_ADD_HI
;
10721 inst
.instruction
|= (Rd
& 8) << 4;
10722 inst
.instruction
|= (Rd
& 7);
10723 inst
.instruction
|= Rn
<< 3;
10729 constraint (Rd
== REG_PC
, BAD_PC
);
10730 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10731 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10732 constraint (Rs
== REG_PC
, BAD_PC
);
10733 reject_bad_reg (Rn
);
10735 /* If we get here, it can't be done in 16 bits. */
10736 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10737 _("shift must be constant"));
10738 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10739 inst
.instruction
|= Rd
<< 8;
10740 inst
.instruction
|= Rs
<< 16;
10741 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10742 _("shift value over 3 not allowed in thumb mode"));
10743 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10744 _("only LSL shift allowed in thumb mode"));
10745 encode_thumb32_shifted_operand (2);
10750 constraint (inst
.instruction
== T_MNEM_adds
10751 || inst
.instruction
== T_MNEM_subs
,
10754 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10756 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10757 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10760 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10761 ? 0x0000 : 0x8000);
10762 inst
.instruction
|= (Rd
<< 4) | Rs
;
10763 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10767 Rn
= inst
.operands
[2].reg
;
10768 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10770 /* We now have Rd, Rs, and Rn set to registers. */
10771 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10773 /* Can't do this for SUB. */
10774 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10775 inst
.instruction
= T_OPCODE_ADD_HI
;
10776 inst
.instruction
|= (Rd
& 8) << 4;
10777 inst
.instruction
|= (Rd
& 7);
10779 inst
.instruction
|= Rn
<< 3;
10781 inst
.instruction
|= Rs
<< 3;
10783 constraint (1, _("dest must overlap one source register"));
10787 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10788 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10789 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10799 Rd
= inst
.operands
[0].reg
;
10800 reject_bad_reg (Rd
);
10802 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10804 /* Defer to section relaxation. */
10805 inst
.relax
= inst
.instruction
;
10806 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10807 inst
.instruction
|= Rd
<< 4;
10809 else if (unified_syntax
&& inst
.size_req
!= 2)
10811 /* Generate a 32-bit opcode. */
10812 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10813 inst
.instruction
|= Rd
<< 8;
10814 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10815 inst
.reloc
.pc_rel
= 1;
10819 /* Generate a 16-bit opcode. */
10820 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10822 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10823 inst
.reloc
.pc_rel
= 1;
10824 inst
.instruction
|= Rd
<< 4;
10827 if (inst
.reloc
.exp
.X_op
== O_symbol
10828 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10829 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10830 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10831 inst
.reloc
.exp
.X_add_number
+= 1;
10834 /* Arithmetic instructions for which there is just one 16-bit
10835 instruction encoding, and it allows only two low registers.
10836 For maximal compatibility with ARM syntax, we allow three register
10837 operands even when Thumb-32 instructions are not available, as long
10838 as the first two are identical. For instance, both "sbc r0,r1" and
10839 "sbc r0,r0,r1" are allowed. */
10845 Rd
= inst
.operands
[0].reg
;
10846 Rs
= (inst
.operands
[1].present
10847 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10848 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10849 Rn
= inst
.operands
[2].reg
;
10851 reject_bad_reg (Rd
);
10852 reject_bad_reg (Rs
);
10853 if (inst
.operands
[2].isreg
)
10854 reject_bad_reg (Rn
);
10856 if (unified_syntax
)
10858 if (!inst
.operands
[2].isreg
)
10860 /* For an immediate, we always generate a 32-bit opcode;
10861 section relaxation will shrink it later if possible. */
10862 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10863 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10864 inst
.instruction
|= Rd
<< 8;
10865 inst
.instruction
|= Rs
<< 16;
10866 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10870 bfd_boolean narrow
;
10872 /* See if we can do this with a 16-bit instruction. */
10873 if (THUMB_SETS_FLAGS (inst
.instruction
))
10874 narrow
= !in_it_block ();
10876 narrow
= in_it_block ();
10878 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10880 if (inst
.operands
[2].shifted
)
10882 if (inst
.size_req
== 4)
10888 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10889 inst
.instruction
|= Rd
;
10890 inst
.instruction
|= Rn
<< 3;
10894 /* If we get here, it can't be done in 16 bits. */
10895 constraint (inst
.operands
[2].shifted
10896 && inst
.operands
[2].immisreg
,
10897 _("shift must be constant"));
10898 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10899 inst
.instruction
|= Rd
<< 8;
10900 inst
.instruction
|= Rs
<< 16;
10901 encode_thumb32_shifted_operand (2);
10906 /* On its face this is a lie - the instruction does set the
10907 flags. However, the only supported mnemonic in this mode
10908 says it doesn't. */
10909 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10911 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10912 _("unshifted register required"));
10913 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10914 constraint (Rd
!= Rs
,
10915 _("dest and source1 must be the same register"));
10917 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10918 inst
.instruction
|= Rd
;
10919 inst
.instruction
|= Rn
<< 3;
10923 /* Similarly, but for instructions where the arithmetic operation is
10924 commutative, so we can allow either of them to be different from
10925 the destination operand in a 16-bit instruction. For instance, all
10926 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10933 Rd
= inst
.operands
[0].reg
;
10934 Rs
= (inst
.operands
[1].present
10935 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10936 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10937 Rn
= inst
.operands
[2].reg
;
10939 reject_bad_reg (Rd
);
10940 reject_bad_reg (Rs
);
10941 if (inst
.operands
[2].isreg
)
10942 reject_bad_reg (Rn
);
10944 if (unified_syntax
)
10946 if (!inst
.operands
[2].isreg
)
10948 /* For an immediate, we always generate a 32-bit opcode;
10949 section relaxation will shrink it later if possible. */
10950 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10951 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10952 inst
.instruction
|= Rd
<< 8;
10953 inst
.instruction
|= Rs
<< 16;
10954 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10958 bfd_boolean narrow
;
10960 /* See if we can do this with a 16-bit instruction. */
10961 if (THUMB_SETS_FLAGS (inst
.instruction
))
10962 narrow
= !in_it_block ();
10964 narrow
= in_it_block ();
10966 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10968 if (inst
.operands
[2].shifted
)
10970 if (inst
.size_req
== 4)
10977 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10978 inst
.instruction
|= Rd
;
10979 inst
.instruction
|= Rn
<< 3;
10984 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10985 inst
.instruction
|= Rd
;
10986 inst
.instruction
|= Rs
<< 3;
10991 /* If we get here, it can't be done in 16 bits. */
10992 constraint (inst
.operands
[2].shifted
10993 && inst
.operands
[2].immisreg
,
10994 _("shift must be constant"));
10995 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10996 inst
.instruction
|= Rd
<< 8;
10997 inst
.instruction
|= Rs
<< 16;
10998 encode_thumb32_shifted_operand (2);
11003 /* On its face this is a lie - the instruction does set the
11004 flags. However, the only supported mnemonic in this mode
11005 says it doesn't. */
11006 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11008 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11009 _("unshifted register required"));
11010 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11012 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11013 inst
.instruction
|= Rd
;
11016 inst
.instruction
|= Rn
<< 3;
11018 inst
.instruction
|= Rs
<< 3;
11020 constraint (1, _("dest must overlap one source register"));
11028 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11029 constraint (msb
> 32, _("bit-field extends past end of register"));
11030 /* The instruction encoding stores the LSB and MSB,
11031 not the LSB and width. */
11032 Rd
= inst
.operands
[0].reg
;
11033 reject_bad_reg (Rd
);
11034 inst
.instruction
|= Rd
<< 8;
11035 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11036 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11037 inst
.instruction
|= msb
- 1;
11046 Rd
= inst
.operands
[0].reg
;
11047 reject_bad_reg (Rd
);
11049 /* #0 in second position is alternative syntax for bfc, which is
11050 the same instruction but with REG_PC in the Rm field. */
11051 if (!inst
.operands
[1].isreg
)
11055 Rn
= inst
.operands
[1].reg
;
11056 reject_bad_reg (Rn
);
11059 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11060 constraint (msb
> 32, _("bit-field extends past end of register"));
11061 /* The instruction encoding stores the LSB and MSB,
11062 not the LSB and width. */
11063 inst
.instruction
|= Rd
<< 8;
11064 inst
.instruction
|= Rn
<< 16;
11065 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11066 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11067 inst
.instruction
|= msb
- 1;
11075 Rd
= inst
.operands
[0].reg
;
11076 Rn
= inst
.operands
[1].reg
;
11078 reject_bad_reg (Rd
);
11079 reject_bad_reg (Rn
);
11081 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11082 _("bit-field extends past end of register"));
11083 inst
.instruction
|= Rd
<< 8;
11084 inst
.instruction
|= Rn
<< 16;
11085 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11086 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11087 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11090 /* ARM V5 Thumb BLX (argument parse)
11091 BLX <target_addr> which is BLX(1)
11092 BLX <Rm> which is BLX(2)
11093 Unfortunately, there are two different opcodes for this mnemonic.
11094 So, the insns[].value is not used, and the code here zaps values
11095 into inst.instruction.
11097 ??? How to take advantage of the additional two bits of displacement
11098 available in Thumb32 mode? Need new relocation? */
11103 set_it_insn_type_last ();
11105 if (inst
.operands
[0].isreg
)
11107 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11108 /* We have a register, so this is BLX(2). */
11109 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11113 /* No register. This must be BLX(1). */
11114 inst
.instruction
= 0xf000e800;
11115 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11124 bfd_reloc_code_real_type reloc
;
11127 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11129 if (in_it_block ())
11131 /* Conditional branches inside IT blocks are encoded as unconditional
11133 cond
= COND_ALWAYS
;
11138 if (cond
!= COND_ALWAYS
)
11139 opcode
= T_MNEM_bcond
;
11141 opcode
= inst
.instruction
;
11144 && (inst
.size_req
== 4
11145 || (inst
.size_req
!= 2
11146 && (inst
.operands
[0].hasreloc
11147 || inst
.reloc
.exp
.X_op
== O_constant
))))
11149 inst
.instruction
= THUMB_OP32(opcode
);
11150 if (cond
== COND_ALWAYS
)
11151 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11155 _("selected architecture does not support "
11156 "wide conditional branch instruction"));
11158 gas_assert (cond
!= 0xF);
11159 inst
.instruction
|= cond
<< 22;
11160 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11165 inst
.instruction
= THUMB_OP16(opcode
);
11166 if (cond
== COND_ALWAYS
)
11167 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11170 inst
.instruction
|= cond
<< 8;
11171 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11173 /* Allow section relaxation. */
11174 if (unified_syntax
&& inst
.size_req
!= 2)
11175 inst
.relax
= opcode
;
11177 inst
.reloc
.type
= reloc
;
11178 inst
.reloc
.pc_rel
= 1;
11181 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11182 between the two is the maximum immediate allowed - which is passed in
11185 do_t_bkpt_hlt1 (int range
)
11187 constraint (inst
.cond
!= COND_ALWAYS
,
11188 _("instruction is always unconditional"));
11189 if (inst
.operands
[0].present
)
11191 constraint (inst
.operands
[0].imm
> range
,
11192 _("immediate value out of range"));
11193 inst
.instruction
|= inst
.operands
[0].imm
;
11196 set_it_insn_type (NEUTRAL_IT_INSN
);
11202 do_t_bkpt_hlt1 (63);
11208 do_t_bkpt_hlt1 (255);
11212 do_t_branch23 (void)
11214 set_it_insn_type_last ();
11215 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11217 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11218 this file. We used to simply ignore the PLT reloc type here --
11219 the branch encoding is now needed to deal with TLSCALL relocs.
11220 So if we see a PLT reloc now, put it back to how it used to be to
11221 keep the preexisting behaviour. */
11222 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11223 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11225 #if defined(OBJ_COFF)
11226 /* If the destination of the branch is a defined symbol which does not have
11227 the THUMB_FUNC attribute, then we must be calling a function which has
11228 the (interfacearm) attribute. We look for the Thumb entry point to that
11229 function and change the branch to refer to that function instead. */
11230 if ( inst
.reloc
.exp
.X_op
== O_symbol
11231 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11232 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11233 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11234 inst
.reloc
.exp
.X_add_symbol
=
11235 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11242 set_it_insn_type_last ();
11243 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11244 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11245 should cause the alignment to be checked once it is known. This is
11246 because BX PC only works if the instruction is word aligned. */
11254 set_it_insn_type_last ();
11255 Rm
= inst
.operands
[0].reg
;
11256 reject_bad_reg (Rm
);
11257 inst
.instruction
|= Rm
<< 16;
11266 Rd
= inst
.operands
[0].reg
;
11267 Rm
= inst
.operands
[1].reg
;
11269 reject_bad_reg (Rd
);
11270 reject_bad_reg (Rm
);
11272 inst
.instruction
|= Rd
<< 8;
11273 inst
.instruction
|= Rm
<< 16;
11274 inst
.instruction
|= Rm
;
11280 set_it_insn_type (OUTSIDE_IT_INSN
);
11281 inst
.instruction
|= inst
.operands
[0].imm
;
11287 set_it_insn_type (OUTSIDE_IT_INSN
);
11289 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11290 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11292 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11293 inst
.instruction
= 0xf3af8000;
11294 inst
.instruction
|= imod
<< 9;
11295 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11296 if (inst
.operands
[1].present
)
11297 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11301 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11302 && (inst
.operands
[0].imm
& 4),
11303 _("selected processor does not support 'A' form "
11304 "of this instruction"));
11305 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11306 _("Thumb does not support the 2-argument "
11307 "form of this instruction"));
11308 inst
.instruction
|= inst
.operands
[0].imm
;
11312 /* THUMB CPY instruction (argument parse). */
11317 if (inst
.size_req
== 4)
11319 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11320 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11321 inst
.instruction
|= inst
.operands
[1].reg
;
11325 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11326 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11327 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11334 set_it_insn_type (OUTSIDE_IT_INSN
);
11335 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11336 inst
.instruction
|= inst
.operands
[0].reg
;
11337 inst
.reloc
.pc_rel
= 1;
11338 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11344 inst
.instruction
|= inst
.operands
[0].imm
;
11350 unsigned Rd
, Rn
, Rm
;
11352 Rd
= inst
.operands
[0].reg
;
11353 Rn
= (inst
.operands
[1].present
11354 ? inst
.operands
[1].reg
: Rd
);
11355 Rm
= inst
.operands
[2].reg
;
11357 reject_bad_reg (Rd
);
11358 reject_bad_reg (Rn
);
11359 reject_bad_reg (Rm
);
11361 inst
.instruction
|= Rd
<< 8;
11362 inst
.instruction
|= Rn
<< 16;
11363 inst
.instruction
|= Rm
;
11369 if (unified_syntax
&& inst
.size_req
== 4)
11370 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11372 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11378 unsigned int cond
= inst
.operands
[0].imm
;
11380 set_it_insn_type (IT_INSN
);
11381 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11383 now_it
.warn_deprecated
= FALSE
;
11385 /* If the condition is a negative condition, invert the mask. */
11386 if ((cond
& 0x1) == 0x0)
11388 unsigned int mask
= inst
.instruction
& 0x000f;
11390 if ((mask
& 0x7) == 0)
11392 /* No conversion needed. */
11393 now_it
.block_length
= 1;
11395 else if ((mask
& 0x3) == 0)
11398 now_it
.block_length
= 2;
11400 else if ((mask
& 0x1) == 0)
11403 now_it
.block_length
= 3;
11408 now_it
.block_length
= 4;
11411 inst
.instruction
&= 0xfff0;
11412 inst
.instruction
|= mask
;
11415 inst
.instruction
|= cond
<< 4;
11418 /* Helper function used for both push/pop and ldm/stm. */
11420 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11424 load
= (inst
.instruction
& (1 << 20)) != 0;
11426 if (mask
& (1 << 13))
11427 inst
.error
= _("SP not allowed in register list");
11429 if ((mask
& (1 << base
)) != 0
11431 inst
.error
= _("having the base register in the register list when "
11432 "using write back is UNPREDICTABLE");
11436 if (mask
& (1 << 15))
11438 if (mask
& (1 << 14))
11439 inst
.error
= _("LR and PC should not both be in register list");
11441 set_it_insn_type_last ();
11446 if (mask
& (1 << 15))
11447 inst
.error
= _("PC not allowed in register list");
11450 if ((mask
& (mask
- 1)) == 0)
11452 /* Single register transfers implemented as str/ldr. */
11455 if (inst
.instruction
& (1 << 23))
11456 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11458 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11462 if (inst
.instruction
& (1 << 23))
11463 inst
.instruction
= 0x00800000; /* ia -> [base] */
11465 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11468 inst
.instruction
|= 0xf8400000;
11470 inst
.instruction
|= 0x00100000;
11472 mask
= ffs (mask
) - 1;
11475 else if (writeback
)
11476 inst
.instruction
|= WRITE_BACK
;
11478 inst
.instruction
|= mask
;
11479 inst
.instruction
|= base
<< 16;
11485 /* This really doesn't seem worth it. */
11486 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11487 _("expression too complex"));
11488 constraint (inst
.operands
[1].writeback
,
11489 _("Thumb load/store multiple does not support {reglist}^"));
11491 if (unified_syntax
)
11493 bfd_boolean narrow
;
11497 /* See if we can use a 16-bit instruction. */
11498 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11499 && inst
.size_req
!= 4
11500 && !(inst
.operands
[1].imm
& ~0xff))
11502 mask
= 1 << inst
.operands
[0].reg
;
11504 if (inst
.operands
[0].reg
<= 7)
11506 if (inst
.instruction
== T_MNEM_stmia
11507 ? inst
.operands
[0].writeback
11508 : (inst
.operands
[0].writeback
11509 == !(inst
.operands
[1].imm
& mask
)))
11511 if (inst
.instruction
== T_MNEM_stmia
11512 && (inst
.operands
[1].imm
& mask
)
11513 && (inst
.operands
[1].imm
& (mask
- 1)))
11514 as_warn (_("value stored for r%d is UNKNOWN"),
11515 inst
.operands
[0].reg
);
11517 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11518 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11519 inst
.instruction
|= inst
.operands
[1].imm
;
11522 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11524 /* This means 1 register in reg list one of 3 situations:
11525 1. Instruction is stmia, but without writeback.
11526 2. lmdia without writeback, but with Rn not in
11528 3. ldmia with writeback, but with Rn in reglist.
11529 Case 3 is UNPREDICTABLE behaviour, so we handle
11530 case 1 and 2 which can be converted into a 16-bit
11531 str or ldr. The SP cases are handled below. */
11532 unsigned long opcode
;
11533 /* First, record an error for Case 3. */
11534 if (inst
.operands
[1].imm
& mask
11535 && inst
.operands
[0].writeback
)
11537 _("having the base register in the register list when "
11538 "using write back is UNPREDICTABLE");
11540 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11542 inst
.instruction
= THUMB_OP16 (opcode
);
11543 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11544 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11548 else if (inst
.operands
[0] .reg
== REG_SP
)
11550 if (inst
.operands
[0].writeback
)
11553 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11554 ? T_MNEM_push
: T_MNEM_pop
);
11555 inst
.instruction
|= inst
.operands
[1].imm
;
11558 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11561 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11562 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11563 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11571 if (inst
.instruction
< 0xffff)
11572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11574 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11575 inst
.operands
[0].writeback
);
11580 constraint (inst
.operands
[0].reg
> 7
11581 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11582 constraint (inst
.instruction
!= T_MNEM_ldmia
11583 && inst
.instruction
!= T_MNEM_stmia
,
11584 _("Thumb-2 instruction only valid in unified syntax"));
11585 if (inst
.instruction
== T_MNEM_stmia
)
11587 if (!inst
.operands
[0].writeback
)
11588 as_warn (_("this instruction will write back the base register"));
11589 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11590 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11591 as_warn (_("value stored for r%d is UNKNOWN"),
11592 inst
.operands
[0].reg
);
11596 if (!inst
.operands
[0].writeback
11597 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11598 as_warn (_("this instruction will write back the base register"));
11599 else if (inst
.operands
[0].writeback
11600 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11601 as_warn (_("this instruction will not write back the base register"));
11604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11606 inst
.instruction
|= inst
.operands
[1].imm
;
11613 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11614 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11615 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11616 || inst
.operands
[1].negative
,
11619 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11621 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11622 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11623 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11629 if (!inst
.operands
[1].present
)
11631 constraint (inst
.operands
[0].reg
== REG_LR
,
11632 _("r14 not allowed as first register "
11633 "when second register is omitted"));
11634 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11636 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11640 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11641 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11647 unsigned long opcode
;
11650 if (inst
.operands
[0].isreg
11651 && !inst
.operands
[0].preind
11652 && inst
.operands
[0].reg
== REG_PC
)
11653 set_it_insn_type_last ();
11655 opcode
= inst
.instruction
;
11656 if (unified_syntax
)
11658 if (!inst
.operands
[1].isreg
)
11660 if (opcode
<= 0xffff)
11661 inst
.instruction
= THUMB_OP32 (opcode
);
11662 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11665 if (inst
.operands
[1].isreg
11666 && !inst
.operands
[1].writeback
11667 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11668 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11669 && opcode
<= 0xffff
11670 && inst
.size_req
!= 4)
11672 /* Insn may have a 16-bit form. */
11673 Rn
= inst
.operands
[1].reg
;
11674 if (inst
.operands
[1].immisreg
)
11676 inst
.instruction
= THUMB_OP16 (opcode
);
11678 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11680 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11681 reject_bad_reg (inst
.operands
[1].imm
);
11683 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11684 && opcode
!= T_MNEM_ldrsb
)
11685 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11686 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11693 if (inst
.reloc
.pc_rel
)
11694 opcode
= T_MNEM_ldr_pc2
;
11696 opcode
= T_MNEM_ldr_pc
;
11700 if (opcode
== T_MNEM_ldr
)
11701 opcode
= T_MNEM_ldr_sp
;
11703 opcode
= T_MNEM_str_sp
;
11705 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11709 inst
.instruction
= inst
.operands
[0].reg
;
11710 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11712 inst
.instruction
|= THUMB_OP16 (opcode
);
11713 if (inst
.size_req
== 2)
11714 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11716 inst
.relax
= opcode
;
11720 /* Definitely a 32-bit variant. */
11722 /* Warning for Erratum 752419. */
11723 if (opcode
== T_MNEM_ldr
11724 && inst
.operands
[0].reg
== REG_SP
11725 && inst
.operands
[1].writeback
== 1
11726 && !inst
.operands
[1].immisreg
)
11728 if (no_cpu_selected ()
11729 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11730 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11731 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11732 as_warn (_("This instruction may be unpredictable "
11733 "if executed on M-profile cores "
11734 "with interrupts enabled."));
11737 /* Do some validations regarding addressing modes. */
11738 if (inst
.operands
[1].immisreg
)
11739 reject_bad_reg (inst
.operands
[1].imm
);
11741 constraint (inst
.operands
[1].writeback
== 1
11742 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11745 inst
.instruction
= THUMB_OP32 (opcode
);
11746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11747 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11748 check_ldr_r15_aligned ();
11752 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11754 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11756 /* Only [Rn,Rm] is acceptable. */
11757 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11758 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11759 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11760 || inst
.operands
[1].negative
,
11761 _("Thumb does not support this addressing mode"));
11762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11766 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11767 if (!inst
.operands
[1].isreg
)
11768 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11771 constraint (!inst
.operands
[1].preind
11772 || inst
.operands
[1].shifted
11773 || inst
.operands
[1].writeback
,
11774 _("Thumb does not support this addressing mode"));
11775 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11777 constraint (inst
.instruction
& 0x0600,
11778 _("byte or halfword not valid for base register"));
11779 constraint (inst
.operands
[1].reg
== REG_PC
11780 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11781 _("r15 based store not allowed"));
11782 constraint (inst
.operands
[1].immisreg
,
11783 _("invalid base register for register offset"));
11785 if (inst
.operands
[1].reg
== REG_PC
)
11786 inst
.instruction
= T_OPCODE_LDR_PC
;
11787 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11788 inst
.instruction
= T_OPCODE_LDR_SP
;
11790 inst
.instruction
= T_OPCODE_STR_SP
;
11792 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11793 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11797 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11798 if (!inst
.operands
[1].immisreg
)
11800 /* Immediate offset. */
11801 inst
.instruction
|= inst
.operands
[0].reg
;
11802 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11803 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11807 /* Register offset. */
11808 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11809 constraint (inst
.operands
[1].negative
,
11810 _("Thumb does not support this addressing mode"));
11813 switch (inst
.instruction
)
11815 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11816 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11817 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11818 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11819 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11820 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11821 case 0x5600 /* ldrsb */:
11822 case 0x5e00 /* ldrsh */: break;
11826 inst
.instruction
|= inst
.operands
[0].reg
;
11827 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11828 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11834 if (!inst
.operands
[1].present
)
11836 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11837 constraint (inst
.operands
[0].reg
== REG_LR
,
11838 _("r14 not allowed here"));
11839 constraint (inst
.operands
[0].reg
== REG_R12
,
11840 _("r12 not allowed here"));
11843 if (inst
.operands
[2].writeback
11844 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11845 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11846 as_warn (_("base register written back, and overlaps "
11847 "one of transfer registers"));
11849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11850 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11851 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11858 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11864 unsigned Rd
, Rn
, Rm
, Ra
;
11866 Rd
= inst
.operands
[0].reg
;
11867 Rn
= inst
.operands
[1].reg
;
11868 Rm
= inst
.operands
[2].reg
;
11869 Ra
= inst
.operands
[3].reg
;
11871 reject_bad_reg (Rd
);
11872 reject_bad_reg (Rn
);
11873 reject_bad_reg (Rm
);
11874 reject_bad_reg (Ra
);
11876 inst
.instruction
|= Rd
<< 8;
11877 inst
.instruction
|= Rn
<< 16;
11878 inst
.instruction
|= Rm
;
11879 inst
.instruction
|= Ra
<< 12;
11885 unsigned RdLo
, RdHi
, Rn
, Rm
;
11887 RdLo
= inst
.operands
[0].reg
;
11888 RdHi
= inst
.operands
[1].reg
;
11889 Rn
= inst
.operands
[2].reg
;
11890 Rm
= inst
.operands
[3].reg
;
11892 reject_bad_reg (RdLo
);
11893 reject_bad_reg (RdHi
);
11894 reject_bad_reg (Rn
);
11895 reject_bad_reg (Rm
);
11897 inst
.instruction
|= RdLo
<< 12;
11898 inst
.instruction
|= RdHi
<< 8;
11899 inst
.instruction
|= Rn
<< 16;
11900 inst
.instruction
|= Rm
;
11904 do_t_mov_cmp (void)
11908 Rn
= inst
.operands
[0].reg
;
11909 Rm
= inst
.operands
[1].reg
;
11912 set_it_insn_type_last ();
11914 if (unified_syntax
)
11916 int r0off
= (inst
.instruction
== T_MNEM_mov
11917 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11918 unsigned long opcode
;
11919 bfd_boolean narrow
;
11920 bfd_boolean low_regs
;
11922 low_regs
= (Rn
<= 7 && Rm
<= 7);
11923 opcode
= inst
.instruction
;
11924 if (in_it_block ())
11925 narrow
= opcode
!= T_MNEM_movs
;
11927 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11928 if (inst
.size_req
== 4
11929 || inst
.operands
[1].shifted
)
11932 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11933 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11934 && !inst
.operands
[1].shifted
11938 inst
.instruction
= T2_SUBS_PC_LR
;
11942 if (opcode
== T_MNEM_cmp
)
11944 constraint (Rn
== REG_PC
, BAD_PC
);
11947 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11949 warn_deprecated_sp (Rm
);
11950 /* R15 was documented as a valid choice for Rm in ARMv6,
11951 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11952 tools reject R15, so we do too. */
11953 constraint (Rm
== REG_PC
, BAD_PC
);
11956 reject_bad_reg (Rm
);
11958 else if (opcode
== T_MNEM_mov
11959 || opcode
== T_MNEM_movs
)
11961 if (inst
.operands
[1].isreg
)
11963 if (opcode
== T_MNEM_movs
)
11965 reject_bad_reg (Rn
);
11966 reject_bad_reg (Rm
);
11970 /* This is mov.n. */
11971 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11972 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11974 as_tsktsk (_("Use of r%u as a source register is "
11975 "deprecated when r%u is the destination "
11976 "register."), Rm
, Rn
);
11981 /* This is mov.w. */
11982 constraint (Rn
== REG_PC
, BAD_PC
);
11983 constraint (Rm
== REG_PC
, BAD_PC
);
11984 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11985 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11989 reject_bad_reg (Rn
);
11992 if (!inst
.operands
[1].isreg
)
11994 /* Immediate operand. */
11995 if (!in_it_block () && opcode
== T_MNEM_mov
)
11997 if (low_regs
&& narrow
)
11999 inst
.instruction
= THUMB_OP16 (opcode
);
12000 inst
.instruction
|= Rn
<< 8;
12001 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12002 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12004 if (inst
.size_req
== 2)
12005 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12007 inst
.relax
= opcode
;
12012 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12013 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12014 THUMB1_RELOC_ONLY
);
12016 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12017 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12018 inst
.instruction
|= Rn
<< r0off
;
12019 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12022 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12023 && (inst
.instruction
== T_MNEM_mov
12024 || inst
.instruction
== T_MNEM_movs
))
12026 /* Register shifts are encoded as separate shift instructions. */
12027 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12029 if (in_it_block ())
12034 if (inst
.size_req
== 4)
12037 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12043 switch (inst
.operands
[1].shift_kind
)
12046 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12049 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12052 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12055 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12061 inst
.instruction
= opcode
;
12064 inst
.instruction
|= Rn
;
12065 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12070 inst
.instruction
|= CONDS_BIT
;
12072 inst
.instruction
|= Rn
<< 8;
12073 inst
.instruction
|= Rm
<< 16;
12074 inst
.instruction
|= inst
.operands
[1].imm
;
12079 /* Some mov with immediate shift have narrow variants.
12080 Register shifts are handled above. */
12081 if (low_regs
&& inst
.operands
[1].shifted
12082 && (inst
.instruction
== T_MNEM_mov
12083 || inst
.instruction
== T_MNEM_movs
))
12085 if (in_it_block ())
12086 narrow
= (inst
.instruction
== T_MNEM_mov
);
12088 narrow
= (inst
.instruction
== T_MNEM_movs
);
12093 switch (inst
.operands
[1].shift_kind
)
12095 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12096 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12097 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12098 default: narrow
= FALSE
; break;
12104 inst
.instruction
|= Rn
;
12105 inst
.instruction
|= Rm
<< 3;
12106 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12110 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12111 inst
.instruction
|= Rn
<< r0off
;
12112 encode_thumb32_shifted_operand (1);
12116 switch (inst
.instruction
)
12119 /* In v4t or v5t a move of two lowregs produces unpredictable
12120 results. Don't allow this. */
12123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12124 "MOV Rd, Rs with two low registers is not "
12125 "permitted on this architecture");
12126 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12130 inst
.instruction
= T_OPCODE_MOV_HR
;
12131 inst
.instruction
|= (Rn
& 0x8) << 4;
12132 inst
.instruction
|= (Rn
& 0x7);
12133 inst
.instruction
|= Rm
<< 3;
12137 /* We know we have low registers at this point.
12138 Generate LSLS Rd, Rs, #0. */
12139 inst
.instruction
= T_OPCODE_LSL_I
;
12140 inst
.instruction
|= Rn
;
12141 inst
.instruction
|= Rm
<< 3;
12147 inst
.instruction
= T_OPCODE_CMP_LR
;
12148 inst
.instruction
|= Rn
;
12149 inst
.instruction
|= Rm
<< 3;
12153 inst
.instruction
= T_OPCODE_CMP_HR
;
12154 inst
.instruction
|= (Rn
& 0x8) << 4;
12155 inst
.instruction
|= (Rn
& 0x7);
12156 inst
.instruction
|= Rm
<< 3;
12163 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12165 /* PR 10443: Do not silently ignore shifted operands. */
12166 constraint (inst
.operands
[1].shifted
,
12167 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12169 if (inst
.operands
[1].isreg
)
12171 if (Rn
< 8 && Rm
< 8)
12173 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12174 since a MOV instruction produces unpredictable results. */
12175 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12176 inst
.instruction
= T_OPCODE_ADD_I3
;
12178 inst
.instruction
= T_OPCODE_CMP_LR
;
12180 inst
.instruction
|= Rn
;
12181 inst
.instruction
|= Rm
<< 3;
12185 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12186 inst
.instruction
= T_OPCODE_MOV_HR
;
12188 inst
.instruction
= T_OPCODE_CMP_HR
;
12194 constraint (Rn
> 7,
12195 _("only lo regs allowed with immediate"));
12196 inst
.instruction
|= Rn
<< 8;
12197 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12208 top
= (inst
.instruction
& 0x00800000) != 0;
12209 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12211 constraint (top
, _(":lower16: not allowed in this instruction"));
12212 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12214 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12216 constraint (!top
, _(":upper16: not allowed in this instruction"));
12217 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12220 Rd
= inst
.operands
[0].reg
;
12221 reject_bad_reg (Rd
);
12223 inst
.instruction
|= Rd
<< 8;
12224 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12226 imm
= inst
.reloc
.exp
.X_add_number
;
12227 inst
.instruction
|= (imm
& 0xf000) << 4;
12228 inst
.instruction
|= (imm
& 0x0800) << 15;
12229 inst
.instruction
|= (imm
& 0x0700) << 4;
12230 inst
.instruction
|= (imm
& 0x00ff);
12235 do_t_mvn_tst (void)
12239 Rn
= inst
.operands
[0].reg
;
12240 Rm
= inst
.operands
[1].reg
;
12242 if (inst
.instruction
== T_MNEM_cmp
12243 || inst
.instruction
== T_MNEM_cmn
)
12244 constraint (Rn
== REG_PC
, BAD_PC
);
12246 reject_bad_reg (Rn
);
12247 reject_bad_reg (Rm
);
12249 if (unified_syntax
)
12251 int r0off
= (inst
.instruction
== T_MNEM_mvn
12252 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12253 bfd_boolean narrow
;
12255 if (inst
.size_req
== 4
12256 || inst
.instruction
> 0xffff
12257 || inst
.operands
[1].shifted
12258 || Rn
> 7 || Rm
> 7)
12260 else if (inst
.instruction
== T_MNEM_cmn
12261 || inst
.instruction
== T_MNEM_tst
)
12263 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12264 narrow
= !in_it_block ();
12266 narrow
= in_it_block ();
12268 if (!inst
.operands
[1].isreg
)
12270 /* For an immediate, we always generate a 32-bit opcode;
12271 section relaxation will shrink it later if possible. */
12272 if (inst
.instruction
< 0xffff)
12273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12274 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12275 inst
.instruction
|= Rn
<< r0off
;
12276 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12280 /* See if we can do this with a 16-bit instruction. */
12283 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12284 inst
.instruction
|= Rn
;
12285 inst
.instruction
|= Rm
<< 3;
12289 constraint (inst
.operands
[1].shifted
12290 && inst
.operands
[1].immisreg
,
12291 _("shift must be constant"));
12292 if (inst
.instruction
< 0xffff)
12293 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12294 inst
.instruction
|= Rn
<< r0off
;
12295 encode_thumb32_shifted_operand (1);
12301 constraint (inst
.instruction
> 0xffff
12302 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12303 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12304 _("unshifted register required"));
12305 constraint (Rn
> 7 || Rm
> 7,
12308 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12309 inst
.instruction
|= Rn
;
12310 inst
.instruction
|= Rm
<< 3;
12319 if (do_vfp_nsyn_mrs () == SUCCESS
)
12322 Rd
= inst
.operands
[0].reg
;
12323 reject_bad_reg (Rd
);
12324 inst
.instruction
|= Rd
<< 8;
12326 if (inst
.operands
[1].isreg
)
12328 unsigned br
= inst
.operands
[1].reg
;
12329 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12330 as_bad (_("bad register for mrs"));
12332 inst
.instruction
|= br
& (0xf << 16);
12333 inst
.instruction
|= (br
& 0x300) >> 4;
12334 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12338 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12340 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12342 /* PR gas/12698: The constraint is only applied for m_profile.
12343 If the user has specified -march=all, we want to ignore it as
12344 we are building for any CPU type, including non-m variants. */
12345 bfd_boolean m_profile
=
12346 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12347 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12348 "not support requested special purpose register"));
12351 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12353 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12354 _("'APSR', 'CPSR' or 'SPSR' expected"));
12356 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12357 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12358 inst
.instruction
|= 0xf0000;
12368 if (do_vfp_nsyn_msr () == SUCCESS
)
12371 constraint (!inst
.operands
[1].isreg
,
12372 _("Thumb encoding does not support an immediate here"));
12374 if (inst
.operands
[0].isreg
)
12375 flags
= (int)(inst
.operands
[0].reg
);
12377 flags
= inst
.operands
[0].imm
;
12379 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12381 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12383 /* PR gas/12698: The constraint is only applied for m_profile.
12384 If the user has specified -march=all, we want to ignore it as
12385 we are building for any CPU type, including non-m variants. */
12386 bfd_boolean m_profile
=
12387 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12388 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12389 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12390 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12391 && bits
!= PSR_f
)) && m_profile
,
12392 _("selected processor does not support requested special "
12393 "purpose register"));
12396 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12397 "requested special purpose register"));
12399 Rn
= inst
.operands
[1].reg
;
12400 reject_bad_reg (Rn
);
12402 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12403 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12404 inst
.instruction
|= (flags
& 0x300) >> 4;
12405 inst
.instruction
|= (flags
& 0xff);
12406 inst
.instruction
|= Rn
<< 16;
12412 bfd_boolean narrow
;
12413 unsigned Rd
, Rn
, Rm
;
12415 if (!inst
.operands
[2].present
)
12416 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12418 Rd
= inst
.operands
[0].reg
;
12419 Rn
= inst
.operands
[1].reg
;
12420 Rm
= inst
.operands
[2].reg
;
12422 if (unified_syntax
)
12424 if (inst
.size_req
== 4
12430 else if (inst
.instruction
== T_MNEM_muls
)
12431 narrow
= !in_it_block ();
12433 narrow
= in_it_block ();
12437 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12438 constraint (Rn
> 7 || Rm
> 7,
12445 /* 16-bit MULS/Conditional MUL. */
12446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12447 inst
.instruction
|= Rd
;
12450 inst
.instruction
|= Rm
<< 3;
12452 inst
.instruction
|= Rn
<< 3;
12454 constraint (1, _("dest must overlap one source register"));
12458 constraint (inst
.instruction
!= T_MNEM_mul
,
12459 _("Thumb-2 MUL must not set flags"));
12461 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12462 inst
.instruction
|= Rd
<< 8;
12463 inst
.instruction
|= Rn
<< 16;
12464 inst
.instruction
|= Rm
<< 0;
12466 reject_bad_reg (Rd
);
12467 reject_bad_reg (Rn
);
12468 reject_bad_reg (Rm
);
12475 unsigned RdLo
, RdHi
, Rn
, Rm
;
12477 RdLo
= inst
.operands
[0].reg
;
12478 RdHi
= inst
.operands
[1].reg
;
12479 Rn
= inst
.operands
[2].reg
;
12480 Rm
= inst
.operands
[3].reg
;
12482 reject_bad_reg (RdLo
);
12483 reject_bad_reg (RdHi
);
12484 reject_bad_reg (Rn
);
12485 reject_bad_reg (Rm
);
12487 inst
.instruction
|= RdLo
<< 12;
12488 inst
.instruction
|= RdHi
<< 8;
12489 inst
.instruction
|= Rn
<< 16;
12490 inst
.instruction
|= Rm
;
12493 as_tsktsk (_("rdhi and rdlo must be different"));
12499 set_it_insn_type (NEUTRAL_IT_INSN
);
12501 if (unified_syntax
)
12503 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12505 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12506 inst
.instruction
|= inst
.operands
[0].imm
;
12510 /* PR9722: Check for Thumb2 availability before
12511 generating a thumb2 nop instruction. */
12512 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12515 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12518 inst
.instruction
= 0x46c0;
12523 constraint (inst
.operands
[0].present
,
12524 _("Thumb does not support NOP with hints"));
12525 inst
.instruction
= 0x46c0;
12532 if (unified_syntax
)
12534 bfd_boolean narrow
;
12536 if (THUMB_SETS_FLAGS (inst
.instruction
))
12537 narrow
= !in_it_block ();
12539 narrow
= in_it_block ();
12540 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12542 if (inst
.size_req
== 4)
12547 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12553 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12554 inst
.instruction
|= inst
.operands
[0].reg
;
12555 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12560 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12562 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12564 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12565 inst
.instruction
|= inst
.operands
[0].reg
;
12566 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12575 Rd
= inst
.operands
[0].reg
;
12576 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12578 reject_bad_reg (Rd
);
12579 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12580 reject_bad_reg (Rn
);
12582 inst
.instruction
|= Rd
<< 8;
12583 inst
.instruction
|= Rn
<< 16;
12585 if (!inst
.operands
[2].isreg
)
12587 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12588 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12594 Rm
= inst
.operands
[2].reg
;
12595 reject_bad_reg (Rm
);
12597 constraint (inst
.operands
[2].shifted
12598 && inst
.operands
[2].immisreg
,
12599 _("shift must be constant"));
12600 encode_thumb32_shifted_operand (2);
12607 unsigned Rd
, Rn
, Rm
;
12609 Rd
= inst
.operands
[0].reg
;
12610 Rn
= inst
.operands
[1].reg
;
12611 Rm
= inst
.operands
[2].reg
;
12613 reject_bad_reg (Rd
);
12614 reject_bad_reg (Rn
);
12615 reject_bad_reg (Rm
);
12617 inst
.instruction
|= Rd
<< 8;
12618 inst
.instruction
|= Rn
<< 16;
12619 inst
.instruction
|= Rm
;
12620 if (inst
.operands
[3].present
)
12622 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12623 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12624 _("expression too complex"));
12625 inst
.instruction
|= (val
& 0x1c) << 10;
12626 inst
.instruction
|= (val
& 0x03) << 6;
12633 if (!inst
.operands
[3].present
)
12637 inst
.instruction
&= ~0x00000020;
12639 /* PR 10168. Swap the Rm and Rn registers. */
12640 Rtmp
= inst
.operands
[1].reg
;
12641 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12642 inst
.operands
[2].reg
= Rtmp
;
12650 if (inst
.operands
[0].immisreg
)
12651 reject_bad_reg (inst
.operands
[0].imm
);
12653 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12657 do_t_push_pop (void)
12661 constraint (inst
.operands
[0].writeback
,
12662 _("push/pop do not support {reglist}^"));
12663 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12664 _("expression too complex"));
12666 mask
= inst
.operands
[0].imm
;
12667 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12668 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12669 else if (inst
.size_req
!= 4
12670 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12671 ? REG_LR
: REG_PC
)))
12673 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12674 inst
.instruction
|= THUMB_PP_PC_LR
;
12675 inst
.instruction
|= mask
& 0xff;
12677 else if (unified_syntax
)
12679 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12680 encode_thumb2_ldmstm (13, mask
, TRUE
);
12684 inst
.error
= _("invalid register list to push/pop instruction");
12694 Rd
= inst
.operands
[0].reg
;
12695 Rm
= inst
.operands
[1].reg
;
12697 reject_bad_reg (Rd
);
12698 reject_bad_reg (Rm
);
12700 inst
.instruction
|= Rd
<< 8;
12701 inst
.instruction
|= Rm
<< 16;
12702 inst
.instruction
|= Rm
;
12710 Rd
= inst
.operands
[0].reg
;
12711 Rm
= inst
.operands
[1].reg
;
12713 reject_bad_reg (Rd
);
12714 reject_bad_reg (Rm
);
12716 if (Rd
<= 7 && Rm
<= 7
12717 && inst
.size_req
!= 4)
12719 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12720 inst
.instruction
|= Rd
;
12721 inst
.instruction
|= Rm
<< 3;
12723 else if (unified_syntax
)
12725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12726 inst
.instruction
|= Rd
<< 8;
12727 inst
.instruction
|= Rm
<< 16;
12728 inst
.instruction
|= Rm
;
12731 inst
.error
= BAD_HIREG
;
12739 Rd
= inst
.operands
[0].reg
;
12740 Rm
= inst
.operands
[1].reg
;
12742 reject_bad_reg (Rd
);
12743 reject_bad_reg (Rm
);
12745 inst
.instruction
|= Rd
<< 8;
12746 inst
.instruction
|= Rm
;
12754 Rd
= inst
.operands
[0].reg
;
12755 Rs
= (inst
.operands
[1].present
12756 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12757 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12759 reject_bad_reg (Rd
);
12760 reject_bad_reg (Rs
);
12761 if (inst
.operands
[2].isreg
)
12762 reject_bad_reg (inst
.operands
[2].reg
);
12764 inst
.instruction
|= Rd
<< 8;
12765 inst
.instruction
|= Rs
<< 16;
12766 if (!inst
.operands
[2].isreg
)
12768 bfd_boolean narrow
;
12770 if ((inst
.instruction
& 0x00100000) != 0)
12771 narrow
= !in_it_block ();
12773 narrow
= in_it_block ();
12775 if (Rd
> 7 || Rs
> 7)
12778 if (inst
.size_req
== 4 || !unified_syntax
)
12781 if (inst
.reloc
.exp
.X_op
!= O_constant
12782 || inst
.reloc
.exp
.X_add_number
!= 0)
12785 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12786 relaxation, but it doesn't seem worth the hassle. */
12789 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12790 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12791 inst
.instruction
|= Rs
<< 3;
12792 inst
.instruction
|= Rd
;
12796 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12797 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12801 encode_thumb32_shifted_operand (2);
12807 if (warn_on_deprecated
12808 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12809 as_tsktsk (_("setend use is deprecated for ARMv8"));
12811 set_it_insn_type (OUTSIDE_IT_INSN
);
12812 if (inst
.operands
[0].imm
)
12813 inst
.instruction
|= 0x8;
12819 if (!inst
.operands
[1].present
)
12820 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12822 if (unified_syntax
)
12824 bfd_boolean narrow
;
12827 switch (inst
.instruction
)
12830 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12832 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12834 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12836 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12840 if (THUMB_SETS_FLAGS (inst
.instruction
))
12841 narrow
= !in_it_block ();
12843 narrow
= in_it_block ();
12844 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12846 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12848 if (inst
.operands
[2].isreg
12849 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12850 || inst
.operands
[2].reg
> 7))
12852 if (inst
.size_req
== 4)
12855 reject_bad_reg (inst
.operands
[0].reg
);
12856 reject_bad_reg (inst
.operands
[1].reg
);
12860 if (inst
.operands
[2].isreg
)
12862 reject_bad_reg (inst
.operands
[2].reg
);
12863 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12864 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12865 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12866 inst
.instruction
|= inst
.operands
[2].reg
;
12868 /* PR 12854: Error on extraneous shifts. */
12869 constraint (inst
.operands
[2].shifted
,
12870 _("extraneous shift as part of operand to shift insn"));
12874 inst
.operands
[1].shifted
= 1;
12875 inst
.operands
[1].shift_kind
= shift_kind
;
12876 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12877 ? T_MNEM_movs
: T_MNEM_mov
);
12878 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12879 encode_thumb32_shifted_operand (1);
12880 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12881 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12886 if (inst
.operands
[2].isreg
)
12888 switch (shift_kind
)
12890 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12891 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12892 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12893 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12897 inst
.instruction
|= inst
.operands
[0].reg
;
12898 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12900 /* PR 12854: Error on extraneous shifts. */
12901 constraint (inst
.operands
[2].shifted
,
12902 _("extraneous shift as part of operand to shift insn"));
12906 switch (shift_kind
)
12908 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12909 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12910 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12913 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12914 inst
.instruction
|= inst
.operands
[0].reg
;
12915 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12921 constraint (inst
.operands
[0].reg
> 7
12922 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12923 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12925 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12927 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12928 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12929 _("source1 and dest must be same register"));
12931 switch (inst
.instruction
)
12933 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12934 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12935 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12936 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12940 inst
.instruction
|= inst
.operands
[0].reg
;
12941 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12943 /* PR 12854: Error on extraneous shifts. */
12944 constraint (inst
.operands
[2].shifted
,
12945 _("extraneous shift as part of operand to shift insn"));
12949 switch (inst
.instruction
)
12951 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12952 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12953 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12954 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12957 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12958 inst
.instruction
|= inst
.operands
[0].reg
;
12959 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12967 unsigned Rd
, Rn
, Rm
;
12969 Rd
= inst
.operands
[0].reg
;
12970 Rn
= inst
.operands
[1].reg
;
12971 Rm
= inst
.operands
[2].reg
;
12973 reject_bad_reg (Rd
);
12974 reject_bad_reg (Rn
);
12975 reject_bad_reg (Rm
);
12977 inst
.instruction
|= Rd
<< 8;
12978 inst
.instruction
|= Rn
<< 16;
12979 inst
.instruction
|= Rm
;
12985 unsigned Rd
, Rn
, Rm
;
12987 Rd
= inst
.operands
[0].reg
;
12988 Rm
= inst
.operands
[1].reg
;
12989 Rn
= inst
.operands
[2].reg
;
12991 reject_bad_reg (Rd
);
12992 reject_bad_reg (Rn
);
12993 reject_bad_reg (Rm
);
12995 inst
.instruction
|= Rd
<< 8;
12996 inst
.instruction
|= Rn
<< 16;
12997 inst
.instruction
|= Rm
;
13003 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13005 _("SMC is not permitted on this architecture"));
13006 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13007 _("expression too complex"));
13008 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13009 inst
.instruction
|= (value
& 0xf000) >> 12;
13010 inst
.instruction
|= (value
& 0x0ff0);
13011 inst
.instruction
|= (value
& 0x000f) << 16;
13012 /* PR gas/15623: SMC instructions must be last in an IT block. */
13013 set_it_insn_type_last ();
13019 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13021 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13022 inst
.instruction
|= (value
& 0x0fff);
13023 inst
.instruction
|= (value
& 0xf000) << 4;
13027 do_t_ssat_usat (int bias
)
13031 Rd
= inst
.operands
[0].reg
;
13032 Rn
= inst
.operands
[2].reg
;
13034 reject_bad_reg (Rd
);
13035 reject_bad_reg (Rn
);
13037 inst
.instruction
|= Rd
<< 8;
13038 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13039 inst
.instruction
|= Rn
<< 16;
13041 if (inst
.operands
[3].present
)
13043 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13045 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13047 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13048 _("expression too complex"));
13050 if (shift_amount
!= 0)
13052 constraint (shift_amount
> 31,
13053 _("shift expression is too large"));
13055 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13056 inst
.instruction
|= 0x00200000; /* sh bit. */
13058 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13059 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13067 do_t_ssat_usat (1);
13075 Rd
= inst
.operands
[0].reg
;
13076 Rn
= inst
.operands
[2].reg
;
13078 reject_bad_reg (Rd
);
13079 reject_bad_reg (Rn
);
13081 inst
.instruction
|= Rd
<< 8;
13082 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13083 inst
.instruction
|= Rn
<< 16;
13089 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13090 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13091 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13092 || inst
.operands
[2].negative
,
13095 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13097 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13098 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13099 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13100 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13106 if (!inst
.operands
[2].present
)
13107 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13109 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13110 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13111 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13114 inst
.instruction
|= inst
.operands
[0].reg
;
13115 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13116 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13117 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13123 unsigned Rd
, Rn
, Rm
;
13125 Rd
= inst
.operands
[0].reg
;
13126 Rn
= inst
.operands
[1].reg
;
13127 Rm
= inst
.operands
[2].reg
;
13129 reject_bad_reg (Rd
);
13130 reject_bad_reg (Rn
);
13131 reject_bad_reg (Rm
);
13133 inst
.instruction
|= Rd
<< 8;
13134 inst
.instruction
|= Rn
<< 16;
13135 inst
.instruction
|= Rm
;
13136 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13144 Rd
= inst
.operands
[0].reg
;
13145 Rm
= inst
.operands
[1].reg
;
13147 reject_bad_reg (Rd
);
13148 reject_bad_reg (Rm
);
13150 if (inst
.instruction
<= 0xffff
13151 && inst
.size_req
!= 4
13152 && Rd
<= 7 && Rm
<= 7
13153 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13155 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13156 inst
.instruction
|= Rd
;
13157 inst
.instruction
|= Rm
<< 3;
13159 else if (unified_syntax
)
13161 if (inst
.instruction
<= 0xffff)
13162 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13163 inst
.instruction
|= Rd
<< 8;
13164 inst
.instruction
|= Rm
;
13165 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13169 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13170 _("Thumb encoding does not support rotation"));
13171 constraint (1, BAD_HIREG
);
13178 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13187 half
= (inst
.instruction
& 0x10) != 0;
13188 set_it_insn_type_last ();
13189 constraint (inst
.operands
[0].immisreg
,
13190 _("instruction requires register index"));
13192 Rn
= inst
.operands
[0].reg
;
13193 Rm
= inst
.operands
[0].imm
;
13195 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13196 constraint (Rn
== REG_SP
, BAD_SP
);
13197 reject_bad_reg (Rm
);
13199 constraint (!half
&& inst
.operands
[0].shifted
,
13200 _("instruction does not allow shifted index"));
13201 inst
.instruction
|= (Rn
<< 16) | Rm
;
13207 if (!inst
.operands
[0].present
)
13208 inst
.operands
[0].imm
= 0;
13210 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13212 constraint (inst
.size_req
== 2,
13213 _("immediate value out of range"));
13214 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13215 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13216 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13221 inst
.instruction
|= inst
.operands
[0].imm
;
13224 set_it_insn_type (NEUTRAL_IT_INSN
);
13231 do_t_ssat_usat (0);
13239 Rd
= inst
.operands
[0].reg
;
13240 Rn
= inst
.operands
[2].reg
;
13242 reject_bad_reg (Rd
);
13243 reject_bad_reg (Rn
);
13245 inst
.instruction
|= Rd
<< 8;
13246 inst
.instruction
|= inst
.operands
[1].imm
;
13247 inst
.instruction
|= Rn
<< 16;
13250 /* Neon instruction encoder helpers. */
13252 /* Encodings for the different types for various Neon opcodes. */
13254 /* An "invalid" code for the following tables. */
13257 struct neon_tab_entry
13260 unsigned float_or_poly
;
13261 unsigned scalar_or_imm
;
13264 /* Map overloaded Neon opcodes to their respective encodings. */
13265 #define NEON_ENC_TAB \
13266 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13267 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13268 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13269 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13270 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13271 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13272 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13273 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13274 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13275 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13276 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13277 /* Register variants of the following two instructions are encoded as
13278 vcge / vcgt with the operands reversed. */ \
13279 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13280 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13281 X(vfma, N_INV, 0x0000c10, N_INV), \
13282 X(vfms, N_INV, 0x0200c10, N_INV), \
13283 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13284 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13285 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13286 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13287 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13288 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13289 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13290 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13291 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13292 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13293 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13294 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13295 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13296 X(vshl, 0x0000400, N_INV, 0x0800510), \
13297 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13298 X(vand, 0x0000110, N_INV, 0x0800030), \
13299 X(vbic, 0x0100110, N_INV, 0x0800030), \
13300 X(veor, 0x1000110, N_INV, N_INV), \
13301 X(vorn, 0x0300110, N_INV, 0x0800010), \
13302 X(vorr, 0x0200110, N_INV, 0x0800010), \
13303 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13304 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13305 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13306 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13307 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13308 X(vst1, 0x0000000, 0x0800000, N_INV), \
13309 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13310 X(vst2, 0x0000100, 0x0800100, N_INV), \
13311 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13312 X(vst3, 0x0000200, 0x0800200, N_INV), \
13313 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13314 X(vst4, 0x0000300, 0x0800300, N_INV), \
13315 X(vmovn, 0x1b20200, N_INV, N_INV), \
13316 X(vtrn, 0x1b20080, N_INV, N_INV), \
13317 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13318 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13319 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13320 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13321 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13322 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13323 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13324 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13325 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13326 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13327 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13328 X(vseleq, 0xe000a00, N_INV, N_INV), \
13329 X(vselvs, 0xe100a00, N_INV, N_INV), \
13330 X(vselge, 0xe200a00, N_INV, N_INV), \
13331 X(vselgt, 0xe300a00, N_INV, N_INV), \
13332 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13333 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13334 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13335 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13336 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13337 X(aes, 0x3b00300, N_INV, N_INV), \
13338 X(sha3op, 0x2000c00, N_INV, N_INV), \
13339 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13340 X(sha2op, 0x3ba0380, N_INV, N_INV)
13344 #define X(OPC,I,F,S) N_MNEM_##OPC
13349 static const struct neon_tab_entry neon_enc_tab
[] =
13351 #define X(OPC,I,F,S) { (I), (F), (S) }
13356 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13357 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13358 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13359 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13360 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13361 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13362 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13363 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13364 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13365 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13366 #define NEON_ENC_SINGLE_(X) \
13367 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13368 #define NEON_ENC_DOUBLE_(X) \
13369 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13370 #define NEON_ENC_FPV8_(X) \
13371 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13373 #define NEON_ENCODE(type, inst) \
13376 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13377 inst.is_neon = 1; \
13381 #define check_neon_suffixes \
13384 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13386 as_bad (_("invalid neon suffix for non neon instruction")); \
13392 /* Define shapes for instruction operands. The following mnemonic characters
13393 are used in this table:
13395 F - VFP S<n> register
13396 D - Neon D<n> register
13397 Q - Neon Q<n> register
13401 L - D<n> register list
13403 This table is used to generate various data:
13404 - enumerations of the form NS_DDR to be used as arguments to
13406 - a table classifying shapes into single, double, quad, mixed.
13407 - a table used to drive neon_select_shape. */
13409 #define NEON_SHAPE_DEF \
13410 X(3, (D, D, D), DOUBLE), \
13411 X(3, (Q, Q, Q), QUAD), \
13412 X(3, (D, D, I), DOUBLE), \
13413 X(3, (Q, Q, I), QUAD), \
13414 X(3, (D, D, S), DOUBLE), \
13415 X(3, (Q, Q, S), QUAD), \
13416 X(2, (D, D), DOUBLE), \
13417 X(2, (Q, Q), QUAD), \
13418 X(2, (D, S), DOUBLE), \
13419 X(2, (Q, S), QUAD), \
13420 X(2, (D, R), DOUBLE), \
13421 X(2, (Q, R), QUAD), \
13422 X(2, (D, I), DOUBLE), \
13423 X(2, (Q, I), QUAD), \
13424 X(3, (D, L, D), DOUBLE), \
13425 X(2, (D, Q), MIXED), \
13426 X(2, (Q, D), MIXED), \
13427 X(3, (D, Q, I), MIXED), \
13428 X(3, (Q, D, I), MIXED), \
13429 X(3, (Q, D, D), MIXED), \
13430 X(3, (D, Q, Q), MIXED), \
13431 X(3, (Q, Q, D), MIXED), \
13432 X(3, (Q, D, S), MIXED), \
13433 X(3, (D, Q, S), MIXED), \
13434 X(4, (D, D, D, I), DOUBLE), \
13435 X(4, (Q, Q, Q, I), QUAD), \
13436 X(4, (D, D, S, I), DOUBLE), \
13437 X(4, (Q, Q, S, I), QUAD), \
13438 X(2, (F, F), SINGLE), \
13439 X(3, (F, F, F), SINGLE), \
13440 X(2, (F, I), SINGLE), \
13441 X(2, (F, D), MIXED), \
13442 X(2, (D, F), MIXED), \
13443 X(3, (F, F, I), MIXED), \
13444 X(4, (R, R, F, F), SINGLE), \
13445 X(4, (F, F, R, R), SINGLE), \
13446 X(3, (D, R, R), DOUBLE), \
13447 X(3, (R, R, D), DOUBLE), \
13448 X(2, (S, R), SINGLE), \
13449 X(2, (R, S), SINGLE), \
13450 X(2, (F, R), SINGLE), \
13451 X(2, (R, F), SINGLE), \
13452 /* Half float shape supported so far. */\
13453 X (2, (H, D), MIXED), \
13454 X (2, (D, H), MIXED), \
13455 X (2, (H, F), MIXED), \
13456 X (2, (F, H), MIXED), \
13457 X (2, (H, H), HALF), \
13458 X (2, (H, R), HALF), \
13459 X (2, (R, H), HALF), \
13460 X (2, (H, I), HALF), \
13461 X (3, (H, H, H), HALF), \
13462 X (3, (H, F, I), MIXED), \
13463 X (3, (F, H, I), MIXED), \
13464 X (3, (D, H, H), MIXED), \
13465 X (3, (D, H, S), MIXED)
13467 #define S2(A,B) NS_##A##B
13468 #define S3(A,B,C) NS_##A##B##C
13469 #define S4(A,B,C,D) NS_##A##B##C##D
13471 #define X(N, L, C) S##N L
13484 enum neon_shape_class
13493 #define X(N, L, C) SC_##C
13495 static enum neon_shape_class neon_shape_class
[] =
13514 /* Register widths of above. */
13515 static unsigned neon_shape_el_size
[] =
13527 struct neon_shape_info
13530 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13533 #define S2(A,B) { SE_##A, SE_##B }
13534 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13535 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13537 #define X(N, L, C) { N, S##N L }
13539 static struct neon_shape_info neon_shape_tab
[] =
13549 /* Bit masks used in type checking given instructions.
13550 'N_EQK' means the type must be the same as (or based on in some way) the key
13551 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13552 set, various other bits can be set as well in order to modify the meaning of
13553 the type constraint. */
13555 enum neon_type_mask
13579 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13580 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13581 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13582 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13583 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13584 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13585 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13586 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13587 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13588 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13589 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13591 N_MAX_NONSPECIAL
= N_P64
13594 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13596 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13597 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13598 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13599 #define N_S_32 (N_S8 | N_S16 | N_S32)
13600 #define N_F_16_32 (N_F16 | N_F32)
13601 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13602 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13603 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13604 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13606 /* Pass this as the first type argument to neon_check_type to ignore types
13608 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13610 /* Select a "shape" for the current instruction (describing register types or
13611 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13612 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13613 function of operand parsing, so this function doesn't need to be called.
13614 Shapes should be listed in order of decreasing length. */
13616 static enum neon_shape
13617 neon_select_shape (enum neon_shape shape
, ...)
13620 enum neon_shape first_shape
= shape
;
13622 /* Fix missing optional operands. FIXME: we don't know at this point how
13623 many arguments we should have, so this makes the assumption that we have
13624 > 1. This is true of all current Neon opcodes, I think, but may not be
13625 true in the future. */
13626 if (!inst
.operands
[1].present
)
13627 inst
.operands
[1] = inst
.operands
[0];
13629 va_start (ap
, shape
);
13631 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13636 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13638 if (!inst
.operands
[j
].present
)
13644 switch (neon_shape_tab
[shape
].el
[j
])
13646 /* If a .f16, .16, .u16, .s16 type specifier is given over
13647 a VFP single precision register operand, it's essentially
13648 means only half of the register is used.
13650 If the type specifier is given after the mnemonics, the
13651 information is stored in inst.vectype. If the type specifier
13652 is given after register operand, the information is stored
13653 in inst.operands[].vectype.
13655 When there is only one type specifier, and all the register
13656 operands are the same type of hardware register, the type
13657 specifier applies to all register operands.
13659 If no type specifier is given, the shape is inferred from
13660 operand information.
13663 vadd.f16 s0, s1, s2: NS_HHH
13664 vabs.f16 s0, s1: NS_HH
13665 vmov.f16 s0, r1: NS_HR
13666 vmov.f16 r0, s1: NS_RH
13667 vcvt.f16 r0, s1: NS_RH
13668 vcvt.f16.s32 s2, s2, #29: NS_HFI
13669 vcvt.f16.s32 s2, s2: NS_HF
13672 if (!(inst
.operands
[j
].isreg
13673 && inst
.operands
[j
].isvec
13674 && inst
.operands
[j
].issingle
13675 && !inst
.operands
[j
].isquad
13676 && ((inst
.vectype
.elems
== 1
13677 && inst
.vectype
.el
[0].size
== 16)
13678 || (inst
.vectype
.elems
> 1
13679 && inst
.vectype
.el
[j
].size
== 16)
13680 || (inst
.vectype
.elems
== 0
13681 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13682 && inst
.operands
[j
].vectype
.size
== 16))))
13687 if (!(inst
.operands
[j
].isreg
13688 && inst
.operands
[j
].isvec
13689 && inst
.operands
[j
].issingle
13690 && !inst
.operands
[j
].isquad
13691 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13692 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13693 || (inst
.vectype
.elems
== 0
13694 && (inst
.operands
[j
].vectype
.size
== 32
13695 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13700 if (!(inst
.operands
[j
].isreg
13701 && inst
.operands
[j
].isvec
13702 && !inst
.operands
[j
].isquad
13703 && !inst
.operands
[j
].issingle
))
13708 if (!(inst
.operands
[j
].isreg
13709 && !inst
.operands
[j
].isvec
))
13714 if (!(inst
.operands
[j
].isreg
13715 && inst
.operands
[j
].isvec
13716 && inst
.operands
[j
].isquad
13717 && !inst
.operands
[j
].issingle
))
13722 if (!(!inst
.operands
[j
].isreg
13723 && !inst
.operands
[j
].isscalar
))
13728 if (!(!inst
.operands
[j
].isreg
13729 && inst
.operands
[j
].isscalar
))
13739 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13740 /* We've matched all the entries in the shape table, and we don't
13741 have any left over operands which have not been matched. */
13747 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13748 first_error (_("invalid instruction shape"));
13753 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13754 means the Q bit should be set). */
13757 neon_quad (enum neon_shape shape
)
13759 return neon_shape_class
[shape
] == SC_QUAD
;
13763 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13766 /* Allow modification to be made to types which are constrained to be
13767 based on the key element, based on bits set alongside N_EQK. */
13768 if ((typebits
& N_EQK
) != 0)
13770 if ((typebits
& N_HLF
) != 0)
13772 else if ((typebits
& N_DBL
) != 0)
13774 if ((typebits
& N_SGN
) != 0)
13775 *g_type
= NT_signed
;
13776 else if ((typebits
& N_UNS
) != 0)
13777 *g_type
= NT_unsigned
;
13778 else if ((typebits
& N_INT
) != 0)
13779 *g_type
= NT_integer
;
13780 else if ((typebits
& N_FLT
) != 0)
13781 *g_type
= NT_float
;
13782 else if ((typebits
& N_SIZ
) != 0)
13783 *g_type
= NT_untyped
;
13787 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13788 operand type, i.e. the single type specified in a Neon instruction when it
13789 is the only one given. */
13791 static struct neon_type_el
13792 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13794 struct neon_type_el dest
= *key
;
13796 gas_assert ((thisarg
& N_EQK
) != 0);
13798 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13803 /* Convert Neon type and size into compact bitmask representation. */
13805 static enum neon_type_mask
13806 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13813 case 8: return N_8
;
13814 case 16: return N_16
;
13815 case 32: return N_32
;
13816 case 64: return N_64
;
13824 case 8: return N_I8
;
13825 case 16: return N_I16
;
13826 case 32: return N_I32
;
13827 case 64: return N_I64
;
13835 case 16: return N_F16
;
13836 case 32: return N_F32
;
13837 case 64: return N_F64
;
13845 case 8: return N_P8
;
13846 case 16: return N_P16
;
13847 case 64: return N_P64
;
13855 case 8: return N_S8
;
13856 case 16: return N_S16
;
13857 case 32: return N_S32
;
13858 case 64: return N_S64
;
13866 case 8: return N_U8
;
13867 case 16: return N_U16
;
13868 case 32: return N_U32
;
13869 case 64: return N_U64
;
13880 /* Convert compact Neon bitmask type representation to a type and size. Only
13881 handles the case where a single bit is set in the mask. */
13884 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13885 enum neon_type_mask mask
)
13887 if ((mask
& N_EQK
) != 0)
13890 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13892 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13894 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13896 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13901 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13903 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13904 *type
= NT_unsigned
;
13905 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13906 *type
= NT_integer
;
13907 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13908 *type
= NT_untyped
;
13909 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13911 else if ((mask
& (N_F_ALL
)) != 0)
13919 /* Modify a bitmask of allowed types. This is only needed for type
13923 modify_types_allowed (unsigned allowed
, unsigned mods
)
13926 enum neon_el_type type
;
13932 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13934 if (el_type_of_type_chk (&type
, &size
,
13935 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13937 neon_modify_type_size (mods
, &type
, &size
);
13938 destmask
|= type_chk_of_el_type (type
, size
);
13945 /* Check type and return type classification.
13946 The manual states (paraphrase): If one datatype is given, it indicates the
13948 - the second operand, if there is one
13949 - the operand, if there is no second operand
13950 - the result, if there are no operands.
13951 This isn't quite good enough though, so we use a concept of a "key" datatype
13952 which is set on a per-instruction basis, which is the one which matters when
13953 only one data type is written.
13954 Note: this function has side-effects (e.g. filling in missing operands). All
13955 Neon instructions should call it before performing bit encoding. */
13957 static struct neon_type_el
13958 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13961 unsigned i
, pass
, key_el
= 0;
13962 unsigned types
[NEON_MAX_TYPE_ELS
];
13963 enum neon_el_type k_type
= NT_invtype
;
13964 unsigned k_size
= -1u;
13965 struct neon_type_el badtype
= {NT_invtype
, -1};
13966 unsigned key_allowed
= 0;
13968 /* Optional registers in Neon instructions are always (not) in operand 1.
13969 Fill in the missing operand here, if it was omitted. */
13970 if (els
> 1 && !inst
.operands
[1].present
)
13971 inst
.operands
[1] = inst
.operands
[0];
13973 /* Suck up all the varargs. */
13975 for (i
= 0; i
< els
; i
++)
13977 unsigned thisarg
= va_arg (ap
, unsigned);
13978 if (thisarg
== N_IGNORE_TYPE
)
13983 types
[i
] = thisarg
;
13984 if ((thisarg
& N_KEY
) != 0)
13989 if (inst
.vectype
.elems
> 0)
13990 for (i
= 0; i
< els
; i
++)
13991 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13993 first_error (_("types specified in both the mnemonic and operands"));
13997 /* Duplicate inst.vectype elements here as necessary.
13998 FIXME: No idea if this is exactly the same as the ARM assembler,
13999 particularly when an insn takes one register and one non-register
14001 if (inst
.vectype
.elems
== 1 && els
> 1)
14004 inst
.vectype
.elems
= els
;
14005 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14006 for (j
= 0; j
< els
; j
++)
14008 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14011 else if (inst
.vectype
.elems
== 0 && els
> 0)
14014 /* No types were given after the mnemonic, so look for types specified
14015 after each operand. We allow some flexibility here; as long as the
14016 "key" operand has a type, we can infer the others. */
14017 for (j
= 0; j
< els
; j
++)
14018 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14019 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14021 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14023 for (j
= 0; j
< els
; j
++)
14024 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14025 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14030 first_error (_("operand types can't be inferred"));
14034 else if (inst
.vectype
.elems
!= els
)
14036 first_error (_("type specifier has the wrong number of parts"));
14040 for (pass
= 0; pass
< 2; pass
++)
14042 for (i
= 0; i
< els
; i
++)
14044 unsigned thisarg
= types
[i
];
14045 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14046 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14047 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14048 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14050 /* Decay more-specific signed & unsigned types to sign-insensitive
14051 integer types if sign-specific variants are unavailable. */
14052 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14053 && (types_allowed
& N_SU_ALL
) == 0)
14054 g_type
= NT_integer
;
14056 /* If only untyped args are allowed, decay any more specific types to
14057 them. Some instructions only care about signs for some element
14058 sizes, so handle that properly. */
14059 if (((types_allowed
& N_UNT
) == 0)
14060 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14061 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14062 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14063 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14064 g_type
= NT_untyped
;
14068 if ((thisarg
& N_KEY
) != 0)
14072 key_allowed
= thisarg
& ~N_KEY
;
14074 /* Check architecture constraint on FP16 extension. */
14076 && k_type
== NT_float
14077 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14079 inst
.error
= _(BAD_FP16
);
14086 if ((thisarg
& N_VFP
) != 0)
14088 enum neon_shape_el regshape
;
14089 unsigned regwidth
, match
;
14091 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14094 first_error (_("invalid instruction shape"));
14097 regshape
= neon_shape_tab
[ns
].el
[i
];
14098 regwidth
= neon_shape_el_size
[regshape
];
14100 /* In VFP mode, operands must match register widths. If we
14101 have a key operand, use its width, else use the width of
14102 the current operand. */
14108 /* FP16 will use a single precision register. */
14109 if (regwidth
== 32 && match
== 16)
14111 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14115 inst
.error
= _(BAD_FP16
);
14120 if (regwidth
!= match
)
14122 first_error (_("operand size must match register width"));
14127 if ((thisarg
& N_EQK
) == 0)
14129 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14131 if ((given_type
& types_allowed
) == 0)
14133 first_error (_("bad type in Neon instruction"));
14139 enum neon_el_type mod_k_type
= k_type
;
14140 unsigned mod_k_size
= k_size
;
14141 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14142 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14144 first_error (_("inconsistent types in Neon instruction"));
14152 return inst
.vectype
.el
[key_el
];
14155 /* Neon-style VFP instruction forwarding. */
14157 /* Thumb VFP instructions have 0xE in the condition field. */
14160 do_vfp_cond_or_thumb (void)
14165 inst
.instruction
|= 0xe0000000;
14167 inst
.instruction
|= inst
.cond
<< 28;
14170 /* Look up and encode a simple mnemonic, for use as a helper function for the
14171 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14172 etc. It is assumed that operand parsing has already been done, and that the
14173 operands are in the form expected by the given opcode (this isn't necessarily
14174 the same as the form in which they were parsed, hence some massaging must
14175 take place before this function is called).
14176 Checks current arch version against that in the looked-up opcode. */
14179 do_vfp_nsyn_opcode (const char *opname
)
14181 const struct asm_opcode
*opcode
;
14183 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14188 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14189 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14196 inst
.instruction
= opcode
->tvalue
;
14197 opcode
->tencode ();
14201 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14202 opcode
->aencode ();
14207 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14209 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14211 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14214 do_vfp_nsyn_opcode ("fadds");
14216 do_vfp_nsyn_opcode ("fsubs");
14218 /* ARMv8.2 fp16 instruction. */
14220 do_scalar_fp16_v82_encode ();
14225 do_vfp_nsyn_opcode ("faddd");
14227 do_vfp_nsyn_opcode ("fsubd");
14231 /* Check operand types to see if this is a VFP instruction, and if so call
14235 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14237 enum neon_shape rs
;
14238 struct neon_type_el et
;
14243 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14244 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14248 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14249 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14250 N_F_ALL
| N_KEY
| N_VFP
);
14257 if (et
.type
!= NT_invtype
)
14268 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14270 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14272 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14275 do_vfp_nsyn_opcode ("fmacs");
14277 do_vfp_nsyn_opcode ("fnmacs");
14279 /* ARMv8.2 fp16 instruction. */
14281 do_scalar_fp16_v82_encode ();
14286 do_vfp_nsyn_opcode ("fmacd");
14288 do_vfp_nsyn_opcode ("fnmacd");
14293 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14295 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14297 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14300 do_vfp_nsyn_opcode ("ffmas");
14302 do_vfp_nsyn_opcode ("ffnmas");
14304 /* ARMv8.2 fp16 instruction. */
14306 do_scalar_fp16_v82_encode ();
14311 do_vfp_nsyn_opcode ("ffmad");
14313 do_vfp_nsyn_opcode ("ffnmad");
14318 do_vfp_nsyn_mul (enum neon_shape rs
)
14320 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14322 do_vfp_nsyn_opcode ("fmuls");
14324 /* ARMv8.2 fp16 instruction. */
14326 do_scalar_fp16_v82_encode ();
14329 do_vfp_nsyn_opcode ("fmuld");
14333 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14335 int is_neg
= (inst
.instruction
& 0x80) != 0;
14336 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14338 if (rs
== NS_FF
|| rs
== NS_HH
)
14341 do_vfp_nsyn_opcode ("fnegs");
14343 do_vfp_nsyn_opcode ("fabss");
14345 /* ARMv8.2 fp16 instruction. */
14347 do_scalar_fp16_v82_encode ();
14352 do_vfp_nsyn_opcode ("fnegd");
14354 do_vfp_nsyn_opcode ("fabsd");
14358 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14359 insns belong to Neon, and are handled elsewhere. */
14362 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14364 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14368 do_vfp_nsyn_opcode ("fldmdbs");
14370 do_vfp_nsyn_opcode ("fldmias");
14375 do_vfp_nsyn_opcode ("fstmdbs");
14377 do_vfp_nsyn_opcode ("fstmias");
14382 do_vfp_nsyn_sqrt (void)
14384 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14385 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14387 if (rs
== NS_FF
|| rs
== NS_HH
)
14389 do_vfp_nsyn_opcode ("fsqrts");
14391 /* ARMv8.2 fp16 instruction. */
14393 do_scalar_fp16_v82_encode ();
14396 do_vfp_nsyn_opcode ("fsqrtd");
14400 do_vfp_nsyn_div (void)
14402 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14403 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14404 N_F_ALL
| N_KEY
| N_VFP
);
14406 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14408 do_vfp_nsyn_opcode ("fdivs");
14410 /* ARMv8.2 fp16 instruction. */
14412 do_scalar_fp16_v82_encode ();
14415 do_vfp_nsyn_opcode ("fdivd");
14419 do_vfp_nsyn_nmul (void)
14421 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14422 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14423 N_F_ALL
| N_KEY
| N_VFP
);
14425 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14427 NEON_ENCODE (SINGLE
, inst
);
14428 do_vfp_sp_dyadic ();
14430 /* ARMv8.2 fp16 instruction. */
14432 do_scalar_fp16_v82_encode ();
14436 NEON_ENCODE (DOUBLE
, inst
);
14437 do_vfp_dp_rd_rn_rm ();
14439 do_vfp_cond_or_thumb ();
14444 do_vfp_nsyn_cmp (void)
14446 enum neon_shape rs
;
14447 if (inst
.operands
[1].isreg
)
14449 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14450 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14452 if (rs
== NS_FF
|| rs
== NS_HH
)
14454 NEON_ENCODE (SINGLE
, inst
);
14455 do_vfp_sp_monadic ();
14459 NEON_ENCODE (DOUBLE
, inst
);
14460 do_vfp_dp_rd_rm ();
14465 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14466 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14468 switch (inst
.instruction
& 0x0fffffff)
14471 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14474 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14480 if (rs
== NS_FI
|| rs
== NS_HI
)
14482 NEON_ENCODE (SINGLE
, inst
);
14483 do_vfp_sp_compare_z ();
14487 NEON_ENCODE (DOUBLE
, inst
);
14491 do_vfp_cond_or_thumb ();
14493 /* ARMv8.2 fp16 instruction. */
14494 if (rs
== NS_HI
|| rs
== NS_HH
)
14495 do_scalar_fp16_v82_encode ();
14499 nsyn_insert_sp (void)
14501 inst
.operands
[1] = inst
.operands
[0];
14502 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14503 inst
.operands
[0].reg
= REG_SP
;
14504 inst
.operands
[0].isreg
= 1;
14505 inst
.operands
[0].writeback
= 1;
14506 inst
.operands
[0].present
= 1;
14510 do_vfp_nsyn_push (void)
14514 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14515 _("register list must contain at least 1 and at most 16 "
14518 if (inst
.operands
[1].issingle
)
14519 do_vfp_nsyn_opcode ("fstmdbs");
14521 do_vfp_nsyn_opcode ("fstmdbd");
14525 do_vfp_nsyn_pop (void)
14529 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14530 _("register list must contain at least 1 and at most 16 "
14533 if (inst
.operands
[1].issingle
)
14534 do_vfp_nsyn_opcode ("fldmias");
14536 do_vfp_nsyn_opcode ("fldmiad");
14539 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14540 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14543 neon_dp_fixup (struct arm_it
* insn
)
14545 unsigned int i
= insn
->instruction
;
14550 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14561 insn
->instruction
= i
;
14564 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14568 neon_logbits (unsigned x
)
14570 return ffs (x
) - 4;
14573 #define LOW4(R) ((R) & 0xf)
14574 #define HI1(R) (((R) >> 4) & 1)
14576 /* Encode insns with bit pattern:
14578 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14579 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14581 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14582 different meaning for some instruction. */
14585 neon_three_same (int isquad
, int ubit
, int size
)
14587 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14588 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14589 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14590 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14591 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14592 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14593 inst
.instruction
|= (isquad
!= 0) << 6;
14594 inst
.instruction
|= (ubit
!= 0) << 24;
14596 inst
.instruction
|= neon_logbits (size
) << 20;
14598 neon_dp_fixup (&inst
);
14601 /* Encode instructions of the form:
14603 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14604 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14606 Don't write size if SIZE == -1. */
14609 neon_two_same (int qbit
, int ubit
, int size
)
14611 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14612 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14613 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14614 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14615 inst
.instruction
|= (qbit
!= 0) << 6;
14616 inst
.instruction
|= (ubit
!= 0) << 24;
14619 inst
.instruction
|= neon_logbits (size
) << 18;
14621 neon_dp_fixup (&inst
);
14624 /* Neon instruction encoders, in approximate order of appearance. */
14627 do_neon_dyadic_i_su (void)
14629 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14630 struct neon_type_el et
= neon_check_type (3, rs
,
14631 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14632 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14636 do_neon_dyadic_i64_su (void)
14638 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14639 struct neon_type_el et
= neon_check_type (3, rs
,
14640 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14641 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14645 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14648 unsigned size
= et
.size
>> 3;
14649 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14650 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14651 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14652 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14653 inst
.instruction
|= (isquad
!= 0) << 6;
14654 inst
.instruction
|= immbits
<< 16;
14655 inst
.instruction
|= (size
>> 3) << 7;
14656 inst
.instruction
|= (size
& 0x7) << 19;
14658 inst
.instruction
|= (uval
!= 0) << 24;
14660 neon_dp_fixup (&inst
);
14664 do_neon_shl_imm (void)
14666 if (!inst
.operands
[2].isreg
)
14668 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14669 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14670 int imm
= inst
.operands
[2].imm
;
14672 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14673 _("immediate out of range for shift"));
14674 NEON_ENCODE (IMMED
, inst
);
14675 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14679 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14680 struct neon_type_el et
= neon_check_type (3, rs
,
14681 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14684 /* VSHL/VQSHL 3-register variants have syntax such as:
14686 whereas other 3-register operations encoded by neon_three_same have
14689 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14691 tmp
= inst
.operands
[2].reg
;
14692 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14693 inst
.operands
[1].reg
= tmp
;
14694 NEON_ENCODE (INTEGER
, inst
);
14695 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14700 do_neon_qshl_imm (void)
14702 if (!inst
.operands
[2].isreg
)
14704 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14705 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14706 int imm
= inst
.operands
[2].imm
;
14708 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14709 _("immediate out of range for shift"));
14710 NEON_ENCODE (IMMED
, inst
);
14711 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14715 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14716 struct neon_type_el et
= neon_check_type (3, rs
,
14717 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14720 /* See note in do_neon_shl_imm. */
14721 tmp
= inst
.operands
[2].reg
;
14722 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14723 inst
.operands
[1].reg
= tmp
;
14724 NEON_ENCODE (INTEGER
, inst
);
14725 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14730 do_neon_rshl (void)
14732 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14733 struct neon_type_el et
= neon_check_type (3, rs
,
14734 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14737 tmp
= inst
.operands
[2].reg
;
14738 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14739 inst
.operands
[1].reg
= tmp
;
14740 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14744 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14746 /* Handle .I8 pseudo-instructions. */
14749 /* Unfortunately, this will make everything apart from zero out-of-range.
14750 FIXME is this the intended semantics? There doesn't seem much point in
14751 accepting .I8 if so. */
14752 immediate
|= immediate
<< 8;
14758 if (immediate
== (immediate
& 0x000000ff))
14760 *immbits
= immediate
;
14763 else if (immediate
== (immediate
& 0x0000ff00))
14765 *immbits
= immediate
>> 8;
14768 else if (immediate
== (immediate
& 0x00ff0000))
14770 *immbits
= immediate
>> 16;
14773 else if (immediate
== (immediate
& 0xff000000))
14775 *immbits
= immediate
>> 24;
14778 if ((immediate
& 0xffff) != (immediate
>> 16))
14779 goto bad_immediate
;
14780 immediate
&= 0xffff;
14783 if (immediate
== (immediate
& 0x000000ff))
14785 *immbits
= immediate
;
14788 else if (immediate
== (immediate
& 0x0000ff00))
14790 *immbits
= immediate
>> 8;
14795 first_error (_("immediate value out of range"));
14800 do_neon_logic (void)
14802 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14804 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14805 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14806 /* U bit and size field were set as part of the bitmask. */
14807 NEON_ENCODE (INTEGER
, inst
);
14808 neon_three_same (neon_quad (rs
), 0, -1);
14812 const int three_ops_form
= (inst
.operands
[2].present
14813 && !inst
.operands
[2].isreg
);
14814 const int immoperand
= (three_ops_form
? 2 : 1);
14815 enum neon_shape rs
= (three_ops_form
14816 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14817 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14818 struct neon_type_el et
= neon_check_type (2, rs
,
14819 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14820 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14824 if (et
.type
== NT_invtype
)
14827 if (three_ops_form
)
14828 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14829 _("first and second operands shall be the same register"));
14831 NEON_ENCODE (IMMED
, inst
);
14833 immbits
= inst
.operands
[immoperand
].imm
;
14836 /* .i64 is a pseudo-op, so the immediate must be a repeating
14838 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14839 inst
.operands
[immoperand
].reg
: 0))
14841 /* Set immbits to an invalid constant. */
14842 immbits
= 0xdeadbeef;
14849 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14853 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14857 /* Pseudo-instruction for VBIC. */
14858 neon_invert_size (&immbits
, 0, et
.size
);
14859 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14863 /* Pseudo-instruction for VORR. */
14864 neon_invert_size (&immbits
, 0, et
.size
);
14865 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14875 inst
.instruction
|= neon_quad (rs
) << 6;
14876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14878 inst
.instruction
|= cmode
<< 8;
14879 neon_write_immbits (immbits
);
14881 neon_dp_fixup (&inst
);
14886 do_neon_bitfield (void)
14888 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14889 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14890 neon_three_same (neon_quad (rs
), 0, -1);
14894 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14897 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14898 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14900 if (et
.type
== NT_float
)
14902 NEON_ENCODE (FLOAT
, inst
);
14903 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14907 NEON_ENCODE (INTEGER
, inst
);
14908 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14913 do_neon_dyadic_if_su (void)
14915 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14919 do_neon_dyadic_if_su_d (void)
14921 /* This version only allow D registers, but that constraint is enforced during
14922 operand parsing so we don't need to do anything extra here. */
14923 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14927 do_neon_dyadic_if_i_d (void)
14929 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14930 affected if we specify unsigned args. */
14931 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14934 enum vfp_or_neon_is_neon_bits
14937 NEON_CHECK_ARCH
= 2,
14938 NEON_CHECK_ARCH8
= 4
14941 /* Call this function if an instruction which may have belonged to the VFP or
14942 Neon instruction sets, but turned out to be a Neon instruction (due to the
14943 operand types involved, etc.). We have to check and/or fix-up a couple of
14946 - Make sure the user hasn't attempted to make a Neon instruction
14948 - Alter the value in the condition code field if necessary.
14949 - Make sure that the arch supports Neon instructions.
14951 Which of these operations take place depends on bits from enum
14952 vfp_or_neon_is_neon_bits.
14954 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14955 current instruction's condition is COND_ALWAYS, the condition field is
14956 changed to inst.uncond_value. This is necessary because instructions shared
14957 between VFP and Neon may be conditional for the VFP variants only, and the
14958 unconditional Neon version must have, e.g., 0xF in the condition field. */
14961 vfp_or_neon_is_neon (unsigned check
)
14963 /* Conditions are always legal in Thumb mode (IT blocks). */
14964 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14966 if (inst
.cond
!= COND_ALWAYS
)
14968 first_error (_(BAD_COND
));
14971 if (inst
.uncond_value
!= -1)
14972 inst
.instruction
|= inst
.uncond_value
<< 28;
14975 if ((check
& NEON_CHECK_ARCH
)
14976 && !mark_feature_used (&fpu_neon_ext_v1
))
14978 first_error (_(BAD_FPU
));
14982 if ((check
& NEON_CHECK_ARCH8
)
14983 && !mark_feature_used (&fpu_neon_ext_armv8
))
14985 first_error (_(BAD_FPU
));
14993 do_neon_addsub_if_i (void)
14995 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14998 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15001 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15002 affected if we specify unsigned args. */
15003 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15006 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15008 V<op> A,B (A is operand 0, B is operand 2)
15013 so handle that case specially. */
15016 neon_exchange_operands (void)
15018 if (inst
.operands
[1].present
)
15020 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15022 /* Swap operands[1] and operands[2]. */
15023 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15024 inst
.operands
[1] = inst
.operands
[2];
15025 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15030 inst
.operands
[1] = inst
.operands
[2];
15031 inst
.operands
[2] = inst
.operands
[0];
15036 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15038 if (inst
.operands
[2].isreg
)
15041 neon_exchange_operands ();
15042 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15046 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15047 struct neon_type_el et
= neon_check_type (2, rs
,
15048 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15050 NEON_ENCODE (IMMED
, inst
);
15051 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15052 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15053 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15054 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15055 inst
.instruction
|= neon_quad (rs
) << 6;
15056 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15057 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15059 neon_dp_fixup (&inst
);
15066 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15070 do_neon_cmp_inv (void)
15072 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15078 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15081 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15082 scalars, which are encoded in 5 bits, M : Rm.
15083 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15084 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15087 Dot Product instructions are similar to multiply instructions except elsize
15088 should always be 32.
15090 This function translates SCALAR, which is GAS's internal encoding of indexed
15091 scalar register, to raw encoding. There is also register and index range
15092 check based on ELSIZE. */
15095 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15097 unsigned regno
= NEON_SCALAR_REG (scalar
);
15098 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15103 if (regno
> 7 || elno
> 3)
15105 return regno
| (elno
<< 3);
15108 if (regno
> 15 || elno
> 1)
15110 return regno
| (elno
<< 4);
15114 first_error (_("scalar out of range for multiply instruction"));
15120 /* Encode multiply / multiply-accumulate scalar instructions. */
15123 neon_mul_mac (struct neon_type_el et
, int ubit
)
15127 /* Give a more helpful error message if we have an invalid type. */
15128 if (et
.type
== NT_invtype
)
15131 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15136 inst
.instruction
|= LOW4 (scalar
);
15137 inst
.instruction
|= HI1 (scalar
) << 5;
15138 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15139 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15140 inst
.instruction
|= (ubit
!= 0) << 24;
15142 neon_dp_fixup (&inst
);
15146 do_neon_mac_maybe_scalar (void)
15148 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15151 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15154 if (inst
.operands
[2].isscalar
)
15156 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15157 struct neon_type_el et
= neon_check_type (3, rs
,
15158 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15159 NEON_ENCODE (SCALAR
, inst
);
15160 neon_mul_mac (et
, neon_quad (rs
));
15164 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15165 affected if we specify unsigned args. */
15166 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15171 do_neon_fmac (void)
15173 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15176 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15179 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15185 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15186 struct neon_type_el et
= neon_check_type (3, rs
,
15187 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15188 neon_three_same (neon_quad (rs
), 0, et
.size
);
15191 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15192 same types as the MAC equivalents. The polynomial type for this instruction
15193 is encoded the same as the integer type. */
15198 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15201 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15204 if (inst
.operands
[2].isscalar
)
15205 do_neon_mac_maybe_scalar ();
15207 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15211 do_neon_qdmulh (void)
15213 if (inst
.operands
[2].isscalar
)
15215 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15216 struct neon_type_el et
= neon_check_type (3, rs
,
15217 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15218 NEON_ENCODE (SCALAR
, inst
);
15219 neon_mul_mac (et
, neon_quad (rs
));
15223 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15224 struct neon_type_el et
= neon_check_type (3, rs
,
15225 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15226 NEON_ENCODE (INTEGER
, inst
);
15227 /* The U bit (rounding) comes from bit mask. */
15228 neon_three_same (neon_quad (rs
), 0, et
.size
);
15233 do_neon_qrdmlah (void)
15235 /* Check we're on the correct architecture. */
15236 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15238 _("instruction form not available on this architecture.");
15239 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15241 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15242 record_feature_use (&fpu_neon_ext_v8_1
);
15245 if (inst
.operands
[2].isscalar
)
15247 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15248 struct neon_type_el et
= neon_check_type (3, rs
,
15249 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15250 NEON_ENCODE (SCALAR
, inst
);
15251 neon_mul_mac (et
, neon_quad (rs
));
15255 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15256 struct neon_type_el et
= neon_check_type (3, rs
,
15257 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15258 NEON_ENCODE (INTEGER
, inst
);
15259 /* The U bit (rounding) comes from bit mask. */
15260 neon_three_same (neon_quad (rs
), 0, et
.size
);
15265 do_neon_fcmp_absolute (void)
15267 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15268 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15269 N_F_16_32
| N_KEY
);
15270 /* Size field comes from bit mask. */
15271 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15275 do_neon_fcmp_absolute_inv (void)
15277 neon_exchange_operands ();
15278 do_neon_fcmp_absolute ();
15282 do_neon_step (void)
15284 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15285 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15286 N_F_16_32
| N_KEY
);
15287 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15291 do_neon_abs_neg (void)
15293 enum neon_shape rs
;
15294 struct neon_type_el et
;
15296 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15299 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15302 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15303 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15307 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15309 inst
.instruction
|= neon_quad (rs
) << 6;
15310 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15311 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15313 neon_dp_fixup (&inst
);
15319 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15320 struct neon_type_el et
= neon_check_type (2, rs
,
15321 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15322 int imm
= inst
.operands
[2].imm
;
15323 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15324 _("immediate out of range for insert"));
15325 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15331 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15332 struct neon_type_el et
= neon_check_type (2, rs
,
15333 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15334 int imm
= inst
.operands
[2].imm
;
15335 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15336 _("immediate out of range for insert"));
15337 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15341 do_neon_qshlu_imm (void)
15343 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15344 struct neon_type_el et
= neon_check_type (2, rs
,
15345 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15346 int imm
= inst
.operands
[2].imm
;
15347 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15348 _("immediate out of range for shift"));
15349 /* Only encodes the 'U present' variant of the instruction.
15350 In this case, signed types have OP (bit 8) set to 0.
15351 Unsigned types have OP set to 1. */
15352 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15353 /* The rest of the bits are the same as other immediate shifts. */
15354 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15358 do_neon_qmovn (void)
15360 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15361 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15362 /* Saturating move where operands can be signed or unsigned, and the
15363 destination has the same signedness. */
15364 NEON_ENCODE (INTEGER
, inst
);
15365 if (et
.type
== NT_unsigned
)
15366 inst
.instruction
|= 0xc0;
15368 inst
.instruction
|= 0x80;
15369 neon_two_same (0, 1, et
.size
/ 2);
15373 do_neon_qmovun (void)
15375 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15376 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15377 /* Saturating move with unsigned results. Operands must be signed. */
15378 NEON_ENCODE (INTEGER
, inst
);
15379 neon_two_same (0, 1, et
.size
/ 2);
15383 do_neon_rshift_sat_narrow (void)
15385 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15386 or unsigned. If operands are unsigned, results must also be unsigned. */
15387 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15388 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15389 int imm
= inst
.operands
[2].imm
;
15390 /* This gets the bounds check, size encoding and immediate bits calculation
15394 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15395 VQMOVN.I<size> <Dd>, <Qm>. */
15398 inst
.operands
[2].present
= 0;
15399 inst
.instruction
= N_MNEM_vqmovn
;
15404 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15405 _("immediate out of range"));
15406 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15410 do_neon_rshift_sat_narrow_u (void)
15412 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15413 or unsigned. If operands are unsigned, results must also be unsigned. */
15414 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15415 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15416 int imm
= inst
.operands
[2].imm
;
15417 /* This gets the bounds check, size encoding and immediate bits calculation
15421 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15422 VQMOVUN.I<size> <Dd>, <Qm>. */
15425 inst
.operands
[2].present
= 0;
15426 inst
.instruction
= N_MNEM_vqmovun
;
15431 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15432 _("immediate out of range"));
15433 /* FIXME: The manual is kind of unclear about what value U should have in
15434 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15436 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15440 do_neon_movn (void)
15442 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15443 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15444 NEON_ENCODE (INTEGER
, inst
);
15445 neon_two_same (0, 1, et
.size
/ 2);
15449 do_neon_rshift_narrow (void)
15451 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15452 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15453 int imm
= inst
.operands
[2].imm
;
15454 /* This gets the bounds check, size encoding and immediate bits calculation
15458 /* If immediate is zero then we are a pseudo-instruction for
15459 VMOVN.I<size> <Dd>, <Qm> */
15462 inst
.operands
[2].present
= 0;
15463 inst
.instruction
= N_MNEM_vmovn
;
15468 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15469 _("immediate out of range for narrowing operation"));
15470 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15474 do_neon_shll (void)
15476 /* FIXME: Type checking when lengthening. */
15477 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15478 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15479 unsigned imm
= inst
.operands
[2].imm
;
15481 if (imm
== et
.size
)
15483 /* Maximum shift variant. */
15484 NEON_ENCODE (INTEGER
, inst
);
15485 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15486 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15487 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15488 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15489 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15491 neon_dp_fixup (&inst
);
15495 /* A more-specific type check for non-max versions. */
15496 et
= neon_check_type (2, NS_QDI
,
15497 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15498 NEON_ENCODE (IMMED
, inst
);
15499 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15503 /* Check the various types for the VCVT instruction, and return which version
15504 the current instruction is. */
15506 #define CVT_FLAVOUR_VAR \
15507 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15508 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15509 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15510 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15511 /* Half-precision conversions. */ \
15512 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15513 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15514 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15515 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15516 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15517 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15518 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15519 Compared with single/double precision variants, only the co-processor \
15520 field is different, so the encoding flow is reused here. */ \
15521 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15522 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15523 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15524 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15525 /* VFP instructions. */ \
15526 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15527 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15528 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15529 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15530 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15531 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15532 /* VFP instructions with bitshift. */ \
15533 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15534 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15535 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15536 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15537 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15538 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15539 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15540 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15542 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15543 neon_cvt_flavour_##C,
15545 /* The different types of conversions we can do. */
15546 enum neon_cvt_flavour
15549 neon_cvt_flavour_invalid
,
15550 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15555 static enum neon_cvt_flavour
15556 get_neon_cvt_flavour (enum neon_shape rs
)
15558 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15559 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15560 if (et.type != NT_invtype) \
15562 inst.error = NULL; \
15563 return (neon_cvt_flavour_##C); \
15566 struct neon_type_el et
;
15567 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15568 || rs
== NS_FF
) ? N_VFP
: 0;
15569 /* The instruction versions which take an immediate take one register
15570 argument, which is extended to the width of the full register. Thus the
15571 "source" and "destination" registers must have the same width. Hack that
15572 here by making the size equal to the key (wider, in this case) operand. */
15573 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15577 return neon_cvt_flavour_invalid
;
15592 /* Neon-syntax VFP conversions. */
15595 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15597 const char *opname
= 0;
15599 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15600 || rs
== NS_FHI
|| rs
== NS_HFI
)
15602 /* Conversions with immediate bitshift. */
15603 const char *enc
[] =
15605 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15611 if (flavour
< (int) ARRAY_SIZE (enc
))
15613 opname
= enc
[flavour
];
15614 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15615 _("operands 0 and 1 must be the same register"));
15616 inst
.operands
[1] = inst
.operands
[2];
15617 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15622 /* Conversions without bitshift. */
15623 const char *enc
[] =
15625 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15631 if (flavour
< (int) ARRAY_SIZE (enc
))
15632 opname
= enc
[flavour
];
15636 do_vfp_nsyn_opcode (opname
);
15638 /* ARMv8.2 fp16 VCVT instruction. */
15639 if (flavour
== neon_cvt_flavour_s32_f16
15640 || flavour
== neon_cvt_flavour_u32_f16
15641 || flavour
== neon_cvt_flavour_f16_u32
15642 || flavour
== neon_cvt_flavour_f16_s32
)
15643 do_scalar_fp16_v82_encode ();
15647 do_vfp_nsyn_cvtz (void)
15649 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15650 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15651 const char *enc
[] =
15653 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15659 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15660 do_vfp_nsyn_opcode (enc
[flavour
]);
15664 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15665 enum neon_cvt_mode mode
)
15670 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15671 D register operands. */
15672 if (flavour
== neon_cvt_flavour_s32_f64
15673 || flavour
== neon_cvt_flavour_u32_f64
)
15674 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15677 if (flavour
== neon_cvt_flavour_s32_f16
15678 || flavour
== neon_cvt_flavour_u32_f16
)
15679 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15682 set_it_insn_type (OUTSIDE_IT_INSN
);
15686 case neon_cvt_flavour_s32_f64
:
15690 case neon_cvt_flavour_s32_f32
:
15694 case neon_cvt_flavour_s32_f16
:
15698 case neon_cvt_flavour_u32_f64
:
15702 case neon_cvt_flavour_u32_f32
:
15706 case neon_cvt_flavour_u32_f16
:
15711 first_error (_("invalid instruction shape"));
15717 case neon_cvt_mode_a
: rm
= 0; break;
15718 case neon_cvt_mode_n
: rm
= 1; break;
15719 case neon_cvt_mode_p
: rm
= 2; break;
15720 case neon_cvt_mode_m
: rm
= 3; break;
15721 default: first_error (_("invalid rounding mode")); return;
15724 NEON_ENCODE (FPV8
, inst
);
15725 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15726 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15727 inst
.instruction
|= sz
<< 8;
15729 /* ARMv8.2 fp16 VCVT instruction. */
15730 if (flavour
== neon_cvt_flavour_s32_f16
15731 ||flavour
== neon_cvt_flavour_u32_f16
)
15732 do_scalar_fp16_v82_encode ();
15733 inst
.instruction
|= op
<< 7;
15734 inst
.instruction
|= rm
<< 16;
15735 inst
.instruction
|= 0xf0000000;
15736 inst
.is_neon
= TRUE
;
15740 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15742 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15743 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15744 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15746 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15748 if (flavour
== neon_cvt_flavour_invalid
)
15751 /* PR11109: Handle round-to-zero for VCVT conversions. */
15752 if (mode
== neon_cvt_mode_z
15753 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15754 && (flavour
== neon_cvt_flavour_s16_f16
15755 || flavour
== neon_cvt_flavour_u16_f16
15756 || flavour
== neon_cvt_flavour_s32_f32
15757 || flavour
== neon_cvt_flavour_u32_f32
15758 || flavour
== neon_cvt_flavour_s32_f64
15759 || flavour
== neon_cvt_flavour_u32_f64
)
15760 && (rs
== NS_FD
|| rs
== NS_FF
))
15762 do_vfp_nsyn_cvtz ();
15766 /* ARMv8.2 fp16 VCVT conversions. */
15767 if (mode
== neon_cvt_mode_z
15768 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15769 && (flavour
== neon_cvt_flavour_s32_f16
15770 || flavour
== neon_cvt_flavour_u32_f16
)
15773 do_vfp_nsyn_cvtz ();
15774 do_scalar_fp16_v82_encode ();
15778 /* VFP rather than Neon conversions. */
15779 if (flavour
>= neon_cvt_flavour_first_fp
)
15781 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15782 do_vfp_nsyn_cvt (rs
, flavour
);
15784 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15795 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15796 0x0000100, 0x1000100, 0x0, 0x1000000};
15798 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15801 /* Fixed-point conversion with #0 immediate is encoded as an
15802 integer conversion. */
15803 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15805 NEON_ENCODE (IMMED
, inst
);
15806 if (flavour
!= neon_cvt_flavour_invalid
)
15807 inst
.instruction
|= enctab
[flavour
];
15808 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15809 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15810 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15811 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15812 inst
.instruction
|= neon_quad (rs
) << 6;
15813 inst
.instruction
|= 1 << 21;
15814 if (flavour
< neon_cvt_flavour_s16_f16
)
15816 inst
.instruction
|= 1 << 21;
15817 immbits
= 32 - inst
.operands
[2].imm
;
15818 inst
.instruction
|= immbits
<< 16;
15822 inst
.instruction
|= 3 << 20;
15823 immbits
= 16 - inst
.operands
[2].imm
;
15824 inst
.instruction
|= immbits
<< 16;
15825 inst
.instruction
&= ~(1 << 9);
15828 neon_dp_fixup (&inst
);
15834 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15836 NEON_ENCODE (FLOAT
, inst
);
15837 set_it_insn_type (OUTSIDE_IT_INSN
);
15839 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15842 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15843 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15844 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15845 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15846 inst
.instruction
|= neon_quad (rs
) << 6;
15847 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15848 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15849 inst
.instruction
|= mode
<< 8;
15850 if (flavour
== neon_cvt_flavour_u16_f16
15851 || flavour
== neon_cvt_flavour_s16_f16
)
15852 /* Mask off the original size bits and reencode them. */
15853 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15856 inst
.instruction
|= 0xfc000000;
15858 inst
.instruction
|= 0xf0000000;
15864 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15865 0x100, 0x180, 0x0, 0x080};
15867 NEON_ENCODE (INTEGER
, inst
);
15869 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15872 if (flavour
!= neon_cvt_flavour_invalid
)
15873 inst
.instruction
|= enctab
[flavour
];
15875 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15876 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15877 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15878 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15879 inst
.instruction
|= neon_quad (rs
) << 6;
15880 if (flavour
>= neon_cvt_flavour_s16_f16
15881 && flavour
<= neon_cvt_flavour_f16_u16
)
15882 /* Half precision. */
15883 inst
.instruction
|= 1 << 18;
15885 inst
.instruction
|= 2 << 18;
15887 neon_dp_fixup (&inst
);
15892 /* Half-precision conversions for Advanced SIMD -- neon. */
15897 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15899 as_bad (_("operand size must match register width"));
15904 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15906 as_bad (_("operand size must match register width"));
15911 inst
.instruction
= 0x3b60600;
15913 inst
.instruction
= 0x3b60700;
15915 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15916 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15917 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15918 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15919 neon_dp_fixup (&inst
);
15923 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15924 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15925 do_vfp_nsyn_cvt (rs
, flavour
);
15927 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15932 do_neon_cvtr (void)
15934 do_neon_cvt_1 (neon_cvt_mode_x
);
15940 do_neon_cvt_1 (neon_cvt_mode_z
);
15944 do_neon_cvta (void)
15946 do_neon_cvt_1 (neon_cvt_mode_a
);
15950 do_neon_cvtn (void)
15952 do_neon_cvt_1 (neon_cvt_mode_n
);
15956 do_neon_cvtp (void)
15958 do_neon_cvt_1 (neon_cvt_mode_p
);
15962 do_neon_cvtm (void)
15964 do_neon_cvt_1 (neon_cvt_mode_m
);
15968 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15971 mark_feature_used (&fpu_vfp_ext_armv8
);
15973 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15974 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15975 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15976 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15977 inst
.instruction
|= to
? 0x10000 : 0;
15978 inst
.instruction
|= t
? 0x80 : 0;
15979 inst
.instruction
|= is_double
? 0x100 : 0;
15980 do_vfp_cond_or_thumb ();
15984 do_neon_cvttb_1 (bfd_boolean t
)
15986 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15987 NS_DF
, NS_DH
, NS_NULL
);
15991 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15994 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15996 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15999 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16001 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16003 /* The VCVTB and VCVTT instructions with D-register operands
16004 don't work for SP only targets. */
16005 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16009 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16011 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16013 /* The VCVTB and VCVTT instructions with D-register operands
16014 don't work for SP only targets. */
16015 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16019 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16026 do_neon_cvtb (void)
16028 do_neon_cvttb_1 (FALSE
);
16033 do_neon_cvtt (void)
16035 do_neon_cvttb_1 (TRUE
);
16039 neon_move_immediate (void)
16041 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16042 struct neon_type_el et
= neon_check_type (2, rs
,
16043 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16044 unsigned immlo
, immhi
= 0, immbits
;
16045 int op
, cmode
, float_p
;
16047 constraint (et
.type
== NT_invtype
,
16048 _("operand size must be specified for immediate VMOV"));
16050 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16051 op
= (inst
.instruction
& (1 << 5)) != 0;
16053 immlo
= inst
.operands
[1].imm
;
16054 if (inst
.operands
[1].regisimm
)
16055 immhi
= inst
.operands
[1].reg
;
16057 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16058 _("immediate has bits set outside the operand size"));
16060 float_p
= inst
.operands
[1].immisfloat
;
16062 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16063 et
.size
, et
.type
)) == FAIL
)
16065 /* Invert relevant bits only. */
16066 neon_invert_size (&immlo
, &immhi
, et
.size
);
16067 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16068 with one or the other; those cases are caught by
16069 neon_cmode_for_move_imm. */
16071 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16072 &op
, et
.size
, et
.type
)) == FAIL
)
16074 first_error (_("immediate out of range"));
16079 inst
.instruction
&= ~(1 << 5);
16080 inst
.instruction
|= op
<< 5;
16082 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16083 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16084 inst
.instruction
|= neon_quad (rs
) << 6;
16085 inst
.instruction
|= cmode
<< 8;
16087 neon_write_immbits (immbits
);
16093 if (inst
.operands
[1].isreg
)
16095 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16097 NEON_ENCODE (INTEGER
, inst
);
16098 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16099 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16100 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16101 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16102 inst
.instruction
|= neon_quad (rs
) << 6;
16106 NEON_ENCODE (IMMED
, inst
);
16107 neon_move_immediate ();
16110 neon_dp_fixup (&inst
);
16113 /* Encode instructions of form:
16115 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16116 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16119 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16121 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16122 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16123 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16124 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16125 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16126 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16127 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16128 inst
.instruction
|= neon_logbits (size
) << 20;
16130 neon_dp_fixup (&inst
);
16134 do_neon_dyadic_long (void)
16136 /* FIXME: Type checking for lengthening op. */
16137 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16138 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16139 neon_mixed_length (et
, et
.size
);
16143 do_neon_abal (void)
16145 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16146 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16147 neon_mixed_length (et
, et
.size
);
16151 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16153 if (inst
.operands
[2].isscalar
)
16155 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16156 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16157 NEON_ENCODE (SCALAR
, inst
);
16158 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16162 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16163 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16164 NEON_ENCODE (INTEGER
, inst
);
16165 neon_mixed_length (et
, et
.size
);
16170 do_neon_mac_maybe_scalar_long (void)
16172 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16175 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16176 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16179 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16181 unsigned regno
= NEON_SCALAR_REG (scalar
);
16182 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16186 if (regno
> 7 || elno
> 3)
16189 return ((regno
& 0x7)
16190 | ((elno
& 0x1) << 3)
16191 | (((elno
>> 1) & 0x1) << 5));
16195 if (regno
> 15 || elno
> 1)
16198 return (((regno
& 0x1) << 5)
16199 | ((regno
>> 1) & 0x7)
16200 | ((elno
& 0x1) << 3));
16204 first_error (_("scalar out of range for multiply instruction"));
16209 do_neon_fmac_maybe_scalar_long (int subtype
)
16211 enum neon_shape rs
;
16213 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16214 field (bits[21:20]) has different meaning. For scalar index variant, it's
16215 used to differentiate add and subtract, otherwise it's with fixed value
16219 if (inst
.cond
!= COND_ALWAYS
)
16220 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16221 "behaviour is UNPREDICTABLE"));
16223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16226 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16229 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16230 be a scalar index register. */
16231 if (inst
.operands
[2].isscalar
)
16233 high8
= 0xfe000000;
16236 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16240 high8
= 0xfc000000;
16243 inst
.instruction
|= (0x1 << 23);
16244 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16247 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16249 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16250 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16251 so we simply pass -1 as size. */
16252 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16253 neon_three_same (quad_p
, 0, size
);
16255 /* Undo neon_dp_fixup. Redo the high eight bits. */
16256 inst
.instruction
&= 0x00ffffff;
16257 inst
.instruction
|= high8
;
16259 #define LOW1(R) ((R) & 0x1)
16260 #define HI4(R) (((R) >> 1) & 0xf)
16261 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16262 whether the instruction is in Q form and whether Vm is a scalar indexed
16264 if (inst
.operands
[2].isscalar
)
16267 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16268 inst
.instruction
&= 0xffffffd0;
16269 inst
.instruction
|= rm
;
16273 /* Redo Rn as well. */
16274 inst
.instruction
&= 0xfff0ff7f;
16275 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16276 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16281 /* Redo Rn and Rm. */
16282 inst
.instruction
&= 0xfff0ff50;
16283 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16284 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16285 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16286 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16291 do_neon_vfmal (void)
16293 return do_neon_fmac_maybe_scalar_long (0);
16297 do_neon_vfmsl (void)
16299 return do_neon_fmac_maybe_scalar_long (1);
16303 do_neon_dyadic_wide (void)
16305 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16306 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16307 neon_mixed_length (et
, et
.size
);
16311 do_neon_dyadic_narrow (void)
16313 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16314 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16315 /* Operand sign is unimportant, and the U bit is part of the opcode,
16316 so force the operand type to integer. */
16317 et
.type
= NT_integer
;
16318 neon_mixed_length (et
, et
.size
/ 2);
16322 do_neon_mul_sat_scalar_long (void)
16324 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16328 do_neon_vmull (void)
16330 if (inst
.operands
[2].isscalar
)
16331 do_neon_mac_maybe_scalar_long ();
16334 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16335 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16337 if (et
.type
== NT_poly
)
16338 NEON_ENCODE (POLY
, inst
);
16340 NEON_ENCODE (INTEGER
, inst
);
16342 /* For polynomial encoding the U bit must be zero, and the size must
16343 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16344 obviously, as 0b10). */
16347 /* Check we're on the correct architecture. */
16348 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16350 _("Instruction form not available on this architecture.");
16355 neon_mixed_length (et
, et
.size
);
16362 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16363 struct neon_type_el et
= neon_check_type (3, rs
,
16364 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16365 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16367 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16368 _("shift out of range"));
16369 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16370 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16371 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16372 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16373 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16374 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16375 inst
.instruction
|= neon_quad (rs
) << 6;
16376 inst
.instruction
|= imm
<< 8;
16378 neon_dp_fixup (&inst
);
16384 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16385 struct neon_type_el et
= neon_check_type (2, rs
,
16386 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16387 unsigned op
= (inst
.instruction
>> 7) & 3;
16388 /* N (width of reversed regions) is encoded as part of the bitmask. We
16389 extract it here to check the elements to be reversed are smaller.
16390 Otherwise we'd get a reserved instruction. */
16391 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16392 gas_assert (elsize
!= 0);
16393 constraint (et
.size
>= elsize
,
16394 _("elements must be smaller than reversal region"));
16395 neon_two_same (neon_quad (rs
), 1, et
.size
);
16401 if (inst
.operands
[1].isscalar
)
16403 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16404 struct neon_type_el et
= neon_check_type (2, rs
,
16405 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16406 unsigned sizebits
= et
.size
>> 3;
16407 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16408 int logsize
= neon_logbits (et
.size
);
16409 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16411 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16414 NEON_ENCODE (SCALAR
, inst
);
16415 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16416 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16417 inst
.instruction
|= LOW4 (dm
);
16418 inst
.instruction
|= HI1 (dm
) << 5;
16419 inst
.instruction
|= neon_quad (rs
) << 6;
16420 inst
.instruction
|= x
<< 17;
16421 inst
.instruction
|= sizebits
<< 16;
16423 neon_dp_fixup (&inst
);
16427 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16428 struct neon_type_el et
= neon_check_type (2, rs
,
16429 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16430 /* Duplicate ARM register to lanes of vector. */
16431 NEON_ENCODE (ARMREG
, inst
);
16434 case 8: inst
.instruction
|= 0x400000; break;
16435 case 16: inst
.instruction
|= 0x000020; break;
16436 case 32: inst
.instruction
|= 0x000000; break;
16439 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16440 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16442 inst
.instruction
|= neon_quad (rs
) << 21;
16443 /* The encoding for this instruction is identical for the ARM and Thumb
16444 variants, except for the condition field. */
16445 do_vfp_cond_or_thumb ();
16449 /* VMOV has particularly many variations. It can be one of:
16450 0. VMOV<c><q> <Qd>, <Qm>
16451 1. VMOV<c><q> <Dd>, <Dm>
16452 (Register operations, which are VORR with Rm = Rn.)
16453 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16454 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16456 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16457 (ARM register to scalar.)
16458 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16459 (Two ARM registers to vector.)
16460 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16461 (Scalar to ARM register.)
16462 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16463 (Vector to two ARM registers.)
16464 8. VMOV.F32 <Sd>, <Sm>
16465 9. VMOV.F64 <Dd>, <Dm>
16466 (VFP register moves.)
16467 10. VMOV.F32 <Sd>, #imm
16468 11. VMOV.F64 <Dd>, #imm
16469 (VFP float immediate load.)
16470 12. VMOV <Rd>, <Sm>
16471 (VFP single to ARM reg.)
16472 13. VMOV <Sd>, <Rm>
16473 (ARM reg to VFP single.)
16474 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16475 (Two ARM regs to two VFP singles.)
16476 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16477 (Two VFP singles to two ARM regs.)
16479 These cases can be disambiguated using neon_select_shape, except cases 1/9
16480 and 3/11 which depend on the operand type too.
16482 All the encoded bits are hardcoded by this function.
16484 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16485 Cases 5, 7 may be used with VFPv2 and above.
16487 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16488 can specify a type where it doesn't make sense to, and is ignored). */
16493 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16494 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16495 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16496 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16497 struct neon_type_el et
;
16498 const char *ldconst
= 0;
16502 case NS_DD
: /* case 1/9. */
16503 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16504 /* It is not an error here if no type is given. */
16506 if (et
.type
== NT_float
&& et
.size
== 64)
16508 do_vfp_nsyn_opcode ("fcpyd");
16511 /* fall through. */
16513 case NS_QQ
: /* case 0/1. */
16515 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16517 /* The architecture manual I have doesn't explicitly state which
16518 value the U bit should have for register->register moves, but
16519 the equivalent VORR instruction has U = 0, so do that. */
16520 inst
.instruction
= 0x0200110;
16521 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16522 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16523 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16524 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16525 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16526 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16527 inst
.instruction
|= neon_quad (rs
) << 6;
16529 neon_dp_fixup (&inst
);
16533 case NS_DI
: /* case 3/11. */
16534 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16536 if (et
.type
== NT_float
&& et
.size
== 64)
16538 /* case 11 (fconstd). */
16539 ldconst
= "fconstd";
16540 goto encode_fconstd
;
16542 /* fall through. */
16544 case NS_QI
: /* case 2/3. */
16545 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16547 inst
.instruction
= 0x0800010;
16548 neon_move_immediate ();
16549 neon_dp_fixup (&inst
);
16552 case NS_SR
: /* case 4. */
16554 unsigned bcdebits
= 0;
16556 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16557 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16559 /* .<size> is optional here, defaulting to .32. */
16560 if (inst
.vectype
.elems
== 0
16561 && inst
.operands
[0].vectype
.type
== NT_invtype
16562 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16564 inst
.vectype
.el
[0].type
= NT_untyped
;
16565 inst
.vectype
.el
[0].size
= 32;
16566 inst
.vectype
.elems
= 1;
16569 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16570 logsize
= neon_logbits (et
.size
);
16572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16575 && et
.size
!= 32, _(BAD_FPU
));
16576 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16577 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16581 case 8: bcdebits
= 0x8; break;
16582 case 16: bcdebits
= 0x1; break;
16583 case 32: bcdebits
= 0x0; break;
16587 bcdebits
|= x
<< logsize
;
16589 inst
.instruction
= 0xe000b10;
16590 do_vfp_cond_or_thumb ();
16591 inst
.instruction
|= LOW4 (dn
) << 16;
16592 inst
.instruction
|= HI1 (dn
) << 7;
16593 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16594 inst
.instruction
|= (bcdebits
& 3) << 5;
16595 inst
.instruction
|= (bcdebits
>> 2) << 21;
16599 case NS_DRR
: /* case 5 (fmdrr). */
16600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16603 inst
.instruction
= 0xc400b10;
16604 do_vfp_cond_or_thumb ();
16605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16607 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16608 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16611 case NS_RS
: /* case 6. */
16614 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16615 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16616 unsigned abcdebits
= 0;
16618 /* .<dt> is optional here, defaulting to .32. */
16619 if (inst
.vectype
.elems
== 0
16620 && inst
.operands
[0].vectype
.type
== NT_invtype
16621 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16623 inst
.vectype
.el
[0].type
= NT_untyped
;
16624 inst
.vectype
.el
[0].size
= 32;
16625 inst
.vectype
.elems
= 1;
16628 et
= neon_check_type (2, NS_NULL
,
16629 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16630 logsize
= neon_logbits (et
.size
);
16632 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16635 && et
.size
!= 32, _(BAD_FPU
));
16636 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16637 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16641 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16642 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16643 case 32: abcdebits
= 0x00; break;
16647 abcdebits
|= x
<< logsize
;
16648 inst
.instruction
= 0xe100b10;
16649 do_vfp_cond_or_thumb ();
16650 inst
.instruction
|= LOW4 (dn
) << 16;
16651 inst
.instruction
|= HI1 (dn
) << 7;
16652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16653 inst
.instruction
|= (abcdebits
& 3) << 5;
16654 inst
.instruction
|= (abcdebits
>> 2) << 21;
16658 case NS_RRD
: /* case 7 (fmrrd). */
16659 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16662 inst
.instruction
= 0xc500b10;
16663 do_vfp_cond_or_thumb ();
16664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16665 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16666 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16667 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16670 case NS_FF
: /* case 8 (fcpys). */
16671 do_vfp_nsyn_opcode ("fcpys");
16675 case NS_FI
: /* case 10 (fconsts). */
16676 ldconst
= "fconsts";
16678 if (is_quarter_float (inst
.operands
[1].imm
))
16680 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16681 do_vfp_nsyn_opcode (ldconst
);
16683 /* ARMv8.2 fp16 vmov.f16 instruction. */
16685 do_scalar_fp16_v82_encode ();
16688 first_error (_("immediate out of range"));
16692 case NS_RF
: /* case 12 (fmrs). */
16693 do_vfp_nsyn_opcode ("fmrs");
16694 /* ARMv8.2 fp16 vmov.f16 instruction. */
16696 do_scalar_fp16_v82_encode ();
16700 case NS_FR
: /* case 13 (fmsr). */
16701 do_vfp_nsyn_opcode ("fmsr");
16702 /* ARMv8.2 fp16 vmov.f16 instruction. */
16704 do_scalar_fp16_v82_encode ();
16707 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16708 (one of which is a list), but we have parsed four. Do some fiddling to
16709 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16711 case NS_RRFF
: /* case 14 (fmrrs). */
16712 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16713 _("VFP registers must be adjacent"));
16714 inst
.operands
[2].imm
= 2;
16715 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16716 do_vfp_nsyn_opcode ("fmrrs");
16719 case NS_FFRR
: /* case 15 (fmsrr). */
16720 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16721 _("VFP registers must be adjacent"));
16722 inst
.operands
[1] = inst
.operands
[2];
16723 inst
.operands
[2] = inst
.operands
[3];
16724 inst
.operands
[0].imm
= 2;
16725 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16726 do_vfp_nsyn_opcode ("fmsrr");
16730 /* neon_select_shape has determined that the instruction
16731 shape is wrong and has already set the error message. */
16740 do_neon_rshift_round_imm (void)
16742 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16743 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16744 int imm
= inst
.operands
[2].imm
;
16746 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16749 inst
.operands
[2].present
= 0;
16754 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16755 _("immediate out of range for shift"));
16756 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16761 do_neon_movhf (void)
16763 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16764 constraint (rs
!= NS_HH
, _("invalid suffix"));
16766 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16769 do_vfp_sp_monadic ();
16772 inst
.instruction
|= 0xf0000000;
16776 do_neon_movl (void)
16778 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16779 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16780 unsigned sizebits
= et
.size
>> 3;
16781 inst
.instruction
|= sizebits
<< 19;
16782 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16788 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16789 struct neon_type_el et
= neon_check_type (2, rs
,
16790 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16791 NEON_ENCODE (INTEGER
, inst
);
16792 neon_two_same (neon_quad (rs
), 1, et
.size
);
16796 do_neon_zip_uzp (void)
16798 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16799 struct neon_type_el et
= neon_check_type (2, rs
,
16800 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16801 if (rs
== NS_DD
&& et
.size
== 32)
16803 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16804 inst
.instruction
= N_MNEM_vtrn
;
16808 neon_two_same (neon_quad (rs
), 1, et
.size
);
16812 do_neon_sat_abs_neg (void)
16814 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16815 struct neon_type_el et
= neon_check_type (2, rs
,
16816 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16817 neon_two_same (neon_quad (rs
), 1, et
.size
);
16821 do_neon_pair_long (void)
16823 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16824 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16825 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16826 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16827 neon_two_same (neon_quad (rs
), 1, et
.size
);
16831 do_neon_recip_est (void)
16833 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16834 struct neon_type_el et
= neon_check_type (2, rs
,
16835 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16836 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16837 neon_two_same (neon_quad (rs
), 1, et
.size
);
16843 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16844 struct neon_type_el et
= neon_check_type (2, rs
,
16845 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16846 neon_two_same (neon_quad (rs
), 1, et
.size
);
16852 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16853 struct neon_type_el et
= neon_check_type (2, rs
,
16854 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16855 neon_two_same (neon_quad (rs
), 1, et
.size
);
16861 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16862 struct neon_type_el et
= neon_check_type (2, rs
,
16863 N_EQK
| N_INT
, N_8
| N_KEY
);
16864 neon_two_same (neon_quad (rs
), 1, et
.size
);
16870 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16871 neon_two_same (neon_quad (rs
), 1, -1);
16875 do_neon_tbl_tbx (void)
16877 unsigned listlenbits
;
16878 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16880 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16882 first_error (_("bad list length for table lookup"));
16886 listlenbits
= inst
.operands
[1].imm
- 1;
16887 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16888 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16889 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16890 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16891 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16892 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16893 inst
.instruction
|= listlenbits
<< 8;
16895 neon_dp_fixup (&inst
);
16899 do_neon_ldm_stm (void)
16901 /* P, U and L bits are part of bitmask. */
16902 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16903 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16905 if (inst
.operands
[1].issingle
)
16907 do_vfp_nsyn_ldm_stm (is_dbmode
);
16911 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16912 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16914 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16915 _("register list must contain at least 1 and at most 16 "
16918 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16919 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16920 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16921 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16923 inst
.instruction
|= offsetbits
;
16925 do_vfp_cond_or_thumb ();
16929 do_neon_ldr_str (void)
16931 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16933 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16934 And is UNPREDICTABLE in thumb mode. */
16936 && inst
.operands
[1].reg
== REG_PC
16937 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16940 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16941 else if (warn_on_deprecated
)
16942 as_tsktsk (_("Use of PC here is deprecated"));
16945 if (inst
.operands
[0].issingle
)
16948 do_vfp_nsyn_opcode ("flds");
16950 do_vfp_nsyn_opcode ("fsts");
16952 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16953 if (inst
.vectype
.el
[0].size
== 16)
16954 do_scalar_fp16_v82_encode ();
16959 do_vfp_nsyn_opcode ("fldd");
16961 do_vfp_nsyn_opcode ("fstd");
16965 /* "interleave" version also handles non-interleaving register VLD1/VST1
16969 do_neon_ld_st_interleave (void)
16971 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16972 N_8
| N_16
| N_32
| N_64
);
16973 unsigned alignbits
= 0;
16975 /* The bits in this table go:
16976 0: register stride of one (0) or two (1)
16977 1,2: register list length, minus one (1, 2, 3, 4).
16978 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16979 We use -1 for invalid entries. */
16980 const int typetable
[] =
16982 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16983 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16984 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16985 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16989 if (et
.type
== NT_invtype
)
16992 if (inst
.operands
[1].immisalign
)
16993 switch (inst
.operands
[1].imm
>> 8)
16995 case 64: alignbits
= 1; break;
16997 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16998 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16999 goto bad_alignment
;
17003 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17004 goto bad_alignment
;
17009 first_error (_("bad alignment"));
17013 inst
.instruction
|= alignbits
<< 4;
17014 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17016 /* Bits [4:6] of the immediate in a list specifier encode register stride
17017 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17018 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17019 up the right value for "type" in a table based on this value and the given
17020 list style, then stick it back. */
17021 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17022 | (((inst
.instruction
>> 8) & 3) << 3);
17024 typebits
= typetable
[idx
];
17026 constraint (typebits
== -1, _("bad list type for instruction"));
17027 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17028 _("bad element type for instruction"));
17030 inst
.instruction
&= ~0xf00;
17031 inst
.instruction
|= typebits
<< 8;
17034 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17035 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17036 otherwise. The variable arguments are a list of pairs of legal (size, align)
17037 values, terminated with -1. */
17040 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17043 int result
= FAIL
, thissize
, thisalign
;
17045 if (!inst
.operands
[1].immisalign
)
17051 va_start (ap
, do_alignment
);
17055 thissize
= va_arg (ap
, int);
17056 if (thissize
== -1)
17058 thisalign
= va_arg (ap
, int);
17060 if (size
== thissize
&& align
== thisalign
)
17063 while (result
!= SUCCESS
);
17067 if (result
== SUCCESS
)
17070 first_error (_("unsupported alignment for instruction"));
17076 do_neon_ld_st_lane (void)
17078 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17079 int align_good
, do_alignment
= 0;
17080 int logsize
= neon_logbits (et
.size
);
17081 int align
= inst
.operands
[1].imm
>> 8;
17082 int n
= (inst
.instruction
>> 8) & 3;
17083 int max_el
= 64 / et
.size
;
17085 if (et
.type
== NT_invtype
)
17088 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17089 _("bad list length"));
17090 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17091 _("scalar index out of range"));
17092 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17094 _("stride of 2 unavailable when element size is 8"));
17098 case 0: /* VLD1 / VST1. */
17099 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17101 if (align_good
== FAIL
)
17105 unsigned alignbits
= 0;
17108 case 16: alignbits
= 0x1; break;
17109 case 32: alignbits
= 0x3; break;
17112 inst
.instruction
|= alignbits
<< 4;
17116 case 1: /* VLD2 / VST2. */
17117 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17118 16, 32, 32, 64, -1);
17119 if (align_good
== FAIL
)
17122 inst
.instruction
|= 1 << 4;
17125 case 2: /* VLD3 / VST3. */
17126 constraint (inst
.operands
[1].immisalign
,
17127 _("can't use alignment with this instruction"));
17130 case 3: /* VLD4 / VST4. */
17131 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17132 16, 64, 32, 64, 32, 128, -1);
17133 if (align_good
== FAIL
)
17137 unsigned alignbits
= 0;
17140 case 8: alignbits
= 0x1; break;
17141 case 16: alignbits
= 0x1; break;
17142 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17145 inst
.instruction
|= alignbits
<< 4;
17152 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17153 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17154 inst
.instruction
|= 1 << (4 + logsize
);
17156 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17157 inst
.instruction
|= logsize
<< 10;
17160 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17163 do_neon_ld_dup (void)
17165 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17166 int align_good
, do_alignment
= 0;
17168 if (et
.type
== NT_invtype
)
17171 switch ((inst
.instruction
>> 8) & 3)
17173 case 0: /* VLD1. */
17174 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17175 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17176 &do_alignment
, 16, 16, 32, 32, -1);
17177 if (align_good
== FAIL
)
17179 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17182 case 2: inst
.instruction
|= 1 << 5; break;
17183 default: first_error (_("bad list length")); return;
17185 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17188 case 1: /* VLD2. */
17189 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17190 &do_alignment
, 8, 16, 16, 32, 32, 64,
17192 if (align_good
== FAIL
)
17194 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17195 _("bad list length"));
17196 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17197 inst
.instruction
|= 1 << 5;
17198 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17201 case 2: /* VLD3. */
17202 constraint (inst
.operands
[1].immisalign
,
17203 _("can't use alignment with this instruction"));
17204 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17205 _("bad list length"));
17206 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17207 inst
.instruction
|= 1 << 5;
17208 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17211 case 3: /* VLD4. */
17213 int align
= inst
.operands
[1].imm
>> 8;
17214 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17215 16, 64, 32, 64, 32, 128, -1);
17216 if (align_good
== FAIL
)
17218 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17219 _("bad list length"));
17220 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17221 inst
.instruction
|= 1 << 5;
17222 if (et
.size
== 32 && align
== 128)
17223 inst
.instruction
|= 0x3 << 6;
17225 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17232 inst
.instruction
|= do_alignment
<< 4;
17235 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17236 apart from bits [11:4]. */
17239 do_neon_ldx_stx (void)
17241 if (inst
.operands
[1].isreg
)
17242 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17244 switch (NEON_LANE (inst
.operands
[0].imm
))
17246 case NEON_INTERLEAVE_LANES
:
17247 NEON_ENCODE (INTERLV
, inst
);
17248 do_neon_ld_st_interleave ();
17251 case NEON_ALL_LANES
:
17252 NEON_ENCODE (DUP
, inst
);
17253 if (inst
.instruction
== N_INV
)
17255 first_error ("only loads support such operands");
17262 NEON_ENCODE (LANE
, inst
);
17263 do_neon_ld_st_lane ();
17266 /* L bit comes from bit mask. */
17267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17271 if (inst
.operands
[1].postind
)
17273 int postreg
= inst
.operands
[1].imm
& 0xf;
17274 constraint (!inst
.operands
[1].immisreg
,
17275 _("post-index must be a register"));
17276 constraint (postreg
== 0xd || postreg
== 0xf,
17277 _("bad register for post-index"));
17278 inst
.instruction
|= postreg
;
17282 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17283 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17284 || inst
.reloc
.exp
.X_add_number
!= 0,
17287 if (inst
.operands
[1].writeback
)
17289 inst
.instruction
|= 0xd;
17292 inst
.instruction
|= 0xf;
17296 inst
.instruction
|= 0xf9000000;
17298 inst
.instruction
|= 0xf4000000;
17303 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17305 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17306 D register operands. */
17307 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17308 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17311 NEON_ENCODE (FPV8
, inst
);
17313 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17315 do_vfp_sp_dyadic ();
17317 /* ARMv8.2 fp16 instruction. */
17319 do_scalar_fp16_v82_encode ();
17322 do_vfp_dp_rd_rn_rm ();
17325 inst
.instruction
|= 0x100;
17327 inst
.instruction
|= 0xf0000000;
17333 set_it_insn_type (OUTSIDE_IT_INSN
);
17335 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17336 first_error (_("invalid instruction shape"));
17342 set_it_insn_type (OUTSIDE_IT_INSN
);
17344 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17347 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17350 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17354 do_vrint_1 (enum neon_cvt_mode mode
)
17356 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17357 struct neon_type_el et
;
17362 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17363 D register operands. */
17364 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17368 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17370 if (et
.type
!= NT_invtype
)
17372 /* VFP encodings. */
17373 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17374 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17375 set_it_insn_type (OUTSIDE_IT_INSN
);
17377 NEON_ENCODE (FPV8
, inst
);
17378 if (rs
== NS_FF
|| rs
== NS_HH
)
17379 do_vfp_sp_monadic ();
17381 do_vfp_dp_rd_rm ();
17385 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17386 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17387 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17388 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17389 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17390 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17391 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17395 inst
.instruction
|= (rs
== NS_DD
) << 8;
17396 do_vfp_cond_or_thumb ();
17398 /* ARMv8.2 fp16 vrint instruction. */
17400 do_scalar_fp16_v82_encode ();
17404 /* Neon encodings (or something broken...). */
17406 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17408 if (et
.type
== NT_invtype
)
17411 set_it_insn_type (OUTSIDE_IT_INSN
);
17412 NEON_ENCODE (FLOAT
, inst
);
17414 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17417 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17418 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17419 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17420 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17421 inst
.instruction
|= neon_quad (rs
) << 6;
17422 /* Mask off the original size bits and reencode them. */
17423 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17424 | neon_logbits (et
.size
) << 18);
17428 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17429 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17430 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17431 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17432 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17433 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17434 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17439 inst
.instruction
|= 0xfc000000;
17441 inst
.instruction
|= 0xf0000000;
17448 do_vrint_1 (neon_cvt_mode_x
);
17454 do_vrint_1 (neon_cvt_mode_z
);
17460 do_vrint_1 (neon_cvt_mode_r
);
17466 do_vrint_1 (neon_cvt_mode_a
);
17472 do_vrint_1 (neon_cvt_mode_n
);
17478 do_vrint_1 (neon_cvt_mode_p
);
17484 do_vrint_1 (neon_cvt_mode_m
);
17488 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17490 unsigned regno
= NEON_SCALAR_REG (opnd
);
17491 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17493 if (elsize
== 16 && elno
< 2 && regno
< 16)
17494 return regno
| (elno
<< 4);
17495 else if (elsize
== 32 && elno
== 0)
17498 first_error (_("scalar out of range"));
17505 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17507 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17508 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17509 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17510 _("immediate out of range"));
17512 if (inst
.operands
[2].isscalar
)
17514 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17515 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17516 N_KEY
| N_F16
| N_F32
).size
;
17517 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17519 inst
.instruction
= 0xfe000800;
17520 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17521 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17522 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17523 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17524 inst
.instruction
|= LOW4 (m
);
17525 inst
.instruction
|= HI1 (m
) << 5;
17526 inst
.instruction
|= neon_quad (rs
) << 6;
17527 inst
.instruction
|= rot
<< 20;
17528 inst
.instruction
|= (size
== 32) << 23;
17532 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17533 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17534 N_KEY
| N_F16
| N_F32
).size
;
17535 neon_three_same (neon_quad (rs
), 0, -1);
17536 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17537 inst
.instruction
|= 0xfc200800;
17538 inst
.instruction
|= rot
<< 23;
17539 inst
.instruction
|= (size
== 32) << 20;
17546 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17548 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17549 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17550 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17551 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17552 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17553 N_KEY
| N_F16
| N_F32
).size
;
17554 neon_three_same (neon_quad (rs
), 0, -1);
17555 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17556 inst
.instruction
|= 0xfc800800;
17557 inst
.instruction
|= (rot
== 270) << 24;
17558 inst
.instruction
|= (size
== 32) << 20;
17561 /* Dot Product instructions encoding support. */
17564 do_neon_dotproduct (int unsigned_p
)
17566 enum neon_shape rs
;
17567 unsigned scalar_oprd2
= 0;
17570 if (inst
.cond
!= COND_ALWAYS
)
17571 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17572 "is UNPREDICTABLE"));
17574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17577 /* Dot Product instructions are in three-same D/Q register format or the third
17578 operand can be a scalar index register. */
17579 if (inst
.operands
[2].isscalar
)
17581 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17582 high8
= 0xfe000000;
17583 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17587 high8
= 0xfc000000;
17588 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17592 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17594 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17596 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17597 Product instruction, so we pass 0 as the "ubit" parameter. And the
17598 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17599 neon_three_same (neon_quad (rs
), 0, 32);
17601 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17602 different NEON three-same encoding. */
17603 inst
.instruction
&= 0x00ffffff;
17604 inst
.instruction
|= high8
;
17605 /* Encode 'U' bit which indicates signedness. */
17606 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17607 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17608 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17609 the instruction encoding. */
17610 if (inst
.operands
[2].isscalar
)
17612 inst
.instruction
&= 0xffffffd0;
17613 inst
.instruction
|= LOW4 (scalar_oprd2
);
17614 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17618 /* Dot Product instructions for signed integer. */
17621 do_neon_dotproduct_s (void)
17623 return do_neon_dotproduct (0);
17626 /* Dot Product instructions for unsigned integer. */
17629 do_neon_dotproduct_u (void)
17631 return do_neon_dotproduct (1);
17634 /* Crypto v1 instructions. */
17636 do_crypto_2op_1 (unsigned elttype
, int op
)
17638 set_it_insn_type (OUTSIDE_IT_INSN
);
17640 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17646 NEON_ENCODE (INTEGER
, inst
);
17647 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17648 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17649 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17650 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17652 inst
.instruction
|= op
<< 6;
17655 inst
.instruction
|= 0xfc000000;
17657 inst
.instruction
|= 0xf0000000;
17661 do_crypto_3op_1 (int u
, int op
)
17663 set_it_insn_type (OUTSIDE_IT_INSN
);
17665 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17666 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17671 NEON_ENCODE (INTEGER
, inst
);
17672 neon_three_same (1, u
, 8 << op
);
17678 do_crypto_2op_1 (N_8
, 0);
17684 do_crypto_2op_1 (N_8
, 1);
17690 do_crypto_2op_1 (N_8
, 2);
17696 do_crypto_2op_1 (N_8
, 3);
17702 do_crypto_3op_1 (0, 0);
17708 do_crypto_3op_1 (0, 1);
17714 do_crypto_3op_1 (0, 2);
17720 do_crypto_3op_1 (0, 3);
17726 do_crypto_3op_1 (1, 0);
17732 do_crypto_3op_1 (1, 1);
17736 do_sha256su1 (void)
17738 do_crypto_3op_1 (1, 2);
17744 do_crypto_2op_1 (N_32
, -1);
17750 do_crypto_2op_1 (N_32
, 0);
17754 do_sha256su0 (void)
17756 do_crypto_2op_1 (N_32
, 1);
17760 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17762 unsigned int Rd
= inst
.operands
[0].reg
;
17763 unsigned int Rn
= inst
.operands
[1].reg
;
17764 unsigned int Rm
= inst
.operands
[2].reg
;
17766 set_it_insn_type (OUTSIDE_IT_INSN
);
17767 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17768 inst
.instruction
|= LOW4 (Rn
) << 16;
17769 inst
.instruction
|= LOW4 (Rm
);
17770 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17771 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17773 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17774 as_warn (UNPRED_REG ("r15"));
17816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17818 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17819 do_vfp_sp_dp_cvt ();
17820 do_vfp_cond_or_thumb ();
17824 /* Overall per-instruction processing. */
17826 /* We need to be able to fix up arbitrary expressions in some statements.
17827 This is so that we can handle symbols that are an arbitrary distance from
17828 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17829 which returns part of an address in a form which will be valid for
17830 a data instruction. We do this by pushing the expression into a symbol
17831 in the expr_section, and creating a fix for that. */
17834 fix_new_arm (fragS
* frag
,
17848 /* Create an absolute valued symbol, so we have something to
17849 refer to in the object file. Unfortunately for us, gas's
17850 generic expression parsing will already have folded out
17851 any use of .set foo/.type foo %function that may have
17852 been used to set type information of the target location,
17853 that's being specified symbolically. We have to presume
17854 the user knows what they are doing. */
17858 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17860 symbol
= symbol_find_or_make (name
);
17861 S_SET_SEGMENT (symbol
, absolute_section
);
17862 symbol_set_frag (symbol
, &zero_address_frag
);
17863 S_SET_VALUE (symbol
, exp
->X_add_number
);
17864 exp
->X_op
= O_symbol
;
17865 exp
->X_add_symbol
= symbol
;
17866 exp
->X_add_number
= 0;
17872 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17873 (enum bfd_reloc_code_real
) reloc
);
17877 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17878 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17882 /* Mark whether the fix is to a THUMB instruction, or an ARM
17884 new_fix
->tc_fix_data
= thumb_mode
;
17887 /* Create a frg for an instruction requiring relaxation. */
17889 output_relax_insn (void)
17895 /* The size of the instruction is unknown, so tie the debug info to the
17896 start of the instruction. */
17897 dwarf2_emit_insn (0);
17899 switch (inst
.reloc
.exp
.X_op
)
17902 sym
= inst
.reloc
.exp
.X_add_symbol
;
17903 offset
= inst
.reloc
.exp
.X_add_number
;
17907 offset
= inst
.reloc
.exp
.X_add_number
;
17910 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17914 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17915 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17916 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17919 /* Write a 32-bit thumb instruction to buf. */
17921 put_thumb32_insn (char * buf
, unsigned long insn
)
17923 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17924 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17928 output_inst (const char * str
)
17934 as_bad ("%s -- `%s'", inst
.error
, str
);
17939 output_relax_insn ();
17942 if (inst
.size
== 0)
17945 to
= frag_more (inst
.size
);
17946 /* PR 9814: Record the thumb mode into the current frag so that we know
17947 what type of NOP padding to use, if necessary. We override any previous
17948 setting so that if the mode has changed then the NOPS that we use will
17949 match the encoding of the last instruction in the frag. */
17950 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17952 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17954 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17955 put_thumb32_insn (to
, inst
.instruction
);
17957 else if (inst
.size
> INSN_SIZE
)
17959 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17960 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17961 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17964 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17966 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17967 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17968 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17971 dwarf2_emit_insn (inst
.size
);
17975 output_it_inst (int cond
, int mask
, char * to
)
17977 unsigned long instruction
= 0xbf00;
17980 instruction
|= mask
;
17981 instruction
|= cond
<< 4;
17985 to
= frag_more (2);
17987 dwarf2_emit_insn (2);
17991 md_number_to_chars (to
, instruction
, 2);
17996 /* Tag values used in struct asm_opcode's tag field. */
17999 OT_unconditional
, /* Instruction cannot be conditionalized.
18000 The ARM condition field is still 0xE. */
18001 OT_unconditionalF
, /* Instruction cannot be conditionalized
18002 and carries 0xF in its ARM condition field. */
18003 OT_csuffix
, /* Instruction takes a conditional suffix. */
18004 OT_csuffixF
, /* Some forms of the instruction take a conditional
18005 suffix, others place 0xF where the condition field
18007 OT_cinfix3
, /* Instruction takes a conditional infix,
18008 beginning at character index 3. (In
18009 unified mode, it becomes a suffix.) */
18010 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18011 tsts, cmps, cmns, and teqs. */
18012 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18013 character index 3, even in unified mode. Used for
18014 legacy instructions where suffix and infix forms
18015 may be ambiguous. */
18016 OT_csuf_or_in3
, /* Instruction takes either a conditional
18017 suffix or an infix at character index 3. */
18018 OT_odd_infix_unc
, /* This is the unconditional variant of an
18019 instruction that takes a conditional infix
18020 at an unusual position. In unified mode,
18021 this variant will accept a suffix. */
18022 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18023 are the conditional variants of instructions that
18024 take conditional infixes in unusual positions.
18025 The infix appears at character index
18026 (tag - OT_odd_infix_0). These are not accepted
18027 in unified mode. */
18030 /* Subroutine of md_assemble, responsible for looking up the primary
18031 opcode from the mnemonic the user wrote. STR points to the
18032 beginning of the mnemonic.
18034 This is not simply a hash table lookup, because of conditional
18035 variants. Most instructions have conditional variants, which are
18036 expressed with a _conditional affix_ to the mnemonic. If we were
18037 to encode each conditional variant as a literal string in the opcode
18038 table, it would have approximately 20,000 entries.
18040 Most mnemonics take this affix as a suffix, and in unified syntax,
18041 'most' is upgraded to 'all'. However, in the divided syntax, some
18042 instructions take the affix as an infix, notably the s-variants of
18043 the arithmetic instructions. Of those instructions, all but six
18044 have the infix appear after the third character of the mnemonic.
18046 Accordingly, the algorithm for looking up primary opcodes given
18049 1. Look up the identifier in the opcode table.
18050 If we find a match, go to step U.
18052 2. Look up the last two characters of the identifier in the
18053 conditions table. If we find a match, look up the first N-2
18054 characters of the identifier in the opcode table. If we
18055 find a match, go to step CE.
18057 3. Look up the fourth and fifth characters of the identifier in
18058 the conditions table. If we find a match, extract those
18059 characters from the identifier, and look up the remaining
18060 characters in the opcode table. If we find a match, go
18065 U. Examine the tag field of the opcode structure, in case this is
18066 one of the six instructions with its conditional infix in an
18067 unusual place. If it is, the tag tells us where to find the
18068 infix; look it up in the conditions table and set inst.cond
18069 accordingly. Otherwise, this is an unconditional instruction.
18070 Again set inst.cond accordingly. Return the opcode structure.
18072 CE. Examine the tag field to make sure this is an instruction that
18073 should receive a conditional suffix. If it is not, fail.
18074 Otherwise, set inst.cond from the suffix we already looked up,
18075 and return the opcode structure.
18077 CM. Examine the tag field to make sure this is an instruction that
18078 should receive a conditional infix after the third character.
18079 If it is not, fail. Otherwise, undo the edits to the current
18080 line of input and proceed as for case CE. */
18082 static const struct asm_opcode
*
18083 opcode_lookup (char **str
)
18087 const struct asm_opcode
*opcode
;
18088 const struct asm_cond
*cond
;
18091 /* Scan up to the end of the mnemonic, which must end in white space,
18092 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18093 for (base
= end
= *str
; *end
!= '\0'; end
++)
18094 if (*end
== ' ' || *end
== '.')
18100 /* Handle a possible width suffix and/or Neon type suffix. */
18105 /* The .w and .n suffixes are only valid if the unified syntax is in
18107 if (unified_syntax
&& end
[1] == 'w')
18109 else if (unified_syntax
&& end
[1] == 'n')
18114 inst
.vectype
.elems
= 0;
18116 *str
= end
+ offset
;
18118 if (end
[offset
] == '.')
18120 /* See if we have a Neon type suffix (possible in either unified or
18121 non-unified ARM syntax mode). */
18122 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18125 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18131 /* Look for unaffixed or special-case affixed mnemonic. */
18132 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18137 if (opcode
->tag
< OT_odd_infix_0
)
18139 inst
.cond
= COND_ALWAYS
;
18143 if (warn_on_deprecated
&& unified_syntax
)
18144 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18145 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18146 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18149 inst
.cond
= cond
->value
;
18153 /* Cannot have a conditional suffix on a mnemonic of less than two
18155 if (end
- base
< 3)
18158 /* Look for suffixed mnemonic. */
18160 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18161 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18163 if (opcode
&& cond
)
18166 switch (opcode
->tag
)
18168 case OT_cinfix3_legacy
:
18169 /* Ignore conditional suffixes matched on infix only mnemonics. */
18173 case OT_cinfix3_deprecated
:
18174 case OT_odd_infix_unc
:
18175 if (!unified_syntax
)
18177 /* Fall through. */
18181 case OT_csuf_or_in3
:
18182 inst
.cond
= cond
->value
;
18185 case OT_unconditional
:
18186 case OT_unconditionalF
:
18188 inst
.cond
= cond
->value
;
18191 /* Delayed diagnostic. */
18192 inst
.error
= BAD_COND
;
18193 inst
.cond
= COND_ALWAYS
;
18202 /* Cannot have a usual-position infix on a mnemonic of less than
18203 six characters (five would be a suffix). */
18204 if (end
- base
< 6)
18207 /* Look for infixed mnemonic in the usual position. */
18209 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18213 memcpy (save
, affix
, 2);
18214 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18215 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18217 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18218 memcpy (affix
, save
, 2);
18221 && (opcode
->tag
== OT_cinfix3
18222 || opcode
->tag
== OT_cinfix3_deprecated
18223 || opcode
->tag
== OT_csuf_or_in3
18224 || opcode
->tag
== OT_cinfix3_legacy
))
18227 if (warn_on_deprecated
&& unified_syntax
18228 && (opcode
->tag
== OT_cinfix3
18229 || opcode
->tag
== OT_cinfix3_deprecated
))
18230 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18232 inst
.cond
= cond
->value
;
18239 /* This function generates an initial IT instruction, leaving its block
18240 virtually open for the new instructions. Eventually,
18241 the mask will be updated by now_it_add_mask () each time
18242 a new instruction needs to be included in the IT block.
18243 Finally, the block is closed with close_automatic_it_block ().
18244 The block closure can be requested either from md_assemble (),
18245 a tencode (), or due to a label hook. */
18248 new_automatic_it_block (int cond
)
18250 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18251 now_it
.mask
= 0x18;
18253 now_it
.block_length
= 1;
18254 mapping_state (MAP_THUMB
);
18255 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18256 now_it
.warn_deprecated
= FALSE
;
18257 now_it
.insn_cond
= TRUE
;
18260 /* Close an automatic IT block.
18261 See comments in new_automatic_it_block (). */
18264 close_automatic_it_block (void)
18266 now_it
.mask
= 0x10;
18267 now_it
.block_length
= 0;
18270 /* Update the mask of the current automatically-generated IT
18271 instruction. See comments in new_automatic_it_block (). */
18274 now_it_add_mask (int cond
)
18276 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18277 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18278 | ((bitvalue) << (nbit)))
18279 const int resulting_bit
= (cond
& 1);
18281 now_it
.mask
&= 0xf;
18282 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18284 (5 - now_it
.block_length
));
18285 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18287 ((5 - now_it
.block_length
) - 1) );
18288 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18291 #undef SET_BIT_VALUE
18294 /* The IT blocks handling machinery is accessed through the these functions:
18295 it_fsm_pre_encode () from md_assemble ()
18296 set_it_insn_type () optional, from the tencode functions
18297 set_it_insn_type_last () ditto
18298 in_it_block () ditto
18299 it_fsm_post_encode () from md_assemble ()
18300 force_automatic_it_block_close () from label handling functions
18303 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18304 initializing the IT insn type with a generic initial value depending
18305 on the inst.condition.
18306 2) During the tencode function, two things may happen:
18307 a) The tencode function overrides the IT insn type by
18308 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18309 b) The tencode function queries the IT block state by
18310 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18312 Both set_it_insn_type and in_it_block run the internal FSM state
18313 handling function (handle_it_state), because: a) setting the IT insn
18314 type may incur in an invalid state (exiting the function),
18315 and b) querying the state requires the FSM to be updated.
18316 Specifically we want to avoid creating an IT block for conditional
18317 branches, so it_fsm_pre_encode is actually a guess and we can't
18318 determine whether an IT block is required until the tencode () routine
18319 has decided what type of instruction this actually it.
18320 Because of this, if set_it_insn_type and in_it_block have to be used,
18321 set_it_insn_type has to be called first.
18323 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18324 determines the insn IT type depending on the inst.cond code.
18325 When a tencode () routine encodes an instruction that can be
18326 either outside an IT block, or, in the case of being inside, has to be
18327 the last one, set_it_insn_type_last () will determine the proper
18328 IT instruction type based on the inst.cond code. Otherwise,
18329 set_it_insn_type can be called for overriding that logic or
18330 for covering other cases.
18332 Calling handle_it_state () may not transition the IT block state to
18333 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18334 still queried. Instead, if the FSM determines that the state should
18335 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18336 after the tencode () function: that's what it_fsm_post_encode () does.
18338 Since in_it_block () calls the state handling function to get an
18339 updated state, an error may occur (due to invalid insns combination).
18340 In that case, inst.error is set.
18341 Therefore, inst.error has to be checked after the execution of
18342 the tencode () routine.
18344 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18345 any pending state change (if any) that didn't take place in
18346 handle_it_state () as explained above. */
18349 it_fsm_pre_encode (void)
18351 if (inst
.cond
!= COND_ALWAYS
)
18352 inst
.it_insn_type
= INSIDE_IT_INSN
;
18354 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18356 now_it
.state_handled
= 0;
18359 /* IT state FSM handling function. */
18362 handle_it_state (void)
18364 now_it
.state_handled
= 1;
18365 now_it
.insn_cond
= FALSE
;
18367 switch (now_it
.state
)
18369 case OUTSIDE_IT_BLOCK
:
18370 switch (inst
.it_insn_type
)
18372 case OUTSIDE_IT_INSN
:
18375 case INSIDE_IT_INSN
:
18376 case INSIDE_IT_LAST_INSN
:
18377 if (thumb_mode
== 0)
18380 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18381 as_tsktsk (_("Warning: conditional outside an IT block"\
18386 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18387 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18389 /* Automatically generate the IT instruction. */
18390 new_automatic_it_block (inst
.cond
);
18391 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18392 close_automatic_it_block ();
18396 inst
.error
= BAD_OUT_IT
;
18402 case IF_INSIDE_IT_LAST_INSN
:
18403 case NEUTRAL_IT_INSN
:
18407 now_it
.state
= MANUAL_IT_BLOCK
;
18408 now_it
.block_length
= 0;
18413 case AUTOMATIC_IT_BLOCK
:
18414 /* Three things may happen now:
18415 a) We should increment current it block size;
18416 b) We should close current it block (closing insn or 4 insns);
18417 c) We should close current it block and start a new one (due
18418 to incompatible conditions or
18419 4 insns-length block reached). */
18421 switch (inst
.it_insn_type
)
18423 case OUTSIDE_IT_INSN
:
18424 /* The closure of the block shall happen immediately,
18425 so any in_it_block () call reports the block as closed. */
18426 force_automatic_it_block_close ();
18429 case INSIDE_IT_INSN
:
18430 case INSIDE_IT_LAST_INSN
:
18431 case IF_INSIDE_IT_LAST_INSN
:
18432 now_it
.block_length
++;
18434 if (now_it
.block_length
> 4
18435 || !now_it_compatible (inst
.cond
))
18437 force_automatic_it_block_close ();
18438 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18439 new_automatic_it_block (inst
.cond
);
18443 now_it
.insn_cond
= TRUE
;
18444 now_it_add_mask (inst
.cond
);
18447 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18448 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18449 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18450 close_automatic_it_block ();
18453 case NEUTRAL_IT_INSN
:
18454 now_it
.block_length
++;
18455 now_it
.insn_cond
= TRUE
;
18457 if (now_it
.block_length
> 4)
18458 force_automatic_it_block_close ();
18460 now_it_add_mask (now_it
.cc
& 1);
18464 close_automatic_it_block ();
18465 now_it
.state
= MANUAL_IT_BLOCK
;
18470 case MANUAL_IT_BLOCK
:
18472 /* Check conditional suffixes. */
18473 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18476 now_it
.mask
&= 0x1f;
18477 is_last
= (now_it
.mask
== 0x10);
18478 now_it
.insn_cond
= TRUE
;
18480 switch (inst
.it_insn_type
)
18482 case OUTSIDE_IT_INSN
:
18483 inst
.error
= BAD_NOT_IT
;
18486 case INSIDE_IT_INSN
:
18487 if (cond
!= inst
.cond
)
18489 inst
.error
= BAD_IT_COND
;
18494 case INSIDE_IT_LAST_INSN
:
18495 case IF_INSIDE_IT_LAST_INSN
:
18496 if (cond
!= inst
.cond
)
18498 inst
.error
= BAD_IT_COND
;
18503 inst
.error
= BAD_BRANCH
;
18508 case NEUTRAL_IT_INSN
:
18509 /* The BKPT instruction is unconditional even in an IT block. */
18513 inst
.error
= BAD_IT_IT
;
18523 struct depr_insn_mask
18525 unsigned long pattern
;
18526 unsigned long mask
;
18527 const char* description
;
18530 /* List of 16-bit instruction patterns deprecated in an IT block in
18532 static const struct depr_insn_mask depr_it_insns
[] = {
18533 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18534 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18535 { 0xa000, 0xb800, N_("ADR") },
18536 { 0x4800, 0xf800, N_("Literal loads") },
18537 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18538 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18539 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18540 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18541 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18546 it_fsm_post_encode (void)
18550 if (!now_it
.state_handled
)
18551 handle_it_state ();
18553 if (now_it
.insn_cond
18554 && !now_it
.warn_deprecated
18555 && warn_on_deprecated
18556 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18558 if (inst
.instruction
>= 0x10000)
18560 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18561 "deprecated in ARMv8"));
18562 now_it
.warn_deprecated
= TRUE
;
18566 const struct depr_insn_mask
*p
= depr_it_insns
;
18568 while (p
->mask
!= 0)
18570 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18572 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18573 "of the following class are deprecated in ARMv8: "
18574 "%s"), p
->description
);
18575 now_it
.warn_deprecated
= TRUE
;
18583 if (now_it
.block_length
> 1)
18585 as_tsktsk (_("IT blocks containing more than one conditional "
18586 "instruction are deprecated in ARMv8"));
18587 now_it
.warn_deprecated
= TRUE
;
18591 is_last
= (now_it
.mask
== 0x10);
18594 now_it
.state
= OUTSIDE_IT_BLOCK
;
18600 force_automatic_it_block_close (void)
18602 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18604 close_automatic_it_block ();
18605 now_it
.state
= OUTSIDE_IT_BLOCK
;
18613 if (!now_it
.state_handled
)
18614 handle_it_state ();
18616 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18619 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18620 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18621 here, hence the "known" in the function name. */
18624 known_t32_only_insn (const struct asm_opcode
*opcode
)
18626 /* Original Thumb-1 wide instruction. */
18627 if (opcode
->tencode
== do_t_blx
18628 || opcode
->tencode
== do_t_branch23
18629 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18630 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18633 /* Wide-only instruction added to ARMv8-M Baseline. */
18634 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18635 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18636 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18637 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18643 /* Whether wide instruction variant can be used if available for a valid OPCODE
18647 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18649 if (known_t32_only_insn (opcode
))
18652 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18653 of variant T3 of B.W is checked in do_t_branch. */
18654 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18655 && opcode
->tencode
== do_t_branch
)
18658 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18659 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18660 && opcode
->tencode
== do_t_mov_cmp
18661 /* Make sure CMP instruction is not affected. */
18662 && opcode
->aencode
== do_mov
)
18665 /* Wide instruction variants of all instructions with narrow *and* wide
18666 variants become available with ARMv6t2. Other opcodes are either
18667 narrow-only or wide-only and are thus available if OPCODE is valid. */
18668 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18671 /* OPCODE with narrow only instruction variant or wide variant not
18677 md_assemble (char *str
)
18680 const struct asm_opcode
* opcode
;
18682 /* Align the previous label if needed. */
18683 if (last_label_seen
!= NULL
)
18685 symbol_set_frag (last_label_seen
, frag_now
);
18686 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18687 S_SET_SEGMENT (last_label_seen
, now_seg
);
18690 memset (&inst
, '\0', sizeof (inst
));
18691 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18693 opcode
= opcode_lookup (&p
);
18696 /* It wasn't an instruction, but it might be a register alias of
18697 the form alias .req reg, or a Neon .dn/.qn directive. */
18698 if (! create_register_alias (str
, p
)
18699 && ! create_neon_reg_alias (str
, p
))
18700 as_bad (_("bad instruction `%s'"), str
);
18705 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18706 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18708 /* The value which unconditional instructions should have in place of the
18709 condition field. */
18710 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18714 arm_feature_set variant
;
18716 variant
= cpu_variant
;
18717 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18718 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18719 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18720 /* Check that this instruction is supported for this CPU. */
18721 if (!opcode
->tvariant
18722 || (thumb_mode
== 1
18723 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18725 if (opcode
->tencode
== do_t_swi
)
18726 as_bad (_("SVC is not permitted on this architecture"));
18728 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18731 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18732 && opcode
->tencode
!= do_t_branch
)
18734 as_bad (_("Thumb does not support conditional execution"));
18738 /* Two things are addressed here:
18739 1) Implicit require narrow instructions on Thumb-1.
18740 This avoids relaxation accidentally introducing Thumb-2
18742 2) Reject wide instructions in non Thumb-2 cores.
18744 Only instructions with narrow and wide variants need to be handled
18745 but selecting all non wide-only instructions is easier. */
18746 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18747 && !t32_insn_ok (variant
, opcode
))
18749 if (inst
.size_req
== 0)
18751 else if (inst
.size_req
== 4)
18753 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18754 as_bad (_("selected processor does not support 32bit wide "
18755 "variant of instruction `%s'"), str
);
18757 as_bad (_("selected processor does not support `%s' in "
18758 "Thumb-2 mode"), str
);
18763 inst
.instruction
= opcode
->tvalue
;
18765 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18767 /* Prepare the it_insn_type for those encodings that don't set
18769 it_fsm_pre_encode ();
18771 opcode
->tencode ();
18773 it_fsm_post_encode ();
18776 if (!(inst
.error
|| inst
.relax
))
18778 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18779 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18780 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18782 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18787 /* Something has gone badly wrong if we try to relax a fixed size
18789 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18791 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18792 *opcode
->tvariant
);
18793 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18794 set those bits when Thumb-2 32-bit instructions are seen. The impact
18795 of relaxable instructions will be considered later after we finish all
18797 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18798 variant
= arm_arch_none
;
18800 variant
= cpu_variant
;
18801 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18802 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18805 check_neon_suffixes
;
18809 mapping_state (MAP_THUMB
);
18812 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18816 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18817 is_bx
= (opcode
->aencode
== do_bx
);
18819 /* Check that this instruction is supported for this CPU. */
18820 if (!(is_bx
&& fix_v4bx
)
18821 && !(opcode
->avariant
&&
18822 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18824 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18829 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18833 inst
.instruction
= opcode
->avalue
;
18834 if (opcode
->tag
== OT_unconditionalF
)
18835 inst
.instruction
|= 0xFU
<< 28;
18837 inst
.instruction
|= inst
.cond
<< 28;
18838 inst
.size
= INSN_SIZE
;
18839 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18841 it_fsm_pre_encode ();
18842 opcode
->aencode ();
18843 it_fsm_post_encode ();
18845 /* Arm mode bx is marked as both v4T and v5 because it's still required
18846 on a hypothetical non-thumb v5 core. */
18848 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18850 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18851 *opcode
->avariant
);
18853 check_neon_suffixes
;
18857 mapping_state (MAP_ARM
);
18862 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18870 check_it_blocks_finished (void)
18875 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18876 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18877 == MANUAL_IT_BLOCK
)
18879 as_warn (_("section '%s' finished with an open IT block."),
18883 if (now_it
.state
== MANUAL_IT_BLOCK
)
18884 as_warn (_("file finished with an open IT block."));
18888 /* Various frobbings of labels and their addresses. */
18891 arm_start_line_hook (void)
18893 last_label_seen
= NULL
;
18897 arm_frob_label (symbolS
* sym
)
18899 last_label_seen
= sym
;
18901 ARM_SET_THUMB (sym
, thumb_mode
);
18903 #if defined OBJ_COFF || defined OBJ_ELF
18904 ARM_SET_INTERWORK (sym
, support_interwork
);
18907 force_automatic_it_block_close ();
18909 /* Note - do not allow local symbols (.Lxxx) to be labelled
18910 as Thumb functions. This is because these labels, whilst
18911 they exist inside Thumb code, are not the entry points for
18912 possible ARM->Thumb calls. Also, these labels can be used
18913 as part of a computed goto or switch statement. eg gcc
18914 can generate code that looks like this:
18916 ldr r2, [pc, .Laaa]
18926 The first instruction loads the address of the jump table.
18927 The second instruction converts a table index into a byte offset.
18928 The third instruction gets the jump address out of the table.
18929 The fourth instruction performs the jump.
18931 If the address stored at .Laaa is that of a symbol which has the
18932 Thumb_Func bit set, then the linker will arrange for this address
18933 to have the bottom bit set, which in turn would mean that the
18934 address computation performed by the third instruction would end
18935 up with the bottom bit set. Since the ARM is capable of unaligned
18936 word loads, the instruction would then load the incorrect address
18937 out of the jump table, and chaos would ensue. */
18938 if (label_is_thumb_function_name
18939 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18940 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18942 /* When the address of a Thumb function is taken the bottom
18943 bit of that address should be set. This will allow
18944 interworking between Arm and Thumb functions to work
18947 THUMB_SET_FUNC (sym
, 1);
18949 label_is_thumb_function_name
= FALSE
;
18952 dwarf2_emit_label (sym
);
18956 arm_data_in_code (void)
18958 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18960 *input_line_pointer
= '/';
18961 input_line_pointer
+= 5;
18962 *input_line_pointer
= 0;
18970 arm_canonicalize_symbol_name (char * name
)
18974 if (thumb_mode
&& (len
= strlen (name
)) > 5
18975 && streq (name
+ len
- 5, "/data"))
18976 *(name
+ len
- 5) = 0;
18981 /* Table of all register names defined by default. The user can
18982 define additional names with .req. Note that all register names
18983 should appear in both upper and lowercase variants. Some registers
18984 also have mixed-case names. */
18986 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18987 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18988 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18989 #define REGSET(p,t) \
18990 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18991 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18992 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18993 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18994 #define REGSETH(p,t) \
18995 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18996 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18997 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18998 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18999 #define REGSET2(p,t) \
19000 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19001 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19002 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19003 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19004 #define SPLRBANK(base,bank,t) \
19005 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19006 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19007 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19008 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19009 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19010 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19012 static const struct reg_entry reg_names
[] =
19014 /* ARM integer registers. */
19015 REGSET(r
, RN
), REGSET(R
, RN
),
19017 /* ATPCS synonyms. */
19018 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19019 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19020 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19022 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19023 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19024 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19026 /* Well-known aliases. */
19027 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19028 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19030 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19031 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19033 /* Coprocessor numbers. */
19034 REGSET(p
, CP
), REGSET(P
, CP
),
19036 /* Coprocessor register numbers. The "cr" variants are for backward
19038 REGSET(c
, CN
), REGSET(C
, CN
),
19039 REGSET(cr
, CN
), REGSET(CR
, CN
),
19041 /* ARM banked registers. */
19042 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19043 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19044 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19045 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19046 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19047 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19048 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19050 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19051 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19052 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19053 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19054 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19055 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19056 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19057 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19059 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19060 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19061 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19062 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19063 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19064 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19065 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19066 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19067 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19069 /* FPA registers. */
19070 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19071 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19073 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19074 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19076 /* VFP SP registers. */
19077 REGSET(s
,VFS
), REGSET(S
,VFS
),
19078 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19080 /* VFP DP Registers. */
19081 REGSET(d
,VFD
), REGSET(D
,VFD
),
19082 /* Extra Neon DP registers. */
19083 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19085 /* Neon QP registers. */
19086 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19088 /* VFP control registers. */
19089 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19090 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19091 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19092 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19093 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19094 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19095 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19097 /* Maverick DSP coprocessor registers. */
19098 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19099 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19101 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19102 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19103 REGDEF(dspsc
,0,DSPSC
),
19105 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19106 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19107 REGDEF(DSPSC
,0,DSPSC
),
19109 /* iWMMXt data registers - p0, c0-15. */
19110 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19112 /* iWMMXt control registers - p1, c0-3. */
19113 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19114 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19115 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19116 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19118 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19119 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19120 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19121 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19122 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19124 /* XScale accumulator registers. */
19125 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19131 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19132 within psr_required_here. */
19133 static const struct asm_psr psrs
[] =
19135 /* Backward compatibility notation. Note that "all" is no longer
19136 truly all possible PSR bits. */
19137 {"all", PSR_c
| PSR_f
},
19141 /* Individual flags. */
19147 /* Combinations of flags. */
19148 {"fs", PSR_f
| PSR_s
},
19149 {"fx", PSR_f
| PSR_x
},
19150 {"fc", PSR_f
| PSR_c
},
19151 {"sf", PSR_s
| PSR_f
},
19152 {"sx", PSR_s
| PSR_x
},
19153 {"sc", PSR_s
| PSR_c
},
19154 {"xf", PSR_x
| PSR_f
},
19155 {"xs", PSR_x
| PSR_s
},
19156 {"xc", PSR_x
| PSR_c
},
19157 {"cf", PSR_c
| PSR_f
},
19158 {"cs", PSR_c
| PSR_s
},
19159 {"cx", PSR_c
| PSR_x
},
19160 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19161 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19162 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19163 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19164 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19165 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19166 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19167 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19168 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19169 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19170 {"scf", PSR_s
| PSR_c
| PSR_f
},
19171 {"scx", PSR_s
| PSR_c
| PSR_x
},
19172 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19173 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19174 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19175 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19176 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19177 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19178 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19179 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19180 {"csf", PSR_c
| PSR_s
| PSR_f
},
19181 {"csx", PSR_c
| PSR_s
| PSR_x
},
19182 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19183 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19184 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19185 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19186 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19187 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19188 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19189 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19190 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19191 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19192 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19193 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19194 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19195 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19196 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19197 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19198 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19199 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19200 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19201 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19202 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19203 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19204 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19205 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19206 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19207 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19210 /* Table of V7M psr names. */
19211 static const struct asm_psr v7m_psrs
[] =
19213 {"apsr", 0x0 }, {"APSR", 0x0 },
19214 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19215 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19216 {"psr", 0x3 }, {"PSR", 0x3 },
19217 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19218 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19219 {"epsr", 0x6 }, {"EPSR", 0x6 },
19220 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19221 {"msp", 0x8 }, {"MSP", 0x8 },
19222 {"psp", 0x9 }, {"PSP", 0x9 },
19223 {"msplim", 0xa }, {"MSPLIM", 0xa },
19224 {"psplim", 0xb }, {"PSPLIM", 0xb },
19225 {"primask", 0x10}, {"PRIMASK", 0x10},
19226 {"basepri", 0x11}, {"BASEPRI", 0x11},
19227 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19228 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19229 {"control", 0x14}, {"CONTROL", 0x14},
19230 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19231 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19232 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19233 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19234 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19235 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19236 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19237 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19238 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19241 /* Table of all shift-in-operand names. */
19242 static const struct asm_shift_name shift_names
[] =
19244 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19245 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19246 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19247 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19248 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19249 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19252 /* Table of all explicit relocation names. */
19254 static struct reloc_entry reloc_names
[] =
19256 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19257 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19258 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19259 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19260 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19261 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19262 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19263 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19264 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19265 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19266 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19267 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19268 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19269 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19270 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19271 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19272 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19273 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19277 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19278 static const struct asm_cond conds
[] =
19282 {"cs", 0x2}, {"hs", 0x2},
19283 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19297 #define UL_BARRIER(L,U,CODE,FEAT) \
19298 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19299 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19301 static struct asm_barrier_opt barrier_opt_names
[] =
19303 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19304 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19305 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19306 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19307 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19308 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19309 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19310 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19311 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19312 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19313 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19314 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19315 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19316 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19317 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19318 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19323 /* Table of ARM-format instructions. */
19325 /* Macros for gluing together operand strings. N.B. In all cases
19326 other than OPS0, the trailing OP_stop comes from default
19327 zero-initialization of the unspecified elements of the array. */
19328 #define OPS0() { OP_stop, }
19329 #define OPS1(a) { OP_##a, }
19330 #define OPS2(a,b) { OP_##a,OP_##b, }
19331 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19332 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19333 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19334 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19336 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19337 This is useful when mixing operands for ARM and THUMB, i.e. using the
19338 MIX_ARM_THUMB_OPERANDS macro.
19339 In order to use these macros, prefix the number of operands with _
19341 #define OPS_1(a) { a, }
19342 #define OPS_2(a,b) { a,b, }
19343 #define OPS_3(a,b,c) { a,b,c, }
19344 #define OPS_4(a,b,c,d) { a,b,c,d, }
19345 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19346 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19348 /* These macros abstract out the exact format of the mnemonic table and
19349 save some repeated characters. */
19351 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19352 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19353 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19354 THUMB_VARIANT, do_##ae, do_##te }
19356 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19357 a T_MNEM_xyz enumerator. */
19358 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19359 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19360 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19361 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19363 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19364 infix after the third character. */
19365 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19366 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19367 THUMB_VARIANT, do_##ae, do_##te }
19368 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19369 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19370 THUMB_VARIANT, do_##ae, do_##te }
19371 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19372 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19373 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19374 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19375 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19376 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19377 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19378 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19380 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19381 field is still 0xE. Many of the Thumb variants can be executed
19382 conditionally, so this is checked separately. */
19383 #define TUE(mnem, op, top, nops, ops, ae, te) \
19384 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19385 THUMB_VARIANT, do_##ae, do_##te }
19387 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19388 Used by mnemonics that have very minimal differences in the encoding for
19389 ARM and Thumb variants and can be handled in a common function. */
19390 #define TUEc(mnem, op, top, nops, ops, en) \
19391 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19392 THUMB_VARIANT, do_##en, do_##en }
19394 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19395 condition code field. */
19396 #define TUF(mnem, op, top, nops, ops, ae, te) \
19397 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19398 THUMB_VARIANT, do_##ae, do_##te }
19400 /* ARM-only variants of all the above. */
19401 #define CE(mnem, op, nops, ops, ae) \
19402 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19404 #define C3(mnem, op, nops, ops, ae) \
19405 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19407 /* Legacy mnemonics that always have conditional infix after the third
19409 #define CL(mnem, op, nops, ops, ae) \
19410 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19411 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19413 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19414 #define cCE(mnem, op, nops, ops, ae) \
19415 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19417 /* Legacy coprocessor instructions where conditional infix and conditional
19418 suffix are ambiguous. For consistency this includes all FPA instructions,
19419 not just the potentially ambiguous ones. */
19420 #define cCL(mnem, op, nops, ops, ae) \
19421 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19422 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19424 /* Coprocessor, takes either a suffix or a position-3 infix
19425 (for an FPA corner case). */
19426 #define C3E(mnem, op, nops, ops, ae) \
19427 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19428 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19430 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19431 { m1 #m2 m3, OPS##nops ops, \
19432 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19433 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19435 #define CM(m1, m2, op, nops, ops, ae) \
19436 xCM_ (m1, , m2, op, nops, ops, ae), \
19437 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19438 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19439 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19440 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19441 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19442 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19443 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19444 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19445 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19446 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19447 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19448 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19449 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19450 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19451 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19452 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19453 xCM_ (m1, le, m2, op, nops, ops, ae), \
19454 xCM_ (m1, al, m2, op, nops, ops, ae)
19456 #define UE(mnem, op, nops, ops, ae) \
19457 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19459 #define UF(mnem, op, nops, ops, ae) \
19460 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19462 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19463 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19464 use the same encoding function for each. */
19465 #define NUF(mnem, op, nops, ops, enc) \
19466 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19467 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19469 /* Neon data processing, version which indirects through neon_enc_tab for
19470 the various overloaded versions of opcodes. */
19471 #define nUF(mnem, op, nops, ops, enc) \
19472 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19473 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19475 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19477 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19478 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19479 THUMB_VARIANT, do_##enc, do_##enc }
19481 #define NCE(mnem, op, nops, ops, enc) \
19482 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19484 #define NCEF(mnem, op, nops, ops, enc) \
19485 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19487 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19488 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19489 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19490 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19492 #define nCE(mnem, op, nops, ops, enc) \
19493 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19495 #define nCEF(mnem, op, nops, ops, enc) \
19496 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19500 static const struct asm_opcode insns
[] =
19502 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19503 #define THUMB_VARIANT & arm_ext_v4t
19504 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19505 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19506 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19507 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19508 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19509 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19510 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19511 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19512 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19513 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19514 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19515 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19516 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19517 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19518 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19519 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19521 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19522 for setting PSR flag bits. They are obsolete in V6 and do not
19523 have Thumb equivalents. */
19524 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19525 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19526 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19527 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19528 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19529 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19530 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19531 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19532 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19534 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19535 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19536 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19537 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19539 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19540 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19541 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19543 OP_ADDRGLDR
),ldst
, t_ldst
),
19544 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19546 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19547 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19548 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19549 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19550 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19551 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19553 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19554 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19557 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19558 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19559 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19560 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19562 /* Thumb-compatibility pseudo ops. */
19563 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19564 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19565 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19566 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19567 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19568 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19569 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19570 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19571 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19572 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19573 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19574 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19576 /* These may simplify to neg. */
19577 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19578 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19580 #undef THUMB_VARIANT
19581 #define THUMB_VARIANT & arm_ext_os
19583 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19584 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19586 #undef THUMB_VARIANT
19587 #define THUMB_VARIANT & arm_ext_v6
19589 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19591 /* V1 instructions with no Thumb analogue prior to V6T2. */
19592 #undef THUMB_VARIANT
19593 #define THUMB_VARIANT & arm_ext_v6t2
19595 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19596 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19597 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19599 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19600 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19601 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19602 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19604 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19605 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19607 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19608 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19610 /* V1 instructions with no Thumb analogue at all. */
19611 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19612 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19614 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19615 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19616 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19617 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19618 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19619 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19620 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19621 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19624 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19625 #undef THUMB_VARIANT
19626 #define THUMB_VARIANT & arm_ext_v4t
19628 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19629 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19631 #undef THUMB_VARIANT
19632 #define THUMB_VARIANT & arm_ext_v6t2
19634 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19635 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19637 /* Generic coprocessor instructions. */
19638 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19639 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19640 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19641 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19642 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19643 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19644 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19647 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19649 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19650 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19653 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19654 #undef THUMB_VARIANT
19655 #define THUMB_VARIANT & arm_ext_msr
19657 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19658 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19661 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19662 #undef THUMB_VARIANT
19663 #define THUMB_VARIANT & arm_ext_v6t2
19665 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19666 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19667 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19668 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19669 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19670 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19671 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19672 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19675 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19676 #undef THUMB_VARIANT
19677 #define THUMB_VARIANT & arm_ext_v4t
19679 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19680 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19681 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19682 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19683 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19684 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19687 #define ARM_VARIANT & arm_ext_v4t_5
19689 /* ARM Architecture 4T. */
19690 /* Note: bx (and blx) are required on V5, even if the processor does
19691 not support Thumb. */
19692 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19695 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19696 #undef THUMB_VARIANT
19697 #define THUMB_VARIANT & arm_ext_v5t
19699 /* Note: blx has 2 variants; the .value coded here is for
19700 BLX(2). Only this variant has conditional execution. */
19701 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19702 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19704 #undef THUMB_VARIANT
19705 #define THUMB_VARIANT & arm_ext_v6t2
19707 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19708 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19709 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19710 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19711 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19712 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19713 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19714 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19717 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19718 #undef THUMB_VARIANT
19719 #define THUMB_VARIANT & arm_ext_v5exp
19721 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19722 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19723 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19724 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19726 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19727 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19729 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19730 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19731 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19732 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19734 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19735 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19736 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19737 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19739 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19740 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19742 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19743 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19744 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19745 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19748 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19749 #undef THUMB_VARIANT
19750 #define THUMB_VARIANT & arm_ext_v6t2
19752 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19753 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19755 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19756 ADDRGLDRS
), ldrd
, t_ldstd
),
19758 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19759 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19762 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19764 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19767 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19768 #undef THUMB_VARIANT
19769 #define THUMB_VARIANT & arm_ext_v6
19771 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19772 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19773 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19774 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19775 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19776 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19777 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19778 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19779 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19780 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19782 #undef THUMB_VARIANT
19783 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19785 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19786 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19788 #undef THUMB_VARIANT
19789 #define THUMB_VARIANT & arm_ext_v6t2
19791 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19792 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19794 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19795 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19797 /* ARM V6 not included in V7M. */
19798 #undef THUMB_VARIANT
19799 #define THUMB_VARIANT & arm_ext_v6_notm
19800 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19801 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19802 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19803 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19804 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19805 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19806 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19807 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19808 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19809 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19810 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19811 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19812 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19813 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19814 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19815 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19816 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19817 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19818 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19820 /* ARM V6 not included in V7M (eg. integer SIMD). */
19821 #undef THUMB_VARIANT
19822 #define THUMB_VARIANT & arm_ext_v6_dsp
19823 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19824 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19825 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19826 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19827 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19828 /* Old name for QASX. */
19829 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19830 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19831 /* Old name for QSAX. */
19832 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19833 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19834 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19835 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19836 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19837 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19838 /* Old name for SASX. */
19839 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19840 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19841 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19842 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19843 /* Old name for SHASX. */
19844 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19845 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19846 /* Old name for SHSAX. */
19847 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19848 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19849 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19850 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19851 /* Old name for SSAX. */
19852 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19853 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19854 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19855 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19856 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19857 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19858 /* Old name for UASX. */
19859 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19860 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19861 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19862 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19863 /* Old name for UHASX. */
19864 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19865 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19866 /* Old name for UHSAX. */
19867 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19868 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19869 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19870 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19871 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19872 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19873 /* Old name for UQASX. */
19874 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19875 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19876 /* Old name for UQSAX. */
19877 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19878 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19879 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19880 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19881 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19882 /* Old name for USAX. */
19883 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19884 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19885 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19886 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19887 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19888 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19889 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19890 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19891 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19892 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19893 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19894 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19895 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19896 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19897 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19898 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19899 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19900 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19901 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19902 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19903 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19904 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19905 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19906 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19907 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19908 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19909 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19910 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19911 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19912 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19913 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19914 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19915 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19916 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19919 #define ARM_VARIANT & arm_ext_v6k
19920 #undef THUMB_VARIANT
19921 #define THUMB_VARIANT & arm_ext_v6k
19923 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19924 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19925 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19926 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19928 #undef THUMB_VARIANT
19929 #define THUMB_VARIANT & arm_ext_v6_notm
19930 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19932 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19933 RRnpcb
), strexd
, t_strexd
),
19935 #undef THUMB_VARIANT
19936 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19937 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19939 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19941 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19943 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19945 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19948 #define ARM_VARIANT & arm_ext_sec
19949 #undef THUMB_VARIANT
19950 #define THUMB_VARIANT & arm_ext_sec
19952 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19955 #define ARM_VARIANT & arm_ext_virt
19956 #undef THUMB_VARIANT
19957 #define THUMB_VARIANT & arm_ext_virt
19959 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19960 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19963 #define ARM_VARIANT & arm_ext_pan
19964 #undef THUMB_VARIANT
19965 #define THUMB_VARIANT & arm_ext_pan
19967 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19970 #define ARM_VARIANT & arm_ext_v6t2
19971 #undef THUMB_VARIANT
19972 #define THUMB_VARIANT & arm_ext_v6t2
19974 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19975 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19976 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19977 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19979 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19980 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19982 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19983 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19984 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19985 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19987 #undef THUMB_VARIANT
19988 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19989 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19990 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19992 /* Thumb-only instructions. */
19994 #define ARM_VARIANT NULL
19995 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19996 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19998 /* ARM does not really have an IT instruction, so always allow it.
19999 The opcode is copied from Thumb in order to allow warnings in
20000 -mimplicit-it=[never | arm] modes. */
20002 #define ARM_VARIANT & arm_ext_v1
20003 #undef THUMB_VARIANT
20004 #define THUMB_VARIANT & arm_ext_v6t2
20006 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20007 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20008 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20009 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20010 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20011 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20012 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20013 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20014 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20015 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20016 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20017 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20018 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20019 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20020 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20021 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20022 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20023 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20025 /* Thumb2 only instructions. */
20027 #define ARM_VARIANT NULL
20029 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20030 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20031 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20032 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20033 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20034 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20036 /* Hardware division instructions. */
20038 #define ARM_VARIANT & arm_ext_adiv
20039 #undef THUMB_VARIANT
20040 #define THUMB_VARIANT & arm_ext_div
20042 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20043 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20045 /* ARM V6M/V7 instructions. */
20047 #define ARM_VARIANT & arm_ext_barrier
20048 #undef THUMB_VARIANT
20049 #define THUMB_VARIANT & arm_ext_barrier
20051 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20052 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20053 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20055 /* ARM V7 instructions. */
20057 #define ARM_VARIANT & arm_ext_v7
20058 #undef THUMB_VARIANT
20059 #define THUMB_VARIANT & arm_ext_v7
20061 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20062 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20065 #define ARM_VARIANT & arm_ext_mp
20066 #undef THUMB_VARIANT
20067 #define THUMB_VARIANT & arm_ext_mp
20069 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20071 /* AArchv8 instructions. */
20073 #define ARM_VARIANT & arm_ext_v8
20075 /* Instructions shared between armv8-a and armv8-m. */
20076 #undef THUMB_VARIANT
20077 #define THUMB_VARIANT & arm_ext_atomics
20079 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20080 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20081 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20082 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20083 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20084 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20085 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20086 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20087 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20088 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20090 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20092 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20094 #undef THUMB_VARIANT
20095 #define THUMB_VARIANT & arm_ext_v8
20097 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20098 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20099 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20101 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20103 /* ARMv8 T32 only. */
20105 #define ARM_VARIANT NULL
20106 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20107 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20108 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20110 /* FP for ARMv8. */
20112 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20113 #undef THUMB_VARIANT
20114 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20116 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20117 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20118 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20119 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20120 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20121 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20122 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20123 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20124 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20125 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20126 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20127 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20128 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20129 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20130 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20131 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20132 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20134 /* Crypto v1 extensions. */
20136 #define ARM_VARIANT & fpu_crypto_ext_armv8
20137 #undef THUMB_VARIANT
20138 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20140 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20141 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20142 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20143 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20144 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20145 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20146 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20147 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20148 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20149 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20150 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20151 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20152 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20153 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20156 #define ARM_VARIANT & crc_ext_armv8
20157 #undef THUMB_VARIANT
20158 #define THUMB_VARIANT & crc_ext_armv8
20159 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20160 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20161 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20162 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20163 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20164 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20166 /* ARMv8.2 RAS extension. */
20168 #define ARM_VARIANT & arm_ext_ras
20169 #undef THUMB_VARIANT
20170 #define THUMB_VARIANT & arm_ext_ras
20171 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20174 #define ARM_VARIANT & arm_ext_v8_3
20175 #undef THUMB_VARIANT
20176 #define THUMB_VARIANT & arm_ext_v8_3
20177 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20178 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20179 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20182 #define ARM_VARIANT & fpu_neon_ext_dotprod
20183 #undef THUMB_VARIANT
20184 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20185 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20186 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20189 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20190 #undef THUMB_VARIANT
20191 #define THUMB_VARIANT NULL
20193 cCE("wfs", e200110
, 1, (RR
), rd
),
20194 cCE("rfs", e300110
, 1, (RR
), rd
),
20195 cCE("wfc", e400110
, 1, (RR
), rd
),
20196 cCE("rfc", e500110
, 1, (RR
), rd
),
20198 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20199 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20200 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20201 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20203 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20204 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20205 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20206 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20208 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20209 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20210 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20211 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20212 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20213 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20214 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20215 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20216 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20217 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20218 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20219 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20221 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20222 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20223 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20224 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20225 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20226 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20227 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20228 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20229 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20230 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20231 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20232 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20234 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20235 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20236 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20237 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20238 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20239 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20240 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20241 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20242 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20243 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20244 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20245 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20247 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20248 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20249 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20250 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20251 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20252 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20253 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20254 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20255 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20256 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20257 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20258 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20260 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20261 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20262 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20263 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20264 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20265 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20266 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20267 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20268 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20269 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20270 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20271 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20273 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20274 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20275 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20276 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20277 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20278 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20279 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20280 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20281 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20282 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20283 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20284 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20286 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20287 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20288 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20289 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20290 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20291 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20293 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20301 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20303 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20306 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20314 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20327 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20414 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20417 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20418 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20419 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20420 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20421 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20422 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20423 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20424 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20425 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20426 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20427 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20429 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20430 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20431 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20432 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20433 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20434 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20435 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20436 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20437 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20438 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20439 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20440 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20442 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20443 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20444 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20445 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20446 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20447 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20448 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20449 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20450 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20451 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20452 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20453 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20455 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20456 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20457 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20458 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20459 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20460 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20461 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20462 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20463 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20464 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20465 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20466 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20468 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20469 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20470 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20471 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20472 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20473 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20474 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20475 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20476 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20477 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20478 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20479 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20481 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20482 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20483 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20484 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20485 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20486 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20487 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20488 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20489 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20490 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20491 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20492 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20494 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20495 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20496 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20497 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20498 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20499 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20501 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20509 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20511 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20514 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20522 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20535 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20583 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20586 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20587 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20588 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20590 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20591 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20592 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20593 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20594 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20595 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20596 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20597 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20598 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20599 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20600 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20601 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20603 /* The implementation of the FIX instruction is broken on some
20604 assemblers, in that it accepts a precision specifier as well as a
20605 rounding specifier, despite the fact that this is meaningless.
20606 To be more compatible, we accept it as well, though of course it
20607 does not set any bits. */
20608 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20609 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20610 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20611 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20612 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20613 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20614 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20615 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20616 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20617 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20618 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20619 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20620 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20622 /* Instructions that were new with the real FPA, call them V2. */
20624 #define ARM_VARIANT & fpu_fpa_ext_v2
20626 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20627 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20628 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20629 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20630 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20631 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20634 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20636 /* Moves and type conversions. */
20637 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20638 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20639 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20640 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20641 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20642 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20643 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20644 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20645 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20646 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20647 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20648 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20649 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20650 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20652 /* Memory operations. */
20653 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20654 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20655 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20656 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20657 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20658 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20659 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20660 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20661 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20662 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20663 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20664 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20665 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20666 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20667 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20668 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20669 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20670 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20672 /* Monadic operations. */
20673 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20674 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20675 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20677 /* Dyadic operations. */
20678 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20679 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20680 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20681 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20682 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20683 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20684 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20685 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20686 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20689 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20690 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20691 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20692 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20694 /* Double precision load/store are still present on single precision
20695 implementations. */
20696 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20697 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20698 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20699 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20700 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20701 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20702 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20703 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20704 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20705 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20708 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20710 /* Moves and type conversions. */
20711 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20712 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20713 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20714 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20715 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20716 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20717 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20718 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20719 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20720 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20721 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20722 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20723 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20725 /* Monadic operations. */
20726 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20727 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20728 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20730 /* Dyadic operations. */
20731 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20732 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20733 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20734 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20735 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20736 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20737 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20738 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20739 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20742 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20743 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20744 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20745 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20748 #define ARM_VARIANT & fpu_vfp_ext_v2
20750 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20751 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20752 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20753 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20755 /* Instructions which may belong to either the Neon or VFP instruction sets.
20756 Individual encoder functions perform additional architecture checks. */
20758 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20759 #undef THUMB_VARIANT
20760 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20762 /* These mnemonics are unique to VFP. */
20763 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20764 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20765 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20766 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20767 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20768 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20769 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20770 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20771 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20772 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20774 /* Mnemonics shared by Neon and VFP. */
20775 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20776 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20777 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20779 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20780 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20782 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20783 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20785 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20786 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20787 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20788 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20789 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20790 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20791 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20792 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20794 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20795 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20796 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20797 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20800 /* NOTE: All VMOV encoding is special-cased! */
20801 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20802 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20805 #define ARM_VARIANT & arm_ext_fp16
20806 #undef THUMB_VARIANT
20807 #define THUMB_VARIANT & arm_ext_fp16
20808 /* New instructions added from v8.2, allowing the extraction and insertion of
20809 the upper 16 bits of a 32-bit vector register. */
20810 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20811 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20813 /* New backported fma/fms instructions optional in v8.2. */
20814 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20815 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20817 #undef THUMB_VARIANT
20818 #define THUMB_VARIANT & fpu_neon_ext_v1
20820 #define ARM_VARIANT & fpu_neon_ext_v1
20822 /* Data processing with three registers of the same length. */
20823 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20824 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20825 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20826 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20827 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20828 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20829 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20830 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20831 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20832 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20833 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20834 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20835 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20836 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20837 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20838 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20839 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20840 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20841 /* If not immediate, fall back to neon_dyadic_i64_su.
20842 shl_imm should accept I8 I16 I32 I64,
20843 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20844 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20845 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20846 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20847 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20848 /* Logic ops, types optional & ignored. */
20849 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20850 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20851 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20852 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20853 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20854 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20855 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20856 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20857 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20858 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20859 /* Bitfield ops, untyped. */
20860 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20861 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20862 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20863 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20864 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20865 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20866 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20867 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20868 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20869 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20870 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20871 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20872 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20873 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20874 back to neon_dyadic_if_su. */
20875 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20876 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20877 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20878 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20879 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20880 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20881 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20882 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20883 /* Comparison. Type I8 I16 I32 F32. */
20884 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20885 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20886 /* As above, D registers only. */
20887 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20888 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20889 /* Int and float variants, signedness unimportant. */
20890 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20891 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20892 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20893 /* Add/sub take types I8 I16 I32 I64 F32. */
20894 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20895 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20896 /* vtst takes sizes 8, 16, 32. */
20897 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20898 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20899 /* VMUL takes I8 I16 I32 F32 P8. */
20900 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20901 /* VQD{R}MULH takes S16 S32. */
20902 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20903 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20904 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20905 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20906 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20907 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20908 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20909 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20910 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20911 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20912 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20913 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20914 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20915 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20916 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20917 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20918 /* ARM v8.1 extension. */
20919 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20920 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20921 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20922 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20924 /* Two address, int/float. Types S8 S16 S32 F32. */
20925 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20926 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20928 /* Data processing with two registers and a shift amount. */
20929 /* Right shifts, and variants with rounding.
20930 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20931 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20932 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20933 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20934 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20935 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20936 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20937 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20938 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20939 /* Shift and insert. Sizes accepted 8 16 32 64. */
20940 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20941 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20942 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20943 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20944 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20945 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20946 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20947 /* Right shift immediate, saturating & narrowing, with rounding variants.
20948 Types accepted S16 S32 S64 U16 U32 U64. */
20949 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20950 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20951 /* As above, unsigned. Types accepted S16 S32 S64. */
20952 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20953 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20954 /* Right shift narrowing. Types accepted I16 I32 I64. */
20955 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20956 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20957 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20958 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20959 /* CVT with optional immediate for fixed-point variant. */
20960 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20962 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20963 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20965 /* Data processing, three registers of different lengths. */
20966 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20967 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20968 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20969 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20970 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20971 /* If not scalar, fall back to neon_dyadic_long.
20972 Vector types as above, scalar types S16 S32 U16 U32. */
20973 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20974 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20975 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20976 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20977 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20978 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20979 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20980 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20981 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20982 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20983 /* Saturating doubling multiplies. Types S16 S32. */
20984 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20985 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20986 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20987 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20988 S16 S32 U16 U32. */
20989 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20991 /* Extract. Size 8. */
20992 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20993 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20995 /* Two registers, miscellaneous. */
20996 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20997 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20998 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20999 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21000 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21001 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21002 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21003 /* Vector replicate. Sizes 8 16 32. */
21004 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21005 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21006 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21007 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21008 /* VMOVN. Types I16 I32 I64. */
21009 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21010 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21011 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21012 /* VQMOVUN. Types S16 S32 S64. */
21013 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21014 /* VZIP / VUZP. Sizes 8 16 32. */
21015 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21016 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21017 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21018 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21019 /* VQABS / VQNEG. Types S8 S16 S32. */
21020 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21021 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21022 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21023 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21024 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21025 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21026 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21027 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21028 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21029 /* Reciprocal estimates. Types U32 F16 F32. */
21030 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21031 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21032 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21033 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21034 /* VCLS. Types S8 S16 S32. */
21035 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21036 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21037 /* VCLZ. Types I8 I16 I32. */
21038 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21039 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21040 /* VCNT. Size 8. */
21041 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21042 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21043 /* Two address, untyped. */
21044 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21045 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21046 /* VTRN. Sizes 8 16 32. */
21047 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21048 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21050 /* Table lookup. Size 8. */
21051 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21052 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21054 #undef THUMB_VARIANT
21055 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21057 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21059 /* Neon element/structure load/store. */
21060 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21061 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21062 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21063 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21064 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21065 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21066 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21067 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21069 #undef THUMB_VARIANT
21070 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21072 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21073 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21074 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21075 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21076 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21077 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21078 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21079 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21080 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21081 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21083 #undef THUMB_VARIANT
21084 #define THUMB_VARIANT & fpu_vfp_ext_v3
21086 #define ARM_VARIANT & fpu_vfp_ext_v3
21088 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21089 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21090 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21091 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21092 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21093 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21094 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21095 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21096 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21099 #define ARM_VARIANT & fpu_vfp_ext_fma
21100 #undef THUMB_VARIANT
21101 #define THUMB_VARIANT & fpu_vfp_ext_fma
21102 /* Mnemonics shared by Neon and VFP. These are included in the
21103 VFP FMA variant; NEON and VFP FMA always includes the NEON
21104 FMA instructions. */
21105 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21106 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21107 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21108 the v form should always be used. */
21109 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21110 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21111 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21112 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21113 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21114 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21116 #undef THUMB_VARIANT
21118 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21120 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21121 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21122 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21123 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21124 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21125 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21126 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21127 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21130 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21132 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21133 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21134 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21135 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21136 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21137 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21138 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21139 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21140 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21141 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21142 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21143 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21144 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21145 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21146 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21147 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21148 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21149 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21150 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21151 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21152 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21153 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21154 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21155 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21156 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21157 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21158 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21159 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21160 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21161 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21162 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21163 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21164 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21165 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21166 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21167 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21168 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21169 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21170 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21171 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21172 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21173 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21174 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21175 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21176 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21177 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21178 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21179 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21180 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21181 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21182 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21183 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21184 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21185 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21186 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21187 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21188 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21189 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21190 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21191 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21192 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21193 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21194 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21195 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21196 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21197 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21198 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21199 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21200 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21201 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21202 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21203 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21204 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21205 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21206 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21207 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21208 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21209 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21210 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21211 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21212 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21213 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21214 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21215 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21216 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21217 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21218 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21219 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21220 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21221 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21222 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21223 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21224 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21225 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21226 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21227 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21228 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21229 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21230 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21231 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21232 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21233 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21234 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21235 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21236 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21237 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21238 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21239 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21240 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21241 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21242 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21243 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21244 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21245 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21246 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21247 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21248 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21249 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21250 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21251 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21252 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21253 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21254 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21255 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21256 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21257 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21258 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21259 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21260 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21261 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21262 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21263 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21264 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21265 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21266 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21267 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21268 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21269 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21270 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21271 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21272 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21274 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21275 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21276 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21277 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21278 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21279 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21280 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21282 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21283 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21284 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21285 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21286 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21287 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21288 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21289 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21290 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21291 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21292 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21296 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21298 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21299 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21300 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21301 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21302 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21303 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21304 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21314 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21316 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21317 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21318 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21319 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21320 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21321 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21322 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21323 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21324 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21325 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21326 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21327 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21328 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21329 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21330 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21340 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21341 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21343 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21344 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21345 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21346 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21347 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21348 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21349 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21350 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21351 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21352 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21353 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21354 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21357 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21359 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21360 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21361 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21362 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21363 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21364 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21365 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21366 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21367 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21368 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21369 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21370 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21371 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21372 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21373 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21374 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21375 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21376 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21377 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21378 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21379 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21380 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21381 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21382 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21383 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21384 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21385 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21386 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21387 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21388 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21389 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21390 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21391 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21392 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21393 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21394 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21395 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21396 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21397 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21398 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21399 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21400 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21401 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21402 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21403 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21404 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21405 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21406 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21407 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21408 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21409 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21410 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21411 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21412 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21413 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21414 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21415 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21416 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21417 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21418 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21419 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21420 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21421 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21422 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21423 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21424 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21425 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21426 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21427 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21428 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21429 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21430 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21431 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21432 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21433 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21434 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21436 /* ARMv8-M instructions. */
21438 #define ARM_VARIANT NULL
21439 #undef THUMB_VARIANT
21440 #define THUMB_VARIANT & arm_ext_v8m
21441 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21442 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21443 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21444 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21445 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21446 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21447 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21449 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21450 instructions behave as nop if no VFP is present. */
21451 #undef THUMB_VARIANT
21452 #define THUMB_VARIANT & arm_ext_v8m_main
21453 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21454 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21457 #undef THUMB_VARIANT
21483 /* MD interface: bits in the object file. */
21485 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21486 for use in the a.out file, and stores them in the array pointed to by buf.
21487 This knows about the endian-ness of the target machine and does
21488 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21489 2 (short) and 4 (long) Floating numbers are put out as a series of
21490 LITTLENUMS (shorts, here at least). */
21493 md_number_to_chars (char * buf
, valueT val
, int n
)
21495 if (target_big_endian
)
21496 number_to_chars_bigendian (buf
, val
, n
);
21498 number_to_chars_littleendian (buf
, val
, n
);
21502 md_chars_to_number (char * buf
, int n
)
21505 unsigned char * where
= (unsigned char *) buf
;
21507 if (target_big_endian
)
21512 result
|= (*where
++ & 255);
21520 result
|= (where
[n
] & 255);
21527 /* MD interface: Sections. */
21529 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21530 that an rs_machine_dependent frag may reach. */
21533 arm_frag_max_var (fragS
*fragp
)
21535 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21536 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21538 Note that we generate relaxable instructions even for cases that don't
21539 really need it, like an immediate that's a trivial constant. So we're
21540 overestimating the instruction size for some of those cases. Rather
21541 than putting more intelligence here, it would probably be better to
21542 avoid generating a relaxation frag in the first place when it can be
21543 determined up front that a short instruction will suffice. */
21545 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21549 /* Estimate the size of a frag before relaxing. Assume everything fits in
21553 md_estimate_size_before_relax (fragS
* fragp
,
21554 segT segtype ATTRIBUTE_UNUSED
)
21560 /* Convert a machine dependent frag. */
21563 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21565 unsigned long insn
;
21566 unsigned long old_op
;
21574 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21576 old_op
= bfd_get_16(abfd
, buf
);
21577 if (fragp
->fr_symbol
)
21579 exp
.X_op
= O_symbol
;
21580 exp
.X_add_symbol
= fragp
->fr_symbol
;
21584 exp
.X_op
= O_constant
;
21586 exp
.X_add_number
= fragp
->fr_offset
;
21587 opcode
= fragp
->fr_subtype
;
21590 case T_MNEM_ldr_pc
:
21591 case T_MNEM_ldr_pc2
:
21592 case T_MNEM_ldr_sp
:
21593 case T_MNEM_str_sp
:
21600 if (fragp
->fr_var
== 4)
21602 insn
= THUMB_OP32 (opcode
);
21603 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21605 insn
|= (old_op
& 0x700) << 4;
21609 insn
|= (old_op
& 7) << 12;
21610 insn
|= (old_op
& 0x38) << 13;
21612 insn
|= 0x00000c00;
21613 put_thumb32_insn (buf
, insn
);
21614 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21618 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21620 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21623 if (fragp
->fr_var
== 4)
21625 insn
= THUMB_OP32 (opcode
);
21626 insn
|= (old_op
& 0xf0) << 4;
21627 put_thumb32_insn (buf
, insn
);
21628 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21632 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21633 exp
.X_add_number
-= 4;
21641 if (fragp
->fr_var
== 4)
21643 int r0off
= (opcode
== T_MNEM_mov
21644 || opcode
== T_MNEM_movs
) ? 0 : 8;
21645 insn
= THUMB_OP32 (opcode
);
21646 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21647 insn
|= (old_op
& 0x700) << r0off
;
21648 put_thumb32_insn (buf
, insn
);
21649 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21653 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21658 if (fragp
->fr_var
== 4)
21660 insn
= THUMB_OP32(opcode
);
21661 put_thumb32_insn (buf
, insn
);
21662 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21665 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21669 if (fragp
->fr_var
== 4)
21671 insn
= THUMB_OP32(opcode
);
21672 insn
|= (old_op
& 0xf00) << 14;
21673 put_thumb32_insn (buf
, insn
);
21674 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21677 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21680 case T_MNEM_add_sp
:
21681 case T_MNEM_add_pc
:
21682 case T_MNEM_inc_sp
:
21683 case T_MNEM_dec_sp
:
21684 if (fragp
->fr_var
== 4)
21686 /* ??? Choose between add and addw. */
21687 insn
= THUMB_OP32 (opcode
);
21688 insn
|= (old_op
& 0xf0) << 4;
21689 put_thumb32_insn (buf
, insn
);
21690 if (opcode
== T_MNEM_add_pc
)
21691 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21693 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21696 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21704 if (fragp
->fr_var
== 4)
21706 insn
= THUMB_OP32 (opcode
);
21707 insn
|= (old_op
& 0xf0) << 4;
21708 insn
|= (old_op
& 0xf) << 16;
21709 put_thumb32_insn (buf
, insn
);
21710 if (insn
& (1 << 20))
21711 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21713 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21716 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21722 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21723 (enum bfd_reloc_code_real
) reloc_type
);
21724 fixp
->fx_file
= fragp
->fr_file
;
21725 fixp
->fx_line
= fragp
->fr_line
;
21726 fragp
->fr_fix
+= fragp
->fr_var
;
21728 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21729 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21730 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21731 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21734 /* Return the size of a relaxable immediate operand instruction.
21735 SHIFT and SIZE specify the form of the allowable immediate. */
21737 relax_immediate (fragS
*fragp
, int size
, int shift
)
21743 /* ??? Should be able to do better than this. */
21744 if (fragp
->fr_symbol
)
21747 low
= (1 << shift
) - 1;
21748 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21749 offset
= fragp
->fr_offset
;
21750 /* Force misaligned offsets to 32-bit variant. */
21753 if (offset
& ~mask
)
21758 /* Get the address of a symbol during relaxation. */
21760 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21766 sym
= fragp
->fr_symbol
;
21767 sym_frag
= symbol_get_frag (sym
);
21768 know (S_GET_SEGMENT (sym
) != absolute_section
21769 || sym_frag
== &zero_address_frag
);
21770 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21772 /* If frag has yet to be reached on this pass, assume it will
21773 move by STRETCH just as we did. If this is not so, it will
21774 be because some frag between grows, and that will force
21778 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21782 /* Adjust stretch for any alignment frag. Note that if have
21783 been expanding the earlier code, the symbol may be
21784 defined in what appears to be an earlier frag. FIXME:
21785 This doesn't handle the fr_subtype field, which specifies
21786 a maximum number of bytes to skip when doing an
21788 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21790 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21793 stretch
= - ((- stretch
)
21794 & ~ ((1 << (int) f
->fr_offset
) - 1));
21796 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21808 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21811 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21816 /* Assume worst case for symbols not known to be in the same section. */
21817 if (fragp
->fr_symbol
== NULL
21818 || !S_IS_DEFINED (fragp
->fr_symbol
)
21819 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21820 || S_IS_WEAK (fragp
->fr_symbol
))
21823 val
= relaxed_symbol_addr (fragp
, stretch
);
21824 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21825 addr
= (addr
+ 4) & ~3;
21826 /* Force misaligned targets to 32-bit variant. */
21830 if (val
< 0 || val
> 1020)
21835 /* Return the size of a relaxable add/sub immediate instruction. */
21837 relax_addsub (fragS
*fragp
, asection
*sec
)
21842 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21843 op
= bfd_get_16(sec
->owner
, buf
);
21844 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21845 return relax_immediate (fragp
, 8, 0);
21847 return relax_immediate (fragp
, 3, 0);
21850 /* Return TRUE iff the definition of symbol S could be pre-empted
21851 (overridden) at link or load time. */
21853 symbol_preemptible (symbolS
*s
)
21855 /* Weak symbols can always be pre-empted. */
21859 /* Non-global symbols cannot be pre-empted. */
21860 if (! S_IS_EXTERNAL (s
))
21864 /* In ELF, a global symbol can be marked protected, or private. In that
21865 case it can't be pre-empted (other definitions in the same link unit
21866 would violate the ODR). */
21867 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21871 /* Other global symbols might be pre-empted. */
21875 /* Return the size of a relaxable branch instruction. BITS is the
21876 size of the offset field in the narrow instruction. */
21879 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21885 /* Assume worst case for symbols not known to be in the same section. */
21886 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21887 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21888 || S_IS_WEAK (fragp
->fr_symbol
))
21892 /* A branch to a function in ARM state will require interworking. */
21893 if (S_IS_DEFINED (fragp
->fr_symbol
)
21894 && ARM_IS_FUNC (fragp
->fr_symbol
))
21898 if (symbol_preemptible (fragp
->fr_symbol
))
21901 val
= relaxed_symbol_addr (fragp
, stretch
);
21902 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21905 /* Offset is a signed value *2 */
21907 if (val
>= limit
|| val
< -limit
)
21913 /* Relax a machine dependent frag. This returns the amount by which
21914 the current size of the frag should change. */
21917 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21922 oldsize
= fragp
->fr_var
;
21923 switch (fragp
->fr_subtype
)
21925 case T_MNEM_ldr_pc2
:
21926 newsize
= relax_adr (fragp
, sec
, stretch
);
21928 case T_MNEM_ldr_pc
:
21929 case T_MNEM_ldr_sp
:
21930 case T_MNEM_str_sp
:
21931 newsize
= relax_immediate (fragp
, 8, 2);
21935 newsize
= relax_immediate (fragp
, 5, 2);
21939 newsize
= relax_immediate (fragp
, 5, 1);
21943 newsize
= relax_immediate (fragp
, 5, 0);
21946 newsize
= relax_adr (fragp
, sec
, stretch
);
21952 newsize
= relax_immediate (fragp
, 8, 0);
21955 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21958 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21960 case T_MNEM_add_sp
:
21961 case T_MNEM_add_pc
:
21962 newsize
= relax_immediate (fragp
, 8, 2);
21964 case T_MNEM_inc_sp
:
21965 case T_MNEM_dec_sp
:
21966 newsize
= relax_immediate (fragp
, 7, 2);
21972 newsize
= relax_addsub (fragp
, sec
);
21978 fragp
->fr_var
= newsize
;
21979 /* Freeze wide instructions that are at or before the same location as
21980 in the previous pass. This avoids infinite loops.
21981 Don't freeze them unconditionally because targets may be artificially
21982 misaligned by the expansion of preceding frags. */
21983 if (stretch
<= 0 && newsize
> 2)
21985 md_convert_frag (sec
->owner
, sec
, fragp
);
21989 return newsize
- oldsize
;
21992 /* Round up a section size to the appropriate boundary. */
21995 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21998 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21999 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
22001 /* For a.out, force the section size to be aligned. If we don't do
22002 this, BFD will align it for us, but it will not write out the
22003 final bytes of the section. This may be a bug in BFD, but it is
22004 easier to fix it here since that is how the other a.out targets
22008 align
= bfd_get_section_alignment (stdoutput
, segment
);
22009 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
22016 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22017 of an rs_align_code fragment. */
22020 arm_handle_align (fragS
* fragP
)
22022 static unsigned char const arm_noop
[2][2][4] =
22025 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22026 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22029 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22030 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22033 static unsigned char const thumb_noop
[2][2][2] =
22036 {0xc0, 0x46}, /* LE */
22037 {0x46, 0xc0}, /* BE */
22040 {0x00, 0xbf}, /* LE */
22041 {0xbf, 0x00} /* BE */
22044 static unsigned char const wide_thumb_noop
[2][4] =
22045 { /* Wide Thumb-2 */
22046 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22047 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22050 unsigned bytes
, fix
, noop_size
;
22052 const unsigned char * noop
;
22053 const unsigned char *narrow_noop
= NULL
;
22058 if (fragP
->fr_type
!= rs_align_code
)
22061 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22062 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22065 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22066 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22068 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22070 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22072 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22073 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22075 narrow_noop
= thumb_noop
[1][target_big_endian
];
22076 noop
= wide_thumb_noop
[target_big_endian
];
22079 noop
= thumb_noop
[0][target_big_endian
];
22087 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22088 ? selected_cpu
: arm_arch_none
,
22090 [target_big_endian
];
22097 fragP
->fr_var
= noop_size
;
22099 if (bytes
& (noop_size
- 1))
22101 fix
= bytes
& (noop_size
- 1);
22103 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22105 memset (p
, 0, fix
);
22112 if (bytes
& noop_size
)
22114 /* Insert a narrow noop. */
22115 memcpy (p
, narrow_noop
, noop_size
);
22117 bytes
-= noop_size
;
22121 /* Use wide noops for the remainder */
22125 while (bytes
>= noop_size
)
22127 memcpy (p
, noop
, noop_size
);
22129 bytes
-= noop_size
;
22133 fragP
->fr_fix
+= fix
;
22136 /* Called from md_do_align. Used to create an alignment
22137 frag in a code section. */
22140 arm_frag_align_code (int n
, int max
)
22144 /* We assume that there will never be a requirement
22145 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22146 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22151 _("alignments greater than %d bytes not supported in .text sections."),
22152 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22153 as_fatal ("%s", err_msg
);
22156 p
= frag_var (rs_align_code
,
22157 MAX_MEM_FOR_RS_ALIGN_CODE
,
22159 (relax_substateT
) max
,
22166 /* Perform target specific initialisation of a frag.
22167 Note - despite the name this initialisation is not done when the frag
22168 is created, but only when its type is assigned. A frag can be created
22169 and used a long time before its type is set, so beware of assuming that
22170 this initialisation is performed first. */
22174 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22176 /* Record whether this frag is in an ARM or a THUMB area. */
22177 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22180 #else /* OBJ_ELF is defined. */
22182 arm_init_frag (fragS
* fragP
, int max_chars
)
22184 bfd_boolean frag_thumb_mode
;
22186 /* If the current ARM vs THUMB mode has not already
22187 been recorded into this frag then do so now. */
22188 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22189 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22191 /* PR 21809: Do not set a mapping state for debug sections
22192 - it just confuses other tools. */
22193 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22196 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22198 /* Record a mapping symbol for alignment frags. We will delete this
22199 later if the alignment ends up empty. */
22200 switch (fragP
->fr_type
)
22203 case rs_align_test
:
22205 mapping_state_2 (MAP_DATA
, max_chars
);
22207 case rs_align_code
:
22208 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22215 /* When we change sections we need to issue a new mapping symbol. */
22218 arm_elf_change_section (void)
22220 /* Link an unlinked unwind index table section to the .text section. */
22221 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22222 && elf_linked_to_section (now_seg
) == NULL
)
22223 elf_linked_to_section (now_seg
) = text_section
;
22227 arm_elf_section_type (const char * str
, size_t len
)
22229 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22230 return SHT_ARM_EXIDX
;
22235 /* Code to deal with unwinding tables. */
22237 static void add_unwind_adjustsp (offsetT
);
22239 /* Generate any deferred unwind frame offset. */
22242 flush_pending_unwind (void)
22246 offset
= unwind
.pending_offset
;
22247 unwind
.pending_offset
= 0;
22249 add_unwind_adjustsp (offset
);
22252 /* Add an opcode to this list for this function. Two-byte opcodes should
22253 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22257 add_unwind_opcode (valueT op
, int length
)
22259 /* Add any deferred stack adjustment. */
22260 if (unwind
.pending_offset
)
22261 flush_pending_unwind ();
22263 unwind
.sp_restored
= 0;
22265 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22267 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22268 if (unwind
.opcodes
)
22269 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22270 unwind
.opcode_alloc
);
22272 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22277 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22279 unwind
.opcode_count
++;
22283 /* Add unwind opcodes to adjust the stack pointer. */
22286 add_unwind_adjustsp (offsetT offset
)
22290 if (offset
> 0x200)
22292 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22297 /* Long form: 0xb2, uleb128. */
22298 /* This might not fit in a word so add the individual bytes,
22299 remembering the list is built in reverse order. */
22300 o
= (valueT
) ((offset
- 0x204) >> 2);
22302 add_unwind_opcode (0, 1);
22304 /* Calculate the uleb128 encoding of the offset. */
22308 bytes
[n
] = o
& 0x7f;
22314 /* Add the insn. */
22316 add_unwind_opcode (bytes
[n
- 1], 1);
22317 add_unwind_opcode (0xb2, 1);
22319 else if (offset
> 0x100)
22321 /* Two short opcodes. */
22322 add_unwind_opcode (0x3f, 1);
22323 op
= (offset
- 0x104) >> 2;
22324 add_unwind_opcode (op
, 1);
22326 else if (offset
> 0)
22328 /* Short opcode. */
22329 op
= (offset
- 4) >> 2;
22330 add_unwind_opcode (op
, 1);
22332 else if (offset
< 0)
22335 while (offset
> 0x100)
22337 add_unwind_opcode (0x7f, 1);
22340 op
= ((offset
- 4) >> 2) | 0x40;
22341 add_unwind_opcode (op
, 1);
22345 /* Finish the list of unwind opcodes for this function. */
22348 finish_unwind_opcodes (void)
22352 if (unwind
.fp_used
)
22354 /* Adjust sp as necessary. */
22355 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22356 flush_pending_unwind ();
22358 /* After restoring sp from the frame pointer. */
22359 op
= 0x90 | unwind
.fp_reg
;
22360 add_unwind_opcode (op
, 1);
22363 flush_pending_unwind ();
22367 /* Start an exception table entry. If idx is nonzero this is an index table
22371 start_unwind_section (const segT text_seg
, int idx
)
22373 const char * text_name
;
22374 const char * prefix
;
22375 const char * prefix_once
;
22376 const char * group_name
;
22384 prefix
= ELF_STRING_ARM_unwind
;
22385 prefix_once
= ELF_STRING_ARM_unwind_once
;
22386 type
= SHT_ARM_EXIDX
;
22390 prefix
= ELF_STRING_ARM_unwind_info
;
22391 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22392 type
= SHT_PROGBITS
;
22395 text_name
= segment_name (text_seg
);
22396 if (streq (text_name
, ".text"))
22399 if (strncmp (text_name
, ".gnu.linkonce.t.",
22400 strlen (".gnu.linkonce.t.")) == 0)
22402 prefix
= prefix_once
;
22403 text_name
+= strlen (".gnu.linkonce.t.");
22406 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22412 /* Handle COMDAT group. */
22413 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22415 group_name
= elf_group_name (text_seg
);
22416 if (group_name
== NULL
)
22418 as_bad (_("Group section `%s' has no group signature"),
22419 segment_name (text_seg
));
22420 ignore_rest_of_line ();
22423 flags
|= SHF_GROUP
;
22427 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22430 /* Set the section link for index tables. */
22432 elf_linked_to_section (now_seg
) = text_seg
;
22436 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22437 personality routine data. Returns zero, or the index table value for
22438 an inline entry. */
22441 create_unwind_entry (int have_data
)
22446 /* The current word of data. */
22448 /* The number of bytes left in this word. */
22451 finish_unwind_opcodes ();
22453 /* Remember the current text section. */
22454 unwind
.saved_seg
= now_seg
;
22455 unwind
.saved_subseg
= now_subseg
;
22457 start_unwind_section (now_seg
, 0);
22459 if (unwind
.personality_routine
== NULL
)
22461 if (unwind
.personality_index
== -2)
22464 as_bad (_("handlerdata in cantunwind frame"));
22465 return 1; /* EXIDX_CANTUNWIND. */
22468 /* Use a default personality routine if none is specified. */
22469 if (unwind
.personality_index
== -1)
22471 if (unwind
.opcode_count
> 3)
22472 unwind
.personality_index
= 1;
22474 unwind
.personality_index
= 0;
22477 /* Space for the personality routine entry. */
22478 if (unwind
.personality_index
== 0)
22480 if (unwind
.opcode_count
> 3)
22481 as_bad (_("too many unwind opcodes for personality routine 0"));
22485 /* All the data is inline in the index table. */
22488 while (unwind
.opcode_count
> 0)
22490 unwind
.opcode_count
--;
22491 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22495 /* Pad with "finish" opcodes. */
22497 data
= (data
<< 8) | 0xb0;
22504 /* We get two opcodes "free" in the first word. */
22505 size
= unwind
.opcode_count
- 2;
22509 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22510 if (unwind
.personality_index
!= -1)
22512 as_bad (_("attempt to recreate an unwind entry"));
22516 /* An extra byte is required for the opcode count. */
22517 size
= unwind
.opcode_count
+ 1;
22520 size
= (size
+ 3) >> 2;
22522 as_bad (_("too many unwind opcodes"));
22524 frag_align (2, 0, 0);
22525 record_alignment (now_seg
, 2);
22526 unwind
.table_entry
= expr_build_dot ();
22528 /* Allocate the table entry. */
22529 ptr
= frag_more ((size
<< 2) + 4);
22530 /* PR 13449: Zero the table entries in case some of them are not used. */
22531 memset (ptr
, 0, (size
<< 2) + 4);
22532 where
= frag_now_fix () - ((size
<< 2) + 4);
22534 switch (unwind
.personality_index
)
22537 /* ??? Should this be a PLT generating relocation? */
22538 /* Custom personality routine. */
22539 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22540 BFD_RELOC_ARM_PREL31
);
22545 /* Set the first byte to the number of additional words. */
22546 data
= size
> 0 ? size
- 1 : 0;
22550 /* ABI defined personality routines. */
22552 /* Three opcodes bytes are packed into the first word. */
22559 /* The size and first two opcode bytes go in the first word. */
22560 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22565 /* Should never happen. */
22569 /* Pack the opcodes into words (MSB first), reversing the list at the same
22571 while (unwind
.opcode_count
> 0)
22575 md_number_to_chars (ptr
, data
, 4);
22580 unwind
.opcode_count
--;
22582 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22585 /* Finish off the last word. */
22588 /* Pad with "finish" opcodes. */
22590 data
= (data
<< 8) | 0xb0;
22592 md_number_to_chars (ptr
, data
, 4);
22597 /* Add an empty descriptor if there is no user-specified data. */
22598 ptr
= frag_more (4);
22599 md_number_to_chars (ptr
, 0, 4);
22606 /* Initialize the DWARF-2 unwind information for this procedure. */
22609 tc_arm_frame_initial_instructions (void)
22611 cfi_add_CFA_def_cfa (REG_SP
, 0);
22613 #endif /* OBJ_ELF */
22615 /* Convert REGNAME to a DWARF-2 register number. */
22618 tc_arm_regname_to_dw2regnum (char *regname
)
22620 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22624 /* PR 16694: Allow VFP registers as well. */
22625 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22629 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22638 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22642 exp
.X_op
= O_secrel
;
22643 exp
.X_add_symbol
= symbol
;
22644 exp
.X_add_number
= 0;
22645 emit_expr (&exp
, size
);
22649 /* MD interface: Symbol and relocation handling. */
22651 /* Return the address within the segment that a PC-relative fixup is
22652 relative to. For ARM, PC-relative fixups applied to instructions
22653 are generally relative to the location of the fixup plus 8 bytes.
22654 Thumb branches are offset by 4, and Thumb loads relative to PC
22655 require special handling. */
22658 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22660 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22662 /* If this is pc-relative and we are going to emit a relocation
22663 then we just want to put out any pipeline compensation that the linker
22664 will need. Otherwise we want to use the calculated base.
22665 For WinCE we skip the bias for externals as well, since this
22666 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22668 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22669 || (arm_force_relocation (fixP
)
22671 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22677 switch (fixP
->fx_r_type
)
22679 /* PC relative addressing on the Thumb is slightly odd as the
22680 bottom two bits of the PC are forced to zero for the
22681 calculation. This happens *after* application of the
22682 pipeline offset. However, Thumb adrl already adjusts for
22683 this, so we need not do it again. */
22684 case BFD_RELOC_ARM_THUMB_ADD
:
22687 case BFD_RELOC_ARM_THUMB_OFFSET
:
22688 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22689 case BFD_RELOC_ARM_T32_ADD_PC12
:
22690 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22691 return (base
+ 4) & ~3;
22693 /* Thumb branches are simply offset by +4. */
22694 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22695 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22696 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22697 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22698 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22701 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22703 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22704 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22705 && ARM_IS_FUNC (fixP
->fx_addsy
)
22706 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22707 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22710 /* BLX is like branches above, but forces the low two bits of PC to
22712 case BFD_RELOC_THUMB_PCREL_BLX
:
22714 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22715 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22716 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22717 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22718 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22719 return (base
+ 4) & ~3;
22721 /* ARM mode branches are offset by +8. However, the Windows CE
22722 loader expects the relocation not to take this into account. */
22723 case BFD_RELOC_ARM_PCREL_BLX
:
22725 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22726 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22727 && ARM_IS_FUNC (fixP
->fx_addsy
)
22728 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22729 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22732 case BFD_RELOC_ARM_PCREL_CALL
:
22734 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22735 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22736 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22737 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22738 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22741 case BFD_RELOC_ARM_PCREL_BRANCH
:
22742 case BFD_RELOC_ARM_PCREL_JUMP
:
22743 case BFD_RELOC_ARM_PLT32
:
22745 /* When handling fixups immediately, because we have already
22746 discovered the value of a symbol, or the address of the frag involved
22747 we must account for the offset by +8, as the OS loader will never see the reloc.
22748 see fixup_segment() in write.c
22749 The S_IS_EXTERNAL test handles the case of global symbols.
22750 Those need the calculated base, not just the pipe compensation the linker will need. */
22752 && fixP
->fx_addsy
!= NULL
22753 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22754 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22762 /* ARM mode loads relative to PC are also offset by +8. Unlike
22763 branches, the Windows CE loader *does* expect the relocation
22764 to take this into account. */
22765 case BFD_RELOC_ARM_OFFSET_IMM
:
22766 case BFD_RELOC_ARM_OFFSET_IMM8
:
22767 case BFD_RELOC_ARM_HWLITERAL
:
22768 case BFD_RELOC_ARM_LITERAL
:
22769 case BFD_RELOC_ARM_CP_OFF_IMM
:
22773 /* Other PC-relative relocations are un-offset. */
22779 static bfd_boolean flag_warn_syms
= TRUE
;
22782 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22784 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22785 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22786 does mean that the resulting code might be very confusing to the reader.
22787 Also this warning can be triggered if the user omits an operand before
22788 an immediate address, eg:
22792 GAS treats this as an assignment of the value of the symbol foo to a
22793 symbol LDR, and so (without this code) it will not issue any kind of
22794 warning or error message.
22796 Note - ARM instructions are case-insensitive but the strings in the hash
22797 table are all stored in lower case, so we must first ensure that name is
22799 if (flag_warn_syms
&& arm_ops_hsh
)
22801 char * nbuf
= strdup (name
);
22804 for (p
= nbuf
; *p
; p
++)
22806 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22808 static struct hash_control
* already_warned
= NULL
;
22810 if (already_warned
== NULL
)
22811 already_warned
= hash_new ();
22812 /* Only warn about the symbol once. To keep the code
22813 simple we let hash_insert do the lookup for us. */
22814 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22815 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22824 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22825 Otherwise we have no need to default values of symbols. */
22828 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22831 if (name
[0] == '_' && name
[1] == 'G'
22832 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22836 if (symbol_find (name
))
22837 as_bad (_("GOT already in the symbol table"));
22839 GOT_symbol
= symbol_new (name
, undefined_section
,
22840 (valueT
) 0, & zero_address_frag
);
22850 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22851 computed as two separate immediate values, added together. We
22852 already know that this value cannot be computed by just one ARM
22855 static unsigned int
22856 validate_immediate_twopart (unsigned int val
,
22857 unsigned int * highpart
)
22862 for (i
= 0; i
< 32; i
+= 2)
22863 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22869 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22871 else if (a
& 0xff0000)
22873 if (a
& 0xff000000)
22875 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22879 gas_assert (a
& 0xff000000);
22880 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22883 return (a
& 0xff) | (i
<< 7);
22890 validate_offset_imm (unsigned int val
, int hwse
)
22892 if ((hwse
&& val
> 255) || val
> 4095)
22897 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22898 negative immediate constant by altering the instruction. A bit of
22903 by inverting the second operand, and
22906 by negating the second operand. */
22909 negate_data_op (unsigned long * instruction
,
22910 unsigned long value
)
22913 unsigned long negated
, inverted
;
22915 negated
= encode_arm_immediate (-value
);
22916 inverted
= encode_arm_immediate (~value
);
22918 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22921 /* First negates. */
22922 case OPCODE_SUB
: /* ADD <-> SUB */
22923 new_inst
= OPCODE_ADD
;
22928 new_inst
= OPCODE_SUB
;
22932 case OPCODE_CMP
: /* CMP <-> CMN */
22933 new_inst
= OPCODE_CMN
;
22938 new_inst
= OPCODE_CMP
;
22942 /* Now Inverted ops. */
22943 case OPCODE_MOV
: /* MOV <-> MVN */
22944 new_inst
= OPCODE_MVN
;
22949 new_inst
= OPCODE_MOV
;
22953 case OPCODE_AND
: /* AND <-> BIC */
22954 new_inst
= OPCODE_BIC
;
22959 new_inst
= OPCODE_AND
;
22963 case OPCODE_ADC
: /* ADC <-> SBC */
22964 new_inst
= OPCODE_SBC
;
22969 new_inst
= OPCODE_ADC
;
22973 /* We cannot do anything. */
22978 if (value
== (unsigned) FAIL
)
22981 *instruction
&= OPCODE_MASK
;
22982 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22986 /* Like negate_data_op, but for Thumb-2. */
22988 static unsigned int
22989 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22993 unsigned int negated
, inverted
;
22995 negated
= encode_thumb32_immediate (-value
);
22996 inverted
= encode_thumb32_immediate (~value
);
22998 rd
= (*instruction
>> 8) & 0xf;
22999 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23002 /* ADD <-> SUB. Includes CMP <-> CMN. */
23003 case T2_OPCODE_SUB
:
23004 new_inst
= T2_OPCODE_ADD
;
23008 case T2_OPCODE_ADD
:
23009 new_inst
= T2_OPCODE_SUB
;
23013 /* ORR <-> ORN. Includes MOV <-> MVN. */
23014 case T2_OPCODE_ORR
:
23015 new_inst
= T2_OPCODE_ORN
;
23019 case T2_OPCODE_ORN
:
23020 new_inst
= T2_OPCODE_ORR
;
23024 /* AND <-> BIC. TST has no inverted equivalent. */
23025 case T2_OPCODE_AND
:
23026 new_inst
= T2_OPCODE_BIC
;
23033 case T2_OPCODE_BIC
:
23034 new_inst
= T2_OPCODE_AND
;
23039 case T2_OPCODE_ADC
:
23040 new_inst
= T2_OPCODE_SBC
;
23044 case T2_OPCODE_SBC
:
23045 new_inst
= T2_OPCODE_ADC
;
23049 /* We cannot do anything. */
23054 if (value
== (unsigned int)FAIL
)
23057 *instruction
&= T2_OPCODE_MASK
;
23058 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23062 /* Read a 32-bit thumb instruction from buf. */
23064 static unsigned long
23065 get_thumb32_insn (char * buf
)
23067 unsigned long insn
;
23068 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23069 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23074 /* We usually want to set the low bit on the address of thumb function
23075 symbols. In particular .word foo - . should have the low bit set.
23076 Generic code tries to fold the difference of two symbols to
23077 a constant. Prevent this and force a relocation when the first symbols
23078 is a thumb function. */
23081 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23083 if (op
== O_subtract
23084 && l
->X_op
== O_symbol
23085 && r
->X_op
== O_symbol
23086 && THUMB_IS_FUNC (l
->X_add_symbol
))
23088 l
->X_op
= O_subtract
;
23089 l
->X_op_symbol
= r
->X_add_symbol
;
23090 l
->X_add_number
-= r
->X_add_number
;
23094 /* Process as normal. */
23098 /* Encode Thumb2 unconditional branches and calls. The encoding
23099 for the 2 are identical for the immediate values. */
23102 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23104 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23107 addressT S
, I1
, I2
, lo
, hi
;
23109 S
= (value
>> 24) & 0x01;
23110 I1
= (value
>> 23) & 0x01;
23111 I2
= (value
>> 22) & 0x01;
23112 hi
= (value
>> 12) & 0x3ff;
23113 lo
= (value
>> 1) & 0x7ff;
23114 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23115 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23116 newval
|= (S
<< 10) | hi
;
23117 newval2
&= ~T2I1I2MASK
;
23118 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23119 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23120 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23124 md_apply_fix (fixS
* fixP
,
23128 offsetT value
= * valP
;
23130 unsigned int newimm
;
23131 unsigned long temp
;
23133 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23135 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23137 /* Note whether this will delete the relocation. */
23139 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23142 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23143 consistency with the behaviour on 32-bit hosts. Remember value
23145 value
&= 0xffffffff;
23146 value
^= 0x80000000;
23147 value
-= 0x80000000;
23150 fixP
->fx_addnumber
= value
;
23152 /* Same treatment for fixP->fx_offset. */
23153 fixP
->fx_offset
&= 0xffffffff;
23154 fixP
->fx_offset
^= 0x80000000;
23155 fixP
->fx_offset
-= 0x80000000;
23157 switch (fixP
->fx_r_type
)
23159 case BFD_RELOC_NONE
:
23160 /* This will need to go in the object file. */
23164 case BFD_RELOC_ARM_IMMEDIATE
:
23165 /* We claim that this fixup has been processed here,
23166 even if in fact we generate an error because we do
23167 not have a reloc for it, so tc_gen_reloc will reject it. */
23170 if (fixP
->fx_addsy
)
23172 const char *msg
= 0;
23174 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23175 msg
= _("undefined symbol %s used as an immediate value");
23176 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23177 msg
= _("symbol %s is in a different section");
23178 else if (S_IS_WEAK (fixP
->fx_addsy
))
23179 msg
= _("symbol %s is weak and may be overridden later");
23183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23184 msg
, S_GET_NAME (fixP
->fx_addsy
));
23189 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23191 /* If the offset is negative, we should use encoding A2 for ADR. */
23192 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23193 newimm
= negate_data_op (&temp
, value
);
23196 newimm
= encode_arm_immediate (value
);
23198 /* If the instruction will fail, see if we can fix things up by
23199 changing the opcode. */
23200 if (newimm
== (unsigned int) FAIL
)
23201 newimm
= negate_data_op (&temp
, value
);
23202 /* MOV accepts both ARM modified immediate (A1 encoding) and
23203 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23204 When disassembling, MOV is preferred when there is no encoding
23206 if (newimm
== (unsigned int) FAIL
23207 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23208 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23209 && !((temp
>> SBIT_SHIFT
) & 0x1)
23210 && value
>= 0 && value
<= 0xffff)
23212 /* Clear bits[23:20] to change encoding from A1 to A2. */
23213 temp
&= 0xff0fffff;
23214 /* Encoding high 4bits imm. Code below will encode the remaining
23216 temp
|= (value
& 0x0000f000) << 4;
23217 newimm
= value
& 0x00000fff;
23221 if (newimm
== (unsigned int) FAIL
)
23223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23224 _("invalid constant (%lx) after fixup"),
23225 (unsigned long) value
);
23229 newimm
|= (temp
& 0xfffff000);
23230 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23233 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23235 unsigned int highpart
= 0;
23236 unsigned int newinsn
= 0xe1a00000; /* nop. */
23238 if (fixP
->fx_addsy
)
23240 const char *msg
= 0;
23242 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23243 msg
= _("undefined symbol %s used as an immediate value");
23244 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23245 msg
= _("symbol %s is in a different section");
23246 else if (S_IS_WEAK (fixP
->fx_addsy
))
23247 msg
= _("symbol %s is weak and may be overridden later");
23251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23252 msg
, S_GET_NAME (fixP
->fx_addsy
));
23257 newimm
= encode_arm_immediate (value
);
23258 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23260 /* If the instruction will fail, see if we can fix things up by
23261 changing the opcode. */
23262 if (newimm
== (unsigned int) FAIL
23263 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23265 /* No ? OK - try using two ADD instructions to generate
23267 newimm
= validate_immediate_twopart (value
, & highpart
);
23269 /* Yes - then make sure that the second instruction is
23271 if (newimm
!= (unsigned int) FAIL
)
23273 /* Still No ? Try using a negated value. */
23274 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23275 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23276 /* Otherwise - give up. */
23279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23280 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23285 /* Replace the first operand in the 2nd instruction (which
23286 is the PC) with the destination register. We have
23287 already added in the PC in the first instruction and we
23288 do not want to do it again. */
23289 newinsn
&= ~ 0xf0000;
23290 newinsn
|= ((newinsn
& 0x0f000) << 4);
23293 newimm
|= (temp
& 0xfffff000);
23294 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23296 highpart
|= (newinsn
& 0xfffff000);
23297 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23301 case BFD_RELOC_ARM_OFFSET_IMM
:
23302 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23304 /* Fall through. */
23306 case BFD_RELOC_ARM_LITERAL
:
23312 if (validate_offset_imm (value
, 0) == FAIL
)
23314 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23316 _("invalid literal constant: pool needs to be closer"));
23318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23319 _("bad immediate value for offset (%ld)"),
23324 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23326 newval
&= 0xfffff000;
23329 newval
&= 0xff7ff000;
23330 newval
|= value
| (sign
? INDEX_UP
: 0);
23332 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23335 case BFD_RELOC_ARM_OFFSET_IMM8
:
23336 case BFD_RELOC_ARM_HWLITERAL
:
23342 if (validate_offset_imm (value
, 1) == FAIL
)
23344 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23346 _("invalid literal constant: pool needs to be closer"));
23348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23349 _("bad immediate value for 8-bit offset (%ld)"),
23354 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23356 newval
&= 0xfffff0f0;
23359 newval
&= 0xff7ff0f0;
23360 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23362 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23365 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23366 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23368 _("bad immediate value for offset (%ld)"), (long) value
);
23371 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23373 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23376 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23377 /* This is a complicated relocation used for all varieties of Thumb32
23378 load/store instruction with immediate offset:
23380 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23381 *4, optional writeback(W)
23382 (doubleword load/store)
23384 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23385 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23386 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23387 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23388 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23390 Uppercase letters indicate bits that are already encoded at
23391 this point. Lowercase letters are our problem. For the
23392 second block of instructions, the secondary opcode nybble
23393 (bits 8..11) is present, and bit 23 is zero, even if this is
23394 a PC-relative operation. */
23395 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23397 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23399 if ((newval
& 0xf0000000) == 0xe0000000)
23401 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23403 newval
|= (1 << 23);
23406 if (value
% 4 != 0)
23408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23409 _("offset not a multiple of 4"));
23415 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23416 _("offset out of range"));
23421 else if ((newval
& 0x000f0000) == 0x000f0000)
23423 /* PC-relative, 12-bit offset. */
23425 newval
|= (1 << 23);
23430 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23431 _("offset out of range"));
23436 else if ((newval
& 0x00000100) == 0x00000100)
23438 /* Writeback: 8-bit, +/- offset. */
23440 newval
|= (1 << 9);
23445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23446 _("offset out of range"));
23451 else if ((newval
& 0x00000f00) == 0x00000e00)
23453 /* T-instruction: positive 8-bit offset. */
23454 if (value
< 0 || value
> 0xff)
23456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23457 _("offset out of range"));
23465 /* Positive 12-bit or negative 8-bit offset. */
23469 newval
|= (1 << 23);
23479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23480 _("offset out of range"));
23487 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23488 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23491 case BFD_RELOC_ARM_SHIFT_IMM
:
23492 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23493 if (((unsigned long) value
) > 32
23495 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23498 _("shift expression is too large"));
23503 /* Shifts of zero must be done as lsl. */
23505 else if (value
== 32)
23507 newval
&= 0xfffff07f;
23508 newval
|= (value
& 0x1f) << 7;
23509 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23512 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23513 case BFD_RELOC_ARM_T32_ADD_IMM
:
23514 case BFD_RELOC_ARM_T32_IMM12
:
23515 case BFD_RELOC_ARM_T32_ADD_PC12
:
23516 /* We claim that this fixup has been processed here,
23517 even if in fact we generate an error because we do
23518 not have a reloc for it, so tc_gen_reloc will reject it. */
23522 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23525 _("undefined symbol %s used as an immediate value"),
23526 S_GET_NAME (fixP
->fx_addsy
));
23530 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23532 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23535 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23536 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23537 Thumb2 modified immediate encoding (T2). */
23538 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23539 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23541 newimm
= encode_thumb32_immediate (value
);
23542 if (newimm
== (unsigned int) FAIL
)
23543 newimm
= thumb32_negate_data_op (&newval
, value
);
23545 if (newimm
== (unsigned int) FAIL
)
23547 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23549 /* Turn add/sum into addw/subw. */
23550 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23551 newval
= (newval
& 0xfeffffff) | 0x02000000;
23552 /* No flat 12-bit imm encoding for addsw/subsw. */
23553 if ((newval
& 0x00100000) == 0)
23555 /* 12 bit immediate for addw/subw. */
23559 newval
^= 0x00a00000;
23562 newimm
= (unsigned int) FAIL
;
23569 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23570 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23571 disassembling, MOV is preferred when there is no encoding
23573 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23574 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23575 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23576 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23577 && value
>= 0 && value
<=0xffff)
23579 /* Toggle bit[25] to change encoding from T2 to T3. */
23581 /* Clear bits[19:16]. */
23582 newval
&= 0xfff0ffff;
23583 /* Encoding high 4bits imm. Code below will encode the
23584 remaining low 12bits. */
23585 newval
|= (value
& 0x0000f000) << 4;
23586 newimm
= value
& 0x00000fff;
23591 if (newimm
== (unsigned int)FAIL
)
23593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23594 _("invalid constant (%lx) after fixup"),
23595 (unsigned long) value
);
23599 newval
|= (newimm
& 0x800) << 15;
23600 newval
|= (newimm
& 0x700) << 4;
23601 newval
|= (newimm
& 0x0ff);
23603 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23604 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23607 case BFD_RELOC_ARM_SMC
:
23608 if (((unsigned long) value
) > 0xffff)
23609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23610 _("invalid smc expression"));
23611 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23612 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23613 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23616 case BFD_RELOC_ARM_HVC
:
23617 if (((unsigned long) value
) > 0xffff)
23618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23619 _("invalid hvc expression"));
23620 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23621 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23622 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23625 case BFD_RELOC_ARM_SWI
:
23626 if (fixP
->tc_fix_data
!= 0)
23628 if (((unsigned long) value
) > 0xff)
23629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23630 _("invalid swi expression"));
23631 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23633 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23637 if (((unsigned long) value
) > 0x00ffffff)
23638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23639 _("invalid swi expression"));
23640 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23642 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23646 case BFD_RELOC_ARM_MULTI
:
23647 if (((unsigned long) value
) > 0xffff)
23648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23649 _("invalid expression in load/store multiple"));
23650 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23651 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23655 case BFD_RELOC_ARM_PCREL_CALL
:
23657 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23659 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23660 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23661 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23662 /* Flip the bl to blx. This is a simple flip
23663 bit here because we generate PCREL_CALL for
23664 unconditional bls. */
23666 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23667 newval
= newval
| 0x10000000;
23668 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23674 goto arm_branch_common
;
23676 case BFD_RELOC_ARM_PCREL_JUMP
:
23677 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23679 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23680 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23681 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23683 /* This would map to a bl<cond>, b<cond>,
23684 b<always> to a Thumb function. We
23685 need to force a relocation for this particular
23687 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23690 /* Fall through. */
23692 case BFD_RELOC_ARM_PLT32
:
23694 case BFD_RELOC_ARM_PCREL_BRANCH
:
23696 goto arm_branch_common
;
23698 case BFD_RELOC_ARM_PCREL_BLX
:
23701 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23703 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23704 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23705 && ARM_IS_FUNC (fixP
->fx_addsy
))
23707 /* Flip the blx to a bl and warn. */
23708 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23709 newval
= 0xeb000000;
23710 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23711 _("blx to '%s' an ARM ISA state function changed to bl"),
23713 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23719 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23720 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23724 /* We are going to store value (shifted right by two) in the
23725 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23726 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23730 _("misaligned branch destination"));
23731 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23732 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23735 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23737 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23738 newval
|= (value
>> 2) & 0x00ffffff;
23739 /* Set the H bit on BLX instructions. */
23743 newval
|= 0x01000000;
23745 newval
&= ~0x01000000;
23747 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23751 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23752 /* CBZ can only branch forward. */
23754 /* Attempts to use CBZ to branch to the next instruction
23755 (which, strictly speaking, are prohibited) will be turned into
23758 FIXME: It may be better to remove the instruction completely and
23759 perform relaxation. */
23762 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23763 newval
= 0xbf00; /* NOP encoding T1 */
23764 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23771 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23773 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23774 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23775 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23780 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23781 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23784 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23786 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23787 newval
|= (value
& 0x1ff) >> 1;
23788 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23792 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23793 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23796 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23798 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23799 newval
|= (value
& 0xfff) >> 1;
23800 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23804 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23807 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23808 && ARM_IS_FUNC (fixP
->fx_addsy
)
23809 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23811 /* Force a relocation for a branch 20 bits wide. */
23814 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23816 _("conditional branch out of range"));
23818 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23821 addressT S
, J1
, J2
, lo
, hi
;
23823 S
= (value
& 0x00100000) >> 20;
23824 J2
= (value
& 0x00080000) >> 19;
23825 J1
= (value
& 0x00040000) >> 18;
23826 hi
= (value
& 0x0003f000) >> 12;
23827 lo
= (value
& 0x00000ffe) >> 1;
23829 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23830 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23831 newval
|= (S
<< 10) | hi
;
23832 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23834 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23838 case BFD_RELOC_THUMB_PCREL_BLX
:
23839 /* If there is a blx from a thumb state function to
23840 another thumb function flip this to a bl and warn
23844 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23845 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23846 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23848 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23849 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23850 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23852 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23853 newval
= newval
| 0x1000;
23854 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23855 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23860 goto thumb_bl_common
;
23862 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23863 /* A bl from Thumb state ISA to an internal ARM state function
23864 is converted to a blx. */
23866 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23867 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23868 && ARM_IS_FUNC (fixP
->fx_addsy
)
23869 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23871 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23872 newval
= newval
& ~0x1000;
23873 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23874 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23880 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23881 /* For a BLX instruction, make sure that the relocation is rounded up
23882 to a word boundary. This follows the semantics of the instruction
23883 which specifies that bit 1 of the target address will come from bit
23884 1 of the base address. */
23885 value
= (value
+ 3) & ~ 3;
23888 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23889 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23890 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23893 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23895 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23897 else if ((value
& ~0x1ffffff)
23898 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23900 _("Thumb2 branch out of range"));
23903 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23904 encode_thumb2_b_bl_offset (buf
, value
);
23908 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23909 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23912 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23913 encode_thumb2_b_bl_offset (buf
, value
);
23918 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23923 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23924 md_number_to_chars (buf
, value
, 2);
23928 case BFD_RELOC_ARM_TLS_CALL
:
23929 case BFD_RELOC_ARM_THM_TLS_CALL
:
23930 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23931 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23932 case BFD_RELOC_ARM_TLS_GOTDESC
:
23933 case BFD_RELOC_ARM_TLS_GD32
:
23934 case BFD_RELOC_ARM_TLS_LE32
:
23935 case BFD_RELOC_ARM_TLS_IE32
:
23936 case BFD_RELOC_ARM_TLS_LDM32
:
23937 case BFD_RELOC_ARM_TLS_LDO32
:
23938 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23941 case BFD_RELOC_ARM_GOT32
:
23942 case BFD_RELOC_ARM_GOTOFF
:
23945 case BFD_RELOC_ARM_GOT_PREL
:
23946 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23947 md_number_to_chars (buf
, value
, 4);
23950 case BFD_RELOC_ARM_TARGET2
:
23951 /* TARGET2 is not partial-inplace, so we need to write the
23952 addend here for REL targets, because it won't be written out
23953 during reloc processing later. */
23954 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23955 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23959 case BFD_RELOC_RVA
:
23961 case BFD_RELOC_ARM_TARGET1
:
23962 case BFD_RELOC_ARM_ROSEGREL32
:
23963 case BFD_RELOC_ARM_SBREL32
:
23964 case BFD_RELOC_32_PCREL
:
23966 case BFD_RELOC_32_SECREL
:
23968 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23970 /* For WinCE we only do this for pcrel fixups. */
23971 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23973 md_number_to_chars (buf
, value
, 4);
23977 case BFD_RELOC_ARM_PREL31
:
23978 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23980 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23981 if ((value
^ (value
>> 1)) & 0x40000000)
23983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23984 _("rel31 relocation overflow"));
23986 newval
|= value
& 0x7fffffff;
23987 md_number_to_chars (buf
, newval
, 4);
23992 case BFD_RELOC_ARM_CP_OFF_IMM
:
23993 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23994 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23995 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23997 newval
= get_thumb32_insn (buf
);
23998 if ((newval
& 0x0f200f00) == 0x0d000900)
24000 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24001 has permitted values that are multiples of 2, in the range 0
24003 if (value
< -510 || value
> 510 || (value
& 1))
24004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24005 _("co-processor offset out of range"));
24007 else if (value
< -1023 || value
> 1023 || (value
& 3))
24008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24009 _("co-processor offset out of range"));
24014 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24015 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24016 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24018 newval
= get_thumb32_insn (buf
);
24020 newval
&= 0xffffff00;
24023 newval
&= 0xff7fff00;
24024 if ((newval
& 0x0f200f00) == 0x0d000900)
24026 /* This is a fp16 vstr/vldr.
24028 It requires the immediate offset in the instruction is shifted
24029 left by 1 to be a half-word offset.
24031 Here, left shift by 1 first, and later right shift by 2
24032 should get the right offset. */
24035 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24037 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24038 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24039 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24041 put_thumb32_insn (buf
, newval
);
24044 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24045 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24046 if (value
< -255 || value
> 255)
24047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24048 _("co-processor offset out of range"));
24050 goto cp_off_common
;
24052 case BFD_RELOC_ARM_THUMB_OFFSET
:
24053 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24054 /* Exactly what ranges, and where the offset is inserted depends
24055 on the type of instruction, we can establish this from the
24057 switch (newval
>> 12)
24059 case 4: /* PC load. */
24060 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24061 forced to zero for these loads; md_pcrel_from has already
24062 compensated for this. */
24064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24065 _("invalid offset, target not word aligned (0x%08lX)"),
24066 (((unsigned long) fixP
->fx_frag
->fr_address
24067 + (unsigned long) fixP
->fx_where
) & ~3)
24068 + (unsigned long) value
);
24070 if (value
& ~0x3fc)
24071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24072 _("invalid offset, value too big (0x%08lX)"),
24075 newval
|= value
>> 2;
24078 case 9: /* SP load/store. */
24079 if (value
& ~0x3fc)
24080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24081 _("invalid offset, value too big (0x%08lX)"),
24083 newval
|= value
>> 2;
24086 case 6: /* Word load/store. */
24088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24089 _("invalid offset, value too big (0x%08lX)"),
24091 newval
|= value
<< 4; /* 6 - 2. */
24094 case 7: /* Byte load/store. */
24096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24097 _("invalid offset, value too big (0x%08lX)"),
24099 newval
|= value
<< 6;
24102 case 8: /* Halfword load/store. */
24104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24105 _("invalid offset, value too big (0x%08lX)"),
24107 newval
|= value
<< 5; /* 6 - 1. */
24111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24112 "Unable to process relocation for thumb opcode: %lx",
24113 (unsigned long) newval
);
24116 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24119 case BFD_RELOC_ARM_THUMB_ADD
:
24120 /* This is a complicated relocation, since we use it for all of
24121 the following immediate relocations:
24125 9bit ADD/SUB SP word-aligned
24126 10bit ADD PC/SP word-aligned
24128 The type of instruction being processed is encoded in the
24135 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24137 int rd
= (newval
>> 4) & 0xf;
24138 int rs
= newval
& 0xf;
24139 int subtract
= !!(newval
& 0x8000);
24141 /* Check for HI regs, only very restricted cases allowed:
24142 Adjusting SP, and using PC or SP to get an address. */
24143 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24144 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24146 _("invalid Hi register with immediate"));
24148 /* If value is negative, choose the opposite instruction. */
24152 subtract
= !subtract
;
24154 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24155 _("immediate value out of range"));
24160 if (value
& ~0x1fc)
24161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24162 _("invalid immediate for stack address calculation"));
24163 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24164 newval
|= value
>> 2;
24166 else if (rs
== REG_PC
|| rs
== REG_SP
)
24168 /* PR gas/18541. If the addition is for a defined symbol
24169 within range of an ADR instruction then accept it. */
24172 && fixP
->fx_addsy
!= NULL
)
24176 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24177 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24178 || S_IS_WEAK (fixP
->fx_addsy
))
24180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24181 _("address calculation needs a strongly defined nearby symbol"));
24185 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24187 /* Round up to the next 4-byte boundary. */
24192 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24197 _("symbol too far away"));
24207 if (subtract
|| value
& ~0x3fc)
24208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24209 _("invalid immediate for address calculation (value = 0x%08lX)"),
24210 (unsigned long) (subtract
? - value
: value
));
24211 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24213 newval
|= value
>> 2;
24218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24219 _("immediate value out of range"));
24220 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24221 newval
|= (rd
<< 8) | value
;
24226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24227 _("immediate value out of range"));
24228 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24229 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24232 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24235 case BFD_RELOC_ARM_THUMB_IMM
:
24236 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24237 if (value
< 0 || value
> 255)
24238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24239 _("invalid immediate: %ld is out of range"),
24242 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24245 case BFD_RELOC_ARM_THUMB_SHIFT
:
24246 /* 5bit shift value (0..32). LSL cannot take 32. */
24247 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24248 temp
= newval
& 0xf800;
24249 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24251 _("invalid shift value: %ld"), (long) value
);
24252 /* Shifts of zero must be encoded as LSL. */
24254 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24255 /* Shifts of 32 are encoded as zero. */
24256 else if (value
== 32)
24258 newval
|= value
<< 6;
24259 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24262 case BFD_RELOC_VTABLE_INHERIT
:
24263 case BFD_RELOC_VTABLE_ENTRY
:
24267 case BFD_RELOC_ARM_MOVW
:
24268 case BFD_RELOC_ARM_MOVT
:
24269 case BFD_RELOC_ARM_THUMB_MOVW
:
24270 case BFD_RELOC_ARM_THUMB_MOVT
:
24271 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24273 /* REL format relocations are limited to a 16-bit addend. */
24274 if (!fixP
->fx_done
)
24276 if (value
< -0x8000 || value
> 0x7fff)
24277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24278 _("offset out of range"));
24280 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24281 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24286 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24287 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24289 newval
= get_thumb32_insn (buf
);
24290 newval
&= 0xfbf08f00;
24291 newval
|= (value
& 0xf000) << 4;
24292 newval
|= (value
& 0x0800) << 15;
24293 newval
|= (value
& 0x0700) << 4;
24294 newval
|= (value
& 0x00ff);
24295 put_thumb32_insn (buf
, newval
);
24299 newval
= md_chars_to_number (buf
, 4);
24300 newval
&= 0xfff0f000;
24301 newval
|= value
& 0x0fff;
24302 newval
|= (value
& 0xf000) << 4;
24303 md_number_to_chars (buf
, newval
, 4);
24308 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24309 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24310 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24311 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24312 gas_assert (!fixP
->fx_done
);
24315 bfd_boolean is_mov
;
24316 bfd_vma encoded_addend
= value
;
24318 /* Check that addend can be encoded in instruction. */
24319 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24321 _("the offset 0x%08lX is not representable"),
24322 (unsigned long) encoded_addend
);
24324 /* Extract the instruction. */
24325 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24326 is_mov
= (insn
& 0xf800) == 0x2000;
24331 if (!seg
->use_rela_p
)
24332 insn
|= encoded_addend
;
24338 /* Extract the instruction. */
24339 /* Encoding is the following
24344 /* The following conditions must be true :
24349 rd
= (insn
>> 4) & 0xf;
24351 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24353 _("Unable to process relocation for thumb opcode: %lx"),
24354 (unsigned long) insn
);
24356 /* Encode as ADD immediate8 thumb 1 code. */
24357 insn
= 0x3000 | (rd
<< 8);
24359 /* Place the encoded addend into the first 8 bits of the
24361 if (!seg
->use_rela_p
)
24362 insn
|= encoded_addend
;
24365 /* Update the instruction. */
24366 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24370 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24371 case BFD_RELOC_ARM_ALU_PC_G0
:
24372 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24373 case BFD_RELOC_ARM_ALU_PC_G1
:
24374 case BFD_RELOC_ARM_ALU_PC_G2
:
24375 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24376 case BFD_RELOC_ARM_ALU_SB_G0
:
24377 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24378 case BFD_RELOC_ARM_ALU_SB_G1
:
24379 case BFD_RELOC_ARM_ALU_SB_G2
:
24380 gas_assert (!fixP
->fx_done
);
24381 if (!seg
->use_rela_p
)
24384 bfd_vma encoded_addend
;
24385 bfd_vma addend_abs
= abs (value
);
24387 /* Check that the absolute value of the addend can be
24388 expressed as an 8-bit constant plus a rotation. */
24389 encoded_addend
= encode_arm_immediate (addend_abs
);
24390 if (encoded_addend
== (unsigned int) FAIL
)
24391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24392 _("the offset 0x%08lX is not representable"),
24393 (unsigned long) addend_abs
);
24395 /* Extract the instruction. */
24396 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24398 /* If the addend is positive, use an ADD instruction.
24399 Otherwise use a SUB. Take care not to destroy the S bit. */
24400 insn
&= 0xff1fffff;
24406 /* Place the encoded addend into the first 12 bits of the
24408 insn
&= 0xfffff000;
24409 insn
|= encoded_addend
;
24411 /* Update the instruction. */
24412 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24416 case BFD_RELOC_ARM_LDR_PC_G0
:
24417 case BFD_RELOC_ARM_LDR_PC_G1
:
24418 case BFD_RELOC_ARM_LDR_PC_G2
:
24419 case BFD_RELOC_ARM_LDR_SB_G0
:
24420 case BFD_RELOC_ARM_LDR_SB_G1
:
24421 case BFD_RELOC_ARM_LDR_SB_G2
:
24422 gas_assert (!fixP
->fx_done
);
24423 if (!seg
->use_rela_p
)
24426 bfd_vma addend_abs
= abs (value
);
24428 /* Check that the absolute value of the addend can be
24429 encoded in 12 bits. */
24430 if (addend_abs
>= 0x1000)
24431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24432 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24433 (unsigned long) addend_abs
);
24435 /* Extract the instruction. */
24436 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24438 /* If the addend is negative, clear bit 23 of the instruction.
24439 Otherwise set it. */
24441 insn
&= ~(1 << 23);
24445 /* Place the absolute value of the addend into the first 12 bits
24446 of the instruction. */
24447 insn
&= 0xfffff000;
24448 insn
|= addend_abs
;
24450 /* Update the instruction. */
24451 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24455 case BFD_RELOC_ARM_LDRS_PC_G0
:
24456 case BFD_RELOC_ARM_LDRS_PC_G1
:
24457 case BFD_RELOC_ARM_LDRS_PC_G2
:
24458 case BFD_RELOC_ARM_LDRS_SB_G0
:
24459 case BFD_RELOC_ARM_LDRS_SB_G1
:
24460 case BFD_RELOC_ARM_LDRS_SB_G2
:
24461 gas_assert (!fixP
->fx_done
);
24462 if (!seg
->use_rela_p
)
24465 bfd_vma addend_abs
= abs (value
);
24467 /* Check that the absolute value of the addend can be
24468 encoded in 8 bits. */
24469 if (addend_abs
>= 0x100)
24470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24471 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24472 (unsigned long) addend_abs
);
24474 /* Extract the instruction. */
24475 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24477 /* If the addend is negative, clear bit 23 of the instruction.
24478 Otherwise set it. */
24480 insn
&= ~(1 << 23);
24484 /* Place the first four bits of the absolute value of the addend
24485 into the first 4 bits of the instruction, and the remaining
24486 four into bits 8 .. 11. */
24487 insn
&= 0xfffff0f0;
24488 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24490 /* Update the instruction. */
24491 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24495 case BFD_RELOC_ARM_LDC_PC_G0
:
24496 case BFD_RELOC_ARM_LDC_PC_G1
:
24497 case BFD_RELOC_ARM_LDC_PC_G2
:
24498 case BFD_RELOC_ARM_LDC_SB_G0
:
24499 case BFD_RELOC_ARM_LDC_SB_G1
:
24500 case BFD_RELOC_ARM_LDC_SB_G2
:
24501 gas_assert (!fixP
->fx_done
);
24502 if (!seg
->use_rela_p
)
24505 bfd_vma addend_abs
= abs (value
);
24507 /* Check that the absolute value of the addend is a multiple of
24508 four and, when divided by four, fits in 8 bits. */
24509 if (addend_abs
& 0x3)
24510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24511 _("bad offset 0x%08lX (must be word-aligned)"),
24512 (unsigned long) addend_abs
);
24514 if ((addend_abs
>> 2) > 0xff)
24515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24516 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24517 (unsigned long) addend_abs
);
24519 /* Extract the instruction. */
24520 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24522 /* If the addend is negative, clear bit 23 of the instruction.
24523 Otherwise set it. */
24525 insn
&= ~(1 << 23);
24529 /* Place the addend (divided by four) into the first eight
24530 bits of the instruction. */
24531 insn
&= 0xfffffff0;
24532 insn
|= addend_abs
>> 2;
24534 /* Update the instruction. */
24535 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24539 case BFD_RELOC_ARM_V4BX
:
24540 /* This will need to go in the object file. */
24544 case BFD_RELOC_UNUSED
:
24546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24547 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24551 /* Translate internal representation of relocation info to BFD target
24555 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24558 bfd_reloc_code_real_type code
;
24560 reloc
= XNEW (arelent
);
24562 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24563 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24564 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24566 if (fixp
->fx_pcrel
)
24568 if (section
->use_rela_p
)
24569 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24571 fixp
->fx_offset
= reloc
->address
;
24573 reloc
->addend
= fixp
->fx_offset
;
24575 switch (fixp
->fx_r_type
)
24578 if (fixp
->fx_pcrel
)
24580 code
= BFD_RELOC_8_PCREL
;
24583 /* Fall through. */
24586 if (fixp
->fx_pcrel
)
24588 code
= BFD_RELOC_16_PCREL
;
24591 /* Fall through. */
24594 if (fixp
->fx_pcrel
)
24596 code
= BFD_RELOC_32_PCREL
;
24599 /* Fall through. */
24601 case BFD_RELOC_ARM_MOVW
:
24602 if (fixp
->fx_pcrel
)
24604 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24607 /* Fall through. */
24609 case BFD_RELOC_ARM_MOVT
:
24610 if (fixp
->fx_pcrel
)
24612 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24615 /* Fall through. */
24617 case BFD_RELOC_ARM_THUMB_MOVW
:
24618 if (fixp
->fx_pcrel
)
24620 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24623 /* Fall through. */
24625 case BFD_RELOC_ARM_THUMB_MOVT
:
24626 if (fixp
->fx_pcrel
)
24628 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24631 /* Fall through. */
24633 case BFD_RELOC_NONE
:
24634 case BFD_RELOC_ARM_PCREL_BRANCH
:
24635 case BFD_RELOC_ARM_PCREL_BLX
:
24636 case BFD_RELOC_RVA
:
24637 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24638 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24639 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24640 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24641 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24642 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24643 case BFD_RELOC_VTABLE_ENTRY
:
24644 case BFD_RELOC_VTABLE_INHERIT
:
24646 case BFD_RELOC_32_SECREL
:
24648 code
= fixp
->fx_r_type
;
24651 case BFD_RELOC_THUMB_PCREL_BLX
:
24653 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24654 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24657 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24660 case BFD_RELOC_ARM_LITERAL
:
24661 case BFD_RELOC_ARM_HWLITERAL
:
24662 /* If this is called then the a literal has
24663 been referenced across a section boundary. */
24664 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24665 _("literal referenced across section boundary"));
24669 case BFD_RELOC_ARM_TLS_CALL
:
24670 case BFD_RELOC_ARM_THM_TLS_CALL
:
24671 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24672 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24673 case BFD_RELOC_ARM_GOT32
:
24674 case BFD_RELOC_ARM_GOTOFF
:
24675 case BFD_RELOC_ARM_GOT_PREL
:
24676 case BFD_RELOC_ARM_PLT32
:
24677 case BFD_RELOC_ARM_TARGET1
:
24678 case BFD_RELOC_ARM_ROSEGREL32
:
24679 case BFD_RELOC_ARM_SBREL32
:
24680 case BFD_RELOC_ARM_PREL31
:
24681 case BFD_RELOC_ARM_TARGET2
:
24682 case BFD_RELOC_ARM_TLS_LDO32
:
24683 case BFD_RELOC_ARM_PCREL_CALL
:
24684 case BFD_RELOC_ARM_PCREL_JUMP
:
24685 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24686 case BFD_RELOC_ARM_ALU_PC_G0
:
24687 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24688 case BFD_RELOC_ARM_ALU_PC_G1
:
24689 case BFD_RELOC_ARM_ALU_PC_G2
:
24690 case BFD_RELOC_ARM_LDR_PC_G0
:
24691 case BFD_RELOC_ARM_LDR_PC_G1
:
24692 case BFD_RELOC_ARM_LDR_PC_G2
:
24693 case BFD_RELOC_ARM_LDRS_PC_G0
:
24694 case BFD_RELOC_ARM_LDRS_PC_G1
:
24695 case BFD_RELOC_ARM_LDRS_PC_G2
:
24696 case BFD_RELOC_ARM_LDC_PC_G0
:
24697 case BFD_RELOC_ARM_LDC_PC_G1
:
24698 case BFD_RELOC_ARM_LDC_PC_G2
:
24699 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24700 case BFD_RELOC_ARM_ALU_SB_G0
:
24701 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24702 case BFD_RELOC_ARM_ALU_SB_G1
:
24703 case BFD_RELOC_ARM_ALU_SB_G2
:
24704 case BFD_RELOC_ARM_LDR_SB_G0
:
24705 case BFD_RELOC_ARM_LDR_SB_G1
:
24706 case BFD_RELOC_ARM_LDR_SB_G2
:
24707 case BFD_RELOC_ARM_LDRS_SB_G0
:
24708 case BFD_RELOC_ARM_LDRS_SB_G1
:
24709 case BFD_RELOC_ARM_LDRS_SB_G2
:
24710 case BFD_RELOC_ARM_LDC_SB_G0
:
24711 case BFD_RELOC_ARM_LDC_SB_G1
:
24712 case BFD_RELOC_ARM_LDC_SB_G2
:
24713 case BFD_RELOC_ARM_V4BX
:
24714 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24715 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24716 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24717 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24718 code
= fixp
->fx_r_type
;
24721 case BFD_RELOC_ARM_TLS_GOTDESC
:
24722 case BFD_RELOC_ARM_TLS_GD32
:
24723 case BFD_RELOC_ARM_TLS_LE32
:
24724 case BFD_RELOC_ARM_TLS_IE32
:
24725 case BFD_RELOC_ARM_TLS_LDM32
:
24726 /* BFD will include the symbol's address in the addend.
24727 But we don't want that, so subtract it out again here. */
24728 if (!S_IS_COMMON (fixp
->fx_addsy
))
24729 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24730 code
= fixp
->fx_r_type
;
24734 case BFD_RELOC_ARM_IMMEDIATE
:
24735 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24736 _("internal relocation (type: IMMEDIATE) not fixed up"));
24739 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24740 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24741 _("ADRL used for a symbol not defined in the same file"));
24744 case BFD_RELOC_ARM_OFFSET_IMM
:
24745 if (section
->use_rela_p
)
24747 code
= fixp
->fx_r_type
;
24751 if (fixp
->fx_addsy
!= NULL
24752 && !S_IS_DEFINED (fixp
->fx_addsy
)
24753 && S_IS_LOCAL (fixp
->fx_addsy
))
24755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24756 _("undefined local label `%s'"),
24757 S_GET_NAME (fixp
->fx_addsy
));
24761 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24762 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24769 switch (fixp
->fx_r_type
)
24771 case BFD_RELOC_NONE
: type
= "NONE"; break;
24772 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24773 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24774 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24775 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24776 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24777 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24778 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24779 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24780 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24781 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24782 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24783 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24784 default: type
= _("<unknown>"); break;
24786 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24787 _("cannot represent %s relocation in this object file format"),
24794 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24796 && fixp
->fx_addsy
== GOT_symbol
)
24798 code
= BFD_RELOC_ARM_GOTPC
;
24799 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24803 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24805 if (reloc
->howto
== NULL
)
24807 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24808 _("cannot represent %s relocation in this object file format"),
24809 bfd_get_reloc_code_name (code
));
24813 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24814 vtable entry to be used in the relocation's section offset. */
24815 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24816 reloc
->address
= fixp
->fx_offset
;
24821 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24824 cons_fix_new_arm (fragS
* frag
,
24828 bfd_reloc_code_real_type reloc
)
24833 FIXME: @@ Should look at CPU word size. */
24837 reloc
= BFD_RELOC_8
;
24840 reloc
= BFD_RELOC_16
;
24844 reloc
= BFD_RELOC_32
;
24847 reloc
= BFD_RELOC_64
;
24852 if (exp
->X_op
== O_secrel
)
24854 exp
->X_op
= O_symbol
;
24855 reloc
= BFD_RELOC_32_SECREL
;
24859 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24862 #if defined (OBJ_COFF)
24864 arm_validate_fix (fixS
* fixP
)
24866 /* If the destination of the branch is a defined symbol which does not have
24867 the THUMB_FUNC attribute, then we must be calling a function which has
24868 the (interfacearm) attribute. We look for the Thumb entry point to that
24869 function and change the branch to refer to that function instead. */
24870 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24871 && fixP
->fx_addsy
!= NULL
24872 && S_IS_DEFINED (fixP
->fx_addsy
)
24873 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24875 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24882 arm_force_relocation (struct fix
* fixp
)
24884 #if defined (OBJ_COFF) && defined (TE_PE)
24885 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24889 /* In case we have a call or a branch to a function in ARM ISA mode from
24890 a thumb function or vice-versa force the relocation. These relocations
24891 are cleared off for some cores that might have blx and simple transformations
24895 switch (fixp
->fx_r_type
)
24897 case BFD_RELOC_ARM_PCREL_JUMP
:
24898 case BFD_RELOC_ARM_PCREL_CALL
:
24899 case BFD_RELOC_THUMB_PCREL_BLX
:
24900 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24904 case BFD_RELOC_ARM_PCREL_BLX
:
24905 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24906 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24907 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24908 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24917 /* Resolve these relocations even if the symbol is extern or weak.
24918 Technically this is probably wrong due to symbol preemption.
24919 In practice these relocations do not have enough range to be useful
24920 at dynamic link time, and some code (e.g. in the Linux kernel)
24921 expects these references to be resolved. */
24922 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24923 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24924 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24925 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24926 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24927 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24928 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24929 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24930 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24931 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24932 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24933 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24934 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24935 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24938 /* Always leave these relocations for the linker. */
24939 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24940 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24941 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24944 /* Always generate relocations against function symbols. */
24945 if (fixp
->fx_r_type
== BFD_RELOC_32
24947 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24950 return generic_force_reloc (fixp
);
24953 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24954 /* Relocations against function names must be left unadjusted,
24955 so that the linker can use this information to generate interworking
24956 stubs. The MIPS version of this function
24957 also prevents relocations that are mips-16 specific, but I do not
24958 know why it does this.
24961 There is one other problem that ought to be addressed here, but
24962 which currently is not: Taking the address of a label (rather
24963 than a function) and then later jumping to that address. Such
24964 addresses also ought to have their bottom bit set (assuming that
24965 they reside in Thumb code), but at the moment they will not. */
24968 arm_fix_adjustable (fixS
* fixP
)
24970 if (fixP
->fx_addsy
== NULL
)
24973 /* Preserve relocations against symbols with function type. */
24974 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24977 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24978 && fixP
->fx_subsy
== NULL
)
24981 /* We need the symbol name for the VTABLE entries. */
24982 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24983 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24986 /* Don't allow symbols to be discarded on GOT related relocs. */
24987 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24988 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24989 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24990 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24991 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24992 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24993 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24994 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24995 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24996 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24997 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24998 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24999 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25000 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25003 /* Similarly for group relocations. */
25004 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25005 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25006 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25009 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25010 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25011 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25012 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25013 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25014 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25015 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25016 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25017 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25020 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25021 offsets, so keep these symbols. */
25022 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25023 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25028 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25032 elf32_arm_target_format (void)
25035 return (target_big_endian
25036 ? "elf32-bigarm-symbian"
25037 : "elf32-littlearm-symbian");
25038 #elif defined (TE_VXWORKS)
25039 return (target_big_endian
25040 ? "elf32-bigarm-vxworks"
25041 : "elf32-littlearm-vxworks");
25042 #elif defined (TE_NACL)
25043 return (target_big_endian
25044 ? "elf32-bigarm-nacl"
25045 : "elf32-littlearm-nacl");
25047 if (target_big_endian
)
25048 return "elf32-bigarm";
25050 return "elf32-littlearm";
25055 armelf_frob_symbol (symbolS
* symp
,
25058 elf_frob_symbol (symp
, puntp
);
25062 /* MD interface: Finalization. */
25067 literal_pool
* pool
;
25069 /* Ensure that all the IT blocks are properly closed. */
25070 check_it_blocks_finished ();
25072 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25074 /* Put it at the end of the relevant section. */
25075 subseg_set (pool
->section
, pool
->sub_section
);
25077 arm_elf_change_section ();
25084 /* Remove any excess mapping symbols generated for alignment frags in
25085 SEC. We may have created a mapping symbol before a zero byte
25086 alignment; remove it if there's a mapping symbol after the
25089 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25090 void *dummy ATTRIBUTE_UNUSED
)
25092 segment_info_type
*seginfo
= seg_info (sec
);
25095 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25098 for (fragp
= seginfo
->frchainP
->frch_root
;
25100 fragp
= fragp
->fr_next
)
25102 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25103 fragS
*next
= fragp
->fr_next
;
25105 /* Variable-sized frags have been converted to fixed size by
25106 this point. But if this was variable-sized to start with,
25107 there will be a fixed-size frag after it. So don't handle
25109 if (sym
== NULL
|| next
== NULL
)
25112 if (S_GET_VALUE (sym
) < next
->fr_address
)
25113 /* Not at the end of this frag. */
25115 know (S_GET_VALUE (sym
) == next
->fr_address
);
25119 if (next
->tc_frag_data
.first_map
!= NULL
)
25121 /* Next frag starts with a mapping symbol. Discard this
25123 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25127 if (next
->fr_next
== NULL
)
25129 /* This mapping symbol is at the end of the section. Discard
25131 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25132 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25136 /* As long as we have empty frags without any mapping symbols,
25138 /* If the next frag is non-empty and does not start with a
25139 mapping symbol, then this mapping symbol is required. */
25140 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25143 next
= next
->fr_next
;
25145 while (next
!= NULL
);
25150 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25154 arm_adjust_symtab (void)
25159 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25161 if (ARM_IS_THUMB (sym
))
25163 if (THUMB_IS_FUNC (sym
))
25165 /* Mark the symbol as a Thumb function. */
25166 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25167 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25168 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25170 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25171 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25173 as_bad (_("%s: unexpected function type: %d"),
25174 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25176 else switch (S_GET_STORAGE_CLASS (sym
))
25179 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25182 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25185 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25193 if (ARM_IS_INTERWORK (sym
))
25194 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25201 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25203 if (ARM_IS_THUMB (sym
))
25205 elf_symbol_type
* elf_sym
;
25207 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25208 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25210 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25211 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25213 /* If it's a .thumb_func, declare it as so,
25214 otherwise tag label as .code 16. */
25215 if (THUMB_IS_FUNC (sym
))
25216 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25217 ST_BRANCH_TO_THUMB
);
25218 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25219 elf_sym
->internal_elf_sym
.st_info
=
25220 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25225 /* Remove any overlapping mapping symbols generated by alignment frags. */
25226 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25227 /* Now do generic ELF adjustments. */
25228 elf_adjust_symtab ();
25232 /* MD interface: Initialization. */
25235 set_constant_flonums (void)
25239 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25240 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25244 /* Auto-select Thumb mode if it's the only available instruction set for the
25245 given architecture. */
25248 autoselect_thumb_from_cpu_variant (void)
25250 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25251 opcode_select (16);
25260 if ( (arm_ops_hsh
= hash_new ()) == NULL
25261 || (arm_cond_hsh
= hash_new ()) == NULL
25262 || (arm_shift_hsh
= hash_new ()) == NULL
25263 || (arm_psr_hsh
= hash_new ()) == NULL
25264 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25265 || (arm_reg_hsh
= hash_new ()) == NULL
25266 || (arm_reloc_hsh
= hash_new ()) == NULL
25267 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25268 as_fatal (_("virtual memory exhausted"));
25270 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25271 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25272 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25273 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25274 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25275 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25276 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25277 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25278 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25279 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25280 (void *) (v7m_psrs
+ i
));
25281 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25282 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25284 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25286 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25287 (void *) (barrier_opt_names
+ i
));
25289 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25291 struct reloc_entry
* entry
= reloc_names
+ i
;
25293 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25294 /* This makes encode_branch() use the EABI versions of this relocation. */
25295 entry
->reloc
= BFD_RELOC_UNUSED
;
25297 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25301 set_constant_flonums ();
25303 /* Set the cpu variant based on the command-line options. We prefer
25304 -mcpu= over -march= if both are set (as for GCC); and we prefer
25305 -mfpu= over any other way of setting the floating point unit.
25306 Use of legacy options with new options are faulted. */
25309 if (mcpu_cpu_opt
|| march_cpu_opt
)
25310 as_bad (_("use of old and new-style options to set CPU type"));
25312 mcpu_cpu_opt
= legacy_cpu
;
25314 else if (!mcpu_cpu_opt
)
25316 mcpu_cpu_opt
= march_cpu_opt
;
25317 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25318 /* Avoid double free in arm_md_end. */
25319 dyn_march_ext_opt
= NULL
;
25325 as_bad (_("use of old and new-style options to set FPU type"));
25327 mfpu_opt
= legacy_fpu
;
25329 else if (!mfpu_opt
)
25331 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25332 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25333 /* Some environments specify a default FPU. If they don't, infer it
25334 from the processor. */
25336 mfpu_opt
= mcpu_fpu_opt
;
25338 mfpu_opt
= march_fpu_opt
;
25340 mfpu_opt
= &fpu_default
;
25346 if (mcpu_cpu_opt
!= NULL
)
25347 mfpu_opt
= &fpu_default
;
25348 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25349 mfpu_opt
= &fpu_arch_vfp_v2
;
25351 mfpu_opt
= &fpu_arch_fpa
;
25357 mcpu_cpu_opt
= &cpu_default
;
25358 selected_cpu
= cpu_default
;
25360 else if (dyn_mcpu_ext_opt
)
25361 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25363 selected_cpu
= *mcpu_cpu_opt
;
25365 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25366 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25367 else if (mcpu_cpu_opt
)
25368 selected_cpu
= *mcpu_cpu_opt
;
25370 mcpu_cpu_opt
= &arm_arch_any
;
25373 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25374 if (dyn_mcpu_ext_opt
)
25375 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25377 autoselect_thumb_from_cpu_variant ();
25379 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25381 #if defined OBJ_COFF || defined OBJ_ELF
25383 unsigned int flags
= 0;
25385 #if defined OBJ_ELF
25386 flags
= meabi_flags
;
25388 switch (meabi_flags
)
25390 case EF_ARM_EABI_UNKNOWN
:
25392 /* Set the flags in the private structure. */
25393 if (uses_apcs_26
) flags
|= F_APCS26
;
25394 if (support_interwork
) flags
|= F_INTERWORK
;
25395 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25396 if (pic_code
) flags
|= F_PIC
;
25397 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25398 flags
|= F_SOFT_FLOAT
;
25400 switch (mfloat_abi_opt
)
25402 case ARM_FLOAT_ABI_SOFT
:
25403 case ARM_FLOAT_ABI_SOFTFP
:
25404 flags
|= F_SOFT_FLOAT
;
25407 case ARM_FLOAT_ABI_HARD
:
25408 if (flags
& F_SOFT_FLOAT
)
25409 as_bad (_("hard-float conflicts with specified fpu"));
25413 /* Using pure-endian doubles (even if soft-float). */
25414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25415 flags
|= F_VFP_FLOAT
;
25417 #if defined OBJ_ELF
25418 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25419 flags
|= EF_ARM_MAVERICK_FLOAT
;
25422 case EF_ARM_EABI_VER4
:
25423 case EF_ARM_EABI_VER5
:
25424 /* No additional flags to set. */
25431 bfd_set_private_flags (stdoutput
, flags
);
25433 /* We have run out flags in the COFF header to encode the
25434 status of ATPCS support, so instead we create a dummy,
25435 empty, debug section called .arm.atpcs. */
25440 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25444 bfd_set_section_flags
25445 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25446 bfd_set_section_size (stdoutput
, sec
, 0);
25447 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25453 /* Record the CPU type as well. */
25454 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25455 mach
= bfd_mach_arm_iWMMXt2
;
25456 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25457 mach
= bfd_mach_arm_iWMMXt
;
25458 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25459 mach
= bfd_mach_arm_XScale
;
25460 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25461 mach
= bfd_mach_arm_ep9312
;
25462 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25463 mach
= bfd_mach_arm_5TE
;
25464 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25466 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25467 mach
= bfd_mach_arm_5T
;
25469 mach
= bfd_mach_arm_5
;
25471 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25473 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25474 mach
= bfd_mach_arm_4T
;
25476 mach
= bfd_mach_arm_4
;
25478 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25479 mach
= bfd_mach_arm_3M
;
25480 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25481 mach
= bfd_mach_arm_3
;
25482 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25483 mach
= bfd_mach_arm_2a
;
25484 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25485 mach
= bfd_mach_arm_2
;
25487 mach
= bfd_mach_arm_unknown
;
25489 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25492 /* Command line processing. */
25495 Invocation line includes a switch not recognized by the base assembler.
25496 See if it's a processor-specific option.
25498 This routine is somewhat complicated by the need for backwards
25499 compatibility (since older releases of gcc can't be changed).
25500 The new options try to make the interface as compatible as
25503 New options (supported) are:
25505 -mcpu=<cpu name> Assemble for selected processor
25506 -march=<architecture name> Assemble for selected architecture
25507 -mfpu=<fpu architecture> Assemble for selected FPU.
25508 -EB/-mbig-endian Big-endian
25509 -EL/-mlittle-endian Little-endian
25510 -k Generate PIC code
25511 -mthumb Start in Thumb mode
25512 -mthumb-interwork Code supports ARM/Thumb interworking
25514 -m[no-]warn-deprecated Warn about deprecated features
25515 -m[no-]warn-syms Warn when symbols match instructions
25517 For now we will also provide support for:
25519 -mapcs-32 32-bit Program counter
25520 -mapcs-26 26-bit Program counter
25521 -macps-float Floats passed in FP registers
25522 -mapcs-reentrant Reentrant code
25524 (sometime these will probably be replaced with -mapcs=<list of options>
25525 and -matpcs=<list of options>)
25527 The remaining options are only supported for back-wards compatibility.
25528 Cpu variants, the arm part is optional:
25529 -m[arm]1 Currently not supported.
25530 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25531 -m[arm]3 Arm 3 processor
25532 -m[arm]6[xx], Arm 6 processors
25533 -m[arm]7[xx][t][[d]m] Arm 7 processors
25534 -m[arm]8[10] Arm 8 processors
25535 -m[arm]9[20][tdmi] Arm 9 processors
25536 -mstrongarm[110[0]] StrongARM processors
25537 -mxscale XScale processors
25538 -m[arm]v[2345[t[e]]] Arm architectures
25539 -mall All (except the ARM1)
25541 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25542 -mfpe-old (No float load/store multiples)
25543 -mvfpxd VFP Single precision
25545 -mno-fpu Disable all floating point instructions
25547 The following CPU names are recognized:
25548 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25549 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25550 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25551 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25552 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25553 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25554 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25558 const char * md_shortopts
= "m:k";
25560 #ifdef ARM_BI_ENDIAN
25561 #define OPTION_EB (OPTION_MD_BASE + 0)
25562 #define OPTION_EL (OPTION_MD_BASE + 1)
25564 #if TARGET_BYTES_BIG_ENDIAN
25565 #define OPTION_EB (OPTION_MD_BASE + 0)
25567 #define OPTION_EL (OPTION_MD_BASE + 1)
25570 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25572 struct option md_longopts
[] =
25575 {"EB", no_argument
, NULL
, OPTION_EB
},
25578 {"EL", no_argument
, NULL
, OPTION_EL
},
25580 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25581 {NULL
, no_argument
, NULL
, 0}
25584 size_t md_longopts_size
= sizeof (md_longopts
);
25586 struct arm_option_table
25588 const char * option
; /* Option name to match. */
25589 const char * help
; /* Help information. */
25590 int * var
; /* Variable to change. */
25591 int value
; /* What to change it to. */
25592 const char * deprecated
; /* If non-null, print this message. */
25595 struct arm_option_table arm_opts
[] =
25597 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25598 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25599 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25600 &support_interwork
, 1, NULL
},
25601 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25602 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25603 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25605 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25606 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25607 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25608 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25611 /* These are recognized by the assembler, but have no affect on code. */
25612 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25613 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25615 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25616 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25617 &warn_on_deprecated
, 0, NULL
},
25618 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25619 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25620 {NULL
, NULL
, NULL
, 0, NULL
}
25623 struct arm_legacy_option_table
25625 const char * option
; /* Option name to match. */
25626 const arm_feature_set
** var
; /* Variable to change. */
25627 const arm_feature_set value
; /* What to change it to. */
25628 const char * deprecated
; /* If non-null, print this message. */
25631 const struct arm_legacy_option_table arm_legacy_opts
[] =
25633 /* DON'T add any new processors to this list -- we want the whole list
25634 to go away... Add them to the processors table instead. */
25635 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25636 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25637 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25638 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25639 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25640 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25641 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25642 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25643 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25644 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25645 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25646 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25647 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25648 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25649 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25650 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25651 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25652 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25653 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25654 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25655 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25656 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25657 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25658 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25659 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25660 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25661 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25662 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25663 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25664 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25665 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25666 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25667 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25668 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25669 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25670 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25671 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25672 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25673 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25674 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25675 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25676 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25677 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25678 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25679 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25680 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25681 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25682 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25683 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25684 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25685 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25686 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25687 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25688 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25689 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25690 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25691 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25692 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25693 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25694 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25695 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25696 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25697 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25698 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25699 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25700 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25701 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25702 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25703 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25704 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25705 N_("use -mcpu=strongarm110")},
25706 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25707 N_("use -mcpu=strongarm1100")},
25708 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25709 N_("use -mcpu=strongarm1110")},
25710 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25711 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25712 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25714 /* Architecture variants -- don't add any more to this list either. */
25715 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25716 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25717 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25718 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25719 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25720 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25721 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25722 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25723 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25724 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25725 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25726 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25727 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25728 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25729 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25730 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25731 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25732 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25734 /* Floating point variants -- don't add any more to this list either. */
25735 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25736 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25737 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25738 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25739 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25741 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25744 struct arm_cpu_option_table
25748 const arm_feature_set value
;
25749 const arm_feature_set ext
;
25750 /* For some CPUs we assume an FPU unless the user explicitly sets
25752 const arm_feature_set default_fpu
;
25753 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25755 const char * canonical_name
;
25758 /* This list should, at a minimum, contain all the cpu names
25759 recognized by GCC. */
25760 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25762 static const struct arm_cpu_option_table arm_cpus
[] =
25764 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25767 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25770 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25773 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25776 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25779 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25782 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25785 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25788 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25791 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25794 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25797 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25800 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25803 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25806 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25809 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25812 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25815 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25818 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25821 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25824 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25827 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25830 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25833 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25836 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25839 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25842 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25845 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25848 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25851 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25854 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25857 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25860 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25863 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25866 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25869 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25872 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25875 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25878 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25881 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25884 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25887 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25890 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25893 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25896 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25899 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25903 /* For V5 or later processors we default to using VFP; but the user
25904 should really set the FPU type explicitly. */
25905 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25908 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25911 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25914 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25917 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25920 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25923 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25926 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25929 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25932 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25935 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25938 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25941 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25944 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25947 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25950 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25953 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25956 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25959 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25962 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25965 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25968 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25971 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25974 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25977 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25980 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25983 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25986 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25989 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25992 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25995 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25998 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26001 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26004 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26007 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26010 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26013 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26014 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26016 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26018 FPU_ARCH_NEON_VFP_V4
),
26019 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26020 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26021 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26022 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26023 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26024 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26025 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26027 FPU_ARCH_NEON_VFP_V4
),
26028 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26030 FPU_ARCH_NEON_VFP_V4
),
26031 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26033 FPU_ARCH_NEON_VFP_V4
),
26034 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26035 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26036 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26037 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26038 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26039 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26040 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26041 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26042 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26043 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26044 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26045 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26046 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26047 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26048 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26049 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26050 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26051 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26052 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26053 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26054 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26055 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26056 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26057 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26058 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26061 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26063 FPU_ARCH_VFP_V3D16
),
26064 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26065 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26067 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26068 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26069 FPU_ARCH_VFP_V3D16
),
26070 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26071 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26072 FPU_ARCH_VFP_V3D16
),
26073 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26074 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26075 FPU_ARCH_NEON_VFP_ARMV8
),
26076 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26077 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26079 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26082 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26085 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26088 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26091 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26094 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26097 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26100 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26101 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26102 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26104 /* ??? XSCALE is really an architecture. */
26105 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26109 /* ??? iwmmxt is not a processor. */
26110 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26113 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26116 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26121 ARM_CPU_OPT ("ep9312", "ARM920T",
26122 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26123 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26125 /* Marvell processors. */
26126 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26127 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26128 FPU_ARCH_VFP_V3D16
),
26129 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26130 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26131 FPU_ARCH_NEON_VFP_V4
),
26133 /* APM X-Gene family. */
26134 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26136 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26137 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26138 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26139 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26141 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26145 struct arm_arch_option_table
26149 const arm_feature_set value
;
26150 const arm_feature_set default_fpu
;
26153 /* This list should, at a minimum, contain all the architecture names
26154 recognized by GCC. */
26155 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26157 static const struct arm_arch_option_table arm_archs
[] =
26159 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26160 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26161 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26162 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26163 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26164 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26165 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26166 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26167 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26168 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26169 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26170 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26171 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26172 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26173 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26174 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26175 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26176 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26177 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26178 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26179 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26180 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26181 kept to preserve existing behaviour. */
26182 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26183 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26184 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26185 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26186 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26187 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26188 kept to preserve existing behaviour. */
26189 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26190 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26191 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26192 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26193 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26194 /* The official spelling of the ARMv7 profile variants is the dashed form.
26195 Accept the non-dashed form for compatibility with old toolchains. */
26196 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26197 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26198 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26199 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26200 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26201 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26202 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26203 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26204 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26205 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26206 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26207 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26208 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26209 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26210 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26211 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26212 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26213 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26214 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26215 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26217 #undef ARM_ARCH_OPT
26219 /* ISA extensions in the co-processor and main instruction set space. */
26221 struct arm_option_extension_value_table
26225 const arm_feature_set merge_value
;
26226 const arm_feature_set clear_value
;
26227 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26228 indicates that an extension is available for all architectures while
26229 ARM_ANY marks an empty entry. */
26230 const arm_feature_set allowed_archs
[2];
26233 /* The following table must be in alphabetical order with a NULL last entry. */
26235 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26236 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26238 static const struct arm_option_extension_value_table arm_extensions
[] =
26240 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26241 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26242 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26243 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26244 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26245 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26246 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26248 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26249 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26250 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26251 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26252 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26253 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26256 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26257 | ARM_EXT2_FP16_FML
),
26258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26259 | ARM_EXT2_FP16_FML
),
26261 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26262 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26263 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26264 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26265 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26266 Thumb divide instruction. Due to this having the same name as the
26267 previous entry, this will be ignored when doing command-line parsing and
26268 only considered by build attribute selection code. */
26269 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26270 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26271 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26272 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26273 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26274 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26275 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26276 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26277 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26278 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26279 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26280 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26281 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26282 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26283 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26284 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26285 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26286 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26288 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26289 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26290 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26291 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26292 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26294 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26295 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26296 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26297 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26298 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26299 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26300 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26301 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26303 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26304 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26305 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26306 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26307 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26311 /* ISA floating-point and Advanced SIMD extensions. */
26312 struct arm_option_fpu_value_table
26315 const arm_feature_set value
;
26318 /* This list should, at a minimum, contain all the fpu names
26319 recognized by GCC. */
26320 static const struct arm_option_fpu_value_table arm_fpus
[] =
26322 {"softfpa", FPU_NONE
},
26323 {"fpe", FPU_ARCH_FPE
},
26324 {"fpe2", FPU_ARCH_FPE
},
26325 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26326 {"fpa", FPU_ARCH_FPA
},
26327 {"fpa10", FPU_ARCH_FPA
},
26328 {"fpa11", FPU_ARCH_FPA
},
26329 {"arm7500fe", FPU_ARCH_FPA
},
26330 {"softvfp", FPU_ARCH_VFP
},
26331 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26332 {"vfp", FPU_ARCH_VFP_V2
},
26333 {"vfp9", FPU_ARCH_VFP_V2
},
26334 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26335 {"vfp10", FPU_ARCH_VFP_V2
},
26336 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26337 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26338 {"vfpv2", FPU_ARCH_VFP_V2
},
26339 {"vfpv3", FPU_ARCH_VFP_V3
},
26340 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26341 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26342 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26343 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26344 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26345 {"arm1020t", FPU_ARCH_VFP_V1
},
26346 {"arm1020e", FPU_ARCH_VFP_V2
},
26347 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26348 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26349 {"maverick", FPU_ARCH_MAVERICK
},
26350 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26351 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26352 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26353 {"vfpv4", FPU_ARCH_VFP_V4
},
26354 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26355 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26356 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26357 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26358 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26359 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26360 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26361 {"crypto-neon-fp-armv8",
26362 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26363 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26364 {"crypto-neon-fp-armv8.1",
26365 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26366 {NULL
, ARM_ARCH_NONE
}
26369 struct arm_option_value_table
26375 static const struct arm_option_value_table arm_float_abis
[] =
26377 {"hard", ARM_FLOAT_ABI_HARD
},
26378 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26379 {"soft", ARM_FLOAT_ABI_SOFT
},
26384 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26385 static const struct arm_option_value_table arm_eabis
[] =
26387 {"gnu", EF_ARM_EABI_UNKNOWN
},
26388 {"4", EF_ARM_EABI_VER4
},
26389 {"5", EF_ARM_EABI_VER5
},
26394 struct arm_long_option_table
26396 const char * option
; /* Substring to match. */
26397 const char * help
; /* Help information. */
26398 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26399 const char * deprecated
; /* If non-null, print this message. */
26403 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26404 arm_feature_set
**ext_set_p
)
26406 /* We insist on extensions being specified in alphabetical order, and with
26407 extensions being added before being removed. We achieve this by having
26408 the global ARM_EXTENSIONS table in alphabetical order, and using the
26409 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26410 or removing it (0) and only allowing it to change in the order
26412 const struct arm_option_extension_value_table
* opt
= NULL
;
26413 const arm_feature_set arm_any
= ARM_ANY
;
26414 int adding_value
= -1;
26418 *ext_set_p
= XNEW (arm_feature_set
);
26419 **ext_set_p
= arm_arch_none
;
26422 while (str
!= NULL
&& *str
!= 0)
26429 as_bad (_("invalid architectural extension"));
26434 ext
= strchr (str
, '+');
26439 len
= strlen (str
);
26441 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26443 if (adding_value
!= 0)
26446 opt
= arm_extensions
;
26454 if (adding_value
== -1)
26457 opt
= arm_extensions
;
26459 else if (adding_value
!= 1)
26461 as_bad (_("must specify extensions to add before specifying "
26462 "those to remove"));
26469 as_bad (_("missing architectural extension"));
26473 gas_assert (adding_value
!= -1);
26474 gas_assert (opt
!= NULL
);
26476 /* Scan over the options table trying to find an exact match. */
26477 for (; opt
->name
!= NULL
; opt
++)
26478 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26480 int i
, nb_allowed_archs
=
26481 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26482 /* Check we can apply the extension to this architecture. */
26483 for (i
= 0; i
< nb_allowed_archs
; i
++)
26486 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26488 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26491 if (i
== nb_allowed_archs
)
26493 as_bad (_("extension does not apply to the base architecture"));
26497 /* Add or remove the extension. */
26499 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26502 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26504 /* Allowing Thumb division instructions for ARMv7 in autodetection
26505 rely on this break so that duplicate extensions (extensions
26506 with the same name as a previous extension in the list) are not
26507 considered for command-line parsing. */
26511 if (opt
->name
== NULL
)
26513 /* Did we fail to find an extension because it wasn't specified in
26514 alphabetical order, or because it does not exist? */
26516 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26517 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26520 if (opt
->name
== NULL
)
26521 as_bad (_("unknown architectural extension `%s'"), str
);
26523 as_bad (_("architectural extensions must be specified in "
26524 "alphabetical order"));
26530 /* We should skip the extension we've just matched the next time
26542 arm_parse_cpu (const char *str
)
26544 const struct arm_cpu_option_table
*opt
;
26545 const char *ext
= strchr (str
, '+');
26551 len
= strlen (str
);
26555 as_bad (_("missing cpu name `%s'"), str
);
26559 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26560 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26562 mcpu_cpu_opt
= &opt
->value
;
26563 if (!dyn_mcpu_ext_opt
)
26564 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26565 *dyn_mcpu_ext_opt
= opt
->ext
;
26566 mcpu_fpu_opt
= &opt
->default_fpu
;
26567 if (opt
->canonical_name
)
26569 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26570 strcpy (selected_cpu_name
, opt
->canonical_name
);
26576 if (len
>= sizeof selected_cpu_name
)
26577 len
= (sizeof selected_cpu_name
) - 1;
26579 for (i
= 0; i
< len
; i
++)
26580 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26581 selected_cpu_name
[i
] = 0;
26585 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26590 as_bad (_("unknown cpu `%s'"), str
);
26595 arm_parse_arch (const char *str
)
26597 const struct arm_arch_option_table
*opt
;
26598 const char *ext
= strchr (str
, '+');
26604 len
= strlen (str
);
26608 as_bad (_("missing architecture name `%s'"), str
);
26612 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26613 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26615 march_cpu_opt
= &opt
->value
;
26616 march_fpu_opt
= &opt
->default_fpu
;
26617 strcpy (selected_cpu_name
, opt
->name
);
26620 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26625 as_bad (_("unknown architecture `%s'\n"), str
);
26630 arm_parse_fpu (const char * str
)
26632 const struct arm_option_fpu_value_table
* opt
;
26634 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26635 if (streq (opt
->name
, str
))
26637 mfpu_opt
= &opt
->value
;
26641 as_bad (_("unknown floating point format `%s'\n"), str
);
26646 arm_parse_float_abi (const char * str
)
26648 const struct arm_option_value_table
* opt
;
26650 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26651 if (streq (opt
->name
, str
))
26653 mfloat_abi_opt
= opt
->value
;
26657 as_bad (_("unknown floating point abi `%s'\n"), str
);
26663 arm_parse_eabi (const char * str
)
26665 const struct arm_option_value_table
*opt
;
26667 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26668 if (streq (opt
->name
, str
))
26670 meabi_flags
= opt
->value
;
26673 as_bad (_("unknown EABI `%s'\n"), str
);
26679 arm_parse_it_mode (const char * str
)
26681 bfd_boolean ret
= TRUE
;
26683 if (streq ("arm", str
))
26684 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26685 else if (streq ("thumb", str
))
26686 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26687 else if (streq ("always", str
))
26688 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26689 else if (streq ("never", str
))
26690 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26693 as_bad (_("unknown implicit IT mode `%s', should be "\
26694 "arm, thumb, always, or never."), str
);
26702 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26704 codecomposer_syntax
= TRUE
;
26705 arm_comment_chars
[0] = ';';
26706 arm_line_separator_chars
[0] = 0;
26710 struct arm_long_option_table arm_long_opts
[] =
26712 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26713 arm_parse_cpu
, NULL
},
26714 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26715 arm_parse_arch
, NULL
},
26716 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26717 arm_parse_fpu
, NULL
},
26718 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26719 arm_parse_float_abi
, NULL
},
26721 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26722 arm_parse_eabi
, NULL
},
26724 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26725 arm_parse_it_mode
, NULL
},
26726 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26727 arm_ccs_mode
, NULL
},
26728 {NULL
, NULL
, 0, NULL
}
26732 md_parse_option (int c
, const char * arg
)
26734 struct arm_option_table
*opt
;
26735 const struct arm_legacy_option_table
*fopt
;
26736 struct arm_long_option_table
*lopt
;
26742 target_big_endian
= 1;
26748 target_big_endian
= 0;
26752 case OPTION_FIX_V4BX
:
26757 /* Listing option. Just ignore these, we don't support additional
26762 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26764 if (c
== opt
->option
[0]
26765 && ((arg
== NULL
&& opt
->option
[1] == 0)
26766 || streq (arg
, opt
->option
+ 1)))
26768 /* If the option is deprecated, tell the user. */
26769 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26770 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26771 arg
? arg
: "", _(opt
->deprecated
));
26773 if (opt
->var
!= NULL
)
26774 *opt
->var
= opt
->value
;
26780 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26782 if (c
== fopt
->option
[0]
26783 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26784 || streq (arg
, fopt
->option
+ 1)))
26786 /* If the option is deprecated, tell the user. */
26787 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26788 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26789 arg
? arg
: "", _(fopt
->deprecated
));
26791 if (fopt
->var
!= NULL
)
26792 *fopt
->var
= &fopt
->value
;
26798 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26800 /* These options are expected to have an argument. */
26801 if (c
== lopt
->option
[0]
26803 && strncmp (arg
, lopt
->option
+ 1,
26804 strlen (lopt
->option
+ 1)) == 0)
26806 /* If the option is deprecated, tell the user. */
26807 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26808 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26809 _(lopt
->deprecated
));
26811 /* Call the sup-option parser. */
26812 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26823 md_show_usage (FILE * fp
)
26825 struct arm_option_table
*opt
;
26826 struct arm_long_option_table
*lopt
;
26828 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26830 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26831 if (opt
->help
!= NULL
)
26832 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26834 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26835 if (lopt
->help
!= NULL
)
26836 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26840 -EB assemble code for a big-endian cpu\n"));
26845 -EL assemble code for a little-endian cpu\n"));
26849 --fix-v4bx Allow BX in ARMv4 code\n"));
26857 arm_feature_set flags
;
26858 } cpu_arch_ver_table
;
26860 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26861 chronologically for architectures, with an exception for ARMv6-M and
26862 ARMv6S-M due to legacy reasons. No new architecture should have a
26863 special case. This allows for build attribute selection results to be
26864 stable when new architectures are added. */
26865 static const cpu_arch_ver_table cpu_arch_ver
[] =
26872 {1, ARM_ARCH_V4xM
},
26874 {2, ARM_ARCH_V4TxM
},
26876 {3, ARM_ARCH_V5xM
},
26878 {3, ARM_ARCH_V5TxM
},
26880 {4, ARM_ARCH_V5TExP
},
26881 {4, ARM_ARCH_V5TE
},
26882 {5, ARM_ARCH_V5TEJ
},
26885 {7, ARM_ARCH_V6KZ
},
26887 {8, ARM_ARCH_V6T2
},
26888 {8, ARM_ARCH_V6KT2
},
26889 {8, ARM_ARCH_V6ZT2
},
26890 {8, ARM_ARCH_V6KZT2
},
26892 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26893 always selected build attributes to match those of ARMv6-M
26894 (resp. ARMv6S-M). However, due to these architectures being a strict
26895 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26896 would be selected when fully respecting chronology of architectures.
26897 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26898 move them before ARMv7 architectures. */
26899 {11, ARM_ARCH_V6M
},
26900 {12, ARM_ARCH_V6SM
},
26903 {10, ARM_ARCH_V7A
},
26904 {10, ARM_ARCH_V7R
},
26905 {10, ARM_ARCH_V7M
},
26906 {10, ARM_ARCH_V7VE
},
26907 {13, ARM_ARCH_V7EM
},
26908 {14, ARM_ARCH_V8A
},
26909 {14, ARM_ARCH_V8_1A
},
26910 {14, ARM_ARCH_V8_2A
},
26911 {14, ARM_ARCH_V8_3A
},
26912 {16, ARM_ARCH_V8M_BASE
},
26913 {17, ARM_ARCH_V8M_MAIN
},
26914 {15, ARM_ARCH_V8R
},
26915 {16, ARM_ARCH_V8_4A
},
26916 {-1, ARM_ARCH_NONE
}
26919 /* Set an attribute if it has not already been set by the user. */
26922 aeabi_set_attribute_int (int tag
, int value
)
26925 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26926 || !attributes_set_explicitly
[tag
])
26927 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26931 aeabi_set_attribute_string (int tag
, const char *value
)
26934 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26935 || !attributes_set_explicitly
[tag
])
26936 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26939 /* Return whether features in the *NEEDED feature set are available via
26940 extensions for the architecture whose feature set is *ARCH_FSET. */
26943 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26944 const arm_feature_set
*needed
)
26946 int i
, nb_allowed_archs
;
26947 arm_feature_set ext_fset
;
26948 const struct arm_option_extension_value_table
*opt
;
26950 ext_fset
= arm_arch_none
;
26951 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26953 /* Extension does not provide any feature we need. */
26954 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26958 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26959 for (i
= 0; i
< nb_allowed_archs
; i
++)
26962 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26965 /* Extension is available, add it. */
26966 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26967 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26971 /* Can we enable all features in *needed? */
26972 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26975 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26976 a given architecture feature set *ARCH_EXT_FSET including extension feature
26977 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26978 - if true, check for an exact match of the architecture modulo extensions;
26979 - otherwise, select build attribute value of the first superset
26980 architecture released so that results remains stable when new architectures
26982 For -march/-mcpu=all the build attribute value of the most featureful
26983 architecture is returned. Tag_CPU_arch_profile result is returned in
26987 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26988 const arm_feature_set
*ext_fset
,
26989 char *profile
, int exact_match
)
26991 arm_feature_set arch_fset
;
26992 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26994 /* Select most featureful architecture with all its extensions if building
26995 for -march=all as the feature sets used to set build attributes. */
26996 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26998 /* Force revisiting of decision for each new architecture. */
26999 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
27001 return TAG_CPU_ARCH_V8
;
27004 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27006 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27008 arm_feature_set known_arch_fset
;
27010 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27013 /* Base architecture match user-specified architecture and
27014 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27015 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27020 /* Base architecture match user-specified architecture only
27021 (eg. ARMv6-M in the same case as above). Record it in case we
27022 find a match with above condition. */
27023 else if (p_ver_ret
== NULL
27024 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27030 /* Architecture has all features wanted. */
27031 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27033 arm_feature_set added_fset
;
27035 /* Compute features added by this architecture over the one
27036 recorded in p_ver_ret. */
27037 if (p_ver_ret
!= NULL
)
27038 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27040 /* First architecture that match incl. with extensions, or the
27041 only difference in features over the recorded match is
27042 features that were optional and are now mandatory. */
27043 if (p_ver_ret
== NULL
27044 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27050 else if (p_ver_ret
== NULL
)
27052 arm_feature_set needed_ext_fset
;
27054 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27056 /* Architecture has all features needed when using some
27057 extensions. Record it and continue searching in case there
27058 exist an architecture providing all needed features without
27059 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27061 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27068 if (p_ver_ret
== NULL
)
27072 /* Tag_CPU_arch_profile. */
27073 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27074 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27075 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27076 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27078 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27080 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27084 return p_ver_ret
->val
;
27087 /* Set the public EABI object attributes. */
27090 aeabi_set_public_attributes (void)
27095 int fp16_optional
= 0;
27096 int skip_exact_match
= 0;
27097 arm_feature_set flags
, flags_arch
, flags_ext
;
27099 /* Autodetection mode, choose the architecture based the instructions
27101 if (no_cpu_selected ())
27103 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27105 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27106 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27108 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27109 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27111 /* Code run during relaxation relies on selected_cpu being set. */
27112 selected_cpu
= flags
;
27114 /* Otherwise, choose the architecture based on the capabilities of the
27117 flags
= selected_cpu
;
27118 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
27120 /* Allow the user to override the reported architecture. */
27123 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
27124 flags_ext
= arm_arch_none
;
27128 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27129 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
27130 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27133 /* When this function is run again after relaxation has happened there is no
27134 way to determine whether an architecture or CPU was specified by the user:
27135 - selected_cpu is set above for relaxation to work;
27136 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27137 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27138 Therefore, if not in -march=all case we first try an exact match and fall
27139 back to autodetection. */
27140 if (!skip_exact_match
)
27141 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27143 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27145 as_bad (_("no architecture contains all the instructions used\n"));
27147 /* Tag_CPU_name. */
27148 if (selected_cpu_name
[0])
27152 q
= selected_cpu_name
;
27153 if (strncmp (q
, "armv", 4) == 0)
27158 for (i
= 0; q
[i
]; i
++)
27159 q
[i
] = TOUPPER (q
[i
]);
27161 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27164 /* Tag_CPU_arch. */
27165 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27167 /* Tag_CPU_arch_profile. */
27168 if (profile
!= '\0')
27169 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27171 /* Tag_DSP_extension. */
27172 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
27173 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27175 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27176 /* Tag_ARM_ISA_use. */
27177 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27178 || ARM_FEATURE_ZERO (flags_arch
))
27179 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27181 /* Tag_THUMB_ISA_use. */
27182 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27183 || ARM_FEATURE_ZERO (flags_arch
))
27187 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27188 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27190 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27194 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27197 /* Tag_VFP_arch. */
27198 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27199 aeabi_set_attribute_int (Tag_VFP_arch
,
27200 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27202 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27203 aeabi_set_attribute_int (Tag_VFP_arch
,
27204 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27206 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27209 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27211 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27213 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27216 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27217 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27218 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27219 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27220 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27222 /* Tag_ABI_HardFP_use. */
27223 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27224 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27225 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27227 /* Tag_WMMX_arch. */
27228 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27229 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27230 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27231 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27233 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27234 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27235 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27236 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27237 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27238 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27240 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27242 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27246 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27251 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27252 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27253 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27257 We set Tag_DIV_use to two when integer divide instructions have been used
27258 in ARM state, or when Thumb integer divide instructions have been used,
27259 but we have no architecture profile set, nor have we any ARM instructions.
27261 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27262 by the base architecture.
27264 For new architectures we will have to check these tests. */
27265 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27266 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27267 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27268 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27269 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27270 || (profile
== '\0'
27271 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27272 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27273 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27275 /* Tag_MP_extension_use. */
27276 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27277 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27279 /* Tag Virtualization_use. */
27280 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27282 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27285 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27288 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27289 finished and free extension feature bits which will not be used anymore. */
27292 arm_md_post_relax (void)
27294 aeabi_set_public_attributes ();
27295 XDELETE (dyn_mcpu_ext_opt
);
27296 dyn_mcpu_ext_opt
= NULL
;
27297 XDELETE (dyn_march_ext_opt
);
27298 dyn_march_ext_opt
= NULL
;
27301 /* Add the default contents for the .ARM.attributes section. */
27306 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27309 aeabi_set_public_attributes ();
27311 #endif /* OBJ_ELF */
27313 /* Parse a .cpu directive. */
27316 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27318 const struct arm_cpu_option_table
*opt
;
27322 name
= input_line_pointer
;
27323 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27324 input_line_pointer
++;
27325 saved_char
= *input_line_pointer
;
27326 *input_line_pointer
= 0;
27328 /* Skip the first "all" entry. */
27329 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27330 if (streq (opt
->name
, name
))
27332 mcpu_cpu_opt
= &opt
->value
;
27333 if (!dyn_mcpu_ext_opt
)
27334 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27335 *dyn_mcpu_ext_opt
= opt
->ext
;
27336 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27337 if (opt
->canonical_name
)
27338 strcpy (selected_cpu_name
, opt
->canonical_name
);
27342 for (i
= 0; opt
->name
[i
]; i
++)
27343 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27345 selected_cpu_name
[i
] = 0;
27347 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27348 if (dyn_mcpu_ext_opt
)
27349 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27350 *input_line_pointer
= saved_char
;
27351 demand_empty_rest_of_line ();
27354 as_bad (_("unknown cpu `%s'"), name
);
27355 *input_line_pointer
= saved_char
;
27356 ignore_rest_of_line ();
27359 /* Parse a .arch directive. */
27362 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27364 const struct arm_arch_option_table
*opt
;
27368 name
= input_line_pointer
;
27369 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27370 input_line_pointer
++;
27371 saved_char
= *input_line_pointer
;
27372 *input_line_pointer
= 0;
27374 /* Skip the first "all" entry. */
27375 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27376 if (streq (opt
->name
, name
))
27378 mcpu_cpu_opt
= &opt
->value
;
27379 XDELETE (dyn_mcpu_ext_opt
);
27380 dyn_mcpu_ext_opt
= NULL
;
27381 selected_cpu
= *mcpu_cpu_opt
;
27382 strcpy (selected_cpu_name
, opt
->name
);
27383 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27384 *input_line_pointer
= saved_char
;
27385 demand_empty_rest_of_line ();
27389 as_bad (_("unknown architecture `%s'\n"), name
);
27390 *input_line_pointer
= saved_char
;
27391 ignore_rest_of_line ();
27394 /* Parse a .object_arch directive. */
27397 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27399 const struct arm_arch_option_table
*opt
;
27403 name
= input_line_pointer
;
27404 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27405 input_line_pointer
++;
27406 saved_char
= *input_line_pointer
;
27407 *input_line_pointer
= 0;
27409 /* Skip the first "all" entry. */
27410 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27411 if (streq (opt
->name
, name
))
27413 object_arch
= &opt
->value
;
27414 *input_line_pointer
= saved_char
;
27415 demand_empty_rest_of_line ();
27419 as_bad (_("unknown architecture `%s'\n"), name
);
27420 *input_line_pointer
= saved_char
;
27421 ignore_rest_of_line ();
27424 /* Parse a .arch_extension directive. */
27427 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27429 const struct arm_option_extension_value_table
*opt
;
27430 const arm_feature_set arm_any
= ARM_ANY
;
27433 int adding_value
= 1;
27435 name
= input_line_pointer
;
27436 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27437 input_line_pointer
++;
27438 saved_char
= *input_line_pointer
;
27439 *input_line_pointer
= 0;
27441 if (strlen (name
) >= 2
27442 && strncmp (name
, "no", 2) == 0)
27448 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27449 if (streq (opt
->name
, name
))
27451 int i
, nb_allowed_archs
=
27452 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27453 for (i
= 0; i
< nb_allowed_archs
; i
++)
27456 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27458 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27462 if (i
== nb_allowed_archs
)
27464 as_bad (_("architectural extension `%s' is not allowed for the "
27465 "current base architecture"), name
);
27469 if (!dyn_mcpu_ext_opt
)
27471 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27472 *dyn_mcpu_ext_opt
= arm_arch_none
;
27475 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27478 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27481 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27482 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27483 *input_line_pointer
= saved_char
;
27484 demand_empty_rest_of_line ();
27485 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27486 on this return so that duplicate extensions (extensions with the
27487 same name as a previous extension in the list) are not considered
27488 for command-line parsing. */
27492 if (opt
->name
== NULL
)
27493 as_bad (_("unknown architecture extension `%s'\n"), name
);
27495 *input_line_pointer
= saved_char
;
27496 ignore_rest_of_line ();
27499 /* Parse a .fpu directive. */
27502 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27504 const struct arm_option_fpu_value_table
*opt
;
27508 name
= input_line_pointer
;
27509 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27510 input_line_pointer
++;
27511 saved_char
= *input_line_pointer
;
27512 *input_line_pointer
= 0;
27514 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27515 if (streq (opt
->name
, name
))
27517 mfpu_opt
= &opt
->value
;
27518 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27519 if (dyn_mcpu_ext_opt
)
27520 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27521 *input_line_pointer
= saved_char
;
27522 demand_empty_rest_of_line ();
27526 as_bad (_("unknown floating point format `%s'\n"), name
);
27527 *input_line_pointer
= saved_char
;
27528 ignore_rest_of_line ();
27531 /* Copy symbol information. */
27534 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27536 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27540 /* Given a symbolic attribute NAME, return the proper integer value.
27541 Returns -1 if the attribute is not known. */
27544 arm_convert_symbolic_attribute (const char *name
)
27546 static const struct
27551 attribute_table
[] =
27553 /* When you modify this table you should
27554 also modify the list in doc/c-arm.texi. */
27555 #define T(tag) {#tag, tag}
27556 T (Tag_CPU_raw_name
),
27559 T (Tag_CPU_arch_profile
),
27560 T (Tag_ARM_ISA_use
),
27561 T (Tag_THUMB_ISA_use
),
27565 T (Tag_Advanced_SIMD_arch
),
27566 T (Tag_PCS_config
),
27567 T (Tag_ABI_PCS_R9_use
),
27568 T (Tag_ABI_PCS_RW_data
),
27569 T (Tag_ABI_PCS_RO_data
),
27570 T (Tag_ABI_PCS_GOT_use
),
27571 T (Tag_ABI_PCS_wchar_t
),
27572 T (Tag_ABI_FP_rounding
),
27573 T (Tag_ABI_FP_denormal
),
27574 T (Tag_ABI_FP_exceptions
),
27575 T (Tag_ABI_FP_user_exceptions
),
27576 T (Tag_ABI_FP_number_model
),
27577 T (Tag_ABI_align_needed
),
27578 T (Tag_ABI_align8_needed
),
27579 T (Tag_ABI_align_preserved
),
27580 T (Tag_ABI_align8_preserved
),
27581 T (Tag_ABI_enum_size
),
27582 T (Tag_ABI_HardFP_use
),
27583 T (Tag_ABI_VFP_args
),
27584 T (Tag_ABI_WMMX_args
),
27585 T (Tag_ABI_optimization_goals
),
27586 T (Tag_ABI_FP_optimization_goals
),
27587 T (Tag_compatibility
),
27588 T (Tag_CPU_unaligned_access
),
27589 T (Tag_FP_HP_extension
),
27590 T (Tag_VFP_HP_extension
),
27591 T (Tag_ABI_FP_16bit_format
),
27592 T (Tag_MPextension_use
),
27594 T (Tag_nodefaults
),
27595 T (Tag_also_compatible_with
),
27596 T (Tag_conformance
),
27598 T (Tag_Virtualization_use
),
27599 T (Tag_DSP_extension
),
27600 /* We deliberately do not include Tag_MPextension_use_legacy. */
27608 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27609 if (streq (name
, attribute_table
[i
].name
))
27610 return attribute_table
[i
].tag
;
27615 /* Apply sym value for relocations only in the case that they are for
27616 local symbols in the same segment as the fixup and you have the
27617 respective architectural feature for blx and simple switches. */
27620 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27623 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27624 /* PR 17444: If the local symbol is in a different section then a reloc
27625 will always be generated for it, so applying the symbol value now
27626 will result in a double offset being stored in the relocation. */
27627 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27628 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27630 switch (fixP
->fx_r_type
)
27632 case BFD_RELOC_ARM_PCREL_BLX
:
27633 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27634 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27638 case BFD_RELOC_ARM_PCREL_CALL
:
27639 case BFD_RELOC_THUMB_PCREL_BLX
:
27640 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27651 #endif /* OBJ_ELF */