1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR
, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR
, /* ARM LR register */
6930 OP_RRe
, /* ARM register, only even numbered. */
6931 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST
, /* ARM register list */
6935 OP_CLRMLST
, /* CLRM register list */
6936 OP_VRSLST
, /* VFP single-precision register list */
6937 OP_VRDLST
, /* VFP double-precision register list */
6938 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST
, /* Neon element/structure list */
6941 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2
, /* MVE vector list with two elements. */
6943 OP_MSTRLST4
, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV
, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6970 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6971 OP_VLDR
, /* VLDR operand. */
6973 OP_I0
, /* immediate zero */
6974 OP_I7
, /* immediate value 0 .. 7 */
6975 OP_I15
, /* 0 .. 15 */
6976 OP_I16
, /* 1 .. 16 */
6977 OP_I16z
, /* 0 .. 16 */
6978 OP_I31
, /* 0 .. 31 */
6979 OP_I31w
, /* 0 .. 31, optional trailing ! */
6980 OP_I32
, /* 1 .. 32 */
6981 OP_I32z
, /* 0 .. 32 */
6982 OP_I63
, /* 0 .. 63 */
6983 OP_I63s
, /* -64 .. 63 */
6984 OP_I64
, /* 1 .. 64 */
6985 OP_I64z
, /* 0 .. 64 */
6986 OP_I255
, /* 0 .. 255 */
6988 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6989 OP_I7b
, /* 0 .. 7 */
6990 OP_I15b
, /* 0 .. 15 */
6991 OP_I31b
, /* 0 .. 31 */
6993 OP_SH
, /* shifter operand */
6994 OP_SHG
, /* shifter operand with possible group relocation */
6995 OP_ADDR
, /* Memory address expression (any mode) */
6996 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6997 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6998 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6999 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7000 OP_EXP
, /* arbitrary expression */
7001 OP_EXPi
, /* same, with optional immediate prefix */
7002 OP_EXPr
, /* same, with optional relocation suffix */
7003 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7004 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7005 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7006 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7008 OP_CPSF
, /* CPS flags */
7009 OP_ENDI
, /* Endianness specifier */
7010 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7011 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7012 OP_COND
, /* conditional code */
7013 OP_TB
, /* Table branch. */
7015 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7017 OP_RRnpc_I0
, /* ARM register or literal 0 */
7018 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7019 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7020 OP_RF_IF
, /* FPA register or immediate */
7021 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7022 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7024 /* Optional operands. */
7025 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7026 OP_oI31b
, /* 0 .. 31 */
7027 OP_oI32b
, /* 1 .. 32 */
7028 OP_oI32z
, /* 0 .. 32 */
7029 OP_oIffffb
, /* 0 .. 65535 */
7030 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7032 OP_oRR
, /* ARM register */
7033 OP_oLR
, /* ARM LR register */
7034 OP_oRRnpc
, /* ARM register, not the PC */
7035 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7036 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7037 OP_oRND
, /* Optional Neon double precision register */
7038 OP_oRNQ
, /* Optional Neon quad precision register */
7039 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7040 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7041 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7042 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7044 OP_oSHll
, /* LSL immediate */
7045 OP_oSHar
, /* ASR immediate */
7046 OP_oSHllar
, /* LSL or ASR immediate */
7047 OP_oROR
, /* ROR 0/8/16/24 */
7048 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7050 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7052 /* Some pre-defined mixed (ARM/THUMB) operands. */
7053 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7054 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7055 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7057 OP_FIRST_OPTIONAL
= OP_oI7b
7060 /* Generic instruction operand parser. This does no encoding and no
7061 semantic validation; it merely squirrels values away in the inst
7062 structure. Returns SUCCESS or FAIL depending on whether the
7063 specified grammar matched. */
7065 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7067 unsigned const int *upat
= pattern
;
7068 char *backtrack_pos
= 0;
7069 const char *backtrack_error
= 0;
7070 int i
, val
= 0, backtrack_index
= 0;
7071 enum arm_reg_type rtype
;
7072 parse_operand_result result
;
7073 unsigned int op_parse_code
;
7074 bfd_boolean partial_match
;
7076 #define po_char_or_fail(chr) \
7079 if (skip_past_char (&str, chr) == FAIL) \
7084 #define po_reg_or_fail(regtype) \
7087 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7088 & inst.operands[i].vectype); \
7091 first_error (_(reg_expected_msgs[regtype])); \
7094 inst.operands[i].reg = val; \
7095 inst.operands[i].isreg = 1; \
7096 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7097 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7098 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7099 || rtype == REG_TYPE_VFD \
7100 || rtype == REG_TYPE_NQ); \
7101 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7105 #define po_reg_or_goto(regtype, label) \
7108 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7109 & inst.operands[i].vectype); \
7113 inst.operands[i].reg = val; \
7114 inst.operands[i].isreg = 1; \
7115 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7116 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7117 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7118 || rtype == REG_TYPE_VFD \
7119 || rtype == REG_TYPE_NQ); \
7120 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7124 #define po_imm_or_fail(min, max, popt) \
7127 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7129 inst.operands[i].imm = val; \
7133 #define po_scalar_or_goto(elsz, label, reg_type) \
7136 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7140 inst.operands[i].reg = val; \
7141 inst.operands[i].isscalar = 1; \
7145 #define po_misc_or_fail(expr) \
7153 #define po_misc_or_fail_no_backtrack(expr) \
7157 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7158 backtrack_pos = 0; \
7159 if (result != PARSE_OPERAND_SUCCESS) \
7164 #define po_barrier_or_imm(str) \
7167 val = parse_barrier (&str); \
7168 if (val == FAIL && ! ISALPHA (*str)) \
7171 /* ISB can only take SY as an option. */ \
7172 || ((inst.instruction & 0xf0) == 0x60 \
7175 inst.error = _("invalid barrier type"); \
7176 backtrack_pos = 0; \
7182 skip_whitespace (str
);
7184 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7186 op_parse_code
= upat
[i
];
7187 if (op_parse_code
>= 1<<16)
7188 op_parse_code
= thumb
? (op_parse_code
>> 16)
7189 : (op_parse_code
& ((1<<16)-1));
7191 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7193 /* Remember where we are in case we need to backtrack. */
7194 backtrack_pos
= str
;
7195 backtrack_error
= inst
.error
;
7196 backtrack_index
= i
;
7199 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7200 po_char_or_fail (',');
7202 switch (op_parse_code
)
7214 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7215 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7216 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7217 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7218 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7219 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7222 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7226 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7229 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7231 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7233 /* Also accept generic coprocessor regs for unknown registers. */
7235 po_reg_or_fail (REG_TYPE_CN
);
7237 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7238 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7239 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7240 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7241 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7242 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7243 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7244 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7245 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7246 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7249 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7252 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7253 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7255 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7260 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7264 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7266 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7269 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7271 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7274 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7276 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7281 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7284 po_reg_or_fail (REG_TYPE_NSDQ
);
7288 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7292 po_reg_or_fail (REG_TYPE_MQ
);
7294 /* Neon scalar. Using an element size of 8 means that some invalid
7295 scalars are accepted here, so deal with those in later code. */
7296 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7300 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7303 po_imm_or_fail (0, 0, TRUE
);
7308 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7312 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7317 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7320 if (parse_ifimm_zero (&str
))
7321 inst
.operands
[i
].imm
= 0;
7325 = _("only floating point zero is allowed as immediate value");
7333 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7336 po_reg_or_fail (REG_TYPE_RN
);
7340 case OP_RNSDQ_RNSC_MQ_RR
:
7341 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7344 case OP_RNSDQ_RNSC_MQ
:
7345 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7350 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7354 po_reg_or_fail (REG_TYPE_NSDQ
);
7361 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7364 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7367 po_reg_or_fail (REG_TYPE_NSD
);
7371 case OP_RNDQMQ_RNSC_RR
:
7372 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7375 case OP_RNDQ_RNSC_RR
:
7376 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7378 case OP_RNDQMQ_RNSC
:
7379 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7384 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7387 po_reg_or_fail (REG_TYPE_NDQ
);
7393 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7396 po_reg_or_fail (REG_TYPE_VFD
);
7401 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7402 not careful then bad things might happen. */
7403 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7406 case OP_RNDQMQ_Ibig
:
7407 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7412 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7415 /* There's a possibility of getting a 64-bit immediate here, so
7416 we need special handling. */
7417 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7420 inst
.error
= _("immediate value is out of range");
7426 case OP_RNDQMQ_I63b_RR
:
7427 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7430 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7435 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7438 po_imm_or_fail (0, 63, TRUE
);
7443 po_char_or_fail ('[');
7444 po_reg_or_fail (REG_TYPE_RN
);
7445 po_char_or_fail (']');
7451 po_reg_or_fail (REG_TYPE_RN
);
7452 if (skip_past_char (&str
, '!') == SUCCESS
)
7453 inst
.operands
[i
].writeback
= 1;
7457 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7458 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7459 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7460 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7461 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7462 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7463 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7464 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7465 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7466 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7467 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7468 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7470 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7472 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7473 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7475 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7476 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7477 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7478 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7480 /* Immediate variants */
7482 po_char_or_fail ('{');
7483 po_imm_or_fail (0, 255, TRUE
);
7484 po_char_or_fail ('}');
7488 /* The expression parser chokes on a trailing !, so we have
7489 to find it first and zap it. */
7492 while (*s
&& *s
!= ',')
7497 inst
.operands
[i
].writeback
= 1;
7499 po_imm_or_fail (0, 31, TRUE
);
7507 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7512 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7517 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7519 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7521 val
= parse_reloc (&str
);
7524 inst
.error
= _("unrecognized relocation suffix");
7527 else if (val
!= BFD_RELOC_UNUSED
)
7529 inst
.operands
[i
].imm
= val
;
7530 inst
.operands
[i
].hasreloc
= 1;
7536 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7538 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7540 inst
.operands
[i
].hasreloc
= 1;
7542 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7544 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7545 inst
.operands
[i
].hasreloc
= 0;
7549 /* Operand for MOVW or MOVT. */
7551 po_misc_or_fail (parse_half (&str
));
7554 /* Register or expression. */
7555 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7556 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7558 /* Register or immediate. */
7559 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7560 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7562 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7563 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7565 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7567 if (!is_immediate_prefix (*str
))
7570 val
= parse_fpa_immediate (&str
);
7573 /* FPA immediates are encoded as registers 8-15.
7574 parse_fpa_immediate has already applied the offset. */
7575 inst
.operands
[i
].reg
= val
;
7576 inst
.operands
[i
].isreg
= 1;
7579 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7580 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7582 /* Two kinds of register. */
7585 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7587 || (rege
->type
!= REG_TYPE_MMXWR
7588 && rege
->type
!= REG_TYPE_MMXWC
7589 && rege
->type
!= REG_TYPE_MMXWCG
))
7591 inst
.error
= _("iWMMXt data or control register expected");
7594 inst
.operands
[i
].reg
= rege
->number
;
7595 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7601 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7603 || (rege
->type
!= REG_TYPE_MMXWC
7604 && rege
->type
!= REG_TYPE_MMXWCG
))
7606 inst
.error
= _("iWMMXt control register expected");
7609 inst
.operands
[i
].reg
= rege
->number
;
7610 inst
.operands
[i
].isreg
= 1;
7615 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7616 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7617 case OP_oROR
: val
= parse_ror (&str
); break;
7619 case OP_COND
: val
= parse_cond (&str
); break;
7620 case OP_oBARRIER_I15
:
7621 po_barrier_or_imm (str
); break;
7623 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7629 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7630 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7632 inst
.error
= _("Banked registers are not available with this "
7638 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7642 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7645 val
= parse_sys_vldr_vstr (&str
);
7649 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7652 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7654 if (strncasecmp (str
, "APSR_", 5) == 0)
7661 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7662 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7663 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7664 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7665 default: found
= 16;
7669 inst
.operands
[i
].isvec
= 1;
7670 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7671 inst
.operands
[i
].reg
= REG_PC
;
7678 po_misc_or_fail (parse_tb (&str
));
7681 /* Register lists. */
7683 val
= parse_reg_list (&str
, REGLIST_RN
);
7686 inst
.operands
[i
].writeback
= 1;
7692 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7696 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7701 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7706 /* Allow Q registers too. */
7707 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7708 REGLIST_NEON_D
, &partial_match
);
7712 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7713 REGLIST_VFP_S
, &partial_match
);
7714 inst
.operands
[i
].issingle
= 1;
7719 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7720 REGLIST_VFP_D_VPR
, &partial_match
);
7721 if (val
== FAIL
&& !partial_match
)
7724 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7725 REGLIST_VFP_S_VPR
, &partial_match
);
7726 inst
.operands
[i
].issingle
= 1;
7731 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7732 REGLIST_NEON_D
, &partial_match
);
7737 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7738 1, &inst
.operands
[i
].vectype
);
7739 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7743 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7744 0, &inst
.operands
[i
].vectype
);
7747 /* Addressing modes */
7749 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7753 po_misc_or_fail (parse_address (&str
, i
));
7757 po_misc_or_fail_no_backtrack (
7758 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7762 po_misc_or_fail_no_backtrack (
7763 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7767 po_misc_or_fail_no_backtrack (
7768 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7772 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7776 po_misc_or_fail_no_backtrack (
7777 parse_shifter_operand_group_reloc (&str
, i
));
7781 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7785 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7789 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7794 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7797 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7800 po_reg_or_fail (REG_TYPE_ZR
);
7804 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7807 /* Various value-based sanity checks and shared operations. We
7808 do not signal immediate failures for the register constraints;
7809 this allows a syntax error to take precedence. */
7810 switch (op_parse_code
)
7818 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7819 inst
.error
= BAD_PC
;
7824 case OP_RRnpcsp_I32
:
7825 if (inst
.operands
[i
].isreg
)
7827 if (inst
.operands
[i
].reg
== REG_PC
)
7828 inst
.error
= BAD_PC
;
7829 else if (inst
.operands
[i
].reg
== REG_SP
7830 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7831 relaxed since ARMv8-A. */
7832 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7835 inst
.error
= BAD_SP
;
7841 if (inst
.operands
[i
].isreg
7842 && inst
.operands
[i
].reg
== REG_PC
7843 && (inst
.operands
[i
].writeback
|| thumb
))
7844 inst
.error
= BAD_PC
;
7849 if (inst
.operands
[i
].isreg
)
7859 case OP_oBARRIER_I15
:
7872 inst
.operands
[i
].imm
= val
;
7877 if (inst
.operands
[i
].reg
!= REG_LR
)
7878 inst
.error
= _("operand must be LR register");
7883 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7884 inst
.error
= BAD_PC
;
7888 if (inst
.operands
[i
].isreg
7889 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7890 inst
.error
= BAD_ODD
;
7894 if (inst
.operands
[i
].isreg
)
7896 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7897 inst
.error
= BAD_EVEN
;
7898 else if (inst
.operands
[i
].reg
== REG_SP
)
7899 as_tsktsk (MVE_BAD_SP
);
7900 else if (inst
.operands
[i
].reg
== REG_PC
)
7901 inst
.error
= BAD_PC
;
7909 /* If we get here, this operand was successfully parsed. */
7910 inst
.operands
[i
].present
= 1;
7914 inst
.error
= BAD_ARGS
;
7919 /* The parse routine should already have set inst.error, but set a
7920 default here just in case. */
7922 inst
.error
= BAD_SYNTAX
;
7926 /* Do not backtrack over a trailing optional argument that
7927 absorbed some text. We will only fail again, with the
7928 'garbage following instruction' error message, which is
7929 probably less helpful than the current one. */
7930 if (backtrack_index
== i
&& backtrack_pos
!= str
7931 && upat
[i
+1] == OP_stop
)
7934 inst
.error
= BAD_SYNTAX
;
7938 /* Try again, skipping the optional argument at backtrack_pos. */
7939 str
= backtrack_pos
;
7940 inst
.error
= backtrack_error
;
7941 inst
.operands
[backtrack_index
].present
= 0;
7942 i
= backtrack_index
;
7946 /* Check that we have parsed all the arguments. */
7947 if (*str
!= '\0' && !inst
.error
)
7948 inst
.error
= _("garbage following instruction");
7950 return inst
.error
? FAIL
: SUCCESS
;
7953 #undef po_char_or_fail
7954 #undef po_reg_or_fail
7955 #undef po_reg_or_goto
7956 #undef po_imm_or_fail
7957 #undef po_scalar_or_fail
7958 #undef po_barrier_or_imm
7960 /* Shorthand macro for instruction encoding functions issuing errors. */
7961 #define constraint(expr, err) \
7972 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7973 instructions are unpredictable if these registers are used. This
7974 is the BadReg predicate in ARM's Thumb-2 documentation.
7976 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7977 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7978 #define reject_bad_reg(reg) \
7980 if (reg == REG_PC) \
7982 inst.error = BAD_PC; \
7985 else if (reg == REG_SP \
7986 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7988 inst.error = BAD_SP; \
7993 /* If REG is R13 (the stack pointer), warn that its use is
7995 #define warn_deprecated_sp(reg) \
7997 if (warn_on_deprecated && reg == REG_SP) \
7998 as_tsktsk (_("use of r13 is deprecated")); \
8001 /* Functions for operand encoding. ARM, then Thumb. */
8003 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8005 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8007 The only binary encoding difference is the Coprocessor number. Coprocessor
8008 9 is used for half-precision calculations or conversions. The format of the
8009 instruction is the same as the equivalent Coprocessor 10 instruction that
8010 exists for Single-Precision operation. */
8013 do_scalar_fp16_v82_encode (void)
8015 if (inst
.cond
< COND_ALWAYS
)
8016 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8017 " the behaviour is UNPREDICTABLE"));
8018 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8021 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8022 mark_feature_used (&arm_ext_fp16
);
8025 /* If VAL can be encoded in the immediate field of an ARM instruction,
8026 return the encoded form. Otherwise, return FAIL. */
8029 encode_arm_immediate (unsigned int val
)
8036 for (i
= 2; i
< 32; i
+= 2)
8037 if ((a
= rotate_left (val
, i
)) <= 0xff)
8038 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8043 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8044 return the encoded form. Otherwise, return FAIL. */
8046 encode_thumb32_immediate (unsigned int val
)
8053 for (i
= 1; i
<= 24; i
++)
8056 if ((val
& ~(0xff << i
)) == 0)
8057 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8061 if (val
== ((a
<< 16) | a
))
8063 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8067 if (val
== ((a
<< 16) | a
))
8068 return 0x200 | (a
>> 8);
8072 /* Encode a VFP SP or DP register number into inst.instruction. */
8075 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8077 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8080 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8083 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8086 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8091 first_error (_("D register out of range for selected VFP version"));
8099 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8103 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8107 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8111 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8115 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8119 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8127 /* Encode a <shift> in an ARM-format instruction. The immediate,
8128 if any, is handled by md_apply_fix. */
8130 encode_arm_shift (int i
)
8132 /* register-shifted register. */
8133 if (inst
.operands
[i
].immisreg
)
8136 for (op_index
= 0; op_index
<= i
; ++op_index
)
8138 /* Check the operand only when it's presented. In pre-UAL syntax,
8139 if the destination register is the same as the first operand, two
8140 register form of the instruction can be used. */
8141 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8142 && inst
.operands
[op_index
].reg
== REG_PC
)
8143 as_warn (UNPRED_REG ("r15"));
8146 if (inst
.operands
[i
].imm
== REG_PC
)
8147 as_warn (UNPRED_REG ("r15"));
8150 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8151 inst
.instruction
|= SHIFT_ROR
<< 5;
8154 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8155 if (inst
.operands
[i
].immisreg
)
8157 inst
.instruction
|= SHIFT_BY_REG
;
8158 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8161 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8166 encode_arm_shifter_operand (int i
)
8168 if (inst
.operands
[i
].isreg
)
8170 inst
.instruction
|= inst
.operands
[i
].reg
;
8171 encode_arm_shift (i
);
8175 inst
.instruction
|= INST_IMMEDIATE
;
8176 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8177 inst
.instruction
|= inst
.operands
[i
].imm
;
8181 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8183 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8186 Generate an error if the operand is not a register. */
8187 constraint (!inst
.operands
[i
].isreg
,
8188 _("Instruction does not support =N addresses"));
8190 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8192 if (inst
.operands
[i
].preind
)
8196 inst
.error
= _("instruction does not accept preindexed addressing");
8199 inst
.instruction
|= PRE_INDEX
;
8200 if (inst
.operands
[i
].writeback
)
8201 inst
.instruction
|= WRITE_BACK
;
8204 else if (inst
.operands
[i
].postind
)
8206 gas_assert (inst
.operands
[i
].writeback
);
8208 inst
.instruction
|= WRITE_BACK
;
8210 else /* unindexed - only for coprocessor */
8212 inst
.error
= _("instruction does not accept unindexed addressing");
8216 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8217 && (((inst
.instruction
& 0x000f0000) >> 16)
8218 == ((inst
.instruction
& 0x0000f000) >> 12)))
8219 as_warn ((inst
.instruction
& LOAD_BIT
)
8220 ? _("destination register same as write-back base")
8221 : _("source register same as write-back base"));
8224 /* inst.operands[i] was set up by parse_address. Encode it into an
8225 ARM-format mode 2 load or store instruction. If is_t is true,
8226 reject forms that cannot be used with a T instruction (i.e. not
8229 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8231 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8233 encode_arm_addr_mode_common (i
, is_t
);
8235 if (inst
.operands
[i
].immisreg
)
8237 constraint ((inst
.operands
[i
].imm
== REG_PC
8238 || (is_pc
&& inst
.operands
[i
].writeback
)),
8240 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8241 inst
.instruction
|= inst
.operands
[i
].imm
;
8242 if (!inst
.operands
[i
].negative
)
8243 inst
.instruction
|= INDEX_UP
;
8244 if (inst
.operands
[i
].shifted
)
8246 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8247 inst
.instruction
|= SHIFT_ROR
<< 5;
8250 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8251 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8255 else /* immediate offset in inst.relocs[0] */
8257 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8259 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8261 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8262 cannot use PC in addressing.
8263 PC cannot be used in writeback addressing, either. */
8264 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8267 /* Use of PC in str is deprecated for ARMv7. */
8268 if (warn_on_deprecated
8270 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8271 as_tsktsk (_("use of PC in this instruction is deprecated"));
8274 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8276 /* Prefer + for zero encoded value. */
8277 if (!inst
.operands
[i
].negative
)
8278 inst
.instruction
|= INDEX_UP
;
8279 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8284 /* inst.operands[i] was set up by parse_address. Encode it into an
8285 ARM-format mode 3 load or store instruction. Reject forms that
8286 cannot be used with such instructions. If is_t is true, reject
8287 forms that cannot be used with a T instruction (i.e. not
8290 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8292 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8294 inst
.error
= _("instruction does not accept scaled register index");
8298 encode_arm_addr_mode_common (i
, is_t
);
8300 if (inst
.operands
[i
].immisreg
)
8302 constraint ((inst
.operands
[i
].imm
== REG_PC
8303 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8305 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8307 inst
.instruction
|= inst
.operands
[i
].imm
;
8308 if (!inst
.operands
[i
].negative
)
8309 inst
.instruction
|= INDEX_UP
;
8311 else /* immediate offset in inst.relocs[0] */
8313 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8314 && inst
.operands
[i
].writeback
),
8316 inst
.instruction
|= HWOFFSET_IMM
;
8317 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8319 /* Prefer + for zero encoded value. */
8320 if (!inst
.operands
[i
].negative
)
8321 inst
.instruction
|= INDEX_UP
;
8323 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8328 /* Write immediate bits [7:0] to the following locations:
8330 |28/24|23 19|18 16|15 4|3 0|
8331 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8333 This function is used by VMOV/VMVN/VORR/VBIC. */
8336 neon_write_immbits (unsigned immbits
)
8338 inst
.instruction
|= immbits
& 0xf;
8339 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8340 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8343 /* Invert low-order SIZE bits of XHI:XLO. */
8346 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8348 unsigned immlo
= xlo
? *xlo
: 0;
8349 unsigned immhi
= xhi
? *xhi
: 0;
8354 immlo
= (~immlo
) & 0xff;
8358 immlo
= (~immlo
) & 0xffff;
8362 immhi
= (~immhi
) & 0xffffffff;
8366 immlo
= (~immlo
) & 0xffffffff;
8380 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8384 neon_bits_same_in_bytes (unsigned imm
)
8386 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8387 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8388 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8389 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8392 /* For immediate of above form, return 0bABCD. */
8395 neon_squash_bits (unsigned imm
)
8397 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8398 | ((imm
& 0x01000000) >> 21);
8401 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8404 neon_qfloat_bits (unsigned imm
)
8406 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8409 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8410 the instruction. *OP is passed as the initial value of the op field, and
8411 may be set to a different value depending on the constant (i.e.
8412 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8413 MVN). If the immediate looks like a repeated pattern then also
8414 try smaller element sizes. */
8417 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8418 unsigned *immbits
, int *op
, int size
,
8419 enum neon_el_type type
)
8421 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8423 if (type
== NT_float
&& !float_p
)
8426 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8428 if (size
!= 32 || *op
== 1)
8430 *immbits
= neon_qfloat_bits (immlo
);
8436 if (neon_bits_same_in_bytes (immhi
)
8437 && neon_bits_same_in_bytes (immlo
))
8441 *immbits
= (neon_squash_bits (immhi
) << 4)
8442 | neon_squash_bits (immlo
);
8453 if (immlo
== (immlo
& 0x000000ff))
8458 else if (immlo
== (immlo
& 0x0000ff00))
8460 *immbits
= immlo
>> 8;
8463 else if (immlo
== (immlo
& 0x00ff0000))
8465 *immbits
= immlo
>> 16;
8468 else if (immlo
== (immlo
& 0xff000000))
8470 *immbits
= immlo
>> 24;
8473 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8475 *immbits
= (immlo
>> 8) & 0xff;
8478 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8480 *immbits
= (immlo
>> 16) & 0xff;
8484 if ((immlo
& 0xffff) != (immlo
>> 16))
8491 if (immlo
== (immlo
& 0x000000ff))
8496 else if (immlo
== (immlo
& 0x0000ff00))
8498 *immbits
= immlo
>> 8;
8502 if ((immlo
& 0xff) != (immlo
>> 8))
8507 if (immlo
== (immlo
& 0x000000ff))
8509 /* Don't allow MVN with 8-bit immediate. */
8519 #if defined BFD_HOST_64_BIT
8520 /* Returns TRUE if double precision value V may be cast
8521 to single precision without loss of accuracy. */
8524 is_double_a_single (bfd_int64_t v
)
8526 int exp
= (int)((v
>> 52) & 0x7FF);
8527 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8529 return (exp
== 0 || exp
== 0x7FF
8530 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8531 && (mantissa
& 0x1FFFFFFFl
) == 0;
8534 /* Returns a double precision value casted to single precision
8535 (ignoring the least significant bits in exponent and mantissa). */
8538 double_to_single (bfd_int64_t v
)
8540 int sign
= (int) ((v
>> 63) & 1l);
8541 int exp
= (int) ((v
>> 52) & 0x7FF);
8542 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8548 exp
= exp
- 1023 + 127;
8557 /* No denormalized numbers. */
8563 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8565 #endif /* BFD_HOST_64_BIT */
8574 static void do_vfp_nsyn_opcode (const char *);
8576 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8577 Determine whether it can be performed with a move instruction; if
8578 it can, convert inst.instruction to that move instruction and
8579 return TRUE; if it can't, convert inst.instruction to a literal-pool
8580 load and return FALSE. If this is not a valid thing to do in the
8581 current context, set inst.error and return TRUE.
8583 inst.operands[i] describes the destination register. */
8586 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8589 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8590 bfd_boolean arm_p
= (t
== CONST_ARM
);
8593 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8597 if ((inst
.instruction
& tbit
) == 0)
8599 inst
.error
= _("invalid pseudo operation");
8603 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8604 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8605 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8607 inst
.error
= _("constant expression expected");
8611 if (inst
.relocs
[0].exp
.X_op
== O_constant
8612 || inst
.relocs
[0].exp
.X_op
== O_big
)
8614 #if defined BFD_HOST_64_BIT
8619 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8621 LITTLENUM_TYPE w
[X_PRECISION
];
8624 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8626 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8628 /* FIXME: Should we check words w[2..5] ? */
8633 #if defined BFD_HOST_64_BIT
8635 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8636 << LITTLENUM_NUMBER_OF_BITS
)
8637 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8638 << LITTLENUM_NUMBER_OF_BITS
)
8639 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8640 << LITTLENUM_NUMBER_OF_BITS
)
8641 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8643 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8644 | (l
[0] & LITTLENUM_MASK
);
8648 v
= inst
.relocs
[0].exp
.X_add_number
;
8650 if (!inst
.operands
[i
].issingle
)
8654 /* LDR should not use lead in a flag-setting instruction being
8655 chosen so we do not check whether movs can be used. */
8657 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8658 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8659 && inst
.operands
[i
].reg
!= 13
8660 && inst
.operands
[i
].reg
!= 15)
8662 /* Check if on thumb2 it can be done with a mov.w, mvn or
8663 movw instruction. */
8664 unsigned int newimm
;
8665 bfd_boolean isNegated
;
8667 newimm
= encode_thumb32_immediate (v
);
8668 if (newimm
!= (unsigned int) FAIL
)
8672 newimm
= encode_thumb32_immediate (~v
);
8673 if (newimm
!= (unsigned int) FAIL
)
8677 /* The number can be loaded with a mov.w or mvn
8679 if (newimm
!= (unsigned int) FAIL
8680 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8682 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8683 | (inst
.operands
[i
].reg
<< 8));
8684 /* Change to MOVN. */
8685 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8686 inst
.instruction
|= (newimm
& 0x800) << 15;
8687 inst
.instruction
|= (newimm
& 0x700) << 4;
8688 inst
.instruction
|= (newimm
& 0x0ff);
8691 /* The number can be loaded with a movw instruction. */
8692 else if ((v
& ~0xFFFF) == 0
8693 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8695 int imm
= v
& 0xFFFF;
8697 inst
.instruction
= 0xf2400000; /* MOVW. */
8698 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8699 inst
.instruction
|= (imm
& 0xf000) << 4;
8700 inst
.instruction
|= (imm
& 0x0800) << 15;
8701 inst
.instruction
|= (imm
& 0x0700) << 4;
8702 inst
.instruction
|= (imm
& 0x00ff);
8703 /* In case this replacement is being done on Armv8-M
8704 Baseline we need to make sure to disable the
8705 instruction size check, as otherwise GAS will reject
8706 the use of this T32 instruction. */
8714 int value
= encode_arm_immediate (v
);
8718 /* This can be done with a mov instruction. */
8719 inst
.instruction
&= LITERAL_MASK
;
8720 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8721 inst
.instruction
|= value
& 0xfff;
8725 value
= encode_arm_immediate (~ v
);
8728 /* This can be done with a mvn instruction. */
8729 inst
.instruction
&= LITERAL_MASK
;
8730 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8731 inst
.instruction
|= value
& 0xfff;
8735 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8738 unsigned immbits
= 0;
8739 unsigned immlo
= inst
.operands
[1].imm
;
8740 unsigned immhi
= inst
.operands
[1].regisimm
8741 ? inst
.operands
[1].reg
8742 : inst
.relocs
[0].exp
.X_unsigned
8744 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8745 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8746 &op
, 64, NT_invtype
);
8750 neon_invert_size (&immlo
, &immhi
, 64);
8752 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8753 &op
, 64, NT_invtype
);
8758 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8764 /* Fill other bits in vmov encoding for both thumb and arm. */
8766 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8768 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8769 neon_write_immbits (immbits
);
8777 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8778 if (inst
.operands
[i
].issingle
8779 && is_quarter_float (inst
.operands
[1].imm
)
8780 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8782 inst
.operands
[1].imm
=
8783 neon_qfloat_bits (v
);
8784 do_vfp_nsyn_opcode ("fconsts");
8788 /* If our host does not support a 64-bit type then we cannot perform
8789 the following optimization. This mean that there will be a
8790 discrepancy between the output produced by an assembler built for
8791 a 32-bit-only host and the output produced from a 64-bit host, but
8792 this cannot be helped. */
8793 #if defined BFD_HOST_64_BIT
8794 else if (!inst
.operands
[1].issingle
8795 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8797 if (is_double_a_single (v
)
8798 && is_quarter_float (double_to_single (v
)))
8800 inst
.operands
[1].imm
=
8801 neon_qfloat_bits (double_to_single (v
));
8802 do_vfp_nsyn_opcode ("fconstd");
8810 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8811 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8814 inst
.operands
[1].reg
= REG_PC
;
8815 inst
.operands
[1].isreg
= 1;
8816 inst
.operands
[1].preind
= 1;
8817 inst
.relocs
[0].pc_rel
= 1;
8818 inst
.relocs
[0].type
= (thumb_p
8819 ? BFD_RELOC_ARM_THUMB_OFFSET
8821 ? BFD_RELOC_ARM_HWLITERAL
8822 : BFD_RELOC_ARM_LITERAL
));
8826 /* inst.operands[i] was set up by parse_address. Encode it into an
8827 ARM-format instruction. Reject all forms which cannot be encoded
8828 into a coprocessor load/store instruction. If wb_ok is false,
8829 reject use of writeback; if unind_ok is false, reject use of
8830 unindexed addressing. If reloc_override is not 0, use it instead
8831 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8832 (in which case it is preserved). */
8835 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8837 if (!inst
.operands
[i
].isreg
)
8840 if (! inst
.operands
[0].isvec
)
8842 inst
.error
= _("invalid co-processor operand");
8845 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8849 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8851 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8853 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8855 gas_assert (!inst
.operands
[i
].writeback
);
8858 inst
.error
= _("instruction does not support unindexed addressing");
8861 inst
.instruction
|= inst
.operands
[i
].imm
;
8862 inst
.instruction
|= INDEX_UP
;
8866 if (inst
.operands
[i
].preind
)
8867 inst
.instruction
|= PRE_INDEX
;
8869 if (inst
.operands
[i
].writeback
)
8871 if (inst
.operands
[i
].reg
== REG_PC
)
8873 inst
.error
= _("pc may not be used with write-back");
8878 inst
.error
= _("instruction does not support writeback");
8881 inst
.instruction
|= WRITE_BACK
;
8885 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8886 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8887 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8888 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8891 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8893 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8896 /* Prefer + for zero encoded value. */
8897 if (!inst
.operands
[i
].negative
)
8898 inst
.instruction
|= INDEX_UP
;
8903 /* Functions for instruction encoding, sorted by sub-architecture.
8904 First some generics; their names are taken from the conventional
8905 bit positions for register arguments in ARM format instructions. */
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8921 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8928 inst
.instruction
|= inst
.operands
[1].reg
;
8934 inst
.instruction
|= inst
.operands
[0].reg
;
8935 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8960 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8962 if (ARM_CPU_IS_ANY (cpu_variant
))
8964 as_tsktsk ("%s", msg
);
8967 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8979 unsigned Rn
= inst
.operands
[2].reg
;
8980 /* Enforce restrictions on SWP instruction. */
8981 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8983 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8984 _("Rn must not overlap other operands"));
8986 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8988 if (!check_obsolete (&arm_ext_v8
,
8989 _("swp{b} use is obsoleted for ARMv8 and later"))
8990 && warn_on_deprecated
8991 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8992 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8996 inst
.instruction
|= inst
.operands
[1].reg
;
8997 inst
.instruction
|= Rn
<< 16;
9003 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9004 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9005 inst
.instruction
|= inst
.operands
[2].reg
;
9011 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9012 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9013 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9014 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9016 inst
.instruction
|= inst
.operands
[0].reg
;
9017 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9018 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9024 inst
.instruction
|= inst
.operands
[0].imm
;
9030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9031 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9034 /* ARM instructions, in alphabetical order by function name (except
9035 that wrapper functions appear immediately after the function they
9038 /* This is a pseudo-op of the form "adr rd, label" to be converted
9039 into a relative address of the form "add rd, pc, #label-.-8". */
9044 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9046 /* Frag hacking will turn this into a sub instruction if the offset turns
9047 out to be negative. */
9048 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9049 inst
.relocs
[0].pc_rel
= 1;
9050 inst
.relocs
[0].exp
.X_add_number
-= 8;
9052 if (support_interwork
9053 && inst
.relocs
[0].exp
.X_op
== O_symbol
9054 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9055 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9056 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9057 inst
.relocs
[0].exp
.X_add_number
|= 1;
9060 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9061 into a relative address of the form:
9062 add rd, pc, #low(label-.-8)"
9063 add rd, rd, #high(label-.-8)" */
9068 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9070 /* Frag hacking will turn this into a sub instruction if the offset turns
9071 out to be negative. */
9072 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9073 inst
.relocs
[0].pc_rel
= 1;
9074 inst
.size
= INSN_SIZE
* 2;
9075 inst
.relocs
[0].exp
.X_add_number
-= 8;
9077 if (support_interwork
9078 && inst
.relocs
[0].exp
.X_op
== O_symbol
9079 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9080 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9081 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9082 inst
.relocs
[0].exp
.X_add_number
|= 1;
9088 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9089 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9091 if (!inst
.operands
[1].present
)
9092 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9093 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9094 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9095 encode_arm_shifter_operand (2);
9101 if (inst
.operands
[0].present
)
9102 inst
.instruction
|= inst
.operands
[0].imm
;
9104 inst
.instruction
|= 0xf;
9110 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9111 constraint (msb
> 32, _("bit-field extends past end of register"));
9112 /* The instruction encoding stores the LSB and MSB,
9113 not the LSB and width. */
9114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9115 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9116 inst
.instruction
|= (msb
- 1) << 16;
9124 /* #0 in second position is alternative syntax for bfc, which is
9125 the same instruction but with REG_PC in the Rm field. */
9126 if (!inst
.operands
[1].isreg
)
9127 inst
.operands
[1].reg
= REG_PC
;
9129 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9130 constraint (msb
> 32, _("bit-field extends past end of register"));
9131 /* The instruction encoding stores the LSB and MSB,
9132 not the LSB and width. */
9133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9134 inst
.instruction
|= inst
.operands
[1].reg
;
9135 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9136 inst
.instruction
|= (msb
- 1) << 16;
9142 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9143 _("bit-field extends past end of register"));
9144 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9145 inst
.instruction
|= inst
.operands
[1].reg
;
9146 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9147 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9150 /* ARM V5 breakpoint instruction (argument parse)
9151 BKPT <16 bit unsigned immediate>
9152 Instruction is not conditional.
9153 The bit pattern given in insns[] has the COND_ALWAYS condition,
9154 and it is an error if the caller tried to override that. */
9159 /* Top 12 of 16 bits to bits 19:8. */
9160 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9162 /* Bottom 4 of 16 bits to bits 3:0. */
9163 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9167 encode_branch (int default_reloc
)
9169 if (inst
.operands
[0].hasreloc
)
9171 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9172 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9173 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9174 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9175 ? BFD_RELOC_ARM_PLT32
9176 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9179 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9180 inst
.relocs
[0].pc_rel
= 1;
9187 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9188 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9191 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9198 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9200 if (inst
.cond
== COND_ALWAYS
)
9201 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9203 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9207 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9210 /* ARM V5 branch-link-exchange instruction (argument parse)
9211 BLX <target_addr> ie BLX(1)
9212 BLX{<condition>} <Rm> ie BLX(2)
9213 Unfortunately, there are two different opcodes for this mnemonic.
9214 So, the insns[].value is not used, and the code here zaps values
9215 into inst.instruction.
9216 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9221 if (inst
.operands
[0].isreg
)
9223 /* Arg is a register; the opcode provided by insns[] is correct.
9224 It is not illegal to do "blx pc", just useless. */
9225 if (inst
.operands
[0].reg
== REG_PC
)
9226 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9228 inst
.instruction
|= inst
.operands
[0].reg
;
9232 /* Arg is an address; this instruction cannot be executed
9233 conditionally, and the opcode must be adjusted.
9234 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9235 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9236 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9237 inst
.instruction
= 0xfa000000;
9238 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9245 bfd_boolean want_reloc
;
9247 if (inst
.operands
[0].reg
== REG_PC
)
9248 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9250 inst
.instruction
|= inst
.operands
[0].reg
;
9251 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9252 it is for ARMv4t or earlier. */
9253 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9254 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9255 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9259 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9264 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9268 /* ARM v5TEJ. Jump to Jazelle code. */
9273 if (inst
.operands
[0].reg
== REG_PC
)
9274 as_tsktsk (_("use of r15 in bxj is not really useful"));
9276 inst
.instruction
|= inst
.operands
[0].reg
;
9279 /* Co-processor data operation:
9280 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9281 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9285 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9286 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9287 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9289 inst
.instruction
|= inst
.operands
[4].reg
;
9290 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9296 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9297 encode_arm_shifter_operand (1);
9300 /* Transfer between coprocessor and ARM registers.
9301 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9306 No special properties. */
9308 struct deprecated_coproc_regs_s
9315 arm_feature_set deprecated
;
9316 arm_feature_set obsoleted
;
9317 const char *dep_msg
;
9318 const char *obs_msg
;
9321 #define DEPR_ACCESS_V8 \
9322 N_("This coprocessor register access is deprecated in ARMv8")
9324 /* Table of all deprecated coprocessor registers. */
9325 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9327 {15, 0, 7, 10, 5, /* CP15DMB. */
9328 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9329 DEPR_ACCESS_V8
, NULL
},
9330 {15, 0, 7, 10, 4, /* CP15DSB. */
9331 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9332 DEPR_ACCESS_V8
, NULL
},
9333 {15, 0, 7, 5, 4, /* CP15ISB. */
9334 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9335 DEPR_ACCESS_V8
, NULL
},
9336 {14, 6, 1, 0, 0, /* TEEHBR. */
9337 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9338 DEPR_ACCESS_V8
, NULL
},
9339 {14, 6, 0, 0, 0, /* TEECR. */
9340 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9341 DEPR_ACCESS_V8
, NULL
},
9344 #undef DEPR_ACCESS_V8
9346 static const size_t deprecated_coproc_reg_count
=
9347 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9355 Rd
= inst
.operands
[2].reg
;
9358 if (inst
.instruction
== 0xee000010
9359 || inst
.instruction
== 0xfe000010)
9361 reject_bad_reg (Rd
);
9362 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9364 constraint (Rd
== REG_SP
, BAD_SP
);
9369 if (inst
.instruction
== 0xe000010)
9370 constraint (Rd
== REG_PC
, BAD_PC
);
9373 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9375 const struct deprecated_coproc_regs_s
*r
=
9376 deprecated_coproc_regs
+ i
;
9378 if (inst
.operands
[0].reg
== r
->cp
9379 && inst
.operands
[1].imm
== r
->opc1
9380 && inst
.operands
[3].reg
== r
->crn
9381 && inst
.operands
[4].reg
== r
->crm
9382 && inst
.operands
[5].imm
== r
->opc2
)
9384 if (! ARM_CPU_IS_ANY (cpu_variant
)
9385 && warn_on_deprecated
9386 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9387 as_tsktsk ("%s", r
->dep_msg
);
9391 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9392 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9393 inst
.instruction
|= Rd
<< 12;
9394 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9395 inst
.instruction
|= inst
.operands
[4].reg
;
9396 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9399 /* Transfer between coprocessor register and pair of ARM registers.
9400 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9405 Two XScale instructions are special cases of these:
9407 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9408 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9410 Result unpredictable if Rd or Rn is R15. */
9417 Rd
= inst
.operands
[2].reg
;
9418 Rn
= inst
.operands
[3].reg
;
9422 reject_bad_reg (Rd
);
9423 reject_bad_reg (Rn
);
9427 constraint (Rd
== REG_PC
, BAD_PC
);
9428 constraint (Rn
== REG_PC
, BAD_PC
);
9431 /* Only check the MRRC{2} variants. */
9432 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9434 /* If Rd == Rn, error that the operation is
9435 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9436 constraint (Rd
== Rn
, BAD_OVERLAP
);
9439 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9440 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9441 inst
.instruction
|= Rd
<< 12;
9442 inst
.instruction
|= Rn
<< 16;
9443 inst
.instruction
|= inst
.operands
[4].reg
;
9449 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9450 if (inst
.operands
[1].present
)
9452 inst
.instruction
|= CPSI_MMOD
;
9453 inst
.instruction
|= inst
.operands
[1].imm
;
9460 inst
.instruction
|= inst
.operands
[0].imm
;
9466 unsigned Rd
, Rn
, Rm
;
9468 Rd
= inst
.operands
[0].reg
;
9469 Rn
= (inst
.operands
[1].present
9470 ? inst
.operands
[1].reg
: Rd
);
9471 Rm
= inst
.operands
[2].reg
;
9473 constraint ((Rd
== REG_PC
), BAD_PC
);
9474 constraint ((Rn
== REG_PC
), BAD_PC
);
9475 constraint ((Rm
== REG_PC
), BAD_PC
);
9477 inst
.instruction
|= Rd
<< 16;
9478 inst
.instruction
|= Rn
<< 0;
9479 inst
.instruction
|= Rm
<< 8;
9485 /* There is no IT instruction in ARM mode. We
9486 process it to do the validation as if in
9487 thumb mode, just in case the code gets
9488 assembled for thumb using the unified syntax. */
9493 set_pred_insn_type (IT_INSN
);
9494 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9495 now_pred
.cc
= inst
.operands
[0].imm
;
9499 /* If there is only one register in the register list,
9500 then return its register number. Otherwise return -1. */
9502 only_one_reg_in_list (int range
)
9504 int i
= ffs (range
) - 1;
9505 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9509 encode_ldmstm(int from_push_pop_mnem
)
9511 int base_reg
= inst
.operands
[0].reg
;
9512 int range
= inst
.operands
[1].imm
;
9515 inst
.instruction
|= base_reg
<< 16;
9516 inst
.instruction
|= range
;
9518 if (inst
.operands
[1].writeback
)
9519 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9521 if (inst
.operands
[0].writeback
)
9523 inst
.instruction
|= WRITE_BACK
;
9524 /* Check for unpredictable uses of writeback. */
9525 if (inst
.instruction
& LOAD_BIT
)
9527 /* Not allowed in LDM type 2. */
9528 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9529 && ((range
& (1 << REG_PC
)) == 0))
9530 as_warn (_("writeback of base register is UNPREDICTABLE"));
9531 /* Only allowed if base reg not in list for other types. */
9532 else if (range
& (1 << base_reg
))
9533 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9537 /* Not allowed for type 2. */
9538 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9539 as_warn (_("writeback of base register is UNPREDICTABLE"));
9540 /* Only allowed if base reg not in list, or first in list. */
9541 else if ((range
& (1 << base_reg
))
9542 && (range
& ((1 << base_reg
) - 1)))
9543 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9547 /* If PUSH/POP has only one register, then use the A2 encoding. */
9548 one_reg
= only_one_reg_in_list (range
);
9549 if (from_push_pop_mnem
&& one_reg
>= 0)
9551 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9553 if (is_push
&& one_reg
== 13 /* SP */)
9554 /* PR 22483: The A2 encoding cannot be used when
9555 pushing the stack pointer as this is UNPREDICTABLE. */
9558 inst
.instruction
&= A_COND_MASK
;
9559 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9560 inst
.instruction
|= one_reg
<< 12;
9567 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9570 /* ARMv5TE load-consecutive (argument parse)
9579 constraint (inst
.operands
[0].reg
% 2 != 0,
9580 _("first transfer register must be even"));
9581 constraint (inst
.operands
[1].present
9582 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9583 _("can only transfer two consecutive registers"));
9584 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9585 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9587 if (!inst
.operands
[1].present
)
9588 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9590 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9591 register and the first register written; we have to diagnose
9592 overlap between the base and the second register written here. */
9594 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9595 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9596 as_warn (_("base register written back, and overlaps "
9597 "second transfer register"));
9599 if (!(inst
.instruction
& V4_STR_BIT
))
9601 /* For an index-register load, the index register must not overlap the
9602 destination (even if not write-back). */
9603 if (inst
.operands
[2].immisreg
9604 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9605 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9606 as_warn (_("index register overlaps transfer register"));
9608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9609 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9615 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9616 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9617 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9618 || inst
.operands
[1].negative
9619 /* This can arise if the programmer has written
9621 or if they have mistakenly used a register name as the last
9624 It is very difficult to distinguish between these two cases
9625 because "rX" might actually be a label. ie the register
9626 name has been occluded by a symbol of the same name. So we
9627 just generate a general 'bad addressing mode' type error
9628 message and leave it up to the programmer to discover the
9629 true cause and fix their mistake. */
9630 || (inst
.operands
[1].reg
== REG_PC
),
9633 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9634 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9635 _("offset must be zero in ARM encoding"));
9637 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9641 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9647 constraint (inst
.operands
[0].reg
% 2 != 0,
9648 _("even register required"));
9649 constraint (inst
.operands
[1].present
9650 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9651 _("can only load two consecutive registers"));
9652 /* If op 1 were present and equal to PC, this function wouldn't
9653 have been called in the first place. */
9654 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9656 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9657 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9660 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9661 which is not a multiple of four is UNPREDICTABLE. */
9663 check_ldr_r15_aligned (void)
9665 constraint (!(inst
.operands
[1].immisreg
)
9666 && (inst
.operands
[0].reg
== REG_PC
9667 && inst
.operands
[1].reg
== REG_PC
9668 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9669 _("ldr to register 15 must be 4-byte aligned"));
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 if (!inst
.operands
[1].isreg
)
9677 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9679 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9680 check_ldr_r15_aligned ();
9686 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9688 if (inst
.operands
[1].preind
)
9690 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9691 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9692 _("this instruction requires a post-indexed address"));
9694 inst
.operands
[1].preind
= 0;
9695 inst
.operands
[1].postind
= 1;
9696 inst
.operands
[1].writeback
= 1;
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9699 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9702 /* Halfword and signed-byte load/store operations. */
9707 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9709 if (!inst
.operands
[1].isreg
)
9710 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9712 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9718 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9720 if (inst
.operands
[1].preind
)
9722 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9723 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9724 _("this instruction requires a post-indexed address"));
9726 inst
.operands
[1].preind
= 0;
9727 inst
.operands
[1].postind
= 1;
9728 inst
.operands
[1].writeback
= 1;
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9731 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9734 /* Co-processor register load/store.
9735 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9739 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9740 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9741 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9747 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9748 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9749 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9750 && !(inst
.instruction
& 0x00400000))
9751 as_tsktsk (_("Rd and Rm should be different in mla"));
9753 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9754 inst
.instruction
|= inst
.operands
[1].reg
;
9755 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9756 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9762 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9763 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9765 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9766 encode_arm_shifter_operand (1);
9769 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9776 top
= (inst
.instruction
& 0x00400000) != 0;
9777 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9778 _(":lower16: not allowed in this instruction"));
9779 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9780 _(":upper16: not allowed in this instruction"));
9781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9782 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9784 imm
= inst
.relocs
[0].exp
.X_add_number
;
9785 /* The value is in two pieces: 0:11, 16:19. */
9786 inst
.instruction
|= (imm
& 0x00000fff);
9787 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9792 do_vfp_nsyn_mrs (void)
9794 if (inst
.operands
[0].isvec
)
9796 if (inst
.operands
[1].reg
!= 1)
9797 first_error (_("operand 1 must be FPSCR"));
9798 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9799 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9800 do_vfp_nsyn_opcode ("fmstat");
9802 else if (inst
.operands
[1].isvec
)
9803 do_vfp_nsyn_opcode ("fmrx");
9811 do_vfp_nsyn_msr (void)
9813 if (inst
.operands
[0].isvec
)
9814 do_vfp_nsyn_opcode ("fmxr");
9824 unsigned Rt
= inst
.operands
[0].reg
;
9826 if (thumb_mode
&& Rt
== REG_SP
)
9828 inst
.error
= BAD_SP
;
9832 /* MVFR2 is only valid at ARMv8-A. */
9833 if (inst
.operands
[1].reg
== 5)
9834 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9837 /* APSR_ sets isvec. All other refs to PC are illegal. */
9838 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9840 inst
.error
= BAD_PC
;
9844 /* If we get through parsing the register name, we just insert the number
9845 generated into the instruction without further validation. */
9846 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9847 inst
.instruction
|= (Rt
<< 12);
9853 unsigned Rt
= inst
.operands
[1].reg
;
9856 reject_bad_reg (Rt
);
9857 else if (Rt
== REG_PC
)
9859 inst
.error
= BAD_PC
;
9863 /* MVFR2 is only valid for ARMv8-A. */
9864 if (inst
.operands
[0].reg
== 5)
9865 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9868 /* If we get through parsing the register name, we just insert the number
9869 generated into the instruction without further validation. */
9870 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9871 inst
.instruction
|= (Rt
<< 12);
9879 if (do_vfp_nsyn_mrs () == SUCCESS
)
9882 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9885 if (inst
.operands
[1].isreg
)
9887 br
= inst
.operands
[1].reg
;
9888 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9889 as_bad (_("bad register for mrs"));
9893 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9894 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9896 _("'APSR', 'CPSR' or 'SPSR' expected"));
9897 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9900 inst
.instruction
|= br
;
9903 /* Two possible forms:
9904 "{C|S}PSR_<field>, Rm",
9905 "{C|S}PSR_f, #expression". */
9910 if (do_vfp_nsyn_msr () == SUCCESS
)
9913 inst
.instruction
|= inst
.operands
[0].imm
;
9914 if (inst
.operands
[1].isreg
)
9915 inst
.instruction
|= inst
.operands
[1].reg
;
9918 inst
.instruction
|= INST_IMMEDIATE
;
9919 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9920 inst
.relocs
[0].pc_rel
= 0;
9927 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9929 if (!inst
.operands
[2].present
)
9930 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9931 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9932 inst
.instruction
|= inst
.operands
[1].reg
;
9933 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9935 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9936 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9937 as_tsktsk (_("Rd and Rm should be different in mul"));
9940 /* Long Multiply Parser
9941 UMULL RdLo, RdHi, Rm, Rs
9942 SMULL RdLo, RdHi, Rm, Rs
9943 UMLAL RdLo, RdHi, Rm, Rs
9944 SMLAL RdLo, RdHi, Rm, Rs. */
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9951 inst
.instruction
|= inst
.operands
[2].reg
;
9952 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9954 /* rdhi and rdlo must be different. */
9955 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9956 as_tsktsk (_("rdhi and rdlo must be different"));
9958 /* rdhi, rdlo and rm must all be different before armv6. */
9959 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9960 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9961 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9962 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9968 if (inst
.operands
[0].present
9969 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9971 /* Architectural NOP hints are CPSR sets with no bits selected. */
9972 inst
.instruction
&= 0xf0000000;
9973 inst
.instruction
|= 0x0320f000;
9974 if (inst
.operands
[0].present
)
9975 inst
.instruction
|= inst
.operands
[0].imm
;
9979 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9980 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9981 Condition defaults to COND_ALWAYS.
9982 Error if Rd, Rn or Rm are R15. */
9987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9988 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9989 inst
.instruction
|= inst
.operands
[2].reg
;
9990 if (inst
.operands
[3].present
)
9991 encode_arm_shift (3);
9994 /* ARM V6 PKHTB (Argument Parse). */
9999 if (!inst
.operands
[3].present
)
10001 /* If the shift specifier is omitted, turn the instruction
10002 into pkhbt rd, rm, rn. */
10003 inst
.instruction
&= 0xfff00010;
10004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10005 inst
.instruction
|= inst
.operands
[1].reg
;
10006 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10012 inst
.instruction
|= inst
.operands
[2].reg
;
10013 encode_arm_shift (3);
10017 /* ARMv5TE: Preload-Cache
10018 MP Extensions: Preload for write
10022 Syntactically, like LDR with B=1, W=0, L=1. */
10027 constraint (!inst
.operands
[0].isreg
,
10028 _("'[' expected after PLD mnemonic"));
10029 constraint (inst
.operands
[0].postind
,
10030 _("post-indexed expression used in preload instruction"));
10031 constraint (inst
.operands
[0].writeback
,
10032 _("writeback used in preload instruction"));
10033 constraint (!inst
.operands
[0].preind
,
10034 _("unindexed addressing used in preload instruction"));
10035 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10038 /* ARMv7: PLI <addr_mode> */
10042 constraint (!inst
.operands
[0].isreg
,
10043 _("'[' expected after PLI mnemonic"));
10044 constraint (inst
.operands
[0].postind
,
10045 _("post-indexed expression used in preload instruction"));
10046 constraint (inst
.operands
[0].writeback
,
10047 _("writeback used in preload instruction"));
10048 constraint (!inst
.operands
[0].preind
,
10049 _("unindexed addressing used in preload instruction"));
10050 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10051 inst
.instruction
&= ~PRE_INDEX
;
10057 constraint (inst
.operands
[0].writeback
,
10058 _("push/pop do not support {reglist}^"));
10059 inst
.operands
[1] = inst
.operands
[0];
10060 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10061 inst
.operands
[0].isreg
= 1;
10062 inst
.operands
[0].writeback
= 1;
10063 inst
.operands
[0].reg
= REG_SP
;
10064 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10067 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10068 word at the specified address and the following word
10070 Unconditionally executed.
10071 Error if Rn is R15. */
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10077 if (inst
.operands
[0].writeback
)
10078 inst
.instruction
|= WRITE_BACK
;
10081 /* ARM V6 ssat (argument parse). */
10086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10087 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10088 inst
.instruction
|= inst
.operands
[2].reg
;
10090 if (inst
.operands
[3].present
)
10091 encode_arm_shift (3);
10094 /* ARM V6 usat (argument parse). */
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10100 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10101 inst
.instruction
|= inst
.operands
[2].reg
;
10103 if (inst
.operands
[3].present
)
10104 encode_arm_shift (3);
10107 /* ARM V6 ssat16 (argument parse). */
10112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10113 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10114 inst
.instruction
|= inst
.operands
[2].reg
;
10120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10121 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10122 inst
.instruction
|= inst
.operands
[2].reg
;
10125 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10126 preserving the other bits.
10128 setend <endian_specifier>, where <endian_specifier> is either
10134 if (warn_on_deprecated
10135 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10136 as_tsktsk (_("setend use is deprecated for ARMv8"));
10138 if (inst
.operands
[0].imm
)
10139 inst
.instruction
|= 0x200;
10145 unsigned int Rm
= (inst
.operands
[1].present
10146 ? inst
.operands
[1].reg
10147 : inst
.operands
[0].reg
);
10149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10150 inst
.instruction
|= Rm
;
10151 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10153 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10154 inst
.instruction
|= SHIFT_BY_REG
;
10155 /* PR 12854: Error on extraneous shifts. */
10156 constraint (inst
.operands
[2].shifted
,
10157 _("extraneous shift as part of operand to shift insn"));
10160 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10166 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10167 inst
.relocs
[0].pc_rel
= 0;
10173 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10174 inst
.relocs
[0].pc_rel
= 0;
10180 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10181 inst
.relocs
[0].pc_rel
= 0;
10187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10188 _("selected processor does not support SETPAN instruction"));
10190 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10196 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10197 _("selected processor does not support SETPAN instruction"));
10199 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10202 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10203 SMLAxy{cond} Rd,Rm,Rs,Rn
10204 SMLAWy{cond} Rd,Rm,Rs,Rn
10205 Error if any register is R15. */
10210 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10211 inst
.instruction
|= inst
.operands
[1].reg
;
10212 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10213 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10216 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10217 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10218 Error if any register is R15.
10219 Warning if Rdlo == Rdhi. */
10224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10225 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10226 inst
.instruction
|= inst
.operands
[2].reg
;
10227 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10229 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10230 as_tsktsk (_("rdhi and rdlo must be different"));
10233 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10234 SMULxy{cond} Rd,Rm,Rs
10235 Error if any register is R15. */
10240 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10241 inst
.instruction
|= inst
.operands
[1].reg
;
10242 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10245 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10246 the same for both ARM and Thumb-2. */
10253 if (inst
.operands
[0].present
)
10255 reg
= inst
.operands
[0].reg
;
10256 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10261 inst
.instruction
|= reg
<< 16;
10262 inst
.instruction
|= inst
.operands
[1].imm
;
10263 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10264 inst
.instruction
|= WRITE_BACK
;
10267 /* ARM V6 strex (argument parse). */
10272 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10273 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10274 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10275 || inst
.operands
[2].negative
10276 /* See comment in do_ldrex(). */
10277 || (inst
.operands
[2].reg
== REG_PC
),
10280 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10281 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10283 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10284 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10285 _("offset must be zero in ARM encoding"));
10287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10288 inst
.instruction
|= inst
.operands
[1].reg
;
10289 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10290 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10294 do_t_strexbh (void)
10296 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10297 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10298 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10299 || inst
.operands
[2].negative
,
10302 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10303 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10311 constraint (inst
.operands
[1].reg
% 2 != 0,
10312 _("even register required"));
10313 constraint (inst
.operands
[2].present
10314 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10315 _("can only store two consecutive registers"));
10316 /* If op 2 were present and equal to PC, this function wouldn't
10317 have been called in the first place. */
10318 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10320 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10321 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10322 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10326 inst
.instruction
|= inst
.operands
[1].reg
;
10327 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10334 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10335 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10343 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10344 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10349 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10350 extends it to 32-bits, and adds the result to a value in another
10351 register. You can specify a rotation by 0, 8, 16, or 24 bits
10352 before extracting the 16-bit value.
10353 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10354 Condition defaults to COND_ALWAYS.
10355 Error if any register uses R15. */
10360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10361 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10362 inst
.instruction
|= inst
.operands
[2].reg
;
10363 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10368 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10369 Condition defaults to COND_ALWAYS.
10370 Error if any register uses R15. */
10375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10376 inst
.instruction
|= inst
.operands
[1].reg
;
10377 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10380 /* VFP instructions. In a logical order: SP variant first, monad
10381 before dyad, arithmetic then move then load/store. */
10384 do_vfp_sp_monadic (void)
10386 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10387 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10390 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10391 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10395 do_vfp_sp_dyadic (void)
10397 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10398 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10399 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10403 do_vfp_sp_compare_z (void)
10405 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10409 do_vfp_dp_sp_cvt (void)
10411 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10412 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10416 do_vfp_sp_dp_cvt (void)
10418 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10419 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10423 do_vfp_reg_from_sp (void)
10425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10426 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10430 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10434 do_vfp_reg2_from_sp2 (void)
10436 constraint (inst
.operands
[2].imm
!= 2,
10437 _("only two consecutive VFP SP registers allowed here"));
10438 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10439 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10440 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10444 do_vfp_sp_from_reg (void)
10446 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10447 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10450 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10451 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10455 do_vfp_sp2_from_reg2 (void)
10457 constraint (inst
.operands
[0].imm
!= 2,
10458 _("only two consecutive VFP SP registers allowed here"));
10459 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10460 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10461 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10465 do_vfp_sp_ldst (void)
10467 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10468 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10472 do_vfp_dp_ldst (void)
10474 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10475 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10480 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10482 if (inst
.operands
[0].writeback
)
10483 inst
.instruction
|= WRITE_BACK
;
10485 constraint (ldstm_type
!= VFP_LDSTMIA
,
10486 _("this addressing mode requires base-register writeback"));
10487 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10488 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10489 inst
.instruction
|= inst
.operands
[1].imm
;
10493 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10497 if (inst
.operands
[0].writeback
)
10498 inst
.instruction
|= WRITE_BACK
;
10500 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10501 _("this addressing mode requires base-register writeback"));
10503 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10504 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10506 count
= inst
.operands
[1].imm
<< 1;
10507 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10510 inst
.instruction
|= count
;
10514 do_vfp_sp_ldstmia (void)
10516 vfp_sp_ldstm (VFP_LDSTMIA
);
10520 do_vfp_sp_ldstmdb (void)
10522 vfp_sp_ldstm (VFP_LDSTMDB
);
10526 do_vfp_dp_ldstmia (void)
10528 vfp_dp_ldstm (VFP_LDSTMIA
);
10532 do_vfp_dp_ldstmdb (void)
10534 vfp_dp_ldstm (VFP_LDSTMDB
);
10538 do_vfp_xp_ldstmia (void)
10540 vfp_dp_ldstm (VFP_LDSTMIAX
);
10544 do_vfp_xp_ldstmdb (void)
10546 vfp_dp_ldstm (VFP_LDSTMDBX
);
10550 do_vfp_dp_rd_rm (void)
10552 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10553 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10556 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10557 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10561 do_vfp_dp_rn_rd (void)
10563 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10564 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10568 do_vfp_dp_rd_rn (void)
10570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10571 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10575 do_vfp_dp_rd_rn_rm (void)
10577 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10578 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10581 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10582 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10583 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10587 do_vfp_dp_rd (void)
10589 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10593 do_vfp_dp_rm_rd_rn (void)
10595 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10596 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10599 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10600 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10601 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10604 /* VFPv3 instructions. */
10606 do_vfp_sp_const (void)
10608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10609 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10610 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10614 do_vfp_dp_const (void)
10616 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10617 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10618 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10622 vfp_conv (int srcsize
)
10624 int immbits
= srcsize
- inst
.operands
[1].imm
;
10626 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10628 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10629 i.e. immbits must be in range 0 - 16. */
10630 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10633 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10635 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10636 i.e. immbits must be in range 0 - 31. */
10637 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10641 inst
.instruction
|= (immbits
& 1) << 5;
10642 inst
.instruction
|= (immbits
>> 1);
10646 do_vfp_sp_conv_16 (void)
10648 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10653 do_vfp_dp_conv_16 (void)
10655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10660 do_vfp_sp_conv_32 (void)
10662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10667 do_vfp_dp_conv_32 (void)
10669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10673 /* FPA instructions. Also in a logical order. */
10678 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10679 inst
.instruction
|= inst
.operands
[1].reg
;
10683 do_fpa_ldmstm (void)
10685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10686 switch (inst
.operands
[1].imm
)
10688 case 1: inst
.instruction
|= CP_T_X
; break;
10689 case 2: inst
.instruction
|= CP_T_Y
; break;
10690 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10695 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10697 /* The instruction specified "ea" or "fd", so we can only accept
10698 [Rn]{!}. The instruction does not really support stacking or
10699 unstacking, so we have to emulate these by setting appropriate
10700 bits and offsets. */
10701 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10702 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10703 _("this instruction does not support indexing"));
10705 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10706 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10708 if (!(inst
.instruction
& INDEX_UP
))
10709 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10711 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10713 inst
.operands
[2].preind
= 0;
10714 inst
.operands
[2].postind
= 1;
10718 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10721 /* iWMMXt instructions: strictly in alphabetical order. */
10724 do_iwmmxt_tandorc (void)
10726 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10730 do_iwmmxt_textrc (void)
10732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10733 inst
.instruction
|= inst
.operands
[1].imm
;
10737 do_iwmmxt_textrm (void)
10739 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10740 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10741 inst
.instruction
|= inst
.operands
[2].imm
;
10745 do_iwmmxt_tinsr (void)
10747 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10748 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10749 inst
.instruction
|= inst
.operands
[2].imm
;
10753 do_iwmmxt_tmia (void)
10755 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10756 inst
.instruction
|= inst
.operands
[1].reg
;
10757 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10761 do_iwmmxt_waligni (void)
10763 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10764 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10765 inst
.instruction
|= inst
.operands
[2].reg
;
10766 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10770 do_iwmmxt_wmerge (void)
10772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10774 inst
.instruction
|= inst
.operands
[2].reg
;
10775 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10779 do_iwmmxt_wmov (void)
10781 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10783 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10784 inst
.instruction
|= inst
.operands
[1].reg
;
10788 do_iwmmxt_wldstbh (void)
10791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10793 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10795 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10796 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10800 do_iwmmxt_wldstw (void)
10802 /* RIWR_RIWC clears .isreg for a control register. */
10803 if (!inst
.operands
[0].isreg
)
10805 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10806 inst
.instruction
|= 0xf0000000;
10809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10810 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10814 do_iwmmxt_wldstd (void)
10816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10817 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10818 && inst
.operands
[1].immisreg
)
10820 inst
.instruction
&= ~0x1a000ff;
10821 inst
.instruction
|= (0xfU
<< 28);
10822 if (inst
.operands
[1].preind
)
10823 inst
.instruction
|= PRE_INDEX
;
10824 if (!inst
.operands
[1].negative
)
10825 inst
.instruction
|= INDEX_UP
;
10826 if (inst
.operands
[1].writeback
)
10827 inst
.instruction
|= WRITE_BACK
;
10828 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10829 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10830 inst
.instruction
|= inst
.operands
[1].imm
;
10833 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10837 do_iwmmxt_wshufh (void)
10839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10840 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10841 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10846 do_iwmmxt_wzero (void)
10848 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10849 inst
.instruction
|= inst
.operands
[0].reg
;
10850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10851 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10855 do_iwmmxt_wrwrwr_or_imm5 (void)
10857 if (inst
.operands
[2].isreg
)
10860 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10861 _("immediate operand requires iWMMXt2"));
10863 if (inst
.operands
[2].imm
== 0)
10865 switch ((inst
.instruction
>> 20) & 0xf)
10871 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10872 inst
.operands
[2].imm
= 16;
10873 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10879 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10880 inst
.operands
[2].imm
= 32;
10881 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10888 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10890 wrn
= (inst
.instruction
>> 16) & 0xf;
10891 inst
.instruction
&= 0xff0fff0f;
10892 inst
.instruction
|= wrn
;
10893 /* Bail out here; the instruction is now assembled. */
10898 /* Map 32 -> 0, etc. */
10899 inst
.operands
[2].imm
&= 0x1f;
10900 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10904 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10905 operations first, then control, shift, and load/store. */
10907 /* Insns like "foo X,Y,Z". */
10910 do_mav_triple (void)
10912 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10913 inst
.instruction
|= inst
.operands
[1].reg
;
10914 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10917 /* Insns like "foo W,X,Y,Z".
10918 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10923 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10924 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10925 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10926 inst
.instruction
|= inst
.operands
[3].reg
;
10929 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10931 do_mav_dspsc (void)
10933 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10936 /* Maverick shift immediate instructions.
10937 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10938 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10941 do_mav_shift (void)
10943 int imm
= inst
.operands
[2].imm
;
10945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10948 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10949 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10950 Bit 4 should be 0. */
10951 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10953 inst
.instruction
|= imm
;
10956 /* XScale instructions. Also sorted arithmetic before move. */
10958 /* Xscale multiply-accumulate (argument parse)
10961 MIAxycc acc0,Rm,Rs. */
10966 inst
.instruction
|= inst
.operands
[1].reg
;
10967 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10970 /* Xscale move-accumulator-register (argument parse)
10972 MARcc acc0,RdLo,RdHi. */
10977 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10978 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10981 /* Xscale move-register-accumulator (argument parse)
10983 MRAcc RdLo,RdHi,acc0. */
10988 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10990 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10993 /* Encoding functions relevant only to Thumb. */
10995 /* inst.operands[i] is a shifted-register operand; encode
10996 it into inst.instruction in the format used by Thumb32. */
10999 encode_thumb32_shifted_operand (int i
)
11001 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11002 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11004 constraint (inst
.operands
[i
].immisreg
,
11005 _("shift by register not allowed in thumb mode"));
11006 inst
.instruction
|= inst
.operands
[i
].reg
;
11007 if (shift
== SHIFT_RRX
)
11008 inst
.instruction
|= SHIFT_ROR
<< 4;
11011 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11012 _("expression too complex"));
11014 constraint (value
> 32
11015 || (value
== 32 && (shift
== SHIFT_LSL
11016 || shift
== SHIFT_ROR
)),
11017 _("shift expression is too large"));
11021 else if (value
== 32)
11024 inst
.instruction
|= shift
<< 4;
11025 inst
.instruction
|= (value
& 0x1c) << 10;
11026 inst
.instruction
|= (value
& 0x03) << 6;
11031 /* inst.operands[i] was set up by parse_address. Encode it into a
11032 Thumb32 format load or store instruction. Reject forms that cannot
11033 be used with such instructions. If is_t is true, reject forms that
11034 cannot be used with a T instruction; if is_d is true, reject forms
11035 that cannot be used with a D instruction. If it is a store insn,
11036 reject PC in Rn. */
11039 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11041 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11043 constraint (!inst
.operands
[i
].isreg
,
11044 _("Instruction does not support =N addresses"));
11046 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11047 if (inst
.operands
[i
].immisreg
)
11049 constraint (is_pc
, BAD_PC_ADDRESSING
);
11050 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11051 constraint (inst
.operands
[i
].negative
,
11052 _("Thumb does not support negative register indexing"));
11053 constraint (inst
.operands
[i
].postind
,
11054 _("Thumb does not support register post-indexing"));
11055 constraint (inst
.operands
[i
].writeback
,
11056 _("Thumb does not support register indexing with writeback"));
11057 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11058 _("Thumb supports only LSL in shifted register indexing"));
11060 inst
.instruction
|= inst
.operands
[i
].imm
;
11061 if (inst
.operands
[i
].shifted
)
11063 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11064 _("expression too complex"));
11065 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11066 || inst
.relocs
[0].exp
.X_add_number
> 3,
11067 _("shift out of range"));
11068 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11070 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11072 else if (inst
.operands
[i
].preind
)
11074 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11075 constraint (is_t
&& inst
.operands
[i
].writeback
,
11076 _("cannot use writeback with this instruction"));
11077 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11078 BAD_PC_ADDRESSING
);
11082 inst
.instruction
|= 0x01000000;
11083 if (inst
.operands
[i
].writeback
)
11084 inst
.instruction
|= 0x00200000;
11088 inst
.instruction
|= 0x00000c00;
11089 if (inst
.operands
[i
].writeback
)
11090 inst
.instruction
|= 0x00000100;
11092 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11094 else if (inst
.operands
[i
].postind
)
11096 gas_assert (inst
.operands
[i
].writeback
);
11097 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11098 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11101 inst
.instruction
|= 0x00200000;
11103 inst
.instruction
|= 0x00000900;
11104 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11106 else /* unindexed - only for coprocessor */
11107 inst
.error
= _("instruction does not accept unindexed addressing");
11110 /* Table of Thumb instructions which exist in both 16- and 32-bit
11111 encodings (the latter only in post-V6T2 cores). The index is the
11112 value used in the insns table below. When there is more than one
11113 possible 16-bit encoding for the instruction, this table always
11115 Also contains several pseudo-instructions used during relaxation. */
11116 #define T16_32_TAB \
11117 X(_adc, 4140, eb400000), \
11118 X(_adcs, 4140, eb500000), \
11119 X(_add, 1c00, eb000000), \
11120 X(_adds, 1c00, eb100000), \
11121 X(_addi, 0000, f1000000), \
11122 X(_addis, 0000, f1100000), \
11123 X(_add_pc,000f, f20f0000), \
11124 X(_add_sp,000d, f10d0000), \
11125 X(_adr, 000f, f20f0000), \
11126 X(_and, 4000, ea000000), \
11127 X(_ands, 4000, ea100000), \
11128 X(_asr, 1000, fa40f000), \
11129 X(_asrs, 1000, fa50f000), \
11130 X(_b, e000, f000b000), \
11131 X(_bcond, d000, f0008000), \
11132 X(_bf, 0000, f040e001), \
11133 X(_bfcsel,0000, f000e001), \
11134 X(_bfx, 0000, f060e001), \
11135 X(_bfl, 0000, f000c001), \
11136 X(_bflx, 0000, f070e001), \
11137 X(_bic, 4380, ea200000), \
11138 X(_bics, 4380, ea300000), \
11139 X(_cmn, 42c0, eb100f00), \
11140 X(_cmp, 2800, ebb00f00), \
11141 X(_cpsie, b660, f3af8400), \
11142 X(_cpsid, b670, f3af8600), \
11143 X(_cpy, 4600, ea4f0000), \
11144 X(_dec_sp,80dd, f1ad0d00), \
11145 X(_dls, 0000, f040e001), \
11146 X(_dlstp, 0000, f000e001), \
11147 X(_eor, 4040, ea800000), \
11148 X(_eors, 4040, ea900000), \
11149 X(_inc_sp,00dd, f10d0d00), \
11150 X(_lctp, 0000, f00fe001), \
11151 X(_ldmia, c800, e8900000), \
11152 X(_ldr, 6800, f8500000), \
11153 X(_ldrb, 7800, f8100000), \
11154 X(_ldrh, 8800, f8300000), \
11155 X(_ldrsb, 5600, f9100000), \
11156 X(_ldrsh, 5e00, f9300000), \
11157 X(_ldr_pc,4800, f85f0000), \
11158 X(_ldr_pc2,4800, f85f0000), \
11159 X(_ldr_sp,9800, f85d0000), \
11160 X(_le, 0000, f00fc001), \
11161 X(_letp, 0000, f01fc001), \
11162 X(_lsl, 0000, fa00f000), \
11163 X(_lsls, 0000, fa10f000), \
11164 X(_lsr, 0800, fa20f000), \
11165 X(_lsrs, 0800, fa30f000), \
11166 X(_mov, 2000, ea4f0000), \
11167 X(_movs, 2000, ea5f0000), \
11168 X(_mul, 4340, fb00f000), \
11169 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11170 X(_mvn, 43c0, ea6f0000), \
11171 X(_mvns, 43c0, ea7f0000), \
11172 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11173 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11174 X(_orr, 4300, ea400000), \
11175 X(_orrs, 4300, ea500000), \
11176 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11177 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11178 X(_rev, ba00, fa90f080), \
11179 X(_rev16, ba40, fa90f090), \
11180 X(_revsh, bac0, fa90f0b0), \
11181 X(_ror, 41c0, fa60f000), \
11182 X(_rors, 41c0, fa70f000), \
11183 X(_sbc, 4180, eb600000), \
11184 X(_sbcs, 4180, eb700000), \
11185 X(_stmia, c000, e8800000), \
11186 X(_str, 6000, f8400000), \
11187 X(_strb, 7000, f8000000), \
11188 X(_strh, 8000, f8200000), \
11189 X(_str_sp,9000, f84d0000), \
11190 X(_sub, 1e00, eba00000), \
11191 X(_subs, 1e00, ebb00000), \
11192 X(_subi, 8000, f1a00000), \
11193 X(_subis, 8000, f1b00000), \
11194 X(_sxtb, b240, fa4ff080), \
11195 X(_sxth, b200, fa0ff080), \
11196 X(_tst, 4200, ea100f00), \
11197 X(_uxtb, b2c0, fa5ff080), \
11198 X(_uxth, b280, fa1ff080), \
11199 X(_nop, bf00, f3af8000), \
11200 X(_yield, bf10, f3af8001), \
11201 X(_wfe, bf20, f3af8002), \
11202 X(_wfi, bf30, f3af8003), \
11203 X(_wls, 0000, f040c001), \
11204 X(_wlstp, 0000, f000c001), \
11205 X(_sev, bf40, f3af8004), \
11206 X(_sevl, bf50, f3af8005), \
11207 X(_udf, de00, f7f0a000)
11209 /* To catch errors in encoding functions, the codes are all offset by
11210 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11211 as 16-bit instructions. */
11212 #define X(a,b,c) T_MNEM##a
11213 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11216 #define X(a,b,c) 0x##b
11217 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11218 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11221 #define X(a,b,c) 0x##c
11222 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11223 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11224 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11228 /* Thumb instruction encoders, in alphabetical order. */
11230 /* ADDW or SUBW. */
11233 do_t_add_sub_w (void)
11237 Rd
= inst
.operands
[0].reg
;
11238 Rn
= inst
.operands
[1].reg
;
11240 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11241 is the SP-{plus,minus}-immediate form of the instruction. */
11243 constraint (Rd
== REG_PC
, BAD_PC
);
11245 reject_bad_reg (Rd
);
11247 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11248 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11251 /* Parse an add or subtract instruction. We get here with inst.instruction
11252 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11255 do_t_add_sub (void)
11259 Rd
= inst
.operands
[0].reg
;
11260 Rs
= (inst
.operands
[1].present
11261 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11262 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11265 set_pred_insn_type_last ();
11267 if (unified_syntax
)
11270 bfd_boolean narrow
;
11273 flags
= (inst
.instruction
== T_MNEM_adds
11274 || inst
.instruction
== T_MNEM_subs
);
11276 narrow
= !in_pred_block ();
11278 narrow
= in_pred_block ();
11279 if (!inst
.operands
[2].isreg
)
11283 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11284 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11286 add
= (inst
.instruction
== T_MNEM_add
11287 || inst
.instruction
== T_MNEM_adds
);
11289 if (inst
.size_req
!= 4)
11291 /* Attempt to use a narrow opcode, with relaxation if
11293 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11294 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11295 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11296 opcode
= T_MNEM_add_sp
;
11297 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11298 opcode
= T_MNEM_add_pc
;
11299 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11302 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11304 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11308 inst
.instruction
= THUMB_OP16(opcode
);
11309 inst
.instruction
|= (Rd
<< 4) | Rs
;
11310 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11311 || (inst
.relocs
[0].type
11312 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11314 if (inst
.size_req
== 2)
11315 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11317 inst
.relax
= opcode
;
11321 constraint (inst
.size_req
== 2, BAD_HIREG
);
11323 if (inst
.size_req
== 4
11324 || (inst
.size_req
!= 2 && !opcode
))
11326 constraint ((inst
.relocs
[0].type
11327 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11328 && (inst
.relocs
[0].type
11329 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11330 THUMB1_RELOC_ONLY
);
11333 constraint (add
, BAD_PC
);
11334 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11335 _("only SUBS PC, LR, #const allowed"));
11336 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11337 _("expression too complex"));
11338 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11339 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11340 _("immediate value out of range"));
11341 inst
.instruction
= T2_SUBS_PC_LR
11342 | inst
.relocs
[0].exp
.X_add_number
;
11343 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11346 else if (Rs
== REG_PC
)
11348 /* Always use addw/subw. */
11349 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11350 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11355 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11358 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11360 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11362 inst
.instruction
|= Rd
<< 8;
11363 inst
.instruction
|= Rs
<< 16;
11368 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11369 unsigned int shift
= inst
.operands
[2].shift_kind
;
11371 Rn
= inst
.operands
[2].reg
;
11372 /* See if we can do this with a 16-bit instruction. */
11373 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11375 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11380 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11381 || inst
.instruction
== T_MNEM_add
)
11383 : T_OPCODE_SUB_R3
);
11384 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11388 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11390 /* Thumb-1 cores (except v6-M) require at least one high
11391 register in a narrow non flag setting add. */
11392 if (Rd
> 7 || Rn
> 7
11393 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11394 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11401 inst
.instruction
= T_OPCODE_ADD_HI
;
11402 inst
.instruction
|= (Rd
& 8) << 4;
11403 inst
.instruction
|= (Rd
& 7);
11404 inst
.instruction
|= Rn
<< 3;
11410 constraint (Rd
== REG_PC
, BAD_PC
);
11411 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11412 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11413 constraint (Rs
== REG_PC
, BAD_PC
);
11414 reject_bad_reg (Rn
);
11416 /* If we get here, it can't be done in 16 bits. */
11417 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11418 _("shift must be constant"));
11419 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11420 inst
.instruction
|= Rd
<< 8;
11421 inst
.instruction
|= Rs
<< 16;
11422 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11423 _("shift value over 3 not allowed in thumb mode"));
11424 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11425 _("only LSL shift allowed in thumb mode"));
11426 encode_thumb32_shifted_operand (2);
11431 constraint (inst
.instruction
== T_MNEM_adds
11432 || inst
.instruction
== T_MNEM_subs
,
11435 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11437 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11438 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11441 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11442 ? 0x0000 : 0x8000);
11443 inst
.instruction
|= (Rd
<< 4) | Rs
;
11444 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11448 Rn
= inst
.operands
[2].reg
;
11449 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11451 /* We now have Rd, Rs, and Rn set to registers. */
11452 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11454 /* Can't do this for SUB. */
11455 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11456 inst
.instruction
= T_OPCODE_ADD_HI
;
11457 inst
.instruction
|= (Rd
& 8) << 4;
11458 inst
.instruction
|= (Rd
& 7);
11460 inst
.instruction
|= Rn
<< 3;
11462 inst
.instruction
|= Rs
<< 3;
11464 constraint (1, _("dest must overlap one source register"));
11468 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11469 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11470 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11480 Rd
= inst
.operands
[0].reg
;
11481 reject_bad_reg (Rd
);
11483 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11485 /* Defer to section relaxation. */
11486 inst
.relax
= inst
.instruction
;
11487 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11488 inst
.instruction
|= Rd
<< 4;
11490 else if (unified_syntax
&& inst
.size_req
!= 2)
11492 /* Generate a 32-bit opcode. */
11493 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11494 inst
.instruction
|= Rd
<< 8;
11495 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11496 inst
.relocs
[0].pc_rel
= 1;
11500 /* Generate a 16-bit opcode. */
11501 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11502 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11503 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11504 inst
.relocs
[0].pc_rel
= 1;
11505 inst
.instruction
|= Rd
<< 4;
11508 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11509 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11510 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11511 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11512 inst
.relocs
[0].exp
.X_add_number
+= 1;
11515 /* Arithmetic instructions for which there is just one 16-bit
11516 instruction encoding, and it allows only two low registers.
11517 For maximal compatibility with ARM syntax, we allow three register
11518 operands even when Thumb-32 instructions are not available, as long
11519 as the first two are identical. For instance, both "sbc r0,r1" and
11520 "sbc r0,r0,r1" are allowed. */
11526 Rd
= inst
.operands
[0].reg
;
11527 Rs
= (inst
.operands
[1].present
11528 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11529 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11530 Rn
= inst
.operands
[2].reg
;
11532 reject_bad_reg (Rd
);
11533 reject_bad_reg (Rs
);
11534 if (inst
.operands
[2].isreg
)
11535 reject_bad_reg (Rn
);
11537 if (unified_syntax
)
11539 if (!inst
.operands
[2].isreg
)
11541 /* For an immediate, we always generate a 32-bit opcode;
11542 section relaxation will shrink it later if possible. */
11543 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11544 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11545 inst
.instruction
|= Rd
<< 8;
11546 inst
.instruction
|= Rs
<< 16;
11547 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11551 bfd_boolean narrow
;
11553 /* See if we can do this with a 16-bit instruction. */
11554 if (THUMB_SETS_FLAGS (inst
.instruction
))
11555 narrow
= !in_pred_block ();
11557 narrow
= in_pred_block ();
11559 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11561 if (inst
.operands
[2].shifted
)
11563 if (inst
.size_req
== 4)
11569 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11570 inst
.instruction
|= Rd
;
11571 inst
.instruction
|= Rn
<< 3;
11575 /* If we get here, it can't be done in 16 bits. */
11576 constraint (inst
.operands
[2].shifted
11577 && inst
.operands
[2].immisreg
,
11578 _("shift must be constant"));
11579 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11580 inst
.instruction
|= Rd
<< 8;
11581 inst
.instruction
|= Rs
<< 16;
11582 encode_thumb32_shifted_operand (2);
11587 /* On its face this is a lie - the instruction does set the
11588 flags. However, the only supported mnemonic in this mode
11589 says it doesn't. */
11590 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11592 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11593 _("unshifted register required"));
11594 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11595 constraint (Rd
!= Rs
,
11596 _("dest and source1 must be the same register"));
11598 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11599 inst
.instruction
|= Rd
;
11600 inst
.instruction
|= Rn
<< 3;
11604 /* Similarly, but for instructions where the arithmetic operation is
11605 commutative, so we can allow either of them to be different from
11606 the destination operand in a 16-bit instruction. For instance, all
11607 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11614 Rd
= inst
.operands
[0].reg
;
11615 Rs
= (inst
.operands
[1].present
11616 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11617 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11618 Rn
= inst
.operands
[2].reg
;
11620 reject_bad_reg (Rd
);
11621 reject_bad_reg (Rs
);
11622 if (inst
.operands
[2].isreg
)
11623 reject_bad_reg (Rn
);
11625 if (unified_syntax
)
11627 if (!inst
.operands
[2].isreg
)
11629 /* For an immediate, we always generate a 32-bit opcode;
11630 section relaxation will shrink it later if possible. */
11631 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11632 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11633 inst
.instruction
|= Rd
<< 8;
11634 inst
.instruction
|= Rs
<< 16;
11635 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11639 bfd_boolean narrow
;
11641 /* See if we can do this with a 16-bit instruction. */
11642 if (THUMB_SETS_FLAGS (inst
.instruction
))
11643 narrow
= !in_pred_block ();
11645 narrow
= in_pred_block ();
11647 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11649 if (inst
.operands
[2].shifted
)
11651 if (inst
.size_req
== 4)
11658 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11659 inst
.instruction
|= Rd
;
11660 inst
.instruction
|= Rn
<< 3;
11665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11666 inst
.instruction
|= Rd
;
11667 inst
.instruction
|= Rs
<< 3;
11672 /* If we get here, it can't be done in 16 bits. */
11673 constraint (inst
.operands
[2].shifted
11674 && inst
.operands
[2].immisreg
,
11675 _("shift must be constant"));
11676 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11677 inst
.instruction
|= Rd
<< 8;
11678 inst
.instruction
|= Rs
<< 16;
11679 encode_thumb32_shifted_operand (2);
11684 /* On its face this is a lie - the instruction does set the
11685 flags. However, the only supported mnemonic in this mode
11686 says it doesn't. */
11687 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11689 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11690 _("unshifted register required"));
11691 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11693 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11694 inst
.instruction
|= Rd
;
11697 inst
.instruction
|= Rn
<< 3;
11699 inst
.instruction
|= Rs
<< 3;
11701 constraint (1, _("dest must overlap one source register"));
11709 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11710 constraint (msb
> 32, _("bit-field extends past end of register"));
11711 /* The instruction encoding stores the LSB and MSB,
11712 not the LSB and width. */
11713 Rd
= inst
.operands
[0].reg
;
11714 reject_bad_reg (Rd
);
11715 inst
.instruction
|= Rd
<< 8;
11716 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11717 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11718 inst
.instruction
|= msb
- 1;
11727 Rd
= inst
.operands
[0].reg
;
11728 reject_bad_reg (Rd
);
11730 /* #0 in second position is alternative syntax for bfc, which is
11731 the same instruction but with REG_PC in the Rm field. */
11732 if (!inst
.operands
[1].isreg
)
11736 Rn
= inst
.operands
[1].reg
;
11737 reject_bad_reg (Rn
);
11740 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11741 constraint (msb
> 32, _("bit-field extends past end of register"));
11742 /* The instruction encoding stores the LSB and MSB,
11743 not the LSB and width. */
11744 inst
.instruction
|= Rd
<< 8;
11745 inst
.instruction
|= Rn
<< 16;
11746 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11747 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11748 inst
.instruction
|= msb
- 1;
11756 Rd
= inst
.operands
[0].reg
;
11757 Rn
= inst
.operands
[1].reg
;
11759 reject_bad_reg (Rd
);
11760 reject_bad_reg (Rn
);
11762 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11763 _("bit-field extends past end of register"));
11764 inst
.instruction
|= Rd
<< 8;
11765 inst
.instruction
|= Rn
<< 16;
11766 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11767 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11768 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11771 /* ARM V5 Thumb BLX (argument parse)
11772 BLX <target_addr> which is BLX(1)
11773 BLX <Rm> which is BLX(2)
11774 Unfortunately, there are two different opcodes for this mnemonic.
11775 So, the insns[].value is not used, and the code here zaps values
11776 into inst.instruction.
11778 ??? How to take advantage of the additional two bits of displacement
11779 available in Thumb32 mode? Need new relocation? */
11784 set_pred_insn_type_last ();
11786 if (inst
.operands
[0].isreg
)
11788 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11789 /* We have a register, so this is BLX(2). */
11790 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11794 /* No register. This must be BLX(1). */
11795 inst
.instruction
= 0xf000e800;
11796 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11805 bfd_reloc_code_real_type reloc
;
11808 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11810 if (in_pred_block ())
11812 /* Conditional branches inside IT blocks are encoded as unconditional
11814 cond
= COND_ALWAYS
;
11819 if (cond
!= COND_ALWAYS
)
11820 opcode
= T_MNEM_bcond
;
11822 opcode
= inst
.instruction
;
11825 && (inst
.size_req
== 4
11826 || (inst
.size_req
!= 2
11827 && (inst
.operands
[0].hasreloc
11828 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11830 inst
.instruction
= THUMB_OP32(opcode
);
11831 if (cond
== COND_ALWAYS
)
11832 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11835 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11836 _("selected architecture does not support "
11837 "wide conditional branch instruction"));
11839 gas_assert (cond
!= 0xF);
11840 inst
.instruction
|= cond
<< 22;
11841 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11846 inst
.instruction
= THUMB_OP16(opcode
);
11847 if (cond
== COND_ALWAYS
)
11848 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11851 inst
.instruction
|= cond
<< 8;
11852 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11854 /* Allow section relaxation. */
11855 if (unified_syntax
&& inst
.size_req
!= 2)
11856 inst
.relax
= opcode
;
11858 inst
.relocs
[0].type
= reloc
;
11859 inst
.relocs
[0].pc_rel
= 1;
11862 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11863 between the two is the maximum immediate allowed - which is passed in
11866 do_t_bkpt_hlt1 (int range
)
11868 constraint (inst
.cond
!= COND_ALWAYS
,
11869 _("instruction is always unconditional"));
11870 if (inst
.operands
[0].present
)
11872 constraint (inst
.operands
[0].imm
> range
,
11873 _("immediate value out of range"));
11874 inst
.instruction
|= inst
.operands
[0].imm
;
11877 set_pred_insn_type (NEUTRAL_IT_INSN
);
11883 do_t_bkpt_hlt1 (63);
11889 do_t_bkpt_hlt1 (255);
11893 do_t_branch23 (void)
11895 set_pred_insn_type_last ();
11896 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11898 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11899 this file. We used to simply ignore the PLT reloc type here --
11900 the branch encoding is now needed to deal with TLSCALL relocs.
11901 So if we see a PLT reloc now, put it back to how it used to be to
11902 keep the preexisting behaviour. */
11903 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11904 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11906 #if defined(OBJ_COFF)
11907 /* If the destination of the branch is a defined symbol which does not have
11908 the THUMB_FUNC attribute, then we must be calling a function which has
11909 the (interfacearm) attribute. We look for the Thumb entry point to that
11910 function and change the branch to refer to that function instead. */
11911 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11912 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11913 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11914 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11915 inst
.relocs
[0].exp
.X_add_symbol
11916 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11923 set_pred_insn_type_last ();
11924 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11925 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11926 should cause the alignment to be checked once it is known. This is
11927 because BX PC only works if the instruction is word aligned. */
11935 set_pred_insn_type_last ();
11936 Rm
= inst
.operands
[0].reg
;
11937 reject_bad_reg (Rm
);
11938 inst
.instruction
|= Rm
<< 16;
11947 Rd
= inst
.operands
[0].reg
;
11948 Rm
= inst
.operands
[1].reg
;
11950 reject_bad_reg (Rd
);
11951 reject_bad_reg (Rm
);
11953 inst
.instruction
|= Rd
<< 8;
11954 inst
.instruction
|= Rm
<< 16;
11955 inst
.instruction
|= Rm
;
11961 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11967 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11968 inst
.instruction
|= inst
.operands
[0].imm
;
11974 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11976 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11977 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11979 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11980 inst
.instruction
= 0xf3af8000;
11981 inst
.instruction
|= imod
<< 9;
11982 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11983 if (inst
.operands
[1].present
)
11984 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11989 && (inst
.operands
[0].imm
& 4),
11990 _("selected processor does not support 'A' form "
11991 "of this instruction"));
11992 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11993 _("Thumb does not support the 2-argument "
11994 "form of this instruction"));
11995 inst
.instruction
|= inst
.operands
[0].imm
;
11999 /* THUMB CPY instruction (argument parse). */
12004 if (inst
.size_req
== 4)
12006 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12007 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12008 inst
.instruction
|= inst
.operands
[1].reg
;
12012 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12013 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12014 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12021 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12022 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12023 inst
.instruction
|= inst
.operands
[0].reg
;
12024 inst
.relocs
[0].pc_rel
= 1;
12025 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12031 inst
.instruction
|= inst
.operands
[0].imm
;
12037 unsigned Rd
, Rn
, Rm
;
12039 Rd
= inst
.operands
[0].reg
;
12040 Rn
= (inst
.operands
[1].present
12041 ? inst
.operands
[1].reg
: Rd
);
12042 Rm
= inst
.operands
[2].reg
;
12044 reject_bad_reg (Rd
);
12045 reject_bad_reg (Rn
);
12046 reject_bad_reg (Rm
);
12048 inst
.instruction
|= Rd
<< 8;
12049 inst
.instruction
|= Rn
<< 16;
12050 inst
.instruction
|= Rm
;
12056 if (unified_syntax
&& inst
.size_req
== 4)
12057 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12059 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12065 unsigned int cond
= inst
.operands
[0].imm
;
12067 set_pred_insn_type (IT_INSN
);
12068 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12069 now_pred
.cc
= cond
;
12070 now_pred
.warn_deprecated
= FALSE
;
12071 now_pred
.type
= SCALAR_PRED
;
12073 /* If the condition is a negative condition, invert the mask. */
12074 if ((cond
& 0x1) == 0x0)
12076 unsigned int mask
= inst
.instruction
& 0x000f;
12078 if ((mask
& 0x7) == 0)
12080 /* No conversion needed. */
12081 now_pred
.block_length
= 1;
12083 else if ((mask
& 0x3) == 0)
12086 now_pred
.block_length
= 2;
12088 else if ((mask
& 0x1) == 0)
12091 now_pred
.block_length
= 3;
12096 now_pred
.block_length
= 4;
12099 inst
.instruction
&= 0xfff0;
12100 inst
.instruction
|= mask
;
12103 inst
.instruction
|= cond
<< 4;
12106 /* Helper function used for both push/pop and ldm/stm. */
12108 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12109 bfd_boolean writeback
)
12111 bfd_boolean load
, store
;
12113 gas_assert (base
!= -1 || !do_io
);
12114 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12115 store
= do_io
&& !load
;
12117 if (mask
& (1 << 13))
12118 inst
.error
= _("SP not allowed in register list");
12120 if (do_io
&& (mask
& (1 << base
)) != 0
12122 inst
.error
= _("having the base register in the register list when "
12123 "using write back is UNPREDICTABLE");
12127 if (mask
& (1 << 15))
12129 if (mask
& (1 << 14))
12130 inst
.error
= _("LR and PC should not both be in register list");
12132 set_pred_insn_type_last ();
12137 if (mask
& (1 << 15))
12138 inst
.error
= _("PC not allowed in register list");
12141 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12143 /* Single register transfers implemented as str/ldr. */
12146 if (inst
.instruction
& (1 << 23))
12147 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12149 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12153 if (inst
.instruction
& (1 << 23))
12154 inst
.instruction
= 0x00800000; /* ia -> [base] */
12156 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12159 inst
.instruction
|= 0xf8400000;
12161 inst
.instruction
|= 0x00100000;
12163 mask
= ffs (mask
) - 1;
12166 else if (writeback
)
12167 inst
.instruction
|= WRITE_BACK
;
12169 inst
.instruction
|= mask
;
12171 inst
.instruction
|= base
<< 16;
12177 /* This really doesn't seem worth it. */
12178 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12179 _("expression too complex"));
12180 constraint (inst
.operands
[1].writeback
,
12181 _("Thumb load/store multiple does not support {reglist}^"));
12183 if (unified_syntax
)
12185 bfd_boolean narrow
;
12189 /* See if we can use a 16-bit instruction. */
12190 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12191 && inst
.size_req
!= 4
12192 && !(inst
.operands
[1].imm
& ~0xff))
12194 mask
= 1 << inst
.operands
[0].reg
;
12196 if (inst
.operands
[0].reg
<= 7)
12198 if (inst
.instruction
== T_MNEM_stmia
12199 ? inst
.operands
[0].writeback
12200 : (inst
.operands
[0].writeback
12201 == !(inst
.operands
[1].imm
& mask
)))
12203 if (inst
.instruction
== T_MNEM_stmia
12204 && (inst
.operands
[1].imm
& mask
)
12205 && (inst
.operands
[1].imm
& (mask
- 1)))
12206 as_warn (_("value stored for r%d is UNKNOWN"),
12207 inst
.operands
[0].reg
);
12209 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12210 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12211 inst
.instruction
|= inst
.operands
[1].imm
;
12214 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12216 /* This means 1 register in reg list one of 3 situations:
12217 1. Instruction is stmia, but without writeback.
12218 2. lmdia without writeback, but with Rn not in
12220 3. ldmia with writeback, but with Rn in reglist.
12221 Case 3 is UNPREDICTABLE behaviour, so we handle
12222 case 1 and 2 which can be converted into a 16-bit
12223 str or ldr. The SP cases are handled below. */
12224 unsigned long opcode
;
12225 /* First, record an error for Case 3. */
12226 if (inst
.operands
[1].imm
& mask
12227 && inst
.operands
[0].writeback
)
12229 _("having the base register in the register list when "
12230 "using write back is UNPREDICTABLE");
12232 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12234 inst
.instruction
= THUMB_OP16 (opcode
);
12235 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12236 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12240 else if (inst
.operands
[0] .reg
== REG_SP
)
12242 if (inst
.operands
[0].writeback
)
12245 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12246 ? T_MNEM_push
: T_MNEM_pop
);
12247 inst
.instruction
|= inst
.operands
[1].imm
;
12250 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12253 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12254 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12255 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12263 if (inst
.instruction
< 0xffff)
12264 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12266 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12267 inst
.operands
[1].imm
,
12268 inst
.operands
[0].writeback
);
12273 constraint (inst
.operands
[0].reg
> 7
12274 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12275 constraint (inst
.instruction
!= T_MNEM_ldmia
12276 && inst
.instruction
!= T_MNEM_stmia
,
12277 _("Thumb-2 instruction only valid in unified syntax"));
12278 if (inst
.instruction
== T_MNEM_stmia
)
12280 if (!inst
.operands
[0].writeback
)
12281 as_warn (_("this instruction will write back the base register"));
12282 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12283 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12284 as_warn (_("value stored for r%d is UNKNOWN"),
12285 inst
.operands
[0].reg
);
12289 if (!inst
.operands
[0].writeback
12290 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12291 as_warn (_("this instruction will write back the base register"));
12292 else if (inst
.operands
[0].writeback
12293 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12294 as_warn (_("this instruction will not write back the base register"));
12297 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12298 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12299 inst
.instruction
|= inst
.operands
[1].imm
;
12306 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12307 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12308 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12309 || inst
.operands
[1].negative
,
12312 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12315 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12316 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12322 if (!inst
.operands
[1].present
)
12324 constraint (inst
.operands
[0].reg
== REG_LR
,
12325 _("r14 not allowed as first register "
12326 "when second register is omitted"));
12327 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12329 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12332 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12333 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12334 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12340 unsigned long opcode
;
12343 if (inst
.operands
[0].isreg
12344 && !inst
.operands
[0].preind
12345 && inst
.operands
[0].reg
== REG_PC
)
12346 set_pred_insn_type_last ();
12348 opcode
= inst
.instruction
;
12349 if (unified_syntax
)
12351 if (!inst
.operands
[1].isreg
)
12353 if (opcode
<= 0xffff)
12354 inst
.instruction
= THUMB_OP32 (opcode
);
12355 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12358 if (inst
.operands
[1].isreg
12359 && !inst
.operands
[1].writeback
12360 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12361 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12362 && opcode
<= 0xffff
12363 && inst
.size_req
!= 4)
12365 /* Insn may have a 16-bit form. */
12366 Rn
= inst
.operands
[1].reg
;
12367 if (inst
.operands
[1].immisreg
)
12369 inst
.instruction
= THUMB_OP16 (opcode
);
12371 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12373 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12374 reject_bad_reg (inst
.operands
[1].imm
);
12376 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12377 && opcode
!= T_MNEM_ldrsb
)
12378 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12379 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12386 if (inst
.relocs
[0].pc_rel
)
12387 opcode
= T_MNEM_ldr_pc2
;
12389 opcode
= T_MNEM_ldr_pc
;
12393 if (opcode
== T_MNEM_ldr
)
12394 opcode
= T_MNEM_ldr_sp
;
12396 opcode
= T_MNEM_str_sp
;
12398 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12402 inst
.instruction
= inst
.operands
[0].reg
;
12403 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12405 inst
.instruction
|= THUMB_OP16 (opcode
);
12406 if (inst
.size_req
== 2)
12407 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12409 inst
.relax
= opcode
;
12413 /* Definitely a 32-bit variant. */
12415 /* Warning for Erratum 752419. */
12416 if (opcode
== T_MNEM_ldr
12417 && inst
.operands
[0].reg
== REG_SP
12418 && inst
.operands
[1].writeback
== 1
12419 && !inst
.operands
[1].immisreg
)
12421 if (no_cpu_selected ()
12422 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12423 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12424 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12425 as_warn (_("This instruction may be unpredictable "
12426 "if executed on M-profile cores "
12427 "with interrupts enabled."));
12430 /* Do some validations regarding addressing modes. */
12431 if (inst
.operands
[1].immisreg
)
12432 reject_bad_reg (inst
.operands
[1].imm
);
12434 constraint (inst
.operands
[1].writeback
== 1
12435 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12438 inst
.instruction
= THUMB_OP32 (opcode
);
12439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12440 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12441 check_ldr_r15_aligned ();
12445 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12447 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12449 /* Only [Rn,Rm] is acceptable. */
12450 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12451 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12452 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12453 || inst
.operands
[1].negative
,
12454 _("Thumb does not support this addressing mode"));
12455 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12459 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12460 if (!inst
.operands
[1].isreg
)
12461 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12464 constraint (!inst
.operands
[1].preind
12465 || inst
.operands
[1].shifted
12466 || inst
.operands
[1].writeback
,
12467 _("Thumb does not support this addressing mode"));
12468 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12470 constraint (inst
.instruction
& 0x0600,
12471 _("byte or halfword not valid for base register"));
12472 constraint (inst
.operands
[1].reg
== REG_PC
12473 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12474 _("r15 based store not allowed"));
12475 constraint (inst
.operands
[1].immisreg
,
12476 _("invalid base register for register offset"));
12478 if (inst
.operands
[1].reg
== REG_PC
)
12479 inst
.instruction
= T_OPCODE_LDR_PC
;
12480 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12481 inst
.instruction
= T_OPCODE_LDR_SP
;
12483 inst
.instruction
= T_OPCODE_STR_SP
;
12485 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12486 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12490 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12491 if (!inst
.operands
[1].immisreg
)
12493 /* Immediate offset. */
12494 inst
.instruction
|= inst
.operands
[0].reg
;
12495 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12496 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12500 /* Register offset. */
12501 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12502 constraint (inst
.operands
[1].negative
,
12503 _("Thumb does not support this addressing mode"));
12506 switch (inst
.instruction
)
12508 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12509 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12510 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12511 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12512 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12513 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12514 case 0x5600 /* ldrsb */:
12515 case 0x5e00 /* ldrsh */: break;
12519 inst
.instruction
|= inst
.operands
[0].reg
;
12520 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12521 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12527 if (!inst
.operands
[1].present
)
12529 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12530 constraint (inst
.operands
[0].reg
== REG_LR
,
12531 _("r14 not allowed here"));
12532 constraint (inst
.operands
[0].reg
== REG_R12
,
12533 _("r12 not allowed here"));
12536 if (inst
.operands
[2].writeback
12537 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12538 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12539 as_warn (_("base register written back, and overlaps "
12540 "one of transfer registers"));
12542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12543 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12544 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12550 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12551 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12557 unsigned Rd
, Rn
, Rm
, Ra
;
12559 Rd
= inst
.operands
[0].reg
;
12560 Rn
= inst
.operands
[1].reg
;
12561 Rm
= inst
.operands
[2].reg
;
12562 Ra
= inst
.operands
[3].reg
;
12564 reject_bad_reg (Rd
);
12565 reject_bad_reg (Rn
);
12566 reject_bad_reg (Rm
);
12567 reject_bad_reg (Ra
);
12569 inst
.instruction
|= Rd
<< 8;
12570 inst
.instruction
|= Rn
<< 16;
12571 inst
.instruction
|= Rm
;
12572 inst
.instruction
|= Ra
<< 12;
12578 unsigned RdLo
, RdHi
, Rn
, Rm
;
12580 RdLo
= inst
.operands
[0].reg
;
12581 RdHi
= inst
.operands
[1].reg
;
12582 Rn
= inst
.operands
[2].reg
;
12583 Rm
= inst
.operands
[3].reg
;
12585 reject_bad_reg (RdLo
);
12586 reject_bad_reg (RdHi
);
12587 reject_bad_reg (Rn
);
12588 reject_bad_reg (Rm
);
12590 inst
.instruction
|= RdLo
<< 12;
12591 inst
.instruction
|= RdHi
<< 8;
12592 inst
.instruction
|= Rn
<< 16;
12593 inst
.instruction
|= Rm
;
12597 do_t_mov_cmp (void)
12601 Rn
= inst
.operands
[0].reg
;
12602 Rm
= inst
.operands
[1].reg
;
12605 set_pred_insn_type_last ();
12607 if (unified_syntax
)
12609 int r0off
= (inst
.instruction
== T_MNEM_mov
12610 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12611 unsigned long opcode
;
12612 bfd_boolean narrow
;
12613 bfd_boolean low_regs
;
12615 low_regs
= (Rn
<= 7 && Rm
<= 7);
12616 opcode
= inst
.instruction
;
12617 if (in_pred_block ())
12618 narrow
= opcode
!= T_MNEM_movs
;
12620 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12621 if (inst
.size_req
== 4
12622 || inst
.operands
[1].shifted
)
12625 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12626 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12627 && !inst
.operands
[1].shifted
12631 inst
.instruction
= T2_SUBS_PC_LR
;
12635 if (opcode
== T_MNEM_cmp
)
12637 constraint (Rn
== REG_PC
, BAD_PC
);
12640 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12642 warn_deprecated_sp (Rm
);
12643 /* R15 was documented as a valid choice for Rm in ARMv6,
12644 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12645 tools reject R15, so we do too. */
12646 constraint (Rm
== REG_PC
, BAD_PC
);
12649 reject_bad_reg (Rm
);
12651 else if (opcode
== T_MNEM_mov
12652 || opcode
== T_MNEM_movs
)
12654 if (inst
.operands
[1].isreg
)
12656 if (opcode
== T_MNEM_movs
)
12658 reject_bad_reg (Rn
);
12659 reject_bad_reg (Rm
);
12663 /* This is mov.n. */
12664 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12665 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12667 as_tsktsk (_("Use of r%u as a source register is "
12668 "deprecated when r%u is the destination "
12669 "register."), Rm
, Rn
);
12674 /* This is mov.w. */
12675 constraint (Rn
== REG_PC
, BAD_PC
);
12676 constraint (Rm
== REG_PC
, BAD_PC
);
12677 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12678 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12682 reject_bad_reg (Rn
);
12685 if (!inst
.operands
[1].isreg
)
12687 /* Immediate operand. */
12688 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12690 if (low_regs
&& narrow
)
12692 inst
.instruction
= THUMB_OP16 (opcode
);
12693 inst
.instruction
|= Rn
<< 8;
12694 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12695 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12697 if (inst
.size_req
== 2)
12698 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12700 inst
.relax
= opcode
;
12705 constraint ((inst
.relocs
[0].type
12706 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12707 && (inst
.relocs
[0].type
12708 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12709 THUMB1_RELOC_ONLY
);
12711 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12712 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12713 inst
.instruction
|= Rn
<< r0off
;
12714 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12717 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12718 && (inst
.instruction
== T_MNEM_mov
12719 || inst
.instruction
== T_MNEM_movs
))
12721 /* Register shifts are encoded as separate shift instructions. */
12722 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12724 if (in_pred_block ())
12729 if (inst
.size_req
== 4)
12732 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12738 switch (inst
.operands
[1].shift_kind
)
12741 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12744 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12747 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12750 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12756 inst
.instruction
= opcode
;
12759 inst
.instruction
|= Rn
;
12760 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12765 inst
.instruction
|= CONDS_BIT
;
12767 inst
.instruction
|= Rn
<< 8;
12768 inst
.instruction
|= Rm
<< 16;
12769 inst
.instruction
|= inst
.operands
[1].imm
;
12774 /* Some mov with immediate shift have narrow variants.
12775 Register shifts are handled above. */
12776 if (low_regs
&& inst
.operands
[1].shifted
12777 && (inst
.instruction
== T_MNEM_mov
12778 || inst
.instruction
== T_MNEM_movs
))
12780 if (in_pred_block ())
12781 narrow
= (inst
.instruction
== T_MNEM_mov
);
12783 narrow
= (inst
.instruction
== T_MNEM_movs
);
12788 switch (inst
.operands
[1].shift_kind
)
12790 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12791 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12792 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12793 default: narrow
= FALSE
; break;
12799 inst
.instruction
|= Rn
;
12800 inst
.instruction
|= Rm
<< 3;
12801 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12806 inst
.instruction
|= Rn
<< r0off
;
12807 encode_thumb32_shifted_operand (1);
12811 switch (inst
.instruction
)
12814 /* In v4t or v5t a move of two lowregs produces unpredictable
12815 results. Don't allow this. */
12818 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12819 "MOV Rd, Rs with two low registers is not "
12820 "permitted on this architecture");
12821 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12825 inst
.instruction
= T_OPCODE_MOV_HR
;
12826 inst
.instruction
|= (Rn
& 0x8) << 4;
12827 inst
.instruction
|= (Rn
& 0x7);
12828 inst
.instruction
|= Rm
<< 3;
12832 /* We know we have low registers at this point.
12833 Generate LSLS Rd, Rs, #0. */
12834 inst
.instruction
= T_OPCODE_LSL_I
;
12835 inst
.instruction
|= Rn
;
12836 inst
.instruction
|= Rm
<< 3;
12842 inst
.instruction
= T_OPCODE_CMP_LR
;
12843 inst
.instruction
|= Rn
;
12844 inst
.instruction
|= Rm
<< 3;
12848 inst
.instruction
= T_OPCODE_CMP_HR
;
12849 inst
.instruction
|= (Rn
& 0x8) << 4;
12850 inst
.instruction
|= (Rn
& 0x7);
12851 inst
.instruction
|= Rm
<< 3;
12858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12860 /* PR 10443: Do not silently ignore shifted operands. */
12861 constraint (inst
.operands
[1].shifted
,
12862 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12864 if (inst
.operands
[1].isreg
)
12866 if (Rn
< 8 && Rm
< 8)
12868 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12869 since a MOV instruction produces unpredictable results. */
12870 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12871 inst
.instruction
= T_OPCODE_ADD_I3
;
12873 inst
.instruction
= T_OPCODE_CMP_LR
;
12875 inst
.instruction
|= Rn
;
12876 inst
.instruction
|= Rm
<< 3;
12880 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12881 inst
.instruction
= T_OPCODE_MOV_HR
;
12883 inst
.instruction
= T_OPCODE_CMP_HR
;
12889 constraint (Rn
> 7,
12890 _("only lo regs allowed with immediate"));
12891 inst
.instruction
|= Rn
<< 8;
12892 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12903 top
= (inst
.instruction
& 0x00800000) != 0;
12904 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12906 constraint (top
, _(":lower16: not allowed in this instruction"));
12907 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12909 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12911 constraint (!top
, _(":upper16: not allowed in this instruction"));
12912 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12915 Rd
= inst
.operands
[0].reg
;
12916 reject_bad_reg (Rd
);
12918 inst
.instruction
|= Rd
<< 8;
12919 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12921 imm
= inst
.relocs
[0].exp
.X_add_number
;
12922 inst
.instruction
|= (imm
& 0xf000) << 4;
12923 inst
.instruction
|= (imm
& 0x0800) << 15;
12924 inst
.instruction
|= (imm
& 0x0700) << 4;
12925 inst
.instruction
|= (imm
& 0x00ff);
12930 do_t_mvn_tst (void)
12934 Rn
= inst
.operands
[0].reg
;
12935 Rm
= inst
.operands
[1].reg
;
12937 if (inst
.instruction
== T_MNEM_cmp
12938 || inst
.instruction
== T_MNEM_cmn
)
12939 constraint (Rn
== REG_PC
, BAD_PC
);
12941 reject_bad_reg (Rn
);
12942 reject_bad_reg (Rm
);
12944 if (unified_syntax
)
12946 int r0off
= (inst
.instruction
== T_MNEM_mvn
12947 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12948 bfd_boolean narrow
;
12950 if (inst
.size_req
== 4
12951 || inst
.instruction
> 0xffff
12952 || inst
.operands
[1].shifted
12953 || Rn
> 7 || Rm
> 7)
12955 else if (inst
.instruction
== T_MNEM_cmn
12956 || inst
.instruction
== T_MNEM_tst
)
12958 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12959 narrow
= !in_pred_block ();
12961 narrow
= in_pred_block ();
12963 if (!inst
.operands
[1].isreg
)
12965 /* For an immediate, we always generate a 32-bit opcode;
12966 section relaxation will shrink it later if possible. */
12967 if (inst
.instruction
< 0xffff)
12968 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12969 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12970 inst
.instruction
|= Rn
<< r0off
;
12971 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12975 /* See if we can do this with a 16-bit instruction. */
12978 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12979 inst
.instruction
|= Rn
;
12980 inst
.instruction
|= Rm
<< 3;
12984 constraint (inst
.operands
[1].shifted
12985 && inst
.operands
[1].immisreg
,
12986 _("shift must be constant"));
12987 if (inst
.instruction
< 0xffff)
12988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12989 inst
.instruction
|= Rn
<< r0off
;
12990 encode_thumb32_shifted_operand (1);
12996 constraint (inst
.instruction
> 0xffff
12997 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12998 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12999 _("unshifted register required"));
13000 constraint (Rn
> 7 || Rm
> 7,
13003 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13004 inst
.instruction
|= Rn
;
13005 inst
.instruction
|= Rm
<< 3;
13014 if (do_vfp_nsyn_mrs () == SUCCESS
)
13017 Rd
= inst
.operands
[0].reg
;
13018 reject_bad_reg (Rd
);
13019 inst
.instruction
|= Rd
<< 8;
13021 if (inst
.operands
[1].isreg
)
13023 unsigned br
= inst
.operands
[1].reg
;
13024 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13025 as_bad (_("bad register for mrs"));
13027 inst
.instruction
|= br
& (0xf << 16);
13028 inst
.instruction
|= (br
& 0x300) >> 4;
13029 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13033 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13035 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13037 /* PR gas/12698: The constraint is only applied for m_profile.
13038 If the user has specified -march=all, we want to ignore it as
13039 we are building for any CPU type, including non-m variants. */
13040 bfd_boolean m_profile
=
13041 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13042 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13043 "not support requested special purpose register"));
13046 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13048 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13049 _("'APSR', 'CPSR' or 'SPSR' expected"));
13051 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13052 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13053 inst
.instruction
|= 0xf0000;
13063 if (do_vfp_nsyn_msr () == SUCCESS
)
13066 constraint (!inst
.operands
[1].isreg
,
13067 _("Thumb encoding does not support an immediate here"));
13069 if (inst
.operands
[0].isreg
)
13070 flags
= (int)(inst
.operands
[0].reg
);
13072 flags
= inst
.operands
[0].imm
;
13074 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13076 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13078 /* PR gas/12698: The constraint is only applied for m_profile.
13079 If the user has specified -march=all, we want to ignore it as
13080 we are building for any CPU type, including non-m variants. */
13081 bfd_boolean m_profile
=
13082 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13083 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13084 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13085 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13086 && bits
!= PSR_f
)) && m_profile
,
13087 _("selected processor does not support requested special "
13088 "purpose register"));
13091 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13092 "requested special purpose register"));
13094 Rn
= inst
.operands
[1].reg
;
13095 reject_bad_reg (Rn
);
13097 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13098 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13099 inst
.instruction
|= (flags
& 0x300) >> 4;
13100 inst
.instruction
|= (flags
& 0xff);
13101 inst
.instruction
|= Rn
<< 16;
13107 bfd_boolean narrow
;
13108 unsigned Rd
, Rn
, Rm
;
13110 if (!inst
.operands
[2].present
)
13111 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13113 Rd
= inst
.operands
[0].reg
;
13114 Rn
= inst
.operands
[1].reg
;
13115 Rm
= inst
.operands
[2].reg
;
13117 if (unified_syntax
)
13119 if (inst
.size_req
== 4
13125 else if (inst
.instruction
== T_MNEM_muls
)
13126 narrow
= !in_pred_block ();
13128 narrow
= in_pred_block ();
13132 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13133 constraint (Rn
> 7 || Rm
> 7,
13140 /* 16-bit MULS/Conditional MUL. */
13141 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13142 inst
.instruction
|= Rd
;
13145 inst
.instruction
|= Rm
<< 3;
13147 inst
.instruction
|= Rn
<< 3;
13149 constraint (1, _("dest must overlap one source register"));
13153 constraint (inst
.instruction
!= T_MNEM_mul
,
13154 _("Thumb-2 MUL must not set flags"));
13156 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13157 inst
.instruction
|= Rd
<< 8;
13158 inst
.instruction
|= Rn
<< 16;
13159 inst
.instruction
|= Rm
<< 0;
13161 reject_bad_reg (Rd
);
13162 reject_bad_reg (Rn
);
13163 reject_bad_reg (Rm
);
13170 unsigned RdLo
, RdHi
, Rn
, Rm
;
13172 RdLo
= inst
.operands
[0].reg
;
13173 RdHi
= inst
.operands
[1].reg
;
13174 Rn
= inst
.operands
[2].reg
;
13175 Rm
= inst
.operands
[3].reg
;
13177 reject_bad_reg (RdLo
);
13178 reject_bad_reg (RdHi
);
13179 reject_bad_reg (Rn
);
13180 reject_bad_reg (Rm
);
13182 inst
.instruction
|= RdLo
<< 12;
13183 inst
.instruction
|= RdHi
<< 8;
13184 inst
.instruction
|= Rn
<< 16;
13185 inst
.instruction
|= Rm
;
13188 as_tsktsk (_("rdhi and rdlo must be different"));
13194 set_pred_insn_type (NEUTRAL_IT_INSN
);
13196 if (unified_syntax
)
13198 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13200 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13201 inst
.instruction
|= inst
.operands
[0].imm
;
13205 /* PR9722: Check for Thumb2 availability before
13206 generating a thumb2 nop instruction. */
13207 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13209 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13210 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13213 inst
.instruction
= 0x46c0;
13218 constraint (inst
.operands
[0].present
,
13219 _("Thumb does not support NOP with hints"));
13220 inst
.instruction
= 0x46c0;
13227 if (unified_syntax
)
13229 bfd_boolean narrow
;
13231 if (THUMB_SETS_FLAGS (inst
.instruction
))
13232 narrow
= !in_pred_block ();
13234 narrow
= in_pred_block ();
13235 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13237 if (inst
.size_req
== 4)
13242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13243 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13244 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13248 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13249 inst
.instruction
|= inst
.operands
[0].reg
;
13250 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13255 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13257 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13259 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13260 inst
.instruction
|= inst
.operands
[0].reg
;
13261 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13270 Rd
= inst
.operands
[0].reg
;
13271 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13273 reject_bad_reg (Rd
);
13274 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13275 reject_bad_reg (Rn
);
13277 inst
.instruction
|= Rd
<< 8;
13278 inst
.instruction
|= Rn
<< 16;
13280 if (!inst
.operands
[2].isreg
)
13282 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13283 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13289 Rm
= inst
.operands
[2].reg
;
13290 reject_bad_reg (Rm
);
13292 constraint (inst
.operands
[2].shifted
13293 && inst
.operands
[2].immisreg
,
13294 _("shift must be constant"));
13295 encode_thumb32_shifted_operand (2);
13302 unsigned Rd
, Rn
, Rm
;
13304 Rd
= inst
.operands
[0].reg
;
13305 Rn
= inst
.operands
[1].reg
;
13306 Rm
= inst
.operands
[2].reg
;
13308 reject_bad_reg (Rd
);
13309 reject_bad_reg (Rn
);
13310 reject_bad_reg (Rm
);
13312 inst
.instruction
|= Rd
<< 8;
13313 inst
.instruction
|= Rn
<< 16;
13314 inst
.instruction
|= Rm
;
13315 if (inst
.operands
[3].present
)
13317 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13318 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13319 _("expression too complex"));
13320 inst
.instruction
|= (val
& 0x1c) << 10;
13321 inst
.instruction
|= (val
& 0x03) << 6;
13328 if (!inst
.operands
[3].present
)
13332 inst
.instruction
&= ~0x00000020;
13334 /* PR 10168. Swap the Rm and Rn registers. */
13335 Rtmp
= inst
.operands
[1].reg
;
13336 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13337 inst
.operands
[2].reg
= Rtmp
;
13345 if (inst
.operands
[0].immisreg
)
13346 reject_bad_reg (inst
.operands
[0].imm
);
13348 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13352 do_t_push_pop (void)
13356 constraint (inst
.operands
[0].writeback
,
13357 _("push/pop do not support {reglist}^"));
13358 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13359 _("expression too complex"));
13361 mask
= inst
.operands
[0].imm
;
13362 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13363 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13364 else if (inst
.size_req
!= 4
13365 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13366 ? REG_LR
: REG_PC
)))
13368 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13369 inst
.instruction
|= THUMB_PP_PC_LR
;
13370 inst
.instruction
|= mask
& 0xff;
13372 else if (unified_syntax
)
13374 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13375 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13379 inst
.error
= _("invalid register list to push/pop instruction");
13387 if (unified_syntax
)
13388 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13391 inst
.error
= _("invalid register list to push/pop instruction");
13397 do_t_vscclrm (void)
13399 if (inst
.operands
[0].issingle
)
13401 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13402 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13403 inst
.instruction
|= inst
.operands
[0].imm
;
13407 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13408 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13409 inst
.instruction
|= 1 << 8;
13410 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13419 Rd
= inst
.operands
[0].reg
;
13420 Rm
= inst
.operands
[1].reg
;
13422 reject_bad_reg (Rd
);
13423 reject_bad_reg (Rm
);
13425 inst
.instruction
|= Rd
<< 8;
13426 inst
.instruction
|= Rm
<< 16;
13427 inst
.instruction
|= Rm
;
13435 Rd
= inst
.operands
[0].reg
;
13436 Rm
= inst
.operands
[1].reg
;
13438 reject_bad_reg (Rd
);
13439 reject_bad_reg (Rm
);
13441 if (Rd
<= 7 && Rm
<= 7
13442 && inst
.size_req
!= 4)
13444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13445 inst
.instruction
|= Rd
;
13446 inst
.instruction
|= Rm
<< 3;
13448 else if (unified_syntax
)
13450 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13451 inst
.instruction
|= Rd
<< 8;
13452 inst
.instruction
|= Rm
<< 16;
13453 inst
.instruction
|= Rm
;
13456 inst
.error
= BAD_HIREG
;
13464 Rd
= inst
.operands
[0].reg
;
13465 Rm
= inst
.operands
[1].reg
;
13467 reject_bad_reg (Rd
);
13468 reject_bad_reg (Rm
);
13470 inst
.instruction
|= Rd
<< 8;
13471 inst
.instruction
|= Rm
;
13479 Rd
= inst
.operands
[0].reg
;
13480 Rs
= (inst
.operands
[1].present
13481 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13482 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13484 reject_bad_reg (Rd
);
13485 reject_bad_reg (Rs
);
13486 if (inst
.operands
[2].isreg
)
13487 reject_bad_reg (inst
.operands
[2].reg
);
13489 inst
.instruction
|= Rd
<< 8;
13490 inst
.instruction
|= Rs
<< 16;
13491 if (!inst
.operands
[2].isreg
)
13493 bfd_boolean narrow
;
13495 if ((inst
.instruction
& 0x00100000) != 0)
13496 narrow
= !in_pred_block ();
13498 narrow
= in_pred_block ();
13500 if (Rd
> 7 || Rs
> 7)
13503 if (inst
.size_req
== 4 || !unified_syntax
)
13506 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13507 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13510 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13511 relaxation, but it doesn't seem worth the hassle. */
13514 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13515 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13516 inst
.instruction
|= Rs
<< 3;
13517 inst
.instruction
|= Rd
;
13521 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13522 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13526 encode_thumb32_shifted_operand (2);
13532 if (warn_on_deprecated
13533 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13534 as_tsktsk (_("setend use is deprecated for ARMv8"));
13536 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13537 if (inst
.operands
[0].imm
)
13538 inst
.instruction
|= 0x8;
13544 if (!inst
.operands
[1].present
)
13545 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13547 if (unified_syntax
)
13549 bfd_boolean narrow
;
13552 switch (inst
.instruction
)
13555 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13557 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13559 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13561 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13565 if (THUMB_SETS_FLAGS (inst
.instruction
))
13566 narrow
= !in_pred_block ();
13568 narrow
= in_pred_block ();
13569 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13571 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13573 if (inst
.operands
[2].isreg
13574 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13575 || inst
.operands
[2].reg
> 7))
13577 if (inst
.size_req
== 4)
13580 reject_bad_reg (inst
.operands
[0].reg
);
13581 reject_bad_reg (inst
.operands
[1].reg
);
13585 if (inst
.operands
[2].isreg
)
13587 reject_bad_reg (inst
.operands
[2].reg
);
13588 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13589 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13590 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13591 inst
.instruction
|= inst
.operands
[2].reg
;
13593 /* PR 12854: Error on extraneous shifts. */
13594 constraint (inst
.operands
[2].shifted
,
13595 _("extraneous shift as part of operand to shift insn"));
13599 inst
.operands
[1].shifted
= 1;
13600 inst
.operands
[1].shift_kind
= shift_kind
;
13601 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13602 ? T_MNEM_movs
: T_MNEM_mov
);
13603 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13604 encode_thumb32_shifted_operand (1);
13605 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13606 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13611 if (inst
.operands
[2].isreg
)
13613 switch (shift_kind
)
13615 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13616 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13617 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13618 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13622 inst
.instruction
|= inst
.operands
[0].reg
;
13623 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13625 /* PR 12854: Error on extraneous shifts. */
13626 constraint (inst
.operands
[2].shifted
,
13627 _("extraneous shift as part of operand to shift insn"));
13631 switch (shift_kind
)
13633 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13634 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13635 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13638 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13639 inst
.instruction
|= inst
.operands
[0].reg
;
13640 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13646 constraint (inst
.operands
[0].reg
> 7
13647 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13648 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13650 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13652 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13653 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13654 _("source1 and dest must be same register"));
13656 switch (inst
.instruction
)
13658 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13659 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13660 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13661 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13665 inst
.instruction
|= inst
.operands
[0].reg
;
13666 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13668 /* PR 12854: Error on extraneous shifts. */
13669 constraint (inst
.operands
[2].shifted
,
13670 _("extraneous shift as part of operand to shift insn"));
13674 switch (inst
.instruction
)
13676 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13677 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13678 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13679 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13682 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13683 inst
.instruction
|= inst
.operands
[0].reg
;
13684 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13692 unsigned Rd
, Rn
, Rm
;
13694 Rd
= inst
.operands
[0].reg
;
13695 Rn
= inst
.operands
[1].reg
;
13696 Rm
= inst
.operands
[2].reg
;
13698 reject_bad_reg (Rd
);
13699 reject_bad_reg (Rn
);
13700 reject_bad_reg (Rm
);
13702 inst
.instruction
|= Rd
<< 8;
13703 inst
.instruction
|= Rn
<< 16;
13704 inst
.instruction
|= Rm
;
13710 unsigned Rd
, Rn
, Rm
;
13712 Rd
= inst
.operands
[0].reg
;
13713 Rm
= inst
.operands
[1].reg
;
13714 Rn
= inst
.operands
[2].reg
;
13716 reject_bad_reg (Rd
);
13717 reject_bad_reg (Rn
);
13718 reject_bad_reg (Rm
);
13720 inst
.instruction
|= Rd
<< 8;
13721 inst
.instruction
|= Rn
<< 16;
13722 inst
.instruction
|= Rm
;
13728 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13730 _("SMC is not permitted on this architecture"));
13731 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13732 _("expression too complex"));
13733 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13734 inst
.instruction
|= (value
& 0xf000) >> 12;
13735 inst
.instruction
|= (value
& 0x0ff0);
13736 inst
.instruction
|= (value
& 0x000f) << 16;
13737 /* PR gas/15623: SMC instructions must be last in an IT block. */
13738 set_pred_insn_type_last ();
13744 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13746 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13747 inst
.instruction
|= (value
& 0x0fff);
13748 inst
.instruction
|= (value
& 0xf000) << 4;
13752 do_t_ssat_usat (int bias
)
13756 Rd
= inst
.operands
[0].reg
;
13757 Rn
= inst
.operands
[2].reg
;
13759 reject_bad_reg (Rd
);
13760 reject_bad_reg (Rn
);
13762 inst
.instruction
|= Rd
<< 8;
13763 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13764 inst
.instruction
|= Rn
<< 16;
13766 if (inst
.operands
[3].present
)
13768 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13770 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13772 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13773 _("expression too complex"));
13775 if (shift_amount
!= 0)
13777 constraint (shift_amount
> 31,
13778 _("shift expression is too large"));
13780 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13781 inst
.instruction
|= 0x00200000; /* sh bit. */
13783 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13784 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13792 do_t_ssat_usat (1);
13800 Rd
= inst
.operands
[0].reg
;
13801 Rn
= inst
.operands
[2].reg
;
13803 reject_bad_reg (Rd
);
13804 reject_bad_reg (Rn
);
13806 inst
.instruction
|= Rd
<< 8;
13807 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13808 inst
.instruction
|= Rn
<< 16;
13814 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13815 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13816 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13817 || inst
.operands
[2].negative
,
13820 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13822 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13823 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13824 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13825 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13831 if (!inst
.operands
[2].present
)
13832 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13834 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13835 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13836 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13839 inst
.instruction
|= inst
.operands
[0].reg
;
13840 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13841 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13842 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13848 unsigned Rd
, Rn
, Rm
;
13850 Rd
= inst
.operands
[0].reg
;
13851 Rn
= inst
.operands
[1].reg
;
13852 Rm
= inst
.operands
[2].reg
;
13854 reject_bad_reg (Rd
);
13855 reject_bad_reg (Rn
);
13856 reject_bad_reg (Rm
);
13858 inst
.instruction
|= Rd
<< 8;
13859 inst
.instruction
|= Rn
<< 16;
13860 inst
.instruction
|= Rm
;
13861 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13869 Rd
= inst
.operands
[0].reg
;
13870 Rm
= inst
.operands
[1].reg
;
13872 reject_bad_reg (Rd
);
13873 reject_bad_reg (Rm
);
13875 if (inst
.instruction
<= 0xffff
13876 && inst
.size_req
!= 4
13877 && Rd
<= 7 && Rm
<= 7
13878 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13880 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13881 inst
.instruction
|= Rd
;
13882 inst
.instruction
|= Rm
<< 3;
13884 else if (unified_syntax
)
13886 if (inst
.instruction
<= 0xffff)
13887 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13888 inst
.instruction
|= Rd
<< 8;
13889 inst
.instruction
|= Rm
;
13890 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13894 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13895 _("Thumb encoding does not support rotation"));
13896 constraint (1, BAD_HIREG
);
13903 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13912 half
= (inst
.instruction
& 0x10) != 0;
13913 set_pred_insn_type_last ();
13914 constraint (inst
.operands
[0].immisreg
,
13915 _("instruction requires register index"));
13917 Rn
= inst
.operands
[0].reg
;
13918 Rm
= inst
.operands
[0].imm
;
13920 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13921 constraint (Rn
== REG_SP
, BAD_SP
);
13922 reject_bad_reg (Rm
);
13924 constraint (!half
&& inst
.operands
[0].shifted
,
13925 _("instruction does not allow shifted index"));
13926 inst
.instruction
|= (Rn
<< 16) | Rm
;
13932 if (!inst
.operands
[0].present
)
13933 inst
.operands
[0].imm
= 0;
13935 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13937 constraint (inst
.size_req
== 2,
13938 _("immediate value out of range"));
13939 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13940 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13941 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13945 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13946 inst
.instruction
|= inst
.operands
[0].imm
;
13949 set_pred_insn_type (NEUTRAL_IT_INSN
);
13956 do_t_ssat_usat (0);
13964 Rd
= inst
.operands
[0].reg
;
13965 Rn
= inst
.operands
[2].reg
;
13967 reject_bad_reg (Rd
);
13968 reject_bad_reg (Rn
);
13970 inst
.instruction
|= Rd
<< 8;
13971 inst
.instruction
|= inst
.operands
[1].imm
;
13972 inst
.instruction
|= Rn
<< 16;
13975 /* Checking the range of the branch offset (VAL) with NBITS bits
13976 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13978 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13980 gas_assert (nbits
> 0 && nbits
<= 32);
13983 int cmp
= (1 << (nbits
- 1));
13984 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13989 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13995 /* For branches in Armv8.1-M Mainline. */
13997 do_t_branch_future (void)
13999 unsigned long insn
= inst
.instruction
;
14001 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14002 if (inst
.operands
[0].hasreloc
== 0)
14004 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14005 as_bad (BAD_BRANCH_OFF
);
14007 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14011 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14012 inst
.relocs
[0].pc_rel
= 1;
14018 if (inst
.operands
[1].hasreloc
== 0)
14020 int val
= inst
.operands
[1].imm
;
14021 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14022 as_bad (BAD_BRANCH_OFF
);
14024 int immA
= (val
& 0x0001f000) >> 12;
14025 int immB
= (val
& 0x00000ffc) >> 2;
14026 int immC
= (val
& 0x00000002) >> 1;
14027 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14031 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14032 inst
.relocs
[1].pc_rel
= 1;
14037 if (inst
.operands
[1].hasreloc
== 0)
14039 int val
= inst
.operands
[1].imm
;
14040 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14041 as_bad (BAD_BRANCH_OFF
);
14043 int immA
= (val
& 0x0007f000) >> 12;
14044 int immB
= (val
& 0x00000ffc) >> 2;
14045 int immC
= (val
& 0x00000002) >> 1;
14046 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14050 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14051 inst
.relocs
[1].pc_rel
= 1;
14055 case T_MNEM_bfcsel
:
14057 if (inst
.operands
[1].hasreloc
== 0)
14059 int val
= inst
.operands
[1].imm
;
14060 int immA
= (val
& 0x00001000) >> 12;
14061 int immB
= (val
& 0x00000ffc) >> 2;
14062 int immC
= (val
& 0x00000002) >> 1;
14063 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14067 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14068 inst
.relocs
[1].pc_rel
= 1;
14072 if (inst
.operands
[2].hasreloc
== 0)
14074 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14075 int val2
= inst
.operands
[2].imm
;
14076 int val0
= inst
.operands
[0].imm
& 0x1f;
14077 int diff
= val2
- val0
;
14079 inst
.instruction
|= 1 << 17; /* T bit. */
14080 else if (diff
!= 2)
14081 as_bad (_("out of range label-relative fixup value"));
14085 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14086 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14087 inst
.relocs
[2].pc_rel
= 1;
14091 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14092 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14104 /* Helper function for do_t_loloop to handle relocations. */
14106 v8_1_loop_reloc (int is_le
)
14108 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14110 int value
= inst
.relocs
[0].exp
.X_add_number
;
14111 value
= (is_le
) ? -value
: value
;
14113 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14114 as_bad (BAD_BRANCH_OFF
);
14118 immh
= (value
& 0x00000ffc) >> 2;
14119 imml
= (value
& 0x00000002) >> 1;
14121 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14125 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14126 inst
.relocs
[0].pc_rel
= 1;
14130 /* For shifts in MVE. */
14132 do_mve_scalar_shift (void)
14134 if (!inst
.operands
[2].present
)
14136 inst
.operands
[2] = inst
.operands
[1];
14137 inst
.operands
[1].reg
= 0xf;
14140 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14141 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14143 if (inst
.operands
[2].isreg
)
14145 /* Assuming Rm is already checked not to be 11x1. */
14146 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14147 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14148 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14152 /* Assuming imm is already checked as [1,32]. */
14153 unsigned int value
= inst
.operands
[2].imm
;
14154 inst
.instruction
|= (value
& 0x1c) << 10;
14155 inst
.instruction
|= (value
& 0x03) << 6;
14156 /* Change last 4 bits from 0xd to 0xf. */
14157 inst
.instruction
|= 0x2;
14161 /* MVE instruction encoder helpers. */
14162 #define M_MNEM_vabav 0xee800f01
14163 #define M_MNEM_vmladav 0xeef00e00
14164 #define M_MNEM_vmladava 0xeef00e20
14165 #define M_MNEM_vmladavx 0xeef01e00
14166 #define M_MNEM_vmladavax 0xeef01e20
14167 #define M_MNEM_vmlsdav 0xeef00e01
14168 #define M_MNEM_vmlsdava 0xeef00e21
14169 #define M_MNEM_vmlsdavx 0xeef01e01
14170 #define M_MNEM_vmlsdavax 0xeef01e21
14171 #define M_MNEM_vmullt 0xee011e00
14172 #define M_MNEM_vmullb 0xee010e00
14173 #define M_MNEM_vst20 0xfc801e00
14174 #define M_MNEM_vst21 0xfc801e20
14175 #define M_MNEM_vst40 0xfc801e01
14176 #define M_MNEM_vst41 0xfc801e21
14177 #define M_MNEM_vst42 0xfc801e41
14178 #define M_MNEM_vst43 0xfc801e61
14179 #define M_MNEM_vld20 0xfc901e00
14180 #define M_MNEM_vld21 0xfc901e20
14181 #define M_MNEM_vld40 0xfc901e01
14182 #define M_MNEM_vld41 0xfc901e21
14183 #define M_MNEM_vld42 0xfc901e41
14184 #define M_MNEM_vld43 0xfc901e61
14185 #define M_MNEM_vstrb 0xec000e00
14186 #define M_MNEM_vstrh 0xec000e10
14187 #define M_MNEM_vstrw 0xec000e40
14188 #define M_MNEM_vstrd 0xec000e50
14189 #define M_MNEM_vldrb 0xec100e00
14190 #define M_MNEM_vldrh 0xec100e10
14191 #define M_MNEM_vldrw 0xec100e40
14192 #define M_MNEM_vldrd 0xec100e50
14193 #define M_MNEM_vmovlt 0xeea01f40
14194 #define M_MNEM_vmovlb 0xeea00f40
14195 #define M_MNEM_vmovnt 0xfe311e81
14196 #define M_MNEM_vmovnb 0xfe310e81
14197 #define M_MNEM_vadc 0xee300f00
14198 #define M_MNEM_vadci 0xee301f00
14199 #define M_MNEM_vbrsr 0xfe011e60
14200 #define M_MNEM_vaddlv 0xee890f00
14201 #define M_MNEM_vaddlva 0xee890f20
14202 #define M_MNEM_vaddv 0xeef10f00
14203 #define M_MNEM_vaddva 0xeef10f20
14204 #define M_MNEM_vddup 0xee011f6e
14205 #define M_MNEM_vdwdup 0xee011f60
14206 #define M_MNEM_vidup 0xee010f6e
14207 #define M_MNEM_viwdup 0xee010f60
14208 #define M_MNEM_vmaxv 0xeee20f00
14209 #define M_MNEM_vmaxav 0xeee00f00
14210 #define M_MNEM_vminv 0xeee20f80
14211 #define M_MNEM_vminav 0xeee00f80
14212 #define M_MNEM_vmlaldav 0xee800e00
14213 #define M_MNEM_vmlaldava 0xee800e20
14214 #define M_MNEM_vmlaldavx 0xee801e00
14215 #define M_MNEM_vmlaldavax 0xee801e20
14216 #define M_MNEM_vmlsldav 0xee800e01
14217 #define M_MNEM_vmlsldava 0xee800e21
14218 #define M_MNEM_vmlsldavx 0xee801e01
14219 #define M_MNEM_vmlsldavax 0xee801e21
14220 #define M_MNEM_vrmlaldavhx 0xee801f00
14221 #define M_MNEM_vrmlaldavhax 0xee801f20
14222 #define M_MNEM_vrmlsldavh 0xfe800e01
14223 #define M_MNEM_vrmlsldavha 0xfe800e21
14224 #define M_MNEM_vrmlsldavhx 0xfe801e01
14225 #define M_MNEM_vrmlsldavhax 0xfe801e21
14226 #define M_MNEM_vqmovnt 0xee331e01
14227 #define M_MNEM_vqmovnb 0xee330e01
14228 #define M_MNEM_vqmovunt 0xee311e81
14229 #define M_MNEM_vqmovunb 0xee310e81
14230 #define M_MNEM_vshrnt 0xee801fc1
14231 #define M_MNEM_vshrnb 0xee800fc1
14232 #define M_MNEM_vrshrnt 0xfe801fc1
14233 #define M_MNEM_vqshrnt 0xee801f40
14234 #define M_MNEM_vqshrnb 0xee800f40
14235 #define M_MNEM_vqshrunt 0xee801fc0
14236 #define M_MNEM_vqshrunb 0xee800fc0
14237 #define M_MNEM_vrshrnb 0xfe800fc1
14238 #define M_MNEM_vqrshrnt 0xee801f41
14239 #define M_MNEM_vqrshrnb 0xee800f41
14240 #define M_MNEM_vqrshrunt 0xfe801fc0
14241 #define M_MNEM_vqrshrunb 0xfe800fc0
14243 /* Neon instruction encoder helpers. */
14245 /* Encodings for the different types for various Neon opcodes. */
14247 /* An "invalid" code for the following tables. */
14250 struct neon_tab_entry
14253 unsigned float_or_poly
;
14254 unsigned scalar_or_imm
;
14257 /* Map overloaded Neon opcodes to their respective encodings. */
14258 #define NEON_ENC_TAB \
14259 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14260 X(vabdl, 0x0800700, N_INV, N_INV), \
14261 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14262 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14263 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14264 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14265 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14266 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14267 X(vaddl, 0x0800000, N_INV, N_INV), \
14268 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14269 X(vsubl, 0x0800200, N_INV, N_INV), \
14270 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14271 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14272 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14273 /* Register variants of the following two instructions are encoded as
14274 vcge / vcgt with the operands reversed. */ \
14275 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14276 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14277 X(vfma, N_INV, 0x0000c10, N_INV), \
14278 X(vfms, N_INV, 0x0200c10, N_INV), \
14279 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14280 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14281 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14282 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14283 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14284 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14285 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14286 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14287 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14288 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14289 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14290 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14291 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14292 X(vshl, 0x0000400, N_INV, 0x0800510), \
14293 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14294 X(vand, 0x0000110, N_INV, 0x0800030), \
14295 X(vbic, 0x0100110, N_INV, 0x0800030), \
14296 X(veor, 0x1000110, N_INV, N_INV), \
14297 X(vorn, 0x0300110, N_INV, 0x0800010), \
14298 X(vorr, 0x0200110, N_INV, 0x0800010), \
14299 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14300 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14301 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14302 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14303 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14304 X(vst1, 0x0000000, 0x0800000, N_INV), \
14305 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14306 X(vst2, 0x0000100, 0x0800100, N_INV), \
14307 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14308 X(vst3, 0x0000200, 0x0800200, N_INV), \
14309 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14310 X(vst4, 0x0000300, 0x0800300, N_INV), \
14311 X(vmovn, 0x1b20200, N_INV, N_INV), \
14312 X(vtrn, 0x1b20080, N_INV, N_INV), \
14313 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14314 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14315 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14316 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14317 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14318 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14319 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14320 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14321 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14322 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14323 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14324 X(vseleq, 0xe000a00, N_INV, N_INV), \
14325 X(vselvs, 0xe100a00, N_INV, N_INV), \
14326 X(vselge, 0xe200a00, N_INV, N_INV), \
14327 X(vselgt, 0xe300a00, N_INV, N_INV), \
14328 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14329 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14330 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14331 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14332 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14333 X(aes, 0x3b00300, N_INV, N_INV), \
14334 X(sha3op, 0x2000c00, N_INV, N_INV), \
14335 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14336 X(sha2op, 0x3ba0380, N_INV, N_INV)
14340 #define X(OPC,I,F,S) N_MNEM_##OPC
14345 static const struct neon_tab_entry neon_enc_tab
[] =
14347 #define X(OPC,I,F,S) { (I), (F), (S) }
14352 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14353 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14354 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14355 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14356 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14357 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14358 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14359 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14360 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14361 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14362 #define NEON_ENC_SINGLE_(X) \
14363 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14364 #define NEON_ENC_DOUBLE_(X) \
14365 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14366 #define NEON_ENC_FPV8_(X) \
14367 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14369 #define NEON_ENCODE(type, inst) \
14372 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14373 inst.is_neon = 1; \
14377 #define check_neon_suffixes \
14380 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14382 as_bad (_("invalid neon suffix for non neon instruction")); \
14388 /* Define shapes for instruction operands. The following mnemonic characters
14389 are used in this table:
14391 F - VFP S<n> register
14392 D - Neon D<n> register
14393 Q - Neon Q<n> register
14397 L - D<n> register list
14399 This table is used to generate various data:
14400 - enumerations of the form NS_DDR to be used as arguments to
14402 - a table classifying shapes into single, double, quad, mixed.
14403 - a table used to drive neon_select_shape. */
14405 #define NEON_SHAPE_DEF \
14406 X(4, (R, R, Q, Q), QUAD), \
14407 X(4, (Q, R, R, I), QUAD), \
14408 X(4, (R, R, S, S), QUAD), \
14409 X(4, (S, S, R, R), QUAD), \
14410 X(3, (Q, R, I), QUAD), \
14411 X(3, (I, Q, Q), QUAD), \
14412 X(3, (I, Q, R), QUAD), \
14413 X(3, (R, Q, Q), QUAD), \
14414 X(3, (D, D, D), DOUBLE), \
14415 X(3, (Q, Q, Q), QUAD), \
14416 X(3, (D, D, I), DOUBLE), \
14417 X(3, (Q, Q, I), QUAD), \
14418 X(3, (D, D, S), DOUBLE), \
14419 X(3, (Q, Q, S), QUAD), \
14420 X(3, (Q, Q, R), QUAD), \
14421 X(3, (R, R, Q), QUAD), \
14422 X(2, (R, Q), QUAD), \
14423 X(2, (D, D), DOUBLE), \
14424 X(2, (Q, Q), QUAD), \
14425 X(2, (D, S), DOUBLE), \
14426 X(2, (Q, S), QUAD), \
14427 X(2, (D, R), DOUBLE), \
14428 X(2, (Q, R), QUAD), \
14429 X(2, (D, I), DOUBLE), \
14430 X(2, (Q, I), QUAD), \
14431 X(3, (D, L, D), DOUBLE), \
14432 X(2, (D, Q), MIXED), \
14433 X(2, (Q, D), MIXED), \
14434 X(3, (D, Q, I), MIXED), \
14435 X(3, (Q, D, I), MIXED), \
14436 X(3, (Q, D, D), MIXED), \
14437 X(3, (D, Q, Q), MIXED), \
14438 X(3, (Q, Q, D), MIXED), \
14439 X(3, (Q, D, S), MIXED), \
14440 X(3, (D, Q, S), MIXED), \
14441 X(4, (D, D, D, I), DOUBLE), \
14442 X(4, (Q, Q, Q, I), QUAD), \
14443 X(4, (D, D, S, I), DOUBLE), \
14444 X(4, (Q, Q, S, I), QUAD), \
14445 X(2, (F, F), SINGLE), \
14446 X(3, (F, F, F), SINGLE), \
14447 X(2, (F, I), SINGLE), \
14448 X(2, (F, D), MIXED), \
14449 X(2, (D, F), MIXED), \
14450 X(3, (F, F, I), MIXED), \
14451 X(4, (R, R, F, F), SINGLE), \
14452 X(4, (F, F, R, R), SINGLE), \
14453 X(3, (D, R, R), DOUBLE), \
14454 X(3, (R, R, D), DOUBLE), \
14455 X(2, (S, R), SINGLE), \
14456 X(2, (R, S), SINGLE), \
14457 X(2, (F, R), SINGLE), \
14458 X(2, (R, F), SINGLE), \
14459 /* Used for MVE tail predicated loop instructions. */\
14460 X(2, (R, R), QUAD), \
14461 /* Half float shape supported so far. */\
14462 X (2, (H, D), MIXED), \
14463 X (2, (D, H), MIXED), \
14464 X (2, (H, F), MIXED), \
14465 X (2, (F, H), MIXED), \
14466 X (2, (H, H), HALF), \
14467 X (2, (H, R), HALF), \
14468 X (2, (R, H), HALF), \
14469 X (2, (H, I), HALF), \
14470 X (3, (H, H, H), HALF), \
14471 X (3, (H, F, I), MIXED), \
14472 X (3, (F, H, I), MIXED), \
14473 X (3, (D, H, H), MIXED), \
14474 X (3, (D, H, S), MIXED)
14476 #define S2(A,B) NS_##A##B
14477 #define S3(A,B,C) NS_##A##B##C
14478 #define S4(A,B,C,D) NS_##A##B##C##D
14480 #define X(N, L, C) S##N L
14493 enum neon_shape_class
14502 #define X(N, L, C) SC_##C
14504 static enum neon_shape_class neon_shape_class
[] =
14523 /* Register widths of above. */
14524 static unsigned neon_shape_el_size
[] =
14536 struct neon_shape_info
14539 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14542 #define S2(A,B) { SE_##A, SE_##B }
14543 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14544 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14546 #define X(N, L, C) { N, S##N L }
14548 static struct neon_shape_info neon_shape_tab
[] =
14558 /* Bit masks used in type checking given instructions.
14559 'N_EQK' means the type must be the same as (or based on in some way) the key
14560 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14561 set, various other bits can be set as well in order to modify the meaning of
14562 the type constraint. */
14564 enum neon_type_mask
14588 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14589 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14590 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14591 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14592 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14593 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14594 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14595 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14596 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14597 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14598 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14600 N_MAX_NONSPECIAL
= N_P64
14603 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14605 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14606 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14607 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14608 #define N_S_32 (N_S8 | N_S16 | N_S32)
14609 #define N_F_16_32 (N_F16 | N_F32)
14610 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14611 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14612 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14613 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14614 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14615 #define N_F_MVE (N_F16 | N_F32)
14616 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14618 /* Pass this as the first type argument to neon_check_type to ignore types
14620 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14622 /* Select a "shape" for the current instruction (describing register types or
14623 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14624 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14625 function of operand parsing, so this function doesn't need to be called.
14626 Shapes should be listed in order of decreasing length. */
14628 static enum neon_shape
14629 neon_select_shape (enum neon_shape shape
, ...)
14632 enum neon_shape first_shape
= shape
;
14634 /* Fix missing optional operands. FIXME: we don't know at this point how
14635 many arguments we should have, so this makes the assumption that we have
14636 > 1. This is true of all current Neon opcodes, I think, but may not be
14637 true in the future. */
14638 if (!inst
.operands
[1].present
)
14639 inst
.operands
[1] = inst
.operands
[0];
14641 va_start (ap
, shape
);
14643 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14648 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14650 if (!inst
.operands
[j
].present
)
14656 switch (neon_shape_tab
[shape
].el
[j
])
14658 /* If a .f16, .16, .u16, .s16 type specifier is given over
14659 a VFP single precision register operand, it's essentially
14660 means only half of the register is used.
14662 If the type specifier is given after the mnemonics, the
14663 information is stored in inst.vectype. If the type specifier
14664 is given after register operand, the information is stored
14665 in inst.operands[].vectype.
14667 When there is only one type specifier, and all the register
14668 operands are the same type of hardware register, the type
14669 specifier applies to all register operands.
14671 If no type specifier is given, the shape is inferred from
14672 operand information.
14675 vadd.f16 s0, s1, s2: NS_HHH
14676 vabs.f16 s0, s1: NS_HH
14677 vmov.f16 s0, r1: NS_HR
14678 vmov.f16 r0, s1: NS_RH
14679 vcvt.f16 r0, s1: NS_RH
14680 vcvt.f16.s32 s2, s2, #29: NS_HFI
14681 vcvt.f16.s32 s2, s2: NS_HF
14684 if (!(inst
.operands
[j
].isreg
14685 && inst
.operands
[j
].isvec
14686 && inst
.operands
[j
].issingle
14687 && !inst
.operands
[j
].isquad
14688 && ((inst
.vectype
.elems
== 1
14689 && inst
.vectype
.el
[0].size
== 16)
14690 || (inst
.vectype
.elems
> 1
14691 && inst
.vectype
.el
[j
].size
== 16)
14692 || (inst
.vectype
.elems
== 0
14693 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14694 && inst
.operands
[j
].vectype
.size
== 16))))
14699 if (!(inst
.operands
[j
].isreg
14700 && inst
.operands
[j
].isvec
14701 && inst
.operands
[j
].issingle
14702 && !inst
.operands
[j
].isquad
14703 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14704 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14705 || (inst
.vectype
.elems
== 0
14706 && (inst
.operands
[j
].vectype
.size
== 32
14707 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14712 if (!(inst
.operands
[j
].isreg
14713 && inst
.operands
[j
].isvec
14714 && !inst
.operands
[j
].isquad
14715 && !inst
.operands
[j
].issingle
))
14720 if (!(inst
.operands
[j
].isreg
14721 && !inst
.operands
[j
].isvec
))
14726 if (!(inst
.operands
[j
].isreg
14727 && inst
.operands
[j
].isvec
14728 && inst
.operands
[j
].isquad
14729 && !inst
.operands
[j
].issingle
))
14734 if (!(!inst
.operands
[j
].isreg
14735 && !inst
.operands
[j
].isscalar
))
14740 if (!(!inst
.operands
[j
].isreg
14741 && inst
.operands
[j
].isscalar
))
14751 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14752 /* We've matched all the entries in the shape table, and we don't
14753 have any left over operands which have not been matched. */
14759 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14760 first_error (_("invalid instruction shape"));
14765 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14766 means the Q bit should be set). */
14769 neon_quad (enum neon_shape shape
)
14771 return neon_shape_class
[shape
] == SC_QUAD
;
14775 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14778 /* Allow modification to be made to types which are constrained to be
14779 based on the key element, based on bits set alongside N_EQK. */
14780 if ((typebits
& N_EQK
) != 0)
14782 if ((typebits
& N_HLF
) != 0)
14784 else if ((typebits
& N_DBL
) != 0)
14786 if ((typebits
& N_SGN
) != 0)
14787 *g_type
= NT_signed
;
14788 else if ((typebits
& N_UNS
) != 0)
14789 *g_type
= NT_unsigned
;
14790 else if ((typebits
& N_INT
) != 0)
14791 *g_type
= NT_integer
;
14792 else if ((typebits
& N_FLT
) != 0)
14793 *g_type
= NT_float
;
14794 else if ((typebits
& N_SIZ
) != 0)
14795 *g_type
= NT_untyped
;
14799 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14800 operand type, i.e. the single type specified in a Neon instruction when it
14801 is the only one given. */
14803 static struct neon_type_el
14804 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14806 struct neon_type_el dest
= *key
;
14808 gas_assert ((thisarg
& N_EQK
) != 0);
14810 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14815 /* Convert Neon type and size into compact bitmask representation. */
14817 static enum neon_type_mask
14818 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14825 case 8: return N_8
;
14826 case 16: return N_16
;
14827 case 32: return N_32
;
14828 case 64: return N_64
;
14836 case 8: return N_I8
;
14837 case 16: return N_I16
;
14838 case 32: return N_I32
;
14839 case 64: return N_I64
;
14847 case 16: return N_F16
;
14848 case 32: return N_F32
;
14849 case 64: return N_F64
;
14857 case 8: return N_P8
;
14858 case 16: return N_P16
;
14859 case 64: return N_P64
;
14867 case 8: return N_S8
;
14868 case 16: return N_S16
;
14869 case 32: return N_S32
;
14870 case 64: return N_S64
;
14878 case 8: return N_U8
;
14879 case 16: return N_U16
;
14880 case 32: return N_U32
;
14881 case 64: return N_U64
;
14892 /* Convert compact Neon bitmask type representation to a type and size. Only
14893 handles the case where a single bit is set in the mask. */
14896 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14897 enum neon_type_mask mask
)
14899 if ((mask
& N_EQK
) != 0)
14902 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14904 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14906 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14908 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14913 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14915 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14916 *type
= NT_unsigned
;
14917 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14918 *type
= NT_integer
;
14919 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14920 *type
= NT_untyped
;
14921 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14923 else if ((mask
& (N_F_ALL
)) != 0)
14931 /* Modify a bitmask of allowed types. This is only needed for type
14935 modify_types_allowed (unsigned allowed
, unsigned mods
)
14938 enum neon_el_type type
;
14944 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14946 if (el_type_of_type_chk (&type
, &size
,
14947 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14949 neon_modify_type_size (mods
, &type
, &size
);
14950 destmask
|= type_chk_of_el_type (type
, size
);
14957 /* Check type and return type classification.
14958 The manual states (paraphrase): If one datatype is given, it indicates the
14960 - the second operand, if there is one
14961 - the operand, if there is no second operand
14962 - the result, if there are no operands.
14963 This isn't quite good enough though, so we use a concept of a "key" datatype
14964 which is set on a per-instruction basis, which is the one which matters when
14965 only one data type is written.
14966 Note: this function has side-effects (e.g. filling in missing operands). All
14967 Neon instructions should call it before performing bit encoding. */
14969 static struct neon_type_el
14970 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14973 unsigned i
, pass
, key_el
= 0;
14974 unsigned types
[NEON_MAX_TYPE_ELS
];
14975 enum neon_el_type k_type
= NT_invtype
;
14976 unsigned k_size
= -1u;
14977 struct neon_type_el badtype
= {NT_invtype
, -1};
14978 unsigned key_allowed
= 0;
14980 /* Optional registers in Neon instructions are always (not) in operand 1.
14981 Fill in the missing operand here, if it was omitted. */
14982 if (els
> 1 && !inst
.operands
[1].present
)
14983 inst
.operands
[1] = inst
.operands
[0];
14985 /* Suck up all the varargs. */
14987 for (i
= 0; i
< els
; i
++)
14989 unsigned thisarg
= va_arg (ap
, unsigned);
14990 if (thisarg
== N_IGNORE_TYPE
)
14995 types
[i
] = thisarg
;
14996 if ((thisarg
& N_KEY
) != 0)
15001 if (inst
.vectype
.elems
> 0)
15002 for (i
= 0; i
< els
; i
++)
15003 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15005 first_error (_("types specified in both the mnemonic and operands"));
15009 /* Duplicate inst.vectype elements here as necessary.
15010 FIXME: No idea if this is exactly the same as the ARM assembler,
15011 particularly when an insn takes one register and one non-register
15013 if (inst
.vectype
.elems
== 1 && els
> 1)
15016 inst
.vectype
.elems
= els
;
15017 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15018 for (j
= 0; j
< els
; j
++)
15020 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15023 else if (inst
.vectype
.elems
== 0 && els
> 0)
15026 /* No types were given after the mnemonic, so look for types specified
15027 after each operand. We allow some flexibility here; as long as the
15028 "key" operand has a type, we can infer the others. */
15029 for (j
= 0; j
< els
; j
++)
15030 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15031 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15033 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15035 for (j
= 0; j
< els
; j
++)
15036 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15037 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15042 first_error (_("operand types can't be inferred"));
15046 else if (inst
.vectype
.elems
!= els
)
15048 first_error (_("type specifier has the wrong number of parts"));
15052 for (pass
= 0; pass
< 2; pass
++)
15054 for (i
= 0; i
< els
; i
++)
15056 unsigned thisarg
= types
[i
];
15057 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15058 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15059 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15060 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15062 /* Decay more-specific signed & unsigned types to sign-insensitive
15063 integer types if sign-specific variants are unavailable. */
15064 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15065 && (types_allowed
& N_SU_ALL
) == 0)
15066 g_type
= NT_integer
;
15068 /* If only untyped args are allowed, decay any more specific types to
15069 them. Some instructions only care about signs for some element
15070 sizes, so handle that properly. */
15071 if (((types_allowed
& N_UNT
) == 0)
15072 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15073 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15074 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15075 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15076 g_type
= NT_untyped
;
15080 if ((thisarg
& N_KEY
) != 0)
15084 key_allowed
= thisarg
& ~N_KEY
;
15086 /* Check architecture constraint on FP16 extension. */
15088 && k_type
== NT_float
15089 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15091 inst
.error
= _(BAD_FP16
);
15098 if ((thisarg
& N_VFP
) != 0)
15100 enum neon_shape_el regshape
;
15101 unsigned regwidth
, match
;
15103 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15106 first_error (_("invalid instruction shape"));
15109 regshape
= neon_shape_tab
[ns
].el
[i
];
15110 regwidth
= neon_shape_el_size
[regshape
];
15112 /* In VFP mode, operands must match register widths. If we
15113 have a key operand, use its width, else use the width of
15114 the current operand. */
15120 /* FP16 will use a single precision register. */
15121 if (regwidth
== 32 && match
== 16)
15123 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15127 inst
.error
= _(BAD_FP16
);
15132 if (regwidth
!= match
)
15134 first_error (_("operand size must match register width"));
15139 if ((thisarg
& N_EQK
) == 0)
15141 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15143 if ((given_type
& types_allowed
) == 0)
15145 first_error (BAD_SIMD_TYPE
);
15151 enum neon_el_type mod_k_type
= k_type
;
15152 unsigned mod_k_size
= k_size
;
15153 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15154 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15156 first_error (_("inconsistent types in Neon instruction"));
15164 return inst
.vectype
.el
[key_el
];
15167 /* Neon-style VFP instruction forwarding. */
15169 /* Thumb VFP instructions have 0xE in the condition field. */
15172 do_vfp_cond_or_thumb (void)
15177 inst
.instruction
|= 0xe0000000;
15179 inst
.instruction
|= inst
.cond
<< 28;
15182 /* Look up and encode a simple mnemonic, for use as a helper function for the
15183 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15184 etc. It is assumed that operand parsing has already been done, and that the
15185 operands are in the form expected by the given opcode (this isn't necessarily
15186 the same as the form in which they were parsed, hence some massaging must
15187 take place before this function is called).
15188 Checks current arch version against that in the looked-up opcode. */
15191 do_vfp_nsyn_opcode (const char *opname
)
15193 const struct asm_opcode
*opcode
;
15195 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15200 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15201 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15208 inst
.instruction
= opcode
->tvalue
;
15209 opcode
->tencode ();
15213 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15214 opcode
->aencode ();
15219 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15221 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15223 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15226 do_vfp_nsyn_opcode ("fadds");
15228 do_vfp_nsyn_opcode ("fsubs");
15230 /* ARMv8.2 fp16 instruction. */
15232 do_scalar_fp16_v82_encode ();
15237 do_vfp_nsyn_opcode ("faddd");
15239 do_vfp_nsyn_opcode ("fsubd");
15243 /* Check operand types to see if this is a VFP instruction, and if so call
15247 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15249 enum neon_shape rs
;
15250 struct neon_type_el et
;
15255 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15256 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15260 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15261 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15262 N_F_ALL
| N_KEY
| N_VFP
);
15269 if (et
.type
!= NT_invtype
)
15280 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15282 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15284 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15287 do_vfp_nsyn_opcode ("fmacs");
15289 do_vfp_nsyn_opcode ("fnmacs");
15291 /* ARMv8.2 fp16 instruction. */
15293 do_scalar_fp16_v82_encode ();
15298 do_vfp_nsyn_opcode ("fmacd");
15300 do_vfp_nsyn_opcode ("fnmacd");
15305 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15307 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15309 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15312 do_vfp_nsyn_opcode ("ffmas");
15314 do_vfp_nsyn_opcode ("ffnmas");
15316 /* ARMv8.2 fp16 instruction. */
15318 do_scalar_fp16_v82_encode ();
15323 do_vfp_nsyn_opcode ("ffmad");
15325 do_vfp_nsyn_opcode ("ffnmad");
15330 do_vfp_nsyn_mul (enum neon_shape rs
)
15332 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15334 do_vfp_nsyn_opcode ("fmuls");
15336 /* ARMv8.2 fp16 instruction. */
15338 do_scalar_fp16_v82_encode ();
15341 do_vfp_nsyn_opcode ("fmuld");
15345 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15347 int is_neg
= (inst
.instruction
& 0x80) != 0;
15348 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15350 if (rs
== NS_FF
|| rs
== NS_HH
)
15353 do_vfp_nsyn_opcode ("fnegs");
15355 do_vfp_nsyn_opcode ("fabss");
15357 /* ARMv8.2 fp16 instruction. */
15359 do_scalar_fp16_v82_encode ();
15364 do_vfp_nsyn_opcode ("fnegd");
15366 do_vfp_nsyn_opcode ("fabsd");
15370 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15371 insns belong to Neon, and are handled elsewhere. */
15374 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15376 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15380 do_vfp_nsyn_opcode ("fldmdbs");
15382 do_vfp_nsyn_opcode ("fldmias");
15387 do_vfp_nsyn_opcode ("fstmdbs");
15389 do_vfp_nsyn_opcode ("fstmias");
15394 do_vfp_nsyn_sqrt (void)
15396 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15397 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15399 if (rs
== NS_FF
|| rs
== NS_HH
)
15401 do_vfp_nsyn_opcode ("fsqrts");
15403 /* ARMv8.2 fp16 instruction. */
15405 do_scalar_fp16_v82_encode ();
15408 do_vfp_nsyn_opcode ("fsqrtd");
15412 do_vfp_nsyn_div (void)
15414 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15415 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15416 N_F_ALL
| N_KEY
| N_VFP
);
15418 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15420 do_vfp_nsyn_opcode ("fdivs");
15422 /* ARMv8.2 fp16 instruction. */
15424 do_scalar_fp16_v82_encode ();
15427 do_vfp_nsyn_opcode ("fdivd");
15431 do_vfp_nsyn_nmul (void)
15433 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15434 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15435 N_F_ALL
| N_KEY
| N_VFP
);
15437 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15439 NEON_ENCODE (SINGLE
, inst
);
15440 do_vfp_sp_dyadic ();
15442 /* ARMv8.2 fp16 instruction. */
15444 do_scalar_fp16_v82_encode ();
15448 NEON_ENCODE (DOUBLE
, inst
);
15449 do_vfp_dp_rd_rn_rm ();
15451 do_vfp_cond_or_thumb ();
15455 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15459 neon_logbits (unsigned x
)
15461 return ffs (x
) - 4;
15464 #define LOW4(R) ((R) & 0xf)
15465 #define HI1(R) (((R) >> 4) & 1)
15468 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15473 first_error (BAD_EL_TYPE
);
15476 switch (inst
.operands
[0].imm
)
15479 first_error (_("invalid condition"));
15501 /* only accept eq and ne. */
15502 if (inst
.operands
[0].imm
> 1)
15504 first_error (_("invalid condition"));
15507 return inst
.operands
[0].imm
;
15509 if (inst
.operands
[0].imm
== 0x2)
15511 else if (inst
.operands
[0].imm
== 0x8)
15515 first_error (_("invalid condition"));
15519 switch (inst
.operands
[0].imm
)
15522 first_error (_("invalid condition"));
15538 /* Should be unreachable. */
15545 /* We are dealing with a vector predicated block. */
15546 if (inst
.operands
[0].present
)
15548 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15549 struct neon_type_el et
15550 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15553 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15555 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15557 if (et
.type
== NT_invtype
)
15560 if (et
.type
== NT_float
)
15562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15564 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15565 inst
.instruction
|= (et
.size
== 16) << 28;
15566 inst
.instruction
|= 0x3 << 20;
15570 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15572 inst
.instruction
|= 1 << 28;
15573 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15576 if (inst
.operands
[2].isquad
)
15578 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15579 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15580 inst
.instruction
|= (fcond
& 0x2) >> 1;
15584 if (inst
.operands
[2].reg
== REG_SP
)
15585 as_tsktsk (MVE_BAD_SP
);
15586 inst
.instruction
|= 1 << 6;
15587 inst
.instruction
|= (fcond
& 0x2) << 4;
15588 inst
.instruction
|= inst
.operands
[2].reg
;
15590 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15591 inst
.instruction
|= (fcond
& 0x4) << 10;
15592 inst
.instruction
|= (fcond
& 0x1) << 7;
15595 set_pred_insn_type (VPT_INSN
);
15597 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15598 | ((inst
.instruction
& 0xe000) >> 13);
15599 now_pred
.warn_deprecated
= FALSE
;
15600 now_pred
.type
= VECTOR_PRED
;
15607 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15608 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15609 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15610 if (!inst
.operands
[2].present
)
15611 first_error (_("MVE vector or ARM register expected"));
15612 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15614 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15615 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15616 && inst
.operands
[1].isquad
)
15618 inst
.instruction
= N_MNEM_vcmp
;
15622 if (inst
.cond
> COND_ALWAYS
)
15623 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15625 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15627 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15628 struct neon_type_el et
15629 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15632 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15633 && !inst
.operands
[2].iszr
, BAD_PC
);
15635 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15637 inst
.instruction
= 0xee010f00;
15638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15639 inst
.instruction
|= (fcond
& 0x4) << 10;
15640 inst
.instruction
|= (fcond
& 0x1) << 7;
15641 if (et
.type
== NT_float
)
15643 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15645 inst
.instruction
|= (et
.size
== 16) << 28;
15646 inst
.instruction
|= 0x3 << 20;
15650 inst
.instruction
|= 1 << 28;
15651 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15653 if (inst
.operands
[2].isquad
)
15655 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15656 inst
.instruction
|= (fcond
& 0x2) >> 1;
15657 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15661 if (inst
.operands
[2].reg
== REG_SP
)
15662 as_tsktsk (MVE_BAD_SP
);
15663 inst
.instruction
|= 1 << 6;
15664 inst
.instruction
|= (fcond
& 0x2) << 4;
15665 inst
.instruction
|= inst
.operands
[2].reg
;
15673 do_mve_vmaxa_vmina (void)
15675 if (inst
.cond
> COND_ALWAYS
)
15676 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15678 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15680 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15681 struct neon_type_el et
15682 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15684 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15685 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15693 do_mve_vfmas (void)
15695 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15696 struct neon_type_el et
15697 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15699 if (inst
.cond
> COND_ALWAYS
)
15700 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15702 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15704 if (inst
.operands
[2].reg
== REG_SP
)
15705 as_tsktsk (MVE_BAD_SP
);
15706 else if (inst
.operands
[2].reg
== REG_PC
)
15707 as_tsktsk (MVE_BAD_PC
);
15709 inst
.instruction
|= (et
.size
== 16) << 28;
15710 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15711 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15712 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15714 inst
.instruction
|= inst
.operands
[2].reg
;
15719 do_mve_viddup (void)
15721 if (inst
.cond
> COND_ALWAYS
)
15722 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15724 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15726 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15727 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15728 _("immediate must be either 1, 2, 4 or 8"));
15730 enum neon_shape rs
;
15731 struct neon_type_el et
;
15733 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15735 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15736 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15741 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15742 if (inst
.operands
[2].reg
== REG_SP
)
15743 as_tsktsk (MVE_BAD_SP
);
15744 else if (inst
.operands
[2].reg
== REG_PC
)
15745 first_error (BAD_PC
);
15747 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15748 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15749 Rm
= inst
.operands
[2].reg
>> 1;
15751 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15752 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15753 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15754 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15755 inst
.instruction
|= (imm
> 2) << 7;
15756 inst
.instruction
|= Rm
<< 1;
15757 inst
.instruction
|= (imm
== 2 || imm
== 8);
15762 do_mve_vmlas (void)
15764 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15765 struct neon_type_el et
15766 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15768 if (inst
.operands
[2].reg
== REG_PC
)
15769 as_tsktsk (MVE_BAD_PC
);
15770 else if (inst
.operands
[2].reg
== REG_SP
)
15771 as_tsktsk (MVE_BAD_SP
);
15773 if (inst
.cond
> COND_ALWAYS
)
15774 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15776 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15778 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15779 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15780 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15781 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15782 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15784 inst
.instruction
|= inst
.operands
[2].reg
;
15789 do_mve_vshll (void)
15791 struct neon_type_el et
15792 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15794 if (inst
.cond
> COND_ALWAYS
)
15795 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15797 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15799 int imm
= inst
.operands
[2].imm
;
15800 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15801 _("immediate value out of range"));
15803 if ((unsigned)imm
== et
.size
)
15805 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15806 inst
.instruction
|= 0x110001;
15810 inst
.instruction
|= (et
.size
+ imm
) << 16;
15811 inst
.instruction
|= 0x800140;
15814 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15815 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15816 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15817 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15818 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15823 do_mve_vshlc (void)
15825 if (inst
.cond
> COND_ALWAYS
)
15826 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15828 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15830 if (inst
.operands
[1].reg
== REG_PC
)
15831 as_tsktsk (MVE_BAD_PC
);
15832 else if (inst
.operands
[1].reg
== REG_SP
)
15833 as_tsktsk (MVE_BAD_SP
);
15835 int imm
= inst
.operands
[2].imm
;
15836 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15839 inst
.instruction
|= (imm
& 0x1f) << 16;
15840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15841 inst
.instruction
|= inst
.operands
[1].reg
;
15846 do_mve_vshrn (void)
15849 switch (inst
.instruction
)
15851 case M_MNEM_vshrnt
:
15852 case M_MNEM_vshrnb
:
15853 case M_MNEM_vrshrnt
:
15854 case M_MNEM_vrshrnb
:
15855 types
= N_I16
| N_I32
;
15857 case M_MNEM_vqshrnt
:
15858 case M_MNEM_vqshrnb
:
15859 case M_MNEM_vqrshrnt
:
15860 case M_MNEM_vqrshrnb
:
15861 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15863 case M_MNEM_vqshrunt
:
15864 case M_MNEM_vqshrunb
:
15865 case M_MNEM_vqrshrunt
:
15866 case M_MNEM_vqrshrunb
:
15867 types
= N_S16
| N_S32
;
15873 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15875 if (inst
.cond
> COND_ALWAYS
)
15876 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15878 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15880 unsigned Qd
= inst
.operands
[0].reg
;
15881 unsigned Qm
= inst
.operands
[1].reg
;
15882 unsigned imm
= inst
.operands
[2].imm
;
15883 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15885 ? _("immediate operand expected in the range [1,8]")
15886 : _("immediate operand expected in the range [1,16]"));
15888 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15889 inst
.instruction
|= HI1 (Qd
) << 22;
15890 inst
.instruction
|= (et
.size
- imm
) << 16;
15891 inst
.instruction
|= LOW4 (Qd
) << 12;
15892 inst
.instruction
|= HI1 (Qm
) << 5;
15893 inst
.instruction
|= LOW4 (Qm
);
15898 do_mve_vqmovn (void)
15900 struct neon_type_el et
;
15901 if (inst
.instruction
== M_MNEM_vqmovnt
15902 || inst
.instruction
== M_MNEM_vqmovnb
)
15903 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15904 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15906 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15908 if (inst
.cond
> COND_ALWAYS
)
15909 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15911 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15913 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15914 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15915 inst
.instruction
|= (et
.size
== 32) << 18;
15916 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15917 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15918 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15923 do_mve_vpsel (void)
15925 neon_select_shape (NS_QQQ
, NS_NULL
);
15927 if (inst
.cond
> COND_ALWAYS
)
15928 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15930 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15932 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15933 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15934 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15935 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15936 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15937 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15942 do_mve_vpnot (void)
15944 if (inst
.cond
> COND_ALWAYS
)
15945 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15947 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15951 do_mve_vmaxnma_vminnma (void)
15953 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15954 struct neon_type_el et
15955 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15957 if (inst
.cond
> COND_ALWAYS
)
15958 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15960 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15962 inst
.instruction
|= (et
.size
== 16) << 28;
15963 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15964 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15966 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15971 do_mve_vcmul (void)
15973 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15974 struct neon_type_el et
15975 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15977 if (inst
.cond
> COND_ALWAYS
)
15978 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15980 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15982 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15983 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15984 _("immediate out of range"));
15986 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15987 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15988 as_tsktsk (BAD_MVE_SRCDEST
);
15990 inst
.instruction
|= (et
.size
== 32) << 28;
15991 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15992 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15993 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15994 inst
.instruction
|= (rot
> 90) << 12;
15995 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15996 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15997 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15998 inst
.instruction
|= (rot
== 90 || rot
== 270);
16002 /* To handle the Low Overhead Loop instructions
16003 in Armv8.1-M Mainline and MVE. */
16007 unsigned long insn
= inst
.instruction
;
16009 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16011 if (insn
== T_MNEM_lctp
)
16014 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16016 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16018 struct neon_type_el et
16019 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16020 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16027 constraint (!inst
.operands
[0].present
,
16029 /* fall through. */
16032 if (!inst
.operands
[0].present
)
16033 inst
.instruction
|= 1 << 21;
16035 v8_1_loop_reloc (TRUE
);
16040 v8_1_loop_reloc (FALSE
);
16041 /* fall through. */
16044 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16046 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16047 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16048 else if (inst
.operands
[1].reg
== REG_PC
)
16049 as_tsktsk (MVE_BAD_PC
);
16050 if (inst
.operands
[1].reg
== REG_SP
)
16051 as_tsktsk (MVE_BAD_SP
);
16053 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16063 do_vfp_nsyn_cmp (void)
16065 enum neon_shape rs
;
16066 if (!inst
.operands
[0].isreg
)
16073 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16074 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16078 if (inst
.operands
[1].isreg
)
16080 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16081 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16083 if (rs
== NS_FF
|| rs
== NS_HH
)
16085 NEON_ENCODE (SINGLE
, inst
);
16086 do_vfp_sp_monadic ();
16090 NEON_ENCODE (DOUBLE
, inst
);
16091 do_vfp_dp_rd_rm ();
16096 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16097 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16099 switch (inst
.instruction
& 0x0fffffff)
16102 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16105 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16111 if (rs
== NS_FI
|| rs
== NS_HI
)
16113 NEON_ENCODE (SINGLE
, inst
);
16114 do_vfp_sp_compare_z ();
16118 NEON_ENCODE (DOUBLE
, inst
);
16122 do_vfp_cond_or_thumb ();
16124 /* ARMv8.2 fp16 instruction. */
16125 if (rs
== NS_HI
|| rs
== NS_HH
)
16126 do_scalar_fp16_v82_encode ();
16130 nsyn_insert_sp (void)
16132 inst
.operands
[1] = inst
.operands
[0];
16133 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16134 inst
.operands
[0].reg
= REG_SP
;
16135 inst
.operands
[0].isreg
= 1;
16136 inst
.operands
[0].writeback
= 1;
16137 inst
.operands
[0].present
= 1;
16141 do_vfp_nsyn_push (void)
16145 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16146 _("register list must contain at least 1 and at most 16 "
16149 if (inst
.operands
[1].issingle
)
16150 do_vfp_nsyn_opcode ("fstmdbs");
16152 do_vfp_nsyn_opcode ("fstmdbd");
16156 do_vfp_nsyn_pop (void)
16160 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16161 _("register list must contain at least 1 and at most 16 "
16164 if (inst
.operands
[1].issingle
)
16165 do_vfp_nsyn_opcode ("fldmias");
16167 do_vfp_nsyn_opcode ("fldmiad");
16170 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16171 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16174 neon_dp_fixup (struct arm_it
* insn
)
16176 unsigned int i
= insn
->instruction
;
16181 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16192 insn
->instruction
= i
;
16196 mve_encode_qqr (int size
, int U
, int fp
)
16198 if (inst
.operands
[2].reg
== REG_SP
)
16199 as_tsktsk (MVE_BAD_SP
);
16200 else if (inst
.operands
[2].reg
== REG_PC
)
16201 as_tsktsk (MVE_BAD_PC
);
16206 if (((unsigned)inst
.instruction
) == 0xd00)
16207 inst
.instruction
= 0xee300f40;
16209 else if (((unsigned)inst
.instruction
) == 0x200d00)
16210 inst
.instruction
= 0xee301f40;
16212 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16213 inst
.instruction
= 0xee310e60;
16215 /* Setting size which is 1 for F16 and 0 for F32. */
16216 inst
.instruction
|= (size
== 16) << 28;
16221 if (((unsigned)inst
.instruction
) == 0x800)
16222 inst
.instruction
= 0xee010f40;
16224 else if (((unsigned)inst
.instruction
) == 0x1000800)
16225 inst
.instruction
= 0xee011f40;
16227 else if (((unsigned)inst
.instruction
) == 0)
16228 inst
.instruction
= 0xee000f40;
16230 else if (((unsigned)inst
.instruction
) == 0x200)
16231 inst
.instruction
= 0xee001f40;
16233 else if (((unsigned)inst
.instruction
) == 0x900)
16234 inst
.instruction
= 0xee010e40;
16236 else if (((unsigned)inst
.instruction
) == 0x910)
16237 inst
.instruction
= 0xee011e60;
16239 else if (((unsigned)inst
.instruction
) == 0x10)
16240 inst
.instruction
= 0xee000f60;
16242 else if (((unsigned)inst
.instruction
) == 0x210)
16243 inst
.instruction
= 0xee001f60;
16245 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16246 inst
.instruction
= 0xee000e40;
16248 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16249 inst
.instruction
= 0xee010e60;
16251 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16252 inst
.instruction
= 0xfe010e60;
16255 inst
.instruction
|= U
<< 28;
16257 /* Setting bits for size. */
16258 inst
.instruction
|= neon_logbits (size
) << 20;
16260 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16261 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16262 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16263 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16264 inst
.instruction
|= inst
.operands
[2].reg
;
16269 mve_encode_rqq (unsigned bit28
, unsigned size
)
16271 inst
.instruction
|= bit28
<< 28;
16272 inst
.instruction
|= neon_logbits (size
) << 20;
16273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16274 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16275 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16276 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16277 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16282 mve_encode_qqq (int ubit
, int size
)
16285 inst
.instruction
|= (ubit
!= 0) << 28;
16286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16287 inst
.instruction
|= neon_logbits (size
) << 20;
16288 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16289 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16290 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16291 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16292 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16298 mve_encode_rq (unsigned bit28
, unsigned size
)
16300 inst
.instruction
|= bit28
<< 28;
16301 inst
.instruction
|= neon_logbits (size
) << 18;
16302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16303 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16308 mve_encode_rrqq (unsigned U
, unsigned size
)
16310 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16312 inst
.instruction
|= U
<< 28;
16313 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16314 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16315 inst
.instruction
|= (size
== 32) << 16;
16316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16317 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16318 inst
.instruction
|= inst
.operands
[3].reg
;
16322 /* Encode insns with bit pattern:
16324 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16325 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16327 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16328 different meaning for some instruction. */
16331 neon_three_same (int isquad
, int ubit
, int size
)
16333 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16334 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16335 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16336 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16337 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16338 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16339 inst
.instruction
|= (isquad
!= 0) << 6;
16340 inst
.instruction
|= (ubit
!= 0) << 24;
16342 inst
.instruction
|= neon_logbits (size
) << 20;
16344 neon_dp_fixup (&inst
);
16347 /* Encode instructions of the form:
16349 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16350 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16352 Don't write size if SIZE == -1. */
16355 neon_two_same (int qbit
, int ubit
, int size
)
16357 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16358 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16359 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16360 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16361 inst
.instruction
|= (qbit
!= 0) << 6;
16362 inst
.instruction
|= (ubit
!= 0) << 24;
16365 inst
.instruction
|= neon_logbits (size
) << 18;
16367 neon_dp_fixup (&inst
);
16370 enum vfp_or_neon_is_neon_bits
16373 NEON_CHECK_ARCH
= 2,
16374 NEON_CHECK_ARCH8
= 4
16377 /* Call this function if an instruction which may have belonged to the VFP or
16378 Neon instruction sets, but turned out to be a Neon instruction (due to the
16379 operand types involved, etc.). We have to check and/or fix-up a couple of
16382 - Make sure the user hasn't attempted to make a Neon instruction
16384 - Alter the value in the condition code field if necessary.
16385 - Make sure that the arch supports Neon instructions.
16387 Which of these operations take place depends on bits from enum
16388 vfp_or_neon_is_neon_bits.
16390 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16391 current instruction's condition is COND_ALWAYS, the condition field is
16392 changed to inst.uncond_value. This is necessary because instructions shared
16393 between VFP and Neon may be conditional for the VFP variants only, and the
16394 unconditional Neon version must have, e.g., 0xF in the condition field. */
16397 vfp_or_neon_is_neon (unsigned check
)
16399 /* Conditions are always legal in Thumb mode (IT blocks). */
16400 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16402 if (inst
.cond
!= COND_ALWAYS
)
16404 first_error (_(BAD_COND
));
16407 if (inst
.uncond_value
!= -1)
16408 inst
.instruction
|= inst
.uncond_value
<< 28;
16412 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16413 || ((check
& NEON_CHECK_ARCH8
)
16414 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16416 first_error (_(BAD_FPU
));
16424 /* Return TRUE if the SIMD instruction is available for the current
16425 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16426 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16427 vfp_or_neon_is_neon for the NEON specific checks. */
16430 check_simd_pred_availability (int fp
, unsigned check
)
16432 if (inst
.cond
> COND_ALWAYS
)
16434 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16436 inst
.error
= BAD_FPU
;
16439 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16441 else if (inst
.cond
< COND_ALWAYS
)
16443 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16444 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16445 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16450 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16451 && vfp_or_neon_is_neon (check
) == FAIL
)
16454 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16455 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16460 /* Neon instruction encoders, in approximate order of appearance. */
16463 do_neon_dyadic_i_su (void)
16465 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16468 enum neon_shape rs
;
16469 struct neon_type_el et
;
16470 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16471 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16473 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16475 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16479 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16481 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16485 do_neon_dyadic_i64_su (void)
16487 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16489 enum neon_shape rs
;
16490 struct neon_type_el et
;
16491 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16493 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16494 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16498 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16499 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16502 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16504 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16508 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16511 unsigned size
= et
.size
>> 3;
16512 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16513 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16514 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16515 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16516 inst
.instruction
|= (isquad
!= 0) << 6;
16517 inst
.instruction
|= immbits
<< 16;
16518 inst
.instruction
|= (size
>> 3) << 7;
16519 inst
.instruction
|= (size
& 0x7) << 19;
16521 inst
.instruction
|= (uval
!= 0) << 24;
16523 neon_dp_fixup (&inst
);
16529 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16532 if (!inst
.operands
[2].isreg
)
16534 enum neon_shape rs
;
16535 struct neon_type_el et
;
16536 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16538 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16539 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16543 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16544 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16546 int imm
= inst
.operands
[2].imm
;
16548 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16549 _("immediate out of range for shift"));
16550 NEON_ENCODE (IMMED
, inst
);
16551 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16555 enum neon_shape rs
;
16556 struct neon_type_el et
;
16557 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16559 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16560 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16564 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16565 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16571 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16572 _("invalid instruction shape"));
16573 if (inst
.operands
[2].reg
== REG_SP
)
16574 as_tsktsk (MVE_BAD_SP
);
16575 else if (inst
.operands
[2].reg
== REG_PC
)
16576 as_tsktsk (MVE_BAD_PC
);
16578 inst
.instruction
= 0xee311e60;
16579 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16580 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16581 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16583 inst
.instruction
|= inst
.operands
[2].reg
;
16590 /* VSHL/VQSHL 3-register variants have syntax such as:
16592 whereas other 3-register operations encoded by neon_three_same have
16595 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16596 operands[2].reg here. */
16597 tmp
= inst
.operands
[2].reg
;
16598 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16599 inst
.operands
[1].reg
= tmp
;
16600 NEON_ENCODE (INTEGER
, inst
);
16601 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16607 do_neon_qshl (void)
16609 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16612 if (!inst
.operands
[2].isreg
)
16614 enum neon_shape rs
;
16615 struct neon_type_el et
;
16616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16618 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16619 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16623 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16624 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16626 int imm
= inst
.operands
[2].imm
;
16628 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16629 _("immediate out of range for shift"));
16630 NEON_ENCODE (IMMED
, inst
);
16631 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16635 enum neon_shape rs
;
16636 struct neon_type_el et
;
16638 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16640 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16641 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16645 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16646 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16651 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16652 _("invalid instruction shape"));
16653 if (inst
.operands
[2].reg
== REG_SP
)
16654 as_tsktsk (MVE_BAD_SP
);
16655 else if (inst
.operands
[2].reg
== REG_PC
)
16656 as_tsktsk (MVE_BAD_PC
);
16658 inst
.instruction
= 0xee311ee0;
16659 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16660 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16661 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16662 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16663 inst
.instruction
|= inst
.operands
[2].reg
;
16670 /* See note in do_neon_shl. */
16671 tmp
= inst
.operands
[2].reg
;
16672 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16673 inst
.operands
[1].reg
= tmp
;
16674 NEON_ENCODE (INTEGER
, inst
);
16675 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16681 do_neon_rshl (void)
16683 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16686 enum neon_shape rs
;
16687 struct neon_type_el et
;
16688 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16690 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16691 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16695 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16696 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16703 if (inst
.operands
[2].reg
== REG_PC
)
16704 as_tsktsk (MVE_BAD_PC
);
16705 else if (inst
.operands
[2].reg
== REG_SP
)
16706 as_tsktsk (MVE_BAD_SP
);
16708 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16709 _("invalid instruction shape"));
16711 if (inst
.instruction
== 0x0000510)
16712 /* We are dealing with vqrshl. */
16713 inst
.instruction
= 0xee331ee0;
16715 /* We are dealing with vrshl. */
16716 inst
.instruction
= 0xee331e60;
16718 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16719 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16720 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16721 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16722 inst
.instruction
|= inst
.operands
[2].reg
;
16727 tmp
= inst
.operands
[2].reg
;
16728 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16729 inst
.operands
[1].reg
= tmp
;
16730 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16735 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16737 /* Handle .I8 pseudo-instructions. */
16740 /* Unfortunately, this will make everything apart from zero out-of-range.
16741 FIXME is this the intended semantics? There doesn't seem much point in
16742 accepting .I8 if so. */
16743 immediate
|= immediate
<< 8;
16749 if (immediate
== (immediate
& 0x000000ff))
16751 *immbits
= immediate
;
16754 else if (immediate
== (immediate
& 0x0000ff00))
16756 *immbits
= immediate
>> 8;
16759 else if (immediate
== (immediate
& 0x00ff0000))
16761 *immbits
= immediate
>> 16;
16764 else if (immediate
== (immediate
& 0xff000000))
16766 *immbits
= immediate
>> 24;
16769 if ((immediate
& 0xffff) != (immediate
>> 16))
16770 goto bad_immediate
;
16771 immediate
&= 0xffff;
16774 if (immediate
== (immediate
& 0x000000ff))
16776 *immbits
= immediate
;
16779 else if (immediate
== (immediate
& 0x0000ff00))
16781 *immbits
= immediate
>> 8;
16786 first_error (_("immediate value out of range"));
16791 do_neon_logic (void)
16793 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16795 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16797 && !check_simd_pred_availability (FALSE
,
16798 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16800 else if (rs
!= NS_QQQ
16801 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16802 first_error (BAD_FPU
);
16804 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16805 /* U bit and size field were set as part of the bitmask. */
16806 NEON_ENCODE (INTEGER
, inst
);
16807 neon_three_same (neon_quad (rs
), 0, -1);
16811 const int three_ops_form
= (inst
.operands
[2].present
16812 && !inst
.operands
[2].isreg
);
16813 const int immoperand
= (three_ops_form
? 2 : 1);
16814 enum neon_shape rs
= (three_ops_form
16815 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16816 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16817 /* Because neon_select_shape makes the second operand a copy of the first
16818 if the second operand is not present. */
16820 && !check_simd_pred_availability (FALSE
,
16821 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16823 else if (rs
!= NS_QQI
16824 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16825 first_error (BAD_FPU
);
16827 struct neon_type_el et
;
16828 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16829 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16831 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16834 if (et
.type
== NT_invtype
)
16836 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16841 if (three_ops_form
)
16842 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16843 _("first and second operands shall be the same register"));
16845 NEON_ENCODE (IMMED
, inst
);
16847 immbits
= inst
.operands
[immoperand
].imm
;
16850 /* .i64 is a pseudo-op, so the immediate must be a repeating
16852 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16853 inst
.operands
[immoperand
].reg
: 0))
16855 /* Set immbits to an invalid constant. */
16856 immbits
= 0xdeadbeef;
16863 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16867 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16871 /* Pseudo-instruction for VBIC. */
16872 neon_invert_size (&immbits
, 0, et
.size
);
16873 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16877 /* Pseudo-instruction for VORR. */
16878 neon_invert_size (&immbits
, 0, et
.size
);
16879 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16889 inst
.instruction
|= neon_quad (rs
) << 6;
16890 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16891 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16892 inst
.instruction
|= cmode
<< 8;
16893 neon_write_immbits (immbits
);
16895 neon_dp_fixup (&inst
);
16900 do_neon_bitfield (void)
16902 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16903 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16904 neon_three_same (neon_quad (rs
), 0, -1);
16908 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16911 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16912 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16914 if (et
.type
== NT_float
)
16916 NEON_ENCODE (FLOAT
, inst
);
16918 mve_encode_qqr (et
.size
, 0, 1);
16920 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16924 NEON_ENCODE (INTEGER
, inst
);
16926 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16928 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16934 do_neon_dyadic_if_su_d (void)
16936 /* This version only allow D registers, but that constraint is enforced during
16937 operand parsing so we don't need to do anything extra here. */
16938 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16942 do_neon_dyadic_if_i_d (void)
16944 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16945 affected if we specify unsigned args. */
16946 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16950 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16952 constraint (size
< 32, BAD_ADDR_MODE
);
16953 constraint (size
!= elsize
, BAD_EL_TYPE
);
16954 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16955 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16956 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16957 _("destination register and offset register may not be the"
16960 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16967 constraint ((imm
% (size
/ 8) != 0)
16968 || imm
> (0x7f << neon_logbits (size
)),
16969 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16970 " range of +/-[0,508]")
16971 : _("immediate must be a multiple of 8 in the"
16972 " range of +/-[0,1016]"));
16973 inst
.instruction
|= 0x11 << 24;
16974 inst
.instruction
|= add
<< 23;
16975 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16976 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16979 inst
.instruction
|= 1 << 12;
16980 inst
.instruction
|= (size
== 64) << 8;
16981 inst
.instruction
&= 0xffffff00;
16982 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16983 inst
.instruction
|= imm
>> neon_logbits (size
);
16987 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16989 unsigned os
= inst
.operands
[1].imm
>> 5;
16990 constraint (os
!= 0 && size
== 8,
16991 _("can not shift offsets when accessing less than half-word"));
16992 constraint (os
&& os
!= neon_logbits (size
),
16993 _("shift immediate must be 1, 2 or 3 for half-word, word"
16994 " or double-word accesses respectively"));
16995 if (inst
.operands
[1].reg
== REG_PC
)
16996 as_tsktsk (MVE_BAD_PC
);
17001 constraint (elsize
>= 64, BAD_EL_TYPE
);
17004 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17008 constraint (elsize
!= size
, BAD_EL_TYPE
);
17013 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17017 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17018 _("destination register and offset register may not be"
17020 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17022 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17023 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17024 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17028 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17031 inst
.instruction
|= 1 << 23;
17032 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17033 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17035 inst
.instruction
|= neon_logbits (elsize
) << 7;
17036 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17037 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17038 inst
.instruction
|= !!os
;
17042 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17044 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17046 constraint (size
>= 64, BAD_ADDR_MODE
);
17050 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17053 constraint (elsize
!= size
, BAD_EL_TYPE
);
17060 constraint (elsize
!= size
&& type
!= NT_unsigned
17061 && type
!= NT_signed
, BAD_EL_TYPE
);
17065 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17068 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17076 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17081 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17084 constraint (1, _("immediate must be a multiple of 2 in the"
17085 " range of +/-[0,254]"));
17088 constraint (1, _("immediate must be a multiple of 4 in the"
17089 " range of +/-[0,508]"));
17094 if (size
!= elsize
)
17096 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17097 constraint (inst
.operands
[0].reg
> 14,
17098 _("MVE vector register in the range [Q0..Q7] expected"));
17099 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17100 inst
.instruction
|= (size
== 16) << 19;
17101 inst
.instruction
|= neon_logbits (elsize
) << 7;
17105 if (inst
.operands
[1].reg
== REG_PC
)
17106 as_tsktsk (MVE_BAD_PC
);
17107 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17108 as_tsktsk (MVE_BAD_SP
);
17109 inst
.instruction
|= 1 << 12;
17110 inst
.instruction
|= neon_logbits (size
) << 7;
17112 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17113 inst
.instruction
|= add
<< 23;
17114 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17115 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17117 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17118 inst
.instruction
&= 0xffffff80;
17119 inst
.instruction
|= imm
>> neon_logbits (size
);
17124 do_mve_vstr_vldr (void)
17129 if (inst
.cond
> COND_ALWAYS
)
17130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17134 switch (inst
.instruction
)
17141 /* fall through. */
17147 /* fall through. */
17153 /* fall through. */
17159 /* fall through. */
17164 unsigned elsize
= inst
.vectype
.el
[0].size
;
17166 if (inst
.operands
[1].isquad
)
17168 /* We are dealing with [Q, imm]{!} cases. */
17169 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17173 if (inst
.operands
[1].immisreg
== 2)
17175 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17176 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17178 else if (!inst
.operands
[1].immisreg
)
17180 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17181 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17184 constraint (1, BAD_ADDR_MODE
);
17191 do_mve_vst_vld (void)
17193 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17196 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17197 || inst
.relocs
[0].exp
.X_add_number
!= 0
17198 || inst
.operands
[1].immisreg
!= 0,
17200 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17201 if (inst
.operands
[1].reg
== REG_PC
)
17202 as_tsktsk (MVE_BAD_PC
);
17203 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17204 as_tsktsk (MVE_BAD_SP
);
17207 /* These instructions are one of the "exceptions" mentioned in
17208 handle_pred_state. They are MVE instructions that are not VPT compatible
17209 and do not accept a VPT code, thus appending such a code is a syntax
17211 if (inst
.cond
> COND_ALWAYS
)
17212 first_error (BAD_SYNTAX
);
17213 /* If we append a scalar condition code we can set this to
17214 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17215 else if (inst
.cond
< COND_ALWAYS
)
17216 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17218 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17221 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17222 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17223 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17224 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17229 do_mve_vaddlv (void)
17231 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17232 struct neon_type_el et
17233 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17235 if (et
.type
== NT_invtype
)
17236 first_error (BAD_EL_TYPE
);
17238 if (inst
.cond
> COND_ALWAYS
)
17239 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17241 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17243 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17245 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17246 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17248 inst
.instruction
|= inst
.operands
[2].reg
;
17253 do_neon_dyadic_if_su (void)
17255 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17256 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17259 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17260 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17261 && et
.type
== NT_float
17262 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17264 if (!check_simd_pred_availability (et
.type
== NT_float
,
17265 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17268 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17272 do_neon_addsub_if_i (void)
17274 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17275 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17278 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17279 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17280 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17282 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17283 /* If we are parsing Q registers and the element types match MVE, which NEON
17284 also supports, then we must check whether this is an instruction that can
17285 be used by both MVE/NEON. This distinction can be made based on whether
17286 they are predicated or not. */
17287 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17289 if (!check_simd_pred_availability (et
.type
== NT_float
,
17290 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17295 /* If they are either in a D register or are using an unsupported. */
17297 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17301 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17302 affected if we specify unsigned args. */
17303 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17306 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17308 V<op> A,B (A is operand 0, B is operand 2)
17313 so handle that case specially. */
17316 neon_exchange_operands (void)
17318 if (inst
.operands
[1].present
)
17320 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17322 /* Swap operands[1] and operands[2]. */
17323 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17324 inst
.operands
[1] = inst
.operands
[2];
17325 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17330 inst
.operands
[1] = inst
.operands
[2];
17331 inst
.operands
[2] = inst
.operands
[0];
17336 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17338 if (inst
.operands
[2].isreg
)
17341 neon_exchange_operands ();
17342 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17346 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17347 struct neon_type_el et
= neon_check_type (2, rs
,
17348 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17350 NEON_ENCODE (IMMED
, inst
);
17351 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17352 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17353 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17354 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17355 inst
.instruction
|= neon_quad (rs
) << 6;
17356 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17357 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17359 neon_dp_fixup (&inst
);
17366 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17370 do_neon_cmp_inv (void)
17372 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17378 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17381 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17382 scalars, which are encoded in 5 bits, M : Rm.
17383 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17384 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17387 Dot Product instructions are similar to multiply instructions except elsize
17388 should always be 32.
17390 This function translates SCALAR, which is GAS's internal encoding of indexed
17391 scalar register, to raw encoding. There is also register and index range
17392 check based on ELSIZE. */
17395 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17397 unsigned regno
= NEON_SCALAR_REG (scalar
);
17398 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17403 if (regno
> 7 || elno
> 3)
17405 return regno
| (elno
<< 3);
17408 if (regno
> 15 || elno
> 1)
17410 return regno
| (elno
<< 4);
17414 first_error (_("scalar out of range for multiply instruction"));
17420 /* Encode multiply / multiply-accumulate scalar instructions. */
17423 neon_mul_mac (struct neon_type_el et
, int ubit
)
17427 /* Give a more helpful error message if we have an invalid type. */
17428 if (et
.type
== NT_invtype
)
17431 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17436 inst
.instruction
|= LOW4 (scalar
);
17437 inst
.instruction
|= HI1 (scalar
) << 5;
17438 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17439 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17440 inst
.instruction
|= (ubit
!= 0) << 24;
17442 neon_dp_fixup (&inst
);
17446 do_neon_mac_maybe_scalar (void)
17448 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17451 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17454 if (inst
.operands
[2].isscalar
)
17456 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17457 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17458 struct neon_type_el et
= neon_check_type (3, rs
,
17459 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17460 NEON_ENCODE (SCALAR
, inst
);
17461 neon_mul_mac (et
, neon_quad (rs
));
17463 else if (!inst
.operands
[2].isvec
)
17465 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17467 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17468 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17470 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17474 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17475 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17476 affected if we specify unsigned args. */
17477 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17482 do_neon_fmac (void)
17484 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17485 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17488 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17491 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17493 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17494 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17499 if (inst
.operands
[2].reg
== REG_SP
)
17500 as_tsktsk (MVE_BAD_SP
);
17501 else if (inst
.operands
[2].reg
== REG_PC
)
17502 as_tsktsk (MVE_BAD_PC
);
17504 inst
.instruction
= 0xee310e40;
17505 inst
.instruction
|= (et
.size
== 16) << 28;
17506 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17507 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17508 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17509 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17510 inst
.instruction
|= inst
.operands
[2].reg
;
17517 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17520 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17526 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17527 struct neon_type_el et
= neon_check_type (3, rs
,
17528 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17529 neon_three_same (neon_quad (rs
), 0, et
.size
);
17532 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17533 same types as the MAC equivalents. The polynomial type for this instruction
17534 is encoded the same as the integer type. */
17539 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17542 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17545 if (inst
.operands
[2].isscalar
)
17547 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17548 do_neon_mac_maybe_scalar ();
17552 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17554 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17555 struct neon_type_el et
17556 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17557 if (et
.type
== NT_float
)
17558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17561 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17565 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17566 neon_dyadic_misc (NT_poly
,
17567 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17573 do_neon_qdmulh (void)
17575 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17578 if (inst
.operands
[2].isscalar
)
17580 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17581 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17582 struct neon_type_el et
= neon_check_type (3, rs
,
17583 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17584 NEON_ENCODE (SCALAR
, inst
);
17585 neon_mul_mac (et
, neon_quad (rs
));
17589 enum neon_shape rs
;
17590 struct neon_type_el et
;
17591 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17593 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17594 et
= neon_check_type (3, rs
,
17595 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17599 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17600 et
= neon_check_type (3, rs
,
17601 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17604 NEON_ENCODE (INTEGER
, inst
);
17606 mve_encode_qqr (et
.size
, 0, 0);
17608 /* The U bit (rounding) comes from bit mask. */
17609 neon_three_same (neon_quad (rs
), 0, et
.size
);
17614 do_mve_vaddv (void)
17616 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17617 struct neon_type_el et
17618 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17620 if (et
.type
== NT_invtype
)
17621 first_error (BAD_EL_TYPE
);
17623 if (inst
.cond
> COND_ALWAYS
)
17624 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17626 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17628 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17630 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17634 do_mve_vhcadd (void)
17636 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17637 struct neon_type_el et
17638 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17640 if (inst
.cond
> COND_ALWAYS
)
17641 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17643 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17645 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17646 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17648 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17649 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17650 "operand makes instruction UNPREDICTABLE"));
17652 mve_encode_qqq (0, et
.size
);
17653 inst
.instruction
|= (rot
== 270) << 12;
17658 do_mve_vqdmull (void)
17660 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17661 struct neon_type_el et
17662 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17665 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17666 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17667 as_tsktsk (BAD_MVE_SRCDEST
);
17669 if (inst
.cond
> COND_ALWAYS
)
17670 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17672 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17676 mve_encode_qqq (et
.size
== 32, 64);
17677 inst
.instruction
|= 1;
17681 mve_encode_qqr (64, et
.size
== 32, 0);
17682 inst
.instruction
|= 0x3 << 5;
17689 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17690 struct neon_type_el et
17691 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17693 if (et
.type
== NT_invtype
)
17694 first_error (BAD_EL_TYPE
);
17696 if (inst
.cond
> COND_ALWAYS
)
17697 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17699 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17701 mve_encode_qqq (0, 64);
17705 do_mve_vbrsr (void)
17707 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17708 struct neon_type_el et
17709 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17711 if (inst
.cond
> COND_ALWAYS
)
17712 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17714 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17716 mve_encode_qqr (et
.size
, 0, 0);
17722 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17724 if (inst
.cond
> COND_ALWAYS
)
17725 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17727 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17729 mve_encode_qqq (1, 64);
17733 do_mve_vmulh (void)
17735 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17736 struct neon_type_el et
17737 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17739 if (inst
.cond
> COND_ALWAYS
)
17740 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17742 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17744 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17748 do_mve_vqdmlah (void)
17750 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17751 struct neon_type_el et
17752 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17754 if (inst
.cond
> COND_ALWAYS
)
17755 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17757 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17759 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17763 do_mve_vqdmladh (void)
17765 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17766 struct neon_type_el et
17767 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17769 if (inst
.cond
> COND_ALWAYS
)
17770 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17772 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17775 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17776 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17777 as_tsktsk (BAD_MVE_SRCDEST
);
17779 mve_encode_qqq (0, et
.size
);
17784 do_mve_vmull (void)
17787 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17788 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17789 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17790 && inst
.cond
== COND_ALWAYS
17791 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17796 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17797 N_SUF_32
| N_F64
| N_P8
17798 | N_P16
| N_I_MVE
| N_KEY
);
17799 if (((et
.type
== NT_poly
) && et
.size
== 8
17800 && ARM_CPU_IS_ANY (cpu_variant
))
17801 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17808 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17809 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17810 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17812 /* We are dealing with MVE's vmullt. */
17814 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17815 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17816 as_tsktsk (BAD_MVE_SRCDEST
);
17818 if (inst
.cond
> COND_ALWAYS
)
17819 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17821 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17823 if (et
.type
== NT_poly
)
17824 mve_encode_qqq (neon_logbits (et
.size
), 64);
17826 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17831 inst
.instruction
= N_MNEM_vmul
;
17834 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17839 do_mve_vabav (void)
17841 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17846 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17849 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17850 | N_S16
| N_S32
| N_U8
| N_U16
17853 if (inst
.cond
> COND_ALWAYS
)
17854 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17856 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17858 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17862 do_mve_vmladav (void)
17864 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17865 struct neon_type_el et
= neon_check_type (3, rs
,
17866 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17868 if (et
.type
== NT_unsigned
17869 && (inst
.instruction
== M_MNEM_vmladavx
17870 || inst
.instruction
== M_MNEM_vmladavax
17871 || inst
.instruction
== M_MNEM_vmlsdav
17872 || inst
.instruction
== M_MNEM_vmlsdava
17873 || inst
.instruction
== M_MNEM_vmlsdavx
17874 || inst
.instruction
== M_MNEM_vmlsdavax
))
17875 first_error (BAD_SIMD_TYPE
);
17877 constraint (inst
.operands
[2].reg
> 14,
17878 _("MVE vector register in the range [Q0..Q7] expected"));
17880 if (inst
.cond
> COND_ALWAYS
)
17881 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17883 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17885 if (inst
.instruction
== M_MNEM_vmlsdav
17886 || inst
.instruction
== M_MNEM_vmlsdava
17887 || inst
.instruction
== M_MNEM_vmlsdavx
17888 || inst
.instruction
== M_MNEM_vmlsdavax
)
17889 inst
.instruction
|= (et
.size
== 8) << 28;
17891 inst
.instruction
|= (et
.size
== 8) << 8;
17893 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17894 inst
.instruction
|= (et
.size
== 32) << 16;
17898 do_mve_vmlaldav (void)
17900 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17901 struct neon_type_el et
17902 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17903 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17905 if (et
.type
== NT_unsigned
17906 && (inst
.instruction
== M_MNEM_vmlsldav
17907 || inst
.instruction
== M_MNEM_vmlsldava
17908 || inst
.instruction
== M_MNEM_vmlsldavx
17909 || inst
.instruction
== M_MNEM_vmlsldavax
))
17910 first_error (BAD_SIMD_TYPE
);
17912 if (inst
.cond
> COND_ALWAYS
)
17913 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17915 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17917 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17921 do_mve_vrmlaldavh (void)
17923 struct neon_type_el et
;
17924 if (inst
.instruction
== M_MNEM_vrmlsldavh
17925 || inst
.instruction
== M_MNEM_vrmlsldavha
17926 || inst
.instruction
== M_MNEM_vrmlsldavhx
17927 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17929 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17930 if (inst
.operands
[1].reg
== REG_SP
)
17931 as_tsktsk (MVE_BAD_SP
);
17935 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17936 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17937 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17939 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17940 N_U32
| N_S32
| N_KEY
);
17941 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17942 with vmax/min instructions, making the use of SP in assembly really
17943 nonsensical, so instead of issuing a warning like we do for other uses
17944 of SP for the odd register operand we error out. */
17945 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17948 /* Make sure we still check the second operand is an odd one and that PC is
17949 disallowed. This because we are parsing for any GPR operand, to be able
17950 to distinguish between giving a warning or an error for SP as described
17952 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17953 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17955 if (inst
.cond
> COND_ALWAYS
)
17956 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17958 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17960 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17965 do_mve_vmaxnmv (void)
17967 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17968 struct neon_type_el et
17969 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17971 if (inst
.cond
> COND_ALWAYS
)
17972 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17974 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17976 if (inst
.operands
[0].reg
== REG_SP
)
17977 as_tsktsk (MVE_BAD_SP
);
17978 else if (inst
.operands
[0].reg
== REG_PC
)
17979 as_tsktsk (MVE_BAD_PC
);
17981 mve_encode_rq (et
.size
== 16, 64);
17985 do_mve_vmaxv (void)
17987 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17988 struct neon_type_el et
;
17990 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17991 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17993 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17995 if (inst
.cond
> COND_ALWAYS
)
17996 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17998 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18000 if (inst
.operands
[0].reg
== REG_SP
)
18001 as_tsktsk (MVE_BAD_SP
);
18002 else if (inst
.operands
[0].reg
== REG_PC
)
18003 as_tsktsk (MVE_BAD_PC
);
18005 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18010 do_neon_qrdmlah (void)
18012 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18014 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18016 /* Check we're on the correct architecture. */
18017 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18019 = _("instruction form not available on this architecture.");
18020 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18022 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18023 record_feature_use (&fpu_neon_ext_v8_1
);
18025 if (inst
.operands
[2].isscalar
)
18027 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18028 struct neon_type_el et
= neon_check_type (3, rs
,
18029 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18030 NEON_ENCODE (SCALAR
, inst
);
18031 neon_mul_mac (et
, neon_quad (rs
));
18035 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18036 struct neon_type_el et
= neon_check_type (3, rs
,
18037 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18038 NEON_ENCODE (INTEGER
, inst
);
18039 /* The U bit (rounding) comes from bit mask. */
18040 neon_three_same (neon_quad (rs
), 0, et
.size
);
18045 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18046 struct neon_type_el et
18047 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18049 NEON_ENCODE (INTEGER
, inst
);
18050 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18055 do_neon_fcmp_absolute (void)
18057 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18058 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18059 N_F_16_32
| N_KEY
);
18060 /* Size field comes from bit mask. */
18061 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18065 do_neon_fcmp_absolute_inv (void)
18067 neon_exchange_operands ();
18068 do_neon_fcmp_absolute ();
18072 do_neon_step (void)
18074 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18075 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18076 N_F_16_32
| N_KEY
);
18077 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18081 do_neon_abs_neg (void)
18083 enum neon_shape rs
;
18084 struct neon_type_el et
;
18086 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18089 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18090 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18092 if (!check_simd_pred_availability (et
.type
== NT_float
,
18093 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18096 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18097 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18098 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18099 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18100 inst
.instruction
|= neon_quad (rs
) << 6;
18101 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18102 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18104 neon_dp_fixup (&inst
);
18110 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18113 enum neon_shape rs
;
18114 struct neon_type_el et
;
18115 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18117 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18118 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18122 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18123 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18127 int imm
= inst
.operands
[2].imm
;
18128 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18129 _("immediate out of range for insert"));
18130 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18136 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18139 enum neon_shape rs
;
18140 struct neon_type_el et
;
18141 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18143 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18144 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18148 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18149 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18152 int imm
= inst
.operands
[2].imm
;
18153 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18154 _("immediate out of range for insert"));
18155 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18159 do_neon_qshlu_imm (void)
18161 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18164 enum neon_shape rs
;
18165 struct neon_type_el et
;
18166 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18168 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18169 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18173 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18174 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18175 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18178 int imm
= inst
.operands
[2].imm
;
18179 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18180 _("immediate out of range for shift"));
18181 /* Only encodes the 'U present' variant of the instruction.
18182 In this case, signed types have OP (bit 8) set to 0.
18183 Unsigned types have OP set to 1. */
18184 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18185 /* The rest of the bits are the same as other immediate shifts. */
18186 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18190 do_neon_qmovn (void)
18192 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18193 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18194 /* Saturating move where operands can be signed or unsigned, and the
18195 destination has the same signedness. */
18196 NEON_ENCODE (INTEGER
, inst
);
18197 if (et
.type
== NT_unsigned
)
18198 inst
.instruction
|= 0xc0;
18200 inst
.instruction
|= 0x80;
18201 neon_two_same (0, 1, et
.size
/ 2);
18205 do_neon_qmovun (void)
18207 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18208 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18209 /* Saturating move with unsigned results. Operands must be signed. */
18210 NEON_ENCODE (INTEGER
, inst
);
18211 neon_two_same (0, 1, et
.size
/ 2);
18215 do_neon_rshift_sat_narrow (void)
18217 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18218 or unsigned. If operands are unsigned, results must also be unsigned. */
18219 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18220 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18221 int imm
= inst
.operands
[2].imm
;
18222 /* This gets the bounds check, size encoding and immediate bits calculation
18226 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18227 VQMOVN.I<size> <Dd>, <Qm>. */
18230 inst
.operands
[2].present
= 0;
18231 inst
.instruction
= N_MNEM_vqmovn
;
18236 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18237 _("immediate out of range"));
18238 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18242 do_neon_rshift_sat_narrow_u (void)
18244 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18245 or unsigned. If operands are unsigned, results must also be unsigned. */
18246 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18247 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18248 int imm
= inst
.operands
[2].imm
;
18249 /* This gets the bounds check, size encoding and immediate bits calculation
18253 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18254 VQMOVUN.I<size> <Dd>, <Qm>. */
18257 inst
.operands
[2].present
= 0;
18258 inst
.instruction
= N_MNEM_vqmovun
;
18263 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18264 _("immediate out of range"));
18265 /* FIXME: The manual is kind of unclear about what value U should have in
18266 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18268 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18272 do_neon_movn (void)
18274 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18275 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18276 NEON_ENCODE (INTEGER
, inst
);
18277 neon_two_same (0, 1, et
.size
/ 2);
18281 do_neon_rshift_narrow (void)
18283 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18284 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18285 int imm
= inst
.operands
[2].imm
;
18286 /* This gets the bounds check, size encoding and immediate bits calculation
18290 /* If immediate is zero then we are a pseudo-instruction for
18291 VMOVN.I<size> <Dd>, <Qm> */
18294 inst
.operands
[2].present
= 0;
18295 inst
.instruction
= N_MNEM_vmovn
;
18300 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18301 _("immediate out of range for narrowing operation"));
18302 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18306 do_neon_shll (void)
18308 /* FIXME: Type checking when lengthening. */
18309 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18310 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18311 unsigned imm
= inst
.operands
[2].imm
;
18313 if (imm
== et
.size
)
18315 /* Maximum shift variant. */
18316 NEON_ENCODE (INTEGER
, inst
);
18317 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18318 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18319 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18320 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18321 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18323 neon_dp_fixup (&inst
);
18327 /* A more-specific type check for non-max versions. */
18328 et
= neon_check_type (2, NS_QDI
,
18329 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18330 NEON_ENCODE (IMMED
, inst
);
18331 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18335 /* Check the various types for the VCVT instruction, and return which version
18336 the current instruction is. */
18338 #define CVT_FLAVOUR_VAR \
18339 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18340 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18341 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18342 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18343 /* Half-precision conversions. */ \
18344 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18345 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18346 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18347 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18348 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18349 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18350 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18351 Compared with single/double precision variants, only the co-processor \
18352 field is different, so the encoding flow is reused here. */ \
18353 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18354 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18355 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18356 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18357 /* VFP instructions. */ \
18358 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18359 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18360 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18361 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18362 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18363 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18364 /* VFP instructions with bitshift. */ \
18365 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18366 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18367 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18368 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18369 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18370 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18371 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18372 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18374 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18375 neon_cvt_flavour_##C,
18377 /* The different types of conversions we can do. */
18378 enum neon_cvt_flavour
18381 neon_cvt_flavour_invalid
,
18382 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18387 static enum neon_cvt_flavour
18388 get_neon_cvt_flavour (enum neon_shape rs
)
18390 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18391 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18392 if (et.type != NT_invtype) \
18394 inst.error = NULL; \
18395 return (neon_cvt_flavour_##C); \
18398 struct neon_type_el et
;
18399 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18400 || rs
== NS_FF
) ? N_VFP
: 0;
18401 /* The instruction versions which take an immediate take one register
18402 argument, which is extended to the width of the full register. Thus the
18403 "source" and "destination" registers must have the same width. Hack that
18404 here by making the size equal to the key (wider, in this case) operand. */
18405 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18409 return neon_cvt_flavour_invalid
;
18424 /* Neon-syntax VFP conversions. */
18427 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18429 const char *opname
= 0;
18431 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18432 || rs
== NS_FHI
|| rs
== NS_HFI
)
18434 /* Conversions with immediate bitshift. */
18435 const char *enc
[] =
18437 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18443 if (flavour
< (int) ARRAY_SIZE (enc
))
18445 opname
= enc
[flavour
];
18446 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18447 _("operands 0 and 1 must be the same register"));
18448 inst
.operands
[1] = inst
.operands
[2];
18449 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18454 /* Conversions without bitshift. */
18455 const char *enc
[] =
18457 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18463 if (flavour
< (int) ARRAY_SIZE (enc
))
18464 opname
= enc
[flavour
];
18468 do_vfp_nsyn_opcode (opname
);
18470 /* ARMv8.2 fp16 VCVT instruction. */
18471 if (flavour
== neon_cvt_flavour_s32_f16
18472 || flavour
== neon_cvt_flavour_u32_f16
18473 || flavour
== neon_cvt_flavour_f16_u32
18474 || flavour
== neon_cvt_flavour_f16_s32
)
18475 do_scalar_fp16_v82_encode ();
18479 do_vfp_nsyn_cvtz (void)
18481 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18482 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18483 const char *enc
[] =
18485 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18491 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18492 do_vfp_nsyn_opcode (enc
[flavour
]);
18496 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18497 enum neon_cvt_mode mode
)
18502 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18503 D register operands. */
18504 if (flavour
== neon_cvt_flavour_s32_f64
18505 || flavour
== neon_cvt_flavour_u32_f64
)
18506 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18509 if (flavour
== neon_cvt_flavour_s32_f16
18510 || flavour
== neon_cvt_flavour_u32_f16
)
18511 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18514 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18518 case neon_cvt_flavour_s32_f64
:
18522 case neon_cvt_flavour_s32_f32
:
18526 case neon_cvt_flavour_s32_f16
:
18530 case neon_cvt_flavour_u32_f64
:
18534 case neon_cvt_flavour_u32_f32
:
18538 case neon_cvt_flavour_u32_f16
:
18543 first_error (_("invalid instruction shape"));
18549 case neon_cvt_mode_a
: rm
= 0; break;
18550 case neon_cvt_mode_n
: rm
= 1; break;
18551 case neon_cvt_mode_p
: rm
= 2; break;
18552 case neon_cvt_mode_m
: rm
= 3; break;
18553 default: first_error (_("invalid rounding mode")); return;
18556 NEON_ENCODE (FPV8
, inst
);
18557 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18558 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18559 inst
.instruction
|= sz
<< 8;
18561 /* ARMv8.2 fp16 VCVT instruction. */
18562 if (flavour
== neon_cvt_flavour_s32_f16
18563 ||flavour
== neon_cvt_flavour_u32_f16
)
18564 do_scalar_fp16_v82_encode ();
18565 inst
.instruction
|= op
<< 7;
18566 inst
.instruction
|= rm
<< 16;
18567 inst
.instruction
|= 0xf0000000;
18568 inst
.is_neon
= TRUE
;
18572 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18574 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18575 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18576 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18578 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18580 if (flavour
== neon_cvt_flavour_invalid
)
18583 /* PR11109: Handle round-to-zero for VCVT conversions. */
18584 if (mode
== neon_cvt_mode_z
18585 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18586 && (flavour
== neon_cvt_flavour_s16_f16
18587 || flavour
== neon_cvt_flavour_u16_f16
18588 || flavour
== neon_cvt_flavour_s32_f32
18589 || flavour
== neon_cvt_flavour_u32_f32
18590 || flavour
== neon_cvt_flavour_s32_f64
18591 || flavour
== neon_cvt_flavour_u32_f64
)
18592 && (rs
== NS_FD
|| rs
== NS_FF
))
18594 do_vfp_nsyn_cvtz ();
18598 /* ARMv8.2 fp16 VCVT conversions. */
18599 if (mode
== neon_cvt_mode_z
18600 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18601 && (flavour
== neon_cvt_flavour_s32_f16
18602 || flavour
== neon_cvt_flavour_u32_f16
)
18605 do_vfp_nsyn_cvtz ();
18606 do_scalar_fp16_v82_encode ();
18610 /* VFP rather than Neon conversions. */
18611 if (flavour
>= neon_cvt_flavour_first_fp
)
18613 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18614 do_vfp_nsyn_cvt (rs
, flavour
);
18616 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18624 if (mode
== neon_cvt_mode_z
18625 && (flavour
== neon_cvt_flavour_f16_s16
18626 || flavour
== neon_cvt_flavour_f16_u16
18627 || flavour
== neon_cvt_flavour_s16_f16
18628 || flavour
== neon_cvt_flavour_u16_f16
18629 || flavour
== neon_cvt_flavour_f32_u32
18630 || flavour
== neon_cvt_flavour_f32_s32
18631 || flavour
== neon_cvt_flavour_s32_f32
18632 || flavour
== neon_cvt_flavour_u32_f32
))
18634 if (!check_simd_pred_availability (TRUE
,
18635 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18638 else if (mode
== neon_cvt_mode_n
)
18640 /* We are dealing with vcvt with the 'ne' condition. */
18642 inst
.instruction
= N_MNEM_vcvt
;
18643 do_neon_cvt_1 (neon_cvt_mode_z
);
18646 /* fall through. */
18650 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18651 0x0000100, 0x1000100, 0x0, 0x1000000};
18653 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18654 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18657 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18659 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18660 _("immediate value out of range"));
18663 case neon_cvt_flavour_f16_s16
:
18664 case neon_cvt_flavour_f16_u16
:
18665 case neon_cvt_flavour_s16_f16
:
18666 case neon_cvt_flavour_u16_f16
:
18667 constraint (inst
.operands
[2].imm
> 16,
18668 _("immediate value out of range"));
18670 case neon_cvt_flavour_f32_u32
:
18671 case neon_cvt_flavour_f32_s32
:
18672 case neon_cvt_flavour_s32_f32
:
18673 case neon_cvt_flavour_u32_f32
:
18674 constraint (inst
.operands
[2].imm
> 32,
18675 _("immediate value out of range"));
18678 inst
.error
= BAD_FPU
;
18683 /* Fixed-point conversion with #0 immediate is encoded as an
18684 integer conversion. */
18685 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18687 NEON_ENCODE (IMMED
, inst
);
18688 if (flavour
!= neon_cvt_flavour_invalid
)
18689 inst
.instruction
|= enctab
[flavour
];
18690 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18691 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18694 inst
.instruction
|= neon_quad (rs
) << 6;
18695 inst
.instruction
|= 1 << 21;
18696 if (flavour
< neon_cvt_flavour_s16_f16
)
18698 inst
.instruction
|= 1 << 21;
18699 immbits
= 32 - inst
.operands
[2].imm
;
18700 inst
.instruction
|= immbits
<< 16;
18704 inst
.instruction
|= 3 << 20;
18705 immbits
= 16 - inst
.operands
[2].imm
;
18706 inst
.instruction
|= immbits
<< 16;
18707 inst
.instruction
&= ~(1 << 9);
18710 neon_dp_fixup (&inst
);
18715 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18716 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18717 && (flavour
== neon_cvt_flavour_s16_f16
18718 || flavour
== neon_cvt_flavour_u16_f16
18719 || flavour
== neon_cvt_flavour_s32_f32
18720 || flavour
== neon_cvt_flavour_u32_f32
))
18722 if (!check_simd_pred_availability (TRUE
,
18723 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18726 else if (mode
== neon_cvt_mode_z
18727 && (flavour
== neon_cvt_flavour_f16_s16
18728 || flavour
== neon_cvt_flavour_f16_u16
18729 || flavour
== neon_cvt_flavour_s16_f16
18730 || flavour
== neon_cvt_flavour_u16_f16
18731 || flavour
== neon_cvt_flavour_f32_u32
18732 || flavour
== neon_cvt_flavour_f32_s32
18733 || flavour
== neon_cvt_flavour_s32_f32
18734 || flavour
== neon_cvt_flavour_u32_f32
))
18736 if (!check_simd_pred_availability (TRUE
,
18737 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18740 /* fall through. */
18742 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18745 NEON_ENCODE (FLOAT
, inst
);
18746 if (!check_simd_pred_availability (TRUE
,
18747 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18750 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18751 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18752 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18753 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18754 inst
.instruction
|= neon_quad (rs
) << 6;
18755 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18756 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18757 inst
.instruction
|= mode
<< 8;
18758 if (flavour
== neon_cvt_flavour_u16_f16
18759 || flavour
== neon_cvt_flavour_s16_f16
)
18760 /* Mask off the original size bits and reencode them. */
18761 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18764 inst
.instruction
|= 0xfc000000;
18766 inst
.instruction
|= 0xf0000000;
18772 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18773 0x100, 0x180, 0x0, 0x080};
18775 NEON_ENCODE (INTEGER
, inst
);
18777 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18779 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18783 if (flavour
!= neon_cvt_flavour_invalid
)
18784 inst
.instruction
|= enctab
[flavour
];
18786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18790 inst
.instruction
|= neon_quad (rs
) << 6;
18791 if (flavour
>= neon_cvt_flavour_s16_f16
18792 && flavour
<= neon_cvt_flavour_f16_u16
)
18793 /* Half precision. */
18794 inst
.instruction
|= 1 << 18;
18796 inst
.instruction
|= 2 << 18;
18798 neon_dp_fixup (&inst
);
18803 /* Half-precision conversions for Advanced SIMD -- neon. */
18806 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18810 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18812 as_bad (_("operand size must match register width"));
18817 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18819 as_bad (_("operand size must match register width"));
18824 inst
.instruction
= 0x3b60600;
18826 inst
.instruction
= 0x3b60700;
18828 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18829 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18830 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18831 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18832 neon_dp_fixup (&inst
);
18836 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18837 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18838 do_vfp_nsyn_cvt (rs
, flavour
);
18840 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18845 do_neon_cvtr (void)
18847 do_neon_cvt_1 (neon_cvt_mode_x
);
18853 do_neon_cvt_1 (neon_cvt_mode_z
);
18857 do_neon_cvta (void)
18859 do_neon_cvt_1 (neon_cvt_mode_a
);
18863 do_neon_cvtn (void)
18865 do_neon_cvt_1 (neon_cvt_mode_n
);
18869 do_neon_cvtp (void)
18871 do_neon_cvt_1 (neon_cvt_mode_p
);
18875 do_neon_cvtm (void)
18877 do_neon_cvt_1 (neon_cvt_mode_m
);
18881 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18884 mark_feature_used (&fpu_vfp_ext_armv8
);
18886 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18887 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18888 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18889 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18890 inst
.instruction
|= to
? 0x10000 : 0;
18891 inst
.instruction
|= t
? 0x80 : 0;
18892 inst
.instruction
|= is_double
? 0x100 : 0;
18893 do_vfp_cond_or_thumb ();
18897 do_neon_cvttb_1 (bfd_boolean t
)
18899 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18900 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18904 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18906 int single_to_half
= 0;
18907 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
18910 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18912 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18913 && (flavour
== neon_cvt_flavour_u16_f16
18914 || flavour
== neon_cvt_flavour_s16_f16
18915 || flavour
== neon_cvt_flavour_f16_s16
18916 || flavour
== neon_cvt_flavour_f16_u16
18917 || flavour
== neon_cvt_flavour_u32_f32
18918 || flavour
== neon_cvt_flavour_s32_f32
18919 || flavour
== neon_cvt_flavour_f32_s32
18920 || flavour
== neon_cvt_flavour_f32_u32
))
18923 inst
.instruction
= N_MNEM_vcvt
;
18924 set_pred_insn_type (INSIDE_VPT_INSN
);
18925 do_neon_cvt_1 (neon_cvt_mode_z
);
18928 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18929 single_to_half
= 1;
18930 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18932 first_error (BAD_FPU
);
18936 inst
.instruction
= 0xee3f0e01;
18937 inst
.instruction
|= single_to_half
<< 28;
18938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18940 inst
.instruction
|= t
<< 12;
18941 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18945 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18948 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18950 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18953 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18955 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18957 /* The VCVTB and VCVTT instructions with D-register operands
18958 don't work for SP only targets. */
18959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18963 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18965 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18967 /* The VCVTB and VCVTT instructions with D-register operands
18968 don't work for SP only targets. */
18969 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18973 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18980 do_neon_cvtb (void)
18982 do_neon_cvttb_1 (FALSE
);
18987 do_neon_cvtt (void)
18989 do_neon_cvttb_1 (TRUE
);
18993 neon_move_immediate (void)
18995 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18996 struct neon_type_el et
= neon_check_type (2, rs
,
18997 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18998 unsigned immlo
, immhi
= 0, immbits
;
18999 int op
, cmode
, float_p
;
19001 constraint (et
.type
== NT_invtype
,
19002 _("operand size must be specified for immediate VMOV"));
19004 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19005 op
= (inst
.instruction
& (1 << 5)) != 0;
19007 immlo
= inst
.operands
[1].imm
;
19008 if (inst
.operands
[1].regisimm
)
19009 immhi
= inst
.operands
[1].reg
;
19011 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19012 _("immediate has bits set outside the operand size"));
19014 float_p
= inst
.operands
[1].immisfloat
;
19016 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19017 et
.size
, et
.type
)) == FAIL
)
19019 /* Invert relevant bits only. */
19020 neon_invert_size (&immlo
, &immhi
, et
.size
);
19021 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19022 with one or the other; those cases are caught by
19023 neon_cmode_for_move_imm. */
19025 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19026 &op
, et
.size
, et
.type
)) == FAIL
)
19028 first_error (_("immediate out of range"));
19033 inst
.instruction
&= ~(1 << 5);
19034 inst
.instruction
|= op
<< 5;
19036 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19037 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19038 inst
.instruction
|= neon_quad (rs
) << 6;
19039 inst
.instruction
|= cmode
<< 8;
19041 neon_write_immbits (immbits
);
19047 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19050 if (inst
.operands
[1].isreg
)
19052 enum neon_shape rs
;
19053 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19054 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19056 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19058 NEON_ENCODE (INTEGER
, inst
);
19059 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19060 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19061 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19062 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19063 inst
.instruction
|= neon_quad (rs
) << 6;
19067 NEON_ENCODE (IMMED
, inst
);
19068 neon_move_immediate ();
19071 neon_dp_fixup (&inst
);
19073 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19075 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19076 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19077 _("immediate value out of range"));
19081 /* Encode instructions of form:
19083 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19084 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19087 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19091 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19092 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19093 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19094 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19095 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19096 inst
.instruction
|= neon_logbits (size
) << 20;
19098 neon_dp_fixup (&inst
);
19102 do_neon_dyadic_long (void)
19104 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19107 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19110 NEON_ENCODE (INTEGER
, inst
);
19111 /* FIXME: Type checking for lengthening op. */
19112 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19113 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19114 neon_mixed_length (et
, et
.size
);
19116 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19117 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19119 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19120 in an IT block with le/lt conditions. */
19122 if (inst
.cond
== 0xf)
19124 else if (inst
.cond
== 0x10)
19127 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19129 if (inst
.instruction
== N_MNEM_vaddl
)
19131 inst
.instruction
= N_MNEM_vadd
;
19132 do_neon_addsub_if_i ();
19134 else if (inst
.instruction
== N_MNEM_vsubl
)
19136 inst
.instruction
= N_MNEM_vsub
;
19137 do_neon_addsub_if_i ();
19139 else if (inst
.instruction
== N_MNEM_vabdl
)
19141 inst
.instruction
= N_MNEM_vabd
;
19142 do_neon_dyadic_if_su ();
19146 first_error (BAD_FPU
);
19150 do_neon_abal (void)
19152 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19153 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19154 neon_mixed_length (et
, et
.size
);
19158 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19160 if (inst
.operands
[2].isscalar
)
19162 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19163 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19164 NEON_ENCODE (SCALAR
, inst
);
19165 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19169 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19170 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19171 NEON_ENCODE (INTEGER
, inst
);
19172 neon_mixed_length (et
, et
.size
);
19177 do_neon_mac_maybe_scalar_long (void)
19179 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19182 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19183 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19186 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19188 unsigned regno
= NEON_SCALAR_REG (scalar
);
19189 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19193 if (regno
> 7 || elno
> 3)
19196 return ((regno
& 0x7)
19197 | ((elno
& 0x1) << 3)
19198 | (((elno
>> 1) & 0x1) << 5));
19202 if (regno
> 15 || elno
> 1)
19205 return (((regno
& 0x1) << 5)
19206 | ((regno
>> 1) & 0x7)
19207 | ((elno
& 0x1) << 3));
19211 first_error (_("scalar out of range for multiply instruction"));
19216 do_neon_fmac_maybe_scalar_long (int subtype
)
19218 enum neon_shape rs
;
19220 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19221 field (bits[21:20]) has different meaning. For scalar index variant, it's
19222 used to differentiate add and subtract, otherwise it's with fixed value
19226 if (inst
.cond
!= COND_ALWAYS
)
19227 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19228 "behaviour is UNPREDICTABLE"));
19230 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19236 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19237 be a scalar index register. */
19238 if (inst
.operands
[2].isscalar
)
19240 high8
= 0xfe000000;
19243 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19247 high8
= 0xfc000000;
19250 inst
.instruction
|= (0x1 << 23);
19251 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19254 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19256 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19257 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19258 so we simply pass -1 as size. */
19259 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19260 neon_three_same (quad_p
, 0, size
);
19262 /* Undo neon_dp_fixup. Redo the high eight bits. */
19263 inst
.instruction
&= 0x00ffffff;
19264 inst
.instruction
|= high8
;
19266 #define LOW1(R) ((R) & 0x1)
19267 #define HI4(R) (((R) >> 1) & 0xf)
19268 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19269 whether the instruction is in Q form and whether Vm is a scalar indexed
19271 if (inst
.operands
[2].isscalar
)
19274 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19275 inst
.instruction
&= 0xffffffd0;
19276 inst
.instruction
|= rm
;
19280 /* Redo Rn as well. */
19281 inst
.instruction
&= 0xfff0ff7f;
19282 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19283 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19288 /* Redo Rn and Rm. */
19289 inst
.instruction
&= 0xfff0ff50;
19290 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19291 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19292 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19293 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19298 do_neon_vfmal (void)
19300 return do_neon_fmac_maybe_scalar_long (0);
19304 do_neon_vfmsl (void)
19306 return do_neon_fmac_maybe_scalar_long (1);
19310 do_neon_dyadic_wide (void)
19312 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19313 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19314 neon_mixed_length (et
, et
.size
);
19318 do_neon_dyadic_narrow (void)
19320 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19321 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19322 /* Operand sign is unimportant, and the U bit is part of the opcode,
19323 so force the operand type to integer. */
19324 et
.type
= NT_integer
;
19325 neon_mixed_length (et
, et
.size
/ 2);
19329 do_neon_mul_sat_scalar_long (void)
19331 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19335 do_neon_vmull (void)
19337 if (inst
.operands
[2].isscalar
)
19338 do_neon_mac_maybe_scalar_long ();
19341 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19342 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19344 if (et
.type
== NT_poly
)
19345 NEON_ENCODE (POLY
, inst
);
19347 NEON_ENCODE (INTEGER
, inst
);
19349 /* For polynomial encoding the U bit must be zero, and the size must
19350 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19351 obviously, as 0b10). */
19354 /* Check we're on the correct architecture. */
19355 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19357 _("Instruction form not available on this architecture.");
19362 neon_mixed_length (et
, et
.size
);
19369 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19370 struct neon_type_el et
= neon_check_type (3, rs
,
19371 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19372 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19374 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19375 _("shift out of range"));
19376 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19377 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19378 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19379 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19380 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19381 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19382 inst
.instruction
|= neon_quad (rs
) << 6;
19383 inst
.instruction
|= imm
<< 8;
19385 neon_dp_fixup (&inst
);
19391 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19394 enum neon_shape rs
;
19395 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19396 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19398 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19400 struct neon_type_el et
= neon_check_type (2, rs
,
19401 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19403 unsigned op
= (inst
.instruction
>> 7) & 3;
19404 /* N (width of reversed regions) is encoded as part of the bitmask. We
19405 extract it here to check the elements to be reversed are smaller.
19406 Otherwise we'd get a reserved instruction. */
19407 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19409 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19410 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19411 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19412 " operands makes instruction UNPREDICTABLE"));
19414 gas_assert (elsize
!= 0);
19415 constraint (et
.size
>= elsize
,
19416 _("elements must be smaller than reversal region"));
19417 neon_two_same (neon_quad (rs
), 1, et
.size
);
19423 if (inst
.operands
[1].isscalar
)
19425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19427 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19428 struct neon_type_el et
= neon_check_type (2, rs
,
19429 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19430 unsigned sizebits
= et
.size
>> 3;
19431 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19432 int logsize
= neon_logbits (et
.size
);
19433 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19435 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19438 NEON_ENCODE (SCALAR
, inst
);
19439 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19440 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19441 inst
.instruction
|= LOW4 (dm
);
19442 inst
.instruction
|= HI1 (dm
) << 5;
19443 inst
.instruction
|= neon_quad (rs
) << 6;
19444 inst
.instruction
|= x
<< 17;
19445 inst
.instruction
|= sizebits
<< 16;
19447 neon_dp_fixup (&inst
);
19451 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19452 struct neon_type_el et
= neon_check_type (2, rs
,
19453 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19456 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19460 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19463 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19465 if (inst
.operands
[1].reg
== REG_SP
)
19466 as_tsktsk (MVE_BAD_SP
);
19467 else if (inst
.operands
[1].reg
== REG_PC
)
19468 as_tsktsk (MVE_BAD_PC
);
19471 /* Duplicate ARM register to lanes of vector. */
19472 NEON_ENCODE (ARMREG
, inst
);
19475 case 8: inst
.instruction
|= 0x400000; break;
19476 case 16: inst
.instruction
|= 0x000020; break;
19477 case 32: inst
.instruction
|= 0x000000; break;
19480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19482 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19483 inst
.instruction
|= neon_quad (rs
) << 21;
19484 /* The encoding for this instruction is identical for the ARM and Thumb
19485 variants, except for the condition field. */
19486 do_vfp_cond_or_thumb ();
19491 do_mve_mov (int toQ
)
19493 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19495 if (inst
.cond
> COND_ALWAYS
)
19496 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19498 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19507 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19508 _("Index one must be [2,3] and index two must be two less than"
19510 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19511 _("General purpose registers may not be the same"));
19512 constraint (inst
.operands
[Rt
].reg
== REG_SP
19513 || inst
.operands
[Rt2
].reg
== REG_SP
,
19515 constraint (inst
.operands
[Rt
].reg
== REG_PC
19516 || inst
.operands
[Rt2
].reg
== REG_PC
,
19519 inst
.instruction
= 0xec000f00;
19520 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19521 inst
.instruction
|= !!toQ
<< 20;
19522 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19523 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19524 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19525 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19531 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19534 if (inst
.cond
> COND_ALWAYS
)
19535 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19537 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19539 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19542 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19543 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19544 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19545 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19546 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19551 /* VMOV has particularly many variations. It can be one of:
19552 0. VMOV<c><q> <Qd>, <Qm>
19553 1. VMOV<c><q> <Dd>, <Dm>
19554 (Register operations, which are VORR with Rm = Rn.)
19555 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19556 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19558 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19559 (ARM register to scalar.)
19560 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19561 (Two ARM registers to vector.)
19562 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19563 (Scalar to ARM register.)
19564 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19565 (Vector to two ARM registers.)
19566 8. VMOV.F32 <Sd>, <Sm>
19567 9. VMOV.F64 <Dd>, <Dm>
19568 (VFP register moves.)
19569 10. VMOV.F32 <Sd>, #imm
19570 11. VMOV.F64 <Dd>, #imm
19571 (VFP float immediate load.)
19572 12. VMOV <Rd>, <Sm>
19573 (VFP single to ARM reg.)
19574 13. VMOV <Sd>, <Rm>
19575 (ARM reg to VFP single.)
19576 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19577 (Two ARM regs to two VFP singles.)
19578 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19579 (Two VFP singles to two ARM regs.)
19580 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19581 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19582 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19583 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19585 These cases can be disambiguated using neon_select_shape, except cases 1/9
19586 and 3/11 which depend on the operand type too.
19588 All the encoded bits are hardcoded by this function.
19590 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19591 Cases 5, 7 may be used with VFPv2 and above.
19593 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19594 can specify a type where it doesn't make sense to, and is ignored). */
19599 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19600 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19601 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19602 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19604 struct neon_type_el et
;
19605 const char *ldconst
= 0;
19609 case NS_DD
: /* case 1/9. */
19610 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19611 /* It is not an error here if no type is given. */
19613 if (et
.type
== NT_float
&& et
.size
== 64)
19615 do_vfp_nsyn_opcode ("fcpyd");
19618 /* fall through. */
19620 case NS_QQ
: /* case 0/1. */
19622 if (!check_simd_pred_availability (FALSE
,
19623 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19625 /* The architecture manual I have doesn't explicitly state which
19626 value the U bit should have for register->register moves, but
19627 the equivalent VORR instruction has U = 0, so do that. */
19628 inst
.instruction
= 0x0200110;
19629 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19632 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19633 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19634 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19635 inst
.instruction
|= neon_quad (rs
) << 6;
19637 neon_dp_fixup (&inst
);
19641 case NS_DI
: /* case 3/11. */
19642 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19644 if (et
.type
== NT_float
&& et
.size
== 64)
19646 /* case 11 (fconstd). */
19647 ldconst
= "fconstd";
19648 goto encode_fconstd
;
19650 /* fall through. */
19652 case NS_QI
: /* case 2/3. */
19653 if (!check_simd_pred_availability (FALSE
,
19654 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19656 inst
.instruction
= 0x0800010;
19657 neon_move_immediate ();
19658 neon_dp_fixup (&inst
);
19661 case NS_SR
: /* case 4. */
19663 unsigned bcdebits
= 0;
19665 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19666 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19668 /* .<size> is optional here, defaulting to .32. */
19669 if (inst
.vectype
.elems
== 0
19670 && inst
.operands
[0].vectype
.type
== NT_invtype
19671 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19673 inst
.vectype
.el
[0].type
= NT_untyped
;
19674 inst
.vectype
.el
[0].size
= 32;
19675 inst
.vectype
.elems
= 1;
19678 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19679 logsize
= neon_logbits (et
.size
);
19683 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19684 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19690 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19694 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19696 if (inst
.operands
[1].reg
== REG_SP
)
19697 as_tsktsk (MVE_BAD_SP
);
19698 else if (inst
.operands
[1].reg
== REG_PC
)
19699 as_tsktsk (MVE_BAD_PC
);
19701 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19703 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19704 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19709 case 8: bcdebits
= 0x8; break;
19710 case 16: bcdebits
= 0x1; break;
19711 case 32: bcdebits
= 0x0; break;
19715 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19717 inst
.instruction
= 0xe000b10;
19718 do_vfp_cond_or_thumb ();
19719 inst
.instruction
|= LOW4 (dn
) << 16;
19720 inst
.instruction
|= HI1 (dn
) << 7;
19721 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19722 inst
.instruction
|= (bcdebits
& 3) << 5;
19723 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19724 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19728 case NS_DRR
: /* case 5 (fmdrr). */
19729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19730 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19733 inst
.instruction
= 0xc400b10;
19734 do_vfp_cond_or_thumb ();
19735 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19736 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19737 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19738 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19741 case NS_RS
: /* case 6. */
19744 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19745 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19746 unsigned abcdebits
= 0;
19748 /* .<dt> is optional here, defaulting to .32. */
19749 if (inst
.vectype
.elems
== 0
19750 && inst
.operands
[0].vectype
.type
== NT_invtype
19751 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19753 inst
.vectype
.el
[0].type
= NT_untyped
;
19754 inst
.vectype
.el
[0].size
= 32;
19755 inst
.vectype
.elems
= 1;
19758 et
= neon_check_type (2, NS_NULL
,
19759 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19760 logsize
= neon_logbits (et
.size
);
19764 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19765 && vfp_or_neon_is_neon (NEON_CHECK_CC
19766 | NEON_CHECK_ARCH
) == FAIL
)
19771 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19772 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19776 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19778 if (inst
.operands
[0].reg
== REG_SP
)
19779 as_tsktsk (MVE_BAD_SP
);
19780 else if (inst
.operands
[0].reg
== REG_PC
)
19781 as_tsktsk (MVE_BAD_PC
);
19784 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19786 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19787 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19791 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19792 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19793 case 32: abcdebits
= 0x00; break;
19797 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19798 inst
.instruction
= 0xe100b10;
19799 do_vfp_cond_or_thumb ();
19800 inst
.instruction
|= LOW4 (dn
) << 16;
19801 inst
.instruction
|= HI1 (dn
) << 7;
19802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19803 inst
.instruction
|= (abcdebits
& 3) << 5;
19804 inst
.instruction
|= (abcdebits
>> 2) << 21;
19805 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19809 case NS_RRD
: /* case 7 (fmrrd). */
19810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19811 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19814 inst
.instruction
= 0xc500b10;
19815 do_vfp_cond_or_thumb ();
19816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19817 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19818 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19819 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19822 case NS_FF
: /* case 8 (fcpys). */
19823 do_vfp_nsyn_opcode ("fcpys");
19827 case NS_FI
: /* case 10 (fconsts). */
19828 ldconst
= "fconsts";
19830 if (!inst
.operands
[1].immisfloat
)
19833 /* Immediate has to fit in 8 bits so float is enough. */
19834 float imm
= (float) inst
.operands
[1].imm
;
19835 memcpy (&new_imm
, &imm
, sizeof (float));
19836 /* But the assembly may have been written to provide an integer
19837 bit pattern that equates to a float, so check that the
19838 conversion has worked. */
19839 if (is_quarter_float (new_imm
))
19841 if (is_quarter_float (inst
.operands
[1].imm
))
19842 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19844 inst
.operands
[1].imm
= new_imm
;
19845 inst
.operands
[1].immisfloat
= 1;
19849 if (is_quarter_float (inst
.operands
[1].imm
))
19851 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19852 do_vfp_nsyn_opcode (ldconst
);
19854 /* ARMv8.2 fp16 vmov.f16 instruction. */
19856 do_scalar_fp16_v82_encode ();
19859 first_error (_("immediate out of range"));
19863 case NS_RF
: /* case 12 (fmrs). */
19864 do_vfp_nsyn_opcode ("fmrs");
19865 /* ARMv8.2 fp16 vmov.f16 instruction. */
19867 do_scalar_fp16_v82_encode ();
19871 case NS_FR
: /* case 13 (fmsr). */
19872 do_vfp_nsyn_opcode ("fmsr");
19873 /* ARMv8.2 fp16 vmov.f16 instruction. */
19875 do_scalar_fp16_v82_encode ();
19885 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19886 (one of which is a list), but we have parsed four. Do some fiddling to
19887 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19889 case NS_RRFF
: /* case 14 (fmrrs). */
19890 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19891 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19893 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19894 _("VFP registers must be adjacent"));
19895 inst
.operands
[2].imm
= 2;
19896 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19897 do_vfp_nsyn_opcode ("fmrrs");
19900 case NS_FFRR
: /* case 15 (fmsrr). */
19901 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19902 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19904 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19905 _("VFP registers must be adjacent"));
19906 inst
.operands
[1] = inst
.operands
[2];
19907 inst
.operands
[2] = inst
.operands
[3];
19908 inst
.operands
[0].imm
= 2;
19909 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19910 do_vfp_nsyn_opcode ("fmsrr");
19914 /* neon_select_shape has determined that the instruction
19915 shape is wrong and has already set the error message. */
19926 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19927 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19928 && !inst
.operands
[2].present
))
19930 inst
.instruction
= 0;
19933 set_pred_insn_type (INSIDE_IT_INSN
);
19938 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19941 if (inst
.cond
!= COND_ALWAYS
)
19942 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19944 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19945 | N_S16
| N_U16
| N_KEY
);
19947 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19948 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19949 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19950 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19951 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19952 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19957 do_neon_rshift_round_imm (void)
19959 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19962 enum neon_shape rs
;
19963 struct neon_type_el et
;
19965 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19967 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
19968 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
19972 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19973 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19975 int imm
= inst
.operands
[2].imm
;
19977 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19980 inst
.operands
[2].present
= 0;
19985 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19986 _("immediate out of range for shift"));
19987 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19992 do_neon_movhf (void)
19994 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19995 constraint (rs
!= NS_HH
, _("invalid suffix"));
19997 if (inst
.cond
!= COND_ALWAYS
)
20001 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20002 " the behaviour is UNPREDICTABLE"));
20006 inst
.error
= BAD_COND
;
20011 do_vfp_sp_monadic ();
20014 inst
.instruction
|= 0xf0000000;
20018 do_neon_movl (void)
20020 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20021 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20022 unsigned sizebits
= et
.size
>> 3;
20023 inst
.instruction
|= sizebits
<< 19;
20024 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20030 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20031 struct neon_type_el et
= neon_check_type (2, rs
,
20032 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20033 NEON_ENCODE (INTEGER
, inst
);
20034 neon_two_same (neon_quad (rs
), 1, et
.size
);
20038 do_neon_zip_uzp (void)
20040 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20041 struct neon_type_el et
= neon_check_type (2, rs
,
20042 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20043 if (rs
== NS_DD
&& et
.size
== 32)
20045 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20046 inst
.instruction
= N_MNEM_vtrn
;
20050 neon_two_same (neon_quad (rs
), 1, et
.size
);
20054 do_neon_sat_abs_neg (void)
20056 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20059 enum neon_shape rs
;
20060 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20061 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20063 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20064 struct neon_type_el et
= neon_check_type (2, rs
,
20065 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20066 neon_two_same (neon_quad (rs
), 1, et
.size
);
20070 do_neon_pair_long (void)
20072 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20073 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20074 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20075 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20076 neon_two_same (neon_quad (rs
), 1, et
.size
);
20080 do_neon_recip_est (void)
20082 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20083 struct neon_type_el et
= neon_check_type (2, rs
,
20084 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20085 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20086 neon_two_same (neon_quad (rs
), 1, et
.size
);
20092 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20095 enum neon_shape rs
;
20096 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20097 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20099 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20101 struct neon_type_el et
= neon_check_type (2, rs
,
20102 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20103 neon_two_same (neon_quad (rs
), 1, et
.size
);
20109 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20112 enum neon_shape rs
;
20113 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20114 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20116 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20118 struct neon_type_el et
= neon_check_type (2, rs
,
20119 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20120 neon_two_same (neon_quad (rs
), 1, et
.size
);
20126 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20127 struct neon_type_el et
= neon_check_type (2, rs
,
20128 N_EQK
| N_INT
, N_8
| N_KEY
);
20129 neon_two_same (neon_quad (rs
), 1, et
.size
);
20135 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20136 neon_two_same (neon_quad (rs
), 1, -1);
20140 do_neon_tbl_tbx (void)
20142 unsigned listlenbits
;
20143 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20145 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20147 first_error (_("bad list length for table lookup"));
20151 listlenbits
= inst
.operands
[1].imm
- 1;
20152 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20153 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20154 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20155 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20156 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20157 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20158 inst
.instruction
|= listlenbits
<< 8;
20160 neon_dp_fixup (&inst
);
20164 do_neon_ldm_stm (void)
20166 /* P, U and L bits are part of bitmask. */
20167 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20168 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20170 if (inst
.operands
[1].issingle
)
20172 do_vfp_nsyn_ldm_stm (is_dbmode
);
20176 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20177 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20179 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20180 _("register list must contain at least 1 and at most 16 "
20183 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20184 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20185 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20186 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20188 inst
.instruction
|= offsetbits
;
20190 do_vfp_cond_or_thumb ();
20194 do_neon_ldr_str (void)
20196 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20198 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20199 And is UNPREDICTABLE in thumb mode. */
20201 && inst
.operands
[1].reg
== REG_PC
20202 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20205 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20206 else if (warn_on_deprecated
)
20207 as_tsktsk (_("Use of PC here is deprecated"));
20210 if (inst
.operands
[0].issingle
)
20213 do_vfp_nsyn_opcode ("flds");
20215 do_vfp_nsyn_opcode ("fsts");
20217 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20218 if (inst
.vectype
.el
[0].size
== 16)
20219 do_scalar_fp16_v82_encode ();
20224 do_vfp_nsyn_opcode ("fldd");
20226 do_vfp_nsyn_opcode ("fstd");
20231 do_t_vldr_vstr_sysreg (void)
20233 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20234 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20236 /* Use of PC is UNPREDICTABLE. */
20237 if (inst
.operands
[1].reg
== REG_PC
)
20238 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20240 if (inst
.operands
[1].immisreg
)
20241 inst
.error
= _("instruction does not accept register index");
20243 if (!inst
.operands
[1].isreg
)
20244 inst
.error
= _("instruction does not accept PC-relative addressing");
20246 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20247 inst
.error
= _("immediate value out of range");
20249 inst
.instruction
= 0xec000f80;
20251 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20252 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20253 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20254 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20258 do_vldr_vstr (void)
20260 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20262 /* VLDR/VSTR (System Register). */
20265 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20266 as_bad (_("Instruction not permitted on this architecture"));
20268 do_t_vldr_vstr_sysreg ();
20273 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20274 as_bad (_("Instruction not permitted on this architecture"));
20275 do_neon_ldr_str ();
20279 /* "interleave" version also handles non-interleaving register VLD1/VST1
20283 do_neon_ld_st_interleave (void)
20285 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20286 N_8
| N_16
| N_32
| N_64
);
20287 unsigned alignbits
= 0;
20289 /* The bits in this table go:
20290 0: register stride of one (0) or two (1)
20291 1,2: register list length, minus one (1, 2, 3, 4).
20292 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20293 We use -1 for invalid entries. */
20294 const int typetable
[] =
20296 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20297 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20298 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20299 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20303 if (et
.type
== NT_invtype
)
20306 if (inst
.operands
[1].immisalign
)
20307 switch (inst
.operands
[1].imm
>> 8)
20309 case 64: alignbits
= 1; break;
20311 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20312 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20313 goto bad_alignment
;
20317 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20318 goto bad_alignment
;
20323 first_error (_("bad alignment"));
20327 inst
.instruction
|= alignbits
<< 4;
20328 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20330 /* Bits [4:6] of the immediate in a list specifier encode register stride
20331 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20332 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20333 up the right value for "type" in a table based on this value and the given
20334 list style, then stick it back. */
20335 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20336 | (((inst
.instruction
>> 8) & 3) << 3);
20338 typebits
= typetable
[idx
];
20340 constraint (typebits
== -1, _("bad list type for instruction"));
20341 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20344 inst
.instruction
&= ~0xf00;
20345 inst
.instruction
|= typebits
<< 8;
20348 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20349 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20350 otherwise. The variable arguments are a list of pairs of legal (size, align)
20351 values, terminated with -1. */
20354 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20357 int result
= FAIL
, thissize
, thisalign
;
20359 if (!inst
.operands
[1].immisalign
)
20365 va_start (ap
, do_alignment
);
20369 thissize
= va_arg (ap
, int);
20370 if (thissize
== -1)
20372 thisalign
= va_arg (ap
, int);
20374 if (size
== thissize
&& align
== thisalign
)
20377 while (result
!= SUCCESS
);
20381 if (result
== SUCCESS
)
20384 first_error (_("unsupported alignment for instruction"));
20390 do_neon_ld_st_lane (void)
20392 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20393 int align_good
, do_alignment
= 0;
20394 int logsize
= neon_logbits (et
.size
);
20395 int align
= inst
.operands
[1].imm
>> 8;
20396 int n
= (inst
.instruction
>> 8) & 3;
20397 int max_el
= 64 / et
.size
;
20399 if (et
.type
== NT_invtype
)
20402 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20403 _("bad list length"));
20404 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20405 _("scalar index out of range"));
20406 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20408 _("stride of 2 unavailable when element size is 8"));
20412 case 0: /* VLD1 / VST1. */
20413 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20415 if (align_good
== FAIL
)
20419 unsigned alignbits
= 0;
20422 case 16: alignbits
= 0x1; break;
20423 case 32: alignbits
= 0x3; break;
20426 inst
.instruction
|= alignbits
<< 4;
20430 case 1: /* VLD2 / VST2. */
20431 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20432 16, 32, 32, 64, -1);
20433 if (align_good
== FAIL
)
20436 inst
.instruction
|= 1 << 4;
20439 case 2: /* VLD3 / VST3. */
20440 constraint (inst
.operands
[1].immisalign
,
20441 _("can't use alignment with this instruction"));
20444 case 3: /* VLD4 / VST4. */
20445 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20446 16, 64, 32, 64, 32, 128, -1);
20447 if (align_good
== FAIL
)
20451 unsigned alignbits
= 0;
20454 case 8: alignbits
= 0x1; break;
20455 case 16: alignbits
= 0x1; break;
20456 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20459 inst
.instruction
|= alignbits
<< 4;
20466 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20467 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20468 inst
.instruction
|= 1 << (4 + logsize
);
20470 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20471 inst
.instruction
|= logsize
<< 10;
20474 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20477 do_neon_ld_dup (void)
20479 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20480 int align_good
, do_alignment
= 0;
20482 if (et
.type
== NT_invtype
)
20485 switch ((inst
.instruction
>> 8) & 3)
20487 case 0: /* VLD1. */
20488 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20489 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20490 &do_alignment
, 16, 16, 32, 32, -1);
20491 if (align_good
== FAIL
)
20493 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20496 case 2: inst
.instruction
|= 1 << 5; break;
20497 default: first_error (_("bad list length")); return;
20499 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20502 case 1: /* VLD2. */
20503 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20504 &do_alignment
, 8, 16, 16, 32, 32, 64,
20506 if (align_good
== FAIL
)
20508 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20509 _("bad list length"));
20510 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20511 inst
.instruction
|= 1 << 5;
20512 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20515 case 2: /* VLD3. */
20516 constraint (inst
.operands
[1].immisalign
,
20517 _("can't use alignment with this instruction"));
20518 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20519 _("bad list length"));
20520 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20521 inst
.instruction
|= 1 << 5;
20522 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20525 case 3: /* VLD4. */
20527 int align
= inst
.operands
[1].imm
>> 8;
20528 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20529 16, 64, 32, 64, 32, 128, -1);
20530 if (align_good
== FAIL
)
20532 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20533 _("bad list length"));
20534 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20535 inst
.instruction
|= 1 << 5;
20536 if (et
.size
== 32 && align
== 128)
20537 inst
.instruction
|= 0x3 << 6;
20539 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20546 inst
.instruction
|= do_alignment
<< 4;
20549 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20550 apart from bits [11:4]. */
20553 do_neon_ldx_stx (void)
20555 if (inst
.operands
[1].isreg
)
20556 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20558 switch (NEON_LANE (inst
.operands
[0].imm
))
20560 case NEON_INTERLEAVE_LANES
:
20561 NEON_ENCODE (INTERLV
, inst
);
20562 do_neon_ld_st_interleave ();
20565 case NEON_ALL_LANES
:
20566 NEON_ENCODE (DUP
, inst
);
20567 if (inst
.instruction
== N_INV
)
20569 first_error ("only loads support such operands");
20576 NEON_ENCODE (LANE
, inst
);
20577 do_neon_ld_st_lane ();
20580 /* L bit comes from bit mask. */
20581 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20582 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20583 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20585 if (inst
.operands
[1].postind
)
20587 int postreg
= inst
.operands
[1].imm
& 0xf;
20588 constraint (!inst
.operands
[1].immisreg
,
20589 _("post-index must be a register"));
20590 constraint (postreg
== 0xd || postreg
== 0xf,
20591 _("bad register for post-index"));
20592 inst
.instruction
|= postreg
;
20596 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20597 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20598 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20601 if (inst
.operands
[1].writeback
)
20603 inst
.instruction
|= 0xd;
20606 inst
.instruction
|= 0xf;
20610 inst
.instruction
|= 0xf9000000;
20612 inst
.instruction
|= 0xf4000000;
20617 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20619 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20620 D register operands. */
20621 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20625 NEON_ENCODE (FPV8
, inst
);
20627 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20629 do_vfp_sp_dyadic ();
20631 /* ARMv8.2 fp16 instruction. */
20633 do_scalar_fp16_v82_encode ();
20636 do_vfp_dp_rd_rn_rm ();
20639 inst
.instruction
|= 0x100;
20641 inst
.instruction
|= 0xf0000000;
20647 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20649 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20650 first_error (_("invalid instruction shape"));
20656 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20657 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20659 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20662 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20665 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20669 do_vrint_1 (enum neon_cvt_mode mode
)
20671 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20672 struct neon_type_el et
;
20677 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20678 D register operands. */
20679 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20680 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20683 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20685 if (et
.type
!= NT_invtype
)
20687 /* VFP encodings. */
20688 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20689 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20690 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20692 NEON_ENCODE (FPV8
, inst
);
20693 if (rs
== NS_FF
|| rs
== NS_HH
)
20694 do_vfp_sp_monadic ();
20696 do_vfp_dp_rd_rm ();
20700 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20701 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20702 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20703 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20704 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20705 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20706 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20710 inst
.instruction
|= (rs
== NS_DD
) << 8;
20711 do_vfp_cond_or_thumb ();
20713 /* ARMv8.2 fp16 vrint instruction. */
20715 do_scalar_fp16_v82_encode ();
20719 /* Neon encodings (or something broken...). */
20721 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20723 if (et
.type
== NT_invtype
)
20726 if (!check_simd_pred_availability (TRUE
,
20727 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20730 NEON_ENCODE (FLOAT
, inst
);
20732 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20733 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20734 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20735 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20736 inst
.instruction
|= neon_quad (rs
) << 6;
20737 /* Mask off the original size bits and reencode them. */
20738 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20739 | neon_logbits (et
.size
) << 18);
20743 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20744 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20745 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20746 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20747 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20748 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20749 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20754 inst
.instruction
|= 0xfc000000;
20756 inst
.instruction
|= 0xf0000000;
20763 do_vrint_1 (neon_cvt_mode_x
);
20769 do_vrint_1 (neon_cvt_mode_z
);
20775 do_vrint_1 (neon_cvt_mode_r
);
20781 do_vrint_1 (neon_cvt_mode_a
);
20787 do_vrint_1 (neon_cvt_mode_n
);
20793 do_vrint_1 (neon_cvt_mode_p
);
20799 do_vrint_1 (neon_cvt_mode_m
);
20803 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20805 unsigned regno
= NEON_SCALAR_REG (opnd
);
20806 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20808 if (elsize
== 16 && elno
< 2 && regno
< 16)
20809 return regno
| (elno
<< 4);
20810 else if (elsize
== 32 && elno
== 0)
20813 first_error (_("scalar out of range"));
20820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20821 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20822 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20823 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20824 _("expression too complex"));
20825 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20826 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20827 _("immediate out of range"));
20830 if (!check_simd_pred_availability (TRUE
,
20831 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20834 if (inst
.operands
[2].isscalar
)
20836 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20837 first_error (_("invalid instruction shape"));
20838 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20839 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20840 N_KEY
| N_F16
| N_F32
).size
;
20841 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20843 inst
.instruction
= 0xfe000800;
20844 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20845 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20846 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20847 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20848 inst
.instruction
|= LOW4 (m
);
20849 inst
.instruction
|= HI1 (m
) << 5;
20850 inst
.instruction
|= neon_quad (rs
) << 6;
20851 inst
.instruction
|= rot
<< 20;
20852 inst
.instruction
|= (size
== 32) << 23;
20856 enum neon_shape rs
;
20857 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20858 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20860 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20862 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20863 N_KEY
| N_F16
| N_F32
).size
;
20864 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20865 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20866 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20867 as_tsktsk (BAD_MVE_SRCDEST
);
20869 neon_three_same (neon_quad (rs
), 0, -1);
20870 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20871 inst
.instruction
|= 0xfc200800;
20872 inst
.instruction
|= rot
<< 23;
20873 inst
.instruction
|= (size
== 32) << 20;
20880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20881 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20882 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20883 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20884 _("expression too complex"));
20886 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20887 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20888 enum neon_shape rs
;
20889 struct neon_type_el et
;
20890 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20892 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20893 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20897 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20898 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20900 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20901 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20902 "operand makes instruction UNPREDICTABLE"));
20905 if (et
.type
== NT_invtype
)
20908 if (!check_simd_pred_availability (et
.type
== NT_float
,
20909 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20912 if (et
.type
== NT_float
)
20914 neon_three_same (neon_quad (rs
), 0, -1);
20915 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20916 inst
.instruction
|= 0xfc800800;
20917 inst
.instruction
|= (rot
== 270) << 24;
20918 inst
.instruction
|= (et
.size
== 32) << 20;
20922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20923 inst
.instruction
= 0xfe000f00;
20924 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20925 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20927 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20928 inst
.instruction
|= (rot
== 270) << 12;
20929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20930 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20931 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20936 /* Dot Product instructions encoding support. */
20939 do_neon_dotproduct (int unsigned_p
)
20941 enum neon_shape rs
;
20942 unsigned scalar_oprd2
= 0;
20945 if (inst
.cond
!= COND_ALWAYS
)
20946 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20947 "is UNPREDICTABLE"));
20949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20952 /* Dot Product instructions are in three-same D/Q register format or the third
20953 operand can be a scalar index register. */
20954 if (inst
.operands
[2].isscalar
)
20956 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20957 high8
= 0xfe000000;
20958 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20962 high8
= 0xfc000000;
20963 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20967 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20969 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20971 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20972 Product instruction, so we pass 0 as the "ubit" parameter. And the
20973 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20974 neon_three_same (neon_quad (rs
), 0, 32);
20976 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20977 different NEON three-same encoding. */
20978 inst
.instruction
&= 0x00ffffff;
20979 inst
.instruction
|= high8
;
20980 /* Encode 'U' bit which indicates signedness. */
20981 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20982 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20983 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20984 the instruction encoding. */
20985 if (inst
.operands
[2].isscalar
)
20987 inst
.instruction
&= 0xffffffd0;
20988 inst
.instruction
|= LOW4 (scalar_oprd2
);
20989 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20993 /* Dot Product instructions for signed integer. */
20996 do_neon_dotproduct_s (void)
20998 return do_neon_dotproduct (0);
21001 /* Dot Product instructions for unsigned integer. */
21004 do_neon_dotproduct_u (void)
21006 return do_neon_dotproduct (1);
21009 /* Crypto v1 instructions. */
21011 do_crypto_2op_1 (unsigned elttype
, int op
)
21013 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21015 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21021 NEON_ENCODE (INTEGER
, inst
);
21022 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21023 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21024 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21025 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21027 inst
.instruction
|= op
<< 6;
21030 inst
.instruction
|= 0xfc000000;
21032 inst
.instruction
|= 0xf0000000;
21036 do_crypto_3op_1 (int u
, int op
)
21038 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21040 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21041 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21046 NEON_ENCODE (INTEGER
, inst
);
21047 neon_three_same (1, u
, 8 << op
);
21053 do_crypto_2op_1 (N_8
, 0);
21059 do_crypto_2op_1 (N_8
, 1);
21065 do_crypto_2op_1 (N_8
, 2);
21071 do_crypto_2op_1 (N_8
, 3);
21077 do_crypto_3op_1 (0, 0);
21083 do_crypto_3op_1 (0, 1);
21089 do_crypto_3op_1 (0, 2);
21095 do_crypto_3op_1 (0, 3);
21101 do_crypto_3op_1 (1, 0);
21107 do_crypto_3op_1 (1, 1);
21111 do_sha256su1 (void)
21113 do_crypto_3op_1 (1, 2);
21119 do_crypto_2op_1 (N_32
, -1);
21125 do_crypto_2op_1 (N_32
, 0);
21129 do_sha256su0 (void)
21131 do_crypto_2op_1 (N_32
, 1);
21135 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21137 unsigned int Rd
= inst
.operands
[0].reg
;
21138 unsigned int Rn
= inst
.operands
[1].reg
;
21139 unsigned int Rm
= inst
.operands
[2].reg
;
21141 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21142 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21143 inst
.instruction
|= LOW4 (Rn
) << 16;
21144 inst
.instruction
|= LOW4 (Rm
);
21145 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21146 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21148 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21149 as_warn (UNPRED_REG ("r15"));
21191 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21193 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21194 do_vfp_sp_dp_cvt ();
21195 do_vfp_cond_or_thumb ();
21199 /* Overall per-instruction processing. */
21201 /* We need to be able to fix up arbitrary expressions in some statements.
21202 This is so that we can handle symbols that are an arbitrary distance from
21203 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21204 which returns part of an address in a form which will be valid for
21205 a data instruction. We do this by pushing the expression into a symbol
21206 in the expr_section, and creating a fix for that. */
21209 fix_new_arm (fragS
* frag
,
21223 /* Create an absolute valued symbol, so we have something to
21224 refer to in the object file. Unfortunately for us, gas's
21225 generic expression parsing will already have folded out
21226 any use of .set foo/.type foo %function that may have
21227 been used to set type information of the target location,
21228 that's being specified symbolically. We have to presume
21229 the user knows what they are doing. */
21233 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21235 symbol
= symbol_find_or_make (name
);
21236 S_SET_SEGMENT (symbol
, absolute_section
);
21237 symbol_set_frag (symbol
, &zero_address_frag
);
21238 S_SET_VALUE (symbol
, exp
->X_add_number
);
21239 exp
->X_op
= O_symbol
;
21240 exp
->X_add_symbol
= symbol
;
21241 exp
->X_add_number
= 0;
21247 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21248 (enum bfd_reloc_code_real
) reloc
);
21252 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21253 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21257 /* Mark whether the fix is to a THUMB instruction, or an ARM
21259 new_fix
->tc_fix_data
= thumb_mode
;
21262 /* Create a frg for an instruction requiring relaxation. */
21264 output_relax_insn (void)
21270 /* The size of the instruction is unknown, so tie the debug info to the
21271 start of the instruction. */
21272 dwarf2_emit_insn (0);
21274 switch (inst
.relocs
[0].exp
.X_op
)
21277 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21278 offset
= inst
.relocs
[0].exp
.X_add_number
;
21282 offset
= inst
.relocs
[0].exp
.X_add_number
;
21285 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21289 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21290 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21291 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21294 /* Write a 32-bit thumb instruction to buf. */
21296 put_thumb32_insn (char * buf
, unsigned long insn
)
21298 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21299 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21303 output_inst (const char * str
)
21309 as_bad ("%s -- `%s'", inst
.error
, str
);
21314 output_relax_insn ();
21317 if (inst
.size
== 0)
21320 to
= frag_more (inst
.size
);
21321 /* PR 9814: Record the thumb mode into the current frag so that we know
21322 what type of NOP padding to use, if necessary. We override any previous
21323 setting so that if the mode has changed then the NOPS that we use will
21324 match the encoding of the last instruction in the frag. */
21325 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21327 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21329 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21330 put_thumb32_insn (to
, inst
.instruction
);
21332 else if (inst
.size
> INSN_SIZE
)
21334 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21335 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21336 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21339 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21342 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21344 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21345 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21346 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21347 inst
.relocs
[r
].type
);
21350 dwarf2_emit_insn (inst
.size
);
21354 output_it_inst (int cond
, int mask
, char * to
)
21356 unsigned long instruction
= 0xbf00;
21359 instruction
|= mask
;
21360 instruction
|= cond
<< 4;
21364 to
= frag_more (2);
21366 dwarf2_emit_insn (2);
21370 md_number_to_chars (to
, instruction
, 2);
21375 /* Tag values used in struct asm_opcode's tag field. */
21378 OT_unconditional
, /* Instruction cannot be conditionalized.
21379 The ARM condition field is still 0xE. */
21380 OT_unconditionalF
, /* Instruction cannot be conditionalized
21381 and carries 0xF in its ARM condition field. */
21382 OT_csuffix
, /* Instruction takes a conditional suffix. */
21383 OT_csuffixF
, /* Some forms of the instruction take a scalar
21384 conditional suffix, others place 0xF where the
21385 condition field would be, others take a vector
21386 conditional suffix. */
21387 OT_cinfix3
, /* Instruction takes a conditional infix,
21388 beginning at character index 3. (In
21389 unified mode, it becomes a suffix.) */
21390 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21391 tsts, cmps, cmns, and teqs. */
21392 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21393 character index 3, even in unified mode. Used for
21394 legacy instructions where suffix and infix forms
21395 may be ambiguous. */
21396 OT_csuf_or_in3
, /* Instruction takes either a conditional
21397 suffix or an infix at character index 3. */
21398 OT_odd_infix_unc
, /* This is the unconditional variant of an
21399 instruction that takes a conditional infix
21400 at an unusual position. In unified mode,
21401 this variant will accept a suffix. */
21402 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21403 are the conditional variants of instructions that
21404 take conditional infixes in unusual positions.
21405 The infix appears at character index
21406 (tag - OT_odd_infix_0). These are not accepted
21407 in unified mode. */
21410 /* Subroutine of md_assemble, responsible for looking up the primary
21411 opcode from the mnemonic the user wrote. STR points to the
21412 beginning of the mnemonic.
21414 This is not simply a hash table lookup, because of conditional
21415 variants. Most instructions have conditional variants, which are
21416 expressed with a _conditional affix_ to the mnemonic. If we were
21417 to encode each conditional variant as a literal string in the opcode
21418 table, it would have approximately 20,000 entries.
21420 Most mnemonics take this affix as a suffix, and in unified syntax,
21421 'most' is upgraded to 'all'. However, in the divided syntax, some
21422 instructions take the affix as an infix, notably the s-variants of
21423 the arithmetic instructions. Of those instructions, all but six
21424 have the infix appear after the third character of the mnemonic.
21426 Accordingly, the algorithm for looking up primary opcodes given
21429 1. Look up the identifier in the opcode table.
21430 If we find a match, go to step U.
21432 2. Look up the last two characters of the identifier in the
21433 conditions table. If we find a match, look up the first N-2
21434 characters of the identifier in the opcode table. If we
21435 find a match, go to step CE.
21437 3. Look up the fourth and fifth characters of the identifier in
21438 the conditions table. If we find a match, extract those
21439 characters from the identifier, and look up the remaining
21440 characters in the opcode table. If we find a match, go
21445 U. Examine the tag field of the opcode structure, in case this is
21446 one of the six instructions with its conditional infix in an
21447 unusual place. If it is, the tag tells us where to find the
21448 infix; look it up in the conditions table and set inst.cond
21449 accordingly. Otherwise, this is an unconditional instruction.
21450 Again set inst.cond accordingly. Return the opcode structure.
21452 CE. Examine the tag field to make sure this is an instruction that
21453 should receive a conditional suffix. If it is not, fail.
21454 Otherwise, set inst.cond from the suffix we already looked up,
21455 and return the opcode structure.
21457 CM. Examine the tag field to make sure this is an instruction that
21458 should receive a conditional infix after the third character.
21459 If it is not, fail. Otherwise, undo the edits to the current
21460 line of input and proceed as for case CE. */
21462 static const struct asm_opcode
*
21463 opcode_lookup (char **str
)
21467 const struct asm_opcode
*opcode
;
21468 const struct asm_cond
*cond
;
21471 /* Scan up to the end of the mnemonic, which must end in white space,
21472 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21473 for (base
= end
= *str
; *end
!= '\0'; end
++)
21474 if (*end
== ' ' || *end
== '.')
21480 /* Handle a possible width suffix and/or Neon type suffix. */
21485 /* The .w and .n suffixes are only valid if the unified syntax is in
21487 if (unified_syntax
&& end
[1] == 'w')
21489 else if (unified_syntax
&& end
[1] == 'n')
21494 inst
.vectype
.elems
= 0;
21496 *str
= end
+ offset
;
21498 if (end
[offset
] == '.')
21500 /* See if we have a Neon type suffix (possible in either unified or
21501 non-unified ARM syntax mode). */
21502 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21505 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21511 /* Look for unaffixed or special-case affixed mnemonic. */
21512 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21517 if (opcode
->tag
< OT_odd_infix_0
)
21519 inst
.cond
= COND_ALWAYS
;
21523 if (warn_on_deprecated
&& unified_syntax
)
21524 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21525 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21526 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21529 inst
.cond
= cond
->value
;
21532 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21534 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21536 if (end
- base
< 2)
21539 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21540 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21542 /* If this opcode can not be vector predicated then don't accept it with a
21543 vector predication code. */
21544 if (opcode
&& !opcode
->mayBeVecPred
)
21547 if (!opcode
|| !cond
)
21549 /* Cannot have a conditional suffix on a mnemonic of less than two
21551 if (end
- base
< 3)
21554 /* Look for suffixed mnemonic. */
21556 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21557 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21561 if (opcode
&& cond
)
21564 switch (opcode
->tag
)
21566 case OT_cinfix3_legacy
:
21567 /* Ignore conditional suffixes matched on infix only mnemonics. */
21571 case OT_cinfix3_deprecated
:
21572 case OT_odd_infix_unc
:
21573 if (!unified_syntax
)
21575 /* Fall through. */
21579 case OT_csuf_or_in3
:
21580 inst
.cond
= cond
->value
;
21583 case OT_unconditional
:
21584 case OT_unconditionalF
:
21586 inst
.cond
= cond
->value
;
21589 /* Delayed diagnostic. */
21590 inst
.error
= BAD_COND
;
21591 inst
.cond
= COND_ALWAYS
;
21600 /* Cannot have a usual-position infix on a mnemonic of less than
21601 six characters (five would be a suffix). */
21602 if (end
- base
< 6)
21605 /* Look for infixed mnemonic in the usual position. */
21607 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21611 memcpy (save
, affix
, 2);
21612 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21613 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21615 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21616 memcpy (affix
, save
, 2);
21619 && (opcode
->tag
== OT_cinfix3
21620 || opcode
->tag
== OT_cinfix3_deprecated
21621 || opcode
->tag
== OT_csuf_or_in3
21622 || opcode
->tag
== OT_cinfix3_legacy
))
21625 if (warn_on_deprecated
&& unified_syntax
21626 && (opcode
->tag
== OT_cinfix3
21627 || opcode
->tag
== OT_cinfix3_deprecated
))
21628 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21630 inst
.cond
= cond
->value
;
21637 /* This function generates an initial IT instruction, leaving its block
21638 virtually open for the new instructions. Eventually,
21639 the mask will be updated by now_pred_add_mask () each time
21640 a new instruction needs to be included in the IT block.
21641 Finally, the block is closed with close_automatic_it_block ().
21642 The block closure can be requested either from md_assemble (),
21643 a tencode (), or due to a label hook. */
21646 new_automatic_it_block (int cond
)
21648 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21649 now_pred
.mask
= 0x18;
21650 now_pred
.cc
= cond
;
21651 now_pred
.block_length
= 1;
21652 mapping_state (MAP_THUMB
);
21653 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21654 now_pred
.warn_deprecated
= FALSE
;
21655 now_pred
.insn_cond
= TRUE
;
21658 /* Close an automatic IT block.
21659 See comments in new_automatic_it_block (). */
21662 close_automatic_it_block (void)
21664 now_pred
.mask
= 0x10;
21665 now_pred
.block_length
= 0;
21668 /* Update the mask of the current automatically-generated IT
21669 instruction. See comments in new_automatic_it_block (). */
21672 now_pred_add_mask (int cond
)
21674 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21675 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21676 | ((bitvalue) << (nbit)))
21677 const int resulting_bit
= (cond
& 1);
21679 now_pred
.mask
&= 0xf;
21680 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21682 (5 - now_pred
.block_length
));
21683 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21685 ((5 - now_pred
.block_length
) - 1));
21686 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21689 #undef SET_BIT_VALUE
21692 /* The IT blocks handling machinery is accessed through the these functions:
21693 it_fsm_pre_encode () from md_assemble ()
21694 set_pred_insn_type () optional, from the tencode functions
21695 set_pred_insn_type_last () ditto
21696 in_pred_block () ditto
21697 it_fsm_post_encode () from md_assemble ()
21698 force_automatic_it_block_close () from label handling functions
21701 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21702 initializing the IT insn type with a generic initial value depending
21703 on the inst.condition.
21704 2) During the tencode function, two things may happen:
21705 a) The tencode function overrides the IT insn type by
21706 calling either set_pred_insn_type (type) or
21707 set_pred_insn_type_last ().
21708 b) The tencode function queries the IT block state by
21709 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21711 Both set_pred_insn_type and in_pred_block run the internal FSM state
21712 handling function (handle_pred_state), because: a) setting the IT insn
21713 type may incur in an invalid state (exiting the function),
21714 and b) querying the state requires the FSM to be updated.
21715 Specifically we want to avoid creating an IT block for conditional
21716 branches, so it_fsm_pre_encode is actually a guess and we can't
21717 determine whether an IT block is required until the tencode () routine
21718 has decided what type of instruction this actually it.
21719 Because of this, if set_pred_insn_type and in_pred_block have to be
21720 used, set_pred_insn_type has to be called first.
21722 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21723 that determines the insn IT type depending on the inst.cond code.
21724 When a tencode () routine encodes an instruction that can be
21725 either outside an IT block, or, in the case of being inside, has to be
21726 the last one, set_pred_insn_type_last () will determine the proper
21727 IT instruction type based on the inst.cond code. Otherwise,
21728 set_pred_insn_type can be called for overriding that logic or
21729 for covering other cases.
21731 Calling handle_pred_state () may not transition the IT block state to
21732 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21733 still queried. Instead, if the FSM determines that the state should
21734 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21735 after the tencode () function: that's what it_fsm_post_encode () does.
21737 Since in_pred_block () calls the state handling function to get an
21738 updated state, an error may occur (due to invalid insns combination).
21739 In that case, inst.error is set.
21740 Therefore, inst.error has to be checked after the execution of
21741 the tencode () routine.
21743 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21744 any pending state change (if any) that didn't take place in
21745 handle_pred_state () as explained above. */
21748 it_fsm_pre_encode (void)
21750 if (inst
.cond
!= COND_ALWAYS
)
21751 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21753 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21755 now_pred
.state_handled
= 0;
21758 /* IT state FSM handling function. */
21759 /* MVE instructions and non-MVE instructions are handled differently because of
21760 the introduction of VPT blocks.
21761 Specifications say that any non-MVE instruction inside a VPT block is
21762 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21763 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21764 few exceptions we have MVE_UNPREDICABLE_INSN.
21765 The error messages provided depending on the different combinations possible
21766 are described in the cases below:
21767 For 'most' MVE instructions:
21768 1) In an IT block, with an IT code: syntax error
21769 2) In an IT block, with a VPT code: error: must be in a VPT block
21770 3) In an IT block, with no code: warning: UNPREDICTABLE
21771 4) In a VPT block, with an IT code: syntax error
21772 5) In a VPT block, with a VPT code: OK!
21773 6) In a VPT block, with no code: error: missing code
21774 7) Outside a pred block, with an IT code: error: syntax error
21775 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21776 9) Outside a pred block, with no code: OK!
21777 For non-MVE instructions:
21778 10) In an IT block, with an IT code: OK!
21779 11) In an IT block, with a VPT code: syntax error
21780 12) In an IT block, with no code: error: missing code
21781 13) In a VPT block, with an IT code: error: should be in an IT block
21782 14) In a VPT block, with a VPT code: syntax error
21783 15) In a VPT block, with no code: UNPREDICTABLE
21784 16) Outside a pred block, with an IT code: error: should be in an IT block
21785 17) Outside a pred block, with a VPT code: syntax error
21786 18) Outside a pred block, with no code: OK!
21791 handle_pred_state (void)
21793 now_pred
.state_handled
= 1;
21794 now_pred
.insn_cond
= FALSE
;
21796 switch (now_pred
.state
)
21798 case OUTSIDE_PRED_BLOCK
:
21799 switch (inst
.pred_insn_type
)
21801 case MVE_UNPREDICABLE_INSN
:
21802 case MVE_OUTSIDE_PRED_INSN
:
21803 if (inst
.cond
< COND_ALWAYS
)
21805 /* Case 7: Outside a pred block, with an IT code: error: syntax
21807 inst
.error
= BAD_SYNTAX
;
21810 /* Case 9: Outside a pred block, with no code: OK! */
21812 case OUTSIDE_PRED_INSN
:
21813 if (inst
.cond
> COND_ALWAYS
)
21815 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21817 inst
.error
= BAD_SYNTAX
;
21820 /* Case 18: Outside a pred block, with no code: OK! */
21823 case INSIDE_VPT_INSN
:
21824 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21826 inst
.error
= BAD_OUT_VPT
;
21829 case INSIDE_IT_INSN
:
21830 case INSIDE_IT_LAST_INSN
:
21831 if (inst
.cond
< COND_ALWAYS
)
21833 /* Case 16: Outside a pred block, with an IT code: error: should
21834 be in an IT block. */
21835 if (thumb_mode
== 0)
21838 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21839 as_tsktsk (_("Warning: conditional outside an IT block"\
21844 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21845 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21847 /* Automatically generate the IT instruction. */
21848 new_automatic_it_block (inst
.cond
);
21849 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21850 close_automatic_it_block ();
21854 inst
.error
= BAD_OUT_IT
;
21860 else if (inst
.cond
> COND_ALWAYS
)
21862 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21864 inst
.error
= BAD_SYNTAX
;
21869 case IF_INSIDE_IT_LAST_INSN
:
21870 case NEUTRAL_IT_INSN
:
21874 if (inst
.cond
!= COND_ALWAYS
)
21875 first_error (BAD_SYNTAX
);
21876 now_pred
.state
= MANUAL_PRED_BLOCK
;
21877 now_pred
.block_length
= 0;
21878 now_pred
.type
= VECTOR_PRED
;
21882 now_pred
.state
= MANUAL_PRED_BLOCK
;
21883 now_pred
.block_length
= 0;
21884 now_pred
.type
= SCALAR_PRED
;
21889 case AUTOMATIC_PRED_BLOCK
:
21890 /* Three things may happen now:
21891 a) We should increment current it block size;
21892 b) We should close current it block (closing insn or 4 insns);
21893 c) We should close current it block and start a new one (due
21894 to incompatible conditions or
21895 4 insns-length block reached). */
21897 switch (inst
.pred_insn_type
)
21899 case INSIDE_VPT_INSN
:
21901 case MVE_UNPREDICABLE_INSN
:
21902 case MVE_OUTSIDE_PRED_INSN
:
21904 case OUTSIDE_PRED_INSN
:
21905 /* The closure of the block shall happen immediately,
21906 so any in_pred_block () call reports the block as closed. */
21907 force_automatic_it_block_close ();
21910 case INSIDE_IT_INSN
:
21911 case INSIDE_IT_LAST_INSN
:
21912 case IF_INSIDE_IT_LAST_INSN
:
21913 now_pred
.block_length
++;
21915 if (now_pred
.block_length
> 4
21916 || !now_pred_compatible (inst
.cond
))
21918 force_automatic_it_block_close ();
21919 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21920 new_automatic_it_block (inst
.cond
);
21924 now_pred
.insn_cond
= TRUE
;
21925 now_pred_add_mask (inst
.cond
);
21928 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21929 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21930 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21931 close_automatic_it_block ();
21934 case NEUTRAL_IT_INSN
:
21935 now_pred
.block_length
++;
21936 now_pred
.insn_cond
= TRUE
;
21938 if (now_pred
.block_length
> 4)
21939 force_automatic_it_block_close ();
21941 now_pred_add_mask (now_pred
.cc
& 1);
21945 close_automatic_it_block ();
21946 now_pred
.state
= MANUAL_PRED_BLOCK
;
21951 case MANUAL_PRED_BLOCK
:
21954 if (now_pred
.type
== SCALAR_PRED
)
21956 /* Check conditional suffixes. */
21957 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21958 now_pred
.mask
<<= 1;
21959 now_pred
.mask
&= 0x1f;
21960 is_last
= (now_pred
.mask
== 0x10);
21964 now_pred
.cc
^= (now_pred
.mask
>> 4);
21965 cond
= now_pred
.cc
+ 0xf;
21966 now_pred
.mask
<<= 1;
21967 now_pred
.mask
&= 0x1f;
21968 is_last
= now_pred
.mask
== 0x10;
21970 now_pred
.insn_cond
= TRUE
;
21972 switch (inst
.pred_insn_type
)
21974 case OUTSIDE_PRED_INSN
:
21975 if (now_pred
.type
== SCALAR_PRED
)
21977 if (inst
.cond
== COND_ALWAYS
)
21979 /* Case 12: In an IT block, with no code: error: missing
21981 inst
.error
= BAD_NOT_IT
;
21984 else if (inst
.cond
> COND_ALWAYS
)
21986 /* Case 11: In an IT block, with a VPT code: syntax error.
21988 inst
.error
= BAD_SYNTAX
;
21991 else if (thumb_mode
)
21993 /* This is for some special cases where a non-MVE
21994 instruction is not allowed in an IT block, such as cbz,
21995 but are put into one with a condition code.
21996 You could argue this should be a syntax error, but we
21997 gave the 'not allowed in IT block' diagnostic in the
21998 past so we will keep doing so. */
21999 inst
.error
= BAD_NOT_IT
;
22006 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22007 as_tsktsk (MVE_NOT_VPT
);
22010 case MVE_OUTSIDE_PRED_INSN
:
22011 if (now_pred
.type
== SCALAR_PRED
)
22013 if (inst
.cond
== COND_ALWAYS
)
22015 /* Case 3: In an IT block, with no code: warning:
22017 as_tsktsk (MVE_NOT_IT
);
22020 else if (inst
.cond
< COND_ALWAYS
)
22022 /* Case 1: In an IT block, with an IT code: syntax error.
22024 inst
.error
= BAD_SYNTAX
;
22032 if (inst
.cond
< COND_ALWAYS
)
22034 /* Case 4: In a VPT block, with an IT code: syntax error.
22036 inst
.error
= BAD_SYNTAX
;
22039 else if (inst
.cond
== COND_ALWAYS
)
22041 /* Case 6: In a VPT block, with no code: error: missing
22043 inst
.error
= BAD_NOT_VPT
;
22051 case MVE_UNPREDICABLE_INSN
:
22052 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22054 case INSIDE_IT_INSN
:
22055 if (inst
.cond
> COND_ALWAYS
)
22057 /* Case 11: In an IT block, with a VPT code: syntax error. */
22058 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22059 inst
.error
= BAD_SYNTAX
;
22062 else if (now_pred
.type
== SCALAR_PRED
)
22064 /* Case 10: In an IT block, with an IT code: OK! */
22065 if (cond
!= inst
.cond
)
22067 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22074 /* Case 13: In a VPT block, with an IT code: error: should be
22076 inst
.error
= BAD_OUT_IT
;
22081 case INSIDE_VPT_INSN
:
22082 if (now_pred
.type
== SCALAR_PRED
)
22084 /* Case 2: In an IT block, with a VPT code: error: must be in a
22086 inst
.error
= BAD_OUT_VPT
;
22089 /* Case 5: In a VPT block, with a VPT code: OK! */
22090 else if (cond
!= inst
.cond
)
22092 inst
.error
= BAD_VPT_COND
;
22096 case INSIDE_IT_LAST_INSN
:
22097 case IF_INSIDE_IT_LAST_INSN
:
22098 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22100 /* Case 4: In a VPT block, with an IT code: syntax error. */
22101 /* Case 11: In an IT block, with a VPT code: syntax error. */
22102 inst
.error
= BAD_SYNTAX
;
22105 else if (cond
!= inst
.cond
)
22107 inst
.error
= BAD_IT_COND
;
22112 inst
.error
= BAD_BRANCH
;
22117 case NEUTRAL_IT_INSN
:
22118 /* The BKPT instruction is unconditional even in a IT or VPT
22123 if (now_pred
.type
== SCALAR_PRED
)
22125 inst
.error
= BAD_IT_IT
;
22128 /* fall through. */
22130 if (inst
.cond
== COND_ALWAYS
)
22132 /* Executing a VPT/VPST instruction inside an IT block or a
22133 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22135 if (now_pred
.type
== SCALAR_PRED
)
22136 as_tsktsk (MVE_NOT_IT
);
22138 as_tsktsk (MVE_NOT_VPT
);
22143 /* VPT/VPST do not accept condition codes. */
22144 inst
.error
= BAD_SYNTAX
;
22155 struct depr_insn_mask
22157 unsigned long pattern
;
22158 unsigned long mask
;
22159 const char* description
;
22162 /* List of 16-bit instruction patterns deprecated in an IT block in
22164 static const struct depr_insn_mask depr_it_insns
[] = {
22165 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22166 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22167 { 0xa000, 0xb800, N_("ADR") },
22168 { 0x4800, 0xf800, N_("Literal loads") },
22169 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22170 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22171 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22172 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22173 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22178 it_fsm_post_encode (void)
22182 if (!now_pred
.state_handled
)
22183 handle_pred_state ();
22185 if (now_pred
.insn_cond
22186 && !now_pred
.warn_deprecated
22187 && warn_on_deprecated
22188 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22189 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22191 if (inst
.instruction
>= 0x10000)
22193 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22194 "performance deprecated in ARMv8-A and ARMv8-R"));
22195 now_pred
.warn_deprecated
= TRUE
;
22199 const struct depr_insn_mask
*p
= depr_it_insns
;
22201 while (p
->mask
!= 0)
22203 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22205 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22206 "instructions of the following class are "
22207 "performance deprecated in ARMv8-A and "
22208 "ARMv8-R: %s"), p
->description
);
22209 now_pred
.warn_deprecated
= TRUE
;
22217 if (now_pred
.block_length
> 1)
22219 as_tsktsk (_("IT blocks containing more than one conditional "
22220 "instruction are performance deprecated in ARMv8-A and "
22222 now_pred
.warn_deprecated
= TRUE
;
22226 is_last
= (now_pred
.mask
== 0x10);
22229 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22235 force_automatic_it_block_close (void)
22237 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22239 close_automatic_it_block ();
22240 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22246 in_pred_block (void)
22248 if (!now_pred
.state_handled
)
22249 handle_pred_state ();
22251 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22254 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22255 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22256 here, hence the "known" in the function name. */
22259 known_t32_only_insn (const struct asm_opcode
*opcode
)
22261 /* Original Thumb-1 wide instruction. */
22262 if (opcode
->tencode
== do_t_blx
22263 || opcode
->tencode
== do_t_branch23
22264 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22265 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22268 /* Wide-only instruction added to ARMv8-M Baseline. */
22269 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22270 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22271 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22272 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22278 /* Whether wide instruction variant can be used if available for a valid OPCODE
22282 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22284 if (known_t32_only_insn (opcode
))
22287 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22288 of variant T3 of B.W is checked in do_t_branch. */
22289 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22290 && opcode
->tencode
== do_t_branch
)
22293 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22294 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22295 && opcode
->tencode
== do_t_mov_cmp
22296 /* Make sure CMP instruction is not affected. */
22297 && opcode
->aencode
== do_mov
)
22300 /* Wide instruction variants of all instructions with narrow *and* wide
22301 variants become available with ARMv6t2. Other opcodes are either
22302 narrow-only or wide-only and are thus available if OPCODE is valid. */
22303 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22306 /* OPCODE with narrow only instruction variant or wide variant not
22312 md_assemble (char *str
)
22315 const struct asm_opcode
* opcode
;
22317 /* Align the previous label if needed. */
22318 if (last_label_seen
!= NULL
)
22320 symbol_set_frag (last_label_seen
, frag_now
);
22321 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22322 S_SET_SEGMENT (last_label_seen
, now_seg
);
22325 memset (&inst
, '\0', sizeof (inst
));
22327 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22328 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22330 opcode
= opcode_lookup (&p
);
22333 /* It wasn't an instruction, but it might be a register alias of
22334 the form alias .req reg, or a Neon .dn/.qn directive. */
22335 if (! create_register_alias (str
, p
)
22336 && ! create_neon_reg_alias (str
, p
))
22337 as_bad (_("bad instruction `%s'"), str
);
22342 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22343 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22345 /* The value which unconditional instructions should have in place of the
22346 condition field. */
22347 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22351 arm_feature_set variant
;
22353 variant
= cpu_variant
;
22354 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22355 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22356 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22357 /* Check that this instruction is supported for this CPU. */
22358 if (!opcode
->tvariant
22359 || (thumb_mode
== 1
22360 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22362 if (opcode
->tencode
== do_t_swi
)
22363 as_bad (_("SVC is not permitted on this architecture"));
22365 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22368 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22369 && opcode
->tencode
!= do_t_branch
)
22371 as_bad (_("Thumb does not support conditional execution"));
22375 /* Two things are addressed here:
22376 1) Implicit require narrow instructions on Thumb-1.
22377 This avoids relaxation accidentally introducing Thumb-2
22379 2) Reject wide instructions in non Thumb-2 cores.
22381 Only instructions with narrow and wide variants need to be handled
22382 but selecting all non wide-only instructions is easier. */
22383 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22384 && !t32_insn_ok (variant
, opcode
))
22386 if (inst
.size_req
== 0)
22388 else if (inst
.size_req
== 4)
22390 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22391 as_bad (_("selected processor does not support 32bit wide "
22392 "variant of instruction `%s'"), str
);
22394 as_bad (_("selected processor does not support `%s' in "
22395 "Thumb-2 mode"), str
);
22400 inst
.instruction
= opcode
->tvalue
;
22402 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22404 /* Prepare the pred_insn_type for those encodings that don't set
22406 it_fsm_pre_encode ();
22408 opcode
->tencode ();
22410 it_fsm_post_encode ();
22413 if (!(inst
.error
|| inst
.relax
))
22415 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22416 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22417 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22419 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22424 /* Something has gone badly wrong if we try to relax a fixed size
22426 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22428 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22429 *opcode
->tvariant
);
22430 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22431 set those bits when Thumb-2 32-bit instructions are seen. The impact
22432 of relaxable instructions will be considered later after we finish all
22434 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22435 variant
= arm_arch_none
;
22437 variant
= cpu_variant
;
22438 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22439 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22442 check_neon_suffixes
;
22446 mapping_state (MAP_THUMB
);
22449 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22453 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22454 is_bx
= (opcode
->aencode
== do_bx
);
22456 /* Check that this instruction is supported for this CPU. */
22457 if (!(is_bx
&& fix_v4bx
)
22458 && !(opcode
->avariant
&&
22459 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22461 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22466 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22470 inst
.instruction
= opcode
->avalue
;
22471 if (opcode
->tag
== OT_unconditionalF
)
22472 inst
.instruction
|= 0xFU
<< 28;
22474 inst
.instruction
|= inst
.cond
<< 28;
22475 inst
.size
= INSN_SIZE
;
22476 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22478 it_fsm_pre_encode ();
22479 opcode
->aencode ();
22480 it_fsm_post_encode ();
22482 /* Arm mode bx is marked as both v4T and v5 because it's still required
22483 on a hypothetical non-thumb v5 core. */
22485 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22487 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22488 *opcode
->avariant
);
22490 check_neon_suffixes
;
22494 mapping_state (MAP_ARM
);
22499 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22507 check_pred_blocks_finished (void)
22512 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22513 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22514 == MANUAL_PRED_BLOCK
)
22516 if (now_pred
.type
== SCALAR_PRED
)
22517 as_warn (_("section '%s' finished with an open IT block."),
22520 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22524 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22526 if (now_pred
.type
== SCALAR_PRED
)
22527 as_warn (_("file finished with an open IT block."));
22529 as_warn (_("file finished with an open VPT/VPST block."));
22534 /* Various frobbings of labels and their addresses. */
22537 arm_start_line_hook (void)
22539 last_label_seen
= NULL
;
22543 arm_frob_label (symbolS
* sym
)
22545 last_label_seen
= sym
;
22547 ARM_SET_THUMB (sym
, thumb_mode
);
22549 #if defined OBJ_COFF || defined OBJ_ELF
22550 ARM_SET_INTERWORK (sym
, support_interwork
);
22553 force_automatic_it_block_close ();
22555 /* Note - do not allow local symbols (.Lxxx) to be labelled
22556 as Thumb functions. This is because these labels, whilst
22557 they exist inside Thumb code, are not the entry points for
22558 possible ARM->Thumb calls. Also, these labels can be used
22559 as part of a computed goto or switch statement. eg gcc
22560 can generate code that looks like this:
22562 ldr r2, [pc, .Laaa]
22572 The first instruction loads the address of the jump table.
22573 The second instruction converts a table index into a byte offset.
22574 The third instruction gets the jump address out of the table.
22575 The fourth instruction performs the jump.
22577 If the address stored at .Laaa is that of a symbol which has the
22578 Thumb_Func bit set, then the linker will arrange for this address
22579 to have the bottom bit set, which in turn would mean that the
22580 address computation performed by the third instruction would end
22581 up with the bottom bit set. Since the ARM is capable of unaligned
22582 word loads, the instruction would then load the incorrect address
22583 out of the jump table, and chaos would ensue. */
22584 if (label_is_thumb_function_name
22585 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22586 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22588 /* When the address of a Thumb function is taken the bottom
22589 bit of that address should be set. This will allow
22590 interworking between Arm and Thumb functions to work
22593 THUMB_SET_FUNC (sym
, 1);
22595 label_is_thumb_function_name
= FALSE
;
22598 dwarf2_emit_label (sym
);
22602 arm_data_in_code (void)
22604 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22606 *input_line_pointer
= '/';
22607 input_line_pointer
+= 5;
22608 *input_line_pointer
= 0;
22616 arm_canonicalize_symbol_name (char * name
)
22620 if (thumb_mode
&& (len
= strlen (name
)) > 5
22621 && streq (name
+ len
- 5, "/data"))
22622 *(name
+ len
- 5) = 0;
22627 /* Table of all register names defined by default. The user can
22628 define additional names with .req. Note that all register names
22629 should appear in both upper and lowercase variants. Some registers
22630 also have mixed-case names. */
22632 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22633 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22634 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22635 #define REGSET(p,t) \
22636 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22637 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22638 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22639 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22640 #define REGSETH(p,t) \
22641 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22642 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22643 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22644 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22645 #define REGSET2(p,t) \
22646 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22647 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22648 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22649 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22650 #define SPLRBANK(base,bank,t) \
22651 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22652 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22653 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22654 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22655 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22656 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22658 static const struct reg_entry reg_names
[] =
22660 /* ARM integer registers. */
22661 REGSET(r
, RN
), REGSET(R
, RN
),
22663 /* ATPCS synonyms. */
22664 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22665 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22666 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22668 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22669 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22670 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22672 /* Well-known aliases. */
22673 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22674 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22676 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22677 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22679 /* Defining the new Zero register from ARMv8.1-M. */
22683 /* Coprocessor numbers. */
22684 REGSET(p
, CP
), REGSET(P
, CP
),
22686 /* Coprocessor register numbers. The "cr" variants are for backward
22688 REGSET(c
, CN
), REGSET(C
, CN
),
22689 REGSET(cr
, CN
), REGSET(CR
, CN
),
22691 /* ARM banked registers. */
22692 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22693 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22694 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22695 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22696 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22697 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22698 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22700 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22701 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22702 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22703 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22704 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22705 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22706 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22707 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22709 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22710 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22711 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22712 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22713 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22714 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22715 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22716 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22717 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22719 /* FPA registers. */
22720 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22721 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22723 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22724 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22726 /* VFP SP registers. */
22727 REGSET(s
,VFS
), REGSET(S
,VFS
),
22728 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22730 /* VFP DP Registers. */
22731 REGSET(d
,VFD
), REGSET(D
,VFD
),
22732 /* Extra Neon DP registers. */
22733 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22735 /* Neon QP registers. */
22736 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22738 /* VFP control registers. */
22739 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22740 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22741 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22742 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22743 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22744 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22745 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22747 /* Maverick DSP coprocessor registers. */
22748 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22749 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22751 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22752 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22753 REGDEF(dspsc
,0,DSPSC
),
22755 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22756 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22757 REGDEF(DSPSC
,0,DSPSC
),
22759 /* iWMMXt data registers - p0, c0-15. */
22760 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22762 /* iWMMXt control registers - p1, c0-3. */
22763 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22764 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22765 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22766 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22768 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22769 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22770 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22771 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22772 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22774 /* XScale accumulator registers. */
22775 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22781 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22782 within psr_required_here. */
22783 static const struct asm_psr psrs
[] =
22785 /* Backward compatibility notation. Note that "all" is no longer
22786 truly all possible PSR bits. */
22787 {"all", PSR_c
| PSR_f
},
22791 /* Individual flags. */
22797 /* Combinations of flags. */
22798 {"fs", PSR_f
| PSR_s
},
22799 {"fx", PSR_f
| PSR_x
},
22800 {"fc", PSR_f
| PSR_c
},
22801 {"sf", PSR_s
| PSR_f
},
22802 {"sx", PSR_s
| PSR_x
},
22803 {"sc", PSR_s
| PSR_c
},
22804 {"xf", PSR_x
| PSR_f
},
22805 {"xs", PSR_x
| PSR_s
},
22806 {"xc", PSR_x
| PSR_c
},
22807 {"cf", PSR_c
| PSR_f
},
22808 {"cs", PSR_c
| PSR_s
},
22809 {"cx", PSR_c
| PSR_x
},
22810 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22811 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22812 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22813 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22814 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22815 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22816 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22817 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22818 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22819 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22820 {"scf", PSR_s
| PSR_c
| PSR_f
},
22821 {"scx", PSR_s
| PSR_c
| PSR_x
},
22822 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22823 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22824 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22825 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22826 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22827 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22828 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22829 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22830 {"csf", PSR_c
| PSR_s
| PSR_f
},
22831 {"csx", PSR_c
| PSR_s
| PSR_x
},
22832 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22833 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22834 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22835 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22836 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22837 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22838 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22839 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22840 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22841 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22842 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22843 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22844 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22845 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22846 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22847 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22848 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22849 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22850 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22851 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22852 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22853 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22854 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22855 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22856 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22857 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22860 /* Table of V7M psr names. */
22861 static const struct asm_psr v7m_psrs
[] =
22863 {"apsr", 0x0 }, {"APSR", 0x0 },
22864 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22865 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22866 {"psr", 0x3 }, {"PSR", 0x3 },
22867 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22868 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22869 {"epsr", 0x6 }, {"EPSR", 0x6 },
22870 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22871 {"msp", 0x8 }, {"MSP", 0x8 },
22872 {"psp", 0x9 }, {"PSP", 0x9 },
22873 {"msplim", 0xa }, {"MSPLIM", 0xa },
22874 {"psplim", 0xb }, {"PSPLIM", 0xb },
22875 {"primask", 0x10}, {"PRIMASK", 0x10},
22876 {"basepri", 0x11}, {"BASEPRI", 0x11},
22877 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22878 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22879 {"control", 0x14}, {"CONTROL", 0x14},
22880 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22881 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22882 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22883 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22884 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22885 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22886 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22887 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22888 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22891 /* Table of all shift-in-operand names. */
22892 static const struct asm_shift_name shift_names
[] =
22894 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22895 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22896 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22897 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22898 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22899 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22900 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22903 /* Table of all explicit relocation names. */
22905 static struct reloc_entry reloc_names
[] =
22907 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22908 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22909 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22910 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22911 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22912 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22913 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22914 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22915 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22916 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22917 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22918 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22919 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22920 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22921 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22922 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22923 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22924 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22925 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22926 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22927 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22928 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22929 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22930 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22931 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22932 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22933 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22937 /* Table of all conditional affixes. */
22938 static const struct asm_cond conds
[] =
22942 {"cs", 0x2}, {"hs", 0x2},
22943 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22956 static const struct asm_cond vconds
[] =
22962 #define UL_BARRIER(L,U,CODE,FEAT) \
22963 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22964 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22966 static struct asm_barrier_opt barrier_opt_names
[] =
22968 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22969 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22970 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22971 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22972 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22973 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22974 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22975 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22976 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22977 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22978 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22979 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22980 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22981 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22982 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22983 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22988 /* Table of ARM-format instructions. */
22990 /* Macros for gluing together operand strings. N.B. In all cases
22991 other than OPS0, the trailing OP_stop comes from default
22992 zero-initialization of the unspecified elements of the array. */
22993 #define OPS0() { OP_stop, }
22994 #define OPS1(a) { OP_##a, }
22995 #define OPS2(a,b) { OP_##a,OP_##b, }
22996 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22997 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22998 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22999 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23001 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23002 This is useful when mixing operands for ARM and THUMB, i.e. using the
23003 MIX_ARM_THUMB_OPERANDS macro.
23004 In order to use these macros, prefix the number of operands with _
23006 #define OPS_1(a) { a, }
23007 #define OPS_2(a,b) { a,b, }
23008 #define OPS_3(a,b,c) { a,b,c, }
23009 #define OPS_4(a,b,c,d) { a,b,c,d, }
23010 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23011 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23013 /* These macros abstract out the exact format of the mnemonic table and
23014 save some repeated characters. */
23016 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23017 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23018 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23019 THUMB_VARIANT, do_##ae, do_##te, 0 }
23021 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23022 a T_MNEM_xyz enumerator. */
23023 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23024 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23025 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23026 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23028 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23029 infix after the third character. */
23030 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23031 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23032 THUMB_VARIANT, do_##ae, do_##te, 0 }
23033 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23034 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23035 THUMB_VARIANT, do_##ae, do_##te, 0 }
23036 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23037 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23038 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23039 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23040 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23041 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23042 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23043 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23045 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23046 field is still 0xE. Many of the Thumb variants can be executed
23047 conditionally, so this is checked separately. */
23048 #define TUE(mnem, op, top, nops, ops, ae, te) \
23049 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23050 THUMB_VARIANT, do_##ae, do_##te, 0 }
23052 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23053 Used by mnemonics that have very minimal differences in the encoding for
23054 ARM and Thumb variants and can be handled in a common function. */
23055 #define TUEc(mnem, op, top, nops, ops, en) \
23056 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23057 THUMB_VARIANT, do_##en, do_##en, 0 }
23059 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23060 condition code field. */
23061 #define TUF(mnem, op, top, nops, ops, ae, te) \
23062 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23063 THUMB_VARIANT, do_##ae, do_##te, 0 }
23065 /* ARM-only variants of all the above. */
23066 #define CE(mnem, op, nops, ops, ae) \
23067 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23069 #define C3(mnem, op, nops, ops, ae) \
23070 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23072 /* Thumb-only variants of TCE and TUE. */
23073 #define ToC(mnem, top, nops, ops, te) \
23074 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23077 #define ToU(mnem, top, nops, ops, te) \
23078 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23081 /* T_MNEM_xyz enumerator variants of ToC. */
23082 #define toC(mnem, top, nops, ops, te) \
23083 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23086 /* T_MNEM_xyz enumerator variants of ToU. */
23087 #define toU(mnem, top, nops, ops, te) \
23088 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23091 /* Legacy mnemonics that always have conditional infix after the third
23093 #define CL(mnem, op, nops, ops, ae) \
23094 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23095 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23097 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23098 #define cCE(mnem, op, nops, ops, ae) \
23099 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23101 /* mov instructions that are shared between coprocessor and MVE. */
23102 #define mcCE(mnem, op, nops, ops, ae) \
23103 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23105 /* Legacy coprocessor instructions where conditional infix and conditional
23106 suffix are ambiguous. For consistency this includes all FPA instructions,
23107 not just the potentially ambiguous ones. */
23108 #define cCL(mnem, op, nops, ops, ae) \
23109 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23110 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23112 /* Coprocessor, takes either a suffix or a position-3 infix
23113 (for an FPA corner case). */
23114 #define C3E(mnem, op, nops, ops, ae) \
23115 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23116 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23118 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23119 { m1 #m2 m3, OPS##nops ops, \
23120 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23121 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23123 #define CM(m1, m2, op, nops, ops, ae) \
23124 xCM_ (m1, , m2, op, nops, ops, ae), \
23125 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23126 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23127 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23128 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23129 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23130 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23131 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23132 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23133 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23134 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23135 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23136 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23137 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23138 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23139 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23140 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23141 xCM_ (m1, le, m2, op, nops, ops, ae), \
23142 xCM_ (m1, al, m2, op, nops, ops, ae)
23144 #define UE(mnem, op, nops, ops, ae) \
23145 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23147 #define UF(mnem, op, nops, ops, ae) \
23148 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23150 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23151 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23152 use the same encoding function for each. */
23153 #define NUF(mnem, op, nops, ops, enc) \
23154 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23155 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23157 /* Neon data processing, version which indirects through neon_enc_tab for
23158 the various overloaded versions of opcodes. */
23159 #define nUF(mnem, op, nops, ops, enc) \
23160 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23161 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23163 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23165 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23166 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23167 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23169 #define NCE(mnem, op, nops, ops, enc) \
23170 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23172 #define NCEF(mnem, op, nops, ops, enc) \
23173 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23175 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23176 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23177 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23178 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23180 #define nCE(mnem, op, nops, ops, enc) \
23181 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23183 #define nCEF(mnem, op, nops, ops, enc) \
23184 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23187 #define mCEF(mnem, op, nops, ops, enc) \
23188 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23189 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23192 /* nCEF but for MVE predicated instructions. */
23193 #define mnCEF(mnem, op, nops, ops, enc) \
23194 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23196 /* nCE but for MVE predicated instructions. */
23197 #define mnCE(mnem, op, nops, ops, enc) \
23198 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23200 /* NUF but for potentially MVE predicated instructions. */
23201 #define MNUF(mnem, op, nops, ops, enc) \
23202 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23203 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23205 /* nUF but for potentially MVE predicated instructions. */
23206 #define mnUF(mnem, op, nops, ops, enc) \
23207 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23208 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23210 /* ToC but for potentially MVE predicated instructions. */
23211 #define mToC(mnem, top, nops, ops, te) \
23212 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23215 /* NCE but for MVE predicated instructions. */
23216 #define MNCE(mnem, op, nops, ops, enc) \
23217 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23219 /* NCEF but for MVE predicated instructions. */
23220 #define MNCEF(mnem, op, nops, ops, enc) \
23221 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23224 static const struct asm_opcode insns
[] =
23226 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23227 #define THUMB_VARIANT & arm_ext_v4t
23228 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23229 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23230 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23231 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23232 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23233 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23234 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23235 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23236 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23237 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23238 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23239 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23240 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23241 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23242 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23243 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23245 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23246 for setting PSR flag bits. They are obsolete in V6 and do not
23247 have Thumb equivalents. */
23248 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23249 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23250 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23251 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23252 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23253 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23254 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23255 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23256 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23258 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23259 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23260 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23261 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23263 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23264 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23265 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23267 OP_ADDRGLDR
),ldst
, t_ldst
),
23268 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23270 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23271 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23272 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23273 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23274 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23275 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23277 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23278 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23281 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23282 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23283 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23284 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23286 /* Thumb-compatibility pseudo ops. */
23287 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23288 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23289 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23290 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23291 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23292 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23293 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23294 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23295 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23296 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23297 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23298 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23300 /* These may simplify to neg. */
23301 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23302 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23304 #undef THUMB_VARIANT
23305 #define THUMB_VARIANT & arm_ext_os
23307 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23308 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23310 #undef THUMB_VARIANT
23311 #define THUMB_VARIANT & arm_ext_v6
23313 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23315 /* V1 instructions with no Thumb analogue prior to V6T2. */
23316 #undef THUMB_VARIANT
23317 #define THUMB_VARIANT & arm_ext_v6t2
23319 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23320 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23321 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23323 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23324 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23325 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23326 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23328 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23329 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23331 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23332 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23334 /* V1 instructions with no Thumb analogue at all. */
23335 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23336 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23338 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23339 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23340 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23341 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23342 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23343 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23344 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23345 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23348 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23349 #undef THUMB_VARIANT
23350 #define THUMB_VARIANT & arm_ext_v4t
23352 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23353 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23355 #undef THUMB_VARIANT
23356 #define THUMB_VARIANT & arm_ext_v6t2
23358 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23359 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23361 /* Generic coprocessor instructions. */
23362 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23363 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23364 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23365 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23366 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23367 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23368 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23371 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23373 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23374 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23377 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23378 #undef THUMB_VARIANT
23379 #define THUMB_VARIANT & arm_ext_msr
23381 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23382 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23385 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23386 #undef THUMB_VARIANT
23387 #define THUMB_VARIANT & arm_ext_v6t2
23389 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23390 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23391 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23392 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23393 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23394 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23395 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23396 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23399 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23400 #undef THUMB_VARIANT
23401 #define THUMB_VARIANT & arm_ext_v4t
23403 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23404 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23405 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23406 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23407 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23408 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23411 #define ARM_VARIANT & arm_ext_v4t_5
23413 /* ARM Architecture 4T. */
23414 /* Note: bx (and blx) are required on V5, even if the processor does
23415 not support Thumb. */
23416 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23419 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23420 #undef THUMB_VARIANT
23421 #define THUMB_VARIANT & arm_ext_v5t
23423 /* Note: blx has 2 variants; the .value coded here is for
23424 BLX(2). Only this variant has conditional execution. */
23425 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23426 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23428 #undef THUMB_VARIANT
23429 #define THUMB_VARIANT & arm_ext_v6t2
23431 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23432 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23433 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23434 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23435 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23436 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23437 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23438 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23441 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23442 #undef THUMB_VARIANT
23443 #define THUMB_VARIANT & arm_ext_v5exp
23445 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23446 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23447 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23448 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23450 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23451 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23453 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23454 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23455 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23456 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23458 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23459 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23460 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23461 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23463 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23464 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23466 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23467 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23468 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23469 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23472 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23473 #undef THUMB_VARIANT
23474 #define THUMB_VARIANT & arm_ext_v6t2
23476 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23477 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23479 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23480 ADDRGLDRS
), ldrd
, t_ldstd
),
23482 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23483 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23486 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23488 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23491 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23492 #undef THUMB_VARIANT
23493 #define THUMB_VARIANT & arm_ext_v6
23495 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23496 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23497 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23498 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23499 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23500 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23501 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23502 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23503 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23504 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23506 #undef THUMB_VARIANT
23507 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23509 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23510 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23512 #undef THUMB_VARIANT
23513 #define THUMB_VARIANT & arm_ext_v6t2
23515 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23516 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23518 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23519 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23521 /* ARM V6 not included in V7M. */
23522 #undef THUMB_VARIANT
23523 #define THUMB_VARIANT & arm_ext_v6_notm
23524 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23525 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23526 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23527 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23528 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23529 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23530 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23531 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23532 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23533 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23534 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23535 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23536 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23537 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23538 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23539 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23540 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23541 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23542 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23544 /* ARM V6 not included in V7M (eg. integer SIMD). */
23545 #undef THUMB_VARIANT
23546 #define THUMB_VARIANT & arm_ext_v6_dsp
23547 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23548 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23549 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23550 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23551 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23552 /* Old name for QASX. */
23553 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23554 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23555 /* Old name for QSAX. */
23556 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23557 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23558 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23559 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23560 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23561 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23562 /* Old name for SASX. */
23563 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23564 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23565 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23566 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23567 /* Old name for SHASX. */
23568 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23569 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23570 /* Old name for SHSAX. */
23571 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23572 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23573 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23574 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23575 /* Old name for SSAX. */
23576 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23577 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23578 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23579 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23580 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23581 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23582 /* Old name for UASX. */
23583 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23584 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23585 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23586 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23587 /* Old name for UHASX. */
23588 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23589 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23590 /* Old name for UHSAX. */
23591 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23592 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23593 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23594 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23595 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23596 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23597 /* Old name for UQASX. */
23598 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23599 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23600 /* Old name for UQSAX. */
23601 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23602 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23603 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23604 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23605 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23606 /* Old name for USAX. */
23607 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23608 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23609 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23610 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23611 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23612 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23613 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23614 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23615 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23616 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23617 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23618 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23619 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23620 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23621 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23622 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23623 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23624 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23625 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23626 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23627 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23628 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23629 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23630 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23631 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23632 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23633 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23634 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23635 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23636 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23637 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23638 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23639 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23640 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23643 #define ARM_VARIANT & arm_ext_v6k_v6t2
23644 #undef THUMB_VARIANT
23645 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23647 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23648 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23649 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23650 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23652 #undef THUMB_VARIANT
23653 #define THUMB_VARIANT & arm_ext_v6_notm
23654 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23656 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23657 RRnpcb
), strexd
, t_strexd
),
23659 #undef THUMB_VARIANT
23660 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23661 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23663 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23665 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23667 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23669 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23672 #define ARM_VARIANT & arm_ext_sec
23673 #undef THUMB_VARIANT
23674 #define THUMB_VARIANT & arm_ext_sec
23676 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23679 #define ARM_VARIANT & arm_ext_virt
23680 #undef THUMB_VARIANT
23681 #define THUMB_VARIANT & arm_ext_virt
23683 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23684 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23687 #define ARM_VARIANT & arm_ext_pan
23688 #undef THUMB_VARIANT
23689 #define THUMB_VARIANT & arm_ext_pan
23691 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23694 #define ARM_VARIANT & arm_ext_v6t2
23695 #undef THUMB_VARIANT
23696 #define THUMB_VARIANT & arm_ext_v6t2
23698 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23699 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23700 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23701 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23703 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23704 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23706 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23707 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23708 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23709 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23712 #define ARM_VARIANT & arm_ext_v3
23713 #undef THUMB_VARIANT
23714 #define THUMB_VARIANT & arm_ext_v6t2
23716 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23717 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23718 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23721 #define ARM_VARIANT & arm_ext_v6t2
23722 #undef THUMB_VARIANT
23723 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23724 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23725 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23727 /* Thumb-only instructions. */
23729 #define ARM_VARIANT NULL
23730 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23731 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23733 /* ARM does not really have an IT instruction, so always allow it.
23734 The opcode is copied from Thumb in order to allow warnings in
23735 -mimplicit-it=[never | arm] modes. */
23737 #define ARM_VARIANT & arm_ext_v1
23738 #undef THUMB_VARIANT
23739 #define THUMB_VARIANT & arm_ext_v6t2
23741 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23742 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23743 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23744 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23745 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23746 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23747 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23748 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23749 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23750 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23751 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23752 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23753 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23754 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23755 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23756 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23757 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23758 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23760 /* Thumb2 only instructions. */
23762 #define ARM_VARIANT NULL
23764 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23765 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23766 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23767 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23768 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23769 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23771 /* Hardware division instructions. */
23773 #define ARM_VARIANT & arm_ext_adiv
23774 #undef THUMB_VARIANT
23775 #define THUMB_VARIANT & arm_ext_div
23777 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23778 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23780 /* ARM V6M/V7 instructions. */
23782 #define ARM_VARIANT & arm_ext_barrier
23783 #undef THUMB_VARIANT
23784 #define THUMB_VARIANT & arm_ext_barrier
23786 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23787 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23788 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23790 /* ARM V7 instructions. */
23792 #define ARM_VARIANT & arm_ext_v7
23793 #undef THUMB_VARIANT
23794 #define THUMB_VARIANT & arm_ext_v7
23796 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23797 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23800 #define ARM_VARIANT & arm_ext_mp
23801 #undef THUMB_VARIANT
23802 #define THUMB_VARIANT & arm_ext_mp
23804 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23806 /* AArchv8 instructions. */
23808 #define ARM_VARIANT & arm_ext_v8
23810 /* Instructions shared between armv8-a and armv8-m. */
23811 #undef THUMB_VARIANT
23812 #define THUMB_VARIANT & arm_ext_atomics
23814 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23815 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23816 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23817 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23818 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23819 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23820 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23821 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23822 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23823 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23825 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23827 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23829 #undef THUMB_VARIANT
23830 #define THUMB_VARIANT & arm_ext_v8
23832 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23833 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23835 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23838 /* Defined in V8 but is in undefined encoding space for earlier
23839 architectures. However earlier architectures are required to treat
23840 this instuction as a semihosting trap as well. Hence while not explicitly
23841 defined as such, it is in fact correct to define the instruction for all
23843 #undef THUMB_VARIANT
23844 #define THUMB_VARIANT & arm_ext_v1
23846 #define ARM_VARIANT & arm_ext_v1
23847 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23849 /* ARMv8 T32 only. */
23851 #define ARM_VARIANT NULL
23852 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23853 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23854 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23856 /* FP for ARMv8. */
23858 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23859 #undef THUMB_VARIANT
23860 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23862 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23863 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23864 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23865 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23866 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23867 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23868 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23869 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23870 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23871 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23872 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23874 /* Crypto v1 extensions. */
23876 #define ARM_VARIANT & fpu_crypto_ext_armv8
23877 #undef THUMB_VARIANT
23878 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23880 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23881 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23882 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23883 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23884 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23885 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23886 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23887 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23888 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23889 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23890 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23891 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23892 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23893 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23896 #define ARM_VARIANT & crc_ext_armv8
23897 #undef THUMB_VARIANT
23898 #define THUMB_VARIANT & crc_ext_armv8
23899 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23900 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23901 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23902 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23903 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23904 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23906 /* ARMv8.2 RAS extension. */
23908 #define ARM_VARIANT & arm_ext_ras
23909 #undef THUMB_VARIANT
23910 #define THUMB_VARIANT & arm_ext_ras
23911 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23914 #define ARM_VARIANT & arm_ext_v8_3
23915 #undef THUMB_VARIANT
23916 #define THUMB_VARIANT & arm_ext_v8_3
23917 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23920 #define ARM_VARIANT & fpu_neon_ext_dotprod
23921 #undef THUMB_VARIANT
23922 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23923 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23924 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23927 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23928 #undef THUMB_VARIANT
23929 #define THUMB_VARIANT NULL
23931 cCE("wfs", e200110
, 1, (RR
), rd
),
23932 cCE("rfs", e300110
, 1, (RR
), rd
),
23933 cCE("wfc", e400110
, 1, (RR
), rd
),
23934 cCE("rfc", e500110
, 1, (RR
), rd
),
23936 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23937 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23938 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23939 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23941 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23942 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23943 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23944 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23946 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23947 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23948 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23949 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23950 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23951 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23952 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23953 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23954 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23955 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23956 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23957 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23959 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23960 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23961 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23962 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23963 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23964 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23965 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23966 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23967 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23968 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23969 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23970 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23972 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23973 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23974 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23975 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23976 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23977 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23978 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23979 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23980 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23981 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23982 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23983 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23985 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23986 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23987 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23988 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23989 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23990 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23991 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23992 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23993 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23994 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23995 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23996 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23998 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23999 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24000 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24001 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24002 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24003 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24004 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24005 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24006 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24007 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24008 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24009 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24011 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24012 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24013 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24014 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24015 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24016 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24017 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24018 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24019 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24020 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24021 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24022 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24024 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24025 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24026 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24027 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24028 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24029 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24030 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24031 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24032 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24033 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24034 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24035 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24037 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24038 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24039 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24040 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24041 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24042 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24043 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24044 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24045 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24046 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24047 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24048 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24050 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24051 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24052 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24053 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24054 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24055 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24056 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24057 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24058 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24059 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24060 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24061 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24063 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24064 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24065 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24066 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24067 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24068 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24069 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24070 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24071 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24072 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24073 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24074 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24076 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24077 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24078 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24079 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24080 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24081 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24082 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24083 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24084 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24085 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24086 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24087 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24089 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24090 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24091 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24092 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24093 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24094 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24095 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24096 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24097 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24098 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24099 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24100 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24102 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24103 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24104 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24105 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24106 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24107 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24108 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24109 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24110 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24111 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24112 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24113 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24115 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24116 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24117 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24118 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24119 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24120 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24121 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24122 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24123 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24124 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24125 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24126 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24128 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24129 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24130 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24131 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24132 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24133 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24134 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24135 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24136 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24137 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24138 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24139 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24141 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24142 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24143 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24144 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24145 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24146 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24147 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24148 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24149 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24150 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24151 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24152 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24154 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24155 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24156 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24157 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24158 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24159 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24160 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24161 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24162 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24163 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24164 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24165 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24167 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24168 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24169 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24170 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24171 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24172 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24173 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24174 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24175 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24176 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24177 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24178 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24180 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24181 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24182 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24183 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24184 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24185 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24186 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24187 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24188 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24189 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24190 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24191 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24193 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24194 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24195 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24196 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24197 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24198 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24199 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24200 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24201 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24202 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24203 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24204 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24206 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24207 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24208 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24209 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24210 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24211 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24212 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24213 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24214 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24215 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24216 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24217 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24219 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24220 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24221 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24222 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24223 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24224 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24225 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24226 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24227 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24228 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24229 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24230 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24232 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24233 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24234 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24235 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24236 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24237 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24238 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24239 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24240 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24241 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24242 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24243 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24245 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24246 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24247 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24248 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24249 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24250 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24251 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24252 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24253 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24254 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24255 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24256 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24258 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24259 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24260 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24261 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24262 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24263 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24264 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24265 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24266 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24267 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24268 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24269 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24271 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24272 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24273 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24274 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24275 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24276 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24277 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24278 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24279 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24280 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24281 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24282 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24284 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24285 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24286 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24287 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24288 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24289 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24290 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24291 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24292 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24293 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24294 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24295 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24297 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24298 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24299 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24300 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24301 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24302 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24303 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24304 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24305 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24306 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24307 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24308 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24310 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24311 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24312 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24313 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24314 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24315 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24316 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24317 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24318 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24319 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24320 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24321 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24323 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24324 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24325 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24326 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24328 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24329 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24330 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24331 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24332 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24333 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24334 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24335 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24336 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24337 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24338 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24339 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24341 /* The implementation of the FIX instruction is broken on some
24342 assemblers, in that it accepts a precision specifier as well as a
24343 rounding specifier, despite the fact that this is meaningless.
24344 To be more compatible, we accept it as well, though of course it
24345 does not set any bits. */
24346 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24347 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24348 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24349 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24350 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24351 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24352 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24353 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24354 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24355 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24356 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24357 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24358 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24360 /* Instructions that were new with the real FPA, call them V2. */
24362 #define ARM_VARIANT & fpu_fpa_ext_v2
24364 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24365 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24366 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24367 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24368 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24369 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24372 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24374 /* Moves and type conversions. */
24375 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24376 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24377 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24378 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24379 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24380 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24381 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24382 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24383 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24384 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24385 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24387 /* Memory operations. */
24388 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24389 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24390 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24391 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24392 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24393 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24394 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24395 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24396 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24397 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24398 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24399 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24400 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24401 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24402 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24403 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24404 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24405 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24407 /* Monadic operations. */
24408 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24409 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24410 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24412 /* Dyadic operations. */
24413 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24414 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24415 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24416 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24417 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24418 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24419 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24420 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24421 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24424 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24425 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24426 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24427 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24429 /* Double precision load/store are still present on single precision
24430 implementations. */
24431 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24432 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24433 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24434 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24435 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24436 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24437 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24438 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24439 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24440 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24443 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24445 /* Moves and type conversions. */
24446 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24447 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24448 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24449 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24450 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24451 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24452 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24453 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24454 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24455 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24456 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24457 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24459 /* Monadic operations. */
24460 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24461 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24462 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24464 /* Dyadic operations. */
24465 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24466 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24467 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24468 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24469 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24470 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24471 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24472 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24473 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24476 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24477 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24478 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24479 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24481 /* Instructions which may belong to either the Neon or VFP instruction sets.
24482 Individual encoder functions perform additional architecture checks. */
24484 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24485 #undef THUMB_VARIANT
24486 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24488 /* These mnemonics are unique to VFP. */
24489 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24490 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24491 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24492 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24493 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24494 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24495 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24496 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24498 /* Mnemonics shared by Neon and VFP. */
24499 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24501 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24502 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24503 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24504 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24505 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24506 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24508 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24509 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24510 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24511 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24514 /* NOTE: All VMOV encoding is special-cased! */
24515 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24517 #undef THUMB_VARIANT
24518 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24519 by different feature bits. Since we are setting the Thumb guard, we can
24520 require Thumb-1 which makes it a nop guard and set the right feature bit in
24521 do_vldr_vstr (). */
24522 #define THUMB_VARIANT & arm_ext_v4t
24523 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24524 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24527 #define ARM_VARIANT & arm_ext_fp16
24528 #undef THUMB_VARIANT
24529 #define THUMB_VARIANT & arm_ext_fp16
24530 /* New instructions added from v8.2, allowing the extraction and insertion of
24531 the upper 16 bits of a 32-bit vector register. */
24532 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24533 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24535 /* New backported fma/fms instructions optional in v8.2. */
24536 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24537 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24539 #undef THUMB_VARIANT
24540 #define THUMB_VARIANT & fpu_neon_ext_v1
24542 #define ARM_VARIANT & fpu_neon_ext_v1
24544 /* Data processing with three registers of the same length. */
24545 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24546 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24547 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24548 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24549 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24550 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24551 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24552 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24553 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24554 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24555 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24556 /* If not immediate, fall back to neon_dyadic_i64_su.
24557 shl should accept I8 I16 I32 I64,
24558 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24559 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24560 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24561 /* Logic ops, types optional & ignored. */
24562 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24563 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24564 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24565 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24566 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24567 /* Bitfield ops, untyped. */
24568 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24569 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24570 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24571 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24572 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24573 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24574 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24575 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24576 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24577 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24578 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24579 back to neon_dyadic_if_su. */
24580 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24581 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24582 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24583 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24584 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24585 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24586 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24587 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24588 /* Comparison. Type I8 I16 I32 F32. */
24589 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24590 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24591 /* As above, D registers only. */
24592 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24593 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24594 /* Int and float variants, signedness unimportant. */
24595 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24596 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24597 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24598 /* Add/sub take types I8 I16 I32 I64 F32. */
24599 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24600 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24601 /* vtst takes sizes 8, 16, 32. */
24602 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24603 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24604 /* VMUL takes I8 I16 I32 F32 P8. */
24605 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24606 /* VQD{R}MULH takes S16 S32. */
24607 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24608 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24609 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24610 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24611 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24612 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24613 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24614 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24615 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24616 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24617 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24618 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24619 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24620 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24621 /* ARM v8.1 extension. */
24622 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24623 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24624 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24626 /* Two address, int/float. Types S8 S16 S32 F32. */
24627 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24628 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24630 /* Data processing with two registers and a shift amount. */
24631 /* Right shifts, and variants with rounding.
24632 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24633 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24634 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24635 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24636 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24637 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24638 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24639 /* Shift and insert. Sizes accepted 8 16 32 64. */
24640 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24641 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24642 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24643 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24644 /* Right shift immediate, saturating & narrowing, with rounding variants.
24645 Types accepted S16 S32 S64 U16 U32 U64. */
24646 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24647 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24648 /* As above, unsigned. Types accepted S16 S32 S64. */
24649 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24650 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24651 /* Right shift narrowing. Types accepted I16 I32 I64. */
24652 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24653 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24654 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24655 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24656 /* CVT with optional immediate for fixed-point variant. */
24657 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24659 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24661 /* Data processing, three registers of different lengths. */
24662 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24663 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24664 /* If not scalar, fall back to neon_dyadic_long.
24665 Vector types as above, scalar types S16 S32 U16 U32. */
24666 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24667 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24668 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24669 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24670 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24671 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24672 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24673 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24674 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24675 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24676 /* Saturating doubling multiplies. Types S16 S32. */
24677 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24678 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24679 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24680 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24681 S16 S32 U16 U32. */
24682 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24684 /* Extract. Size 8. */
24685 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24686 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24688 /* Two registers, miscellaneous. */
24689 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24690 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24691 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24692 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24693 /* Vector replicate. Sizes 8 16 32. */
24694 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24695 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24696 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24697 /* VMOVN. Types I16 I32 I64. */
24698 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24699 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24700 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24701 /* VQMOVUN. Types S16 S32 S64. */
24702 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24703 /* VZIP / VUZP. Sizes 8 16 32. */
24704 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24705 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24706 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24707 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24708 /* VQABS / VQNEG. Types S8 S16 S32. */
24709 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24710 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24711 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24712 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24713 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24714 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24715 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24716 /* Reciprocal estimates. Types U32 F16 F32. */
24717 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24718 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24719 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24720 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24721 /* VCLS. Types S8 S16 S32. */
24722 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24723 /* VCLZ. Types I8 I16 I32. */
24724 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24725 /* VCNT. Size 8. */
24726 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24727 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24728 /* Two address, untyped. */
24729 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24730 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24731 /* VTRN. Sizes 8 16 32. */
24732 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24733 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24735 /* Table lookup. Size 8. */
24736 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24737 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24739 #undef THUMB_VARIANT
24740 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24742 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24744 /* Neon element/structure load/store. */
24745 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24746 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24747 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24748 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24749 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24750 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24751 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24752 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24754 #undef THUMB_VARIANT
24755 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24757 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24758 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24759 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24760 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24761 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24762 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24763 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24764 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24765 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24766 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24768 #undef THUMB_VARIANT
24769 #define THUMB_VARIANT & fpu_vfp_ext_v3
24771 #define ARM_VARIANT & fpu_vfp_ext_v3
24773 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24774 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24775 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24776 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24777 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24778 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24779 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24780 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24781 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24784 #define ARM_VARIANT & fpu_vfp_ext_fma
24785 #undef THUMB_VARIANT
24786 #define THUMB_VARIANT & fpu_vfp_ext_fma
24787 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24788 VFP FMA variant; NEON and VFP FMA always includes the NEON
24789 FMA instructions. */
24790 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24791 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24793 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24794 the v form should always be used. */
24795 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24796 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24797 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24798 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24799 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24800 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24802 #undef THUMB_VARIANT
24804 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24806 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24807 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24808 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24809 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24810 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24811 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24812 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24813 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24816 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24818 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24819 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24820 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24821 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24822 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24823 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24824 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24825 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24826 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24827 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24828 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24829 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24830 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24831 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24832 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24833 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24834 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24835 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24836 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24837 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24838 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24839 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24840 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24841 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24842 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24843 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24844 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24845 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24846 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24847 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24848 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24849 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24850 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24851 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24852 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24853 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24854 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24855 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24856 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24857 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24858 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24859 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24860 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24861 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24862 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24863 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24864 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24865 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24866 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24867 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24868 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24869 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24870 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24871 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24872 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24873 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24874 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24875 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24876 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24877 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24878 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24879 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24880 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24881 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24882 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24883 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24884 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24885 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24886 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24887 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24888 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24889 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24890 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24891 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24892 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24893 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24894 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24895 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24896 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24897 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24898 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24899 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24900 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24901 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24902 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24903 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24904 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24905 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24906 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24907 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24908 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24909 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24910 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24911 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24912 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24913 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24914 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24915 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24916 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24917 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24918 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24919 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24920 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24921 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24922 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24923 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24924 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24925 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24926 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24927 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24928 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24929 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24930 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24931 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24932 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24933 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24934 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24935 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24936 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24937 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24938 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24939 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24940 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24941 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24942 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24943 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24944 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24945 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24946 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24947 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24948 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24949 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24950 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24951 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24952 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24953 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24954 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24955 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24956 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24957 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24958 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24959 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24960 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24961 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24962 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24963 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24964 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24965 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24966 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24967 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24968 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24969 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24970 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24971 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24972 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24973 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24974 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24975 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24976 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24977 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24978 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24979 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24982 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24984 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24985 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24986 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24987 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24988 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24989 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24990 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24991 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24992 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24993 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24994 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24995 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24996 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24997 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24998 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24999 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25000 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25001 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25002 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25003 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25004 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25005 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25006 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25007 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25008 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25009 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25010 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25011 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25012 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25013 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25014 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25015 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25016 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25017 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25018 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25019 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25020 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25021 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25022 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25023 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25024 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25025 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25026 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25027 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25028 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25029 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25030 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25031 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25032 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25033 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25034 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25035 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25036 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25037 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25038 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25039 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25040 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25043 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25045 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25046 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25047 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25048 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25049 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25050 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25051 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25052 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25053 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25054 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25055 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25056 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25057 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25058 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25059 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25060 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25061 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25062 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25063 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25064 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25065 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25066 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25067 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25068 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25069 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25070 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25071 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25072 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25073 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25074 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25075 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25076 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25077 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25078 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25079 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25080 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25081 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25082 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25083 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25084 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25085 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25086 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25087 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25088 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25089 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25090 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25091 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25092 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25093 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25094 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25095 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25096 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25097 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25098 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25099 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25100 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25101 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25102 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25103 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25104 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25105 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25106 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25107 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25108 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25109 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25110 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25111 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25112 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25113 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25114 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25115 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25116 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25117 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25118 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25119 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25120 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25122 /* ARMv8.5-A instructions. */
25124 #define ARM_VARIANT & arm_ext_sb
25125 #undef THUMB_VARIANT
25126 #define THUMB_VARIANT & arm_ext_sb
25127 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25130 #define ARM_VARIANT & arm_ext_predres
25131 #undef THUMB_VARIANT
25132 #define THUMB_VARIANT & arm_ext_predres
25133 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25134 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25135 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25137 /* ARMv8-M instructions. */
25139 #define ARM_VARIANT NULL
25140 #undef THUMB_VARIANT
25141 #define THUMB_VARIANT & arm_ext_v8m
25142 ToU("sg", e97fe97f
, 0, (), noargs
),
25143 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25144 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25145 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25146 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25147 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25148 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25150 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25151 instructions behave as nop if no VFP is present. */
25152 #undef THUMB_VARIANT
25153 #define THUMB_VARIANT & arm_ext_v8m_main
25154 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25155 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25157 /* Armv8.1-M Mainline instructions. */
25158 #undef THUMB_VARIANT
25159 #define THUMB_VARIANT & arm_ext_v8_1m_main
25160 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25161 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25162 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25163 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25164 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25166 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25167 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25168 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25170 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25171 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25173 #undef THUMB_VARIANT
25174 #define THUMB_VARIANT & mve_ext
25175 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25176 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25177 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25178 ToC("uqrshll", ea51010d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25179 ToC("sqrshrl", ea51012d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25180 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25181 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25182 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25183 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25184 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25185 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25186 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25187 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25188 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25189 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25191 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25192 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25193 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25194 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25195 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25196 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25197 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25198 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25199 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25200 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25201 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25202 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25203 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25204 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25205 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25207 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25208 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25209 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25210 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25211 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25212 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25213 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25214 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25215 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25216 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25217 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25218 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25219 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25220 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25221 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25223 /* MVE and MVE FP only. */
25224 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25225 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25226 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25227 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25228 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25229 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25230 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25231 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25232 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25233 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25234 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25235 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25236 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25237 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25238 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25239 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25240 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25242 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25243 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25244 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25245 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25246 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25247 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25248 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25249 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25250 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25251 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25252 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25253 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25254 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25255 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25256 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25257 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25258 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25259 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25260 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25261 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25263 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25264 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25265 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25266 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25267 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25268 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25269 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25270 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25271 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25272 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25273 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25274 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25275 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25276 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25277 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25278 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25279 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25281 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25282 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25283 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25284 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25285 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25286 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25287 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25288 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25289 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25290 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25291 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25292 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25293 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25294 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25295 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25296 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25297 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25298 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25299 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25300 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25302 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25303 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25304 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25305 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25306 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25308 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25309 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25310 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25311 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25312 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25313 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25314 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25315 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25316 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25317 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25318 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25319 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25320 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25321 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25322 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25323 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25324 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25326 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25327 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25328 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25329 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25330 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25331 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25332 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25333 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25334 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25335 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25336 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25337 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25339 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25340 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25341 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25343 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25344 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25345 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25346 toU("lctp", _lctp
, 0, (), t_loloop
),
25348 #undef THUMB_VARIANT
25349 #define THUMB_VARIANT & mve_fp_ext
25350 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25351 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25352 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25353 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25354 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25355 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25356 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25357 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25360 #define ARM_VARIANT & fpu_vfp_ext_v1
25361 #undef THUMB_VARIANT
25362 #define THUMB_VARIANT & arm_ext_v6t2
25363 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25364 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25366 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25369 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25371 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25372 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25373 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25374 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25376 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25377 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25378 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25380 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25381 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25383 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25384 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25386 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25387 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25390 #define ARM_VARIANT & fpu_vfp_ext_v2
25392 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25393 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25394 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25395 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25398 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25399 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25400 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25401 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25402 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25403 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25404 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25407 #define ARM_VARIANT & fpu_neon_ext_v1
25408 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25409 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25410 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25411 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25412 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25413 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25414 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25415 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25416 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25417 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25418 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25419 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25420 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25421 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25422 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25423 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25424 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25425 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25426 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25427 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25428 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25429 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25430 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25431 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25432 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25433 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25434 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25435 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25436 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25437 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25438 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25439 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25440 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25441 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25442 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25443 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25444 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25447 #define ARM_VARIANT & arm_ext_v8_3
25448 #undef THUMB_VARIANT
25449 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25450 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25451 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25454 #undef THUMB_VARIANT
25486 /* MD interface: bits in the object file. */
25488 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25489 for use in the a.out file, and stores them in the array pointed to by buf.
25490 This knows about the endian-ness of the target machine and does
25491 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25492 2 (short) and 4 (long) Floating numbers are put out as a series of
25493 LITTLENUMS (shorts, here at least). */
25496 md_number_to_chars (char * buf
, valueT val
, int n
)
25498 if (target_big_endian
)
25499 number_to_chars_bigendian (buf
, val
, n
);
25501 number_to_chars_littleendian (buf
, val
, n
);
25505 md_chars_to_number (char * buf
, int n
)
25508 unsigned char * where
= (unsigned char *) buf
;
25510 if (target_big_endian
)
25515 result
|= (*where
++ & 255);
25523 result
|= (where
[n
] & 255);
25530 /* MD interface: Sections. */
25532 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25533 that an rs_machine_dependent frag may reach. */
25536 arm_frag_max_var (fragS
*fragp
)
25538 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25539 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25541 Note that we generate relaxable instructions even for cases that don't
25542 really need it, like an immediate that's a trivial constant. So we're
25543 overestimating the instruction size for some of those cases. Rather
25544 than putting more intelligence here, it would probably be better to
25545 avoid generating a relaxation frag in the first place when it can be
25546 determined up front that a short instruction will suffice. */
25548 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25552 /* Estimate the size of a frag before relaxing. Assume everything fits in
25556 md_estimate_size_before_relax (fragS
* fragp
,
25557 segT segtype ATTRIBUTE_UNUSED
)
25563 /* Convert a machine dependent frag. */
25566 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25568 unsigned long insn
;
25569 unsigned long old_op
;
25577 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25579 old_op
= bfd_get_16(abfd
, buf
);
25580 if (fragp
->fr_symbol
)
25582 exp
.X_op
= O_symbol
;
25583 exp
.X_add_symbol
= fragp
->fr_symbol
;
25587 exp
.X_op
= O_constant
;
25589 exp
.X_add_number
= fragp
->fr_offset
;
25590 opcode
= fragp
->fr_subtype
;
25593 case T_MNEM_ldr_pc
:
25594 case T_MNEM_ldr_pc2
:
25595 case T_MNEM_ldr_sp
:
25596 case T_MNEM_str_sp
:
25603 if (fragp
->fr_var
== 4)
25605 insn
= THUMB_OP32 (opcode
);
25606 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25608 insn
|= (old_op
& 0x700) << 4;
25612 insn
|= (old_op
& 7) << 12;
25613 insn
|= (old_op
& 0x38) << 13;
25615 insn
|= 0x00000c00;
25616 put_thumb32_insn (buf
, insn
);
25617 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25621 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25623 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25626 if (fragp
->fr_var
== 4)
25628 insn
= THUMB_OP32 (opcode
);
25629 insn
|= (old_op
& 0xf0) << 4;
25630 put_thumb32_insn (buf
, insn
);
25631 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25635 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25636 exp
.X_add_number
-= 4;
25644 if (fragp
->fr_var
== 4)
25646 int r0off
= (opcode
== T_MNEM_mov
25647 || opcode
== T_MNEM_movs
) ? 0 : 8;
25648 insn
= THUMB_OP32 (opcode
);
25649 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25650 insn
|= (old_op
& 0x700) << r0off
;
25651 put_thumb32_insn (buf
, insn
);
25652 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25656 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25661 if (fragp
->fr_var
== 4)
25663 insn
= THUMB_OP32(opcode
);
25664 put_thumb32_insn (buf
, insn
);
25665 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25668 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25672 if (fragp
->fr_var
== 4)
25674 insn
= THUMB_OP32(opcode
);
25675 insn
|= (old_op
& 0xf00) << 14;
25676 put_thumb32_insn (buf
, insn
);
25677 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25680 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25683 case T_MNEM_add_sp
:
25684 case T_MNEM_add_pc
:
25685 case T_MNEM_inc_sp
:
25686 case T_MNEM_dec_sp
:
25687 if (fragp
->fr_var
== 4)
25689 /* ??? Choose between add and addw. */
25690 insn
= THUMB_OP32 (opcode
);
25691 insn
|= (old_op
& 0xf0) << 4;
25692 put_thumb32_insn (buf
, insn
);
25693 if (opcode
== T_MNEM_add_pc
)
25694 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25696 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25699 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25707 if (fragp
->fr_var
== 4)
25709 insn
= THUMB_OP32 (opcode
);
25710 insn
|= (old_op
& 0xf0) << 4;
25711 insn
|= (old_op
& 0xf) << 16;
25712 put_thumb32_insn (buf
, insn
);
25713 if (insn
& (1 << 20))
25714 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25716 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25719 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25725 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25726 (enum bfd_reloc_code_real
) reloc_type
);
25727 fixp
->fx_file
= fragp
->fr_file
;
25728 fixp
->fx_line
= fragp
->fr_line
;
25729 fragp
->fr_fix
+= fragp
->fr_var
;
25731 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25732 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25733 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25734 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25737 /* Return the size of a relaxable immediate operand instruction.
25738 SHIFT and SIZE specify the form of the allowable immediate. */
25740 relax_immediate (fragS
*fragp
, int size
, int shift
)
25746 /* ??? Should be able to do better than this. */
25747 if (fragp
->fr_symbol
)
25750 low
= (1 << shift
) - 1;
25751 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25752 offset
= fragp
->fr_offset
;
25753 /* Force misaligned offsets to 32-bit variant. */
25756 if (offset
& ~mask
)
25761 /* Get the address of a symbol during relaxation. */
25763 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25769 sym
= fragp
->fr_symbol
;
25770 sym_frag
= symbol_get_frag (sym
);
25771 know (S_GET_SEGMENT (sym
) != absolute_section
25772 || sym_frag
== &zero_address_frag
);
25773 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25775 /* If frag has yet to be reached on this pass, assume it will
25776 move by STRETCH just as we did. If this is not so, it will
25777 be because some frag between grows, and that will force
25781 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25785 /* Adjust stretch for any alignment frag. Note that if have
25786 been expanding the earlier code, the symbol may be
25787 defined in what appears to be an earlier frag. FIXME:
25788 This doesn't handle the fr_subtype field, which specifies
25789 a maximum number of bytes to skip when doing an
25791 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25793 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25796 stretch
= - ((- stretch
)
25797 & ~ ((1 << (int) f
->fr_offset
) - 1));
25799 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25811 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25814 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25819 /* Assume worst case for symbols not known to be in the same section. */
25820 if (fragp
->fr_symbol
== NULL
25821 || !S_IS_DEFINED (fragp
->fr_symbol
)
25822 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25823 || S_IS_WEAK (fragp
->fr_symbol
))
25826 val
= relaxed_symbol_addr (fragp
, stretch
);
25827 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25828 addr
= (addr
+ 4) & ~3;
25829 /* Force misaligned targets to 32-bit variant. */
25833 if (val
< 0 || val
> 1020)
25838 /* Return the size of a relaxable add/sub immediate instruction. */
25840 relax_addsub (fragS
*fragp
, asection
*sec
)
25845 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25846 op
= bfd_get_16(sec
->owner
, buf
);
25847 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25848 return relax_immediate (fragp
, 8, 0);
25850 return relax_immediate (fragp
, 3, 0);
25853 /* Return TRUE iff the definition of symbol S could be pre-empted
25854 (overridden) at link or load time. */
25856 symbol_preemptible (symbolS
*s
)
25858 /* Weak symbols can always be pre-empted. */
25862 /* Non-global symbols cannot be pre-empted. */
25863 if (! S_IS_EXTERNAL (s
))
25867 /* In ELF, a global symbol can be marked protected, or private. In that
25868 case it can't be pre-empted (other definitions in the same link unit
25869 would violate the ODR). */
25870 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25874 /* Other global symbols might be pre-empted. */
25878 /* Return the size of a relaxable branch instruction. BITS is the
25879 size of the offset field in the narrow instruction. */
25882 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25888 /* Assume worst case for symbols not known to be in the same section. */
25889 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25890 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25891 || S_IS_WEAK (fragp
->fr_symbol
))
25895 /* A branch to a function in ARM state will require interworking. */
25896 if (S_IS_DEFINED (fragp
->fr_symbol
)
25897 && ARM_IS_FUNC (fragp
->fr_symbol
))
25901 if (symbol_preemptible (fragp
->fr_symbol
))
25904 val
= relaxed_symbol_addr (fragp
, stretch
);
25905 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25908 /* Offset is a signed value *2 */
25910 if (val
>= limit
|| val
< -limit
)
25916 /* Relax a machine dependent frag. This returns the amount by which
25917 the current size of the frag should change. */
25920 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25925 oldsize
= fragp
->fr_var
;
25926 switch (fragp
->fr_subtype
)
25928 case T_MNEM_ldr_pc2
:
25929 newsize
= relax_adr (fragp
, sec
, stretch
);
25931 case T_MNEM_ldr_pc
:
25932 case T_MNEM_ldr_sp
:
25933 case T_MNEM_str_sp
:
25934 newsize
= relax_immediate (fragp
, 8, 2);
25938 newsize
= relax_immediate (fragp
, 5, 2);
25942 newsize
= relax_immediate (fragp
, 5, 1);
25946 newsize
= relax_immediate (fragp
, 5, 0);
25949 newsize
= relax_adr (fragp
, sec
, stretch
);
25955 newsize
= relax_immediate (fragp
, 8, 0);
25958 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25961 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25963 case T_MNEM_add_sp
:
25964 case T_MNEM_add_pc
:
25965 newsize
= relax_immediate (fragp
, 8, 2);
25967 case T_MNEM_inc_sp
:
25968 case T_MNEM_dec_sp
:
25969 newsize
= relax_immediate (fragp
, 7, 2);
25975 newsize
= relax_addsub (fragp
, sec
);
25981 fragp
->fr_var
= newsize
;
25982 /* Freeze wide instructions that are at or before the same location as
25983 in the previous pass. This avoids infinite loops.
25984 Don't freeze them unconditionally because targets may be artificially
25985 misaligned by the expansion of preceding frags. */
25986 if (stretch
<= 0 && newsize
> 2)
25988 md_convert_frag (sec
->owner
, sec
, fragp
);
25992 return newsize
- oldsize
;
25995 /* Round up a section size to the appropriate boundary. */
25998 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26004 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26005 of an rs_align_code fragment. */
26008 arm_handle_align (fragS
* fragP
)
26010 static unsigned char const arm_noop
[2][2][4] =
26013 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26014 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26017 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26018 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26021 static unsigned char const thumb_noop
[2][2][2] =
26024 {0xc0, 0x46}, /* LE */
26025 {0x46, 0xc0}, /* BE */
26028 {0x00, 0xbf}, /* LE */
26029 {0xbf, 0x00} /* BE */
26032 static unsigned char const wide_thumb_noop
[2][4] =
26033 { /* Wide Thumb-2 */
26034 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26035 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26038 unsigned bytes
, fix
, noop_size
;
26040 const unsigned char * noop
;
26041 const unsigned char *narrow_noop
= NULL
;
26046 if (fragP
->fr_type
!= rs_align_code
)
26049 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26050 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26053 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26054 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26056 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26058 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26060 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26061 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26063 narrow_noop
= thumb_noop
[1][target_big_endian
];
26064 noop
= wide_thumb_noop
[target_big_endian
];
26067 noop
= thumb_noop
[0][target_big_endian
];
26075 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26076 ? selected_cpu
: arm_arch_none
,
26078 [target_big_endian
];
26085 fragP
->fr_var
= noop_size
;
26087 if (bytes
& (noop_size
- 1))
26089 fix
= bytes
& (noop_size
- 1);
26091 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26093 memset (p
, 0, fix
);
26100 if (bytes
& noop_size
)
26102 /* Insert a narrow noop. */
26103 memcpy (p
, narrow_noop
, noop_size
);
26105 bytes
-= noop_size
;
26109 /* Use wide noops for the remainder */
26113 while (bytes
>= noop_size
)
26115 memcpy (p
, noop
, noop_size
);
26117 bytes
-= noop_size
;
26121 fragP
->fr_fix
+= fix
;
26124 /* Called from md_do_align. Used to create an alignment
26125 frag in a code section. */
26128 arm_frag_align_code (int n
, int max
)
26132 /* We assume that there will never be a requirement
26133 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26134 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26139 _("alignments greater than %d bytes not supported in .text sections."),
26140 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26141 as_fatal ("%s", err_msg
);
26144 p
= frag_var (rs_align_code
,
26145 MAX_MEM_FOR_RS_ALIGN_CODE
,
26147 (relax_substateT
) max
,
26154 /* Perform target specific initialisation of a frag.
26155 Note - despite the name this initialisation is not done when the frag
26156 is created, but only when its type is assigned. A frag can be created
26157 and used a long time before its type is set, so beware of assuming that
26158 this initialisation is performed first. */
26162 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26164 /* Record whether this frag is in an ARM or a THUMB area. */
26165 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26168 #else /* OBJ_ELF is defined. */
26170 arm_init_frag (fragS
* fragP
, int max_chars
)
26172 bfd_boolean frag_thumb_mode
;
26174 /* If the current ARM vs THUMB mode has not already
26175 been recorded into this frag then do so now. */
26176 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26177 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26179 /* PR 21809: Do not set a mapping state for debug sections
26180 - it just confuses other tools. */
26181 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26184 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26186 /* Record a mapping symbol for alignment frags. We will delete this
26187 later if the alignment ends up empty. */
26188 switch (fragP
->fr_type
)
26191 case rs_align_test
:
26193 mapping_state_2 (MAP_DATA
, max_chars
);
26195 case rs_align_code
:
26196 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26203 /* When we change sections we need to issue a new mapping symbol. */
26206 arm_elf_change_section (void)
26208 /* Link an unlinked unwind index table section to the .text section. */
26209 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26210 && elf_linked_to_section (now_seg
) == NULL
)
26211 elf_linked_to_section (now_seg
) = text_section
;
26215 arm_elf_section_type (const char * str
, size_t len
)
26217 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26218 return SHT_ARM_EXIDX
;
26223 /* Code to deal with unwinding tables. */
26225 static void add_unwind_adjustsp (offsetT
);
26227 /* Generate any deferred unwind frame offset. */
26230 flush_pending_unwind (void)
26234 offset
= unwind
.pending_offset
;
26235 unwind
.pending_offset
= 0;
26237 add_unwind_adjustsp (offset
);
26240 /* Add an opcode to this list for this function. Two-byte opcodes should
26241 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26245 add_unwind_opcode (valueT op
, int length
)
26247 /* Add any deferred stack adjustment. */
26248 if (unwind
.pending_offset
)
26249 flush_pending_unwind ();
26251 unwind
.sp_restored
= 0;
26253 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26255 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26256 if (unwind
.opcodes
)
26257 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26258 unwind
.opcode_alloc
);
26260 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26265 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26267 unwind
.opcode_count
++;
26271 /* Add unwind opcodes to adjust the stack pointer. */
26274 add_unwind_adjustsp (offsetT offset
)
26278 if (offset
> 0x200)
26280 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26285 /* Long form: 0xb2, uleb128. */
26286 /* This might not fit in a word so add the individual bytes,
26287 remembering the list is built in reverse order. */
26288 o
= (valueT
) ((offset
- 0x204) >> 2);
26290 add_unwind_opcode (0, 1);
26292 /* Calculate the uleb128 encoding of the offset. */
26296 bytes
[n
] = o
& 0x7f;
26302 /* Add the insn. */
26304 add_unwind_opcode (bytes
[n
- 1], 1);
26305 add_unwind_opcode (0xb2, 1);
26307 else if (offset
> 0x100)
26309 /* Two short opcodes. */
26310 add_unwind_opcode (0x3f, 1);
26311 op
= (offset
- 0x104) >> 2;
26312 add_unwind_opcode (op
, 1);
26314 else if (offset
> 0)
26316 /* Short opcode. */
26317 op
= (offset
- 4) >> 2;
26318 add_unwind_opcode (op
, 1);
26320 else if (offset
< 0)
26323 while (offset
> 0x100)
26325 add_unwind_opcode (0x7f, 1);
26328 op
= ((offset
- 4) >> 2) | 0x40;
26329 add_unwind_opcode (op
, 1);
26333 /* Finish the list of unwind opcodes for this function. */
26336 finish_unwind_opcodes (void)
26340 if (unwind
.fp_used
)
26342 /* Adjust sp as necessary. */
26343 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26344 flush_pending_unwind ();
26346 /* After restoring sp from the frame pointer. */
26347 op
= 0x90 | unwind
.fp_reg
;
26348 add_unwind_opcode (op
, 1);
26351 flush_pending_unwind ();
26355 /* Start an exception table entry. If idx is nonzero this is an index table
26359 start_unwind_section (const segT text_seg
, int idx
)
26361 const char * text_name
;
26362 const char * prefix
;
26363 const char * prefix_once
;
26364 const char * group_name
;
26372 prefix
= ELF_STRING_ARM_unwind
;
26373 prefix_once
= ELF_STRING_ARM_unwind_once
;
26374 type
= SHT_ARM_EXIDX
;
26378 prefix
= ELF_STRING_ARM_unwind_info
;
26379 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26380 type
= SHT_PROGBITS
;
26383 text_name
= segment_name (text_seg
);
26384 if (streq (text_name
, ".text"))
26387 if (strncmp (text_name
, ".gnu.linkonce.t.",
26388 strlen (".gnu.linkonce.t.")) == 0)
26390 prefix
= prefix_once
;
26391 text_name
+= strlen (".gnu.linkonce.t.");
26394 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26400 /* Handle COMDAT group. */
26401 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26403 group_name
= elf_group_name (text_seg
);
26404 if (group_name
== NULL
)
26406 as_bad (_("Group section `%s' has no group signature"),
26407 segment_name (text_seg
));
26408 ignore_rest_of_line ();
26411 flags
|= SHF_GROUP
;
26415 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26418 /* Set the section link for index tables. */
26420 elf_linked_to_section (now_seg
) = text_seg
;
26424 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26425 personality routine data. Returns zero, or the index table value for
26426 an inline entry. */
26429 create_unwind_entry (int have_data
)
26434 /* The current word of data. */
26436 /* The number of bytes left in this word. */
26439 finish_unwind_opcodes ();
26441 /* Remember the current text section. */
26442 unwind
.saved_seg
= now_seg
;
26443 unwind
.saved_subseg
= now_subseg
;
26445 start_unwind_section (now_seg
, 0);
26447 if (unwind
.personality_routine
== NULL
)
26449 if (unwind
.personality_index
== -2)
26452 as_bad (_("handlerdata in cantunwind frame"));
26453 return 1; /* EXIDX_CANTUNWIND. */
26456 /* Use a default personality routine if none is specified. */
26457 if (unwind
.personality_index
== -1)
26459 if (unwind
.opcode_count
> 3)
26460 unwind
.personality_index
= 1;
26462 unwind
.personality_index
= 0;
26465 /* Space for the personality routine entry. */
26466 if (unwind
.personality_index
== 0)
26468 if (unwind
.opcode_count
> 3)
26469 as_bad (_("too many unwind opcodes for personality routine 0"));
26473 /* All the data is inline in the index table. */
26476 while (unwind
.opcode_count
> 0)
26478 unwind
.opcode_count
--;
26479 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26483 /* Pad with "finish" opcodes. */
26485 data
= (data
<< 8) | 0xb0;
26492 /* We get two opcodes "free" in the first word. */
26493 size
= unwind
.opcode_count
- 2;
26497 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26498 if (unwind
.personality_index
!= -1)
26500 as_bad (_("attempt to recreate an unwind entry"));
26504 /* An extra byte is required for the opcode count. */
26505 size
= unwind
.opcode_count
+ 1;
26508 size
= (size
+ 3) >> 2;
26510 as_bad (_("too many unwind opcodes"));
26512 frag_align (2, 0, 0);
26513 record_alignment (now_seg
, 2);
26514 unwind
.table_entry
= expr_build_dot ();
26516 /* Allocate the table entry. */
26517 ptr
= frag_more ((size
<< 2) + 4);
26518 /* PR 13449: Zero the table entries in case some of them are not used. */
26519 memset (ptr
, 0, (size
<< 2) + 4);
26520 where
= frag_now_fix () - ((size
<< 2) + 4);
26522 switch (unwind
.personality_index
)
26525 /* ??? Should this be a PLT generating relocation? */
26526 /* Custom personality routine. */
26527 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26528 BFD_RELOC_ARM_PREL31
);
26533 /* Set the first byte to the number of additional words. */
26534 data
= size
> 0 ? size
- 1 : 0;
26538 /* ABI defined personality routines. */
26540 /* Three opcodes bytes are packed into the first word. */
26547 /* The size and first two opcode bytes go in the first word. */
26548 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26553 /* Should never happen. */
26557 /* Pack the opcodes into words (MSB first), reversing the list at the same
26559 while (unwind
.opcode_count
> 0)
26563 md_number_to_chars (ptr
, data
, 4);
26568 unwind
.opcode_count
--;
26570 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26573 /* Finish off the last word. */
26576 /* Pad with "finish" opcodes. */
26578 data
= (data
<< 8) | 0xb0;
26580 md_number_to_chars (ptr
, data
, 4);
26585 /* Add an empty descriptor if there is no user-specified data. */
26586 ptr
= frag_more (4);
26587 md_number_to_chars (ptr
, 0, 4);
26594 /* Initialize the DWARF-2 unwind information for this procedure. */
26597 tc_arm_frame_initial_instructions (void)
26599 cfi_add_CFA_def_cfa (REG_SP
, 0);
26601 #endif /* OBJ_ELF */
26603 /* Convert REGNAME to a DWARF-2 register number. */
26606 tc_arm_regname_to_dw2regnum (char *regname
)
26608 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26612 /* PR 16694: Allow VFP registers as well. */
26613 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26617 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26626 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26630 exp
.X_op
= O_secrel
;
26631 exp
.X_add_symbol
= symbol
;
26632 exp
.X_add_number
= 0;
26633 emit_expr (&exp
, size
);
26637 /* MD interface: Symbol and relocation handling. */
26639 /* Return the address within the segment that a PC-relative fixup is
26640 relative to. For ARM, PC-relative fixups applied to instructions
26641 are generally relative to the location of the fixup plus 8 bytes.
26642 Thumb branches are offset by 4, and Thumb loads relative to PC
26643 require special handling. */
26646 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26648 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26650 /* If this is pc-relative and we are going to emit a relocation
26651 then we just want to put out any pipeline compensation that the linker
26652 will need. Otherwise we want to use the calculated base.
26653 For WinCE we skip the bias for externals as well, since this
26654 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26656 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26657 || (arm_force_relocation (fixP
)
26659 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26665 switch (fixP
->fx_r_type
)
26667 /* PC relative addressing on the Thumb is slightly odd as the
26668 bottom two bits of the PC are forced to zero for the
26669 calculation. This happens *after* application of the
26670 pipeline offset. However, Thumb adrl already adjusts for
26671 this, so we need not do it again. */
26672 case BFD_RELOC_ARM_THUMB_ADD
:
26675 case BFD_RELOC_ARM_THUMB_OFFSET
:
26676 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26677 case BFD_RELOC_ARM_T32_ADD_PC12
:
26678 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26679 return (base
+ 4) & ~3;
26681 /* Thumb branches are simply offset by +4. */
26682 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26683 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26684 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26685 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26686 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26687 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26688 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26689 case BFD_RELOC_ARM_THUMB_BF17
:
26690 case BFD_RELOC_ARM_THUMB_BF19
:
26691 case BFD_RELOC_ARM_THUMB_BF13
:
26692 case BFD_RELOC_ARM_THUMB_LOOP12
:
26695 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26697 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26698 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26699 && ARM_IS_FUNC (fixP
->fx_addsy
)
26700 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26701 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26704 /* BLX is like branches above, but forces the low two bits of PC to
26706 case BFD_RELOC_THUMB_PCREL_BLX
:
26708 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26709 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26710 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26711 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26712 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26713 return (base
+ 4) & ~3;
26715 /* ARM mode branches are offset by +8. However, the Windows CE
26716 loader expects the relocation not to take this into account. */
26717 case BFD_RELOC_ARM_PCREL_BLX
:
26719 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26720 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26721 && ARM_IS_FUNC (fixP
->fx_addsy
)
26722 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26723 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26726 case BFD_RELOC_ARM_PCREL_CALL
:
26728 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26729 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26730 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26731 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26732 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26735 case BFD_RELOC_ARM_PCREL_BRANCH
:
26736 case BFD_RELOC_ARM_PCREL_JUMP
:
26737 case BFD_RELOC_ARM_PLT32
:
26739 /* When handling fixups immediately, because we have already
26740 discovered the value of a symbol, or the address of the frag involved
26741 we must account for the offset by +8, as the OS loader will never see the reloc.
26742 see fixup_segment() in write.c
26743 The S_IS_EXTERNAL test handles the case of global symbols.
26744 Those need the calculated base, not just the pipe compensation the linker will need. */
26746 && fixP
->fx_addsy
!= NULL
26747 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26748 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26756 /* ARM mode loads relative to PC are also offset by +8. Unlike
26757 branches, the Windows CE loader *does* expect the relocation
26758 to take this into account. */
26759 case BFD_RELOC_ARM_OFFSET_IMM
:
26760 case BFD_RELOC_ARM_OFFSET_IMM8
:
26761 case BFD_RELOC_ARM_HWLITERAL
:
26762 case BFD_RELOC_ARM_LITERAL
:
26763 case BFD_RELOC_ARM_CP_OFF_IMM
:
26767 /* Other PC-relative relocations are un-offset. */
26773 static bfd_boolean flag_warn_syms
= TRUE
;
26776 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26778 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26779 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26780 does mean that the resulting code might be very confusing to the reader.
26781 Also this warning can be triggered if the user omits an operand before
26782 an immediate address, eg:
26786 GAS treats this as an assignment of the value of the symbol foo to a
26787 symbol LDR, and so (without this code) it will not issue any kind of
26788 warning or error message.
26790 Note - ARM instructions are case-insensitive but the strings in the hash
26791 table are all stored in lower case, so we must first ensure that name is
26793 if (flag_warn_syms
&& arm_ops_hsh
)
26795 char * nbuf
= strdup (name
);
26798 for (p
= nbuf
; *p
; p
++)
26800 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26802 static struct hash_control
* already_warned
= NULL
;
26804 if (already_warned
== NULL
)
26805 already_warned
= hash_new ();
26806 /* Only warn about the symbol once. To keep the code
26807 simple we let hash_insert do the lookup for us. */
26808 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26809 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26818 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26819 Otherwise we have no need to default values of symbols. */
26822 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26825 if (name
[0] == '_' && name
[1] == 'G'
26826 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26830 if (symbol_find (name
))
26831 as_bad (_("GOT already in the symbol table"));
26833 GOT_symbol
= symbol_new (name
, undefined_section
,
26834 (valueT
) 0, & zero_address_frag
);
26844 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26845 computed as two separate immediate values, added together. We
26846 already know that this value cannot be computed by just one ARM
26849 static unsigned int
26850 validate_immediate_twopart (unsigned int val
,
26851 unsigned int * highpart
)
26856 for (i
= 0; i
< 32; i
+= 2)
26857 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26863 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26865 else if (a
& 0xff0000)
26867 if (a
& 0xff000000)
26869 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26873 gas_assert (a
& 0xff000000);
26874 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26877 return (a
& 0xff) | (i
<< 7);
26884 validate_offset_imm (unsigned int val
, int hwse
)
26886 if ((hwse
&& val
> 255) || val
> 4095)
26891 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26892 negative immediate constant by altering the instruction. A bit of
26897 by inverting the second operand, and
26900 by negating the second operand. */
26903 negate_data_op (unsigned long * instruction
,
26904 unsigned long value
)
26907 unsigned long negated
, inverted
;
26909 negated
= encode_arm_immediate (-value
);
26910 inverted
= encode_arm_immediate (~value
);
26912 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26915 /* First negates. */
26916 case OPCODE_SUB
: /* ADD <-> SUB */
26917 new_inst
= OPCODE_ADD
;
26922 new_inst
= OPCODE_SUB
;
26926 case OPCODE_CMP
: /* CMP <-> CMN */
26927 new_inst
= OPCODE_CMN
;
26932 new_inst
= OPCODE_CMP
;
26936 /* Now Inverted ops. */
26937 case OPCODE_MOV
: /* MOV <-> MVN */
26938 new_inst
= OPCODE_MVN
;
26943 new_inst
= OPCODE_MOV
;
26947 case OPCODE_AND
: /* AND <-> BIC */
26948 new_inst
= OPCODE_BIC
;
26953 new_inst
= OPCODE_AND
;
26957 case OPCODE_ADC
: /* ADC <-> SBC */
26958 new_inst
= OPCODE_SBC
;
26963 new_inst
= OPCODE_ADC
;
26967 /* We cannot do anything. */
26972 if (value
== (unsigned) FAIL
)
26975 *instruction
&= OPCODE_MASK
;
26976 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26980 /* Like negate_data_op, but for Thumb-2. */
26982 static unsigned int
26983 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26987 unsigned int negated
, inverted
;
26989 negated
= encode_thumb32_immediate (-value
);
26990 inverted
= encode_thumb32_immediate (~value
);
26992 rd
= (*instruction
>> 8) & 0xf;
26993 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26996 /* ADD <-> SUB. Includes CMP <-> CMN. */
26997 case T2_OPCODE_SUB
:
26998 new_inst
= T2_OPCODE_ADD
;
27002 case T2_OPCODE_ADD
:
27003 new_inst
= T2_OPCODE_SUB
;
27007 /* ORR <-> ORN. Includes MOV <-> MVN. */
27008 case T2_OPCODE_ORR
:
27009 new_inst
= T2_OPCODE_ORN
;
27013 case T2_OPCODE_ORN
:
27014 new_inst
= T2_OPCODE_ORR
;
27018 /* AND <-> BIC. TST has no inverted equivalent. */
27019 case T2_OPCODE_AND
:
27020 new_inst
= T2_OPCODE_BIC
;
27027 case T2_OPCODE_BIC
:
27028 new_inst
= T2_OPCODE_AND
;
27033 case T2_OPCODE_ADC
:
27034 new_inst
= T2_OPCODE_SBC
;
27038 case T2_OPCODE_SBC
:
27039 new_inst
= T2_OPCODE_ADC
;
27043 /* We cannot do anything. */
27048 if (value
== (unsigned int)FAIL
)
27051 *instruction
&= T2_OPCODE_MASK
;
27052 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27056 /* Read a 32-bit thumb instruction from buf. */
27058 static unsigned long
27059 get_thumb32_insn (char * buf
)
27061 unsigned long insn
;
27062 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27063 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27068 /* We usually want to set the low bit on the address of thumb function
27069 symbols. In particular .word foo - . should have the low bit set.
27070 Generic code tries to fold the difference of two symbols to
27071 a constant. Prevent this and force a relocation when the first symbols
27072 is a thumb function. */
27075 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27077 if (op
== O_subtract
27078 && l
->X_op
== O_symbol
27079 && r
->X_op
== O_symbol
27080 && THUMB_IS_FUNC (l
->X_add_symbol
))
27082 l
->X_op
= O_subtract
;
27083 l
->X_op_symbol
= r
->X_add_symbol
;
27084 l
->X_add_number
-= r
->X_add_number
;
27088 /* Process as normal. */
27092 /* Encode Thumb2 unconditional branches and calls. The encoding
27093 for the 2 are identical for the immediate values. */
27096 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27098 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27101 addressT S
, I1
, I2
, lo
, hi
;
27103 S
= (value
>> 24) & 0x01;
27104 I1
= (value
>> 23) & 0x01;
27105 I2
= (value
>> 22) & 0x01;
27106 hi
= (value
>> 12) & 0x3ff;
27107 lo
= (value
>> 1) & 0x7ff;
27108 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27109 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27110 newval
|= (S
<< 10) | hi
;
27111 newval2
&= ~T2I1I2MASK
;
27112 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27113 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27114 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27118 md_apply_fix (fixS
* fixP
,
27122 offsetT value
= * valP
;
27124 unsigned int newimm
;
27125 unsigned long temp
;
27127 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27129 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27131 /* Note whether this will delete the relocation. */
27133 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27136 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27137 consistency with the behaviour on 32-bit hosts. Remember value
27139 value
&= 0xffffffff;
27140 value
^= 0x80000000;
27141 value
-= 0x80000000;
27144 fixP
->fx_addnumber
= value
;
27146 /* Same treatment for fixP->fx_offset. */
27147 fixP
->fx_offset
&= 0xffffffff;
27148 fixP
->fx_offset
^= 0x80000000;
27149 fixP
->fx_offset
-= 0x80000000;
27151 switch (fixP
->fx_r_type
)
27153 case BFD_RELOC_NONE
:
27154 /* This will need to go in the object file. */
27158 case BFD_RELOC_ARM_IMMEDIATE
:
27159 /* We claim that this fixup has been processed here,
27160 even if in fact we generate an error because we do
27161 not have a reloc for it, so tc_gen_reloc will reject it. */
27164 if (fixP
->fx_addsy
)
27166 const char *msg
= 0;
27168 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27169 msg
= _("undefined symbol %s used as an immediate value");
27170 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27171 msg
= _("symbol %s is in a different section");
27172 else if (S_IS_WEAK (fixP
->fx_addsy
))
27173 msg
= _("symbol %s is weak and may be overridden later");
27177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27178 msg
, S_GET_NAME (fixP
->fx_addsy
));
27183 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27185 /* If the offset is negative, we should use encoding A2 for ADR. */
27186 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27187 newimm
= negate_data_op (&temp
, value
);
27190 newimm
= encode_arm_immediate (value
);
27192 /* If the instruction will fail, see if we can fix things up by
27193 changing the opcode. */
27194 if (newimm
== (unsigned int) FAIL
)
27195 newimm
= negate_data_op (&temp
, value
);
27196 /* MOV accepts both ARM modified immediate (A1 encoding) and
27197 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27198 When disassembling, MOV is preferred when there is no encoding
27200 if (newimm
== (unsigned int) FAIL
27201 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27202 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27203 && !((temp
>> SBIT_SHIFT
) & 0x1)
27204 && value
>= 0 && value
<= 0xffff)
27206 /* Clear bits[23:20] to change encoding from A1 to A2. */
27207 temp
&= 0xff0fffff;
27208 /* Encoding high 4bits imm. Code below will encode the remaining
27210 temp
|= (value
& 0x0000f000) << 4;
27211 newimm
= value
& 0x00000fff;
27215 if (newimm
== (unsigned int) FAIL
)
27217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27218 _("invalid constant (%lx) after fixup"),
27219 (unsigned long) value
);
27223 newimm
|= (temp
& 0xfffff000);
27224 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27227 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27229 unsigned int highpart
= 0;
27230 unsigned int newinsn
= 0xe1a00000; /* nop. */
27232 if (fixP
->fx_addsy
)
27234 const char *msg
= 0;
27236 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27237 msg
= _("undefined symbol %s used as an immediate value");
27238 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27239 msg
= _("symbol %s is in a different section");
27240 else if (S_IS_WEAK (fixP
->fx_addsy
))
27241 msg
= _("symbol %s is weak and may be overridden later");
27245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27246 msg
, S_GET_NAME (fixP
->fx_addsy
));
27251 newimm
= encode_arm_immediate (value
);
27252 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27254 /* If the instruction will fail, see if we can fix things up by
27255 changing the opcode. */
27256 if (newimm
== (unsigned int) FAIL
27257 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27259 /* No ? OK - try using two ADD instructions to generate
27261 newimm
= validate_immediate_twopart (value
, & highpart
);
27263 /* Yes - then make sure that the second instruction is
27265 if (newimm
!= (unsigned int) FAIL
)
27267 /* Still No ? Try using a negated value. */
27268 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27269 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27270 /* Otherwise - give up. */
27273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27274 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27279 /* Replace the first operand in the 2nd instruction (which
27280 is the PC) with the destination register. We have
27281 already added in the PC in the first instruction and we
27282 do not want to do it again. */
27283 newinsn
&= ~ 0xf0000;
27284 newinsn
|= ((newinsn
& 0x0f000) << 4);
27287 newimm
|= (temp
& 0xfffff000);
27288 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27290 highpart
|= (newinsn
& 0xfffff000);
27291 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27295 case BFD_RELOC_ARM_OFFSET_IMM
:
27296 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27298 /* Fall through. */
27300 case BFD_RELOC_ARM_LITERAL
:
27306 if (validate_offset_imm (value
, 0) == FAIL
)
27308 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27310 _("invalid literal constant: pool needs to be closer"));
27312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27313 _("bad immediate value for offset (%ld)"),
27318 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27320 newval
&= 0xfffff000;
27323 newval
&= 0xff7ff000;
27324 newval
|= value
| (sign
? INDEX_UP
: 0);
27326 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27329 case BFD_RELOC_ARM_OFFSET_IMM8
:
27330 case BFD_RELOC_ARM_HWLITERAL
:
27336 if (validate_offset_imm (value
, 1) == FAIL
)
27338 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27340 _("invalid literal constant: pool needs to be closer"));
27342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27343 _("bad immediate value for 8-bit offset (%ld)"),
27348 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27350 newval
&= 0xfffff0f0;
27353 newval
&= 0xff7ff0f0;
27354 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27356 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27359 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27360 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27362 _("bad immediate value for offset (%ld)"), (long) value
);
27365 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27367 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27370 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27371 /* This is a complicated relocation used for all varieties of Thumb32
27372 load/store instruction with immediate offset:
27374 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27375 *4, optional writeback(W)
27376 (doubleword load/store)
27378 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27379 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27380 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27381 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27382 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27384 Uppercase letters indicate bits that are already encoded at
27385 this point. Lowercase letters are our problem. For the
27386 second block of instructions, the secondary opcode nybble
27387 (bits 8..11) is present, and bit 23 is zero, even if this is
27388 a PC-relative operation. */
27389 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27391 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27393 if ((newval
& 0xf0000000) == 0xe0000000)
27395 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27397 newval
|= (1 << 23);
27400 if (value
% 4 != 0)
27402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27403 _("offset not a multiple of 4"));
27409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27410 _("offset out of range"));
27415 else if ((newval
& 0x000f0000) == 0x000f0000)
27417 /* PC-relative, 12-bit offset. */
27419 newval
|= (1 << 23);
27424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27425 _("offset out of range"));
27430 else if ((newval
& 0x00000100) == 0x00000100)
27432 /* Writeback: 8-bit, +/- offset. */
27434 newval
|= (1 << 9);
27439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27440 _("offset out of range"));
27445 else if ((newval
& 0x00000f00) == 0x00000e00)
27447 /* T-instruction: positive 8-bit offset. */
27448 if (value
< 0 || value
> 0xff)
27450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27451 _("offset out of range"));
27459 /* Positive 12-bit or negative 8-bit offset. */
27463 newval
|= (1 << 23);
27473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27474 _("offset out of range"));
27481 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27482 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27485 case BFD_RELOC_ARM_SHIFT_IMM
:
27486 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27487 if (((unsigned long) value
) > 32
27489 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27492 _("shift expression is too large"));
27497 /* Shifts of zero must be done as lsl. */
27499 else if (value
== 32)
27501 newval
&= 0xfffff07f;
27502 newval
|= (value
& 0x1f) << 7;
27503 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27506 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27507 case BFD_RELOC_ARM_T32_ADD_IMM
:
27508 case BFD_RELOC_ARM_T32_IMM12
:
27509 case BFD_RELOC_ARM_T32_ADD_PC12
:
27510 /* We claim that this fixup has been processed here,
27511 even if in fact we generate an error because we do
27512 not have a reloc for it, so tc_gen_reloc will reject it. */
27516 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27519 _("undefined symbol %s used as an immediate value"),
27520 S_GET_NAME (fixP
->fx_addsy
));
27524 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27526 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27529 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27530 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27531 Thumb2 modified immediate encoding (T2). */
27532 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27533 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27535 newimm
= encode_thumb32_immediate (value
);
27536 if (newimm
== (unsigned int) FAIL
)
27537 newimm
= thumb32_negate_data_op (&newval
, value
);
27539 if (newimm
== (unsigned int) FAIL
)
27541 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27543 /* Turn add/sum into addw/subw. */
27544 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27545 newval
= (newval
& 0xfeffffff) | 0x02000000;
27546 /* No flat 12-bit imm encoding for addsw/subsw. */
27547 if ((newval
& 0x00100000) == 0)
27549 /* 12 bit immediate for addw/subw. */
27553 newval
^= 0x00a00000;
27556 newimm
= (unsigned int) FAIL
;
27563 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27564 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27565 disassembling, MOV is preferred when there is no encoding
27567 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27568 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27569 but with the Rn field [19:16] set to 1111. */
27570 && (((newval
>> 16) & 0xf) == 0xf)
27571 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27572 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27573 && value
>= 0 && value
<= 0xffff)
27575 /* Toggle bit[25] to change encoding from T2 to T3. */
27577 /* Clear bits[19:16]. */
27578 newval
&= 0xfff0ffff;
27579 /* Encoding high 4bits imm. Code below will encode the
27580 remaining low 12bits. */
27581 newval
|= (value
& 0x0000f000) << 4;
27582 newimm
= value
& 0x00000fff;
27587 if (newimm
== (unsigned int)FAIL
)
27589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27590 _("invalid constant (%lx) after fixup"),
27591 (unsigned long) value
);
27595 newval
|= (newimm
& 0x800) << 15;
27596 newval
|= (newimm
& 0x700) << 4;
27597 newval
|= (newimm
& 0x0ff);
27599 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27600 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27603 case BFD_RELOC_ARM_SMC
:
27604 if (((unsigned long) value
) > 0xffff)
27605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27606 _("invalid smc expression"));
27607 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27608 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27609 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27612 case BFD_RELOC_ARM_HVC
:
27613 if (((unsigned long) value
) > 0xffff)
27614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27615 _("invalid hvc expression"));
27616 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27617 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27618 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27621 case BFD_RELOC_ARM_SWI
:
27622 if (fixP
->tc_fix_data
!= 0)
27624 if (((unsigned long) value
) > 0xff)
27625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27626 _("invalid swi expression"));
27627 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27629 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27633 if (((unsigned long) value
) > 0x00ffffff)
27634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27635 _("invalid swi expression"));
27636 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27638 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27642 case BFD_RELOC_ARM_MULTI
:
27643 if (((unsigned long) value
) > 0xffff)
27644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27645 _("invalid expression in load/store multiple"));
27646 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27647 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27651 case BFD_RELOC_ARM_PCREL_CALL
:
27653 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27655 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27656 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27657 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27658 /* Flip the bl to blx. This is a simple flip
27659 bit here because we generate PCREL_CALL for
27660 unconditional bls. */
27662 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27663 newval
= newval
| 0x10000000;
27664 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27670 goto arm_branch_common
;
27672 case BFD_RELOC_ARM_PCREL_JUMP
:
27673 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27675 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27676 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27677 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27679 /* This would map to a bl<cond>, b<cond>,
27680 b<always> to a Thumb function. We
27681 need to force a relocation for this particular
27683 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27686 /* Fall through. */
27688 case BFD_RELOC_ARM_PLT32
:
27690 case BFD_RELOC_ARM_PCREL_BRANCH
:
27692 goto arm_branch_common
;
27694 case BFD_RELOC_ARM_PCREL_BLX
:
27697 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27699 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27700 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27701 && ARM_IS_FUNC (fixP
->fx_addsy
))
27703 /* Flip the blx to a bl and warn. */
27704 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27705 newval
= 0xeb000000;
27706 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27707 _("blx to '%s' an ARM ISA state function changed to bl"),
27709 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27715 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27716 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27720 /* We are going to store value (shifted right by two) in the
27721 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27722 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27726 _("misaligned branch destination"));
27727 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27728 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27731 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27733 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27734 newval
|= (value
>> 2) & 0x00ffffff;
27735 /* Set the H bit on BLX instructions. */
27739 newval
|= 0x01000000;
27741 newval
&= ~0x01000000;
27743 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27747 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27748 /* CBZ can only branch forward. */
27750 /* Attempts to use CBZ to branch to the next instruction
27751 (which, strictly speaking, are prohibited) will be turned into
27754 FIXME: It may be better to remove the instruction completely and
27755 perform relaxation. */
27758 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27759 newval
= 0xbf00; /* NOP encoding T1 */
27760 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27767 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27769 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27770 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27771 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27776 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27777 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27780 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27782 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27783 newval
|= (value
& 0x1ff) >> 1;
27784 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27788 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27789 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27792 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27794 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27795 newval
|= (value
& 0xfff) >> 1;
27796 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27800 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27802 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27803 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27804 && ARM_IS_FUNC (fixP
->fx_addsy
)
27805 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27807 /* Force a relocation for a branch 20 bits wide. */
27810 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27812 _("conditional branch out of range"));
27814 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27817 addressT S
, J1
, J2
, lo
, hi
;
27819 S
= (value
& 0x00100000) >> 20;
27820 J2
= (value
& 0x00080000) >> 19;
27821 J1
= (value
& 0x00040000) >> 18;
27822 hi
= (value
& 0x0003f000) >> 12;
27823 lo
= (value
& 0x00000ffe) >> 1;
27825 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27826 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27827 newval
|= (S
<< 10) | hi
;
27828 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27829 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27830 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27834 case BFD_RELOC_THUMB_PCREL_BLX
:
27835 /* If there is a blx from a thumb state function to
27836 another thumb function flip this to a bl and warn
27840 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27841 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27842 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27844 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27845 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27846 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27848 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27849 newval
= newval
| 0x1000;
27850 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27851 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27856 goto thumb_bl_common
;
27858 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27859 /* A bl from Thumb state ISA to an internal ARM state function
27860 is converted to a blx. */
27862 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27863 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27864 && ARM_IS_FUNC (fixP
->fx_addsy
)
27865 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27867 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27868 newval
= newval
& ~0x1000;
27869 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27870 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27876 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27877 /* For a BLX instruction, make sure that the relocation is rounded up
27878 to a word boundary. This follows the semantics of the instruction
27879 which specifies that bit 1 of the target address will come from bit
27880 1 of the base address. */
27881 value
= (value
+ 3) & ~ 3;
27884 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27885 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27886 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27889 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27891 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27893 else if ((value
& ~0x1ffffff)
27894 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27896 _("Thumb2 branch out of range"));
27899 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27900 encode_thumb2_b_bl_offset (buf
, value
);
27904 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27905 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27908 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27909 encode_thumb2_b_bl_offset (buf
, value
);
27914 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27919 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27920 md_number_to_chars (buf
, value
, 2);
27924 case BFD_RELOC_ARM_TLS_CALL
:
27925 case BFD_RELOC_ARM_THM_TLS_CALL
:
27926 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27927 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27928 case BFD_RELOC_ARM_TLS_GOTDESC
:
27929 case BFD_RELOC_ARM_TLS_GD32
:
27930 case BFD_RELOC_ARM_TLS_LE32
:
27931 case BFD_RELOC_ARM_TLS_IE32
:
27932 case BFD_RELOC_ARM_TLS_LDM32
:
27933 case BFD_RELOC_ARM_TLS_LDO32
:
27934 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27937 /* Same handling as above, but with the arm_fdpic guard. */
27938 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27939 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27940 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27943 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27948 _("Relocation supported only in FDPIC mode"));
27952 case BFD_RELOC_ARM_GOT32
:
27953 case BFD_RELOC_ARM_GOTOFF
:
27956 case BFD_RELOC_ARM_GOT_PREL
:
27957 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27958 md_number_to_chars (buf
, value
, 4);
27961 case BFD_RELOC_ARM_TARGET2
:
27962 /* TARGET2 is not partial-inplace, so we need to write the
27963 addend here for REL targets, because it won't be written out
27964 during reloc processing later. */
27965 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27966 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27969 /* Relocations for FDPIC. */
27970 case BFD_RELOC_ARM_GOTFUNCDESC
:
27971 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27972 case BFD_RELOC_ARM_FUNCDESC
:
27975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27976 md_number_to_chars (buf
, 0, 4);
27980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27981 _("Relocation supported only in FDPIC mode"));
27986 case BFD_RELOC_RVA
:
27988 case BFD_RELOC_ARM_TARGET1
:
27989 case BFD_RELOC_ARM_ROSEGREL32
:
27990 case BFD_RELOC_ARM_SBREL32
:
27991 case BFD_RELOC_32_PCREL
:
27993 case BFD_RELOC_32_SECREL
:
27995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27997 /* For WinCE we only do this for pcrel fixups. */
27998 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28000 md_number_to_chars (buf
, value
, 4);
28004 case BFD_RELOC_ARM_PREL31
:
28005 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28007 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28008 if ((value
^ (value
>> 1)) & 0x40000000)
28010 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28011 _("rel31 relocation overflow"));
28013 newval
|= value
& 0x7fffffff;
28014 md_number_to_chars (buf
, newval
, 4);
28019 case BFD_RELOC_ARM_CP_OFF_IMM
:
28020 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28021 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28022 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28023 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28025 newval
= get_thumb32_insn (buf
);
28026 if ((newval
& 0x0f200f00) == 0x0d000900)
28028 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28029 has permitted values that are multiples of 2, in the range 0
28031 if (value
< -510 || value
> 510 || (value
& 1))
28032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28033 _("co-processor offset out of range"));
28035 else if ((newval
& 0xfe001f80) == 0xec000f80)
28037 if (value
< -511 || value
> 512 || (value
& 3))
28038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28039 _("co-processor offset out of range"));
28041 else if (value
< -1023 || value
> 1023 || (value
& 3))
28042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28043 _("co-processor offset out of range"));
28048 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28049 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28050 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28052 newval
= get_thumb32_insn (buf
);
28055 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28056 newval
&= 0xffffff80;
28058 newval
&= 0xffffff00;
28062 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28063 newval
&= 0xff7fff80;
28065 newval
&= 0xff7fff00;
28066 if ((newval
& 0x0f200f00) == 0x0d000900)
28068 /* This is a fp16 vstr/vldr.
28070 It requires the immediate offset in the instruction is shifted
28071 left by 1 to be a half-word offset.
28073 Here, left shift by 1 first, and later right shift by 2
28074 should get the right offset. */
28077 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28079 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28080 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28081 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28083 put_thumb32_insn (buf
, newval
);
28086 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28087 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28088 if (value
< -255 || value
> 255)
28089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28090 _("co-processor offset out of range"));
28092 goto cp_off_common
;
28094 case BFD_RELOC_ARM_THUMB_OFFSET
:
28095 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28096 /* Exactly what ranges, and where the offset is inserted depends
28097 on the type of instruction, we can establish this from the
28099 switch (newval
>> 12)
28101 case 4: /* PC load. */
28102 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28103 forced to zero for these loads; md_pcrel_from has already
28104 compensated for this. */
28106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28107 _("invalid offset, target not word aligned (0x%08lX)"),
28108 (((unsigned long) fixP
->fx_frag
->fr_address
28109 + (unsigned long) fixP
->fx_where
) & ~3)
28110 + (unsigned long) value
);
28112 if (value
& ~0x3fc)
28113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28114 _("invalid offset, value too big (0x%08lX)"),
28117 newval
|= value
>> 2;
28120 case 9: /* SP load/store. */
28121 if (value
& ~0x3fc)
28122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28123 _("invalid offset, value too big (0x%08lX)"),
28125 newval
|= value
>> 2;
28128 case 6: /* Word load/store. */
28130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28131 _("invalid offset, value too big (0x%08lX)"),
28133 newval
|= value
<< 4; /* 6 - 2. */
28136 case 7: /* Byte load/store. */
28138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28139 _("invalid offset, value too big (0x%08lX)"),
28141 newval
|= value
<< 6;
28144 case 8: /* Halfword load/store. */
28146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28147 _("invalid offset, value too big (0x%08lX)"),
28149 newval
|= value
<< 5; /* 6 - 1. */
28153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28154 "Unable to process relocation for thumb opcode: %lx",
28155 (unsigned long) newval
);
28158 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28161 case BFD_RELOC_ARM_THUMB_ADD
:
28162 /* This is a complicated relocation, since we use it for all of
28163 the following immediate relocations:
28167 9bit ADD/SUB SP word-aligned
28168 10bit ADD PC/SP word-aligned
28170 The type of instruction being processed is encoded in the
28177 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28179 int rd
= (newval
>> 4) & 0xf;
28180 int rs
= newval
& 0xf;
28181 int subtract
= !!(newval
& 0x8000);
28183 /* Check for HI regs, only very restricted cases allowed:
28184 Adjusting SP, and using PC or SP to get an address. */
28185 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28186 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28188 _("invalid Hi register with immediate"));
28190 /* If value is negative, choose the opposite instruction. */
28194 subtract
= !subtract
;
28196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28197 _("immediate value out of range"));
28202 if (value
& ~0x1fc)
28203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28204 _("invalid immediate for stack address calculation"));
28205 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28206 newval
|= value
>> 2;
28208 else if (rs
== REG_PC
|| rs
== REG_SP
)
28210 /* PR gas/18541. If the addition is for a defined symbol
28211 within range of an ADR instruction then accept it. */
28214 && fixP
->fx_addsy
!= NULL
)
28218 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28219 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28220 || S_IS_WEAK (fixP
->fx_addsy
))
28222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28223 _("address calculation needs a strongly defined nearby symbol"));
28227 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28229 /* Round up to the next 4-byte boundary. */
28234 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28239 _("symbol too far away"));
28249 if (subtract
|| value
& ~0x3fc)
28250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28251 _("invalid immediate for address calculation (value = 0x%08lX)"),
28252 (unsigned long) (subtract
? - value
: value
));
28253 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28255 newval
|= value
>> 2;
28260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28261 _("immediate value out of range"));
28262 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28263 newval
|= (rd
<< 8) | value
;
28268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28269 _("immediate value out of range"));
28270 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28271 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28274 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28277 case BFD_RELOC_ARM_THUMB_IMM
:
28278 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28279 if (value
< 0 || value
> 255)
28280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28281 _("invalid immediate: %ld is out of range"),
28284 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28287 case BFD_RELOC_ARM_THUMB_SHIFT
:
28288 /* 5bit shift value (0..32). LSL cannot take 32. */
28289 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28290 temp
= newval
& 0xf800;
28291 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28293 _("invalid shift value: %ld"), (long) value
);
28294 /* Shifts of zero must be encoded as LSL. */
28296 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28297 /* Shifts of 32 are encoded as zero. */
28298 else if (value
== 32)
28300 newval
|= value
<< 6;
28301 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28304 case BFD_RELOC_VTABLE_INHERIT
:
28305 case BFD_RELOC_VTABLE_ENTRY
:
28309 case BFD_RELOC_ARM_MOVW
:
28310 case BFD_RELOC_ARM_MOVT
:
28311 case BFD_RELOC_ARM_THUMB_MOVW
:
28312 case BFD_RELOC_ARM_THUMB_MOVT
:
28313 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28315 /* REL format relocations are limited to a 16-bit addend. */
28316 if (!fixP
->fx_done
)
28318 if (value
< -0x8000 || value
> 0x7fff)
28319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28320 _("offset out of range"));
28322 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28323 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28328 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28329 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28331 newval
= get_thumb32_insn (buf
);
28332 newval
&= 0xfbf08f00;
28333 newval
|= (value
& 0xf000) << 4;
28334 newval
|= (value
& 0x0800) << 15;
28335 newval
|= (value
& 0x0700) << 4;
28336 newval
|= (value
& 0x00ff);
28337 put_thumb32_insn (buf
, newval
);
28341 newval
= md_chars_to_number (buf
, 4);
28342 newval
&= 0xfff0f000;
28343 newval
|= value
& 0x0fff;
28344 newval
|= (value
& 0xf000) << 4;
28345 md_number_to_chars (buf
, newval
, 4);
28350 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28351 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28352 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28353 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28354 gas_assert (!fixP
->fx_done
);
28357 bfd_boolean is_mov
;
28358 bfd_vma encoded_addend
= value
;
28360 /* Check that addend can be encoded in instruction. */
28361 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28363 _("the offset 0x%08lX is not representable"),
28364 (unsigned long) encoded_addend
);
28366 /* Extract the instruction. */
28367 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28368 is_mov
= (insn
& 0xf800) == 0x2000;
28373 if (!seg
->use_rela_p
)
28374 insn
|= encoded_addend
;
28380 /* Extract the instruction. */
28381 /* Encoding is the following
28386 /* The following conditions must be true :
28391 rd
= (insn
>> 4) & 0xf;
28393 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28395 _("Unable to process relocation for thumb opcode: %lx"),
28396 (unsigned long) insn
);
28398 /* Encode as ADD immediate8 thumb 1 code. */
28399 insn
= 0x3000 | (rd
<< 8);
28401 /* Place the encoded addend into the first 8 bits of the
28403 if (!seg
->use_rela_p
)
28404 insn
|= encoded_addend
;
28407 /* Update the instruction. */
28408 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28412 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28413 case BFD_RELOC_ARM_ALU_PC_G0
:
28414 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28415 case BFD_RELOC_ARM_ALU_PC_G1
:
28416 case BFD_RELOC_ARM_ALU_PC_G2
:
28417 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28418 case BFD_RELOC_ARM_ALU_SB_G0
:
28419 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28420 case BFD_RELOC_ARM_ALU_SB_G1
:
28421 case BFD_RELOC_ARM_ALU_SB_G2
:
28422 gas_assert (!fixP
->fx_done
);
28423 if (!seg
->use_rela_p
)
28426 bfd_vma encoded_addend
;
28427 bfd_vma addend_abs
= llabs (value
);
28429 /* Check that the absolute value of the addend can be
28430 expressed as an 8-bit constant plus a rotation. */
28431 encoded_addend
= encode_arm_immediate (addend_abs
);
28432 if (encoded_addend
== (unsigned int) FAIL
)
28433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28434 _("the offset 0x%08lX is not representable"),
28435 (unsigned long) addend_abs
);
28437 /* Extract the instruction. */
28438 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28440 /* If the addend is positive, use an ADD instruction.
28441 Otherwise use a SUB. Take care not to destroy the S bit. */
28442 insn
&= 0xff1fffff;
28448 /* Place the encoded addend into the first 12 bits of the
28450 insn
&= 0xfffff000;
28451 insn
|= encoded_addend
;
28453 /* Update the instruction. */
28454 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28458 case BFD_RELOC_ARM_LDR_PC_G0
:
28459 case BFD_RELOC_ARM_LDR_PC_G1
:
28460 case BFD_RELOC_ARM_LDR_PC_G2
:
28461 case BFD_RELOC_ARM_LDR_SB_G0
:
28462 case BFD_RELOC_ARM_LDR_SB_G1
:
28463 case BFD_RELOC_ARM_LDR_SB_G2
:
28464 gas_assert (!fixP
->fx_done
);
28465 if (!seg
->use_rela_p
)
28468 bfd_vma addend_abs
= llabs (value
);
28470 /* Check that the absolute value of the addend can be
28471 encoded in 12 bits. */
28472 if (addend_abs
>= 0x1000)
28473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28474 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28475 (unsigned long) addend_abs
);
28477 /* Extract the instruction. */
28478 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28480 /* If the addend is negative, clear bit 23 of the instruction.
28481 Otherwise set it. */
28483 insn
&= ~(1 << 23);
28487 /* Place the absolute value of the addend into the first 12 bits
28488 of the instruction. */
28489 insn
&= 0xfffff000;
28490 insn
|= addend_abs
;
28492 /* Update the instruction. */
28493 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28497 case BFD_RELOC_ARM_LDRS_PC_G0
:
28498 case BFD_RELOC_ARM_LDRS_PC_G1
:
28499 case BFD_RELOC_ARM_LDRS_PC_G2
:
28500 case BFD_RELOC_ARM_LDRS_SB_G0
:
28501 case BFD_RELOC_ARM_LDRS_SB_G1
:
28502 case BFD_RELOC_ARM_LDRS_SB_G2
:
28503 gas_assert (!fixP
->fx_done
);
28504 if (!seg
->use_rela_p
)
28507 bfd_vma addend_abs
= llabs (value
);
28509 /* Check that the absolute value of the addend can be
28510 encoded in 8 bits. */
28511 if (addend_abs
>= 0x100)
28512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28513 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28514 (unsigned long) addend_abs
);
28516 /* Extract the instruction. */
28517 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28519 /* If the addend is negative, clear bit 23 of the instruction.
28520 Otherwise set it. */
28522 insn
&= ~(1 << 23);
28526 /* Place the first four bits of the absolute value of the addend
28527 into the first 4 bits of the instruction, and the remaining
28528 four into bits 8 .. 11. */
28529 insn
&= 0xfffff0f0;
28530 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28532 /* Update the instruction. */
28533 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28537 case BFD_RELOC_ARM_LDC_PC_G0
:
28538 case BFD_RELOC_ARM_LDC_PC_G1
:
28539 case BFD_RELOC_ARM_LDC_PC_G2
:
28540 case BFD_RELOC_ARM_LDC_SB_G0
:
28541 case BFD_RELOC_ARM_LDC_SB_G1
:
28542 case BFD_RELOC_ARM_LDC_SB_G2
:
28543 gas_assert (!fixP
->fx_done
);
28544 if (!seg
->use_rela_p
)
28547 bfd_vma addend_abs
= llabs (value
);
28549 /* Check that the absolute value of the addend is a multiple of
28550 four and, when divided by four, fits in 8 bits. */
28551 if (addend_abs
& 0x3)
28552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28553 _("bad offset 0x%08lX (must be word-aligned)"),
28554 (unsigned long) addend_abs
);
28556 if ((addend_abs
>> 2) > 0xff)
28557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28558 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28559 (unsigned long) addend_abs
);
28561 /* Extract the instruction. */
28562 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28564 /* If the addend is negative, clear bit 23 of the instruction.
28565 Otherwise set it. */
28567 insn
&= ~(1 << 23);
28571 /* Place the addend (divided by four) into the first eight
28572 bits of the instruction. */
28573 insn
&= 0xfffffff0;
28574 insn
|= addend_abs
>> 2;
28576 /* Update the instruction. */
28577 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28581 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28583 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28584 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28585 && ARM_IS_FUNC (fixP
->fx_addsy
)
28586 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28588 /* Force a relocation for a branch 5 bits wide. */
28591 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28597 addressT boff
= value
>> 1;
28599 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28600 newval
|= (boff
<< 7);
28601 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28605 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28607 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28608 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28609 && ARM_IS_FUNC (fixP
->fx_addsy
)
28610 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28614 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28616 _("branch out of range"));
28618 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28620 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28622 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28623 addressT diff
= value
- boff
;
28627 newval
|= 1 << 1; /* T bit. */
28629 else if (diff
!= 2)
28631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28632 _("out of range label-relative fixup value"));
28634 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28638 case BFD_RELOC_ARM_THUMB_BF17
:
28640 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28641 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28642 && ARM_IS_FUNC (fixP
->fx_addsy
)
28643 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28645 /* Force a relocation for a branch 17 bits wide. */
28649 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28653 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28656 addressT immA
, immB
, immC
;
28658 immA
= (value
& 0x0001f000) >> 12;
28659 immB
= (value
& 0x00000ffc) >> 2;
28660 immC
= (value
& 0x00000002) >> 1;
28662 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28663 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28665 newval2
|= (immC
<< 11) | (immB
<< 1);
28666 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28667 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28671 case BFD_RELOC_ARM_THUMB_BF19
:
28673 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28674 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28675 && ARM_IS_FUNC (fixP
->fx_addsy
)
28676 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28678 /* Force a relocation for a branch 19 bits wide. */
28682 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28686 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28689 addressT immA
, immB
, immC
;
28691 immA
= (value
& 0x0007f000) >> 12;
28692 immB
= (value
& 0x00000ffc) >> 2;
28693 immC
= (value
& 0x00000002) >> 1;
28695 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28696 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28698 newval2
|= (immC
<< 11) | (immB
<< 1);
28699 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28700 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28704 case BFD_RELOC_ARM_THUMB_BF13
:
28706 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28707 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28708 && ARM_IS_FUNC (fixP
->fx_addsy
)
28709 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28711 /* Force a relocation for a branch 13 bits wide. */
28715 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28719 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28722 addressT immA
, immB
, immC
;
28724 immA
= (value
& 0x00001000) >> 12;
28725 immB
= (value
& 0x00000ffc) >> 2;
28726 immC
= (value
& 0x00000002) >> 1;
28728 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28729 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28731 newval2
|= (immC
<< 11) | (immB
<< 1);
28732 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28733 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28737 case BFD_RELOC_ARM_THUMB_LOOP12
:
28739 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28740 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28741 && ARM_IS_FUNC (fixP
->fx_addsy
)
28742 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28744 /* Force a relocation for a branch 12 bits wide. */
28748 bfd_vma insn
= get_thumb32_insn (buf
);
28749 /* le lr, <label>, le <label> or letp lr, <label> */
28750 if (((insn
& 0xffffffff) == 0xf00fc001)
28751 || ((insn
& 0xffffffff) == 0xf02fc001)
28752 || ((insn
& 0xffffffff) == 0xf01fc001))
28755 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28758 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28760 addressT imml
, immh
;
28762 immh
= (value
& 0x00000ffc) >> 2;
28763 imml
= (value
& 0x00000002) >> 1;
28765 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28766 newval
|= (imml
<< 11) | (immh
<< 1);
28767 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28771 case BFD_RELOC_ARM_V4BX
:
28772 /* This will need to go in the object file. */
28776 case BFD_RELOC_UNUSED
:
28778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28779 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28783 /* Translate internal representation of relocation info to BFD target
28787 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28790 bfd_reloc_code_real_type code
;
28792 reloc
= XNEW (arelent
);
28794 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28795 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28796 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28798 if (fixp
->fx_pcrel
)
28800 if (section
->use_rela_p
)
28801 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28803 fixp
->fx_offset
= reloc
->address
;
28805 reloc
->addend
= fixp
->fx_offset
;
28807 switch (fixp
->fx_r_type
)
28810 if (fixp
->fx_pcrel
)
28812 code
= BFD_RELOC_8_PCREL
;
28815 /* Fall through. */
28818 if (fixp
->fx_pcrel
)
28820 code
= BFD_RELOC_16_PCREL
;
28823 /* Fall through. */
28826 if (fixp
->fx_pcrel
)
28828 code
= BFD_RELOC_32_PCREL
;
28831 /* Fall through. */
28833 case BFD_RELOC_ARM_MOVW
:
28834 if (fixp
->fx_pcrel
)
28836 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28839 /* Fall through. */
28841 case BFD_RELOC_ARM_MOVT
:
28842 if (fixp
->fx_pcrel
)
28844 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28847 /* Fall through. */
28849 case BFD_RELOC_ARM_THUMB_MOVW
:
28850 if (fixp
->fx_pcrel
)
28852 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28855 /* Fall through. */
28857 case BFD_RELOC_ARM_THUMB_MOVT
:
28858 if (fixp
->fx_pcrel
)
28860 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28863 /* Fall through. */
28865 case BFD_RELOC_NONE
:
28866 case BFD_RELOC_ARM_PCREL_BRANCH
:
28867 case BFD_RELOC_ARM_PCREL_BLX
:
28868 case BFD_RELOC_RVA
:
28869 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28870 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28871 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28872 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28873 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28874 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28875 case BFD_RELOC_VTABLE_ENTRY
:
28876 case BFD_RELOC_VTABLE_INHERIT
:
28878 case BFD_RELOC_32_SECREL
:
28880 code
= fixp
->fx_r_type
;
28883 case BFD_RELOC_THUMB_PCREL_BLX
:
28885 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28886 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28889 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28892 case BFD_RELOC_ARM_LITERAL
:
28893 case BFD_RELOC_ARM_HWLITERAL
:
28894 /* If this is called then the a literal has
28895 been referenced across a section boundary. */
28896 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28897 _("literal referenced across section boundary"));
28901 case BFD_RELOC_ARM_TLS_CALL
:
28902 case BFD_RELOC_ARM_THM_TLS_CALL
:
28903 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28904 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28905 case BFD_RELOC_ARM_GOT32
:
28906 case BFD_RELOC_ARM_GOTOFF
:
28907 case BFD_RELOC_ARM_GOT_PREL
:
28908 case BFD_RELOC_ARM_PLT32
:
28909 case BFD_RELOC_ARM_TARGET1
:
28910 case BFD_RELOC_ARM_ROSEGREL32
:
28911 case BFD_RELOC_ARM_SBREL32
:
28912 case BFD_RELOC_ARM_PREL31
:
28913 case BFD_RELOC_ARM_TARGET2
:
28914 case BFD_RELOC_ARM_TLS_LDO32
:
28915 case BFD_RELOC_ARM_PCREL_CALL
:
28916 case BFD_RELOC_ARM_PCREL_JUMP
:
28917 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28918 case BFD_RELOC_ARM_ALU_PC_G0
:
28919 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28920 case BFD_RELOC_ARM_ALU_PC_G1
:
28921 case BFD_RELOC_ARM_ALU_PC_G2
:
28922 case BFD_RELOC_ARM_LDR_PC_G0
:
28923 case BFD_RELOC_ARM_LDR_PC_G1
:
28924 case BFD_RELOC_ARM_LDR_PC_G2
:
28925 case BFD_RELOC_ARM_LDRS_PC_G0
:
28926 case BFD_RELOC_ARM_LDRS_PC_G1
:
28927 case BFD_RELOC_ARM_LDRS_PC_G2
:
28928 case BFD_RELOC_ARM_LDC_PC_G0
:
28929 case BFD_RELOC_ARM_LDC_PC_G1
:
28930 case BFD_RELOC_ARM_LDC_PC_G2
:
28931 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28932 case BFD_RELOC_ARM_ALU_SB_G0
:
28933 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28934 case BFD_RELOC_ARM_ALU_SB_G1
:
28935 case BFD_RELOC_ARM_ALU_SB_G2
:
28936 case BFD_RELOC_ARM_LDR_SB_G0
:
28937 case BFD_RELOC_ARM_LDR_SB_G1
:
28938 case BFD_RELOC_ARM_LDR_SB_G2
:
28939 case BFD_RELOC_ARM_LDRS_SB_G0
:
28940 case BFD_RELOC_ARM_LDRS_SB_G1
:
28941 case BFD_RELOC_ARM_LDRS_SB_G2
:
28942 case BFD_RELOC_ARM_LDC_SB_G0
:
28943 case BFD_RELOC_ARM_LDC_SB_G1
:
28944 case BFD_RELOC_ARM_LDC_SB_G2
:
28945 case BFD_RELOC_ARM_V4BX
:
28946 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28947 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28948 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28949 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28950 case BFD_RELOC_ARM_GOTFUNCDESC
:
28951 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28952 case BFD_RELOC_ARM_FUNCDESC
:
28953 case BFD_RELOC_ARM_THUMB_BF17
:
28954 case BFD_RELOC_ARM_THUMB_BF19
:
28955 case BFD_RELOC_ARM_THUMB_BF13
:
28956 code
= fixp
->fx_r_type
;
28959 case BFD_RELOC_ARM_TLS_GOTDESC
:
28960 case BFD_RELOC_ARM_TLS_GD32
:
28961 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28962 case BFD_RELOC_ARM_TLS_LE32
:
28963 case BFD_RELOC_ARM_TLS_IE32
:
28964 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28965 case BFD_RELOC_ARM_TLS_LDM32
:
28966 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28967 /* BFD will include the symbol's address in the addend.
28968 But we don't want that, so subtract it out again here. */
28969 if (!S_IS_COMMON (fixp
->fx_addsy
))
28970 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28971 code
= fixp
->fx_r_type
;
28975 case BFD_RELOC_ARM_IMMEDIATE
:
28976 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28977 _("internal relocation (type: IMMEDIATE) not fixed up"));
28980 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28981 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28982 _("ADRL used for a symbol not defined in the same file"));
28985 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28986 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28987 case BFD_RELOC_ARM_THUMB_LOOP12
:
28988 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28989 _("%s used for a symbol not defined in the same file"),
28990 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28993 case BFD_RELOC_ARM_OFFSET_IMM
:
28994 if (section
->use_rela_p
)
28996 code
= fixp
->fx_r_type
;
29000 if (fixp
->fx_addsy
!= NULL
29001 && !S_IS_DEFINED (fixp
->fx_addsy
)
29002 && S_IS_LOCAL (fixp
->fx_addsy
))
29004 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29005 _("undefined local label `%s'"),
29006 S_GET_NAME (fixp
->fx_addsy
));
29010 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29011 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29018 switch (fixp
->fx_r_type
)
29020 case BFD_RELOC_NONE
: type
= "NONE"; break;
29021 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29022 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29023 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29024 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29025 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29026 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29027 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29028 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29029 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29030 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29031 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29032 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29033 default: type
= _("<unknown>"); break;
29035 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29036 _("cannot represent %s relocation in this object file format"),
29043 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29045 && fixp
->fx_addsy
== GOT_symbol
)
29047 code
= BFD_RELOC_ARM_GOTPC
;
29048 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29052 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29054 if (reloc
->howto
== NULL
)
29056 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29057 _("cannot represent %s relocation in this object file format"),
29058 bfd_get_reloc_code_name (code
));
29062 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29063 vtable entry to be used in the relocation's section offset. */
29064 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29065 reloc
->address
= fixp
->fx_offset
;
29070 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29073 cons_fix_new_arm (fragS
* frag
,
29077 bfd_reloc_code_real_type reloc
)
29082 FIXME: @@ Should look at CPU word size. */
29086 reloc
= BFD_RELOC_8
;
29089 reloc
= BFD_RELOC_16
;
29093 reloc
= BFD_RELOC_32
;
29096 reloc
= BFD_RELOC_64
;
29101 if (exp
->X_op
== O_secrel
)
29103 exp
->X_op
= O_symbol
;
29104 reloc
= BFD_RELOC_32_SECREL
;
29108 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29111 #if defined (OBJ_COFF)
29113 arm_validate_fix (fixS
* fixP
)
29115 /* If the destination of the branch is a defined symbol which does not have
29116 the THUMB_FUNC attribute, then we must be calling a function which has
29117 the (interfacearm) attribute. We look for the Thumb entry point to that
29118 function and change the branch to refer to that function instead. */
29119 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29120 && fixP
->fx_addsy
!= NULL
29121 && S_IS_DEFINED (fixP
->fx_addsy
)
29122 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29124 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29131 arm_force_relocation (struct fix
* fixp
)
29133 #if defined (OBJ_COFF) && defined (TE_PE)
29134 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29138 /* In case we have a call or a branch to a function in ARM ISA mode from
29139 a thumb function or vice-versa force the relocation. These relocations
29140 are cleared off for some cores that might have blx and simple transformations
29144 switch (fixp
->fx_r_type
)
29146 case BFD_RELOC_ARM_PCREL_JUMP
:
29147 case BFD_RELOC_ARM_PCREL_CALL
:
29148 case BFD_RELOC_THUMB_PCREL_BLX
:
29149 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29153 case BFD_RELOC_ARM_PCREL_BLX
:
29154 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29155 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29156 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29157 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29166 /* Resolve these relocations even if the symbol is extern or weak.
29167 Technically this is probably wrong due to symbol preemption.
29168 In practice these relocations do not have enough range to be useful
29169 at dynamic link time, and some code (e.g. in the Linux kernel)
29170 expects these references to be resolved. */
29171 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29172 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29173 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29174 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29175 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29176 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29177 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29178 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29179 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29180 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29181 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29182 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29183 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29184 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29187 /* Always leave these relocations for the linker. */
29188 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29189 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29190 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29193 /* Always generate relocations against function symbols. */
29194 if (fixp
->fx_r_type
== BFD_RELOC_32
29196 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29199 return generic_force_reloc (fixp
);
29202 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29203 /* Relocations against function names must be left unadjusted,
29204 so that the linker can use this information to generate interworking
29205 stubs. The MIPS version of this function
29206 also prevents relocations that are mips-16 specific, but I do not
29207 know why it does this.
29210 There is one other problem that ought to be addressed here, but
29211 which currently is not: Taking the address of a label (rather
29212 than a function) and then later jumping to that address. Such
29213 addresses also ought to have their bottom bit set (assuming that
29214 they reside in Thumb code), but at the moment they will not. */
29217 arm_fix_adjustable (fixS
* fixP
)
29219 if (fixP
->fx_addsy
== NULL
)
29222 /* Preserve relocations against symbols with function type. */
29223 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29226 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29227 && fixP
->fx_subsy
== NULL
)
29230 /* We need the symbol name for the VTABLE entries. */
29231 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29232 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29235 /* Don't allow symbols to be discarded on GOT related relocs. */
29236 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29237 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29238 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29239 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29240 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29241 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29242 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29243 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29244 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29245 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29246 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29247 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29248 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29249 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29250 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29251 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29252 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29255 /* Similarly for group relocations. */
29256 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29257 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29258 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29261 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29262 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29263 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29264 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29265 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29266 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29267 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29268 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29269 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29272 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29273 offsets, so keep these symbols. */
29274 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29275 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29280 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29284 elf32_arm_target_format (void)
29287 return (target_big_endian
29288 ? "elf32-bigarm-symbian"
29289 : "elf32-littlearm-symbian");
29290 #elif defined (TE_VXWORKS)
29291 return (target_big_endian
29292 ? "elf32-bigarm-vxworks"
29293 : "elf32-littlearm-vxworks");
29294 #elif defined (TE_NACL)
29295 return (target_big_endian
29296 ? "elf32-bigarm-nacl"
29297 : "elf32-littlearm-nacl");
29301 if (target_big_endian
)
29302 return "elf32-bigarm-fdpic";
29304 return "elf32-littlearm-fdpic";
29308 if (target_big_endian
)
29309 return "elf32-bigarm";
29311 return "elf32-littlearm";
29317 armelf_frob_symbol (symbolS
* symp
,
29320 elf_frob_symbol (symp
, puntp
);
29324 /* MD interface: Finalization. */
29329 literal_pool
* pool
;
29331 /* Ensure that all the predication blocks are properly closed. */
29332 check_pred_blocks_finished ();
29334 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29336 /* Put it at the end of the relevant section. */
29337 subseg_set (pool
->section
, pool
->sub_section
);
29339 arm_elf_change_section ();
29346 /* Remove any excess mapping symbols generated for alignment frags in
29347 SEC. We may have created a mapping symbol before a zero byte
29348 alignment; remove it if there's a mapping symbol after the
29351 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29352 void *dummy ATTRIBUTE_UNUSED
)
29354 segment_info_type
*seginfo
= seg_info (sec
);
29357 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29360 for (fragp
= seginfo
->frchainP
->frch_root
;
29362 fragp
= fragp
->fr_next
)
29364 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29365 fragS
*next
= fragp
->fr_next
;
29367 /* Variable-sized frags have been converted to fixed size by
29368 this point. But if this was variable-sized to start with,
29369 there will be a fixed-size frag after it. So don't handle
29371 if (sym
== NULL
|| next
== NULL
)
29374 if (S_GET_VALUE (sym
) < next
->fr_address
)
29375 /* Not at the end of this frag. */
29377 know (S_GET_VALUE (sym
) == next
->fr_address
);
29381 if (next
->tc_frag_data
.first_map
!= NULL
)
29383 /* Next frag starts with a mapping symbol. Discard this
29385 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29389 if (next
->fr_next
== NULL
)
29391 /* This mapping symbol is at the end of the section. Discard
29393 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29394 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29398 /* As long as we have empty frags without any mapping symbols,
29400 /* If the next frag is non-empty and does not start with a
29401 mapping symbol, then this mapping symbol is required. */
29402 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29405 next
= next
->fr_next
;
29407 while (next
!= NULL
);
29412 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29416 arm_adjust_symtab (void)
29421 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29423 if (ARM_IS_THUMB (sym
))
29425 if (THUMB_IS_FUNC (sym
))
29427 /* Mark the symbol as a Thumb function. */
29428 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29429 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29430 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29432 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29433 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29435 as_bad (_("%s: unexpected function type: %d"),
29436 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29438 else switch (S_GET_STORAGE_CLASS (sym
))
29441 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29444 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29447 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29455 if (ARM_IS_INTERWORK (sym
))
29456 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29463 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29465 if (ARM_IS_THUMB (sym
))
29467 elf_symbol_type
* elf_sym
;
29469 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29470 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29472 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29473 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29475 /* If it's a .thumb_func, declare it as so,
29476 otherwise tag label as .code 16. */
29477 if (THUMB_IS_FUNC (sym
))
29478 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29479 ST_BRANCH_TO_THUMB
);
29480 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29481 elf_sym
->internal_elf_sym
.st_info
=
29482 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29487 /* Remove any overlapping mapping symbols generated by alignment frags. */
29488 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29489 /* Now do generic ELF adjustments. */
29490 elf_adjust_symtab ();
29494 /* MD interface: Initialization. */
29497 set_constant_flonums (void)
29501 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29502 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29506 /* Auto-select Thumb mode if it's the only available instruction set for the
29507 given architecture. */
29510 autoselect_thumb_from_cpu_variant (void)
29512 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29513 opcode_select (16);
29522 if ( (arm_ops_hsh
= hash_new ()) == NULL
29523 || (arm_cond_hsh
= hash_new ()) == NULL
29524 || (arm_vcond_hsh
= hash_new ()) == NULL
29525 || (arm_shift_hsh
= hash_new ()) == NULL
29526 || (arm_psr_hsh
= hash_new ()) == NULL
29527 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29528 || (arm_reg_hsh
= hash_new ()) == NULL
29529 || (arm_reloc_hsh
= hash_new ()) == NULL
29530 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29531 as_fatal (_("virtual memory exhausted"));
29533 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29534 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29535 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29536 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29537 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29538 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29539 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29540 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29541 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29542 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29543 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29544 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29545 (void *) (v7m_psrs
+ i
));
29546 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29547 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29549 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29551 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29552 (void *) (barrier_opt_names
+ i
));
29554 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29556 struct reloc_entry
* entry
= reloc_names
+ i
;
29558 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29559 /* This makes encode_branch() use the EABI versions of this relocation. */
29560 entry
->reloc
= BFD_RELOC_UNUSED
;
29562 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29566 set_constant_flonums ();
29568 /* Set the cpu variant based on the command-line options. We prefer
29569 -mcpu= over -march= if both are set (as for GCC); and we prefer
29570 -mfpu= over any other way of setting the floating point unit.
29571 Use of legacy options with new options are faulted. */
29574 if (mcpu_cpu_opt
|| march_cpu_opt
)
29575 as_bad (_("use of old and new-style options to set CPU type"));
29577 selected_arch
= *legacy_cpu
;
29579 else if (mcpu_cpu_opt
)
29581 selected_arch
= *mcpu_cpu_opt
;
29582 selected_ext
= *mcpu_ext_opt
;
29584 else if (march_cpu_opt
)
29586 selected_arch
= *march_cpu_opt
;
29587 selected_ext
= *march_ext_opt
;
29589 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29594 as_bad (_("use of old and new-style options to set FPU type"));
29596 selected_fpu
= *legacy_fpu
;
29599 selected_fpu
= *mfpu_opt
;
29602 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29603 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29604 /* Some environments specify a default FPU. If they don't, infer it
29605 from the processor. */
29607 selected_fpu
= *mcpu_fpu_opt
;
29608 else if (march_fpu_opt
)
29609 selected_fpu
= *march_fpu_opt
;
29611 selected_fpu
= fpu_default
;
29615 if (ARM_FEATURE_ZERO (selected_fpu
))
29617 if (!no_cpu_selected ())
29618 selected_fpu
= fpu_default
;
29620 selected_fpu
= fpu_arch_fpa
;
29624 if (ARM_FEATURE_ZERO (selected_arch
))
29626 selected_arch
= cpu_default
;
29627 selected_cpu
= selected_arch
;
29629 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29631 /* Autodection of feature mode: allow all features in cpu_variant but leave
29632 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29633 after all instruction have been processed and we can decide what CPU
29634 should be selected. */
29635 if (ARM_FEATURE_ZERO (selected_arch
))
29636 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29638 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29641 autoselect_thumb_from_cpu_variant ();
29643 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29645 #if defined OBJ_COFF || defined OBJ_ELF
29647 unsigned int flags
= 0;
29649 #if defined OBJ_ELF
29650 flags
= meabi_flags
;
29652 switch (meabi_flags
)
29654 case EF_ARM_EABI_UNKNOWN
:
29656 /* Set the flags in the private structure. */
29657 if (uses_apcs_26
) flags
|= F_APCS26
;
29658 if (support_interwork
) flags
|= F_INTERWORK
;
29659 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29660 if (pic_code
) flags
|= F_PIC
;
29661 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29662 flags
|= F_SOFT_FLOAT
;
29664 switch (mfloat_abi_opt
)
29666 case ARM_FLOAT_ABI_SOFT
:
29667 case ARM_FLOAT_ABI_SOFTFP
:
29668 flags
|= F_SOFT_FLOAT
;
29671 case ARM_FLOAT_ABI_HARD
:
29672 if (flags
& F_SOFT_FLOAT
)
29673 as_bad (_("hard-float conflicts with specified fpu"));
29677 /* Using pure-endian doubles (even if soft-float). */
29678 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29679 flags
|= F_VFP_FLOAT
;
29681 #if defined OBJ_ELF
29682 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29683 flags
|= EF_ARM_MAVERICK_FLOAT
;
29686 case EF_ARM_EABI_VER4
:
29687 case EF_ARM_EABI_VER5
:
29688 /* No additional flags to set. */
29695 bfd_set_private_flags (stdoutput
, flags
);
29697 /* We have run out flags in the COFF header to encode the
29698 status of ATPCS support, so instead we create a dummy,
29699 empty, debug section called .arm.atpcs. */
29704 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29708 bfd_set_section_flags
29709 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29710 bfd_set_section_size (stdoutput
, sec
, 0);
29711 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29717 /* Record the CPU type as well. */
29718 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29719 mach
= bfd_mach_arm_iWMMXt2
;
29720 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29721 mach
= bfd_mach_arm_iWMMXt
;
29722 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29723 mach
= bfd_mach_arm_XScale
;
29724 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29725 mach
= bfd_mach_arm_ep9312
;
29726 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29727 mach
= bfd_mach_arm_5TE
;
29728 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29730 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29731 mach
= bfd_mach_arm_5T
;
29733 mach
= bfd_mach_arm_5
;
29735 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29737 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29738 mach
= bfd_mach_arm_4T
;
29740 mach
= bfd_mach_arm_4
;
29742 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29743 mach
= bfd_mach_arm_3M
;
29744 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29745 mach
= bfd_mach_arm_3
;
29746 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29747 mach
= bfd_mach_arm_2a
;
29748 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29749 mach
= bfd_mach_arm_2
;
29751 mach
= bfd_mach_arm_unknown
;
29753 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29756 /* Command line processing. */
29759 Invocation line includes a switch not recognized by the base assembler.
29760 See if it's a processor-specific option.
29762 This routine is somewhat complicated by the need for backwards
29763 compatibility (since older releases of gcc can't be changed).
29764 The new options try to make the interface as compatible as
29767 New options (supported) are:
29769 -mcpu=<cpu name> Assemble for selected processor
29770 -march=<architecture name> Assemble for selected architecture
29771 -mfpu=<fpu architecture> Assemble for selected FPU.
29772 -EB/-mbig-endian Big-endian
29773 -EL/-mlittle-endian Little-endian
29774 -k Generate PIC code
29775 -mthumb Start in Thumb mode
29776 -mthumb-interwork Code supports ARM/Thumb interworking
29778 -m[no-]warn-deprecated Warn about deprecated features
29779 -m[no-]warn-syms Warn when symbols match instructions
29781 For now we will also provide support for:
29783 -mapcs-32 32-bit Program counter
29784 -mapcs-26 26-bit Program counter
29785 -macps-float Floats passed in FP registers
29786 -mapcs-reentrant Reentrant code
29788 (sometime these will probably be replaced with -mapcs=<list of options>
29789 and -matpcs=<list of options>)
29791 The remaining options are only supported for back-wards compatibility.
29792 Cpu variants, the arm part is optional:
29793 -m[arm]1 Currently not supported.
29794 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29795 -m[arm]3 Arm 3 processor
29796 -m[arm]6[xx], Arm 6 processors
29797 -m[arm]7[xx][t][[d]m] Arm 7 processors
29798 -m[arm]8[10] Arm 8 processors
29799 -m[arm]9[20][tdmi] Arm 9 processors
29800 -mstrongarm[110[0]] StrongARM processors
29801 -mxscale XScale processors
29802 -m[arm]v[2345[t[e]]] Arm architectures
29803 -mall All (except the ARM1)
29805 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29806 -mfpe-old (No float load/store multiples)
29807 -mvfpxd VFP Single precision
29809 -mno-fpu Disable all floating point instructions
29811 The following CPU names are recognized:
29812 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29813 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29814 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29815 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29816 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29817 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29818 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29822 const char * md_shortopts
= "m:k";
29824 #ifdef ARM_BI_ENDIAN
29825 #define OPTION_EB (OPTION_MD_BASE + 0)
29826 #define OPTION_EL (OPTION_MD_BASE + 1)
29828 #if TARGET_BYTES_BIG_ENDIAN
29829 #define OPTION_EB (OPTION_MD_BASE + 0)
29831 #define OPTION_EL (OPTION_MD_BASE + 1)
29834 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29835 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29837 struct option md_longopts
[] =
29840 {"EB", no_argument
, NULL
, OPTION_EB
},
29843 {"EL", no_argument
, NULL
, OPTION_EL
},
29845 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29847 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29849 {NULL
, no_argument
, NULL
, 0}
29852 size_t md_longopts_size
= sizeof (md_longopts
);
29854 struct arm_option_table
29856 const char * option
; /* Option name to match. */
29857 const char * help
; /* Help information. */
29858 int * var
; /* Variable to change. */
29859 int value
; /* What to change it to. */
29860 const char * deprecated
; /* If non-null, print this message. */
29863 struct arm_option_table arm_opts
[] =
29865 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29866 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29867 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29868 &support_interwork
, 1, NULL
},
29869 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29870 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29871 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29873 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29874 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29875 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29876 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29879 /* These are recognized by the assembler, but have no affect on code. */
29880 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29881 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29883 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29884 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29885 &warn_on_deprecated
, 0, NULL
},
29886 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29887 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29888 {NULL
, NULL
, NULL
, 0, NULL
}
29891 struct arm_legacy_option_table
29893 const char * option
; /* Option name to match. */
29894 const arm_feature_set
** var
; /* Variable to change. */
29895 const arm_feature_set value
; /* What to change it to. */
29896 const char * deprecated
; /* If non-null, print this message. */
29899 const struct arm_legacy_option_table arm_legacy_opts
[] =
29901 /* DON'T add any new processors to this list -- we want the whole list
29902 to go away... Add them to the processors table instead. */
29903 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29904 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29905 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29906 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29907 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29908 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29909 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29910 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29911 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29912 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29913 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29914 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29915 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29916 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29917 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29918 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29919 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29920 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29921 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29922 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29923 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29924 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29925 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29926 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29927 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29928 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29929 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29930 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29931 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29932 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29933 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29934 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29935 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29936 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29937 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29938 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29939 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29940 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29941 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29942 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29943 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29944 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29945 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29946 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29947 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29948 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29949 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29950 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29951 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29952 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29953 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29954 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29955 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29956 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29957 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29958 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29959 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29960 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29961 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29962 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29963 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29964 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29965 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29966 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29967 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29968 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29969 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29970 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29971 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29972 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29973 N_("use -mcpu=strongarm110")},
29974 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29975 N_("use -mcpu=strongarm1100")},
29976 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29977 N_("use -mcpu=strongarm1110")},
29978 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29979 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29980 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29982 /* Architecture variants -- don't add any more to this list either. */
29983 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29984 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29985 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29986 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29987 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29988 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29989 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29990 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29991 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29992 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29993 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29994 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29995 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29996 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29997 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29998 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29999 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30000 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30002 /* Floating point variants -- don't add any more to this list either. */
30003 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30004 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30005 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30006 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30007 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30009 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30012 struct arm_cpu_option_table
30016 const arm_feature_set value
;
30017 const arm_feature_set ext
;
30018 /* For some CPUs we assume an FPU unless the user explicitly sets
30020 const arm_feature_set default_fpu
;
30021 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30023 const char * canonical_name
;
30026 /* This list should, at a minimum, contain all the cpu names
30027 recognized by GCC. */
30028 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30030 static const struct arm_cpu_option_table arm_cpus
[] =
30032 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30035 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30038 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30041 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30044 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30047 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30050 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30053 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30056 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30059 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30062 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30065 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30068 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30071 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30074 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30077 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30080 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30083 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30086 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30089 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30092 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30095 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30098 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30101 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30104 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30107 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30110 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30113 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30116 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30119 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30122 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30125 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30128 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30131 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30134 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30137 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30140 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30143 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30146 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30149 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30152 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30155 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30158 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30161 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30164 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30167 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30171 /* For V5 or later processors we default to using VFP; but the user
30172 should really set the FPU type explicitly. */
30173 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30176 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30179 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30182 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30185 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30188 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30191 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30194 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30197 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30200 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30203 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30206 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30209 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30212 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30215 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30218 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30221 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30224 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30227 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30230 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30233 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30236 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30239 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30242 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30245 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30248 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30251 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30254 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30257 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30260 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30263 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30266 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30269 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30272 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30275 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30278 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30281 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30282 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30284 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30286 FPU_ARCH_NEON_VFP_V4
),
30287 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30288 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30289 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30290 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30291 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30292 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30293 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30295 FPU_ARCH_NEON_VFP_V4
),
30296 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30298 FPU_ARCH_NEON_VFP_V4
),
30299 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30301 FPU_ARCH_NEON_VFP_V4
),
30302 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30303 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30304 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30305 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30306 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30307 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30308 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30309 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30310 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30311 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30312 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30313 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30314 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30315 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30316 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30317 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30318 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30319 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30320 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30321 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30322 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30323 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30324 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30325 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30326 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30327 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30328 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30329 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30330 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30331 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30332 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30335 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30337 FPU_ARCH_VFP_V3D16
),
30338 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30339 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30341 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30342 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30343 FPU_ARCH_VFP_V3D16
),
30344 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30345 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30346 FPU_ARCH_VFP_V3D16
),
30347 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30348 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30349 FPU_ARCH_NEON_VFP_ARMV8
),
30350 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30351 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30353 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30356 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30359 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30362 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30365 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30368 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30371 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30374 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30375 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30376 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30377 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30378 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30379 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30380 /* ??? XSCALE is really an architecture. */
30381 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30385 /* ??? iwmmxt is not a processor. */
30386 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30389 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30392 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30397 ARM_CPU_OPT ("ep9312", "ARM920T",
30398 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30399 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30401 /* Marvell processors. */
30402 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30403 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30404 FPU_ARCH_VFP_V3D16
),
30405 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30406 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30407 FPU_ARCH_NEON_VFP_V4
),
30409 /* APM X-Gene family. */
30410 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30412 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30413 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30414 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30415 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30417 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30421 struct arm_ext_table
30425 const arm_feature_set merge
;
30426 const arm_feature_set clear
;
30429 struct arm_arch_option_table
30433 const arm_feature_set value
;
30434 const arm_feature_set default_fpu
;
30435 const struct arm_ext_table
* ext_table
;
30438 /* Used to add support for +E and +noE extension. */
30439 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30440 /* Used to add support for a +E extension. */
30441 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30442 /* Used to add support for a +noE extension. */
30443 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30445 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30446 ~0 & ~FPU_ENDIAN_PURE)
30448 static const struct arm_ext_table armv5te_ext_table
[] =
30450 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30451 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30454 static const struct arm_ext_table armv7_ext_table
[] =
30456 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30457 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30460 static const struct arm_ext_table armv7ve_ext_table
[] =
30462 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30463 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30464 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30465 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30466 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30467 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30468 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30470 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30471 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30473 /* Aliases for +simd. */
30474 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30476 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30477 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30478 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30480 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30483 static const struct arm_ext_table armv7a_ext_table
[] =
30485 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30486 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30487 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30488 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30489 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30490 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30491 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30493 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30494 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30496 /* Aliases for +simd. */
30497 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30498 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30500 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30501 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30503 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30504 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30505 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30508 static const struct arm_ext_table armv7r_ext_table
[] =
30510 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30511 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30512 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30513 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30514 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30515 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30516 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30517 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30518 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30521 static const struct arm_ext_table armv7em_ext_table
[] =
30523 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30524 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30525 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30526 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30527 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30528 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30529 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30532 static const struct arm_ext_table armv8a_ext_table
[] =
30534 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30535 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30536 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30537 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30539 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30540 should use the +simd option to turn on FP. */
30541 ARM_REMOVE ("fp", ALL_FP
),
30542 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30543 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30544 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30548 static const struct arm_ext_table armv81a_ext_table
[] =
30550 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30551 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30552 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30554 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30555 should use the +simd option to turn on FP. */
30556 ARM_REMOVE ("fp", ALL_FP
),
30557 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30558 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30559 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30562 static const struct arm_ext_table armv82a_ext_table
[] =
30564 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30565 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30566 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30567 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30568 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30569 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30571 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30572 should use the +simd option to turn on FP. */
30573 ARM_REMOVE ("fp", ALL_FP
),
30574 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30575 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30576 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30579 static const struct arm_ext_table armv84a_ext_table
[] =
30581 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30582 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30583 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30584 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30586 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30587 should use the +simd option to turn on FP. */
30588 ARM_REMOVE ("fp", ALL_FP
),
30589 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30590 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30591 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30594 static const struct arm_ext_table armv85a_ext_table
[] =
30596 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30597 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30598 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30599 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30601 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30602 should use the +simd option to turn on FP. */
30603 ARM_REMOVE ("fp", ALL_FP
),
30604 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30607 static const struct arm_ext_table armv8m_main_ext_table
[] =
30609 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30610 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30611 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30612 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30613 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30616 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30618 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30619 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30621 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30622 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30625 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30626 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30627 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30628 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30630 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30631 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30632 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30633 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30636 static const struct arm_ext_table armv8r_ext_table
[] =
30638 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30639 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30640 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30641 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30642 ARM_REMOVE ("fp", ALL_FP
),
30643 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30644 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30647 /* This list should, at a minimum, contain all the architecture names
30648 recognized by GCC. */
30649 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30650 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30651 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30653 static const struct arm_arch_option_table arm_archs
[] =
30655 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30656 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30657 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30658 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30659 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30660 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30661 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30662 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30663 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30664 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30665 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30666 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30667 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30668 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30669 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30670 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30671 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30672 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30673 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30674 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30675 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30676 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30677 kept to preserve existing behaviour. */
30678 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30679 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30680 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30681 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30682 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30683 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30684 kept to preserve existing behaviour. */
30685 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30686 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30687 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30688 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30689 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30690 /* The official spelling of the ARMv7 profile variants is the dashed form.
30691 Accept the non-dashed form for compatibility with old toolchains. */
30692 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30693 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30694 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30695 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30696 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30697 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30698 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30699 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30700 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30701 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30703 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30705 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30706 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30707 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30708 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30709 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30710 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30711 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30712 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30713 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30714 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30715 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30717 #undef ARM_ARCH_OPT
30719 /* ISA extensions in the co-processor and main instruction set space. */
30721 struct arm_option_extension_value_table
30725 const arm_feature_set merge_value
;
30726 const arm_feature_set clear_value
;
30727 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30728 indicates that an extension is available for all architectures while
30729 ARM_ANY marks an empty entry. */
30730 const arm_feature_set allowed_archs
[2];
30733 /* The following table must be in alphabetical order with a NULL last entry. */
30735 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30736 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30738 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30739 use the context sensitive approach using arm_ext_table's. */
30740 static const struct arm_option_extension_value_table arm_extensions
[] =
30742 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30743 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30744 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30745 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30746 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30747 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30748 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30750 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30751 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30752 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30753 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30754 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30755 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30756 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30758 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30759 | ARM_EXT2_FP16_FML
),
30760 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30761 | ARM_EXT2_FP16_FML
),
30763 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30764 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30765 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30766 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30767 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30768 Thumb divide instruction. Due to this having the same name as the
30769 previous entry, this will be ignored when doing command-line parsing and
30770 only considered by build attribute selection code. */
30771 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30772 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30773 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30774 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30775 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30776 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30777 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30778 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30779 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30780 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30781 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30782 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30783 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30784 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30785 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30786 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30787 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30788 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30789 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30790 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30791 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30793 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30794 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30795 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30796 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30797 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30798 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30799 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30800 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30802 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30803 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30804 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30805 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30806 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30807 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30808 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30809 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30811 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30812 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30813 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30814 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30815 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30819 /* ISA floating-point and Advanced SIMD extensions. */
30820 struct arm_option_fpu_value_table
30823 const arm_feature_set value
;
30826 /* This list should, at a minimum, contain all the fpu names
30827 recognized by GCC. */
30828 static const struct arm_option_fpu_value_table arm_fpus
[] =
30830 {"softfpa", FPU_NONE
},
30831 {"fpe", FPU_ARCH_FPE
},
30832 {"fpe2", FPU_ARCH_FPE
},
30833 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30834 {"fpa", FPU_ARCH_FPA
},
30835 {"fpa10", FPU_ARCH_FPA
},
30836 {"fpa11", FPU_ARCH_FPA
},
30837 {"arm7500fe", FPU_ARCH_FPA
},
30838 {"softvfp", FPU_ARCH_VFP
},
30839 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30840 {"vfp", FPU_ARCH_VFP_V2
},
30841 {"vfp9", FPU_ARCH_VFP_V2
},
30842 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30843 {"vfp10", FPU_ARCH_VFP_V2
},
30844 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30845 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30846 {"vfpv2", FPU_ARCH_VFP_V2
},
30847 {"vfpv3", FPU_ARCH_VFP_V3
},
30848 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30849 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30850 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30851 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30852 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30853 {"arm1020t", FPU_ARCH_VFP_V1
},
30854 {"arm1020e", FPU_ARCH_VFP_V2
},
30855 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30856 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30857 {"maverick", FPU_ARCH_MAVERICK
},
30858 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30859 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30860 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30861 {"vfpv4", FPU_ARCH_VFP_V4
},
30862 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30863 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30864 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30865 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30866 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30867 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30868 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30869 {"crypto-neon-fp-armv8",
30870 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30871 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30872 {"crypto-neon-fp-armv8.1",
30873 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30874 {NULL
, ARM_ARCH_NONE
}
30877 struct arm_option_value_table
30883 static const struct arm_option_value_table arm_float_abis
[] =
30885 {"hard", ARM_FLOAT_ABI_HARD
},
30886 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30887 {"soft", ARM_FLOAT_ABI_SOFT
},
30892 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30893 static const struct arm_option_value_table arm_eabis
[] =
30895 {"gnu", EF_ARM_EABI_UNKNOWN
},
30896 {"4", EF_ARM_EABI_VER4
},
30897 {"5", EF_ARM_EABI_VER5
},
30902 struct arm_long_option_table
30904 const char * option
; /* Substring to match. */
30905 const char * help
; /* Help information. */
30906 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30907 const char * deprecated
; /* If non-null, print this message. */
30911 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30912 arm_feature_set
*ext_set
,
30913 const struct arm_ext_table
*ext_table
)
30915 /* We insist on extensions being specified in alphabetical order, and with
30916 extensions being added before being removed. We achieve this by having
30917 the global ARM_EXTENSIONS table in alphabetical order, and using the
30918 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30919 or removing it (0) and only allowing it to change in the order
30921 const struct arm_option_extension_value_table
* opt
= NULL
;
30922 const arm_feature_set arm_any
= ARM_ANY
;
30923 int adding_value
= -1;
30925 while (str
!= NULL
&& *str
!= 0)
30932 as_bad (_("invalid architectural extension"));
30937 ext
= strchr (str
, '+');
30942 len
= strlen (str
);
30944 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30946 if (adding_value
!= 0)
30949 opt
= arm_extensions
;
30957 if (adding_value
== -1)
30960 opt
= arm_extensions
;
30962 else if (adding_value
!= 1)
30964 as_bad (_("must specify extensions to add before specifying "
30965 "those to remove"));
30972 as_bad (_("missing architectural extension"));
30976 gas_assert (adding_value
!= -1);
30977 gas_assert (opt
!= NULL
);
30979 if (ext_table
!= NULL
)
30981 const struct arm_ext_table
* ext_opt
= ext_table
;
30982 bfd_boolean found
= FALSE
;
30983 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30984 if (ext_opt
->name_len
== len
30985 && strncmp (ext_opt
->name
, str
, len
) == 0)
30989 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30990 /* TODO: Option not supported. When we remove the
30991 legacy table this case should error out. */
30994 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30998 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30999 /* TODO: Option not supported. When we remove the
31000 legacy table this case should error out. */
31002 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31014 /* Scan over the options table trying to find an exact match. */
31015 for (; opt
->name
!= NULL
; opt
++)
31016 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31018 int i
, nb_allowed_archs
=
31019 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31020 /* Check we can apply the extension to this architecture. */
31021 for (i
= 0; i
< nb_allowed_archs
; i
++)
31024 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31026 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31029 if (i
== nb_allowed_archs
)
31031 as_bad (_("extension does not apply to the base architecture"));
31035 /* Add or remove the extension. */
31037 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31039 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31041 /* Allowing Thumb division instructions for ARMv7 in autodetection
31042 rely on this break so that duplicate extensions (extensions
31043 with the same name as a previous extension in the list) are not
31044 considered for command-line parsing. */
31048 if (opt
->name
== NULL
)
31050 /* Did we fail to find an extension because it wasn't specified in
31051 alphabetical order, or because it does not exist? */
31053 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31054 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31057 if (opt
->name
== NULL
)
31058 as_bad (_("unknown architectural extension `%s'"), str
);
31060 as_bad (_("architectural extensions must be specified in "
31061 "alphabetical order"));
31067 /* We should skip the extension we've just matched the next time
31079 arm_parse_cpu (const char *str
)
31081 const struct arm_cpu_option_table
*opt
;
31082 const char *ext
= strchr (str
, '+');
31088 len
= strlen (str
);
31092 as_bad (_("missing cpu name `%s'"), str
);
31096 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31097 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31099 mcpu_cpu_opt
= &opt
->value
;
31100 if (mcpu_ext_opt
== NULL
)
31101 mcpu_ext_opt
= XNEW (arm_feature_set
);
31102 *mcpu_ext_opt
= opt
->ext
;
31103 mcpu_fpu_opt
= &opt
->default_fpu
;
31104 if (opt
->canonical_name
)
31106 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31107 strcpy (selected_cpu_name
, opt
->canonical_name
);
31113 if (len
>= sizeof selected_cpu_name
)
31114 len
= (sizeof selected_cpu_name
) - 1;
31116 for (i
= 0; i
< len
; i
++)
31117 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31118 selected_cpu_name
[i
] = 0;
31122 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31127 as_bad (_("unknown cpu `%s'"), str
);
31132 arm_parse_arch (const char *str
)
31134 const struct arm_arch_option_table
*opt
;
31135 const char *ext
= strchr (str
, '+');
31141 len
= strlen (str
);
31145 as_bad (_("missing architecture name `%s'"), str
);
31149 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31150 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31152 march_cpu_opt
= &opt
->value
;
31153 if (march_ext_opt
== NULL
)
31154 march_ext_opt
= XNEW (arm_feature_set
);
31155 *march_ext_opt
= arm_arch_none
;
31156 march_fpu_opt
= &opt
->default_fpu
;
31157 strcpy (selected_cpu_name
, opt
->name
);
31160 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31166 as_bad (_("unknown architecture `%s'\n"), str
);
31171 arm_parse_fpu (const char * str
)
31173 const struct arm_option_fpu_value_table
* opt
;
31175 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31176 if (streq (opt
->name
, str
))
31178 mfpu_opt
= &opt
->value
;
31182 as_bad (_("unknown floating point format `%s'\n"), str
);
31187 arm_parse_float_abi (const char * str
)
31189 const struct arm_option_value_table
* opt
;
31191 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31192 if (streq (opt
->name
, str
))
31194 mfloat_abi_opt
= opt
->value
;
31198 as_bad (_("unknown floating point abi `%s'\n"), str
);
31204 arm_parse_eabi (const char * str
)
31206 const struct arm_option_value_table
*opt
;
31208 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31209 if (streq (opt
->name
, str
))
31211 meabi_flags
= opt
->value
;
31214 as_bad (_("unknown EABI `%s'\n"), str
);
31220 arm_parse_it_mode (const char * str
)
31222 bfd_boolean ret
= TRUE
;
31224 if (streq ("arm", str
))
31225 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31226 else if (streq ("thumb", str
))
31227 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31228 else if (streq ("always", str
))
31229 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31230 else if (streq ("never", str
))
31231 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31234 as_bad (_("unknown implicit IT mode `%s', should be "\
31235 "arm, thumb, always, or never."), str
);
31243 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31245 codecomposer_syntax
= TRUE
;
31246 arm_comment_chars
[0] = ';';
31247 arm_line_separator_chars
[0] = 0;
31251 struct arm_long_option_table arm_long_opts
[] =
31253 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31254 arm_parse_cpu
, NULL
},
31255 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31256 arm_parse_arch
, NULL
},
31257 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31258 arm_parse_fpu
, NULL
},
31259 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31260 arm_parse_float_abi
, NULL
},
31262 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31263 arm_parse_eabi
, NULL
},
31265 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31266 arm_parse_it_mode
, NULL
},
31267 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31268 arm_ccs_mode
, NULL
},
31269 {NULL
, NULL
, 0, NULL
}
31273 md_parse_option (int c
, const char * arg
)
31275 struct arm_option_table
*opt
;
31276 const struct arm_legacy_option_table
*fopt
;
31277 struct arm_long_option_table
*lopt
;
31283 target_big_endian
= 1;
31289 target_big_endian
= 0;
31293 case OPTION_FIX_V4BX
:
31301 #endif /* OBJ_ELF */
31304 /* Listing option. Just ignore these, we don't support additional
31309 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31311 if (c
== opt
->option
[0]
31312 && ((arg
== NULL
&& opt
->option
[1] == 0)
31313 || streq (arg
, opt
->option
+ 1)))
31315 /* If the option is deprecated, tell the user. */
31316 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31317 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31318 arg
? arg
: "", _(opt
->deprecated
));
31320 if (opt
->var
!= NULL
)
31321 *opt
->var
= opt
->value
;
31327 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31329 if (c
== fopt
->option
[0]
31330 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31331 || streq (arg
, fopt
->option
+ 1)))
31333 /* If the option is deprecated, tell the user. */
31334 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31335 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31336 arg
? arg
: "", _(fopt
->deprecated
));
31338 if (fopt
->var
!= NULL
)
31339 *fopt
->var
= &fopt
->value
;
31345 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31347 /* These options are expected to have an argument. */
31348 if (c
== lopt
->option
[0]
31350 && strncmp (arg
, lopt
->option
+ 1,
31351 strlen (lopt
->option
+ 1)) == 0)
31353 /* If the option is deprecated, tell the user. */
31354 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31355 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31356 _(lopt
->deprecated
));
31358 /* Call the sup-option parser. */
31359 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31370 md_show_usage (FILE * fp
)
31372 struct arm_option_table
*opt
;
31373 struct arm_long_option_table
*lopt
;
31375 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31377 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31378 if (opt
->help
!= NULL
)
31379 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31381 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31382 if (lopt
->help
!= NULL
)
31383 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31387 -EB assemble code for a big-endian cpu\n"));
31392 -EL assemble code for a little-endian cpu\n"));
31396 --fix-v4bx Allow BX in ARMv4 code\n"));
31400 --fdpic generate an FDPIC object file\n"));
31401 #endif /* OBJ_ELF */
31409 arm_feature_set flags
;
31410 } cpu_arch_ver_table
;
31412 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31413 chronologically for architectures, with an exception for ARMv6-M and
31414 ARMv6S-M due to legacy reasons. No new architecture should have a
31415 special case. This allows for build attribute selection results to be
31416 stable when new architectures are added. */
31417 static const cpu_arch_ver_table cpu_arch_ver
[] =
31419 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31420 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31421 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31422 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31423 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31424 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31425 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31426 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31427 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31428 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31429 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31430 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31431 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31432 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31433 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31434 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31435 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31436 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31437 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31438 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31439 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31440 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31441 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31442 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31444 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31445 always selected build attributes to match those of ARMv6-M
31446 (resp. ARMv6S-M). However, due to these architectures being a strict
31447 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31448 would be selected when fully respecting chronology of architectures.
31449 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31450 move them before ARMv7 architectures. */
31451 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31452 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31454 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31455 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31456 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31457 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31458 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31459 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31460 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31461 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31462 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31463 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31464 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31465 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31466 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31467 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31468 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31469 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31470 {-1, ARM_ARCH_NONE
}
31473 /* Set an attribute if it has not already been set by the user. */
31476 aeabi_set_attribute_int (int tag
, int value
)
31479 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31480 || !attributes_set_explicitly
[tag
])
31481 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31485 aeabi_set_attribute_string (int tag
, const char *value
)
31488 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31489 || !attributes_set_explicitly
[tag
])
31490 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31493 /* Return whether features in the *NEEDED feature set are available via
31494 extensions for the architecture whose feature set is *ARCH_FSET. */
31497 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31498 const arm_feature_set
*needed
)
31500 int i
, nb_allowed_archs
;
31501 arm_feature_set ext_fset
;
31502 const struct arm_option_extension_value_table
*opt
;
31504 ext_fset
= arm_arch_none
;
31505 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31507 /* Extension does not provide any feature we need. */
31508 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31512 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31513 for (i
= 0; i
< nb_allowed_archs
; i
++)
31516 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31519 /* Extension is available, add it. */
31520 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31521 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31525 /* Can we enable all features in *needed? */
31526 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31529 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31530 a given architecture feature set *ARCH_EXT_FSET including extension feature
31531 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31532 - if true, check for an exact match of the architecture modulo extensions;
31533 - otherwise, select build attribute value of the first superset
31534 architecture released so that results remains stable when new architectures
31536 For -march/-mcpu=all the build attribute value of the most featureful
31537 architecture is returned. Tag_CPU_arch_profile result is returned in
31541 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31542 const arm_feature_set
*ext_fset
,
31543 char *profile
, int exact_match
)
31545 arm_feature_set arch_fset
;
31546 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31548 /* Select most featureful architecture with all its extensions if building
31549 for -march=all as the feature sets used to set build attributes. */
31550 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31552 /* Force revisiting of decision for each new architecture. */
31553 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31555 return TAG_CPU_ARCH_V8
;
31558 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31560 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31562 arm_feature_set known_arch_fset
;
31564 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31567 /* Base architecture match user-specified architecture and
31568 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31569 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31574 /* Base architecture match user-specified architecture only
31575 (eg. ARMv6-M in the same case as above). Record it in case we
31576 find a match with above condition. */
31577 else if (p_ver_ret
== NULL
31578 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31584 /* Architecture has all features wanted. */
31585 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31587 arm_feature_set added_fset
;
31589 /* Compute features added by this architecture over the one
31590 recorded in p_ver_ret. */
31591 if (p_ver_ret
!= NULL
)
31592 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31594 /* First architecture that match incl. with extensions, or the
31595 only difference in features over the recorded match is
31596 features that were optional and are now mandatory. */
31597 if (p_ver_ret
== NULL
31598 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31604 else if (p_ver_ret
== NULL
)
31606 arm_feature_set needed_ext_fset
;
31608 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31610 /* Architecture has all features needed when using some
31611 extensions. Record it and continue searching in case there
31612 exist an architecture providing all needed features without
31613 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31615 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31622 if (p_ver_ret
== NULL
)
31626 /* Tag_CPU_arch_profile. */
31627 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31628 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31629 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31630 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31632 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31634 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31638 return p_ver_ret
->val
;
31641 /* Set the public EABI object attributes. */
31644 aeabi_set_public_attributes (void)
31646 char profile
= '\0';
31649 int fp16_optional
= 0;
31650 int skip_exact_match
= 0;
31651 arm_feature_set flags
, flags_arch
, flags_ext
;
31653 /* Autodetection mode, choose the architecture based the instructions
31655 if (no_cpu_selected ())
31657 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31659 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31660 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31662 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31663 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31665 /* Code run during relaxation relies on selected_cpu being set. */
31666 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31667 flags_ext
= arm_arch_none
;
31668 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31669 selected_ext
= flags_ext
;
31670 selected_cpu
= flags
;
31672 /* Otherwise, choose the architecture based on the capabilities of the
31676 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31677 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31678 flags_ext
= selected_ext
;
31679 flags
= selected_cpu
;
31681 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31683 /* Allow the user to override the reported architecture. */
31684 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31686 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31687 flags_ext
= arm_arch_none
;
31690 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31692 /* When this function is run again after relaxation has happened there is no
31693 way to determine whether an architecture or CPU was specified by the user:
31694 - selected_cpu is set above for relaxation to work;
31695 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31696 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31697 Therefore, if not in -march=all case we first try an exact match and fall
31698 back to autodetection. */
31699 if (!skip_exact_match
)
31700 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31702 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31704 as_bad (_("no architecture contains all the instructions used\n"));
31706 /* Tag_CPU_name. */
31707 if (selected_cpu_name
[0])
31711 q
= selected_cpu_name
;
31712 if (strncmp (q
, "armv", 4) == 0)
31717 for (i
= 0; q
[i
]; i
++)
31718 q
[i
] = TOUPPER (q
[i
]);
31720 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31723 /* Tag_CPU_arch. */
31724 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31726 /* Tag_CPU_arch_profile. */
31727 if (profile
!= '\0')
31728 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31730 /* Tag_DSP_extension. */
31731 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31732 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31734 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31735 /* Tag_ARM_ISA_use. */
31736 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31737 || ARM_FEATURE_ZERO (flags_arch
))
31738 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31740 /* Tag_THUMB_ISA_use. */
31741 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31742 || ARM_FEATURE_ZERO (flags_arch
))
31746 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31747 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31749 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31753 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31756 /* Tag_VFP_arch. */
31757 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31758 aeabi_set_attribute_int (Tag_VFP_arch
,
31759 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31761 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31762 aeabi_set_attribute_int (Tag_VFP_arch
,
31763 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31765 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31768 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31770 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31772 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31775 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31776 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31777 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31778 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31779 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31781 /* Tag_ABI_HardFP_use. */
31782 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31783 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31784 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31786 /* Tag_WMMX_arch. */
31787 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31788 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31789 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31790 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31792 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31793 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31794 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31795 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31796 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31797 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31799 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31801 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31805 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31810 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31811 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31812 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31813 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31815 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31816 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31817 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31821 We set Tag_DIV_use to two when integer divide instructions have been used
31822 in ARM state, or when Thumb integer divide instructions have been used,
31823 but we have no architecture profile set, nor have we any ARM instructions.
31825 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31826 by the base architecture.
31828 For new architectures we will have to check these tests. */
31829 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31830 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31831 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31832 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31833 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31834 || (profile
== '\0'
31835 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31836 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31837 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31839 /* Tag_MP_extension_use. */
31840 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31841 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31843 /* Tag Virtualization_use. */
31844 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31846 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31849 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31852 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31853 finished and free extension feature bits which will not be used anymore. */
31856 arm_md_post_relax (void)
31858 aeabi_set_public_attributes ();
31859 XDELETE (mcpu_ext_opt
);
31860 mcpu_ext_opt
= NULL
;
31861 XDELETE (march_ext_opt
);
31862 march_ext_opt
= NULL
;
31865 /* Add the default contents for the .ARM.attributes section. */
31870 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31873 aeabi_set_public_attributes ();
31875 #endif /* OBJ_ELF */
31877 /* Parse a .cpu directive. */
31880 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31882 const struct arm_cpu_option_table
*opt
;
31886 name
= input_line_pointer
;
31887 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31888 input_line_pointer
++;
31889 saved_char
= *input_line_pointer
;
31890 *input_line_pointer
= 0;
31892 /* Skip the first "all" entry. */
31893 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31894 if (streq (opt
->name
, name
))
31896 selected_arch
= opt
->value
;
31897 selected_ext
= opt
->ext
;
31898 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31899 if (opt
->canonical_name
)
31900 strcpy (selected_cpu_name
, opt
->canonical_name
);
31904 for (i
= 0; opt
->name
[i
]; i
++)
31905 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31907 selected_cpu_name
[i
] = 0;
31909 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31911 *input_line_pointer
= saved_char
;
31912 demand_empty_rest_of_line ();
31915 as_bad (_("unknown cpu `%s'"), name
);
31916 *input_line_pointer
= saved_char
;
31917 ignore_rest_of_line ();
31920 /* Parse a .arch directive. */
31923 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31925 const struct arm_arch_option_table
*opt
;
31929 name
= input_line_pointer
;
31930 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31931 input_line_pointer
++;
31932 saved_char
= *input_line_pointer
;
31933 *input_line_pointer
= 0;
31935 /* Skip the first "all" entry. */
31936 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31937 if (streq (opt
->name
, name
))
31939 selected_arch
= opt
->value
;
31940 selected_ext
= arm_arch_none
;
31941 selected_cpu
= selected_arch
;
31942 strcpy (selected_cpu_name
, opt
->name
);
31943 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31944 *input_line_pointer
= saved_char
;
31945 demand_empty_rest_of_line ();
31949 as_bad (_("unknown architecture `%s'\n"), name
);
31950 *input_line_pointer
= saved_char
;
31951 ignore_rest_of_line ();
31954 /* Parse a .object_arch directive. */
31957 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31959 const struct arm_arch_option_table
*opt
;
31963 name
= input_line_pointer
;
31964 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31965 input_line_pointer
++;
31966 saved_char
= *input_line_pointer
;
31967 *input_line_pointer
= 0;
31969 /* Skip the first "all" entry. */
31970 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31971 if (streq (opt
->name
, name
))
31973 selected_object_arch
= opt
->value
;
31974 *input_line_pointer
= saved_char
;
31975 demand_empty_rest_of_line ();
31979 as_bad (_("unknown architecture `%s'\n"), name
);
31980 *input_line_pointer
= saved_char
;
31981 ignore_rest_of_line ();
31984 /* Parse a .arch_extension directive. */
31987 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31989 const struct arm_option_extension_value_table
*opt
;
31992 int adding_value
= 1;
31994 name
= input_line_pointer
;
31995 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31996 input_line_pointer
++;
31997 saved_char
= *input_line_pointer
;
31998 *input_line_pointer
= 0;
32000 if (strlen (name
) >= 2
32001 && strncmp (name
, "no", 2) == 0)
32007 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32008 if (streq (opt
->name
, name
))
32010 int i
, nb_allowed_archs
=
32011 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32012 for (i
= 0; i
< nb_allowed_archs
; i
++)
32015 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32017 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32021 if (i
== nb_allowed_archs
)
32023 as_bad (_("architectural extension `%s' is not allowed for the "
32024 "current base architecture"), name
);
32029 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32032 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32034 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32035 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32036 *input_line_pointer
= saved_char
;
32037 demand_empty_rest_of_line ();
32038 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32039 on this return so that duplicate extensions (extensions with the
32040 same name as a previous extension in the list) are not considered
32041 for command-line parsing. */
32045 if (opt
->name
== NULL
)
32046 as_bad (_("unknown architecture extension `%s'\n"), name
);
32048 *input_line_pointer
= saved_char
;
32049 ignore_rest_of_line ();
32052 /* Parse a .fpu directive. */
32055 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32057 const struct arm_option_fpu_value_table
*opt
;
32061 name
= input_line_pointer
;
32062 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32063 input_line_pointer
++;
32064 saved_char
= *input_line_pointer
;
32065 *input_line_pointer
= 0;
32067 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32068 if (streq (opt
->name
, name
))
32070 selected_fpu
= opt
->value
;
32071 #ifndef CPU_DEFAULT
32072 if (no_cpu_selected ())
32073 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32076 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32077 *input_line_pointer
= saved_char
;
32078 demand_empty_rest_of_line ();
32082 as_bad (_("unknown floating point format `%s'\n"), name
);
32083 *input_line_pointer
= saved_char
;
32084 ignore_rest_of_line ();
32087 /* Copy symbol information. */
32090 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32092 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32096 /* Given a symbolic attribute NAME, return the proper integer value.
32097 Returns -1 if the attribute is not known. */
32100 arm_convert_symbolic_attribute (const char *name
)
32102 static const struct
32107 attribute_table
[] =
32109 /* When you modify this table you should
32110 also modify the list in doc/c-arm.texi. */
32111 #define T(tag) {#tag, tag}
32112 T (Tag_CPU_raw_name
),
32115 T (Tag_CPU_arch_profile
),
32116 T (Tag_ARM_ISA_use
),
32117 T (Tag_THUMB_ISA_use
),
32121 T (Tag_Advanced_SIMD_arch
),
32122 T (Tag_PCS_config
),
32123 T (Tag_ABI_PCS_R9_use
),
32124 T (Tag_ABI_PCS_RW_data
),
32125 T (Tag_ABI_PCS_RO_data
),
32126 T (Tag_ABI_PCS_GOT_use
),
32127 T (Tag_ABI_PCS_wchar_t
),
32128 T (Tag_ABI_FP_rounding
),
32129 T (Tag_ABI_FP_denormal
),
32130 T (Tag_ABI_FP_exceptions
),
32131 T (Tag_ABI_FP_user_exceptions
),
32132 T (Tag_ABI_FP_number_model
),
32133 T (Tag_ABI_align_needed
),
32134 T (Tag_ABI_align8_needed
),
32135 T (Tag_ABI_align_preserved
),
32136 T (Tag_ABI_align8_preserved
),
32137 T (Tag_ABI_enum_size
),
32138 T (Tag_ABI_HardFP_use
),
32139 T (Tag_ABI_VFP_args
),
32140 T (Tag_ABI_WMMX_args
),
32141 T (Tag_ABI_optimization_goals
),
32142 T (Tag_ABI_FP_optimization_goals
),
32143 T (Tag_compatibility
),
32144 T (Tag_CPU_unaligned_access
),
32145 T (Tag_FP_HP_extension
),
32146 T (Tag_VFP_HP_extension
),
32147 T (Tag_ABI_FP_16bit_format
),
32148 T (Tag_MPextension_use
),
32150 T (Tag_nodefaults
),
32151 T (Tag_also_compatible_with
),
32152 T (Tag_conformance
),
32154 T (Tag_Virtualization_use
),
32155 T (Tag_DSP_extension
),
32157 /* We deliberately do not include Tag_MPextension_use_legacy. */
32165 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32166 if (streq (name
, attribute_table
[i
].name
))
32167 return attribute_table
[i
].tag
;
32172 /* Apply sym value for relocations only in the case that they are for
32173 local symbols in the same segment as the fixup and you have the
32174 respective architectural feature for blx and simple switches. */
32177 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32180 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32181 /* PR 17444: If the local symbol is in a different section then a reloc
32182 will always be generated for it, so applying the symbol value now
32183 will result in a double offset being stored in the relocation. */
32184 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32185 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32187 switch (fixP
->fx_r_type
)
32189 case BFD_RELOC_ARM_PCREL_BLX
:
32190 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32191 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32195 case BFD_RELOC_ARM_PCREL_CALL
:
32196 case BFD_RELOC_THUMB_PCREL_BLX
:
32197 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32208 #endif /* OBJ_ELF */