1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
/* Instruction to indicate a MVE instruction without
469 a predication code. */
472 /* The maximum number of operands we need. */
473 #define ARM_IT_MAX_OPERANDS 6
474 #define ARM_IT_MAX_RELOCS 3
479 unsigned long instruction
;
483 /* "uncond_value" is set to the value in place of the conditional field in
484 unconditional versions of the instruction, or -1 if nothing is
487 struct neon_type vectype
;
488 /* This does not indicate an actual NEON instruction, only that
489 the mnemonic accepts neon-style type suffixes. */
491 /* Set to the opcode if the instruction needs relaxation.
492 Zero if the instruction is not relaxed. */
496 bfd_reloc_code_real_type type
;
499 } relocs
[ARM_IT_MAX_RELOCS
];
501 enum pred_instruction_type pred_insn_type
;
507 struct neon_type_el vectype
;
508 unsigned present
: 1; /* Operand present. */
509 unsigned isreg
: 1; /* Operand was a register. */
510 unsigned immisreg
: 1; /* .imm field is a second register. */
511 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
512 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
513 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
514 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
515 instructions. This allows us to disambiguate ARM <-> vector insns. */
516 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
517 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
518 unsigned isquad
: 1; /* Operand is SIMD quad register. */
519 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
520 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
521 unsigned writeback
: 1; /* Operand has trailing ! */
522 unsigned preind
: 1; /* Preindexed address. */
523 unsigned postind
: 1; /* Postindexed address. */
524 unsigned negative
: 1; /* Index register was negated. */
525 unsigned shifted
: 1; /* Shift applied to operation. */
526 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
527 } operands
[ARM_IT_MAX_OPERANDS
];
530 static struct arm_it inst
;
532 #define NUM_FLOAT_VALS 8
534 const char * fp_const
[] =
536 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
539 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
549 #define CP_T_X 0x00008000
550 #define CP_T_Y 0x00400000
552 #define CONDS_BIT 0x00100000
553 #define LOAD_BIT 0x00100000
555 #define DOUBLE_LOAD_FLAG 0x00000001
559 const char * template_name
;
563 #define COND_ALWAYS 0xE
567 const char * template_name
;
571 struct asm_barrier_opt
573 const char * template_name
;
575 const arm_feature_set arch
;
578 /* The bit that distinguishes CPSR and SPSR. */
579 #define SPSR_BIT (1 << 22)
581 /* The individual PSR flag bits. */
582 #define PSR_c (1 << 16)
583 #define PSR_x (1 << 17)
584 #define PSR_s (1 << 18)
585 #define PSR_f (1 << 19)
590 bfd_reloc_code_real_type reloc
;
595 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
596 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
601 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
604 /* Bits for DEFINED field in neon_typed_alias. */
605 #define NTA_HASTYPE 1
606 #define NTA_HASINDEX 2
608 struct neon_typed_alias
610 unsigned char defined
;
612 struct neon_type_el eltype
;
615 /* ARM register categories. This includes coprocessor numbers and various
616 architecture extensions' registers. Each entry should have an error message
617 in reg_expected_msgs below. */
646 /* Structure for a hash table entry for a register.
647 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
648 information which states whether a vector type or index is specified (for a
649 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
655 unsigned char builtin
;
656 struct neon_typed_alias
* neon
;
659 /* Diagnostics used when we don't get a register of the expected type. */
660 const char * const reg_expected_msgs
[] =
662 [REG_TYPE_RN
] = N_("ARM register expected"),
663 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
664 [REG_TYPE_CN
] = N_("co-processor register expected"),
665 [REG_TYPE_FN
] = N_("FPA register expected"),
666 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
667 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
668 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
669 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
670 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
671 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
672 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
674 [REG_TYPE_VFC
] = N_("VFP system register expected"),
675 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
676 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
677 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
678 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
679 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
680 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
681 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
682 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
683 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
684 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
685 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
686 [REG_TYPE_RNB
] = N_("")
689 /* Some well known registers that we refer to directly elsewhere. */
695 /* ARM instructions take 4bytes in the object file, Thumb instructions
701 /* Basic string to match. */
702 const char * template_name
;
704 /* Parameters to instruction. */
705 unsigned int operands
[8];
707 /* Conditional tag - see opcode_lookup. */
708 unsigned int tag
: 4;
710 /* Basic instruction code. */
711 unsigned int avalue
: 28;
713 /* Thumb-format instruction code. */
716 /* Which architecture variant provides this instruction. */
717 const arm_feature_set
* avariant
;
718 const arm_feature_set
* tvariant
;
720 /* Function to call to encode instruction in ARM format. */
721 void (* aencode
) (void);
723 /* Function to call to encode instruction in Thumb format. */
724 void (* tencode
) (void);
726 /* Indicates whether this instruction may be vector predicated. */
727 unsigned int mayBeVecPred
: 1;
730 /* Defines for various bits that we will want to toggle. */
731 #define INST_IMMEDIATE 0x02000000
732 #define OFFSET_REG 0x02000000
733 #define HWOFFSET_IMM 0x00400000
734 #define SHIFT_BY_REG 0x00000010
735 #define PRE_INDEX 0x01000000
736 #define INDEX_UP 0x00800000
737 #define WRITE_BACK 0x00200000
738 #define LDM_TYPE_2_OR_3 0x00400000
739 #define CPSI_MMOD 0x00020000
741 #define LITERAL_MASK 0xf000f000
742 #define OPCODE_MASK 0xfe1fffff
743 #define V4_STR_BIT 0x00000020
744 #define VLDR_VMOV_SAME 0x0040f000
746 #define T2_SUBS_PC_LR 0xf3de8f00
748 #define DATA_OP_SHIFT 21
749 #define SBIT_SHIFT 20
751 #define T2_OPCODE_MASK 0xfe1fffff
752 #define T2_DATA_OP_SHIFT 21
753 #define T2_SBIT_SHIFT 20
755 #define A_COND_MASK 0xf0000000
756 #define A_PUSH_POP_OP_MASK 0x0fff0000
758 /* Opcodes for pushing/poping registers to/from the stack. */
759 #define A1_OPCODE_PUSH 0x092d0000
760 #define A2_OPCODE_PUSH 0x052d0004
761 #define A2_OPCODE_POP 0x049d0004
763 /* Codes to distinguish the arithmetic instructions. */
774 #define OPCODE_CMP 10
775 #define OPCODE_CMN 11
776 #define OPCODE_ORR 12
777 #define OPCODE_MOV 13
778 #define OPCODE_BIC 14
779 #define OPCODE_MVN 15
781 #define T2_OPCODE_AND 0
782 #define T2_OPCODE_BIC 1
783 #define T2_OPCODE_ORR 2
784 #define T2_OPCODE_ORN 3
785 #define T2_OPCODE_EOR 4
786 #define T2_OPCODE_ADD 8
787 #define T2_OPCODE_ADC 10
788 #define T2_OPCODE_SBC 11
789 #define T2_OPCODE_SUB 13
790 #define T2_OPCODE_RSB 14
792 #define T_OPCODE_MUL 0x4340
793 #define T_OPCODE_TST 0x4200
794 #define T_OPCODE_CMN 0x42c0
795 #define T_OPCODE_NEG 0x4240
796 #define T_OPCODE_MVN 0x43c0
798 #define T_OPCODE_ADD_R3 0x1800
799 #define T_OPCODE_SUB_R3 0x1a00
800 #define T_OPCODE_ADD_HI 0x4400
801 #define T_OPCODE_ADD_ST 0xb000
802 #define T_OPCODE_SUB_ST 0xb080
803 #define T_OPCODE_ADD_SP 0xa800
804 #define T_OPCODE_ADD_PC 0xa000
805 #define T_OPCODE_ADD_I8 0x3000
806 #define T_OPCODE_SUB_I8 0x3800
807 #define T_OPCODE_ADD_I3 0x1c00
808 #define T_OPCODE_SUB_I3 0x1e00
810 #define T_OPCODE_ASR_R 0x4100
811 #define T_OPCODE_LSL_R 0x4080
812 #define T_OPCODE_LSR_R 0x40c0
813 #define T_OPCODE_ROR_R 0x41c0
814 #define T_OPCODE_ASR_I 0x1000
815 #define T_OPCODE_LSL_I 0x0000
816 #define T_OPCODE_LSR_I 0x0800
818 #define T_OPCODE_MOV_I8 0x2000
819 #define T_OPCODE_CMP_I8 0x2800
820 #define T_OPCODE_CMP_LR 0x4280
821 #define T_OPCODE_MOV_HR 0x4600
822 #define T_OPCODE_CMP_HR 0x4500
824 #define T_OPCODE_LDR_PC 0x4800
825 #define T_OPCODE_LDR_SP 0x9800
826 #define T_OPCODE_STR_SP 0x9000
827 #define T_OPCODE_LDR_IW 0x6800
828 #define T_OPCODE_STR_IW 0x6000
829 #define T_OPCODE_LDR_IH 0x8800
830 #define T_OPCODE_STR_IH 0x8000
831 #define T_OPCODE_LDR_IB 0x7800
832 #define T_OPCODE_STR_IB 0x7000
833 #define T_OPCODE_LDR_RW 0x5800
834 #define T_OPCODE_STR_RW 0x5000
835 #define T_OPCODE_LDR_RH 0x5a00
836 #define T_OPCODE_STR_RH 0x5200
837 #define T_OPCODE_LDR_RB 0x5c00
838 #define T_OPCODE_STR_RB 0x5400
840 #define T_OPCODE_PUSH 0xb400
841 #define T_OPCODE_POP 0xbc00
843 #define T_OPCODE_BRANCH 0xe000
845 #define THUMB_SIZE 2 /* Size of thumb instruction. */
846 #define THUMB_PP_PC_LR 0x0100
847 #define THUMB_LOAD_BIT 0x0800
848 #define THUMB2_LOAD_BIT 0x00100000
850 #define BAD_SYNTAX _("syntax error")
851 #define BAD_ARGS _("bad arguments to instruction")
852 #define BAD_SP _("r13 not allowed here")
853 #define BAD_PC _("r15 not allowed here")
854 #define BAD_COND _("instruction cannot be conditional")
855 #define BAD_OVERLAP _("registers may not be the same")
856 #define BAD_HIREG _("lo register required")
857 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
858 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
859 #define BAD_BRANCH _("branch must be last instruction in IT block")
860 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
861 #define BAD_NOT_IT _("instruction not allowed in IT block")
862 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
863 #define BAD_FPU _("selected FPU does not support instruction")
864 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
865 #define BAD_OUT_VPT \
866 _("vector predicated instruction should be in VPT/VPST block")
867 #define BAD_IT_COND _("incorrect condition in IT block")
868 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
869 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
870 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
871 #define BAD_PC_ADDRESSING \
872 _("cannot use register index with PC-relative addressing")
873 #define BAD_PC_WRITEBACK \
874 _("cannot use writeback with PC-relative addressing")
875 #define BAD_RANGE _("branch out of range")
876 #define BAD_FP16 _("selected processor does not support fp16 instruction")
877 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
878 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
879 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
881 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
883 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
885 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
888 static struct hash_control
* arm_ops_hsh
;
889 static struct hash_control
* arm_cond_hsh
;
890 static struct hash_control
* arm_vcond_hsh
;
891 static struct hash_control
* arm_shift_hsh
;
892 static struct hash_control
* arm_psr_hsh
;
893 static struct hash_control
* arm_v7m_psr_hsh
;
894 static struct hash_control
* arm_reg_hsh
;
895 static struct hash_control
* arm_reloc_hsh
;
896 static struct hash_control
* arm_barrier_opt_hsh
;
898 /* Stuff needed to resolve the label ambiguity
907 symbolS
* last_label_seen
;
908 static int label_is_thumb_function_name
= FALSE
;
910 /* Literal pool structure. Held on a per-section
911 and per-sub-section basis. */
913 #define MAX_LITERAL_POOL_SIZE 1024
914 typedef struct literal_pool
916 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
917 unsigned int next_free_entry
;
923 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
925 struct literal_pool
* next
;
926 unsigned int alignment
;
929 /* Pointer to a linked list of literal pools. */
930 literal_pool
* list_of_pools
= NULL
;
932 typedef enum asmfunc_states
935 WAITING_ASMFUNC_NAME
,
939 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
942 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
944 static struct current_pred now_pred
;
948 now_pred_compatible (int cond
)
950 return (cond
& ~1) == (now_pred
.cc
& ~1);
954 conditional_insn (void)
956 return inst
.cond
!= COND_ALWAYS
;
959 static int in_pred_block (void);
961 static int handle_pred_state (void);
963 static void force_automatic_it_block_close (void);
965 static void it_fsm_post_encode (void);
967 #define set_pred_insn_type(type) \
970 inst.pred_insn_type = type; \
971 if (handle_pred_state () == FAIL) \
976 #define set_pred_insn_type_nonvoid(type, failret) \
979 inst.pred_insn_type = type; \
980 if (handle_pred_state () == FAIL) \
985 #define set_pred_insn_type_last() \
988 if (inst.cond == COND_ALWAYS) \
989 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
991 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
997 /* This array holds the chars that always start a comment. If the
998 pre-processor is disabled, these aren't very useful. */
999 char arm_comment_chars
[] = "@";
1001 /* This array holds the chars that only start a comment at the beginning of
1002 a line. If the line seems to have the form '# 123 filename'
1003 .line and .file directives will appear in the pre-processed output. */
1004 /* Note that input_file.c hand checks for '#' at the beginning of the
1005 first line of the input file. This is because the compiler outputs
1006 #NO_APP at the beginning of its output. */
1007 /* Also note that comments like this one will always work. */
1008 const char line_comment_chars
[] = "#";
1010 char arm_line_separator_chars
[] = ";";
1012 /* Chars that can be used to separate mant
1013 from exp in floating point numbers. */
1014 const char EXP_CHARS
[] = "eE";
1016 /* Chars that mean this number is a floating point constant. */
1017 /* As in 0f12.456 */
1018 /* or 0d1.2345e12 */
1020 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1022 /* Prefix characters that indicate the start of an immediate
1024 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1026 /* Separator character handling. */
1028 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1031 skip_past_char (char ** str
, char c
)
1033 /* PR gas/14987: Allow for whitespace before the expected character. */
1034 skip_whitespace (*str
);
1045 #define skip_past_comma(str) skip_past_char (str, ',')
1047 /* Arithmetic expressions (possibly involving symbols). */
1049 /* Return TRUE if anything in the expression is a bignum. */
1052 walk_no_bignums (symbolS
* sp
)
1054 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1057 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1059 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1060 || (symbol_get_value_expression (sp
)->X_op_symbol
1061 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1067 static bfd_boolean in_my_get_expression
= FALSE
;
1069 /* Third argument to my_get_expression. */
1070 #define GE_NO_PREFIX 0
1071 #define GE_IMM_PREFIX 1
1072 #define GE_OPT_PREFIX 2
1073 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1074 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1075 #define GE_OPT_PREFIX_BIG 3
1078 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1082 /* In unified syntax, all prefixes are optional. */
1084 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1087 switch (prefix_mode
)
1089 case GE_NO_PREFIX
: break;
1091 if (!is_immediate_prefix (**str
))
1093 inst
.error
= _("immediate expression requires a # prefix");
1099 case GE_OPT_PREFIX_BIG
:
1100 if (is_immediate_prefix (**str
))
1107 memset (ep
, 0, sizeof (expressionS
));
1109 save_in
= input_line_pointer
;
1110 input_line_pointer
= *str
;
1111 in_my_get_expression
= TRUE
;
1113 in_my_get_expression
= FALSE
;
1115 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1117 /* We found a bad or missing expression in md_operand(). */
1118 *str
= input_line_pointer
;
1119 input_line_pointer
= save_in
;
1120 if (inst
.error
== NULL
)
1121 inst
.error
= (ep
->X_op
== O_absent
1122 ? _("missing expression") :_("bad expression"));
1126 /* Get rid of any bignums now, so that we don't generate an error for which
1127 we can't establish a line number later on. Big numbers are never valid
1128 in instructions, which is where this routine is always called. */
1129 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1130 && (ep
->X_op
== O_big
1131 || (ep
->X_add_symbol
1132 && (walk_no_bignums (ep
->X_add_symbol
)
1134 && walk_no_bignums (ep
->X_op_symbol
))))))
1136 inst
.error
= _("invalid constant");
1137 *str
= input_line_pointer
;
1138 input_line_pointer
= save_in
;
1142 *str
= input_line_pointer
;
1143 input_line_pointer
= save_in
;
1147 /* Turn a string in input_line_pointer into a floating point constant
1148 of type TYPE, and store the appropriate bytes in *LITP. The number
1149 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1150 returned, or NULL on OK.
1152 Note that fp constants aren't represent in the normal way on the ARM.
1153 In big endian mode, things are as expected. However, in little endian
1154 mode fp constants are big-endian word-wise, and little-endian byte-wise
1155 within the words. For example, (double) 1.1 in big endian mode is
1156 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1157 the byte sequence 99 99 f1 3f 9a 99 99 99.
1159 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1162 md_atof (int type
, char * litP
, int * sizeP
)
1165 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1197 return _("Unrecognized or unsupported floating point constant");
1200 t
= atof_ieee (input_line_pointer
, type
, words
);
1202 input_line_pointer
= t
;
1203 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1205 if (target_big_endian
)
1207 for (i
= 0; i
< prec
; i
++)
1209 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1210 litP
+= sizeof (LITTLENUM_TYPE
);
1215 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1216 for (i
= prec
- 1; i
>= 0; i
--)
1218 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1219 litP
+= sizeof (LITTLENUM_TYPE
);
1222 /* For a 4 byte float the order of elements in `words' is 1 0.
1223 For an 8 byte float the order is 1 0 3 2. */
1224 for (i
= 0; i
< prec
; i
+= 2)
1226 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1227 sizeof (LITTLENUM_TYPE
));
1228 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1229 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1230 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1237 /* We handle all bad expressions here, so that we can report the faulty
1238 instruction in the error message. */
1241 md_operand (expressionS
* exp
)
1243 if (in_my_get_expression
)
1244 exp
->X_op
= O_illegal
;
1247 /* Immediate values. */
1250 /* Generic immediate-value read function for use in directives.
1251 Accepts anything that 'expression' can fold to a constant.
1252 *val receives the number. */
1255 immediate_for_directive (int *val
)
1258 exp
.X_op
= O_illegal
;
1260 if (is_immediate_prefix (*input_line_pointer
))
1262 input_line_pointer
++;
1266 if (exp
.X_op
!= O_constant
)
1268 as_bad (_("expected #constant"));
1269 ignore_rest_of_line ();
1272 *val
= exp
.X_add_number
;
1277 /* Register parsing. */
1279 /* Generic register parser. CCP points to what should be the
1280 beginning of a register name. If it is indeed a valid register
1281 name, advance CCP over it and return the reg_entry structure;
1282 otherwise return NULL. Does not issue diagnostics. */
1284 static struct reg_entry
*
1285 arm_reg_parse_multi (char **ccp
)
1289 struct reg_entry
*reg
;
1291 skip_whitespace (start
);
1293 #ifdef REGISTER_PREFIX
1294 if (*start
!= REGISTER_PREFIX
)
1298 #ifdef OPTIONAL_REGISTER_PREFIX
1299 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1304 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1309 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1311 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1321 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1322 enum arm_reg_type type
)
1324 /* Alternative syntaxes are accepted for a few register classes. */
1331 /* Generic coprocessor register names are allowed for these. */
1332 if (reg
&& reg
->type
== REG_TYPE_CN
)
1337 /* For backward compatibility, a bare number is valid here. */
1339 unsigned long processor
= strtoul (start
, ccp
, 10);
1340 if (*ccp
!= start
&& processor
<= 15)
1345 case REG_TYPE_MMXWC
:
1346 /* WC includes WCG. ??? I'm not sure this is true for all
1347 instructions that take WC registers. */
1348 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1359 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1360 return value is the register number or FAIL. */
1363 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1366 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1369 /* Do not allow a scalar (reg+index) to parse as a register. */
1370 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1373 if (reg
&& reg
->type
== type
)
1376 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1383 /* Parse a Neon type specifier. *STR should point at the leading '.'
1384 character. Does no verification at this stage that the type fits the opcode
1391 Can all be legally parsed by this function.
1393 Fills in neon_type struct pointer with parsed information, and updates STR
1394 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1395 type, FAIL if not. */
1398 parse_neon_type (struct neon_type
*type
, char **str
)
1405 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1407 enum neon_el_type thistype
= NT_untyped
;
1408 unsigned thissize
= -1u;
1415 /* Just a size without an explicit type. */
1419 switch (TOLOWER (*ptr
))
1421 case 'i': thistype
= NT_integer
; break;
1422 case 'f': thistype
= NT_float
; break;
1423 case 'p': thistype
= NT_poly
; break;
1424 case 's': thistype
= NT_signed
; break;
1425 case 'u': thistype
= NT_unsigned
; break;
1427 thistype
= NT_float
;
1432 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1438 /* .f is an abbreviation for .f32. */
1439 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1444 thissize
= strtoul (ptr
, &ptr
, 10);
1446 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1449 as_bad (_("bad size %d in type specifier"), thissize
);
1457 type
->el
[type
->elems
].type
= thistype
;
1458 type
->el
[type
->elems
].size
= thissize
;
1463 /* Empty/missing type is not a successful parse. */
1464 if (type
->elems
== 0)
1472 /* Errors may be set multiple times during parsing or bit encoding
1473 (particularly in the Neon bits), but usually the earliest error which is set
1474 will be the most meaningful. Avoid overwriting it with later (cascading)
1475 errors by calling this function. */
1478 first_error (const char *err
)
1484 /* Parse a single type, e.g. ".s32", leading period included. */
1486 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1489 struct neon_type optype
;
1493 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1495 if (optype
.elems
== 1)
1496 *vectype
= optype
.el
[0];
1499 first_error (_("only one type should be specified for operand"));
1505 first_error (_("vector type expected"));
1517 /* Special meanings for indices (which have a range of 0-7), which will fit into
1520 #define NEON_ALL_LANES 15
1521 #define NEON_INTERLEAVE_LANES 14
1523 /* Record a use of the given feature. */
1525 record_feature_use (const arm_feature_set
*feature
)
1528 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1530 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1533 /* If the given feature available in the selected CPU, mark it as used.
1534 Returns TRUE iff feature is available. */
1536 mark_feature_used (const arm_feature_set
*feature
)
1538 /* Ensure the option is valid on the current architecture. */
1539 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1542 /* Add the appropriate architecture feature for the barrier option used.
1544 record_feature_use (feature
);
1549 /* Parse either a register or a scalar, with an optional type. Return the
1550 register number, and optionally fill in the actual type of the register
1551 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1552 type/index information in *TYPEINFO. */
1555 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1556 enum arm_reg_type
*rtype
,
1557 struct neon_typed_alias
*typeinfo
)
1560 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1561 struct neon_typed_alias atype
;
1562 struct neon_type_el parsetype
;
1566 atype
.eltype
.type
= NT_invtype
;
1567 atype
.eltype
.size
= -1;
1569 /* Try alternate syntax for some types of register. Note these are mutually
1570 exclusive with the Neon syntax extensions. */
1573 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1581 /* Undo polymorphism when a set of register types may be accepted. */
1582 if ((type
== REG_TYPE_NDQ
1583 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1584 || (type
== REG_TYPE_VFSD
1585 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1586 || (type
== REG_TYPE_NSDQ
1587 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1588 || reg
->type
== REG_TYPE_NQ
))
1589 || (type
== REG_TYPE_NSD
1590 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1591 || (type
== REG_TYPE_MMXWC
1592 && (reg
->type
== REG_TYPE_MMXWCG
)))
1593 type
= (enum arm_reg_type
) reg
->type
;
1595 if (type
== REG_TYPE_MQ
)
1597 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1600 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1603 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1605 first_error (_("expected MVE register [q0..q7]"));
1610 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1611 && (type
== REG_TYPE_NQ
))
1615 if (type
!= reg
->type
)
1621 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1623 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1625 first_error (_("can't redefine type for operand"));
1628 atype
.defined
|= NTA_HASTYPE
;
1629 atype
.eltype
= parsetype
;
1632 if (skip_past_char (&str
, '[') == SUCCESS
)
1634 if (type
!= REG_TYPE_VFD
1635 && !(type
== REG_TYPE_VFS
1636 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1638 first_error (_("only D registers may be indexed"));
1642 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1644 first_error (_("can't change index for operand"));
1648 atype
.defined
|= NTA_HASINDEX
;
1650 if (skip_past_char (&str
, ']') == SUCCESS
)
1651 atype
.index
= NEON_ALL_LANES
;
1656 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1658 if (exp
.X_op
!= O_constant
)
1660 first_error (_("constant expression required"));
1664 if (skip_past_char (&str
, ']') == FAIL
)
1667 atype
.index
= exp
.X_add_number
;
1682 /* Like arm_reg_parse, but also allow the following extra features:
1683 - If RTYPE is non-zero, return the (possibly restricted) type of the
1684 register (e.g. Neon double or quad reg when either has been requested).
1685 - If this is a Neon vector type with additional type information, fill
1686 in the struct pointed to by VECTYPE (if non-NULL).
1687 This function will fault on encountering a scalar. */
1690 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1691 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1693 struct neon_typed_alias atype
;
1695 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1700 /* Do not allow regname(... to parse as a register. */
1704 /* Do not allow a scalar (reg+index) to parse as a register. */
1705 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1707 first_error (_("register operand expected, but got scalar"));
1712 *vectype
= atype
.eltype
;
1719 #define NEON_SCALAR_REG(X) ((X) >> 4)
1720 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1722 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1723 have enough information to be able to do a good job bounds-checking. So, we
1724 just do easy checks here, and do further checks later. */
1727 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1731 struct neon_typed_alias atype
;
1732 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1735 reg_type
= REG_TYPE_VFS
;
1737 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1739 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1742 if (atype
.index
== NEON_ALL_LANES
)
1744 first_error (_("scalar must have an index"));
1747 else if (atype
.index
>= 64 / elsize
)
1749 first_error (_("scalar index out of range"));
1754 *type
= atype
.eltype
;
1758 return reg
* 16 + atype
.index
;
1761 /* Types of registers in a list. */
1774 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1777 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1783 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1785 /* We come back here if we get ranges concatenated by '+' or '|'. */
1788 skip_whitespace (str
);
1801 const char apsr_str
[] = "apsr";
1802 int apsr_str_len
= strlen (apsr_str
);
1804 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1805 if (etype
== REGLIST_CLRM
)
1807 if (reg
== REG_SP
|| reg
== REG_PC
)
1809 else if (reg
== FAIL
1810 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1811 && !ISALPHA (*(str
+ apsr_str_len
)))
1814 str
+= apsr_str_len
;
1819 first_error (_("r0-r12, lr or APSR expected"));
1823 else /* etype == REGLIST_RN. */
1827 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1838 first_error (_("bad range in register list"));
1842 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1844 if (range
& (1 << i
))
1846 (_("Warning: duplicated register (r%d) in register list"),
1854 if (range
& (1 << reg
))
1855 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1857 else if (reg
<= cur_reg
)
1858 as_tsktsk (_("Warning: register range not in ascending order"));
1863 while (skip_past_comma (&str
) != FAIL
1864 || (in_range
= 1, *str
++ == '-'));
1867 if (skip_past_char (&str
, '}') == FAIL
)
1869 first_error (_("missing `}'"));
1873 else if (etype
== REGLIST_RN
)
1877 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1880 if (exp
.X_op
== O_constant
)
1882 if (exp
.X_add_number
1883 != (exp
.X_add_number
& 0x0000ffff))
1885 inst
.error
= _("invalid register mask");
1889 if ((range
& exp
.X_add_number
) != 0)
1891 int regno
= range
& exp
.X_add_number
;
1894 regno
= (1 << regno
) - 1;
1896 (_("Warning: duplicated register (r%d) in register list"),
1900 range
|= exp
.X_add_number
;
1904 if (inst
.relocs
[0].type
!= 0)
1906 inst
.error
= _("expression too complex");
1910 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1911 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1912 inst
.relocs
[0].pc_rel
= 0;
1916 if (*str
== '|' || *str
== '+')
1922 while (another_range
);
1928 /* Parse a VFP register list. If the string is invalid return FAIL.
1929 Otherwise return the number of registers, and set PBASE to the first
1930 register. Parses registers of type ETYPE.
1931 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1932 - Q registers can be used to specify pairs of D registers
1933 - { } can be omitted from around a singleton register list
1934 FIXME: This is not implemented, as it would require backtracking in
1937 This could be done (the meaning isn't really ambiguous), but doesn't
1938 fit in well with the current parsing framework.
1939 - 32 D registers may be used (also true for VFPv3).
1940 FIXME: Types are ignored in these register lists, which is probably a
1944 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1945 bfd_boolean
*partial_match
)
1950 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1954 unsigned long mask
= 0;
1956 bfd_boolean vpr_seen
= FALSE
;
1957 bfd_boolean expect_vpr
=
1958 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
1960 if (skip_past_char (&str
, '{') == FAIL
)
1962 inst
.error
= _("expecting {");
1969 case REGLIST_VFP_S_VPR
:
1970 regtype
= REG_TYPE_VFS
;
1975 case REGLIST_VFP_D_VPR
:
1976 regtype
= REG_TYPE_VFD
;
1979 case REGLIST_NEON_D
:
1980 regtype
= REG_TYPE_NDQ
;
1987 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
1989 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1990 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1994 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1997 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2004 base_reg
= max_regs
;
2005 *partial_match
= FALSE
;
2009 int setmask
= 1, addregs
= 1;
2010 const char vpr_str
[] = "vpr";
2011 int vpr_str_len
= strlen (vpr_str
);
2013 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2017 if (new_base
== FAIL
2018 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2019 && !ISALPHA (*(str
+ vpr_str_len
))
2025 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2029 first_error (_("VPR expected last"));
2032 else if (new_base
== FAIL
)
2034 if (regtype
== REG_TYPE_VFS
)
2035 first_error (_("VFP single precision register or VPR "
2037 else /* regtype == REG_TYPE_VFD. */
2038 first_error (_("VFP/Neon double precision register or VPR "
2043 else if (new_base
== FAIL
)
2045 first_error (_(reg_expected_msgs
[regtype
]));
2049 *partial_match
= TRUE
;
2053 if (new_base
>= max_regs
)
2055 first_error (_("register out of range in list"));
2059 /* Note: a value of 2 * n is returned for the register Q<n>. */
2060 if (regtype
== REG_TYPE_NQ
)
2066 if (new_base
< base_reg
)
2067 base_reg
= new_base
;
2069 if (mask
& (setmask
<< new_base
))
2071 first_error (_("invalid register list"));
2075 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2077 as_tsktsk (_("register list not in ascending order"));
2081 mask
|= setmask
<< new_base
;
2084 if (*str
== '-') /* We have the start of a range expression */
2090 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2093 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2097 if (high_range
>= max_regs
)
2099 first_error (_("register out of range in list"));
2103 if (regtype
== REG_TYPE_NQ
)
2104 high_range
= high_range
+ 1;
2106 if (high_range
<= new_base
)
2108 inst
.error
= _("register range not in ascending order");
2112 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2114 if (mask
& (setmask
<< new_base
))
2116 inst
.error
= _("invalid register list");
2120 mask
|= setmask
<< new_base
;
2125 while (skip_past_comma (&str
) != FAIL
);
2129 /* Sanity check -- should have raised a parse error above. */
2130 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2135 if (expect_vpr
&& !vpr_seen
)
2137 first_error (_("VPR expected last"));
2141 /* Final test -- the registers must be consecutive. */
2143 for (i
= 0; i
< count
; i
++)
2145 if ((mask
& (1u << i
)) == 0)
2147 inst
.error
= _("non-contiguous register range");
2157 /* True if two alias types are the same. */
2160 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2168 if (a
->defined
!= b
->defined
)
2171 if ((a
->defined
& NTA_HASTYPE
) != 0
2172 && (a
->eltype
.type
!= b
->eltype
.type
2173 || a
->eltype
.size
!= b
->eltype
.size
))
2176 if ((a
->defined
& NTA_HASINDEX
) != 0
2177 && (a
->index
!= b
->index
))
2183 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2184 The base register is put in *PBASE.
2185 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2187 The register stride (minus one) is put in bit 4 of the return value.
2188 Bits [6:5] encode the list length (minus one).
2189 The type of the list elements is put in *ELTYPE, if non-NULL. */
2191 #define NEON_LANE(X) ((X) & 0xf)
2192 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2193 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2196 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2197 struct neon_type_el
*eltype
)
2204 int leading_brace
= 0;
2205 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2206 const char *const incr_error
= _("register stride must be 1 or 2");
2207 const char *const type_error
= _("mismatched element/structure types in list");
2208 struct neon_typed_alias firsttype
;
2209 firsttype
.defined
= 0;
2210 firsttype
.eltype
.type
= NT_invtype
;
2211 firsttype
.eltype
.size
= -1;
2212 firsttype
.index
= -1;
2214 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2219 struct neon_typed_alias atype
;
2220 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2224 first_error (_(reg_expected_msgs
[rtype
]));
2231 if (rtype
== REG_TYPE_NQ
)
2237 else if (reg_incr
== -1)
2239 reg_incr
= getreg
- base_reg
;
2240 if (reg_incr
< 1 || reg_incr
> 2)
2242 first_error (_(incr_error
));
2246 else if (getreg
!= base_reg
+ reg_incr
* count
)
2248 first_error (_(incr_error
));
2252 if (! neon_alias_types_same (&atype
, &firsttype
))
2254 first_error (_(type_error
));
2258 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2262 struct neon_typed_alias htype
;
2263 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2265 lane
= NEON_INTERLEAVE_LANES
;
2266 else if (lane
!= NEON_INTERLEAVE_LANES
)
2268 first_error (_(type_error
));
2273 else if (reg_incr
!= 1)
2275 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2279 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2282 first_error (_(reg_expected_msgs
[rtype
]));
2285 if (! neon_alias_types_same (&htype
, &firsttype
))
2287 first_error (_(type_error
));
2290 count
+= hireg
+ dregs
- getreg
;
2294 /* If we're using Q registers, we can't use [] or [n] syntax. */
2295 if (rtype
== REG_TYPE_NQ
)
2301 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2305 else if (lane
!= atype
.index
)
2307 first_error (_(type_error
));
2311 else if (lane
== -1)
2312 lane
= NEON_INTERLEAVE_LANES
;
2313 else if (lane
!= NEON_INTERLEAVE_LANES
)
2315 first_error (_(type_error
));
2320 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2322 /* No lane set by [x]. We must be interleaving structures. */
2324 lane
= NEON_INTERLEAVE_LANES
;
2327 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2328 || (count
> 1 && reg_incr
== -1))
2330 first_error (_("error parsing element/structure list"));
2334 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2336 first_error (_("expected }"));
2344 *eltype
= firsttype
.eltype
;
2349 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2352 /* Parse an explicit relocation suffix on an expression. This is
2353 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2354 arm_reloc_hsh contains no entries, so this function can only
2355 succeed if there is no () after the word. Returns -1 on error,
2356 BFD_RELOC_UNUSED if there wasn't any suffix. */
2359 parse_reloc (char **str
)
2361 struct reloc_entry
*r
;
2365 return BFD_RELOC_UNUSED
;
2370 while (*q
&& *q
!= ')' && *q
!= ',')
2375 if ((r
= (struct reloc_entry
*)
2376 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2383 /* Directives: register aliases. */
2385 static struct reg_entry
*
2386 insert_reg_alias (char *str
, unsigned number
, int type
)
2388 struct reg_entry
*new_reg
;
2391 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2393 if (new_reg
->builtin
)
2394 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2396 /* Only warn about a redefinition if it's not defined as the
2398 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2399 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2404 name
= xstrdup (str
);
2405 new_reg
= XNEW (struct reg_entry
);
2407 new_reg
->name
= name
;
2408 new_reg
->number
= number
;
2409 new_reg
->type
= type
;
2410 new_reg
->builtin
= FALSE
;
2411 new_reg
->neon
= NULL
;
2413 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2420 insert_neon_reg_alias (char *str
, int number
, int type
,
2421 struct neon_typed_alias
*atype
)
2423 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2427 first_error (_("attempt to redefine typed alias"));
2433 reg
->neon
= XNEW (struct neon_typed_alias
);
2434 *reg
->neon
= *atype
;
2438 /* Look for the .req directive. This is of the form:
2440 new_register_name .req existing_register_name
2442 If we find one, or if it looks sufficiently like one that we want to
2443 handle any error here, return TRUE. Otherwise return FALSE. */
2446 create_register_alias (char * newname
, char *p
)
2448 struct reg_entry
*old
;
2449 char *oldname
, *nbuf
;
2452 /* The input scrubber ensures that whitespace after the mnemonic is
2453 collapsed to single spaces. */
2455 if (strncmp (oldname
, " .req ", 6) != 0)
2459 if (*oldname
== '\0')
2462 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2465 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2469 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2470 the desired alias name, and p points to its end. If not, then
2471 the desired alias name is in the global original_case_string. */
2472 #ifdef TC_CASE_SENSITIVE
2475 newname
= original_case_string
;
2476 nlen
= strlen (newname
);
2479 nbuf
= xmemdup0 (newname
, nlen
);
2481 /* Create aliases under the new name as stated; an all-lowercase
2482 version of the new name; and an all-uppercase version of the new
2484 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2486 for (p
= nbuf
; *p
; p
++)
2489 if (strncmp (nbuf
, newname
, nlen
))
2491 /* If this attempt to create an additional alias fails, do not bother
2492 trying to create the all-lower case alias. We will fail and issue
2493 a second, duplicate error message. This situation arises when the
2494 programmer does something like:
2497 The second .req creates the "Foo" alias but then fails to create
2498 the artificial FOO alias because it has already been created by the
2500 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2507 for (p
= nbuf
; *p
; p
++)
2510 if (strncmp (nbuf
, newname
, nlen
))
2511 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2518 /* Create a Neon typed/indexed register alias using directives, e.g.:
2523 These typed registers can be used instead of the types specified after the
2524 Neon mnemonic, so long as all operands given have types. Types can also be
2525 specified directly, e.g.:
2526 vadd d0.s32, d1.s32, d2.s32 */
2529 create_neon_reg_alias (char *newname
, char *p
)
2531 enum arm_reg_type basetype
;
2532 struct reg_entry
*basereg
;
2533 struct reg_entry mybasereg
;
2534 struct neon_type ntype
;
2535 struct neon_typed_alias typeinfo
;
2536 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2539 typeinfo
.defined
= 0;
2540 typeinfo
.eltype
.type
= NT_invtype
;
2541 typeinfo
.eltype
.size
= -1;
2542 typeinfo
.index
= -1;
2546 if (strncmp (p
, " .dn ", 5) == 0)
2547 basetype
= REG_TYPE_VFD
;
2548 else if (strncmp (p
, " .qn ", 5) == 0)
2549 basetype
= REG_TYPE_NQ
;
2558 basereg
= arm_reg_parse_multi (&p
);
2560 if (basereg
&& basereg
->type
!= basetype
)
2562 as_bad (_("bad type for register"));
2566 if (basereg
== NULL
)
2569 /* Try parsing as an integer. */
2570 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2571 if (exp
.X_op
!= O_constant
)
2573 as_bad (_("expression must be constant"));
2576 basereg
= &mybasereg
;
2577 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2583 typeinfo
= *basereg
->neon
;
2585 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2587 /* We got a type. */
2588 if (typeinfo
.defined
& NTA_HASTYPE
)
2590 as_bad (_("can't redefine the type of a register alias"));
2594 typeinfo
.defined
|= NTA_HASTYPE
;
2595 if (ntype
.elems
!= 1)
2597 as_bad (_("you must specify a single type only"));
2600 typeinfo
.eltype
= ntype
.el
[0];
2603 if (skip_past_char (&p
, '[') == SUCCESS
)
2606 /* We got a scalar index. */
2608 if (typeinfo
.defined
& NTA_HASINDEX
)
2610 as_bad (_("can't redefine the index of a scalar alias"));
2614 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2616 if (exp
.X_op
!= O_constant
)
2618 as_bad (_("scalar index must be constant"));
2622 typeinfo
.defined
|= NTA_HASINDEX
;
2623 typeinfo
.index
= exp
.X_add_number
;
2625 if (skip_past_char (&p
, ']') == FAIL
)
2627 as_bad (_("expecting ]"));
2632 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2633 the desired alias name, and p points to its end. If not, then
2634 the desired alias name is in the global original_case_string. */
2635 #ifdef TC_CASE_SENSITIVE
2636 namelen
= nameend
- newname
;
2638 newname
= original_case_string
;
2639 namelen
= strlen (newname
);
2642 namebuf
= xmemdup0 (newname
, namelen
);
2644 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2645 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2647 /* Insert name in all uppercase. */
2648 for (p
= namebuf
; *p
; p
++)
2651 if (strncmp (namebuf
, newname
, namelen
))
2652 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2653 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2655 /* Insert name in all lowercase. */
2656 for (p
= namebuf
; *p
; p
++)
2659 if (strncmp (namebuf
, newname
, namelen
))
2660 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2661 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2667 /* Should never be called, as .req goes between the alias and the
2668 register name, not at the beginning of the line. */
2671 s_req (int a ATTRIBUTE_UNUSED
)
2673 as_bad (_("invalid syntax for .req directive"));
2677 s_dn (int a ATTRIBUTE_UNUSED
)
2679 as_bad (_("invalid syntax for .dn directive"));
2683 s_qn (int a ATTRIBUTE_UNUSED
)
2685 as_bad (_("invalid syntax for .qn directive"));
2688 /* The .unreq directive deletes an alias which was previously defined
2689 by .req. For example:
2695 s_unreq (int a ATTRIBUTE_UNUSED
)
2700 name
= input_line_pointer
;
2702 while (*input_line_pointer
!= 0
2703 && *input_line_pointer
!= ' '
2704 && *input_line_pointer
!= '\n')
2705 ++input_line_pointer
;
2707 saved_char
= *input_line_pointer
;
2708 *input_line_pointer
= 0;
2711 as_bad (_("invalid syntax for .unreq directive"));
2714 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2718 as_bad (_("unknown register alias '%s'"), name
);
2719 else if (reg
->builtin
)
2720 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2727 hash_delete (arm_reg_hsh
, name
, FALSE
);
2728 free ((char *) reg
->name
);
2733 /* Also locate the all upper case and all lower case versions.
2734 Do not complain if we cannot find one or the other as it
2735 was probably deleted above. */
2737 nbuf
= strdup (name
);
2738 for (p
= nbuf
; *p
; p
++)
2740 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2743 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2744 free ((char *) reg
->name
);
2750 for (p
= nbuf
; *p
; p
++)
2752 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2755 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2756 free ((char *) reg
->name
);
2766 *input_line_pointer
= saved_char
;
2767 demand_empty_rest_of_line ();
2770 /* Directives: Instruction set selection. */
2773 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2774 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2775 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2776 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2778 /* Create a new mapping symbol for the transition to STATE. */
2781 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2784 const char * symname
;
2791 type
= BSF_NO_FLAGS
;
2795 type
= BSF_NO_FLAGS
;
2799 type
= BSF_NO_FLAGS
;
2805 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2806 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2811 THUMB_SET_FUNC (symbolP
, 0);
2812 ARM_SET_THUMB (symbolP
, 0);
2813 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2817 THUMB_SET_FUNC (symbolP
, 1);
2818 ARM_SET_THUMB (symbolP
, 1);
2819 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2827 /* Save the mapping symbols for future reference. Also check that
2828 we do not place two mapping symbols at the same offset within a
2829 frag. We'll handle overlap between frags in
2830 check_mapping_symbols.
2832 If .fill or other data filling directive generates zero sized data,
2833 the mapping symbol for the following code will have the same value
2834 as the one generated for the data filling directive. In this case,
2835 we replace the old symbol with the new one at the same address. */
2838 if (frag
->tc_frag_data
.first_map
!= NULL
)
2840 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2841 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2843 frag
->tc_frag_data
.first_map
= symbolP
;
2845 if (frag
->tc_frag_data
.last_map
!= NULL
)
2847 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2848 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2849 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2851 frag
->tc_frag_data
.last_map
= symbolP
;
2854 /* We must sometimes convert a region marked as code to data during
2855 code alignment, if an odd number of bytes have to be padded. The
2856 code mapping symbol is pushed to an aligned address. */
2859 insert_data_mapping_symbol (enum mstate state
,
2860 valueT value
, fragS
*frag
, offsetT bytes
)
2862 /* If there was already a mapping symbol, remove it. */
2863 if (frag
->tc_frag_data
.last_map
!= NULL
2864 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2866 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2870 know (frag
->tc_frag_data
.first_map
== symp
);
2871 frag
->tc_frag_data
.first_map
= NULL
;
2873 frag
->tc_frag_data
.last_map
= NULL
;
2874 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2877 make_mapping_symbol (MAP_DATA
, value
, frag
);
2878 make_mapping_symbol (state
, value
+ bytes
, frag
);
2881 static void mapping_state_2 (enum mstate state
, int max_chars
);
2883 /* Set the mapping state to STATE. Only call this when about to
2884 emit some STATE bytes to the file. */
2886 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2888 mapping_state (enum mstate state
)
2890 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2892 if (mapstate
== state
)
2893 /* The mapping symbol has already been emitted.
2894 There is nothing else to do. */
2897 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2899 All ARM instructions require 4-byte alignment.
2900 (Almost) all Thumb instructions require 2-byte alignment.
2902 When emitting instructions into any section, mark the section
2905 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2906 but themselves require 2-byte alignment; this applies to some
2907 PC- relative forms. However, these cases will involve implicit
2908 literal pool generation or an explicit .align >=2, both of
2909 which will cause the section to me marked with sufficient
2910 alignment. Thus, we don't handle those cases here. */
2911 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2913 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2914 /* This case will be evaluated later. */
2917 mapping_state_2 (state
, 0);
2920 /* Same as mapping_state, but MAX_CHARS bytes have already been
2921 allocated. Put the mapping symbol that far back. */
2924 mapping_state_2 (enum mstate state
, int max_chars
)
2926 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2928 if (!SEG_NORMAL (now_seg
))
2931 if (mapstate
== state
)
2932 /* The mapping symbol has already been emitted.
2933 There is nothing else to do. */
2936 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2937 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2939 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2940 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2943 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2946 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2947 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2951 #define mapping_state(x) ((void)0)
2952 #define mapping_state_2(x, y) ((void)0)
2955 /* Find the real, Thumb encoded start of a Thumb function. */
2959 find_real_start (symbolS
* symbolP
)
2962 const char * name
= S_GET_NAME (symbolP
);
2963 symbolS
* new_target
;
2965 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2966 #define STUB_NAME ".real_start_of"
2971 /* The compiler may generate BL instructions to local labels because
2972 it needs to perform a branch to a far away location. These labels
2973 do not have a corresponding ".real_start_of" label. We check
2974 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2975 the ".real_start_of" convention for nonlocal branches. */
2976 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2979 real_start
= concat (STUB_NAME
, name
, NULL
);
2980 new_target
= symbol_find (real_start
);
2983 if (new_target
== NULL
)
2985 as_warn (_("Failed to find real start of function: %s\n"), name
);
2986 new_target
= symbolP
;
2994 opcode_select (int width
)
3001 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3002 as_bad (_("selected processor does not support THUMB opcodes"));
3005 /* No need to force the alignment, since we will have been
3006 coming from ARM mode, which is word-aligned. */
3007 record_alignment (now_seg
, 1);
3014 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3015 as_bad (_("selected processor does not support ARM opcodes"));
3020 frag_align (2, 0, 0);
3022 record_alignment (now_seg
, 1);
3027 as_bad (_("invalid instruction size selected (%d)"), width
);
3032 s_arm (int ignore ATTRIBUTE_UNUSED
)
3035 demand_empty_rest_of_line ();
3039 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3042 demand_empty_rest_of_line ();
3046 s_code (int unused ATTRIBUTE_UNUSED
)
3050 temp
= get_absolute_expression ();
3055 opcode_select (temp
);
3059 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3064 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3066 /* If we are not already in thumb mode go into it, EVEN if
3067 the target processor does not support thumb instructions.
3068 This is used by gcc/config/arm/lib1funcs.asm for example
3069 to compile interworking support functions even if the
3070 target processor should not support interworking. */
3074 record_alignment (now_seg
, 1);
3077 demand_empty_rest_of_line ();
3081 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3085 /* The following label is the name/address of the start of a Thumb function.
3086 We need to know this for the interworking support. */
3087 label_is_thumb_function_name
= TRUE
;
3090 /* Perform a .set directive, but also mark the alias as
3091 being a thumb function. */
3094 s_thumb_set (int equiv
)
3096 /* XXX the following is a duplicate of the code for s_set() in read.c
3097 We cannot just call that code as we need to get at the symbol that
3104 /* Especial apologies for the random logic:
3105 This just grew, and could be parsed much more simply!
3107 delim
= get_symbol_name (& name
);
3108 end_name
= input_line_pointer
;
3109 (void) restore_line_pointer (delim
);
3111 if (*input_line_pointer
!= ',')
3114 as_bad (_("expected comma after name \"%s\""), name
);
3116 ignore_rest_of_line ();
3120 input_line_pointer
++;
3123 if (name
[0] == '.' && name
[1] == '\0')
3125 /* XXX - this should not happen to .thumb_set. */
3129 if ((symbolP
= symbol_find (name
)) == NULL
3130 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3133 /* When doing symbol listings, play games with dummy fragments living
3134 outside the normal fragment chain to record the file and line info
3136 if (listing
& LISTING_SYMBOLS
)
3138 extern struct list_info_struct
* listing_tail
;
3139 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3141 memset (dummy_frag
, 0, sizeof (fragS
));
3142 dummy_frag
->fr_type
= rs_fill
;
3143 dummy_frag
->line
= listing_tail
;
3144 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3145 dummy_frag
->fr_symbol
= symbolP
;
3149 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3152 /* "set" symbols are local unless otherwise specified. */
3153 SF_SET_LOCAL (symbolP
);
3154 #endif /* OBJ_COFF */
3155 } /* Make a new symbol. */
3157 symbol_table_insert (symbolP
);
3162 && S_IS_DEFINED (symbolP
)
3163 && S_GET_SEGMENT (symbolP
) != reg_section
)
3164 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3166 pseudo_set (symbolP
);
3168 demand_empty_rest_of_line ();
3170 /* XXX Now we come to the Thumb specific bit of code. */
3172 THUMB_SET_FUNC (symbolP
, 1);
3173 ARM_SET_THUMB (symbolP
, 1);
3174 #if defined OBJ_ELF || defined OBJ_COFF
3175 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3179 /* Directives: Mode selection. */
3181 /* .syntax [unified|divided] - choose the new unified syntax
3182 (same for Arm and Thumb encoding, modulo slight differences in what
3183 can be represented) or the old divergent syntax for each mode. */
3185 s_syntax (int unused ATTRIBUTE_UNUSED
)
3189 delim
= get_symbol_name (& name
);
3191 if (!strcasecmp (name
, "unified"))
3192 unified_syntax
= TRUE
;
3193 else if (!strcasecmp (name
, "divided"))
3194 unified_syntax
= FALSE
;
3197 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3200 (void) restore_line_pointer (delim
);
3201 demand_empty_rest_of_line ();
3204 /* Directives: sectioning and alignment. */
3207 s_bss (int ignore ATTRIBUTE_UNUSED
)
3209 /* We don't support putting frags in the BSS segment, we fake it by
3210 marking in_bss, then looking at s_skip for clues. */
3211 subseg_set (bss_section
, 0);
3212 demand_empty_rest_of_line ();
3214 #ifdef md_elf_section_change_hook
3215 md_elf_section_change_hook ();
3220 s_even (int ignore ATTRIBUTE_UNUSED
)
3222 /* Never make frag if expect extra pass. */
3224 frag_align (1, 0, 0);
3226 record_alignment (now_seg
, 1);
3228 demand_empty_rest_of_line ();
3231 /* Directives: CodeComposer Studio. */
3233 /* .ref (for CodeComposer Studio syntax only). */
3235 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3237 if (codecomposer_syntax
)
3238 ignore_rest_of_line ();
3240 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3243 /* If name is not NULL, then it is used for marking the beginning of a
3244 function, whereas if it is NULL then it means the function end. */
3246 asmfunc_debug (const char * name
)
3248 static const char * last_name
= NULL
;
3252 gas_assert (last_name
== NULL
);
3255 if (debug_type
== DEBUG_STABS
)
3256 stabs_generate_asm_func (name
, name
);
3260 gas_assert (last_name
!= NULL
);
3262 if (debug_type
== DEBUG_STABS
)
3263 stabs_generate_asm_endfunc (last_name
, last_name
);
3270 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3272 if (codecomposer_syntax
)
3274 switch (asmfunc_state
)
3276 case OUTSIDE_ASMFUNC
:
3277 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3280 case WAITING_ASMFUNC_NAME
:
3281 as_bad (_(".asmfunc repeated."));
3284 case WAITING_ENDASMFUNC
:
3285 as_bad (_(".asmfunc without function."));
3288 demand_empty_rest_of_line ();
3291 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3295 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3297 if (codecomposer_syntax
)
3299 switch (asmfunc_state
)
3301 case OUTSIDE_ASMFUNC
:
3302 as_bad (_(".endasmfunc without a .asmfunc."));
3305 case WAITING_ASMFUNC_NAME
:
3306 as_bad (_(".endasmfunc without function."));
3309 case WAITING_ENDASMFUNC
:
3310 asmfunc_state
= OUTSIDE_ASMFUNC
;
3311 asmfunc_debug (NULL
);
3314 demand_empty_rest_of_line ();
3317 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3321 s_ccs_def (int name
)
3323 if (codecomposer_syntax
)
3326 as_bad (_(".def pseudo-op only available with -mccs flag."));
3329 /* Directives: Literal pools. */
3331 static literal_pool
*
3332 find_literal_pool (void)
3334 literal_pool
* pool
;
3336 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3338 if (pool
->section
== now_seg
3339 && pool
->sub_section
== now_subseg
)
3346 static literal_pool
*
3347 find_or_make_literal_pool (void)
3349 /* Next literal pool ID number. */
3350 static unsigned int latest_pool_num
= 1;
3351 literal_pool
* pool
;
3353 pool
= find_literal_pool ();
3357 /* Create a new pool. */
3358 pool
= XNEW (literal_pool
);
3362 pool
->next_free_entry
= 0;
3363 pool
->section
= now_seg
;
3364 pool
->sub_section
= now_subseg
;
3365 pool
->next
= list_of_pools
;
3366 pool
->symbol
= NULL
;
3367 pool
->alignment
= 2;
3369 /* Add it to the list. */
3370 list_of_pools
= pool
;
3373 /* New pools, and emptied pools, will have a NULL symbol. */
3374 if (pool
->symbol
== NULL
)
3376 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3377 (valueT
) 0, &zero_address_frag
);
3378 pool
->id
= latest_pool_num
++;
3385 /* Add the literal in the global 'inst'
3386 structure to the relevant literal pool. */
3389 add_to_lit_pool (unsigned int nbytes
)
3391 #define PADDING_SLOT 0x1
3392 #define LIT_ENTRY_SIZE_MASK 0xFF
3393 literal_pool
* pool
;
3394 unsigned int entry
, pool_size
= 0;
3395 bfd_boolean padding_slot_p
= FALSE
;
3401 imm1
= inst
.operands
[1].imm
;
3402 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3403 : inst
.relocs
[0].exp
.X_unsigned
? 0
3404 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3405 if (target_big_endian
)
3408 imm2
= inst
.operands
[1].imm
;
3412 pool
= find_or_make_literal_pool ();
3414 /* Check if this literal value is already in the pool. */
3415 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3419 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3420 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3421 && (pool
->literals
[entry
].X_add_number
3422 == inst
.relocs
[0].exp
.X_add_number
)
3423 && (pool
->literals
[entry
].X_md
== nbytes
)
3424 && (pool
->literals
[entry
].X_unsigned
3425 == inst
.relocs
[0].exp
.X_unsigned
))
3428 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3429 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3430 && (pool
->literals
[entry
].X_add_number
3431 == inst
.relocs
[0].exp
.X_add_number
)
3432 && (pool
->literals
[entry
].X_add_symbol
3433 == inst
.relocs
[0].exp
.X_add_symbol
)
3434 && (pool
->literals
[entry
].X_op_symbol
3435 == inst
.relocs
[0].exp
.X_op_symbol
)
3436 && (pool
->literals
[entry
].X_md
== nbytes
))
3439 else if ((nbytes
== 8)
3440 && !(pool_size
& 0x7)
3441 && ((entry
+ 1) != pool
->next_free_entry
)
3442 && (pool
->literals
[entry
].X_op
== O_constant
)
3443 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3444 && (pool
->literals
[entry
].X_unsigned
3445 == inst
.relocs
[0].exp
.X_unsigned
)
3446 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3447 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3448 && (pool
->literals
[entry
+ 1].X_unsigned
3449 == inst
.relocs
[0].exp
.X_unsigned
))
3452 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3453 if (padding_slot_p
&& (nbytes
== 4))
3459 /* Do we need to create a new entry? */
3460 if (entry
== pool
->next_free_entry
)
3462 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3464 inst
.error
= _("literal pool overflow");
3470 /* For 8-byte entries, we align to an 8-byte boundary,
3471 and split it into two 4-byte entries, because on 32-bit
3472 host, 8-byte constants are treated as big num, thus
3473 saved in "generic_bignum" which will be overwritten
3474 by later assignments.
3476 We also need to make sure there is enough space for
3479 We also check to make sure the literal operand is a
3481 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3482 || inst
.relocs
[0].exp
.X_op
== O_big
))
3484 inst
.error
= _("invalid type for literal pool");
3487 else if (pool_size
& 0x7)
3489 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3491 inst
.error
= _("literal pool overflow");
3495 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3496 pool
->literals
[entry
].X_op
= O_constant
;
3497 pool
->literals
[entry
].X_add_number
= 0;
3498 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3499 pool
->next_free_entry
+= 1;
3502 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3504 inst
.error
= _("literal pool overflow");
3508 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3509 pool
->literals
[entry
].X_op
= O_constant
;
3510 pool
->literals
[entry
].X_add_number
= imm1
;
3511 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3512 pool
->literals
[entry
++].X_md
= 4;
3513 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3514 pool
->literals
[entry
].X_op
= O_constant
;
3515 pool
->literals
[entry
].X_add_number
= imm2
;
3516 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3517 pool
->literals
[entry
].X_md
= 4;
3518 pool
->alignment
= 3;
3519 pool
->next_free_entry
+= 1;
3523 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3524 pool
->literals
[entry
].X_md
= 4;
3528 /* PR ld/12974: Record the location of the first source line to reference
3529 this entry in the literal pool. If it turns out during linking that the
3530 symbol does not exist we will be able to give an accurate line number for
3531 the (first use of the) missing reference. */
3532 if (debug_type
== DEBUG_DWARF2
)
3533 dwarf2_where (pool
->locs
+ entry
);
3535 pool
->next_free_entry
+= 1;
3537 else if (padding_slot_p
)
3539 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3540 pool
->literals
[entry
].X_md
= nbytes
;
3543 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3544 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3545 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3551 tc_start_label_without_colon (void)
3553 bfd_boolean ret
= TRUE
;
3555 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3557 const char *label
= input_line_pointer
;
3559 while (!is_end_of_line
[(int) label
[-1]])
3564 as_bad (_("Invalid label '%s'"), label
);
3568 asmfunc_debug (label
);
3570 asmfunc_state
= WAITING_ENDASMFUNC
;
3576 /* Can't use symbol_new here, so have to create a symbol and then at
3577 a later date assign it a value. That's what these functions do. */
3580 symbol_locate (symbolS
* symbolP
,
3581 const char * name
, /* It is copied, the caller can modify. */
3582 segT segment
, /* Segment identifier (SEG_<something>). */
3583 valueT valu
, /* Symbol value. */
3584 fragS
* frag
) /* Associated fragment. */
3587 char * preserved_copy_of_name
;
3589 name_length
= strlen (name
) + 1; /* +1 for \0. */
3590 obstack_grow (¬es
, name
, name_length
);
3591 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3593 #ifdef tc_canonicalize_symbol_name
3594 preserved_copy_of_name
=
3595 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3598 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3600 S_SET_SEGMENT (symbolP
, segment
);
3601 S_SET_VALUE (symbolP
, valu
);
3602 symbol_clear_list_pointers (symbolP
);
3604 symbol_set_frag (symbolP
, frag
);
3606 /* Link to end of symbol chain. */
3608 extern int symbol_table_frozen
;
3610 if (symbol_table_frozen
)
3614 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3616 obj_symbol_new_hook (symbolP
);
3618 #ifdef tc_symbol_new_hook
3619 tc_symbol_new_hook (symbolP
);
3623 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3624 #endif /* DEBUG_SYMS */
3628 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3631 literal_pool
* pool
;
3634 pool
= find_literal_pool ();
3636 || pool
->symbol
== NULL
3637 || pool
->next_free_entry
== 0)
3640 /* Align pool as you have word accesses.
3641 Only make a frag if we have to. */
3643 frag_align (pool
->alignment
, 0, 0);
3645 record_alignment (now_seg
, 2);
3648 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3649 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3651 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3653 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3654 (valueT
) frag_now_fix (), frag_now
);
3655 symbol_table_insert (pool
->symbol
);
3657 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3659 #if defined OBJ_COFF || defined OBJ_ELF
3660 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3663 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3666 if (debug_type
== DEBUG_DWARF2
)
3667 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3669 /* First output the expression in the instruction to the pool. */
3670 emit_expr (&(pool
->literals
[entry
]),
3671 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3674 /* Mark the pool as empty. */
3675 pool
->next_free_entry
= 0;
3676 pool
->symbol
= NULL
;
3680 /* Forward declarations for functions below, in the MD interface
3682 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3683 static valueT
create_unwind_entry (int);
3684 static void start_unwind_section (const segT
, int);
3685 static void add_unwind_opcode (valueT
, int);
3686 static void flush_pending_unwind (void);
3688 /* Directives: Data. */
3691 s_arm_elf_cons (int nbytes
)
3695 #ifdef md_flush_pending_output
3696 md_flush_pending_output ();
3699 if (is_it_end_of_statement ())
3701 demand_empty_rest_of_line ();
3705 #ifdef md_cons_align
3706 md_cons_align (nbytes
);
3709 mapping_state (MAP_DATA
);
3713 char *base
= input_line_pointer
;
3717 if (exp
.X_op
!= O_symbol
)
3718 emit_expr (&exp
, (unsigned int) nbytes
);
3721 char *before_reloc
= input_line_pointer
;
3722 reloc
= parse_reloc (&input_line_pointer
);
3725 as_bad (_("unrecognized relocation suffix"));
3726 ignore_rest_of_line ();
3729 else if (reloc
== BFD_RELOC_UNUSED
)
3730 emit_expr (&exp
, (unsigned int) nbytes
);
3733 reloc_howto_type
*howto
= (reloc_howto_type
*)
3734 bfd_reloc_type_lookup (stdoutput
,
3735 (bfd_reloc_code_real_type
) reloc
);
3736 int size
= bfd_get_reloc_size (howto
);
3738 if (reloc
== BFD_RELOC_ARM_PLT32
)
3740 as_bad (_("(plt) is only valid on branch targets"));
3741 reloc
= BFD_RELOC_UNUSED
;
3746 as_bad (ngettext ("%s relocations do not fit in %d byte",
3747 "%s relocations do not fit in %d bytes",
3749 howto
->name
, nbytes
);
3752 /* We've parsed an expression stopping at O_symbol.
3753 But there may be more expression left now that we
3754 have parsed the relocation marker. Parse it again.
3755 XXX Surely there is a cleaner way to do this. */
3756 char *p
= input_line_pointer
;
3758 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3760 memcpy (save_buf
, base
, input_line_pointer
- base
);
3761 memmove (base
+ (input_line_pointer
- before_reloc
),
3762 base
, before_reloc
- base
);
3764 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3766 memcpy (base
, save_buf
, p
- base
);
3768 offset
= nbytes
- size
;
3769 p
= frag_more (nbytes
);
3770 memset (p
, 0, nbytes
);
3771 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3772 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3778 while (*input_line_pointer
++ == ',');
3780 /* Put terminator back into stream. */
3781 input_line_pointer
--;
3782 demand_empty_rest_of_line ();
3785 /* Emit an expression containing a 32-bit thumb instruction.
3786 Implementation based on put_thumb32_insn. */
3789 emit_thumb32_expr (expressionS
* exp
)
3791 expressionS exp_high
= *exp
;
3793 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3794 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3795 exp
->X_add_number
&= 0xffff;
3796 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3799 /* Guess the instruction size based on the opcode. */
3802 thumb_insn_size (int opcode
)
3804 if ((unsigned int) opcode
< 0xe800u
)
3806 else if ((unsigned int) opcode
>= 0xe8000000u
)
3813 emit_insn (expressionS
*exp
, int nbytes
)
3817 if (exp
->X_op
== O_constant
)
3822 size
= thumb_insn_size (exp
->X_add_number
);
3826 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3828 as_bad (_(".inst.n operand too big. "\
3829 "Use .inst.w instead"));
3834 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3835 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3837 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3839 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3840 emit_thumb32_expr (exp
);
3842 emit_expr (exp
, (unsigned int) size
);
3844 it_fsm_post_encode ();
3848 as_bad (_("cannot determine Thumb instruction size. " \
3849 "Use .inst.n/.inst.w instead"));
3852 as_bad (_("constant expression required"));
3857 /* Like s_arm_elf_cons but do not use md_cons_align and
3858 set the mapping state to MAP_ARM/MAP_THUMB. */
3861 s_arm_elf_inst (int nbytes
)
3863 if (is_it_end_of_statement ())
3865 demand_empty_rest_of_line ();
3869 /* Calling mapping_state () here will not change ARM/THUMB,
3870 but will ensure not to be in DATA state. */
3873 mapping_state (MAP_THUMB
);
3878 as_bad (_("width suffixes are invalid in ARM mode"));
3879 ignore_rest_of_line ();
3885 mapping_state (MAP_ARM
);
3894 if (! emit_insn (& exp
, nbytes
))
3896 ignore_rest_of_line ();
3900 while (*input_line_pointer
++ == ',');
3902 /* Put terminator back into stream. */
3903 input_line_pointer
--;
3904 demand_empty_rest_of_line ();
3907 /* Parse a .rel31 directive. */
3910 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3917 if (*input_line_pointer
== '1')
3918 highbit
= 0x80000000;
3919 else if (*input_line_pointer
!= '0')
3920 as_bad (_("expected 0 or 1"));
3922 input_line_pointer
++;
3923 if (*input_line_pointer
!= ',')
3924 as_bad (_("missing comma"));
3925 input_line_pointer
++;
3927 #ifdef md_flush_pending_output
3928 md_flush_pending_output ();
3931 #ifdef md_cons_align
3935 mapping_state (MAP_DATA
);
3940 md_number_to_chars (p
, highbit
, 4);
3941 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3942 BFD_RELOC_ARM_PREL31
);
3944 demand_empty_rest_of_line ();
3947 /* Directives: AEABI stack-unwind tables. */
3949 /* Parse an unwind_fnstart directive. Simply records the current location. */
3952 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3954 demand_empty_rest_of_line ();
3955 if (unwind
.proc_start
)
3957 as_bad (_("duplicate .fnstart directive"));
3961 /* Mark the start of the function. */
3962 unwind
.proc_start
= expr_build_dot ();
3964 /* Reset the rest of the unwind info. */
3965 unwind
.opcode_count
= 0;
3966 unwind
.table_entry
= NULL
;
3967 unwind
.personality_routine
= NULL
;
3968 unwind
.personality_index
= -1;
3969 unwind
.frame_size
= 0;
3970 unwind
.fp_offset
= 0;
3971 unwind
.fp_reg
= REG_SP
;
3973 unwind
.sp_restored
= 0;
3977 /* Parse a handlerdata directive. Creates the exception handling table entry
3978 for the function. */
3981 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3983 demand_empty_rest_of_line ();
3984 if (!unwind
.proc_start
)
3985 as_bad (MISSING_FNSTART
);
3987 if (unwind
.table_entry
)
3988 as_bad (_("duplicate .handlerdata directive"));
3990 create_unwind_entry (1);
3993 /* Parse an unwind_fnend directive. Generates the index table entry. */
3996 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4001 unsigned int marked_pr_dependency
;
4003 demand_empty_rest_of_line ();
4005 if (!unwind
.proc_start
)
4007 as_bad (_(".fnend directive without .fnstart"));
4011 /* Add eh table entry. */
4012 if (unwind
.table_entry
== NULL
)
4013 val
= create_unwind_entry (0);
4017 /* Add index table entry. This is two words. */
4018 start_unwind_section (unwind
.saved_seg
, 1);
4019 frag_align (2, 0, 0);
4020 record_alignment (now_seg
, 2);
4022 ptr
= frag_more (8);
4024 where
= frag_now_fix () - 8;
4026 /* Self relative offset of the function start. */
4027 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4028 BFD_RELOC_ARM_PREL31
);
4030 /* Indicate dependency on EHABI-defined personality routines to the
4031 linker, if it hasn't been done already. */
4032 marked_pr_dependency
4033 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4034 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4035 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4037 static const char *const name
[] =
4039 "__aeabi_unwind_cpp_pr0",
4040 "__aeabi_unwind_cpp_pr1",
4041 "__aeabi_unwind_cpp_pr2"
4043 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4044 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4045 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4046 |= 1 << unwind
.personality_index
;
4050 /* Inline exception table entry. */
4051 md_number_to_chars (ptr
+ 4, val
, 4);
4053 /* Self relative offset of the table entry. */
4054 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4055 BFD_RELOC_ARM_PREL31
);
4057 /* Restore the original section. */
4058 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4060 unwind
.proc_start
= NULL
;
4064 /* Parse an unwind_cantunwind directive. */
4067 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4069 demand_empty_rest_of_line ();
4070 if (!unwind
.proc_start
)
4071 as_bad (MISSING_FNSTART
);
4073 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4074 as_bad (_("personality routine specified for cantunwind frame"));
4076 unwind
.personality_index
= -2;
4080 /* Parse a personalityindex directive. */
4083 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4087 if (!unwind
.proc_start
)
4088 as_bad (MISSING_FNSTART
);
4090 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4091 as_bad (_("duplicate .personalityindex directive"));
4095 if (exp
.X_op
!= O_constant
4096 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4098 as_bad (_("bad personality routine number"));
4099 ignore_rest_of_line ();
4103 unwind
.personality_index
= exp
.X_add_number
;
4105 demand_empty_rest_of_line ();
4109 /* Parse a personality directive. */
4112 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4116 if (!unwind
.proc_start
)
4117 as_bad (MISSING_FNSTART
);
4119 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4120 as_bad (_("duplicate .personality directive"));
4122 c
= get_symbol_name (& name
);
4123 p
= input_line_pointer
;
4125 ++ input_line_pointer
;
4126 unwind
.personality_routine
= symbol_find_or_make (name
);
4128 demand_empty_rest_of_line ();
4132 /* Parse a directive saving core registers. */
4135 s_arm_unwind_save_core (void)
4141 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4144 as_bad (_("expected register list"));
4145 ignore_rest_of_line ();
4149 demand_empty_rest_of_line ();
4151 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4152 into .unwind_save {..., sp...}. We aren't bothered about the value of
4153 ip because it is clobbered by calls. */
4154 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4155 && (range
& 0x3000) == 0x1000)
4157 unwind
.opcode_count
--;
4158 unwind
.sp_restored
= 0;
4159 range
= (range
| 0x2000) & ~0x1000;
4160 unwind
.pending_offset
= 0;
4166 /* See if we can use the short opcodes. These pop a block of up to 8
4167 registers starting with r4, plus maybe r14. */
4168 for (n
= 0; n
< 8; n
++)
4170 /* Break at the first non-saved register. */
4171 if ((range
& (1 << (n
+ 4))) == 0)
4174 /* See if there are any other bits set. */
4175 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4177 /* Use the long form. */
4178 op
= 0x8000 | ((range
>> 4) & 0xfff);
4179 add_unwind_opcode (op
, 2);
4183 /* Use the short form. */
4185 op
= 0xa8; /* Pop r14. */
4187 op
= 0xa0; /* Do not pop r14. */
4189 add_unwind_opcode (op
, 1);
4196 op
= 0xb100 | (range
& 0xf);
4197 add_unwind_opcode (op
, 2);
4200 /* Record the number of bytes pushed. */
4201 for (n
= 0; n
< 16; n
++)
4203 if (range
& (1 << n
))
4204 unwind
.frame_size
+= 4;
4209 /* Parse a directive saving FPA registers. */
4212 s_arm_unwind_save_fpa (int reg
)
4218 /* Get Number of registers to transfer. */
4219 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4222 exp
.X_op
= O_illegal
;
4224 if (exp
.X_op
!= O_constant
)
4226 as_bad (_("expected , <constant>"));
4227 ignore_rest_of_line ();
4231 num_regs
= exp
.X_add_number
;
4233 if (num_regs
< 1 || num_regs
> 4)
4235 as_bad (_("number of registers must be in the range [1:4]"));
4236 ignore_rest_of_line ();
4240 demand_empty_rest_of_line ();
4245 op
= 0xb4 | (num_regs
- 1);
4246 add_unwind_opcode (op
, 1);
4251 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4252 add_unwind_opcode (op
, 2);
4254 unwind
.frame_size
+= num_regs
* 12;
4258 /* Parse a directive saving VFP registers for ARMv6 and above. */
4261 s_arm_unwind_save_vfp_armv6 (void)
4266 int num_vfpv3_regs
= 0;
4267 int num_regs_below_16
;
4268 bfd_boolean partial_match
;
4270 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4274 as_bad (_("expected register list"));
4275 ignore_rest_of_line ();
4279 demand_empty_rest_of_line ();
4281 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4282 than FSTMX/FLDMX-style ones). */
4284 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4286 num_vfpv3_regs
= count
;
4287 else if (start
+ count
> 16)
4288 num_vfpv3_regs
= start
+ count
- 16;
4290 if (num_vfpv3_regs
> 0)
4292 int start_offset
= start
> 16 ? start
- 16 : 0;
4293 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4294 add_unwind_opcode (op
, 2);
4297 /* Generate opcode for registers numbered in the range 0 .. 15. */
4298 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4299 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4300 if (num_regs_below_16
> 0)
4302 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4303 add_unwind_opcode (op
, 2);
4306 unwind
.frame_size
+= count
* 8;
4310 /* Parse a directive saving VFP registers for pre-ARMv6. */
4313 s_arm_unwind_save_vfp (void)
4318 bfd_boolean partial_match
;
4320 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4324 as_bad (_("expected register list"));
4325 ignore_rest_of_line ();
4329 demand_empty_rest_of_line ();
4334 op
= 0xb8 | (count
- 1);
4335 add_unwind_opcode (op
, 1);
4340 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4341 add_unwind_opcode (op
, 2);
4343 unwind
.frame_size
+= count
* 8 + 4;
4347 /* Parse a directive saving iWMMXt data registers. */
4350 s_arm_unwind_save_mmxwr (void)
4358 if (*input_line_pointer
== '{')
4359 input_line_pointer
++;
4363 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4367 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4372 as_tsktsk (_("register list not in ascending order"));
4375 if (*input_line_pointer
== '-')
4377 input_line_pointer
++;
4378 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4381 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4384 else if (reg
>= hi_reg
)
4386 as_bad (_("bad register range"));
4389 for (; reg
< hi_reg
; reg
++)
4393 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4395 skip_past_char (&input_line_pointer
, '}');
4397 demand_empty_rest_of_line ();
4399 /* Generate any deferred opcodes because we're going to be looking at
4401 flush_pending_unwind ();
4403 for (i
= 0; i
< 16; i
++)
4405 if (mask
& (1 << i
))
4406 unwind
.frame_size
+= 8;
4409 /* Attempt to combine with a previous opcode. We do this because gcc
4410 likes to output separate unwind directives for a single block of
4412 if (unwind
.opcode_count
> 0)
4414 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4415 if ((i
& 0xf8) == 0xc0)
4418 /* Only merge if the blocks are contiguous. */
4421 if ((mask
& 0xfe00) == (1 << 9))
4423 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4424 unwind
.opcode_count
--;
4427 else if (i
== 6 && unwind
.opcode_count
>= 2)
4429 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4433 op
= 0xffff << (reg
- 1);
4435 && ((mask
& op
) == (1u << (reg
- 1))))
4437 op
= (1 << (reg
+ i
+ 1)) - 1;
4438 op
&= ~((1 << reg
) - 1);
4440 unwind
.opcode_count
-= 2;
4447 /* We want to generate opcodes in the order the registers have been
4448 saved, ie. descending order. */
4449 for (reg
= 15; reg
>= -1; reg
--)
4451 /* Save registers in blocks. */
4453 || !(mask
& (1 << reg
)))
4455 /* We found an unsaved reg. Generate opcodes to save the
4462 op
= 0xc0 | (hi_reg
- 10);
4463 add_unwind_opcode (op
, 1);
4468 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4469 add_unwind_opcode (op
, 2);
4478 ignore_rest_of_line ();
4482 s_arm_unwind_save_mmxwcg (void)
4489 if (*input_line_pointer
== '{')
4490 input_line_pointer
++;
4492 skip_whitespace (input_line_pointer
);
4496 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4500 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4506 as_tsktsk (_("register list not in ascending order"));
4509 if (*input_line_pointer
== '-')
4511 input_line_pointer
++;
4512 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4515 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4518 else if (reg
>= hi_reg
)
4520 as_bad (_("bad register range"));
4523 for (; reg
< hi_reg
; reg
++)
4527 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4529 skip_past_char (&input_line_pointer
, '}');
4531 demand_empty_rest_of_line ();
4533 /* Generate any deferred opcodes because we're going to be looking at
4535 flush_pending_unwind ();
4537 for (reg
= 0; reg
< 16; reg
++)
4539 if (mask
& (1 << reg
))
4540 unwind
.frame_size
+= 4;
4543 add_unwind_opcode (op
, 2);
4546 ignore_rest_of_line ();
4550 /* Parse an unwind_save directive.
4551 If the argument is non-zero, this is a .vsave directive. */
4554 s_arm_unwind_save (int arch_v6
)
4557 struct reg_entry
*reg
;
4558 bfd_boolean had_brace
= FALSE
;
4560 if (!unwind
.proc_start
)
4561 as_bad (MISSING_FNSTART
);
4563 /* Figure out what sort of save we have. */
4564 peek
= input_line_pointer
;
4572 reg
= arm_reg_parse_multi (&peek
);
4576 as_bad (_("register expected"));
4577 ignore_rest_of_line ();
4586 as_bad (_("FPA .unwind_save does not take a register list"));
4587 ignore_rest_of_line ();
4590 input_line_pointer
= peek
;
4591 s_arm_unwind_save_fpa (reg
->number
);
4595 s_arm_unwind_save_core ();
4600 s_arm_unwind_save_vfp_armv6 ();
4602 s_arm_unwind_save_vfp ();
4605 case REG_TYPE_MMXWR
:
4606 s_arm_unwind_save_mmxwr ();
4609 case REG_TYPE_MMXWCG
:
4610 s_arm_unwind_save_mmxwcg ();
4614 as_bad (_(".unwind_save does not support this kind of register"));
4615 ignore_rest_of_line ();
4620 /* Parse an unwind_movsp directive. */
4623 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4629 if (!unwind
.proc_start
)
4630 as_bad (MISSING_FNSTART
);
4632 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4635 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4636 ignore_rest_of_line ();
4640 /* Optional constant. */
4641 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4643 if (immediate_for_directive (&offset
) == FAIL
)
4649 demand_empty_rest_of_line ();
4651 if (reg
== REG_SP
|| reg
== REG_PC
)
4653 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4657 if (unwind
.fp_reg
!= REG_SP
)
4658 as_bad (_("unexpected .unwind_movsp directive"));
4660 /* Generate opcode to restore the value. */
4662 add_unwind_opcode (op
, 1);
4664 /* Record the information for later. */
4665 unwind
.fp_reg
= reg
;
4666 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4667 unwind
.sp_restored
= 1;
4670 /* Parse an unwind_pad directive. */
4673 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4677 if (!unwind
.proc_start
)
4678 as_bad (MISSING_FNSTART
);
4680 if (immediate_for_directive (&offset
) == FAIL
)
4685 as_bad (_("stack increment must be multiple of 4"));
4686 ignore_rest_of_line ();
4690 /* Don't generate any opcodes, just record the details for later. */
4691 unwind
.frame_size
+= offset
;
4692 unwind
.pending_offset
+= offset
;
4694 demand_empty_rest_of_line ();
4697 /* Parse an unwind_setfp directive. */
4700 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4706 if (!unwind
.proc_start
)
4707 as_bad (MISSING_FNSTART
);
4709 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4710 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4713 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4715 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4717 as_bad (_("expected <reg>, <reg>"));
4718 ignore_rest_of_line ();
4722 /* Optional constant. */
4723 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4725 if (immediate_for_directive (&offset
) == FAIL
)
4731 demand_empty_rest_of_line ();
4733 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4735 as_bad (_("register must be either sp or set by a previous"
4736 "unwind_movsp directive"));
4740 /* Don't generate any opcodes, just record the information for later. */
4741 unwind
.fp_reg
= fp_reg
;
4743 if (sp_reg
== REG_SP
)
4744 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4746 unwind
.fp_offset
-= offset
;
4749 /* Parse an unwind_raw directive. */
4752 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4755 /* This is an arbitrary limit. */
4756 unsigned char op
[16];
4759 if (!unwind
.proc_start
)
4760 as_bad (MISSING_FNSTART
);
4763 if (exp
.X_op
== O_constant
4764 && skip_past_comma (&input_line_pointer
) != FAIL
)
4766 unwind
.frame_size
+= exp
.X_add_number
;
4770 exp
.X_op
= O_illegal
;
4772 if (exp
.X_op
!= O_constant
)
4774 as_bad (_("expected <offset>, <opcode>"));
4775 ignore_rest_of_line ();
4781 /* Parse the opcode. */
4786 as_bad (_("unwind opcode too long"));
4787 ignore_rest_of_line ();
4789 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4791 as_bad (_("invalid unwind opcode"));
4792 ignore_rest_of_line ();
4795 op
[count
++] = exp
.X_add_number
;
4797 /* Parse the next byte. */
4798 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4804 /* Add the opcode bytes in reverse order. */
4806 add_unwind_opcode (op
[count
], 1);
4808 demand_empty_rest_of_line ();
4812 /* Parse a .eabi_attribute directive. */
4815 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4817 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4819 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4820 attributes_set_explicitly
[tag
] = 1;
4823 /* Emit a tls fix for the symbol. */
4826 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4830 #ifdef md_flush_pending_output
4831 md_flush_pending_output ();
4834 #ifdef md_cons_align
4838 /* Since we're just labelling the code, there's no need to define a
4841 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4842 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4843 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4844 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4846 #endif /* OBJ_ELF */
4848 static void s_arm_arch (int);
4849 static void s_arm_object_arch (int);
4850 static void s_arm_cpu (int);
4851 static void s_arm_fpu (int);
4852 static void s_arm_arch_extension (int);
4857 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4864 if (exp
.X_op
== O_symbol
)
4865 exp
.X_op
= O_secrel
;
4867 emit_expr (&exp
, 4);
4869 while (*input_line_pointer
++ == ',');
4871 input_line_pointer
--;
4872 demand_empty_rest_of_line ();
4876 /* This table describes all the machine specific pseudo-ops the assembler
4877 has to support. The fields are:
4878 pseudo-op name without dot
4879 function to call to execute this pseudo-op
4880 Integer arg to pass to the function. */
4882 const pseudo_typeS md_pseudo_table
[] =
4884 /* Never called because '.req' does not start a line. */
4885 { "req", s_req
, 0 },
4886 /* Following two are likewise never called. */
4889 { "unreq", s_unreq
, 0 },
4890 { "bss", s_bss
, 0 },
4891 { "align", s_align_ptwo
, 2 },
4892 { "arm", s_arm
, 0 },
4893 { "thumb", s_thumb
, 0 },
4894 { "code", s_code
, 0 },
4895 { "force_thumb", s_force_thumb
, 0 },
4896 { "thumb_func", s_thumb_func
, 0 },
4897 { "thumb_set", s_thumb_set
, 0 },
4898 { "even", s_even
, 0 },
4899 { "ltorg", s_ltorg
, 0 },
4900 { "pool", s_ltorg
, 0 },
4901 { "syntax", s_syntax
, 0 },
4902 { "cpu", s_arm_cpu
, 0 },
4903 { "arch", s_arm_arch
, 0 },
4904 { "object_arch", s_arm_object_arch
, 0 },
4905 { "fpu", s_arm_fpu
, 0 },
4906 { "arch_extension", s_arm_arch_extension
, 0 },
4908 { "word", s_arm_elf_cons
, 4 },
4909 { "long", s_arm_elf_cons
, 4 },
4910 { "inst.n", s_arm_elf_inst
, 2 },
4911 { "inst.w", s_arm_elf_inst
, 4 },
4912 { "inst", s_arm_elf_inst
, 0 },
4913 { "rel31", s_arm_rel31
, 0 },
4914 { "fnstart", s_arm_unwind_fnstart
, 0 },
4915 { "fnend", s_arm_unwind_fnend
, 0 },
4916 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4917 { "personality", s_arm_unwind_personality
, 0 },
4918 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4919 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4920 { "save", s_arm_unwind_save
, 0 },
4921 { "vsave", s_arm_unwind_save
, 1 },
4922 { "movsp", s_arm_unwind_movsp
, 0 },
4923 { "pad", s_arm_unwind_pad
, 0 },
4924 { "setfp", s_arm_unwind_setfp
, 0 },
4925 { "unwind_raw", s_arm_unwind_raw
, 0 },
4926 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4927 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4931 /* These are used for dwarf. */
4935 /* These are used for dwarf2. */
4936 { "file", dwarf2_directive_file
, 0 },
4937 { "loc", dwarf2_directive_loc
, 0 },
4938 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4940 { "extend", float_cons
, 'x' },
4941 { "ldouble", float_cons
, 'x' },
4942 { "packed", float_cons
, 'p' },
4944 {"secrel32", pe_directive_secrel
, 0},
4947 /* These are for compatibility with CodeComposer Studio. */
4948 {"ref", s_ccs_ref
, 0},
4949 {"def", s_ccs_def
, 0},
4950 {"asmfunc", s_ccs_asmfunc
, 0},
4951 {"endasmfunc", s_ccs_endasmfunc
, 0},
4956 /* Parser functions used exclusively in instruction operands. */
4958 /* Generic immediate-value read function for use in insn parsing.
4959 STR points to the beginning of the immediate (the leading #);
4960 VAL receives the value; if the value is outside [MIN, MAX]
4961 issue an error. PREFIX_OPT is true if the immediate prefix is
4965 parse_immediate (char **str
, int *val
, int min
, int max
,
4966 bfd_boolean prefix_opt
)
4970 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4971 if (exp
.X_op
!= O_constant
)
4973 inst
.error
= _("constant expression required");
4977 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4979 inst
.error
= _("immediate value out of range");
4983 *val
= exp
.X_add_number
;
4987 /* Less-generic immediate-value read function with the possibility of loading a
4988 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4989 instructions. Puts the result directly in inst.operands[i]. */
4992 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4993 bfd_boolean allow_symbol_p
)
4996 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4999 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5001 if (exp_p
->X_op
== O_constant
)
5003 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5004 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5005 O_constant. We have to be careful not to break compilation for
5006 32-bit X_add_number, though. */
5007 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5009 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5010 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5012 inst
.operands
[i
].regisimm
= 1;
5015 else if (exp_p
->X_op
== O_big
5016 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5018 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5020 /* Bignums have their least significant bits in
5021 generic_bignum[0]. Make sure we put 32 bits in imm and
5022 32 bits in reg, in a (hopefully) portable way. */
5023 gas_assert (parts
!= 0);
5025 /* Make sure that the number is not too big.
5026 PR 11972: Bignums can now be sign-extended to the
5027 size of a .octa so check that the out of range bits
5028 are all zero or all one. */
5029 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5031 LITTLENUM_TYPE m
= -1;
5033 if (generic_bignum
[parts
* 2] != 0
5034 && generic_bignum
[parts
* 2] != m
)
5037 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5038 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5042 inst
.operands
[i
].imm
= 0;
5043 for (j
= 0; j
< parts
; j
++, idx
++)
5044 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5045 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5046 inst
.operands
[i
].reg
= 0;
5047 for (j
= 0; j
< parts
; j
++, idx
++)
5048 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5049 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5050 inst
.operands
[i
].regisimm
= 1;
5052 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5060 /* Returns the pseudo-register number of an FPA immediate constant,
5061 or FAIL if there isn't a valid constant here. */
5064 parse_fpa_immediate (char ** str
)
5066 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5072 /* First try and match exact strings, this is to guarantee
5073 that some formats will work even for cross assembly. */
5075 for (i
= 0; fp_const
[i
]; i
++)
5077 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5081 *str
+= strlen (fp_const
[i
]);
5082 if (is_end_of_line
[(unsigned char) **str
])
5088 /* Just because we didn't get a match doesn't mean that the constant
5089 isn't valid, just that it is in a format that we don't
5090 automatically recognize. Try parsing it with the standard
5091 expression routines. */
5093 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5095 /* Look for a raw floating point number. */
5096 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5097 && is_end_of_line
[(unsigned char) *save_in
])
5099 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5101 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5103 if (words
[j
] != fp_values
[i
][j
])
5107 if (j
== MAX_LITTLENUMS
)
5115 /* Try and parse a more complex expression, this will probably fail
5116 unless the code uses a floating point prefix (eg "0f"). */
5117 save_in
= input_line_pointer
;
5118 input_line_pointer
= *str
;
5119 if (expression (&exp
) == absolute_section
5120 && exp
.X_op
== O_big
5121 && exp
.X_add_number
< 0)
5123 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5125 #define X_PRECISION 5
5126 #define E_PRECISION 15L
5127 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5129 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5131 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5133 if (words
[j
] != fp_values
[i
][j
])
5137 if (j
== MAX_LITTLENUMS
)
5139 *str
= input_line_pointer
;
5140 input_line_pointer
= save_in
;
5147 *str
= input_line_pointer
;
5148 input_line_pointer
= save_in
;
5149 inst
.error
= _("invalid FPA immediate expression");
5153 /* Returns 1 if a number has "quarter-precision" float format
5154 0baBbbbbbc defgh000 00000000 00000000. */
5157 is_quarter_float (unsigned imm
)
5159 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5160 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5164 /* Detect the presence of a floating point or integer zero constant,
5168 parse_ifimm_zero (char **in
)
5172 if (!is_immediate_prefix (**in
))
5174 /* In unified syntax, all prefixes are optional. */
5175 if (!unified_syntax
)
5181 /* Accept #0x0 as a synonym for #0. */
5182 if (strncmp (*in
, "0x", 2) == 0)
5185 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5190 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5191 &generic_floating_point_number
);
5194 && generic_floating_point_number
.sign
== '+'
5195 && (generic_floating_point_number
.low
5196 > generic_floating_point_number
.leader
))
5202 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5203 0baBbbbbbc defgh000 00000000 00000000.
5204 The zero and minus-zero cases need special handling, since they can't be
5205 encoded in the "quarter-precision" float format, but can nonetheless be
5206 loaded as integer constants. */
5209 parse_qfloat_immediate (char **ccp
, int *immed
)
5213 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5214 int found_fpchar
= 0;
5216 skip_past_char (&str
, '#');
5218 /* We must not accidentally parse an integer as a floating-point number. Make
5219 sure that the value we parse is not an integer by checking for special
5220 characters '.' or 'e'.
5221 FIXME: This is a horrible hack, but doing better is tricky because type
5222 information isn't in a very usable state at parse time. */
5224 skip_whitespace (fpnum
);
5226 if (strncmp (fpnum
, "0x", 2) == 0)
5230 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5231 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5241 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5243 unsigned fpword
= 0;
5246 /* Our FP word must be 32 bits (single-precision FP). */
5247 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5249 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5253 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5266 /* Shift operands. */
5269 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5272 struct asm_shift_name
5275 enum shift_kind kind
;
5278 /* Third argument to parse_shift. */
5279 enum parse_shift_mode
5281 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5282 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5283 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5284 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5285 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5288 /* Parse a <shift> specifier on an ARM data processing instruction.
5289 This has three forms:
5291 (LSL|LSR|ASL|ASR|ROR) Rs
5292 (LSL|LSR|ASL|ASR|ROR) #imm
5295 Note that ASL is assimilated to LSL in the instruction encoding, and
5296 RRX to ROR #0 (which cannot be written as such). */
5299 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5301 const struct asm_shift_name
*shift_name
;
5302 enum shift_kind shift
;
5307 for (p
= *str
; ISALPHA (*p
); p
++)
5312 inst
.error
= _("shift expression expected");
5316 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5319 if (shift_name
== NULL
)
5321 inst
.error
= _("shift expression expected");
5325 shift
= shift_name
->kind
;
5329 case NO_SHIFT_RESTRICT
:
5330 case SHIFT_IMMEDIATE
: break;
5332 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5333 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5335 inst
.error
= _("'LSL' or 'ASR' required");
5340 case SHIFT_LSL_IMMEDIATE
:
5341 if (shift
!= SHIFT_LSL
)
5343 inst
.error
= _("'LSL' required");
5348 case SHIFT_ASR_IMMEDIATE
:
5349 if (shift
!= SHIFT_ASR
)
5351 inst
.error
= _("'ASR' required");
5359 if (shift
!= SHIFT_RRX
)
5361 /* Whitespace can appear here if the next thing is a bare digit. */
5362 skip_whitespace (p
);
5364 if (mode
== NO_SHIFT_RESTRICT
5365 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5367 inst
.operands
[i
].imm
= reg
;
5368 inst
.operands
[i
].immisreg
= 1;
5370 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5373 inst
.operands
[i
].shift_kind
= shift
;
5374 inst
.operands
[i
].shifted
= 1;
5379 /* Parse a <shifter_operand> for an ARM data processing instruction:
5382 #<immediate>, <rotate>
5386 where <shift> is defined by parse_shift above, and <rotate> is a
5387 multiple of 2 between 0 and 30. Validation of immediate operands
5388 is deferred to md_apply_fix. */
5391 parse_shifter_operand (char **str
, int i
)
5396 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5398 inst
.operands
[i
].reg
= value
;
5399 inst
.operands
[i
].isreg
= 1;
5401 /* parse_shift will override this if appropriate */
5402 inst
.relocs
[0].exp
.X_op
= O_constant
;
5403 inst
.relocs
[0].exp
.X_add_number
= 0;
5405 if (skip_past_comma (str
) == FAIL
)
5408 /* Shift operation on register. */
5409 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5412 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5415 if (skip_past_comma (str
) == SUCCESS
)
5417 /* #x, y -- ie explicit rotation by Y. */
5418 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5421 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5423 inst
.error
= _("constant expression expected");
5427 value
= exp
.X_add_number
;
5428 if (value
< 0 || value
> 30 || value
% 2 != 0)
5430 inst
.error
= _("invalid rotation");
5433 if (inst
.relocs
[0].exp
.X_add_number
< 0
5434 || inst
.relocs
[0].exp
.X_add_number
> 255)
5436 inst
.error
= _("invalid constant");
5440 /* Encode as specified. */
5441 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5445 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5446 inst
.relocs
[0].pc_rel
= 0;
5450 /* Group relocation information. Each entry in the table contains the
5451 textual name of the relocation as may appear in assembler source
5452 and must end with a colon.
5453 Along with this textual name are the relocation codes to be used if
5454 the corresponding instruction is an ALU instruction (ADD or SUB only),
5455 an LDR, an LDRS, or an LDC. */
5457 struct group_reloc_table_entry
5468 /* Varieties of non-ALU group relocation. */
5475 static struct group_reloc_table_entry group_reloc_table
[] =
5476 { /* Program counter relative: */
5478 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5483 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5484 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5485 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5486 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5488 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5493 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5494 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5495 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5496 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5498 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5499 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5500 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5501 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5502 /* Section base relative */
5504 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5509 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5510 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5511 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5512 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5514 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5519 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5520 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5521 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5522 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5524 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5525 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5526 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5527 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5528 /* Absolute thumb alu relocations. */
5530 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5535 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5540 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5545 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5550 /* Given the address of a pointer pointing to the textual name of a group
5551 relocation as may appear in assembler source, attempt to find its details
5552 in group_reloc_table. The pointer will be updated to the character after
5553 the trailing colon. On failure, FAIL will be returned; SUCCESS
5554 otherwise. On success, *entry will be updated to point at the relevant
5555 group_reloc_table entry. */
5558 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5561 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5563 int length
= strlen (group_reloc_table
[i
].name
);
5565 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5566 && (*str
)[length
] == ':')
5568 *out
= &group_reloc_table
[i
];
5569 *str
+= (length
+ 1);
5577 /* Parse a <shifter_operand> for an ARM data processing instruction
5578 (as for parse_shifter_operand) where group relocations are allowed:
5581 #<immediate>, <rotate>
5582 #:<group_reloc>:<expression>
5586 where <group_reloc> is one of the strings defined in group_reloc_table.
5587 The hashes are optional.
5589 Everything else is as for parse_shifter_operand. */
5591 static parse_operand_result
5592 parse_shifter_operand_group_reloc (char **str
, int i
)
5594 /* Determine if we have the sequence of characters #: or just :
5595 coming next. If we do, then we check for a group relocation.
5596 If we don't, punt the whole lot to parse_shifter_operand. */
5598 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5599 || (*str
)[0] == ':')
5601 struct group_reloc_table_entry
*entry
;
5603 if ((*str
)[0] == '#')
5608 /* Try to parse a group relocation. Anything else is an error. */
5609 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5611 inst
.error
= _("unknown group relocation");
5612 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5615 /* We now have the group relocation table entry corresponding to
5616 the name in the assembler source. Next, we parse the expression. */
5617 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5618 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5620 /* Record the relocation type (always the ALU variant here). */
5621 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5622 gas_assert (inst
.relocs
[0].type
!= 0);
5624 return PARSE_OPERAND_SUCCESS
;
5627 return parse_shifter_operand (str
, i
) == SUCCESS
5628 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5630 /* Never reached. */
5633 /* Parse a Neon alignment expression. Information is written to
5634 inst.operands[i]. We assume the initial ':' has been skipped.
5636 align .imm = align << 8, .immisalign=1, .preind=0 */
5637 static parse_operand_result
5638 parse_neon_alignment (char **str
, int i
)
5643 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5645 if (exp
.X_op
!= O_constant
)
5647 inst
.error
= _("alignment must be constant");
5648 return PARSE_OPERAND_FAIL
;
5651 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5652 inst
.operands
[i
].immisalign
= 1;
5653 /* Alignments are not pre-indexes. */
5654 inst
.operands
[i
].preind
= 0;
5657 return PARSE_OPERAND_SUCCESS
;
5660 /* Parse all forms of an ARM address expression. Information is written
5661 to inst.operands[i] and/or inst.relocs[0].
5663 Preindexed addressing (.preind=1):
5665 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5666 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5667 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5668 .shift_kind=shift .relocs[0].exp=shift_imm
5670 These three may have a trailing ! which causes .writeback to be set also.
5672 Postindexed addressing (.postind=1, .writeback=1):
5674 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5675 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5676 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5677 .shift_kind=shift .relocs[0].exp=shift_imm
5679 Unindexed addressing (.preind=0, .postind=0):
5681 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5685 [Rn]{!} shorthand for [Rn,#0]{!}
5686 =immediate .isreg=0 .relocs[0].exp=immediate
5687 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5689 It is the caller's responsibility to check for addressing modes not
5690 supported by the instruction, and to set inst.relocs[0].type. */
5692 static parse_operand_result
5693 parse_address_main (char **str
, int i
, int group_relocations
,
5694 group_reloc_type group_type
)
5699 if (skip_past_char (&p
, '[') == FAIL
)
5701 if (skip_past_char (&p
, '=') == FAIL
)
5703 /* Bare address - translate to PC-relative offset. */
5704 inst
.relocs
[0].pc_rel
= 1;
5705 inst
.operands
[i
].reg
= REG_PC
;
5706 inst
.operands
[i
].isreg
= 1;
5707 inst
.operands
[i
].preind
= 1;
5709 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5710 return PARSE_OPERAND_FAIL
;
5712 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5713 /*allow_symbol_p=*/TRUE
))
5714 return PARSE_OPERAND_FAIL
;
5717 return PARSE_OPERAND_SUCCESS
;
5720 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5721 skip_whitespace (p
);
5723 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5725 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5726 return PARSE_OPERAND_FAIL
;
5728 inst
.operands
[i
].reg
= reg
;
5729 inst
.operands
[i
].isreg
= 1;
5731 if (skip_past_comma (&p
) == SUCCESS
)
5733 inst
.operands
[i
].preind
= 1;
5736 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5738 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5740 inst
.operands
[i
].imm
= reg
;
5741 inst
.operands
[i
].immisreg
= 1;
5743 if (skip_past_comma (&p
) == SUCCESS
)
5744 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5745 return PARSE_OPERAND_FAIL
;
5747 else if (skip_past_char (&p
, ':') == SUCCESS
)
5749 /* FIXME: '@' should be used here, but it's filtered out by generic
5750 code before we get to see it here. This may be subject to
5752 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5754 if (result
!= PARSE_OPERAND_SUCCESS
)
5759 if (inst
.operands
[i
].negative
)
5761 inst
.operands
[i
].negative
= 0;
5765 if (group_relocations
5766 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5768 struct group_reloc_table_entry
*entry
;
5770 /* Skip over the #: or : sequence. */
5776 /* Try to parse a group relocation. Anything else is an
5778 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5780 inst
.error
= _("unknown group relocation");
5781 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5784 /* We now have the group relocation table entry corresponding to
5785 the name in the assembler source. Next, we parse the
5787 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5788 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5790 /* Record the relocation type. */
5795 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5800 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5805 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5812 if (inst
.relocs
[0].type
== 0)
5814 inst
.error
= _("this group relocation is not allowed on this instruction");
5815 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5822 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5823 return PARSE_OPERAND_FAIL
;
5824 /* If the offset is 0, find out if it's a +0 or -0. */
5825 if (inst
.relocs
[0].exp
.X_op
== O_constant
5826 && inst
.relocs
[0].exp
.X_add_number
== 0)
5828 skip_whitespace (q
);
5832 skip_whitespace (q
);
5835 inst
.operands
[i
].negative
= 1;
5840 else if (skip_past_char (&p
, ':') == SUCCESS
)
5842 /* FIXME: '@' should be used here, but it's filtered out by generic code
5843 before we get to see it here. This may be subject to change. */
5844 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5846 if (result
!= PARSE_OPERAND_SUCCESS
)
5850 if (skip_past_char (&p
, ']') == FAIL
)
5852 inst
.error
= _("']' expected");
5853 return PARSE_OPERAND_FAIL
;
5856 if (skip_past_char (&p
, '!') == SUCCESS
)
5857 inst
.operands
[i
].writeback
= 1;
5859 else if (skip_past_comma (&p
) == SUCCESS
)
5861 if (skip_past_char (&p
, '{') == SUCCESS
)
5863 /* [Rn], {expr} - unindexed, with option */
5864 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5865 0, 255, TRUE
) == FAIL
)
5866 return PARSE_OPERAND_FAIL
;
5868 if (skip_past_char (&p
, '}') == FAIL
)
5870 inst
.error
= _("'}' expected at end of 'option' field");
5871 return PARSE_OPERAND_FAIL
;
5873 if (inst
.operands
[i
].preind
)
5875 inst
.error
= _("cannot combine index with option");
5876 return PARSE_OPERAND_FAIL
;
5879 return PARSE_OPERAND_SUCCESS
;
5883 inst
.operands
[i
].postind
= 1;
5884 inst
.operands
[i
].writeback
= 1;
5886 if (inst
.operands
[i
].preind
)
5888 inst
.error
= _("cannot combine pre- and post-indexing");
5889 return PARSE_OPERAND_FAIL
;
5893 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5895 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5897 /* We might be using the immediate for alignment already. If we
5898 are, OR the register number into the low-order bits. */
5899 if (inst
.operands
[i
].immisalign
)
5900 inst
.operands
[i
].imm
|= reg
;
5902 inst
.operands
[i
].imm
= reg
;
5903 inst
.operands
[i
].immisreg
= 1;
5905 if (skip_past_comma (&p
) == SUCCESS
)
5906 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5907 return PARSE_OPERAND_FAIL
;
5913 if (inst
.operands
[i
].negative
)
5915 inst
.operands
[i
].negative
= 0;
5918 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5919 return PARSE_OPERAND_FAIL
;
5920 /* If the offset is 0, find out if it's a +0 or -0. */
5921 if (inst
.relocs
[0].exp
.X_op
== O_constant
5922 && inst
.relocs
[0].exp
.X_add_number
== 0)
5924 skip_whitespace (q
);
5928 skip_whitespace (q
);
5931 inst
.operands
[i
].negative
= 1;
5937 /* If at this point neither .preind nor .postind is set, we have a
5938 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5939 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5941 inst
.operands
[i
].preind
= 1;
5942 inst
.relocs
[0].exp
.X_op
= O_constant
;
5943 inst
.relocs
[0].exp
.X_add_number
= 0;
5946 return PARSE_OPERAND_SUCCESS
;
5950 parse_address (char **str
, int i
)
5952 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5956 static parse_operand_result
5957 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5959 return parse_address_main (str
, i
, 1, type
);
5962 /* Parse an operand for a MOVW or MOVT instruction. */
5964 parse_half (char **str
)
5969 skip_past_char (&p
, '#');
5970 if (strncasecmp (p
, ":lower16:", 9) == 0)
5971 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
5972 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5973 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
5975 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
5978 skip_whitespace (p
);
5981 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5984 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
5986 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
5988 inst
.error
= _("constant expression expected");
5991 if (inst
.relocs
[0].exp
.X_add_number
< 0
5992 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
5994 inst
.error
= _("immediate value out of range");
6002 /* Miscellaneous. */
6004 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6005 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6007 parse_psr (char **str
, bfd_boolean lhs
)
6010 unsigned long psr_field
;
6011 const struct asm_psr
*psr
;
6013 bfd_boolean is_apsr
= FALSE
;
6014 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6016 /* PR gas/12698: If the user has specified -march=all then m_profile will
6017 be TRUE, but we want to ignore it in this case as we are building for any
6018 CPU type, including non-m variants. */
6019 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6022 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6023 feature for ease of use and backwards compatibility. */
6025 if (strncasecmp (p
, "SPSR", 4) == 0)
6028 goto unsupported_psr
;
6030 psr_field
= SPSR_BIT
;
6032 else if (strncasecmp (p
, "CPSR", 4) == 0)
6035 goto unsupported_psr
;
6039 else if (strncasecmp (p
, "APSR", 4) == 0)
6041 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6042 and ARMv7-R architecture CPUs. */
6051 while (ISALNUM (*p
) || *p
== '_');
6053 if (strncasecmp (start
, "iapsr", 5) == 0
6054 || strncasecmp (start
, "eapsr", 5) == 0
6055 || strncasecmp (start
, "xpsr", 4) == 0
6056 || strncasecmp (start
, "psr", 3) == 0)
6057 p
= start
+ strcspn (start
, "rR") + 1;
6059 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6065 /* If APSR is being written, a bitfield may be specified. Note that
6066 APSR itself is handled above. */
6067 if (psr
->field
<= 3)
6069 psr_field
= psr
->field
;
6075 /* M-profile MSR instructions have the mask field set to "10", except
6076 *PSR variants which modify APSR, which may use a different mask (and
6077 have been handled already). Do that by setting the PSR_f field
6079 return psr
->field
| (lhs
? PSR_f
: 0);
6082 goto unsupported_psr
;
6088 /* A suffix follows. */
6094 while (ISALNUM (*p
) || *p
== '_');
6098 /* APSR uses a notation for bits, rather than fields. */
6099 unsigned int nzcvq_bits
= 0;
6100 unsigned int g_bit
= 0;
6103 for (bit
= start
; bit
!= p
; bit
++)
6105 switch (TOLOWER (*bit
))
6108 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6112 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6116 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6120 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6124 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6128 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6132 inst
.error
= _("unexpected bit specified after APSR");
6137 if (nzcvq_bits
== 0x1f)
6142 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6144 inst
.error
= _("selected processor does not "
6145 "support DSP extension");
6152 if ((nzcvq_bits
& 0x20) != 0
6153 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6154 || (g_bit
& 0x2) != 0)
6156 inst
.error
= _("bad bitmask specified after APSR");
6162 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6167 psr_field
|= psr
->field
;
6173 goto error
; /* Garbage after "[CS]PSR". */
6175 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6176 is deprecated, but allow it anyway. */
6180 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6183 else if (!m_profile
)
6184 /* These bits are never right for M-profile devices: don't set them
6185 (only code paths which read/write APSR reach here). */
6186 psr_field
|= (PSR_c
| PSR_f
);
6192 inst
.error
= _("selected processor does not support requested special "
6193 "purpose register");
6197 inst
.error
= _("flag for {c}psr instruction expected");
6202 parse_sys_vldr_vstr (char **str
)
6211 {"FPSCR", 0x1, 0x0},
6212 {"FPSCR_nzcvqc", 0x2, 0x0},
6215 {"FPCXTNS", 0x6, 0x1},
6216 {"FPCXTS", 0x7, 0x1}
6218 char *op_end
= strchr (*str
, ',');
6219 size_t op_strlen
= op_end
- *str
;
6221 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6223 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6225 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6234 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6235 value suitable for splatting into the AIF field of the instruction. */
6238 parse_cps_flags (char **str
)
6247 case '\0': case ',':
6250 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6251 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6252 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6255 inst
.error
= _("unrecognized CPS flag");
6260 if (saw_a_flag
== 0)
6262 inst
.error
= _("missing CPS flags");
6270 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6271 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6274 parse_endian_specifier (char **str
)
6279 if (strncasecmp (s
, "BE", 2))
6281 else if (strncasecmp (s
, "LE", 2))
6285 inst
.error
= _("valid endian specifiers are be or le");
6289 if (ISALNUM (s
[2]) || s
[2] == '_')
6291 inst
.error
= _("valid endian specifiers are be or le");
6296 return little_endian
;
6299 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6300 value suitable for poking into the rotate field of an sxt or sxta
6301 instruction, or FAIL on error. */
6304 parse_ror (char **str
)
6309 if (strncasecmp (s
, "ROR", 3) == 0)
6313 inst
.error
= _("missing rotation field after comma");
6317 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6322 case 0: *str
= s
; return 0x0;
6323 case 8: *str
= s
; return 0x1;
6324 case 16: *str
= s
; return 0x2;
6325 case 24: *str
= s
; return 0x3;
6328 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6333 /* Parse a conditional code (from conds[] below). The value returned is in the
6334 range 0 .. 14, or FAIL. */
6336 parse_cond (char **str
)
6339 const struct asm_cond
*c
;
6341 /* Condition codes are always 2 characters, so matching up to
6342 3 characters is sufficient. */
6347 while (ISALPHA (*q
) && n
< 3)
6349 cond
[n
] = TOLOWER (*q
);
6354 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6357 inst
.error
= _("condition required");
6365 /* Parse an option for a barrier instruction. Returns the encoding for the
6368 parse_barrier (char **str
)
6371 const struct asm_barrier_opt
*o
;
6374 while (ISALPHA (*q
))
6377 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6382 if (!mark_feature_used (&o
->arch
))
6389 /* Parse the operands of a table branch instruction. Similar to a memory
6392 parse_tb (char **str
)
6397 if (skip_past_char (&p
, '[') == FAIL
)
6399 inst
.error
= _("'[' expected");
6403 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6405 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6408 inst
.operands
[0].reg
= reg
;
6410 if (skip_past_comma (&p
) == FAIL
)
6412 inst
.error
= _("',' expected");
6416 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6418 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6421 inst
.operands
[0].imm
= reg
;
6423 if (skip_past_comma (&p
) == SUCCESS
)
6425 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6427 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6429 inst
.error
= _("invalid shift");
6432 inst
.operands
[0].shifted
= 1;
6435 if (skip_past_char (&p
, ']') == FAIL
)
6437 inst
.error
= _("']' expected");
6444 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6445 information on the types the operands can take and how they are encoded.
6446 Up to four operands may be read; this function handles setting the
6447 ".present" field for each read operand itself.
6448 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6449 else returns FAIL. */
6452 parse_neon_mov (char **str
, int *which_operand
)
6454 int i
= *which_operand
, val
;
6455 enum arm_reg_type rtype
;
6457 struct neon_type_el optype
;
6459 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6461 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6462 inst
.operands
[i
].reg
= val
;
6463 inst
.operands
[i
].isscalar
= 1;
6464 inst
.operands
[i
].vectype
= optype
;
6465 inst
.operands
[i
++].present
= 1;
6467 if (skip_past_comma (&ptr
) == FAIL
)
6470 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6473 inst
.operands
[i
].reg
= val
;
6474 inst
.operands
[i
].isreg
= 1;
6475 inst
.operands
[i
].present
= 1;
6477 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6480 /* Cases 0, 1, 2, 3, 5 (D only). */
6481 if (skip_past_comma (&ptr
) == FAIL
)
6484 inst
.operands
[i
].reg
= val
;
6485 inst
.operands
[i
].isreg
= 1;
6486 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6487 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6488 inst
.operands
[i
].isvec
= 1;
6489 inst
.operands
[i
].vectype
= optype
;
6490 inst
.operands
[i
++].present
= 1;
6492 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6494 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6495 Case 13: VMOV <Sd>, <Rm> */
6496 inst
.operands
[i
].reg
= val
;
6497 inst
.operands
[i
].isreg
= 1;
6498 inst
.operands
[i
].present
= 1;
6500 if (rtype
== REG_TYPE_NQ
)
6502 first_error (_("can't use Neon quad register here"));
6505 else if (rtype
!= REG_TYPE_VFS
)
6508 if (skip_past_comma (&ptr
) == FAIL
)
6510 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6512 inst
.operands
[i
].reg
= val
;
6513 inst
.operands
[i
].isreg
= 1;
6514 inst
.operands
[i
].present
= 1;
6517 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6520 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6521 Case 1: VMOV<c><q> <Dd>, <Dm>
6522 Case 8: VMOV.F32 <Sd>, <Sm>
6523 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6525 inst
.operands
[i
].reg
= val
;
6526 inst
.operands
[i
].isreg
= 1;
6527 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6528 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6529 inst
.operands
[i
].isvec
= 1;
6530 inst
.operands
[i
].vectype
= optype
;
6531 inst
.operands
[i
].present
= 1;
6533 if (skip_past_comma (&ptr
) == SUCCESS
)
6538 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6541 inst
.operands
[i
].reg
= val
;
6542 inst
.operands
[i
].isreg
= 1;
6543 inst
.operands
[i
++].present
= 1;
6545 if (skip_past_comma (&ptr
) == FAIL
)
6548 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6551 inst
.operands
[i
].reg
= val
;
6552 inst
.operands
[i
].isreg
= 1;
6553 inst
.operands
[i
].present
= 1;
6556 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6557 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6558 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6559 Case 10: VMOV.F32 <Sd>, #<imm>
6560 Case 11: VMOV.F64 <Dd>, #<imm> */
6561 inst
.operands
[i
].immisfloat
= 1;
6562 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6564 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6565 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6569 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6573 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6576 inst
.operands
[i
].reg
= val
;
6577 inst
.operands
[i
].isreg
= 1;
6578 inst
.operands
[i
++].present
= 1;
6580 if (skip_past_comma (&ptr
) == FAIL
)
6583 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6585 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6586 inst
.operands
[i
].reg
= val
;
6587 inst
.operands
[i
].isscalar
= 1;
6588 inst
.operands
[i
].present
= 1;
6589 inst
.operands
[i
].vectype
= optype
;
6591 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6593 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6594 inst
.operands
[i
].reg
= val
;
6595 inst
.operands
[i
].isreg
= 1;
6596 inst
.operands
[i
++].present
= 1;
6598 if (skip_past_comma (&ptr
) == FAIL
)
6601 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6604 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6608 inst
.operands
[i
].reg
= val
;
6609 inst
.operands
[i
].isreg
= 1;
6610 inst
.operands
[i
].isvec
= 1;
6611 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6612 inst
.operands
[i
].vectype
= optype
;
6613 inst
.operands
[i
].present
= 1;
6615 if (rtype
== REG_TYPE_VFS
)
6619 if (skip_past_comma (&ptr
) == FAIL
)
6621 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6624 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6627 inst
.operands
[i
].reg
= val
;
6628 inst
.operands
[i
].isreg
= 1;
6629 inst
.operands
[i
].isvec
= 1;
6630 inst
.operands
[i
].issingle
= 1;
6631 inst
.operands
[i
].vectype
= optype
;
6632 inst
.operands
[i
].present
= 1;
6635 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6639 inst
.operands
[i
].reg
= val
;
6640 inst
.operands
[i
].isreg
= 1;
6641 inst
.operands
[i
].isvec
= 1;
6642 inst
.operands
[i
].issingle
= 1;
6643 inst
.operands
[i
].vectype
= optype
;
6644 inst
.operands
[i
].present
= 1;
6649 first_error (_("parse error"));
6653 /* Successfully parsed the operands. Update args. */
6659 first_error (_("expected comma"));
6663 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6667 /* Use this macro when the operand constraints are different
6668 for ARM and THUMB (e.g. ldrd). */
6669 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6670 ((arm_operand) | ((thumb_operand) << 16))
6672 /* Matcher codes for parse_operands. */
6673 enum operand_parse_code
6675 OP_stop
, /* end of line */
6677 OP_RR
, /* ARM register */
6678 OP_RRnpc
, /* ARM register, not r15 */
6679 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6680 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6681 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6682 optional trailing ! */
6683 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6684 OP_RCP
, /* Coprocessor number */
6685 OP_RCN
, /* Coprocessor register */
6686 OP_RF
, /* FPA register */
6687 OP_RVS
, /* VFP single precision register */
6688 OP_RVD
, /* VFP double precision register (0..15) */
6689 OP_RND
, /* Neon double precision register (0..31) */
6690 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6691 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6693 OP_RNQ
, /* Neon quad precision register */
6694 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6695 OP_RVSD
, /* VFP single or double precision register */
6696 OP_RNSD
, /* Neon single or double precision register */
6697 OP_RNDQ
, /* Neon double or quad precision register */
6698 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6699 OP_RNSDQ
, /* Neon single, double or quad precision register */
6700 OP_RNSC
, /* Neon scalar D[X] */
6701 OP_RVC
, /* VFP control register */
6702 OP_RMF
, /* Maverick F register */
6703 OP_RMD
, /* Maverick D register */
6704 OP_RMFX
, /* Maverick FX register */
6705 OP_RMDX
, /* Maverick DX register */
6706 OP_RMAX
, /* Maverick AX register */
6707 OP_RMDS
, /* Maverick DSPSC register */
6708 OP_RIWR
, /* iWMMXt wR register */
6709 OP_RIWC
, /* iWMMXt wC register */
6710 OP_RIWG
, /* iWMMXt wCG register */
6711 OP_RXA
, /* XScale accumulator register */
6713 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6715 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6717 /* New operands for Armv8.1-M Mainline. */
6718 OP_LR
, /* ARM LR register */
6719 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6721 OP_REGLST
, /* ARM register list */
6722 OP_CLRMLST
, /* CLRM register list */
6723 OP_VRSLST
, /* VFP single-precision register list */
6724 OP_VRDLST
, /* VFP double-precision register list */
6725 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6726 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6727 OP_NSTRLST
, /* Neon element/structure list */
6728 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6730 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6731 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6732 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6733 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6734 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6735 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6736 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6737 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6738 OP_VMOV
, /* Neon VMOV operands. */
6739 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6740 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6741 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6742 OP_VLDR
, /* VLDR operand. */
6744 OP_I0
, /* immediate zero */
6745 OP_I7
, /* immediate value 0 .. 7 */
6746 OP_I15
, /* 0 .. 15 */
6747 OP_I16
, /* 1 .. 16 */
6748 OP_I16z
, /* 0 .. 16 */
6749 OP_I31
, /* 0 .. 31 */
6750 OP_I31w
, /* 0 .. 31, optional trailing ! */
6751 OP_I32
, /* 1 .. 32 */
6752 OP_I32z
, /* 0 .. 32 */
6753 OP_I63
, /* 0 .. 63 */
6754 OP_I63s
, /* -64 .. 63 */
6755 OP_I64
, /* 1 .. 64 */
6756 OP_I64z
, /* 0 .. 64 */
6757 OP_I255
, /* 0 .. 255 */
6759 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6760 OP_I7b
, /* 0 .. 7 */
6761 OP_I15b
, /* 0 .. 15 */
6762 OP_I31b
, /* 0 .. 31 */
6764 OP_SH
, /* shifter operand */
6765 OP_SHG
, /* shifter operand with possible group relocation */
6766 OP_ADDR
, /* Memory address expression (any mode) */
6767 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6768 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6769 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6770 OP_EXP
, /* arbitrary expression */
6771 OP_EXPi
, /* same, with optional immediate prefix */
6772 OP_EXPr
, /* same, with optional relocation suffix */
6773 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6774 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6775 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6776 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6778 OP_CPSF
, /* CPS flags */
6779 OP_ENDI
, /* Endianness specifier */
6780 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6781 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6782 OP_COND
, /* conditional code */
6783 OP_TB
, /* Table branch. */
6785 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6787 OP_RRnpc_I0
, /* ARM register or literal 0 */
6788 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6789 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6790 OP_RF_IF
, /* FPA register or immediate */
6791 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6792 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6794 /* Optional operands. */
6795 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6796 OP_oI31b
, /* 0 .. 31 */
6797 OP_oI32b
, /* 1 .. 32 */
6798 OP_oI32z
, /* 0 .. 32 */
6799 OP_oIffffb
, /* 0 .. 65535 */
6800 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6802 OP_oRR
, /* ARM register */
6803 OP_oLR
, /* ARM LR register */
6804 OP_oRRnpc
, /* ARM register, not the PC */
6805 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6806 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6807 OP_oRND
, /* Optional Neon double precision register */
6808 OP_oRNQ
, /* Optional Neon quad precision register */
6809 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
6810 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6811 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6812 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
6814 OP_oSHll
, /* LSL immediate */
6815 OP_oSHar
, /* ASR immediate */
6816 OP_oSHllar
, /* LSL or ASR immediate */
6817 OP_oROR
, /* ROR 0/8/16/24 */
6818 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6820 /* Some pre-defined mixed (ARM/THUMB) operands. */
6821 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6822 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6823 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6825 OP_FIRST_OPTIONAL
= OP_oI7b
6828 /* Generic instruction operand parser. This does no encoding and no
6829 semantic validation; it merely squirrels values away in the inst
6830 structure. Returns SUCCESS or FAIL depending on whether the
6831 specified grammar matched. */
6833 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6835 unsigned const int *upat
= pattern
;
6836 char *backtrack_pos
= 0;
6837 const char *backtrack_error
= 0;
6838 int i
, val
= 0, backtrack_index
= 0;
6839 enum arm_reg_type rtype
;
6840 parse_operand_result result
;
6841 unsigned int op_parse_code
;
6842 bfd_boolean partial_match
;
6844 #define po_char_or_fail(chr) \
6847 if (skip_past_char (&str, chr) == FAIL) \
6852 #define po_reg_or_fail(regtype) \
6855 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6856 & inst.operands[i].vectype); \
6859 first_error (_(reg_expected_msgs[regtype])); \
6862 inst.operands[i].reg = val; \
6863 inst.operands[i].isreg = 1; \
6864 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6865 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6866 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6867 || rtype == REG_TYPE_VFD \
6868 || rtype == REG_TYPE_NQ); \
6872 #define po_reg_or_goto(regtype, label) \
6875 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6876 & inst.operands[i].vectype); \
6880 inst.operands[i].reg = val; \
6881 inst.operands[i].isreg = 1; \
6882 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6883 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6884 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6885 || rtype == REG_TYPE_VFD \
6886 || rtype == REG_TYPE_NQ); \
6890 #define po_imm_or_fail(min, max, popt) \
6893 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6895 inst.operands[i].imm = val; \
6899 #define po_scalar_or_goto(elsz, label) \
6902 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6905 inst.operands[i].reg = val; \
6906 inst.operands[i].isscalar = 1; \
6910 #define po_misc_or_fail(expr) \
6918 #define po_misc_or_fail_no_backtrack(expr) \
6922 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6923 backtrack_pos = 0; \
6924 if (result != PARSE_OPERAND_SUCCESS) \
6929 #define po_barrier_or_imm(str) \
6932 val = parse_barrier (&str); \
6933 if (val == FAIL && ! ISALPHA (*str)) \
6936 /* ISB can only take SY as an option. */ \
6937 || ((inst.instruction & 0xf0) == 0x60 \
6940 inst.error = _("invalid barrier type"); \
6941 backtrack_pos = 0; \
6947 skip_whitespace (str
);
6949 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6951 op_parse_code
= upat
[i
];
6952 if (op_parse_code
>= 1<<16)
6953 op_parse_code
= thumb
? (op_parse_code
>> 16)
6954 : (op_parse_code
& ((1<<16)-1));
6956 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6958 /* Remember where we are in case we need to backtrack. */
6959 gas_assert (!backtrack_pos
);
6960 backtrack_pos
= str
;
6961 backtrack_error
= inst
.error
;
6962 backtrack_index
= i
;
6965 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6966 po_char_or_fail (',');
6968 switch (op_parse_code
)
6978 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6979 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6980 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6981 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6982 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6983 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6986 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
6990 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
6993 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6995 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6997 /* Also accept generic coprocessor regs for unknown registers. */
6999 po_reg_or_fail (REG_TYPE_CN
);
7001 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7002 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7003 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7004 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7005 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7006 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7007 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7008 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7009 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7010 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7013 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7016 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7017 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7020 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7024 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7025 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7027 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7029 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7034 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7037 po_reg_or_fail (REG_TYPE_NSDQ
);
7040 /* Neon scalar. Using an element size of 8 means that some invalid
7041 scalars are accepted here, so deal with those in later code. */
7042 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
7046 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7049 po_imm_or_fail (0, 0, TRUE
);
7054 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7059 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7062 if (parse_ifimm_zero (&str
))
7063 inst
.operands
[i
].imm
= 0;
7067 = _("only floating point zero is allowed as immediate value");
7075 po_scalar_or_goto (8, try_rr
);
7078 po_reg_or_fail (REG_TYPE_RN
);
7084 po_scalar_or_goto (8, try_nsdq
);
7087 po_reg_or_fail (REG_TYPE_NSDQ
);
7093 po_scalar_or_goto (8, try_s_scalar
);
7096 po_scalar_or_goto (4, try_nsd
);
7099 po_reg_or_fail (REG_TYPE_NSD
);
7105 po_scalar_or_goto (8, try_ndq
);
7108 po_reg_or_fail (REG_TYPE_NDQ
);
7114 po_scalar_or_goto (8, try_vfd
);
7117 po_reg_or_fail (REG_TYPE_VFD
);
7122 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7123 not careful then bad things might happen. */
7124 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7129 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7132 /* There's a possibility of getting a 64-bit immediate here, so
7133 we need special handling. */
7134 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7137 inst
.error
= _("immediate value is out of range");
7145 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7148 po_imm_or_fail (0, 63, TRUE
);
7153 po_char_or_fail ('[');
7154 po_reg_or_fail (REG_TYPE_RN
);
7155 po_char_or_fail (']');
7161 po_reg_or_fail (REG_TYPE_RN
);
7162 if (skip_past_char (&str
, '!') == SUCCESS
)
7163 inst
.operands
[i
].writeback
= 1;
7167 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7168 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7169 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7170 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7171 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7172 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7173 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7174 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7175 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7176 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7177 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7178 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7180 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7182 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7183 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7185 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7186 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7187 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7188 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7190 /* Immediate variants */
7192 po_char_or_fail ('{');
7193 po_imm_or_fail (0, 255, TRUE
);
7194 po_char_or_fail ('}');
7198 /* The expression parser chokes on a trailing !, so we have
7199 to find it first and zap it. */
7202 while (*s
&& *s
!= ',')
7207 inst
.operands
[i
].writeback
= 1;
7209 po_imm_or_fail (0, 31, TRUE
);
7217 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7222 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7227 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7229 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7231 val
= parse_reloc (&str
);
7234 inst
.error
= _("unrecognized relocation suffix");
7237 else if (val
!= BFD_RELOC_UNUSED
)
7239 inst
.operands
[i
].imm
= val
;
7240 inst
.operands
[i
].hasreloc
= 1;
7246 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7248 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7250 inst
.operands
[i
].hasreloc
= 1;
7252 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7254 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7255 inst
.operands
[i
].hasreloc
= 0;
7259 /* Operand for MOVW or MOVT. */
7261 po_misc_or_fail (parse_half (&str
));
7264 /* Register or expression. */
7265 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7266 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7268 /* Register or immediate. */
7269 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7270 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7272 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7274 if (!is_immediate_prefix (*str
))
7277 val
= parse_fpa_immediate (&str
);
7280 /* FPA immediates are encoded as registers 8-15.
7281 parse_fpa_immediate has already applied the offset. */
7282 inst
.operands
[i
].reg
= val
;
7283 inst
.operands
[i
].isreg
= 1;
7286 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7287 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7289 /* Two kinds of register. */
7292 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7294 || (rege
->type
!= REG_TYPE_MMXWR
7295 && rege
->type
!= REG_TYPE_MMXWC
7296 && rege
->type
!= REG_TYPE_MMXWCG
))
7298 inst
.error
= _("iWMMXt data or control register expected");
7301 inst
.operands
[i
].reg
= rege
->number
;
7302 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7308 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7310 || (rege
->type
!= REG_TYPE_MMXWC
7311 && rege
->type
!= REG_TYPE_MMXWCG
))
7313 inst
.error
= _("iWMMXt control register expected");
7316 inst
.operands
[i
].reg
= rege
->number
;
7317 inst
.operands
[i
].isreg
= 1;
7322 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7323 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7324 case OP_oROR
: val
= parse_ror (&str
); break;
7325 case OP_COND
: val
= parse_cond (&str
); break;
7326 case OP_oBARRIER_I15
:
7327 po_barrier_or_imm (str
); break;
7329 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7335 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7336 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7338 inst
.error
= _("Banked registers are not available with this "
7344 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7348 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7351 val
= parse_sys_vldr_vstr (&str
);
7355 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7358 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7360 if (strncasecmp (str
, "APSR_", 5) == 0)
7367 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7368 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7369 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7370 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7371 default: found
= 16;
7375 inst
.operands
[i
].isvec
= 1;
7376 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7377 inst
.operands
[i
].reg
= REG_PC
;
7384 po_misc_or_fail (parse_tb (&str
));
7387 /* Register lists. */
7389 val
= parse_reg_list (&str
, REGLIST_RN
);
7392 inst
.operands
[i
].writeback
= 1;
7398 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7402 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7407 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7412 /* Allow Q registers too. */
7413 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7414 REGLIST_NEON_D
, &partial_match
);
7418 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7419 REGLIST_VFP_S
, &partial_match
);
7420 inst
.operands
[i
].issingle
= 1;
7425 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7426 REGLIST_VFP_D_VPR
, &partial_match
);
7427 if (val
== FAIL
&& !partial_match
)
7430 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7431 REGLIST_VFP_S_VPR
, &partial_match
);
7432 inst
.operands
[i
].issingle
= 1;
7437 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7438 REGLIST_NEON_D
, &partial_match
);
7442 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7443 &inst
.operands
[i
].vectype
);
7446 /* Addressing modes */
7448 po_misc_or_fail (parse_address (&str
, i
));
7452 po_misc_or_fail_no_backtrack (
7453 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7457 po_misc_or_fail_no_backtrack (
7458 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7462 po_misc_or_fail_no_backtrack (
7463 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7467 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7471 po_misc_or_fail_no_backtrack (
7472 parse_shifter_operand_group_reloc (&str
, i
));
7476 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7480 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7484 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7488 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7491 /* Various value-based sanity checks and shared operations. We
7492 do not signal immediate failures for the register constraints;
7493 this allows a syntax error to take precedence. */
7494 switch (op_parse_code
)
7502 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7503 inst
.error
= BAD_PC
;
7508 if (inst
.operands
[i
].isreg
)
7510 if (inst
.operands
[i
].reg
== REG_PC
)
7511 inst
.error
= BAD_PC
;
7512 else if (inst
.operands
[i
].reg
== REG_SP
7513 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7514 relaxed since ARMv8-A. */
7515 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7518 inst
.error
= BAD_SP
;
7524 if (inst
.operands
[i
].isreg
7525 && inst
.operands
[i
].reg
== REG_PC
7526 && (inst
.operands
[i
].writeback
|| thumb
))
7527 inst
.error
= BAD_PC
;
7531 if (inst
.operands
[i
].isreg
)
7540 case OP_oBARRIER_I15
:
7551 inst
.operands
[i
].imm
= val
;
7556 if (inst
.operands
[i
].reg
!= REG_LR
)
7557 inst
.error
= _("operand must be LR register");
7564 /* If we get here, this operand was successfully parsed. */
7565 inst
.operands
[i
].present
= 1;
7569 inst
.error
= BAD_ARGS
;
7574 /* The parse routine should already have set inst.error, but set a
7575 default here just in case. */
7577 inst
.error
= BAD_SYNTAX
;
7581 /* Do not backtrack over a trailing optional argument that
7582 absorbed some text. We will only fail again, with the
7583 'garbage following instruction' error message, which is
7584 probably less helpful than the current one. */
7585 if (backtrack_index
== i
&& backtrack_pos
!= str
7586 && upat
[i
+1] == OP_stop
)
7589 inst
.error
= BAD_SYNTAX
;
7593 /* Try again, skipping the optional argument at backtrack_pos. */
7594 str
= backtrack_pos
;
7595 inst
.error
= backtrack_error
;
7596 inst
.operands
[backtrack_index
].present
= 0;
7597 i
= backtrack_index
;
7601 /* Check that we have parsed all the arguments. */
7602 if (*str
!= '\0' && !inst
.error
)
7603 inst
.error
= _("garbage following instruction");
7605 return inst
.error
? FAIL
: SUCCESS
;
7608 #undef po_char_or_fail
7609 #undef po_reg_or_fail
7610 #undef po_reg_or_goto
7611 #undef po_imm_or_fail
7612 #undef po_scalar_or_fail
7613 #undef po_barrier_or_imm
7615 /* Shorthand macro for instruction encoding functions issuing errors. */
7616 #define constraint(expr, err) \
7627 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7628 instructions are unpredictable if these registers are used. This
7629 is the BadReg predicate in ARM's Thumb-2 documentation.
7631 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7632 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7633 #define reject_bad_reg(reg) \
7635 if (reg == REG_PC) \
7637 inst.error = BAD_PC; \
7640 else if (reg == REG_SP \
7641 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7643 inst.error = BAD_SP; \
7648 /* If REG is R13 (the stack pointer), warn that its use is
7650 #define warn_deprecated_sp(reg) \
7652 if (warn_on_deprecated && reg == REG_SP) \
7653 as_tsktsk (_("use of r13 is deprecated")); \
7656 /* Functions for operand encoding. ARM, then Thumb. */
7658 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7660 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7662 The only binary encoding difference is the Coprocessor number. Coprocessor
7663 9 is used for half-precision calculations or conversions. The format of the
7664 instruction is the same as the equivalent Coprocessor 10 instruction that
7665 exists for Single-Precision operation. */
7668 do_scalar_fp16_v82_encode (void)
7670 if (inst
.cond
< COND_ALWAYS
)
7671 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7672 " the behaviour is UNPREDICTABLE"));
7673 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7676 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7677 mark_feature_used (&arm_ext_fp16
);
7680 /* If VAL can be encoded in the immediate field of an ARM instruction,
7681 return the encoded form. Otherwise, return FAIL. */
7684 encode_arm_immediate (unsigned int val
)
7691 for (i
= 2; i
< 32; i
+= 2)
7692 if ((a
= rotate_left (val
, i
)) <= 0xff)
7693 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7698 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7699 return the encoded form. Otherwise, return FAIL. */
7701 encode_thumb32_immediate (unsigned int val
)
7708 for (i
= 1; i
<= 24; i
++)
7711 if ((val
& ~(0xff << i
)) == 0)
7712 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7716 if (val
== ((a
<< 16) | a
))
7718 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7722 if (val
== ((a
<< 16) | a
))
7723 return 0x200 | (a
>> 8);
7727 /* Encode a VFP SP or DP register number into inst.instruction. */
7730 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7732 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7735 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7738 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7741 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7746 first_error (_("D register out of range for selected VFP version"));
7754 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7758 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7762 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7766 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7770 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7774 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7782 /* Encode a <shift> in an ARM-format instruction. The immediate,
7783 if any, is handled by md_apply_fix. */
7785 encode_arm_shift (int i
)
7787 /* register-shifted register. */
7788 if (inst
.operands
[i
].immisreg
)
7791 for (op_index
= 0; op_index
<= i
; ++op_index
)
7793 /* Check the operand only when it's presented. In pre-UAL syntax,
7794 if the destination register is the same as the first operand, two
7795 register form of the instruction can be used. */
7796 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7797 && inst
.operands
[op_index
].reg
== REG_PC
)
7798 as_warn (UNPRED_REG ("r15"));
7801 if (inst
.operands
[i
].imm
== REG_PC
)
7802 as_warn (UNPRED_REG ("r15"));
7805 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7806 inst
.instruction
|= SHIFT_ROR
<< 5;
7809 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7810 if (inst
.operands
[i
].immisreg
)
7812 inst
.instruction
|= SHIFT_BY_REG
;
7813 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7816 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7821 encode_arm_shifter_operand (int i
)
7823 if (inst
.operands
[i
].isreg
)
7825 inst
.instruction
|= inst
.operands
[i
].reg
;
7826 encode_arm_shift (i
);
7830 inst
.instruction
|= INST_IMMEDIATE
;
7831 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
7832 inst
.instruction
|= inst
.operands
[i
].imm
;
7836 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7838 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7841 Generate an error if the operand is not a register. */
7842 constraint (!inst
.operands
[i
].isreg
,
7843 _("Instruction does not support =N addresses"));
7845 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7847 if (inst
.operands
[i
].preind
)
7851 inst
.error
= _("instruction does not accept preindexed addressing");
7854 inst
.instruction
|= PRE_INDEX
;
7855 if (inst
.operands
[i
].writeback
)
7856 inst
.instruction
|= WRITE_BACK
;
7859 else if (inst
.operands
[i
].postind
)
7861 gas_assert (inst
.operands
[i
].writeback
);
7863 inst
.instruction
|= WRITE_BACK
;
7865 else /* unindexed - only for coprocessor */
7867 inst
.error
= _("instruction does not accept unindexed addressing");
7871 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7872 && (((inst
.instruction
& 0x000f0000) >> 16)
7873 == ((inst
.instruction
& 0x0000f000) >> 12)))
7874 as_warn ((inst
.instruction
& LOAD_BIT
)
7875 ? _("destination register same as write-back base")
7876 : _("source register same as write-back base"));
7879 /* inst.operands[i] was set up by parse_address. Encode it into an
7880 ARM-format mode 2 load or store instruction. If is_t is true,
7881 reject forms that cannot be used with a T instruction (i.e. not
7884 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7886 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7888 encode_arm_addr_mode_common (i
, is_t
);
7890 if (inst
.operands
[i
].immisreg
)
7892 constraint ((inst
.operands
[i
].imm
== REG_PC
7893 || (is_pc
&& inst
.operands
[i
].writeback
)),
7895 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7896 inst
.instruction
|= inst
.operands
[i
].imm
;
7897 if (!inst
.operands
[i
].negative
)
7898 inst
.instruction
|= INDEX_UP
;
7899 if (inst
.operands
[i
].shifted
)
7901 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7902 inst
.instruction
|= SHIFT_ROR
<< 5;
7905 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7906 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
7910 else /* immediate offset in inst.relocs[0] */
7912 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
7914 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7916 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7917 cannot use PC in addressing.
7918 PC cannot be used in writeback addressing, either. */
7919 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7922 /* Use of PC in str is deprecated for ARMv7. */
7923 if (warn_on_deprecated
7925 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7926 as_tsktsk (_("use of PC in this instruction is deprecated"));
7929 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7931 /* Prefer + for zero encoded value. */
7932 if (!inst
.operands
[i
].negative
)
7933 inst
.instruction
|= INDEX_UP
;
7934 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
7939 /* inst.operands[i] was set up by parse_address. Encode it into an
7940 ARM-format mode 3 load or store instruction. Reject forms that
7941 cannot be used with such instructions. If is_t is true, reject
7942 forms that cannot be used with a T instruction (i.e. not
7945 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7947 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7949 inst
.error
= _("instruction does not accept scaled register index");
7953 encode_arm_addr_mode_common (i
, is_t
);
7955 if (inst
.operands
[i
].immisreg
)
7957 constraint ((inst
.operands
[i
].imm
== REG_PC
7958 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7960 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7962 inst
.instruction
|= inst
.operands
[i
].imm
;
7963 if (!inst
.operands
[i
].negative
)
7964 inst
.instruction
|= INDEX_UP
;
7966 else /* immediate offset in inst.relocs[0] */
7968 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
7969 && inst
.operands
[i
].writeback
),
7971 inst
.instruction
|= HWOFFSET_IMM
;
7972 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
7974 /* Prefer + for zero encoded value. */
7975 if (!inst
.operands
[i
].negative
)
7976 inst
.instruction
|= INDEX_UP
;
7978 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7983 /* Write immediate bits [7:0] to the following locations:
7985 |28/24|23 19|18 16|15 4|3 0|
7986 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7988 This function is used by VMOV/VMVN/VORR/VBIC. */
7991 neon_write_immbits (unsigned immbits
)
7993 inst
.instruction
|= immbits
& 0xf;
7994 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7995 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7998 /* Invert low-order SIZE bits of XHI:XLO. */
8001 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8003 unsigned immlo
= xlo
? *xlo
: 0;
8004 unsigned immhi
= xhi
? *xhi
: 0;
8009 immlo
= (~immlo
) & 0xff;
8013 immlo
= (~immlo
) & 0xffff;
8017 immhi
= (~immhi
) & 0xffffffff;
8021 immlo
= (~immlo
) & 0xffffffff;
8035 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8039 neon_bits_same_in_bytes (unsigned imm
)
8041 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8042 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8043 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8044 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8047 /* For immediate of above form, return 0bABCD. */
8050 neon_squash_bits (unsigned imm
)
8052 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8053 | ((imm
& 0x01000000) >> 21);
8056 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8059 neon_qfloat_bits (unsigned imm
)
8061 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8064 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8065 the instruction. *OP is passed as the initial value of the op field, and
8066 may be set to a different value depending on the constant (i.e.
8067 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8068 MVN). If the immediate looks like a repeated pattern then also
8069 try smaller element sizes. */
8072 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8073 unsigned *immbits
, int *op
, int size
,
8074 enum neon_el_type type
)
8076 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8078 if (type
== NT_float
&& !float_p
)
8081 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8083 if (size
!= 32 || *op
== 1)
8085 *immbits
= neon_qfloat_bits (immlo
);
8091 if (neon_bits_same_in_bytes (immhi
)
8092 && neon_bits_same_in_bytes (immlo
))
8096 *immbits
= (neon_squash_bits (immhi
) << 4)
8097 | neon_squash_bits (immlo
);
8108 if (immlo
== (immlo
& 0x000000ff))
8113 else if (immlo
== (immlo
& 0x0000ff00))
8115 *immbits
= immlo
>> 8;
8118 else if (immlo
== (immlo
& 0x00ff0000))
8120 *immbits
= immlo
>> 16;
8123 else if (immlo
== (immlo
& 0xff000000))
8125 *immbits
= immlo
>> 24;
8128 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8130 *immbits
= (immlo
>> 8) & 0xff;
8133 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8135 *immbits
= (immlo
>> 16) & 0xff;
8139 if ((immlo
& 0xffff) != (immlo
>> 16))
8146 if (immlo
== (immlo
& 0x000000ff))
8151 else if (immlo
== (immlo
& 0x0000ff00))
8153 *immbits
= immlo
>> 8;
8157 if ((immlo
& 0xff) != (immlo
>> 8))
8162 if (immlo
== (immlo
& 0x000000ff))
8164 /* Don't allow MVN with 8-bit immediate. */
8174 #if defined BFD_HOST_64_BIT
8175 /* Returns TRUE if double precision value V may be cast
8176 to single precision without loss of accuracy. */
8179 is_double_a_single (bfd_int64_t v
)
8181 int exp
= (int)((v
>> 52) & 0x7FF);
8182 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8184 return (exp
== 0 || exp
== 0x7FF
8185 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8186 && (mantissa
& 0x1FFFFFFFl
) == 0;
8189 /* Returns a double precision value casted to single precision
8190 (ignoring the least significant bits in exponent and mantissa). */
8193 double_to_single (bfd_int64_t v
)
8195 int sign
= (int) ((v
>> 63) & 1l);
8196 int exp
= (int) ((v
>> 52) & 0x7FF);
8197 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8203 exp
= exp
- 1023 + 127;
8212 /* No denormalized numbers. */
8218 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8220 #endif /* BFD_HOST_64_BIT */
8229 static void do_vfp_nsyn_opcode (const char *);
8231 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8232 Determine whether it can be performed with a move instruction; if
8233 it can, convert inst.instruction to that move instruction and
8234 return TRUE; if it can't, convert inst.instruction to a literal-pool
8235 load and return FALSE. If this is not a valid thing to do in the
8236 current context, set inst.error and return TRUE.
8238 inst.operands[i] describes the destination register. */
8241 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8244 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8245 bfd_boolean arm_p
= (t
== CONST_ARM
);
8248 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8252 if ((inst
.instruction
& tbit
) == 0)
8254 inst
.error
= _("invalid pseudo operation");
8258 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8259 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8260 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8262 inst
.error
= _("constant expression expected");
8266 if (inst
.relocs
[0].exp
.X_op
== O_constant
8267 || inst
.relocs
[0].exp
.X_op
== O_big
)
8269 #if defined BFD_HOST_64_BIT
8274 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8276 LITTLENUM_TYPE w
[X_PRECISION
];
8279 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8281 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8283 /* FIXME: Should we check words w[2..5] ? */
8288 #if defined BFD_HOST_64_BIT
8290 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8291 << LITTLENUM_NUMBER_OF_BITS
)
8292 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8293 << LITTLENUM_NUMBER_OF_BITS
)
8294 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8295 << LITTLENUM_NUMBER_OF_BITS
)
8296 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8298 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8299 | (l
[0] & LITTLENUM_MASK
);
8303 v
= inst
.relocs
[0].exp
.X_add_number
;
8305 if (!inst
.operands
[i
].issingle
)
8309 /* LDR should not use lead in a flag-setting instruction being
8310 chosen so we do not check whether movs can be used. */
8312 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8313 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8314 && inst
.operands
[i
].reg
!= 13
8315 && inst
.operands
[i
].reg
!= 15)
8317 /* Check if on thumb2 it can be done with a mov.w, mvn or
8318 movw instruction. */
8319 unsigned int newimm
;
8320 bfd_boolean isNegated
;
8322 newimm
= encode_thumb32_immediate (v
);
8323 if (newimm
!= (unsigned int) FAIL
)
8327 newimm
= encode_thumb32_immediate (~v
);
8328 if (newimm
!= (unsigned int) FAIL
)
8332 /* The number can be loaded with a mov.w or mvn
8334 if (newimm
!= (unsigned int) FAIL
8335 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8337 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8338 | (inst
.operands
[i
].reg
<< 8));
8339 /* Change to MOVN. */
8340 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8341 inst
.instruction
|= (newimm
& 0x800) << 15;
8342 inst
.instruction
|= (newimm
& 0x700) << 4;
8343 inst
.instruction
|= (newimm
& 0x0ff);
8346 /* The number can be loaded with a movw instruction. */
8347 else if ((v
& ~0xFFFF) == 0
8348 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8350 int imm
= v
& 0xFFFF;
8352 inst
.instruction
= 0xf2400000; /* MOVW. */
8353 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8354 inst
.instruction
|= (imm
& 0xf000) << 4;
8355 inst
.instruction
|= (imm
& 0x0800) << 15;
8356 inst
.instruction
|= (imm
& 0x0700) << 4;
8357 inst
.instruction
|= (imm
& 0x00ff);
8364 int value
= encode_arm_immediate (v
);
8368 /* This can be done with a mov instruction. */
8369 inst
.instruction
&= LITERAL_MASK
;
8370 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8371 inst
.instruction
|= value
& 0xfff;
8375 value
= encode_arm_immediate (~ v
);
8378 /* This can be done with a mvn instruction. */
8379 inst
.instruction
&= LITERAL_MASK
;
8380 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8381 inst
.instruction
|= value
& 0xfff;
8385 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8388 unsigned immbits
= 0;
8389 unsigned immlo
= inst
.operands
[1].imm
;
8390 unsigned immhi
= inst
.operands
[1].regisimm
8391 ? inst
.operands
[1].reg
8392 : inst
.relocs
[0].exp
.X_unsigned
8394 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8395 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8396 &op
, 64, NT_invtype
);
8400 neon_invert_size (&immlo
, &immhi
, 64);
8402 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8403 &op
, 64, NT_invtype
);
8408 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8414 /* Fill other bits in vmov encoding for both thumb and arm. */
8416 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8418 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8419 neon_write_immbits (immbits
);
8427 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8428 if (inst
.operands
[i
].issingle
8429 && is_quarter_float (inst
.operands
[1].imm
)
8430 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8432 inst
.operands
[1].imm
=
8433 neon_qfloat_bits (v
);
8434 do_vfp_nsyn_opcode ("fconsts");
8438 /* If our host does not support a 64-bit type then we cannot perform
8439 the following optimization. This mean that there will be a
8440 discrepancy between the output produced by an assembler built for
8441 a 32-bit-only host and the output produced from a 64-bit host, but
8442 this cannot be helped. */
8443 #if defined BFD_HOST_64_BIT
8444 else if (!inst
.operands
[1].issingle
8445 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8447 if (is_double_a_single (v
)
8448 && is_quarter_float (double_to_single (v
)))
8450 inst
.operands
[1].imm
=
8451 neon_qfloat_bits (double_to_single (v
));
8452 do_vfp_nsyn_opcode ("fconstd");
8460 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8461 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8464 inst
.operands
[1].reg
= REG_PC
;
8465 inst
.operands
[1].isreg
= 1;
8466 inst
.operands
[1].preind
= 1;
8467 inst
.relocs
[0].pc_rel
= 1;
8468 inst
.relocs
[0].type
= (thumb_p
8469 ? BFD_RELOC_ARM_THUMB_OFFSET
8471 ? BFD_RELOC_ARM_HWLITERAL
8472 : BFD_RELOC_ARM_LITERAL
));
8476 /* inst.operands[i] was set up by parse_address. Encode it into an
8477 ARM-format instruction. Reject all forms which cannot be encoded
8478 into a coprocessor load/store instruction. If wb_ok is false,
8479 reject use of writeback; if unind_ok is false, reject use of
8480 unindexed addressing. If reloc_override is not 0, use it instead
8481 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8482 (in which case it is preserved). */
8485 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8487 if (!inst
.operands
[i
].isreg
)
8490 if (! inst
.operands
[0].isvec
)
8492 inst
.error
= _("invalid co-processor operand");
8495 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8499 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8501 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8503 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8505 gas_assert (!inst
.operands
[i
].writeback
);
8508 inst
.error
= _("instruction does not support unindexed addressing");
8511 inst
.instruction
|= inst
.operands
[i
].imm
;
8512 inst
.instruction
|= INDEX_UP
;
8516 if (inst
.operands
[i
].preind
)
8517 inst
.instruction
|= PRE_INDEX
;
8519 if (inst
.operands
[i
].writeback
)
8521 if (inst
.operands
[i
].reg
== REG_PC
)
8523 inst
.error
= _("pc may not be used with write-back");
8528 inst
.error
= _("instruction does not support writeback");
8531 inst
.instruction
|= WRITE_BACK
;
8535 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8536 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8537 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8538 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8541 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8543 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8546 /* Prefer + for zero encoded value. */
8547 if (!inst
.operands
[i
].negative
)
8548 inst
.instruction
|= INDEX_UP
;
8553 /* Functions for instruction encoding, sorted by sub-architecture.
8554 First some generics; their names are taken from the conventional
8555 bit positions for register arguments in ARM format instructions. */
8565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8578 inst
.instruction
|= inst
.operands
[1].reg
;
8584 inst
.instruction
|= inst
.operands
[0].reg
;
8585 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8592 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8598 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8599 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8610 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8612 if (ARM_CPU_IS_ANY (cpu_variant
))
8614 as_tsktsk ("%s", msg
);
8617 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8629 unsigned Rn
= inst
.operands
[2].reg
;
8630 /* Enforce restrictions on SWP instruction. */
8631 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8633 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8634 _("Rn must not overlap other operands"));
8636 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8638 if (!check_obsolete (&arm_ext_v8
,
8639 _("swp{b} use is obsoleted for ARMv8 and later"))
8640 && warn_on_deprecated
8641 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8642 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8646 inst
.instruction
|= inst
.operands
[1].reg
;
8647 inst
.instruction
|= Rn
<< 16;
8653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8655 inst
.instruction
|= inst
.operands
[2].reg
;
8661 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8662 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8663 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8664 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8666 inst
.instruction
|= inst
.operands
[0].reg
;
8667 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8668 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8674 inst
.instruction
|= inst
.operands
[0].imm
;
8680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8681 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8684 /* ARM instructions, in alphabetical order by function name (except
8685 that wrapper functions appear immediately after the function they
8688 /* This is a pseudo-op of the form "adr rd, label" to be converted
8689 into a relative address of the form "add rd, pc, #label-.-8". */
8694 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8696 /* Frag hacking will turn this into a sub instruction if the offset turns
8697 out to be negative. */
8698 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8699 inst
.relocs
[0].pc_rel
= 1;
8700 inst
.relocs
[0].exp
.X_add_number
-= 8;
8702 if (support_interwork
8703 && inst
.relocs
[0].exp
.X_op
== O_symbol
8704 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8705 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8706 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8707 inst
.relocs
[0].exp
.X_add_number
|= 1;
8710 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8711 into a relative address of the form:
8712 add rd, pc, #low(label-.-8)"
8713 add rd, rd, #high(label-.-8)" */
8718 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8720 /* Frag hacking will turn this into a sub instruction if the offset turns
8721 out to be negative. */
8722 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8723 inst
.relocs
[0].pc_rel
= 1;
8724 inst
.size
= INSN_SIZE
* 2;
8725 inst
.relocs
[0].exp
.X_add_number
-= 8;
8727 if (support_interwork
8728 && inst
.relocs
[0].exp
.X_op
== O_symbol
8729 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
8730 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
8731 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
8732 inst
.relocs
[0].exp
.X_add_number
|= 1;
8738 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8739 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8741 if (!inst
.operands
[1].present
)
8742 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8744 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8745 encode_arm_shifter_operand (2);
8751 if (inst
.operands
[0].present
)
8752 inst
.instruction
|= inst
.operands
[0].imm
;
8754 inst
.instruction
|= 0xf;
8760 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8761 constraint (msb
> 32, _("bit-field extends past end of register"));
8762 /* The instruction encoding stores the LSB and MSB,
8763 not the LSB and width. */
8764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8765 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8766 inst
.instruction
|= (msb
- 1) << 16;
8774 /* #0 in second position is alternative syntax for bfc, which is
8775 the same instruction but with REG_PC in the Rm field. */
8776 if (!inst
.operands
[1].isreg
)
8777 inst
.operands
[1].reg
= REG_PC
;
8779 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8780 constraint (msb
> 32, _("bit-field extends past end of register"));
8781 /* The instruction encoding stores the LSB and MSB,
8782 not the LSB and width. */
8783 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8784 inst
.instruction
|= inst
.operands
[1].reg
;
8785 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8786 inst
.instruction
|= (msb
- 1) << 16;
8792 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8793 _("bit-field extends past end of register"));
8794 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8795 inst
.instruction
|= inst
.operands
[1].reg
;
8796 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8797 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8800 /* ARM V5 breakpoint instruction (argument parse)
8801 BKPT <16 bit unsigned immediate>
8802 Instruction is not conditional.
8803 The bit pattern given in insns[] has the COND_ALWAYS condition,
8804 and it is an error if the caller tried to override that. */
8809 /* Top 12 of 16 bits to bits 19:8. */
8810 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8812 /* Bottom 4 of 16 bits to bits 3:0. */
8813 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8817 encode_branch (int default_reloc
)
8819 if (inst
.operands
[0].hasreloc
)
8821 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8822 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8823 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8824 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8825 ? BFD_RELOC_ARM_PLT32
8826 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8829 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
8830 inst
.relocs
[0].pc_rel
= 1;
8837 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8838 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8841 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8848 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8850 if (inst
.cond
== COND_ALWAYS
)
8851 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8853 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8857 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8860 /* ARM V5 branch-link-exchange instruction (argument parse)
8861 BLX <target_addr> ie BLX(1)
8862 BLX{<condition>} <Rm> ie BLX(2)
8863 Unfortunately, there are two different opcodes for this mnemonic.
8864 So, the insns[].value is not used, and the code here zaps values
8865 into inst.instruction.
8866 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8871 if (inst
.operands
[0].isreg
)
8873 /* Arg is a register; the opcode provided by insns[] is correct.
8874 It is not illegal to do "blx pc", just useless. */
8875 if (inst
.operands
[0].reg
== REG_PC
)
8876 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8878 inst
.instruction
|= inst
.operands
[0].reg
;
8882 /* Arg is an address; this instruction cannot be executed
8883 conditionally, and the opcode must be adjusted.
8884 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8885 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8886 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8887 inst
.instruction
= 0xfa000000;
8888 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8895 bfd_boolean want_reloc
;
8897 if (inst
.operands
[0].reg
== REG_PC
)
8898 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8900 inst
.instruction
|= inst
.operands
[0].reg
;
8901 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8902 it is for ARMv4t or earlier. */
8903 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8904 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8905 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8909 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8914 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
8918 /* ARM v5TEJ. Jump to Jazelle code. */
8923 if (inst
.operands
[0].reg
== REG_PC
)
8924 as_tsktsk (_("use of r15 in bxj is not really useful"));
8926 inst
.instruction
|= inst
.operands
[0].reg
;
8929 /* Co-processor data operation:
8930 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8931 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8935 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8936 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8937 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8938 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8939 inst
.instruction
|= inst
.operands
[4].reg
;
8940 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8946 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8947 encode_arm_shifter_operand (1);
8950 /* Transfer between coprocessor and ARM registers.
8951 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8956 No special properties. */
8958 struct deprecated_coproc_regs_s
8965 arm_feature_set deprecated
;
8966 arm_feature_set obsoleted
;
8967 const char *dep_msg
;
8968 const char *obs_msg
;
8971 #define DEPR_ACCESS_V8 \
8972 N_("This coprocessor register access is deprecated in ARMv8")
8974 /* Table of all deprecated coprocessor registers. */
8975 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8977 {15, 0, 7, 10, 5, /* CP15DMB. */
8978 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8979 DEPR_ACCESS_V8
, NULL
},
8980 {15, 0, 7, 10, 4, /* CP15DSB. */
8981 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8982 DEPR_ACCESS_V8
, NULL
},
8983 {15, 0, 7, 5, 4, /* CP15ISB. */
8984 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8985 DEPR_ACCESS_V8
, NULL
},
8986 {14, 6, 1, 0, 0, /* TEEHBR. */
8987 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8988 DEPR_ACCESS_V8
, NULL
},
8989 {14, 6, 0, 0, 0, /* TEECR. */
8990 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8991 DEPR_ACCESS_V8
, NULL
},
8994 #undef DEPR_ACCESS_V8
8996 static const size_t deprecated_coproc_reg_count
=
8997 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9005 Rd
= inst
.operands
[2].reg
;
9008 if (inst
.instruction
== 0xee000010
9009 || inst
.instruction
== 0xfe000010)
9011 reject_bad_reg (Rd
);
9012 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9014 constraint (Rd
== REG_SP
, BAD_SP
);
9019 if (inst
.instruction
== 0xe000010)
9020 constraint (Rd
== REG_PC
, BAD_PC
);
9023 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9025 const struct deprecated_coproc_regs_s
*r
=
9026 deprecated_coproc_regs
+ i
;
9028 if (inst
.operands
[0].reg
== r
->cp
9029 && inst
.operands
[1].imm
== r
->opc1
9030 && inst
.operands
[3].reg
== r
->crn
9031 && inst
.operands
[4].reg
== r
->crm
9032 && inst
.operands
[5].imm
== r
->opc2
)
9034 if (! ARM_CPU_IS_ANY (cpu_variant
)
9035 && warn_on_deprecated
9036 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9037 as_tsktsk ("%s", r
->dep_msg
);
9041 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9042 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9043 inst
.instruction
|= Rd
<< 12;
9044 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9045 inst
.instruction
|= inst
.operands
[4].reg
;
9046 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9049 /* Transfer between coprocessor register and pair of ARM registers.
9050 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9055 Two XScale instructions are special cases of these:
9057 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9058 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9060 Result unpredictable if Rd or Rn is R15. */
9067 Rd
= inst
.operands
[2].reg
;
9068 Rn
= inst
.operands
[3].reg
;
9072 reject_bad_reg (Rd
);
9073 reject_bad_reg (Rn
);
9077 constraint (Rd
== REG_PC
, BAD_PC
);
9078 constraint (Rn
== REG_PC
, BAD_PC
);
9081 /* Only check the MRRC{2} variants. */
9082 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9084 /* If Rd == Rn, error that the operation is
9085 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9086 constraint (Rd
== Rn
, BAD_OVERLAP
);
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9090 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9091 inst
.instruction
|= Rd
<< 12;
9092 inst
.instruction
|= Rn
<< 16;
9093 inst
.instruction
|= inst
.operands
[4].reg
;
9099 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9100 if (inst
.operands
[1].present
)
9102 inst
.instruction
|= CPSI_MMOD
;
9103 inst
.instruction
|= inst
.operands
[1].imm
;
9110 inst
.instruction
|= inst
.operands
[0].imm
;
9116 unsigned Rd
, Rn
, Rm
;
9118 Rd
= inst
.operands
[0].reg
;
9119 Rn
= (inst
.operands
[1].present
9120 ? inst
.operands
[1].reg
: Rd
);
9121 Rm
= inst
.operands
[2].reg
;
9123 constraint ((Rd
== REG_PC
), BAD_PC
);
9124 constraint ((Rn
== REG_PC
), BAD_PC
);
9125 constraint ((Rm
== REG_PC
), BAD_PC
);
9127 inst
.instruction
|= Rd
<< 16;
9128 inst
.instruction
|= Rn
<< 0;
9129 inst
.instruction
|= Rm
<< 8;
9135 /* There is no IT instruction in ARM mode. We
9136 process it to do the validation as if in
9137 thumb mode, just in case the code gets
9138 assembled for thumb using the unified syntax. */
9143 set_pred_insn_type (IT_INSN
);
9144 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9145 now_pred
.cc
= inst
.operands
[0].imm
;
9149 /* If there is only one register in the register list,
9150 then return its register number. Otherwise return -1. */
9152 only_one_reg_in_list (int range
)
9154 int i
= ffs (range
) - 1;
9155 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9159 encode_ldmstm(int from_push_pop_mnem
)
9161 int base_reg
= inst
.operands
[0].reg
;
9162 int range
= inst
.operands
[1].imm
;
9165 inst
.instruction
|= base_reg
<< 16;
9166 inst
.instruction
|= range
;
9168 if (inst
.operands
[1].writeback
)
9169 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9171 if (inst
.operands
[0].writeback
)
9173 inst
.instruction
|= WRITE_BACK
;
9174 /* Check for unpredictable uses of writeback. */
9175 if (inst
.instruction
& LOAD_BIT
)
9177 /* Not allowed in LDM type 2. */
9178 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9179 && ((range
& (1 << REG_PC
)) == 0))
9180 as_warn (_("writeback of base register is UNPREDICTABLE"));
9181 /* Only allowed if base reg not in list for other types. */
9182 else if (range
& (1 << base_reg
))
9183 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9187 /* Not allowed for type 2. */
9188 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9189 as_warn (_("writeback of base register is UNPREDICTABLE"));
9190 /* Only allowed if base reg not in list, or first in list. */
9191 else if ((range
& (1 << base_reg
))
9192 && (range
& ((1 << base_reg
) - 1)))
9193 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9197 /* If PUSH/POP has only one register, then use the A2 encoding. */
9198 one_reg
= only_one_reg_in_list (range
);
9199 if (from_push_pop_mnem
&& one_reg
>= 0)
9201 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9203 if (is_push
&& one_reg
== 13 /* SP */)
9204 /* PR 22483: The A2 encoding cannot be used when
9205 pushing the stack pointer as this is UNPREDICTABLE. */
9208 inst
.instruction
&= A_COND_MASK
;
9209 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9210 inst
.instruction
|= one_reg
<< 12;
9217 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9220 /* ARMv5TE load-consecutive (argument parse)
9229 constraint (inst
.operands
[0].reg
% 2 != 0,
9230 _("first transfer register must be even"));
9231 constraint (inst
.operands
[1].present
9232 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9233 _("can only transfer two consecutive registers"));
9234 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9235 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9237 if (!inst
.operands
[1].present
)
9238 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9240 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9241 register and the first register written; we have to diagnose
9242 overlap between the base and the second register written here. */
9244 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9245 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9246 as_warn (_("base register written back, and overlaps "
9247 "second transfer register"));
9249 if (!(inst
.instruction
& V4_STR_BIT
))
9251 /* For an index-register load, the index register must not overlap the
9252 destination (even if not write-back). */
9253 if (inst
.operands
[2].immisreg
9254 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9255 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9256 as_warn (_("index register overlaps transfer register"));
9258 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9259 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9265 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9266 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9267 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9268 || inst
.operands
[1].negative
9269 /* This can arise if the programmer has written
9271 or if they have mistakenly used a register name as the last
9274 It is very difficult to distinguish between these two cases
9275 because "rX" might actually be a label. ie the register
9276 name has been occluded by a symbol of the same name. So we
9277 just generate a general 'bad addressing mode' type error
9278 message and leave it up to the programmer to discover the
9279 true cause and fix their mistake. */
9280 || (inst
.operands
[1].reg
== REG_PC
),
9283 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9284 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9285 _("offset must be zero in ARM encoding"));
9287 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9291 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9297 constraint (inst
.operands
[0].reg
% 2 != 0,
9298 _("even register required"));
9299 constraint (inst
.operands
[1].present
9300 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9301 _("can only load two consecutive registers"));
9302 /* If op 1 were present and equal to PC, this function wouldn't
9303 have been called in the first place. */
9304 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9307 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9310 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9311 which is not a multiple of four is UNPREDICTABLE. */
9313 check_ldr_r15_aligned (void)
9315 constraint (!(inst
.operands
[1].immisreg
)
9316 && (inst
.operands
[0].reg
== REG_PC
9317 && inst
.operands
[1].reg
== REG_PC
9318 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9319 _("ldr to register 15 must be 4-byte aligned"));
9325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9326 if (!inst
.operands
[1].isreg
)
9327 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9329 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9330 check_ldr_r15_aligned ();
9336 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9338 if (inst
.operands
[1].preind
)
9340 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9341 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9342 _("this instruction requires a post-indexed address"));
9344 inst
.operands
[1].preind
= 0;
9345 inst
.operands
[1].postind
= 1;
9346 inst
.operands
[1].writeback
= 1;
9348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9349 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9352 /* Halfword and signed-byte load/store operations. */
9357 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9359 if (!inst
.operands
[1].isreg
)
9360 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9362 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9368 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9370 if (inst
.operands
[1].preind
)
9372 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9373 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9374 _("this instruction requires a post-indexed address"));
9376 inst
.operands
[1].preind
= 0;
9377 inst
.operands
[1].postind
= 1;
9378 inst
.operands
[1].writeback
= 1;
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9381 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9384 /* Co-processor register load/store.
9385 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9389 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9390 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9391 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9397 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9398 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9399 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9400 && !(inst
.instruction
& 0x00400000))
9401 as_tsktsk (_("Rd and Rm should be different in mla"));
9403 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9404 inst
.instruction
|= inst
.operands
[1].reg
;
9405 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9406 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9412 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9413 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9415 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9416 encode_arm_shifter_operand (1);
9419 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9426 top
= (inst
.instruction
& 0x00400000) != 0;
9427 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9428 _(":lower16: not allowed in this instruction"));
9429 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9430 _(":upper16: not allowed in this instruction"));
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9432 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9434 imm
= inst
.relocs
[0].exp
.X_add_number
;
9435 /* The value is in two pieces: 0:11, 16:19. */
9436 inst
.instruction
|= (imm
& 0x00000fff);
9437 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9442 do_vfp_nsyn_mrs (void)
9444 if (inst
.operands
[0].isvec
)
9446 if (inst
.operands
[1].reg
!= 1)
9447 first_error (_("operand 1 must be FPSCR"));
9448 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9449 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9450 do_vfp_nsyn_opcode ("fmstat");
9452 else if (inst
.operands
[1].isvec
)
9453 do_vfp_nsyn_opcode ("fmrx");
9461 do_vfp_nsyn_msr (void)
9463 if (inst
.operands
[0].isvec
)
9464 do_vfp_nsyn_opcode ("fmxr");
9474 unsigned Rt
= inst
.operands
[0].reg
;
9476 if (thumb_mode
&& Rt
== REG_SP
)
9478 inst
.error
= BAD_SP
;
9482 /* MVFR2 is only valid at ARMv8-A. */
9483 if (inst
.operands
[1].reg
== 5)
9484 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9487 /* APSR_ sets isvec. All other refs to PC are illegal. */
9488 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9490 inst
.error
= BAD_PC
;
9494 /* If we get through parsing the register name, we just insert the number
9495 generated into the instruction without further validation. */
9496 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9497 inst
.instruction
|= (Rt
<< 12);
9503 unsigned Rt
= inst
.operands
[1].reg
;
9506 reject_bad_reg (Rt
);
9507 else if (Rt
== REG_PC
)
9509 inst
.error
= BAD_PC
;
9513 /* MVFR2 is only valid for ARMv8-A. */
9514 if (inst
.operands
[0].reg
== 5)
9515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9518 /* If we get through parsing the register name, we just insert the number
9519 generated into the instruction without further validation. */
9520 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9521 inst
.instruction
|= (Rt
<< 12);
9529 if (do_vfp_nsyn_mrs () == SUCCESS
)
9532 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9535 if (inst
.operands
[1].isreg
)
9537 br
= inst
.operands
[1].reg
;
9538 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9539 as_bad (_("bad register for mrs"));
9543 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9544 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9546 _("'APSR', 'CPSR' or 'SPSR' expected"));
9547 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9550 inst
.instruction
|= br
;
9553 /* Two possible forms:
9554 "{C|S}PSR_<field>, Rm",
9555 "{C|S}PSR_f, #expression". */
9560 if (do_vfp_nsyn_msr () == SUCCESS
)
9563 inst
.instruction
|= inst
.operands
[0].imm
;
9564 if (inst
.operands
[1].isreg
)
9565 inst
.instruction
|= inst
.operands
[1].reg
;
9568 inst
.instruction
|= INST_IMMEDIATE
;
9569 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9570 inst
.relocs
[0].pc_rel
= 0;
9577 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9579 if (!inst
.operands
[2].present
)
9580 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9581 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9582 inst
.instruction
|= inst
.operands
[1].reg
;
9583 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9585 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9586 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9587 as_tsktsk (_("Rd and Rm should be different in mul"));
9590 /* Long Multiply Parser
9591 UMULL RdLo, RdHi, Rm, Rs
9592 SMULL RdLo, RdHi, Rm, Rs
9593 UMLAL RdLo, RdHi, Rm, Rs
9594 SMLAL RdLo, RdHi, Rm, Rs. */
9599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9600 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9601 inst
.instruction
|= inst
.operands
[2].reg
;
9602 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9604 /* rdhi and rdlo must be different. */
9605 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9606 as_tsktsk (_("rdhi and rdlo must be different"));
9608 /* rdhi, rdlo and rm must all be different before armv6. */
9609 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9610 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9611 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9612 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9618 if (inst
.operands
[0].present
9619 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9621 /* Architectural NOP hints are CPSR sets with no bits selected. */
9622 inst
.instruction
&= 0xf0000000;
9623 inst
.instruction
|= 0x0320f000;
9624 if (inst
.operands
[0].present
)
9625 inst
.instruction
|= inst
.operands
[0].imm
;
9629 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9630 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9631 Condition defaults to COND_ALWAYS.
9632 Error if Rd, Rn or Rm are R15. */
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9639 inst
.instruction
|= inst
.operands
[2].reg
;
9640 if (inst
.operands
[3].present
)
9641 encode_arm_shift (3);
9644 /* ARM V6 PKHTB (Argument Parse). */
9649 if (!inst
.operands
[3].present
)
9651 /* If the shift specifier is omitted, turn the instruction
9652 into pkhbt rd, rm, rn. */
9653 inst
.instruction
&= 0xfff00010;
9654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9655 inst
.instruction
|= inst
.operands
[1].reg
;
9656 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9661 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9662 inst
.instruction
|= inst
.operands
[2].reg
;
9663 encode_arm_shift (3);
9667 /* ARMv5TE: Preload-Cache
9668 MP Extensions: Preload for write
9672 Syntactically, like LDR with B=1, W=0, L=1. */
9677 constraint (!inst
.operands
[0].isreg
,
9678 _("'[' expected after PLD mnemonic"));
9679 constraint (inst
.operands
[0].postind
,
9680 _("post-indexed expression used in preload instruction"));
9681 constraint (inst
.operands
[0].writeback
,
9682 _("writeback used in preload instruction"));
9683 constraint (!inst
.operands
[0].preind
,
9684 _("unindexed addressing used in preload instruction"));
9685 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9688 /* ARMv7: PLI <addr_mode> */
9692 constraint (!inst
.operands
[0].isreg
,
9693 _("'[' expected after PLI mnemonic"));
9694 constraint (inst
.operands
[0].postind
,
9695 _("post-indexed expression used in preload instruction"));
9696 constraint (inst
.operands
[0].writeback
,
9697 _("writeback used in preload instruction"));
9698 constraint (!inst
.operands
[0].preind
,
9699 _("unindexed addressing used in preload instruction"));
9700 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9701 inst
.instruction
&= ~PRE_INDEX
;
9707 constraint (inst
.operands
[0].writeback
,
9708 _("push/pop do not support {reglist}^"));
9709 inst
.operands
[1] = inst
.operands
[0];
9710 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9711 inst
.operands
[0].isreg
= 1;
9712 inst
.operands
[0].writeback
= 1;
9713 inst
.operands
[0].reg
= REG_SP
;
9714 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9717 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9718 word at the specified address and the following word
9720 Unconditionally executed.
9721 Error if Rn is R15. */
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9727 if (inst
.operands
[0].writeback
)
9728 inst
.instruction
|= WRITE_BACK
;
9731 /* ARM V6 ssat (argument parse). */
9736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9737 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9738 inst
.instruction
|= inst
.operands
[2].reg
;
9740 if (inst
.operands
[3].present
)
9741 encode_arm_shift (3);
9744 /* ARM V6 usat (argument parse). */
9749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9750 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9751 inst
.instruction
|= inst
.operands
[2].reg
;
9753 if (inst
.operands
[3].present
)
9754 encode_arm_shift (3);
9757 /* ARM V6 ssat16 (argument parse). */
9762 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9763 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9764 inst
.instruction
|= inst
.operands
[2].reg
;
9770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9771 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9772 inst
.instruction
|= inst
.operands
[2].reg
;
9775 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9776 preserving the other bits.
9778 setend <endian_specifier>, where <endian_specifier> is either
9784 if (warn_on_deprecated
9785 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9786 as_tsktsk (_("setend use is deprecated for ARMv8"));
9788 if (inst
.operands
[0].imm
)
9789 inst
.instruction
|= 0x200;
9795 unsigned int Rm
= (inst
.operands
[1].present
9796 ? inst
.operands
[1].reg
9797 : inst
.operands
[0].reg
);
9799 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9800 inst
.instruction
|= Rm
;
9801 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9803 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9804 inst
.instruction
|= SHIFT_BY_REG
;
9805 /* PR 12854: Error on extraneous shifts. */
9806 constraint (inst
.operands
[2].shifted
,
9807 _("extraneous shift as part of operand to shift insn"));
9810 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
9816 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
9817 inst
.relocs
[0].pc_rel
= 0;
9823 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
9824 inst
.relocs
[0].pc_rel
= 0;
9830 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
9831 inst
.relocs
[0].pc_rel
= 0;
9837 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9838 _("selected processor does not support SETPAN instruction"));
9840 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9847 _("selected processor does not support SETPAN instruction"));
9849 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9852 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9853 SMLAxy{cond} Rd,Rm,Rs,Rn
9854 SMLAWy{cond} Rd,Rm,Rs,Rn
9855 Error if any register is R15. */
9860 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9861 inst
.instruction
|= inst
.operands
[1].reg
;
9862 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9863 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9866 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9867 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9868 Error if any register is R15.
9869 Warning if Rdlo == Rdhi. */
9874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9876 inst
.instruction
|= inst
.operands
[2].reg
;
9877 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9879 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9880 as_tsktsk (_("rdhi and rdlo must be different"));
9883 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9884 SMULxy{cond} Rd,Rm,Rs
9885 Error if any register is R15. */
9890 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9891 inst
.instruction
|= inst
.operands
[1].reg
;
9892 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9895 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9896 the same for both ARM and Thumb-2. */
9903 if (inst
.operands
[0].present
)
9905 reg
= inst
.operands
[0].reg
;
9906 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9911 inst
.instruction
|= reg
<< 16;
9912 inst
.instruction
|= inst
.operands
[1].imm
;
9913 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9914 inst
.instruction
|= WRITE_BACK
;
9917 /* ARM V6 strex (argument parse). */
9922 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9923 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9924 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9925 || inst
.operands
[2].negative
9926 /* See comment in do_ldrex(). */
9927 || (inst
.operands
[2].reg
== REG_PC
),
9930 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9931 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9933 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9934 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9935 _("offset must be zero in ARM encoding"));
9937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9938 inst
.instruction
|= inst
.operands
[1].reg
;
9939 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9940 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9946 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9947 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9948 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9949 || inst
.operands
[2].negative
,
9952 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9953 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9961 constraint (inst
.operands
[1].reg
% 2 != 0,
9962 _("even register required"));
9963 constraint (inst
.operands
[2].present
9964 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9965 _("can only store two consecutive registers"));
9966 /* If op 2 were present and equal to PC, this function wouldn't
9967 have been called in the first place. */
9968 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9970 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9971 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9972 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9976 inst
.instruction
|= inst
.operands
[1].reg
;
9977 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9984 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9985 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9993 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9994 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9999 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10000 extends it to 32-bits, and adds the result to a value in another
10001 register. You can specify a rotation by 0, 8, 16, or 24 bits
10002 before extracting the 16-bit value.
10003 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10004 Condition defaults to COND_ALWAYS.
10005 Error if any register uses R15. */
10010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10012 inst
.instruction
|= inst
.operands
[2].reg
;
10013 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10018 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10019 Condition defaults to COND_ALWAYS.
10020 Error if any register uses R15. */
10025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10026 inst
.instruction
|= inst
.operands
[1].reg
;
10027 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10030 /* VFP instructions. In a logical order: SP variant first, monad
10031 before dyad, arithmetic then move then load/store. */
10034 do_vfp_sp_monadic (void)
10036 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10037 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10041 do_vfp_sp_dyadic (void)
10043 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10044 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10045 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10049 do_vfp_sp_compare_z (void)
10051 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10055 do_vfp_dp_sp_cvt (void)
10057 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10058 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10062 do_vfp_sp_dp_cvt (void)
10064 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10065 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10069 do_vfp_reg_from_sp (void)
10071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10072 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10076 do_vfp_reg2_from_sp2 (void)
10078 constraint (inst
.operands
[2].imm
!= 2,
10079 _("only two consecutive VFP SP registers allowed here"));
10080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10082 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10086 do_vfp_sp_from_reg (void)
10088 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10089 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10093 do_vfp_sp2_from_reg2 (void)
10095 constraint (inst
.operands
[0].imm
!= 2,
10096 _("only two consecutive VFP SP registers allowed here"));
10097 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10099 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10103 do_vfp_sp_ldst (void)
10105 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10106 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10110 do_vfp_dp_ldst (void)
10112 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10113 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10118 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10120 if (inst
.operands
[0].writeback
)
10121 inst
.instruction
|= WRITE_BACK
;
10123 constraint (ldstm_type
!= VFP_LDSTMIA
,
10124 _("this addressing mode requires base-register writeback"));
10125 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10126 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10127 inst
.instruction
|= inst
.operands
[1].imm
;
10131 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10135 if (inst
.operands
[0].writeback
)
10136 inst
.instruction
|= WRITE_BACK
;
10138 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10139 _("this addressing mode requires base-register writeback"));
10141 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10142 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10144 count
= inst
.operands
[1].imm
<< 1;
10145 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10148 inst
.instruction
|= count
;
10152 do_vfp_sp_ldstmia (void)
10154 vfp_sp_ldstm (VFP_LDSTMIA
);
10158 do_vfp_sp_ldstmdb (void)
10160 vfp_sp_ldstm (VFP_LDSTMDB
);
10164 do_vfp_dp_ldstmia (void)
10166 vfp_dp_ldstm (VFP_LDSTMIA
);
10170 do_vfp_dp_ldstmdb (void)
10172 vfp_dp_ldstm (VFP_LDSTMDB
);
10176 do_vfp_xp_ldstmia (void)
10178 vfp_dp_ldstm (VFP_LDSTMIAX
);
10182 do_vfp_xp_ldstmdb (void)
10184 vfp_dp_ldstm (VFP_LDSTMDBX
);
10188 do_vfp_dp_rd_rm (void)
10190 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10191 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10195 do_vfp_dp_rn_rd (void)
10197 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10198 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10202 do_vfp_dp_rd_rn (void)
10204 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10205 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10209 do_vfp_dp_rd_rn_rm (void)
10211 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10212 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10213 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10217 do_vfp_dp_rd (void)
10219 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10223 do_vfp_dp_rm_rd_rn (void)
10225 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10226 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10227 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10230 /* VFPv3 instructions. */
10232 do_vfp_sp_const (void)
10234 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10235 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10236 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10240 do_vfp_dp_const (void)
10242 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10243 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10244 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10248 vfp_conv (int srcsize
)
10250 int immbits
= srcsize
- inst
.operands
[1].imm
;
10252 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10254 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10255 i.e. immbits must be in range 0 - 16. */
10256 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10259 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10261 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10262 i.e. immbits must be in range 0 - 31. */
10263 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10267 inst
.instruction
|= (immbits
& 1) << 5;
10268 inst
.instruction
|= (immbits
>> 1);
10272 do_vfp_sp_conv_16 (void)
10274 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10279 do_vfp_dp_conv_16 (void)
10281 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10286 do_vfp_sp_conv_32 (void)
10288 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10293 do_vfp_dp_conv_32 (void)
10295 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10299 /* FPA instructions. Also in a logical order. */
10304 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10305 inst
.instruction
|= inst
.operands
[1].reg
;
10309 do_fpa_ldmstm (void)
10311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10312 switch (inst
.operands
[1].imm
)
10314 case 1: inst
.instruction
|= CP_T_X
; break;
10315 case 2: inst
.instruction
|= CP_T_Y
; break;
10316 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10321 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10323 /* The instruction specified "ea" or "fd", so we can only accept
10324 [Rn]{!}. The instruction does not really support stacking or
10325 unstacking, so we have to emulate these by setting appropriate
10326 bits and offsets. */
10327 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10328 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10329 _("this instruction does not support indexing"));
10331 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10332 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10334 if (!(inst
.instruction
& INDEX_UP
))
10335 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10337 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10339 inst
.operands
[2].preind
= 0;
10340 inst
.operands
[2].postind
= 1;
10344 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10347 /* iWMMXt instructions: strictly in alphabetical order. */
10350 do_iwmmxt_tandorc (void)
10352 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10356 do_iwmmxt_textrc (void)
10358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10359 inst
.instruction
|= inst
.operands
[1].imm
;
10363 do_iwmmxt_textrm (void)
10365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10366 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10367 inst
.instruction
|= inst
.operands
[2].imm
;
10371 do_iwmmxt_tinsr (void)
10373 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10374 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10375 inst
.instruction
|= inst
.operands
[2].imm
;
10379 do_iwmmxt_tmia (void)
10381 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10382 inst
.instruction
|= inst
.operands
[1].reg
;
10383 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10387 do_iwmmxt_waligni (void)
10389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10390 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10391 inst
.instruction
|= inst
.operands
[2].reg
;
10392 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10396 do_iwmmxt_wmerge (void)
10398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10399 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10400 inst
.instruction
|= inst
.operands
[2].reg
;
10401 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10405 do_iwmmxt_wmov (void)
10407 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10409 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10410 inst
.instruction
|= inst
.operands
[1].reg
;
10414 do_iwmmxt_wldstbh (void)
10417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10419 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10421 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10422 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10426 do_iwmmxt_wldstw (void)
10428 /* RIWR_RIWC clears .isreg for a control register. */
10429 if (!inst
.operands
[0].isreg
)
10431 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10432 inst
.instruction
|= 0xf0000000;
10435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10436 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10440 do_iwmmxt_wldstd (void)
10442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10443 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10444 && inst
.operands
[1].immisreg
)
10446 inst
.instruction
&= ~0x1a000ff;
10447 inst
.instruction
|= (0xfU
<< 28);
10448 if (inst
.operands
[1].preind
)
10449 inst
.instruction
|= PRE_INDEX
;
10450 if (!inst
.operands
[1].negative
)
10451 inst
.instruction
|= INDEX_UP
;
10452 if (inst
.operands
[1].writeback
)
10453 inst
.instruction
|= WRITE_BACK
;
10454 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10455 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10456 inst
.instruction
|= inst
.operands
[1].imm
;
10459 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10463 do_iwmmxt_wshufh (void)
10465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10467 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10468 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10472 do_iwmmxt_wzero (void)
10474 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10475 inst
.instruction
|= inst
.operands
[0].reg
;
10476 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10477 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10481 do_iwmmxt_wrwrwr_or_imm5 (void)
10483 if (inst
.operands
[2].isreg
)
10486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10487 _("immediate operand requires iWMMXt2"));
10489 if (inst
.operands
[2].imm
== 0)
10491 switch ((inst
.instruction
>> 20) & 0xf)
10497 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10498 inst
.operands
[2].imm
= 16;
10499 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10505 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10506 inst
.operands
[2].imm
= 32;
10507 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10514 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10516 wrn
= (inst
.instruction
>> 16) & 0xf;
10517 inst
.instruction
&= 0xff0fff0f;
10518 inst
.instruction
|= wrn
;
10519 /* Bail out here; the instruction is now assembled. */
10524 /* Map 32 -> 0, etc. */
10525 inst
.operands
[2].imm
&= 0x1f;
10526 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10530 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10531 operations first, then control, shift, and load/store. */
10533 /* Insns like "foo X,Y,Z". */
10536 do_mav_triple (void)
10538 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10539 inst
.instruction
|= inst
.operands
[1].reg
;
10540 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10543 /* Insns like "foo W,X,Y,Z".
10544 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10549 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10550 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10551 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10552 inst
.instruction
|= inst
.operands
[3].reg
;
10555 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10557 do_mav_dspsc (void)
10559 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10562 /* Maverick shift immediate instructions.
10563 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10564 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10567 do_mav_shift (void)
10569 int imm
= inst
.operands
[2].imm
;
10571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10572 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10574 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10575 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10576 Bit 4 should be 0. */
10577 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10579 inst
.instruction
|= imm
;
10582 /* XScale instructions. Also sorted arithmetic before move. */
10584 /* Xscale multiply-accumulate (argument parse)
10587 MIAxycc acc0,Rm,Rs. */
10592 inst
.instruction
|= inst
.operands
[1].reg
;
10593 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10596 /* Xscale move-accumulator-register (argument parse)
10598 MARcc acc0,RdLo,RdHi. */
10603 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10604 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10607 /* Xscale move-register-accumulator (argument parse)
10609 MRAcc RdLo,RdHi,acc0. */
10614 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10616 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10619 /* Encoding functions relevant only to Thumb. */
10621 /* inst.operands[i] is a shifted-register operand; encode
10622 it into inst.instruction in the format used by Thumb32. */
10625 encode_thumb32_shifted_operand (int i
)
10627 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10628 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10630 constraint (inst
.operands
[i
].immisreg
,
10631 _("shift by register not allowed in thumb mode"));
10632 inst
.instruction
|= inst
.operands
[i
].reg
;
10633 if (shift
== SHIFT_RRX
)
10634 inst
.instruction
|= SHIFT_ROR
<< 4;
10637 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10638 _("expression too complex"));
10640 constraint (value
> 32
10641 || (value
== 32 && (shift
== SHIFT_LSL
10642 || shift
== SHIFT_ROR
)),
10643 _("shift expression is too large"));
10647 else if (value
== 32)
10650 inst
.instruction
|= shift
<< 4;
10651 inst
.instruction
|= (value
& 0x1c) << 10;
10652 inst
.instruction
|= (value
& 0x03) << 6;
10657 /* inst.operands[i] was set up by parse_address. Encode it into a
10658 Thumb32 format load or store instruction. Reject forms that cannot
10659 be used with such instructions. If is_t is true, reject forms that
10660 cannot be used with a T instruction; if is_d is true, reject forms
10661 that cannot be used with a D instruction. If it is a store insn,
10662 reject PC in Rn. */
10665 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10667 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10669 constraint (!inst
.operands
[i
].isreg
,
10670 _("Instruction does not support =N addresses"));
10672 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10673 if (inst
.operands
[i
].immisreg
)
10675 constraint (is_pc
, BAD_PC_ADDRESSING
);
10676 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10677 constraint (inst
.operands
[i
].negative
,
10678 _("Thumb does not support negative register indexing"));
10679 constraint (inst
.operands
[i
].postind
,
10680 _("Thumb does not support register post-indexing"));
10681 constraint (inst
.operands
[i
].writeback
,
10682 _("Thumb does not support register indexing with writeback"));
10683 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10684 _("Thumb supports only LSL in shifted register indexing"));
10686 inst
.instruction
|= inst
.operands
[i
].imm
;
10687 if (inst
.operands
[i
].shifted
)
10689 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10690 _("expression too complex"));
10691 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10692 || inst
.relocs
[0].exp
.X_add_number
> 3,
10693 _("shift out of range"));
10694 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10696 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10698 else if (inst
.operands
[i
].preind
)
10700 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10701 constraint (is_t
&& inst
.operands
[i
].writeback
,
10702 _("cannot use writeback with this instruction"));
10703 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10704 BAD_PC_ADDRESSING
);
10708 inst
.instruction
|= 0x01000000;
10709 if (inst
.operands
[i
].writeback
)
10710 inst
.instruction
|= 0x00200000;
10714 inst
.instruction
|= 0x00000c00;
10715 if (inst
.operands
[i
].writeback
)
10716 inst
.instruction
|= 0x00000100;
10718 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10720 else if (inst
.operands
[i
].postind
)
10722 gas_assert (inst
.operands
[i
].writeback
);
10723 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10724 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10727 inst
.instruction
|= 0x00200000;
10729 inst
.instruction
|= 0x00000900;
10730 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10732 else /* unindexed - only for coprocessor */
10733 inst
.error
= _("instruction does not accept unindexed addressing");
10736 /* Table of Thumb instructions which exist in both 16- and 32-bit
10737 encodings (the latter only in post-V6T2 cores). The index is the
10738 value used in the insns table below. When there is more than one
10739 possible 16-bit encoding for the instruction, this table always
10741 Also contains several pseudo-instructions used during relaxation. */
10742 #define T16_32_TAB \
10743 X(_adc, 4140, eb400000), \
10744 X(_adcs, 4140, eb500000), \
10745 X(_add, 1c00, eb000000), \
10746 X(_adds, 1c00, eb100000), \
10747 X(_addi, 0000, f1000000), \
10748 X(_addis, 0000, f1100000), \
10749 X(_add_pc,000f, f20f0000), \
10750 X(_add_sp,000d, f10d0000), \
10751 X(_adr, 000f, f20f0000), \
10752 X(_and, 4000, ea000000), \
10753 X(_ands, 4000, ea100000), \
10754 X(_asr, 1000, fa40f000), \
10755 X(_asrs, 1000, fa50f000), \
10756 X(_b, e000, f000b000), \
10757 X(_bcond, d000, f0008000), \
10758 X(_bf, 0000, f040e001), \
10759 X(_bfcsel,0000, f000e001), \
10760 X(_bfx, 0000, f060e001), \
10761 X(_bfl, 0000, f000c001), \
10762 X(_bflx, 0000, f070e001), \
10763 X(_bic, 4380, ea200000), \
10764 X(_bics, 4380, ea300000), \
10765 X(_cmn, 42c0, eb100f00), \
10766 X(_cmp, 2800, ebb00f00), \
10767 X(_cpsie, b660, f3af8400), \
10768 X(_cpsid, b670, f3af8600), \
10769 X(_cpy, 4600, ea4f0000), \
10770 X(_dec_sp,80dd, f1ad0d00), \
10771 X(_dls, 0000, f040e001), \
10772 X(_eor, 4040, ea800000), \
10773 X(_eors, 4040, ea900000), \
10774 X(_inc_sp,00dd, f10d0d00), \
10775 X(_ldmia, c800, e8900000), \
10776 X(_ldr, 6800, f8500000), \
10777 X(_ldrb, 7800, f8100000), \
10778 X(_ldrh, 8800, f8300000), \
10779 X(_ldrsb, 5600, f9100000), \
10780 X(_ldrsh, 5e00, f9300000), \
10781 X(_ldr_pc,4800, f85f0000), \
10782 X(_ldr_pc2,4800, f85f0000), \
10783 X(_ldr_sp,9800, f85d0000), \
10784 X(_le, 0000, f00fc001), \
10785 X(_lsl, 0000, fa00f000), \
10786 X(_lsls, 0000, fa10f000), \
10787 X(_lsr, 0800, fa20f000), \
10788 X(_lsrs, 0800, fa30f000), \
10789 X(_mov, 2000, ea4f0000), \
10790 X(_movs, 2000, ea5f0000), \
10791 X(_mul, 4340, fb00f000), \
10792 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10793 X(_mvn, 43c0, ea6f0000), \
10794 X(_mvns, 43c0, ea7f0000), \
10795 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10796 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10797 X(_orr, 4300, ea400000), \
10798 X(_orrs, 4300, ea500000), \
10799 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10800 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10801 X(_rev, ba00, fa90f080), \
10802 X(_rev16, ba40, fa90f090), \
10803 X(_revsh, bac0, fa90f0b0), \
10804 X(_ror, 41c0, fa60f000), \
10805 X(_rors, 41c0, fa70f000), \
10806 X(_sbc, 4180, eb600000), \
10807 X(_sbcs, 4180, eb700000), \
10808 X(_stmia, c000, e8800000), \
10809 X(_str, 6000, f8400000), \
10810 X(_strb, 7000, f8000000), \
10811 X(_strh, 8000, f8200000), \
10812 X(_str_sp,9000, f84d0000), \
10813 X(_sub, 1e00, eba00000), \
10814 X(_subs, 1e00, ebb00000), \
10815 X(_subi, 8000, f1a00000), \
10816 X(_subis, 8000, f1b00000), \
10817 X(_sxtb, b240, fa4ff080), \
10818 X(_sxth, b200, fa0ff080), \
10819 X(_tst, 4200, ea100f00), \
10820 X(_uxtb, b2c0, fa5ff080), \
10821 X(_uxth, b280, fa1ff080), \
10822 X(_nop, bf00, f3af8000), \
10823 X(_yield, bf10, f3af8001), \
10824 X(_wfe, bf20, f3af8002), \
10825 X(_wfi, bf30, f3af8003), \
10826 X(_wls, 0000, f040c001), \
10827 X(_sev, bf40, f3af8004), \
10828 X(_sevl, bf50, f3af8005), \
10829 X(_udf, de00, f7f0a000)
10831 /* To catch errors in encoding functions, the codes are all offset by
10832 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10833 as 16-bit instructions. */
10834 #define X(a,b,c) T_MNEM##a
10835 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10838 #define X(a,b,c) 0x##b
10839 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10840 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10843 #define X(a,b,c) 0x##c
10844 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10845 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10846 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10850 /* Thumb instruction encoders, in alphabetical order. */
10852 /* ADDW or SUBW. */
10855 do_t_add_sub_w (void)
10859 Rd
= inst
.operands
[0].reg
;
10860 Rn
= inst
.operands
[1].reg
;
10862 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10863 is the SP-{plus,minus}-immediate form of the instruction. */
10865 constraint (Rd
== REG_PC
, BAD_PC
);
10867 reject_bad_reg (Rd
);
10869 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10870 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10873 /* Parse an add or subtract instruction. We get here with inst.instruction
10874 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10877 do_t_add_sub (void)
10881 Rd
= inst
.operands
[0].reg
;
10882 Rs
= (inst
.operands
[1].present
10883 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10884 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10887 set_pred_insn_type_last ();
10889 if (unified_syntax
)
10892 bfd_boolean narrow
;
10895 flags
= (inst
.instruction
== T_MNEM_adds
10896 || inst
.instruction
== T_MNEM_subs
);
10898 narrow
= !in_pred_block ();
10900 narrow
= in_pred_block ();
10901 if (!inst
.operands
[2].isreg
)
10905 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10906 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10908 add
= (inst
.instruction
== T_MNEM_add
10909 || inst
.instruction
== T_MNEM_adds
);
10911 if (inst
.size_req
!= 4)
10913 /* Attempt to use a narrow opcode, with relaxation if
10915 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10916 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10917 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10918 opcode
= T_MNEM_add_sp
;
10919 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10920 opcode
= T_MNEM_add_pc
;
10921 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10924 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10926 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10930 inst
.instruction
= THUMB_OP16(opcode
);
10931 inst
.instruction
|= (Rd
<< 4) | Rs
;
10932 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10933 || (inst
.relocs
[0].type
10934 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
10936 if (inst
.size_req
== 2)
10937 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
10939 inst
.relax
= opcode
;
10943 constraint (inst
.size_req
== 2, BAD_HIREG
);
10945 if (inst
.size_req
== 4
10946 || (inst
.size_req
!= 2 && !opcode
))
10948 constraint ((inst
.relocs
[0].type
10949 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
10950 && (inst
.relocs
[0].type
10951 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
10952 THUMB1_RELOC_ONLY
);
10955 constraint (add
, BAD_PC
);
10956 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10957 _("only SUBS PC, LR, #const allowed"));
10958 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10959 _("expression too complex"));
10960 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
10961 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
10962 _("immediate value out of range"));
10963 inst
.instruction
= T2_SUBS_PC_LR
10964 | inst
.relocs
[0].exp
.X_add_number
;
10965 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10968 else if (Rs
== REG_PC
)
10970 /* Always use addw/subw. */
10971 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10972 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
10976 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10977 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10980 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10982 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10984 inst
.instruction
|= Rd
<< 8;
10985 inst
.instruction
|= Rs
<< 16;
10990 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10991 unsigned int shift
= inst
.operands
[2].shift_kind
;
10993 Rn
= inst
.operands
[2].reg
;
10994 /* See if we can do this with a 16-bit instruction. */
10995 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10997 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11002 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11003 || inst
.instruction
== T_MNEM_add
)
11005 : T_OPCODE_SUB_R3
);
11006 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11010 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11012 /* Thumb-1 cores (except v6-M) require at least one high
11013 register in a narrow non flag setting add. */
11014 if (Rd
> 7 || Rn
> 7
11015 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11016 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11023 inst
.instruction
= T_OPCODE_ADD_HI
;
11024 inst
.instruction
|= (Rd
& 8) << 4;
11025 inst
.instruction
|= (Rd
& 7);
11026 inst
.instruction
|= Rn
<< 3;
11032 constraint (Rd
== REG_PC
, BAD_PC
);
11033 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11034 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11035 constraint (Rs
== REG_PC
, BAD_PC
);
11036 reject_bad_reg (Rn
);
11038 /* If we get here, it can't be done in 16 bits. */
11039 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11040 _("shift must be constant"));
11041 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11042 inst
.instruction
|= Rd
<< 8;
11043 inst
.instruction
|= Rs
<< 16;
11044 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11045 _("shift value over 3 not allowed in thumb mode"));
11046 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11047 _("only LSL shift allowed in thumb mode"));
11048 encode_thumb32_shifted_operand (2);
11053 constraint (inst
.instruction
== T_MNEM_adds
11054 || inst
.instruction
== T_MNEM_subs
,
11057 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11059 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11060 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11063 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11064 ? 0x0000 : 0x8000);
11065 inst
.instruction
|= (Rd
<< 4) | Rs
;
11066 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11070 Rn
= inst
.operands
[2].reg
;
11071 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11073 /* We now have Rd, Rs, and Rn set to registers. */
11074 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11076 /* Can't do this for SUB. */
11077 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11078 inst
.instruction
= T_OPCODE_ADD_HI
;
11079 inst
.instruction
|= (Rd
& 8) << 4;
11080 inst
.instruction
|= (Rd
& 7);
11082 inst
.instruction
|= Rn
<< 3;
11084 inst
.instruction
|= Rs
<< 3;
11086 constraint (1, _("dest must overlap one source register"));
11090 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11091 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11092 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11102 Rd
= inst
.operands
[0].reg
;
11103 reject_bad_reg (Rd
);
11105 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11107 /* Defer to section relaxation. */
11108 inst
.relax
= inst
.instruction
;
11109 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11110 inst
.instruction
|= Rd
<< 4;
11112 else if (unified_syntax
&& inst
.size_req
!= 2)
11114 /* Generate a 32-bit opcode. */
11115 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11116 inst
.instruction
|= Rd
<< 8;
11117 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11118 inst
.relocs
[0].pc_rel
= 1;
11122 /* Generate a 16-bit opcode. */
11123 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11124 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11125 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11126 inst
.relocs
[0].pc_rel
= 1;
11127 inst
.instruction
|= Rd
<< 4;
11130 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11131 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11132 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11133 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11134 inst
.relocs
[0].exp
.X_add_number
+= 1;
11137 /* Arithmetic instructions for which there is just one 16-bit
11138 instruction encoding, and it allows only two low registers.
11139 For maximal compatibility with ARM syntax, we allow three register
11140 operands even when Thumb-32 instructions are not available, as long
11141 as the first two are identical. For instance, both "sbc r0,r1" and
11142 "sbc r0,r0,r1" are allowed. */
11148 Rd
= inst
.operands
[0].reg
;
11149 Rs
= (inst
.operands
[1].present
11150 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11151 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11152 Rn
= inst
.operands
[2].reg
;
11154 reject_bad_reg (Rd
);
11155 reject_bad_reg (Rs
);
11156 if (inst
.operands
[2].isreg
)
11157 reject_bad_reg (Rn
);
11159 if (unified_syntax
)
11161 if (!inst
.operands
[2].isreg
)
11163 /* For an immediate, we always generate a 32-bit opcode;
11164 section relaxation will shrink it later if possible. */
11165 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11166 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11167 inst
.instruction
|= Rd
<< 8;
11168 inst
.instruction
|= Rs
<< 16;
11169 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11173 bfd_boolean narrow
;
11175 /* See if we can do this with a 16-bit instruction. */
11176 if (THUMB_SETS_FLAGS (inst
.instruction
))
11177 narrow
= !in_pred_block ();
11179 narrow
= in_pred_block ();
11181 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11183 if (inst
.operands
[2].shifted
)
11185 if (inst
.size_req
== 4)
11191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11192 inst
.instruction
|= Rd
;
11193 inst
.instruction
|= Rn
<< 3;
11197 /* If we get here, it can't be done in 16 bits. */
11198 constraint (inst
.operands
[2].shifted
11199 && inst
.operands
[2].immisreg
,
11200 _("shift must be constant"));
11201 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11202 inst
.instruction
|= Rd
<< 8;
11203 inst
.instruction
|= Rs
<< 16;
11204 encode_thumb32_shifted_operand (2);
11209 /* On its face this is a lie - the instruction does set the
11210 flags. However, the only supported mnemonic in this mode
11211 says it doesn't. */
11212 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11214 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11215 _("unshifted register required"));
11216 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11217 constraint (Rd
!= Rs
,
11218 _("dest and source1 must be the same register"));
11220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11221 inst
.instruction
|= Rd
;
11222 inst
.instruction
|= Rn
<< 3;
11226 /* Similarly, but for instructions where the arithmetic operation is
11227 commutative, so we can allow either of them to be different from
11228 the destination operand in a 16-bit instruction. For instance, all
11229 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11236 Rd
= inst
.operands
[0].reg
;
11237 Rs
= (inst
.operands
[1].present
11238 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11239 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11240 Rn
= inst
.operands
[2].reg
;
11242 reject_bad_reg (Rd
);
11243 reject_bad_reg (Rs
);
11244 if (inst
.operands
[2].isreg
)
11245 reject_bad_reg (Rn
);
11247 if (unified_syntax
)
11249 if (!inst
.operands
[2].isreg
)
11251 /* For an immediate, we always generate a 32-bit opcode;
11252 section relaxation will shrink it later if possible. */
11253 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11254 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11255 inst
.instruction
|= Rd
<< 8;
11256 inst
.instruction
|= Rs
<< 16;
11257 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11261 bfd_boolean narrow
;
11263 /* See if we can do this with a 16-bit instruction. */
11264 if (THUMB_SETS_FLAGS (inst
.instruction
))
11265 narrow
= !in_pred_block ();
11267 narrow
= in_pred_block ();
11269 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11271 if (inst
.operands
[2].shifted
)
11273 if (inst
.size_req
== 4)
11280 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11281 inst
.instruction
|= Rd
;
11282 inst
.instruction
|= Rn
<< 3;
11287 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11288 inst
.instruction
|= Rd
;
11289 inst
.instruction
|= Rs
<< 3;
11294 /* If we get here, it can't be done in 16 bits. */
11295 constraint (inst
.operands
[2].shifted
11296 && inst
.operands
[2].immisreg
,
11297 _("shift must be constant"));
11298 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11299 inst
.instruction
|= Rd
<< 8;
11300 inst
.instruction
|= Rs
<< 16;
11301 encode_thumb32_shifted_operand (2);
11306 /* On its face this is a lie - the instruction does set the
11307 flags. However, the only supported mnemonic in this mode
11308 says it doesn't. */
11309 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11311 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11312 _("unshifted register required"));
11313 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11315 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11316 inst
.instruction
|= Rd
;
11319 inst
.instruction
|= Rn
<< 3;
11321 inst
.instruction
|= Rs
<< 3;
11323 constraint (1, _("dest must overlap one source register"));
11331 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11332 constraint (msb
> 32, _("bit-field extends past end of register"));
11333 /* The instruction encoding stores the LSB and MSB,
11334 not the LSB and width. */
11335 Rd
= inst
.operands
[0].reg
;
11336 reject_bad_reg (Rd
);
11337 inst
.instruction
|= Rd
<< 8;
11338 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11339 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11340 inst
.instruction
|= msb
- 1;
11349 Rd
= inst
.operands
[0].reg
;
11350 reject_bad_reg (Rd
);
11352 /* #0 in second position is alternative syntax for bfc, which is
11353 the same instruction but with REG_PC in the Rm field. */
11354 if (!inst
.operands
[1].isreg
)
11358 Rn
= inst
.operands
[1].reg
;
11359 reject_bad_reg (Rn
);
11362 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11363 constraint (msb
> 32, _("bit-field extends past end of register"));
11364 /* The instruction encoding stores the LSB and MSB,
11365 not the LSB and width. */
11366 inst
.instruction
|= Rd
<< 8;
11367 inst
.instruction
|= Rn
<< 16;
11368 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11369 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11370 inst
.instruction
|= msb
- 1;
11378 Rd
= inst
.operands
[0].reg
;
11379 Rn
= inst
.operands
[1].reg
;
11381 reject_bad_reg (Rd
);
11382 reject_bad_reg (Rn
);
11384 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11385 _("bit-field extends past end of register"));
11386 inst
.instruction
|= Rd
<< 8;
11387 inst
.instruction
|= Rn
<< 16;
11388 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11389 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11390 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11393 /* ARM V5 Thumb BLX (argument parse)
11394 BLX <target_addr> which is BLX(1)
11395 BLX <Rm> which is BLX(2)
11396 Unfortunately, there are two different opcodes for this mnemonic.
11397 So, the insns[].value is not used, and the code here zaps values
11398 into inst.instruction.
11400 ??? How to take advantage of the additional two bits of displacement
11401 available in Thumb32 mode? Need new relocation? */
11406 set_pred_insn_type_last ();
11408 if (inst
.operands
[0].isreg
)
11410 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11411 /* We have a register, so this is BLX(2). */
11412 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11416 /* No register. This must be BLX(1). */
11417 inst
.instruction
= 0xf000e800;
11418 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11427 bfd_reloc_code_real_type reloc
;
11430 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11432 if (in_pred_block ())
11434 /* Conditional branches inside IT blocks are encoded as unconditional
11436 cond
= COND_ALWAYS
;
11441 if (cond
!= COND_ALWAYS
)
11442 opcode
= T_MNEM_bcond
;
11444 opcode
= inst
.instruction
;
11447 && (inst
.size_req
== 4
11448 || (inst
.size_req
!= 2
11449 && (inst
.operands
[0].hasreloc
11450 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11452 inst
.instruction
= THUMB_OP32(opcode
);
11453 if (cond
== COND_ALWAYS
)
11454 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11457 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11458 _("selected architecture does not support "
11459 "wide conditional branch instruction"));
11461 gas_assert (cond
!= 0xF);
11462 inst
.instruction
|= cond
<< 22;
11463 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11468 inst
.instruction
= THUMB_OP16(opcode
);
11469 if (cond
== COND_ALWAYS
)
11470 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11473 inst
.instruction
|= cond
<< 8;
11474 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11476 /* Allow section relaxation. */
11477 if (unified_syntax
&& inst
.size_req
!= 2)
11478 inst
.relax
= opcode
;
11480 inst
.relocs
[0].type
= reloc
;
11481 inst
.relocs
[0].pc_rel
= 1;
11484 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11485 between the two is the maximum immediate allowed - which is passed in
11488 do_t_bkpt_hlt1 (int range
)
11490 constraint (inst
.cond
!= COND_ALWAYS
,
11491 _("instruction is always unconditional"));
11492 if (inst
.operands
[0].present
)
11494 constraint (inst
.operands
[0].imm
> range
,
11495 _("immediate value out of range"));
11496 inst
.instruction
|= inst
.operands
[0].imm
;
11499 set_pred_insn_type (NEUTRAL_IT_INSN
);
11505 do_t_bkpt_hlt1 (63);
11511 do_t_bkpt_hlt1 (255);
11515 do_t_branch23 (void)
11517 set_pred_insn_type_last ();
11518 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11520 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11521 this file. We used to simply ignore the PLT reloc type here --
11522 the branch encoding is now needed to deal with TLSCALL relocs.
11523 So if we see a PLT reloc now, put it back to how it used to be to
11524 keep the preexisting behaviour. */
11525 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11526 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11528 #if defined(OBJ_COFF)
11529 /* If the destination of the branch is a defined symbol which does not have
11530 the THUMB_FUNC attribute, then we must be calling a function which has
11531 the (interfacearm) attribute. We look for the Thumb entry point to that
11532 function and change the branch to refer to that function instead. */
11533 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11534 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11535 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11536 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11537 inst
.relocs
[0].exp
.X_add_symbol
11538 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11545 set_pred_insn_type_last ();
11546 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11547 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11548 should cause the alignment to be checked once it is known. This is
11549 because BX PC only works if the instruction is word aligned. */
11557 set_pred_insn_type_last ();
11558 Rm
= inst
.operands
[0].reg
;
11559 reject_bad_reg (Rm
);
11560 inst
.instruction
|= Rm
<< 16;
11569 Rd
= inst
.operands
[0].reg
;
11570 Rm
= inst
.operands
[1].reg
;
11572 reject_bad_reg (Rd
);
11573 reject_bad_reg (Rm
);
11575 inst
.instruction
|= Rd
<< 8;
11576 inst
.instruction
|= Rm
<< 16;
11577 inst
.instruction
|= Rm
;
11583 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11589 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11590 inst
.instruction
|= inst
.operands
[0].imm
;
11596 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11598 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11599 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11601 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11602 inst
.instruction
= 0xf3af8000;
11603 inst
.instruction
|= imod
<< 9;
11604 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11605 if (inst
.operands
[1].present
)
11606 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11610 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11611 && (inst
.operands
[0].imm
& 4),
11612 _("selected processor does not support 'A' form "
11613 "of this instruction"));
11614 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11615 _("Thumb does not support the 2-argument "
11616 "form of this instruction"));
11617 inst
.instruction
|= inst
.operands
[0].imm
;
11621 /* THUMB CPY instruction (argument parse). */
11626 if (inst
.size_req
== 4)
11628 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11629 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11630 inst
.instruction
|= inst
.operands
[1].reg
;
11634 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11635 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11636 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11643 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11644 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11645 inst
.instruction
|= inst
.operands
[0].reg
;
11646 inst
.relocs
[0].pc_rel
= 1;
11647 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11653 inst
.instruction
|= inst
.operands
[0].imm
;
11659 unsigned Rd
, Rn
, Rm
;
11661 Rd
= inst
.operands
[0].reg
;
11662 Rn
= (inst
.operands
[1].present
11663 ? inst
.operands
[1].reg
: Rd
);
11664 Rm
= inst
.operands
[2].reg
;
11666 reject_bad_reg (Rd
);
11667 reject_bad_reg (Rn
);
11668 reject_bad_reg (Rm
);
11670 inst
.instruction
|= Rd
<< 8;
11671 inst
.instruction
|= Rn
<< 16;
11672 inst
.instruction
|= Rm
;
11678 if (unified_syntax
&& inst
.size_req
== 4)
11679 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11681 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11687 unsigned int cond
= inst
.operands
[0].imm
;
11689 set_pred_insn_type (IT_INSN
);
11690 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
11691 now_pred
.cc
= cond
;
11692 now_pred
.warn_deprecated
= FALSE
;
11693 now_pred
.type
= SCALAR_PRED
;
11695 /* If the condition is a negative condition, invert the mask. */
11696 if ((cond
& 0x1) == 0x0)
11698 unsigned int mask
= inst
.instruction
& 0x000f;
11700 if ((mask
& 0x7) == 0)
11702 /* No conversion needed. */
11703 now_pred
.block_length
= 1;
11705 else if ((mask
& 0x3) == 0)
11708 now_pred
.block_length
= 2;
11710 else if ((mask
& 0x1) == 0)
11713 now_pred
.block_length
= 3;
11718 now_pred
.block_length
= 4;
11721 inst
.instruction
&= 0xfff0;
11722 inst
.instruction
|= mask
;
11725 inst
.instruction
|= cond
<< 4;
11731 /* We are dealing with a vector predicated block. */
11732 set_pred_insn_type (VPT_INSN
);
11734 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
11735 | ((inst
.instruction
& 0xe000) >> 13);
11736 now_pred
.warn_deprecated
= FALSE
;
11737 now_pred
.type
= VECTOR_PRED
;
11740 /* Helper function used for both push/pop and ldm/stm. */
11742 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
11743 bfd_boolean writeback
)
11745 bfd_boolean load
, store
;
11747 gas_assert (base
!= -1 || !do_io
);
11748 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
11749 store
= do_io
&& !load
;
11751 if (mask
& (1 << 13))
11752 inst
.error
= _("SP not allowed in register list");
11754 if (do_io
&& (mask
& (1 << base
)) != 0
11756 inst
.error
= _("having the base register in the register list when "
11757 "using write back is UNPREDICTABLE");
11761 if (mask
& (1 << 15))
11763 if (mask
& (1 << 14))
11764 inst
.error
= _("LR and PC should not both be in register list");
11766 set_pred_insn_type_last ();
11771 if (mask
& (1 << 15))
11772 inst
.error
= _("PC not allowed in register list");
11775 if (do_io
&& ((mask
& (mask
- 1)) == 0))
11777 /* Single register transfers implemented as str/ldr. */
11780 if (inst
.instruction
& (1 << 23))
11781 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11783 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11787 if (inst
.instruction
& (1 << 23))
11788 inst
.instruction
= 0x00800000; /* ia -> [base] */
11790 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11793 inst
.instruction
|= 0xf8400000;
11795 inst
.instruction
|= 0x00100000;
11797 mask
= ffs (mask
) - 1;
11800 else if (writeback
)
11801 inst
.instruction
|= WRITE_BACK
;
11803 inst
.instruction
|= mask
;
11805 inst
.instruction
|= base
<< 16;
11811 /* This really doesn't seem worth it. */
11812 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
11813 _("expression too complex"));
11814 constraint (inst
.operands
[1].writeback
,
11815 _("Thumb load/store multiple does not support {reglist}^"));
11817 if (unified_syntax
)
11819 bfd_boolean narrow
;
11823 /* See if we can use a 16-bit instruction. */
11824 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11825 && inst
.size_req
!= 4
11826 && !(inst
.operands
[1].imm
& ~0xff))
11828 mask
= 1 << inst
.operands
[0].reg
;
11830 if (inst
.operands
[0].reg
<= 7)
11832 if (inst
.instruction
== T_MNEM_stmia
11833 ? inst
.operands
[0].writeback
11834 : (inst
.operands
[0].writeback
11835 == !(inst
.operands
[1].imm
& mask
)))
11837 if (inst
.instruction
== T_MNEM_stmia
11838 && (inst
.operands
[1].imm
& mask
)
11839 && (inst
.operands
[1].imm
& (mask
- 1)))
11840 as_warn (_("value stored for r%d is UNKNOWN"),
11841 inst
.operands
[0].reg
);
11843 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11845 inst
.instruction
|= inst
.operands
[1].imm
;
11848 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11850 /* This means 1 register in reg list one of 3 situations:
11851 1. Instruction is stmia, but without writeback.
11852 2. lmdia without writeback, but with Rn not in
11854 3. ldmia with writeback, but with Rn in reglist.
11855 Case 3 is UNPREDICTABLE behaviour, so we handle
11856 case 1 and 2 which can be converted into a 16-bit
11857 str or ldr. The SP cases are handled below. */
11858 unsigned long opcode
;
11859 /* First, record an error for Case 3. */
11860 if (inst
.operands
[1].imm
& mask
11861 && inst
.operands
[0].writeback
)
11863 _("having the base register in the register list when "
11864 "using write back is UNPREDICTABLE");
11866 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11868 inst
.instruction
= THUMB_OP16 (opcode
);
11869 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11870 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11874 else if (inst
.operands
[0] .reg
== REG_SP
)
11876 if (inst
.operands
[0].writeback
)
11879 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11880 ? T_MNEM_push
: T_MNEM_pop
);
11881 inst
.instruction
|= inst
.operands
[1].imm
;
11884 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11887 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11888 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11889 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11897 if (inst
.instruction
< 0xffff)
11898 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11900 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
11901 inst
.operands
[1].imm
,
11902 inst
.operands
[0].writeback
);
11907 constraint (inst
.operands
[0].reg
> 7
11908 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11909 constraint (inst
.instruction
!= T_MNEM_ldmia
11910 && inst
.instruction
!= T_MNEM_stmia
,
11911 _("Thumb-2 instruction only valid in unified syntax"));
11912 if (inst
.instruction
== T_MNEM_stmia
)
11914 if (!inst
.operands
[0].writeback
)
11915 as_warn (_("this instruction will write back the base register"));
11916 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11917 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11918 as_warn (_("value stored for r%d is UNKNOWN"),
11919 inst
.operands
[0].reg
);
11923 if (!inst
.operands
[0].writeback
11924 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11925 as_warn (_("this instruction will write back the base register"));
11926 else if (inst
.operands
[0].writeback
11927 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11928 as_warn (_("this instruction will not write back the base register"));
11931 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11932 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11933 inst
.instruction
|= inst
.operands
[1].imm
;
11940 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11941 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11942 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11943 || inst
.operands
[1].negative
,
11946 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11950 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11956 if (!inst
.operands
[1].present
)
11958 constraint (inst
.operands
[0].reg
== REG_LR
,
11959 _("r14 not allowed as first register "
11960 "when second register is omitted"));
11961 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11963 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11967 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11968 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11974 unsigned long opcode
;
11977 if (inst
.operands
[0].isreg
11978 && !inst
.operands
[0].preind
11979 && inst
.operands
[0].reg
== REG_PC
)
11980 set_pred_insn_type_last ();
11982 opcode
= inst
.instruction
;
11983 if (unified_syntax
)
11985 if (!inst
.operands
[1].isreg
)
11987 if (opcode
<= 0xffff)
11988 inst
.instruction
= THUMB_OP32 (opcode
);
11989 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11992 if (inst
.operands
[1].isreg
11993 && !inst
.operands
[1].writeback
11994 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11995 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11996 && opcode
<= 0xffff
11997 && inst
.size_req
!= 4)
11999 /* Insn may have a 16-bit form. */
12000 Rn
= inst
.operands
[1].reg
;
12001 if (inst
.operands
[1].immisreg
)
12003 inst
.instruction
= THUMB_OP16 (opcode
);
12005 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12007 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12008 reject_bad_reg (inst
.operands
[1].imm
);
12010 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12011 && opcode
!= T_MNEM_ldrsb
)
12012 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12013 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12020 if (inst
.relocs
[0].pc_rel
)
12021 opcode
= T_MNEM_ldr_pc2
;
12023 opcode
= T_MNEM_ldr_pc
;
12027 if (opcode
== T_MNEM_ldr
)
12028 opcode
= T_MNEM_ldr_sp
;
12030 opcode
= T_MNEM_str_sp
;
12032 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12036 inst
.instruction
= inst
.operands
[0].reg
;
12037 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12039 inst
.instruction
|= THUMB_OP16 (opcode
);
12040 if (inst
.size_req
== 2)
12041 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12043 inst
.relax
= opcode
;
12047 /* Definitely a 32-bit variant. */
12049 /* Warning for Erratum 752419. */
12050 if (opcode
== T_MNEM_ldr
12051 && inst
.operands
[0].reg
== REG_SP
12052 && inst
.operands
[1].writeback
== 1
12053 && !inst
.operands
[1].immisreg
)
12055 if (no_cpu_selected ()
12056 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12057 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12058 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12059 as_warn (_("This instruction may be unpredictable "
12060 "if executed on M-profile cores "
12061 "with interrupts enabled."));
12064 /* Do some validations regarding addressing modes. */
12065 if (inst
.operands
[1].immisreg
)
12066 reject_bad_reg (inst
.operands
[1].imm
);
12068 constraint (inst
.operands
[1].writeback
== 1
12069 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12072 inst
.instruction
= THUMB_OP32 (opcode
);
12073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12074 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12075 check_ldr_r15_aligned ();
12079 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12081 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12083 /* Only [Rn,Rm] is acceptable. */
12084 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12085 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12086 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12087 || inst
.operands
[1].negative
,
12088 _("Thumb does not support this addressing mode"));
12089 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12094 if (!inst
.operands
[1].isreg
)
12095 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12098 constraint (!inst
.operands
[1].preind
12099 || inst
.operands
[1].shifted
12100 || inst
.operands
[1].writeback
,
12101 _("Thumb does not support this addressing mode"));
12102 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12104 constraint (inst
.instruction
& 0x0600,
12105 _("byte or halfword not valid for base register"));
12106 constraint (inst
.operands
[1].reg
== REG_PC
12107 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12108 _("r15 based store not allowed"));
12109 constraint (inst
.operands
[1].immisreg
,
12110 _("invalid base register for register offset"));
12112 if (inst
.operands
[1].reg
== REG_PC
)
12113 inst
.instruction
= T_OPCODE_LDR_PC
;
12114 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12115 inst
.instruction
= T_OPCODE_LDR_SP
;
12117 inst
.instruction
= T_OPCODE_STR_SP
;
12119 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12120 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12124 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12125 if (!inst
.operands
[1].immisreg
)
12127 /* Immediate offset. */
12128 inst
.instruction
|= inst
.operands
[0].reg
;
12129 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12130 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12134 /* Register offset. */
12135 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12136 constraint (inst
.operands
[1].negative
,
12137 _("Thumb does not support this addressing mode"));
12140 switch (inst
.instruction
)
12142 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12143 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12144 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12145 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12146 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12147 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12148 case 0x5600 /* ldrsb */:
12149 case 0x5e00 /* ldrsh */: break;
12153 inst
.instruction
|= inst
.operands
[0].reg
;
12154 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12155 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12161 if (!inst
.operands
[1].present
)
12163 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12164 constraint (inst
.operands
[0].reg
== REG_LR
,
12165 _("r14 not allowed here"));
12166 constraint (inst
.operands
[0].reg
== REG_R12
,
12167 _("r12 not allowed here"));
12170 if (inst
.operands
[2].writeback
12171 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12172 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12173 as_warn (_("base register written back, and overlaps "
12174 "one of transfer registers"));
12176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12177 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12178 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12185 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12191 unsigned Rd
, Rn
, Rm
, Ra
;
12193 Rd
= inst
.operands
[0].reg
;
12194 Rn
= inst
.operands
[1].reg
;
12195 Rm
= inst
.operands
[2].reg
;
12196 Ra
= inst
.operands
[3].reg
;
12198 reject_bad_reg (Rd
);
12199 reject_bad_reg (Rn
);
12200 reject_bad_reg (Rm
);
12201 reject_bad_reg (Ra
);
12203 inst
.instruction
|= Rd
<< 8;
12204 inst
.instruction
|= Rn
<< 16;
12205 inst
.instruction
|= Rm
;
12206 inst
.instruction
|= Ra
<< 12;
12212 unsigned RdLo
, RdHi
, Rn
, Rm
;
12214 RdLo
= inst
.operands
[0].reg
;
12215 RdHi
= inst
.operands
[1].reg
;
12216 Rn
= inst
.operands
[2].reg
;
12217 Rm
= inst
.operands
[3].reg
;
12219 reject_bad_reg (RdLo
);
12220 reject_bad_reg (RdHi
);
12221 reject_bad_reg (Rn
);
12222 reject_bad_reg (Rm
);
12224 inst
.instruction
|= RdLo
<< 12;
12225 inst
.instruction
|= RdHi
<< 8;
12226 inst
.instruction
|= Rn
<< 16;
12227 inst
.instruction
|= Rm
;
12231 do_t_mov_cmp (void)
12235 Rn
= inst
.operands
[0].reg
;
12236 Rm
= inst
.operands
[1].reg
;
12239 set_pred_insn_type_last ();
12241 if (unified_syntax
)
12243 int r0off
= (inst
.instruction
== T_MNEM_mov
12244 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12245 unsigned long opcode
;
12246 bfd_boolean narrow
;
12247 bfd_boolean low_regs
;
12249 low_regs
= (Rn
<= 7 && Rm
<= 7);
12250 opcode
= inst
.instruction
;
12251 if (in_pred_block ())
12252 narrow
= opcode
!= T_MNEM_movs
;
12254 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12255 if (inst
.size_req
== 4
12256 || inst
.operands
[1].shifted
)
12259 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12260 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12261 && !inst
.operands
[1].shifted
12265 inst
.instruction
= T2_SUBS_PC_LR
;
12269 if (opcode
== T_MNEM_cmp
)
12271 constraint (Rn
== REG_PC
, BAD_PC
);
12274 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12276 warn_deprecated_sp (Rm
);
12277 /* R15 was documented as a valid choice for Rm in ARMv6,
12278 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12279 tools reject R15, so we do too. */
12280 constraint (Rm
== REG_PC
, BAD_PC
);
12283 reject_bad_reg (Rm
);
12285 else if (opcode
== T_MNEM_mov
12286 || opcode
== T_MNEM_movs
)
12288 if (inst
.operands
[1].isreg
)
12290 if (opcode
== T_MNEM_movs
)
12292 reject_bad_reg (Rn
);
12293 reject_bad_reg (Rm
);
12297 /* This is mov.n. */
12298 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12299 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12301 as_tsktsk (_("Use of r%u as a source register is "
12302 "deprecated when r%u is the destination "
12303 "register."), Rm
, Rn
);
12308 /* This is mov.w. */
12309 constraint (Rn
== REG_PC
, BAD_PC
);
12310 constraint (Rm
== REG_PC
, BAD_PC
);
12311 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12312 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12316 reject_bad_reg (Rn
);
12319 if (!inst
.operands
[1].isreg
)
12321 /* Immediate operand. */
12322 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12324 if (low_regs
&& narrow
)
12326 inst
.instruction
= THUMB_OP16 (opcode
);
12327 inst
.instruction
|= Rn
<< 8;
12328 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12329 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12331 if (inst
.size_req
== 2)
12332 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12334 inst
.relax
= opcode
;
12339 constraint ((inst
.relocs
[0].type
12340 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12341 && (inst
.relocs
[0].type
12342 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12343 THUMB1_RELOC_ONLY
);
12345 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12346 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12347 inst
.instruction
|= Rn
<< r0off
;
12348 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12351 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12352 && (inst
.instruction
== T_MNEM_mov
12353 || inst
.instruction
== T_MNEM_movs
))
12355 /* Register shifts are encoded as separate shift instructions. */
12356 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12358 if (in_pred_block ())
12363 if (inst
.size_req
== 4)
12366 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12372 switch (inst
.operands
[1].shift_kind
)
12375 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12378 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12381 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12384 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12390 inst
.instruction
= opcode
;
12393 inst
.instruction
|= Rn
;
12394 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12399 inst
.instruction
|= CONDS_BIT
;
12401 inst
.instruction
|= Rn
<< 8;
12402 inst
.instruction
|= Rm
<< 16;
12403 inst
.instruction
|= inst
.operands
[1].imm
;
12408 /* Some mov with immediate shift have narrow variants.
12409 Register shifts are handled above. */
12410 if (low_regs
&& inst
.operands
[1].shifted
12411 && (inst
.instruction
== T_MNEM_mov
12412 || inst
.instruction
== T_MNEM_movs
))
12414 if (in_pred_block ())
12415 narrow
= (inst
.instruction
== T_MNEM_mov
);
12417 narrow
= (inst
.instruction
== T_MNEM_movs
);
12422 switch (inst
.operands
[1].shift_kind
)
12424 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12425 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12426 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12427 default: narrow
= FALSE
; break;
12433 inst
.instruction
|= Rn
;
12434 inst
.instruction
|= Rm
<< 3;
12435 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12439 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12440 inst
.instruction
|= Rn
<< r0off
;
12441 encode_thumb32_shifted_operand (1);
12445 switch (inst
.instruction
)
12448 /* In v4t or v5t a move of two lowregs produces unpredictable
12449 results. Don't allow this. */
12452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12453 "MOV Rd, Rs with two low registers is not "
12454 "permitted on this architecture");
12455 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12459 inst
.instruction
= T_OPCODE_MOV_HR
;
12460 inst
.instruction
|= (Rn
& 0x8) << 4;
12461 inst
.instruction
|= (Rn
& 0x7);
12462 inst
.instruction
|= Rm
<< 3;
12466 /* We know we have low registers at this point.
12467 Generate LSLS Rd, Rs, #0. */
12468 inst
.instruction
= T_OPCODE_LSL_I
;
12469 inst
.instruction
|= Rn
;
12470 inst
.instruction
|= Rm
<< 3;
12476 inst
.instruction
= T_OPCODE_CMP_LR
;
12477 inst
.instruction
|= Rn
;
12478 inst
.instruction
|= Rm
<< 3;
12482 inst
.instruction
= T_OPCODE_CMP_HR
;
12483 inst
.instruction
|= (Rn
& 0x8) << 4;
12484 inst
.instruction
|= (Rn
& 0x7);
12485 inst
.instruction
|= Rm
<< 3;
12492 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12494 /* PR 10443: Do not silently ignore shifted operands. */
12495 constraint (inst
.operands
[1].shifted
,
12496 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12498 if (inst
.operands
[1].isreg
)
12500 if (Rn
< 8 && Rm
< 8)
12502 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12503 since a MOV instruction produces unpredictable results. */
12504 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12505 inst
.instruction
= T_OPCODE_ADD_I3
;
12507 inst
.instruction
= T_OPCODE_CMP_LR
;
12509 inst
.instruction
|= Rn
;
12510 inst
.instruction
|= Rm
<< 3;
12514 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12515 inst
.instruction
= T_OPCODE_MOV_HR
;
12517 inst
.instruction
= T_OPCODE_CMP_HR
;
12523 constraint (Rn
> 7,
12524 _("only lo regs allowed with immediate"));
12525 inst
.instruction
|= Rn
<< 8;
12526 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12537 top
= (inst
.instruction
& 0x00800000) != 0;
12538 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12540 constraint (top
, _(":lower16: not allowed in this instruction"));
12541 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12543 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12545 constraint (!top
, _(":upper16: not allowed in this instruction"));
12546 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12549 Rd
= inst
.operands
[0].reg
;
12550 reject_bad_reg (Rd
);
12552 inst
.instruction
|= Rd
<< 8;
12553 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12555 imm
= inst
.relocs
[0].exp
.X_add_number
;
12556 inst
.instruction
|= (imm
& 0xf000) << 4;
12557 inst
.instruction
|= (imm
& 0x0800) << 15;
12558 inst
.instruction
|= (imm
& 0x0700) << 4;
12559 inst
.instruction
|= (imm
& 0x00ff);
12564 do_t_mvn_tst (void)
12568 Rn
= inst
.operands
[0].reg
;
12569 Rm
= inst
.operands
[1].reg
;
12571 if (inst
.instruction
== T_MNEM_cmp
12572 || inst
.instruction
== T_MNEM_cmn
)
12573 constraint (Rn
== REG_PC
, BAD_PC
);
12575 reject_bad_reg (Rn
);
12576 reject_bad_reg (Rm
);
12578 if (unified_syntax
)
12580 int r0off
= (inst
.instruction
== T_MNEM_mvn
12581 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12582 bfd_boolean narrow
;
12584 if (inst
.size_req
== 4
12585 || inst
.instruction
> 0xffff
12586 || inst
.operands
[1].shifted
12587 || Rn
> 7 || Rm
> 7)
12589 else if (inst
.instruction
== T_MNEM_cmn
12590 || inst
.instruction
== T_MNEM_tst
)
12592 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12593 narrow
= !in_pred_block ();
12595 narrow
= in_pred_block ();
12597 if (!inst
.operands
[1].isreg
)
12599 /* For an immediate, we always generate a 32-bit opcode;
12600 section relaxation will shrink it later if possible. */
12601 if (inst
.instruction
< 0xffff)
12602 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12603 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12604 inst
.instruction
|= Rn
<< r0off
;
12605 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12609 /* See if we can do this with a 16-bit instruction. */
12612 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12613 inst
.instruction
|= Rn
;
12614 inst
.instruction
|= Rm
<< 3;
12618 constraint (inst
.operands
[1].shifted
12619 && inst
.operands
[1].immisreg
,
12620 _("shift must be constant"));
12621 if (inst
.instruction
< 0xffff)
12622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12623 inst
.instruction
|= Rn
<< r0off
;
12624 encode_thumb32_shifted_operand (1);
12630 constraint (inst
.instruction
> 0xffff
12631 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12632 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12633 _("unshifted register required"));
12634 constraint (Rn
> 7 || Rm
> 7,
12637 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12638 inst
.instruction
|= Rn
;
12639 inst
.instruction
|= Rm
<< 3;
12648 if (do_vfp_nsyn_mrs () == SUCCESS
)
12651 Rd
= inst
.operands
[0].reg
;
12652 reject_bad_reg (Rd
);
12653 inst
.instruction
|= Rd
<< 8;
12655 if (inst
.operands
[1].isreg
)
12657 unsigned br
= inst
.operands
[1].reg
;
12658 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12659 as_bad (_("bad register for mrs"));
12661 inst
.instruction
|= br
& (0xf << 16);
12662 inst
.instruction
|= (br
& 0x300) >> 4;
12663 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12667 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12669 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12671 /* PR gas/12698: The constraint is only applied for m_profile.
12672 If the user has specified -march=all, we want to ignore it as
12673 we are building for any CPU type, including non-m variants. */
12674 bfd_boolean m_profile
=
12675 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12676 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12677 "not support requested special purpose register"));
12680 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12682 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12683 _("'APSR', 'CPSR' or 'SPSR' expected"));
12685 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12686 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12687 inst
.instruction
|= 0xf0000;
12697 if (do_vfp_nsyn_msr () == SUCCESS
)
12700 constraint (!inst
.operands
[1].isreg
,
12701 _("Thumb encoding does not support an immediate here"));
12703 if (inst
.operands
[0].isreg
)
12704 flags
= (int)(inst
.operands
[0].reg
);
12706 flags
= inst
.operands
[0].imm
;
12708 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12710 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12712 /* PR gas/12698: The constraint is only applied for m_profile.
12713 If the user has specified -march=all, we want to ignore it as
12714 we are building for any CPU type, including non-m variants. */
12715 bfd_boolean m_profile
=
12716 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12717 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12718 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12719 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12720 && bits
!= PSR_f
)) && m_profile
,
12721 _("selected processor does not support requested special "
12722 "purpose register"));
12725 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12726 "requested special purpose register"));
12728 Rn
= inst
.operands
[1].reg
;
12729 reject_bad_reg (Rn
);
12731 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12732 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12733 inst
.instruction
|= (flags
& 0x300) >> 4;
12734 inst
.instruction
|= (flags
& 0xff);
12735 inst
.instruction
|= Rn
<< 16;
12741 bfd_boolean narrow
;
12742 unsigned Rd
, Rn
, Rm
;
12744 if (!inst
.operands
[2].present
)
12745 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12747 Rd
= inst
.operands
[0].reg
;
12748 Rn
= inst
.operands
[1].reg
;
12749 Rm
= inst
.operands
[2].reg
;
12751 if (unified_syntax
)
12753 if (inst
.size_req
== 4
12759 else if (inst
.instruction
== T_MNEM_muls
)
12760 narrow
= !in_pred_block ();
12762 narrow
= in_pred_block ();
12766 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12767 constraint (Rn
> 7 || Rm
> 7,
12774 /* 16-bit MULS/Conditional MUL. */
12775 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12776 inst
.instruction
|= Rd
;
12779 inst
.instruction
|= Rm
<< 3;
12781 inst
.instruction
|= Rn
<< 3;
12783 constraint (1, _("dest must overlap one source register"));
12787 constraint (inst
.instruction
!= T_MNEM_mul
,
12788 _("Thumb-2 MUL must not set flags"));
12790 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12791 inst
.instruction
|= Rd
<< 8;
12792 inst
.instruction
|= Rn
<< 16;
12793 inst
.instruction
|= Rm
<< 0;
12795 reject_bad_reg (Rd
);
12796 reject_bad_reg (Rn
);
12797 reject_bad_reg (Rm
);
12804 unsigned RdLo
, RdHi
, Rn
, Rm
;
12806 RdLo
= inst
.operands
[0].reg
;
12807 RdHi
= inst
.operands
[1].reg
;
12808 Rn
= inst
.operands
[2].reg
;
12809 Rm
= inst
.operands
[3].reg
;
12811 reject_bad_reg (RdLo
);
12812 reject_bad_reg (RdHi
);
12813 reject_bad_reg (Rn
);
12814 reject_bad_reg (Rm
);
12816 inst
.instruction
|= RdLo
<< 12;
12817 inst
.instruction
|= RdHi
<< 8;
12818 inst
.instruction
|= Rn
<< 16;
12819 inst
.instruction
|= Rm
;
12822 as_tsktsk (_("rdhi and rdlo must be different"));
12828 set_pred_insn_type (NEUTRAL_IT_INSN
);
12830 if (unified_syntax
)
12832 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12834 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12835 inst
.instruction
|= inst
.operands
[0].imm
;
12839 /* PR9722: Check for Thumb2 availability before
12840 generating a thumb2 nop instruction. */
12841 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12843 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12844 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12847 inst
.instruction
= 0x46c0;
12852 constraint (inst
.operands
[0].present
,
12853 _("Thumb does not support NOP with hints"));
12854 inst
.instruction
= 0x46c0;
12861 if (unified_syntax
)
12863 bfd_boolean narrow
;
12865 if (THUMB_SETS_FLAGS (inst
.instruction
))
12866 narrow
= !in_pred_block ();
12868 narrow
= in_pred_block ();
12869 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12871 if (inst
.size_req
== 4)
12876 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12877 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12882 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12883 inst
.instruction
|= inst
.operands
[0].reg
;
12884 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12889 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12891 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12894 inst
.instruction
|= inst
.operands
[0].reg
;
12895 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12904 Rd
= inst
.operands
[0].reg
;
12905 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12907 reject_bad_reg (Rd
);
12908 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12909 reject_bad_reg (Rn
);
12911 inst
.instruction
|= Rd
<< 8;
12912 inst
.instruction
|= Rn
<< 16;
12914 if (!inst
.operands
[2].isreg
)
12916 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12917 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12923 Rm
= inst
.operands
[2].reg
;
12924 reject_bad_reg (Rm
);
12926 constraint (inst
.operands
[2].shifted
12927 && inst
.operands
[2].immisreg
,
12928 _("shift must be constant"));
12929 encode_thumb32_shifted_operand (2);
12936 unsigned Rd
, Rn
, Rm
;
12938 Rd
= inst
.operands
[0].reg
;
12939 Rn
= inst
.operands
[1].reg
;
12940 Rm
= inst
.operands
[2].reg
;
12942 reject_bad_reg (Rd
);
12943 reject_bad_reg (Rn
);
12944 reject_bad_reg (Rm
);
12946 inst
.instruction
|= Rd
<< 8;
12947 inst
.instruction
|= Rn
<< 16;
12948 inst
.instruction
|= Rm
;
12949 if (inst
.operands
[3].present
)
12951 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
12952 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
12953 _("expression too complex"));
12954 inst
.instruction
|= (val
& 0x1c) << 10;
12955 inst
.instruction
|= (val
& 0x03) << 6;
12962 if (!inst
.operands
[3].present
)
12966 inst
.instruction
&= ~0x00000020;
12968 /* PR 10168. Swap the Rm and Rn registers. */
12969 Rtmp
= inst
.operands
[1].reg
;
12970 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12971 inst
.operands
[2].reg
= Rtmp
;
12979 if (inst
.operands
[0].immisreg
)
12980 reject_bad_reg (inst
.operands
[0].imm
);
12982 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12986 do_t_push_pop (void)
12990 constraint (inst
.operands
[0].writeback
,
12991 _("push/pop do not support {reglist}^"));
12992 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12993 _("expression too complex"));
12995 mask
= inst
.operands
[0].imm
;
12996 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12997 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12998 else if (inst
.size_req
!= 4
12999 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13000 ? REG_LR
: REG_PC
)))
13002 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13003 inst
.instruction
|= THUMB_PP_PC_LR
;
13004 inst
.instruction
|= mask
& 0xff;
13006 else if (unified_syntax
)
13008 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13009 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13013 inst
.error
= _("invalid register list to push/pop instruction");
13021 if (unified_syntax
)
13022 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13025 inst
.error
= _("invalid register list to push/pop instruction");
13031 do_t_vscclrm (void)
13033 if (inst
.operands
[0].issingle
)
13035 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13036 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13037 inst
.instruction
|= inst
.operands
[0].imm
;
13041 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13042 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13043 inst
.instruction
|= 1 << 8;
13044 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13053 Rd
= inst
.operands
[0].reg
;
13054 Rm
= inst
.operands
[1].reg
;
13056 reject_bad_reg (Rd
);
13057 reject_bad_reg (Rm
);
13059 inst
.instruction
|= Rd
<< 8;
13060 inst
.instruction
|= Rm
<< 16;
13061 inst
.instruction
|= Rm
;
13069 Rd
= inst
.operands
[0].reg
;
13070 Rm
= inst
.operands
[1].reg
;
13072 reject_bad_reg (Rd
);
13073 reject_bad_reg (Rm
);
13075 if (Rd
<= 7 && Rm
<= 7
13076 && inst
.size_req
!= 4)
13078 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13079 inst
.instruction
|= Rd
;
13080 inst
.instruction
|= Rm
<< 3;
13082 else if (unified_syntax
)
13084 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13085 inst
.instruction
|= Rd
<< 8;
13086 inst
.instruction
|= Rm
<< 16;
13087 inst
.instruction
|= Rm
;
13090 inst
.error
= BAD_HIREG
;
13098 Rd
= inst
.operands
[0].reg
;
13099 Rm
= inst
.operands
[1].reg
;
13101 reject_bad_reg (Rd
);
13102 reject_bad_reg (Rm
);
13104 inst
.instruction
|= Rd
<< 8;
13105 inst
.instruction
|= Rm
;
13113 Rd
= inst
.operands
[0].reg
;
13114 Rs
= (inst
.operands
[1].present
13115 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13116 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13118 reject_bad_reg (Rd
);
13119 reject_bad_reg (Rs
);
13120 if (inst
.operands
[2].isreg
)
13121 reject_bad_reg (inst
.operands
[2].reg
);
13123 inst
.instruction
|= Rd
<< 8;
13124 inst
.instruction
|= Rs
<< 16;
13125 if (!inst
.operands
[2].isreg
)
13127 bfd_boolean narrow
;
13129 if ((inst
.instruction
& 0x00100000) != 0)
13130 narrow
= !in_pred_block ();
13132 narrow
= in_pred_block ();
13134 if (Rd
> 7 || Rs
> 7)
13137 if (inst
.size_req
== 4 || !unified_syntax
)
13140 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13141 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13144 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13145 relaxation, but it doesn't seem worth the hassle. */
13148 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13149 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13150 inst
.instruction
|= Rs
<< 3;
13151 inst
.instruction
|= Rd
;
13155 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13156 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13160 encode_thumb32_shifted_operand (2);
13166 if (warn_on_deprecated
13167 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13168 as_tsktsk (_("setend use is deprecated for ARMv8"));
13170 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13171 if (inst
.operands
[0].imm
)
13172 inst
.instruction
|= 0x8;
13178 if (!inst
.operands
[1].present
)
13179 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13181 if (unified_syntax
)
13183 bfd_boolean narrow
;
13186 switch (inst
.instruction
)
13189 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13191 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13193 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13195 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13199 if (THUMB_SETS_FLAGS (inst
.instruction
))
13200 narrow
= !in_pred_block ();
13202 narrow
= in_pred_block ();
13203 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13205 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13207 if (inst
.operands
[2].isreg
13208 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13209 || inst
.operands
[2].reg
> 7))
13211 if (inst
.size_req
== 4)
13214 reject_bad_reg (inst
.operands
[0].reg
);
13215 reject_bad_reg (inst
.operands
[1].reg
);
13219 if (inst
.operands
[2].isreg
)
13221 reject_bad_reg (inst
.operands
[2].reg
);
13222 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13223 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13224 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13225 inst
.instruction
|= inst
.operands
[2].reg
;
13227 /* PR 12854: Error on extraneous shifts. */
13228 constraint (inst
.operands
[2].shifted
,
13229 _("extraneous shift as part of operand to shift insn"));
13233 inst
.operands
[1].shifted
= 1;
13234 inst
.operands
[1].shift_kind
= shift_kind
;
13235 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13236 ? T_MNEM_movs
: T_MNEM_mov
);
13237 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13238 encode_thumb32_shifted_operand (1);
13239 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13240 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13245 if (inst
.operands
[2].isreg
)
13247 switch (shift_kind
)
13249 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13250 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13251 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13252 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13256 inst
.instruction
|= inst
.operands
[0].reg
;
13257 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13259 /* PR 12854: Error on extraneous shifts. */
13260 constraint (inst
.operands
[2].shifted
,
13261 _("extraneous shift as part of operand to shift insn"));
13265 switch (shift_kind
)
13267 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13268 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13269 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13272 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13273 inst
.instruction
|= inst
.operands
[0].reg
;
13274 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13280 constraint (inst
.operands
[0].reg
> 7
13281 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13282 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13284 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13286 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13287 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13288 _("source1 and dest must be same register"));
13290 switch (inst
.instruction
)
13292 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13293 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13294 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13295 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13299 inst
.instruction
|= inst
.operands
[0].reg
;
13300 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13302 /* PR 12854: Error on extraneous shifts. */
13303 constraint (inst
.operands
[2].shifted
,
13304 _("extraneous shift as part of operand to shift insn"));
13308 switch (inst
.instruction
)
13310 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13311 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13312 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13313 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13316 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13317 inst
.instruction
|= inst
.operands
[0].reg
;
13318 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13326 unsigned Rd
, Rn
, Rm
;
13328 Rd
= inst
.operands
[0].reg
;
13329 Rn
= inst
.operands
[1].reg
;
13330 Rm
= inst
.operands
[2].reg
;
13332 reject_bad_reg (Rd
);
13333 reject_bad_reg (Rn
);
13334 reject_bad_reg (Rm
);
13336 inst
.instruction
|= Rd
<< 8;
13337 inst
.instruction
|= Rn
<< 16;
13338 inst
.instruction
|= Rm
;
13344 unsigned Rd
, Rn
, Rm
;
13346 Rd
= inst
.operands
[0].reg
;
13347 Rm
= inst
.operands
[1].reg
;
13348 Rn
= inst
.operands
[2].reg
;
13350 reject_bad_reg (Rd
);
13351 reject_bad_reg (Rn
);
13352 reject_bad_reg (Rm
);
13354 inst
.instruction
|= Rd
<< 8;
13355 inst
.instruction
|= Rn
<< 16;
13356 inst
.instruction
|= Rm
;
13362 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13364 _("SMC is not permitted on this architecture"));
13365 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13366 _("expression too complex"));
13367 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13368 inst
.instruction
|= (value
& 0xf000) >> 12;
13369 inst
.instruction
|= (value
& 0x0ff0);
13370 inst
.instruction
|= (value
& 0x000f) << 16;
13371 /* PR gas/15623: SMC instructions must be last in an IT block. */
13372 set_pred_insn_type_last ();
13378 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13380 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13381 inst
.instruction
|= (value
& 0x0fff);
13382 inst
.instruction
|= (value
& 0xf000) << 4;
13386 do_t_ssat_usat (int bias
)
13390 Rd
= inst
.operands
[0].reg
;
13391 Rn
= inst
.operands
[2].reg
;
13393 reject_bad_reg (Rd
);
13394 reject_bad_reg (Rn
);
13396 inst
.instruction
|= Rd
<< 8;
13397 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13398 inst
.instruction
|= Rn
<< 16;
13400 if (inst
.operands
[3].present
)
13402 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13404 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13406 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13407 _("expression too complex"));
13409 if (shift_amount
!= 0)
13411 constraint (shift_amount
> 31,
13412 _("shift expression is too large"));
13414 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13415 inst
.instruction
|= 0x00200000; /* sh bit. */
13417 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13418 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13426 do_t_ssat_usat (1);
13434 Rd
= inst
.operands
[0].reg
;
13435 Rn
= inst
.operands
[2].reg
;
13437 reject_bad_reg (Rd
);
13438 reject_bad_reg (Rn
);
13440 inst
.instruction
|= Rd
<< 8;
13441 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13442 inst
.instruction
|= Rn
<< 16;
13448 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13449 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13450 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13451 || inst
.operands
[2].negative
,
13454 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13456 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13457 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13458 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13459 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13465 if (!inst
.operands
[2].present
)
13466 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13468 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13469 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13470 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13473 inst
.instruction
|= inst
.operands
[0].reg
;
13474 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13475 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13476 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13482 unsigned Rd
, Rn
, Rm
;
13484 Rd
= inst
.operands
[0].reg
;
13485 Rn
= inst
.operands
[1].reg
;
13486 Rm
= inst
.operands
[2].reg
;
13488 reject_bad_reg (Rd
);
13489 reject_bad_reg (Rn
);
13490 reject_bad_reg (Rm
);
13492 inst
.instruction
|= Rd
<< 8;
13493 inst
.instruction
|= Rn
<< 16;
13494 inst
.instruction
|= Rm
;
13495 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13503 Rd
= inst
.operands
[0].reg
;
13504 Rm
= inst
.operands
[1].reg
;
13506 reject_bad_reg (Rd
);
13507 reject_bad_reg (Rm
);
13509 if (inst
.instruction
<= 0xffff
13510 && inst
.size_req
!= 4
13511 && Rd
<= 7 && Rm
<= 7
13512 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13515 inst
.instruction
|= Rd
;
13516 inst
.instruction
|= Rm
<< 3;
13518 else if (unified_syntax
)
13520 if (inst
.instruction
<= 0xffff)
13521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13522 inst
.instruction
|= Rd
<< 8;
13523 inst
.instruction
|= Rm
;
13524 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13528 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13529 _("Thumb encoding does not support rotation"));
13530 constraint (1, BAD_HIREG
);
13537 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13546 half
= (inst
.instruction
& 0x10) != 0;
13547 set_pred_insn_type_last ();
13548 constraint (inst
.operands
[0].immisreg
,
13549 _("instruction requires register index"));
13551 Rn
= inst
.operands
[0].reg
;
13552 Rm
= inst
.operands
[0].imm
;
13554 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13555 constraint (Rn
== REG_SP
, BAD_SP
);
13556 reject_bad_reg (Rm
);
13558 constraint (!half
&& inst
.operands
[0].shifted
,
13559 _("instruction does not allow shifted index"));
13560 inst
.instruction
|= (Rn
<< 16) | Rm
;
13566 if (!inst
.operands
[0].present
)
13567 inst
.operands
[0].imm
= 0;
13569 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13571 constraint (inst
.size_req
== 2,
13572 _("immediate value out of range"));
13573 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13574 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13575 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13579 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13580 inst
.instruction
|= inst
.operands
[0].imm
;
13583 set_pred_insn_type (NEUTRAL_IT_INSN
);
13590 do_t_ssat_usat (0);
13598 Rd
= inst
.operands
[0].reg
;
13599 Rn
= inst
.operands
[2].reg
;
13601 reject_bad_reg (Rd
);
13602 reject_bad_reg (Rn
);
13604 inst
.instruction
|= Rd
<< 8;
13605 inst
.instruction
|= inst
.operands
[1].imm
;
13606 inst
.instruction
|= Rn
<< 16;
13609 /* Checking the range of the branch offset (VAL) with NBITS bits
13610 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13612 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13614 gas_assert (nbits
> 0 && nbits
<= 32);
13617 int cmp
= (1 << (nbits
- 1));
13618 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13623 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13629 /* For branches in Armv8.1-M Mainline. */
13631 do_t_branch_future (void)
13633 unsigned long insn
= inst
.instruction
;
13635 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13636 if (inst
.operands
[0].hasreloc
== 0)
13638 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13639 as_bad (BAD_BRANCH_OFF
);
13641 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13645 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13646 inst
.relocs
[0].pc_rel
= 1;
13652 if (inst
.operands
[1].hasreloc
== 0)
13654 int val
= inst
.operands
[1].imm
;
13655 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13656 as_bad (BAD_BRANCH_OFF
);
13658 int immA
= (val
& 0x0001f000) >> 12;
13659 int immB
= (val
& 0x00000ffc) >> 2;
13660 int immC
= (val
& 0x00000002) >> 1;
13661 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13665 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13666 inst
.relocs
[1].pc_rel
= 1;
13671 if (inst
.operands
[1].hasreloc
== 0)
13673 int val
= inst
.operands
[1].imm
;
13674 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13675 as_bad (BAD_BRANCH_OFF
);
13677 int immA
= (val
& 0x0007f000) >> 12;
13678 int immB
= (val
& 0x00000ffc) >> 2;
13679 int immC
= (val
& 0x00000002) >> 1;
13680 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13684 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13685 inst
.relocs
[1].pc_rel
= 1;
13689 case T_MNEM_bfcsel
:
13691 if (inst
.operands
[1].hasreloc
== 0)
13693 int val
= inst
.operands
[1].imm
;
13694 int immA
= (val
& 0x00001000) >> 12;
13695 int immB
= (val
& 0x00000ffc) >> 2;
13696 int immC
= (val
& 0x00000002) >> 1;
13697 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13701 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
13702 inst
.relocs
[1].pc_rel
= 1;
13706 if (inst
.operands
[2].hasreloc
== 0)
13708 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
13709 int val2
= inst
.operands
[2].imm
;
13710 int val0
= inst
.operands
[0].imm
& 0x1f;
13711 int diff
= val2
- val0
;
13713 inst
.instruction
|= 1 << 17; /* T bit. */
13714 else if (diff
!= 2)
13715 as_bad (_("out of range label-relative fixup value"));
13719 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
13720 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
13721 inst
.relocs
[2].pc_rel
= 1;
13725 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
13726 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
13731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13738 /* Helper function for do_t_loloop to handle relocations. */
13740 v8_1_loop_reloc (int is_le
)
13742 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
13744 int value
= inst
.relocs
[0].exp
.X_add_number
;
13745 value
= (is_le
) ? -value
: value
;
13747 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
13748 as_bad (BAD_BRANCH_OFF
);
13752 immh
= (value
& 0x00000ffc) >> 2;
13753 imml
= (value
& 0x00000002) >> 1;
13755 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
13759 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
13760 inst
.relocs
[0].pc_rel
= 1;
13764 /* To handle the Scalar Low Overhead Loop instructions
13765 in Armv8.1-M Mainline. */
13769 unsigned long insn
= inst
.instruction
;
13771 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13778 if (!inst
.operands
[0].present
)
13779 inst
.instruction
|= 1 << 21;
13781 v8_1_loop_reloc (TRUE
);
13785 v8_1_loop_reloc (FALSE
);
13786 /* Fall through. */
13788 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
13789 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
13796 /* Neon instruction encoder helpers. */
13798 /* Encodings for the different types for various Neon opcodes. */
13800 /* An "invalid" code for the following tables. */
13803 struct neon_tab_entry
13806 unsigned float_or_poly
;
13807 unsigned scalar_or_imm
;
13810 /* Map overloaded Neon opcodes to their respective encodings. */
13811 #define NEON_ENC_TAB \
13812 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13813 X(vabdl, 0x0800700, N_INV, N_INV), \
13814 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13815 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13816 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13817 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13818 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13819 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13820 X(vaddl, 0x0800000, N_INV, N_INV), \
13821 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13822 X(vsubl, 0x0800200, N_INV, N_INV), \
13823 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13824 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13825 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13826 /* Register variants of the following two instructions are encoded as
13827 vcge / vcgt with the operands reversed. */ \
13828 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13829 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13830 X(vfma, N_INV, 0x0000c10, N_INV), \
13831 X(vfms, N_INV, 0x0200c10, N_INV), \
13832 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13833 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13834 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13835 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13836 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13837 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13838 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13839 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13840 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13841 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13842 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13843 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13844 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13845 X(vshl, 0x0000400, N_INV, 0x0800510), \
13846 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13847 X(vand, 0x0000110, N_INV, 0x0800030), \
13848 X(vbic, 0x0100110, N_INV, 0x0800030), \
13849 X(veor, 0x1000110, N_INV, N_INV), \
13850 X(vorn, 0x0300110, N_INV, 0x0800010), \
13851 X(vorr, 0x0200110, N_INV, 0x0800010), \
13852 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13853 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13854 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13855 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13856 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13857 X(vst1, 0x0000000, 0x0800000, N_INV), \
13858 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13859 X(vst2, 0x0000100, 0x0800100, N_INV), \
13860 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13861 X(vst3, 0x0000200, 0x0800200, N_INV), \
13862 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13863 X(vst4, 0x0000300, 0x0800300, N_INV), \
13864 X(vmovn, 0x1b20200, N_INV, N_INV), \
13865 X(vtrn, 0x1b20080, N_INV, N_INV), \
13866 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13867 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13868 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13869 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13870 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13871 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13872 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13873 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13874 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13875 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13876 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13877 X(vseleq, 0xe000a00, N_INV, N_INV), \
13878 X(vselvs, 0xe100a00, N_INV, N_INV), \
13879 X(vselge, 0xe200a00, N_INV, N_INV), \
13880 X(vselgt, 0xe300a00, N_INV, N_INV), \
13881 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13882 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13883 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13884 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13885 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13886 X(aes, 0x3b00300, N_INV, N_INV), \
13887 X(sha3op, 0x2000c00, N_INV, N_INV), \
13888 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13889 X(sha2op, 0x3ba0380, N_INV, N_INV)
13893 #define X(OPC,I,F,S) N_MNEM_##OPC
13898 static const struct neon_tab_entry neon_enc_tab
[] =
13900 #define X(OPC,I,F,S) { (I), (F), (S) }
13905 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13906 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13907 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13908 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13909 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13910 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13911 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13912 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13913 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13914 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13915 #define NEON_ENC_SINGLE_(X) \
13916 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13917 #define NEON_ENC_DOUBLE_(X) \
13918 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13919 #define NEON_ENC_FPV8_(X) \
13920 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13922 #define NEON_ENCODE(type, inst) \
13925 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13926 inst.is_neon = 1; \
13930 #define check_neon_suffixes \
13933 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13935 as_bad (_("invalid neon suffix for non neon instruction")); \
13941 /* Define shapes for instruction operands. The following mnemonic characters
13942 are used in this table:
13944 F - VFP S<n> register
13945 D - Neon D<n> register
13946 Q - Neon Q<n> register
13950 L - D<n> register list
13952 This table is used to generate various data:
13953 - enumerations of the form NS_DDR to be used as arguments to
13955 - a table classifying shapes into single, double, quad, mixed.
13956 - a table used to drive neon_select_shape. */
13958 #define NEON_SHAPE_DEF \
13959 X(3, (D, D, D), DOUBLE), \
13960 X(3, (Q, Q, Q), QUAD), \
13961 X(3, (D, D, I), DOUBLE), \
13962 X(3, (Q, Q, I), QUAD), \
13963 X(3, (D, D, S), DOUBLE), \
13964 X(3, (Q, Q, S), QUAD), \
13965 X(3, (Q, Q, R), QUAD), \
13966 X(2, (D, D), DOUBLE), \
13967 X(2, (Q, Q), QUAD), \
13968 X(2, (D, S), DOUBLE), \
13969 X(2, (Q, S), QUAD), \
13970 X(2, (D, R), DOUBLE), \
13971 X(2, (Q, R), QUAD), \
13972 X(2, (D, I), DOUBLE), \
13973 X(2, (Q, I), QUAD), \
13974 X(3, (D, L, D), DOUBLE), \
13975 X(2, (D, Q), MIXED), \
13976 X(2, (Q, D), MIXED), \
13977 X(3, (D, Q, I), MIXED), \
13978 X(3, (Q, D, I), MIXED), \
13979 X(3, (Q, D, D), MIXED), \
13980 X(3, (D, Q, Q), MIXED), \
13981 X(3, (Q, Q, D), MIXED), \
13982 X(3, (Q, D, S), MIXED), \
13983 X(3, (D, Q, S), MIXED), \
13984 X(4, (D, D, D, I), DOUBLE), \
13985 X(4, (Q, Q, Q, I), QUAD), \
13986 X(4, (D, D, S, I), DOUBLE), \
13987 X(4, (Q, Q, S, I), QUAD), \
13988 X(2, (F, F), SINGLE), \
13989 X(3, (F, F, F), SINGLE), \
13990 X(2, (F, I), SINGLE), \
13991 X(2, (F, D), MIXED), \
13992 X(2, (D, F), MIXED), \
13993 X(3, (F, F, I), MIXED), \
13994 X(4, (R, R, F, F), SINGLE), \
13995 X(4, (F, F, R, R), SINGLE), \
13996 X(3, (D, R, R), DOUBLE), \
13997 X(3, (R, R, D), DOUBLE), \
13998 X(2, (S, R), SINGLE), \
13999 X(2, (R, S), SINGLE), \
14000 X(2, (F, R), SINGLE), \
14001 X(2, (R, F), SINGLE), \
14002 /* Half float shape supported so far. */\
14003 X (2, (H, D), MIXED), \
14004 X (2, (D, H), MIXED), \
14005 X (2, (H, F), MIXED), \
14006 X (2, (F, H), MIXED), \
14007 X (2, (H, H), HALF), \
14008 X (2, (H, R), HALF), \
14009 X (2, (R, H), HALF), \
14010 X (2, (H, I), HALF), \
14011 X (3, (H, H, H), HALF), \
14012 X (3, (H, F, I), MIXED), \
14013 X (3, (F, H, I), MIXED), \
14014 X (3, (D, H, H), MIXED), \
14015 X (3, (D, H, S), MIXED)
14017 #define S2(A,B) NS_##A##B
14018 #define S3(A,B,C) NS_##A##B##C
14019 #define S4(A,B,C,D) NS_##A##B##C##D
14021 #define X(N, L, C) S##N L
14034 enum neon_shape_class
14043 #define X(N, L, C) SC_##C
14045 static enum neon_shape_class neon_shape_class
[] =
14064 /* Register widths of above. */
14065 static unsigned neon_shape_el_size
[] =
14077 struct neon_shape_info
14080 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14083 #define S2(A,B) { SE_##A, SE_##B }
14084 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14085 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14087 #define X(N, L, C) { N, S##N L }
14089 static struct neon_shape_info neon_shape_tab
[] =
14099 /* Bit masks used in type checking given instructions.
14100 'N_EQK' means the type must be the same as (or based on in some way) the key
14101 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14102 set, various other bits can be set as well in order to modify the meaning of
14103 the type constraint. */
14105 enum neon_type_mask
14129 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14130 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14131 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14132 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14133 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14134 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14135 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14136 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14137 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14138 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14139 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14141 N_MAX_NONSPECIAL
= N_P64
14144 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14146 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14147 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14148 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14149 #define N_S_32 (N_S8 | N_S16 | N_S32)
14150 #define N_F_16_32 (N_F16 | N_F32)
14151 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14152 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14153 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14154 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14155 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14156 #define N_F_MVE (N_F16 | N_F32)
14157 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14159 /* Pass this as the first type argument to neon_check_type to ignore types
14161 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14163 /* Select a "shape" for the current instruction (describing register types or
14164 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14165 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14166 function of operand parsing, so this function doesn't need to be called.
14167 Shapes should be listed in order of decreasing length. */
14169 static enum neon_shape
14170 neon_select_shape (enum neon_shape shape
, ...)
14173 enum neon_shape first_shape
= shape
;
14175 /* Fix missing optional operands. FIXME: we don't know at this point how
14176 many arguments we should have, so this makes the assumption that we have
14177 > 1. This is true of all current Neon opcodes, I think, but may not be
14178 true in the future. */
14179 if (!inst
.operands
[1].present
)
14180 inst
.operands
[1] = inst
.operands
[0];
14182 va_start (ap
, shape
);
14184 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14189 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14191 if (!inst
.operands
[j
].present
)
14197 switch (neon_shape_tab
[shape
].el
[j
])
14199 /* If a .f16, .16, .u16, .s16 type specifier is given over
14200 a VFP single precision register operand, it's essentially
14201 means only half of the register is used.
14203 If the type specifier is given after the mnemonics, the
14204 information is stored in inst.vectype. If the type specifier
14205 is given after register operand, the information is stored
14206 in inst.operands[].vectype.
14208 When there is only one type specifier, and all the register
14209 operands are the same type of hardware register, the type
14210 specifier applies to all register operands.
14212 If no type specifier is given, the shape is inferred from
14213 operand information.
14216 vadd.f16 s0, s1, s2: NS_HHH
14217 vabs.f16 s0, s1: NS_HH
14218 vmov.f16 s0, r1: NS_HR
14219 vmov.f16 r0, s1: NS_RH
14220 vcvt.f16 r0, s1: NS_RH
14221 vcvt.f16.s32 s2, s2, #29: NS_HFI
14222 vcvt.f16.s32 s2, s2: NS_HF
14225 if (!(inst
.operands
[j
].isreg
14226 && inst
.operands
[j
].isvec
14227 && inst
.operands
[j
].issingle
14228 && !inst
.operands
[j
].isquad
14229 && ((inst
.vectype
.elems
== 1
14230 && inst
.vectype
.el
[0].size
== 16)
14231 || (inst
.vectype
.elems
> 1
14232 && inst
.vectype
.el
[j
].size
== 16)
14233 || (inst
.vectype
.elems
== 0
14234 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14235 && inst
.operands
[j
].vectype
.size
== 16))))
14240 if (!(inst
.operands
[j
].isreg
14241 && inst
.operands
[j
].isvec
14242 && inst
.operands
[j
].issingle
14243 && !inst
.operands
[j
].isquad
14244 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14245 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14246 || (inst
.vectype
.elems
== 0
14247 && (inst
.operands
[j
].vectype
.size
== 32
14248 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14253 if (!(inst
.operands
[j
].isreg
14254 && inst
.operands
[j
].isvec
14255 && !inst
.operands
[j
].isquad
14256 && !inst
.operands
[j
].issingle
))
14261 if (!(inst
.operands
[j
].isreg
14262 && !inst
.operands
[j
].isvec
))
14267 if (!(inst
.operands
[j
].isreg
14268 && inst
.operands
[j
].isvec
14269 && inst
.operands
[j
].isquad
14270 && !inst
.operands
[j
].issingle
))
14275 if (!(!inst
.operands
[j
].isreg
14276 && !inst
.operands
[j
].isscalar
))
14281 if (!(!inst
.operands
[j
].isreg
14282 && inst
.operands
[j
].isscalar
))
14292 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14293 /* We've matched all the entries in the shape table, and we don't
14294 have any left over operands which have not been matched. */
14300 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14301 first_error (_("invalid instruction shape"));
14306 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14307 means the Q bit should be set). */
14310 neon_quad (enum neon_shape shape
)
14312 return neon_shape_class
[shape
] == SC_QUAD
;
14316 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14319 /* Allow modification to be made to types which are constrained to be
14320 based on the key element, based on bits set alongside N_EQK. */
14321 if ((typebits
& N_EQK
) != 0)
14323 if ((typebits
& N_HLF
) != 0)
14325 else if ((typebits
& N_DBL
) != 0)
14327 if ((typebits
& N_SGN
) != 0)
14328 *g_type
= NT_signed
;
14329 else if ((typebits
& N_UNS
) != 0)
14330 *g_type
= NT_unsigned
;
14331 else if ((typebits
& N_INT
) != 0)
14332 *g_type
= NT_integer
;
14333 else if ((typebits
& N_FLT
) != 0)
14334 *g_type
= NT_float
;
14335 else if ((typebits
& N_SIZ
) != 0)
14336 *g_type
= NT_untyped
;
14340 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14341 operand type, i.e. the single type specified in a Neon instruction when it
14342 is the only one given. */
14344 static struct neon_type_el
14345 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14347 struct neon_type_el dest
= *key
;
14349 gas_assert ((thisarg
& N_EQK
) != 0);
14351 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14356 /* Convert Neon type and size into compact bitmask representation. */
14358 static enum neon_type_mask
14359 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14366 case 8: return N_8
;
14367 case 16: return N_16
;
14368 case 32: return N_32
;
14369 case 64: return N_64
;
14377 case 8: return N_I8
;
14378 case 16: return N_I16
;
14379 case 32: return N_I32
;
14380 case 64: return N_I64
;
14388 case 16: return N_F16
;
14389 case 32: return N_F32
;
14390 case 64: return N_F64
;
14398 case 8: return N_P8
;
14399 case 16: return N_P16
;
14400 case 64: return N_P64
;
14408 case 8: return N_S8
;
14409 case 16: return N_S16
;
14410 case 32: return N_S32
;
14411 case 64: return N_S64
;
14419 case 8: return N_U8
;
14420 case 16: return N_U16
;
14421 case 32: return N_U32
;
14422 case 64: return N_U64
;
14433 /* Convert compact Neon bitmask type representation to a type and size. Only
14434 handles the case where a single bit is set in the mask. */
14437 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14438 enum neon_type_mask mask
)
14440 if ((mask
& N_EQK
) != 0)
14443 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14445 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14447 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14449 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14454 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14456 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14457 *type
= NT_unsigned
;
14458 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14459 *type
= NT_integer
;
14460 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14461 *type
= NT_untyped
;
14462 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14464 else if ((mask
& (N_F_ALL
)) != 0)
14472 /* Modify a bitmask of allowed types. This is only needed for type
14476 modify_types_allowed (unsigned allowed
, unsigned mods
)
14479 enum neon_el_type type
;
14485 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14487 if (el_type_of_type_chk (&type
, &size
,
14488 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14490 neon_modify_type_size (mods
, &type
, &size
);
14491 destmask
|= type_chk_of_el_type (type
, size
);
14498 /* Check type and return type classification.
14499 The manual states (paraphrase): If one datatype is given, it indicates the
14501 - the second operand, if there is one
14502 - the operand, if there is no second operand
14503 - the result, if there are no operands.
14504 This isn't quite good enough though, so we use a concept of a "key" datatype
14505 which is set on a per-instruction basis, which is the one which matters when
14506 only one data type is written.
14507 Note: this function has side-effects (e.g. filling in missing operands). All
14508 Neon instructions should call it before performing bit encoding. */
14510 static struct neon_type_el
14511 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14514 unsigned i
, pass
, key_el
= 0;
14515 unsigned types
[NEON_MAX_TYPE_ELS
];
14516 enum neon_el_type k_type
= NT_invtype
;
14517 unsigned k_size
= -1u;
14518 struct neon_type_el badtype
= {NT_invtype
, -1};
14519 unsigned key_allowed
= 0;
14521 /* Optional registers in Neon instructions are always (not) in operand 1.
14522 Fill in the missing operand here, if it was omitted. */
14523 if (els
> 1 && !inst
.operands
[1].present
)
14524 inst
.operands
[1] = inst
.operands
[0];
14526 /* Suck up all the varargs. */
14528 for (i
= 0; i
< els
; i
++)
14530 unsigned thisarg
= va_arg (ap
, unsigned);
14531 if (thisarg
== N_IGNORE_TYPE
)
14536 types
[i
] = thisarg
;
14537 if ((thisarg
& N_KEY
) != 0)
14542 if (inst
.vectype
.elems
> 0)
14543 for (i
= 0; i
< els
; i
++)
14544 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14546 first_error (_("types specified in both the mnemonic and operands"));
14550 /* Duplicate inst.vectype elements here as necessary.
14551 FIXME: No idea if this is exactly the same as the ARM assembler,
14552 particularly when an insn takes one register and one non-register
14554 if (inst
.vectype
.elems
== 1 && els
> 1)
14557 inst
.vectype
.elems
= els
;
14558 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14559 for (j
= 0; j
< els
; j
++)
14561 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14564 else if (inst
.vectype
.elems
== 0 && els
> 0)
14567 /* No types were given after the mnemonic, so look for types specified
14568 after each operand. We allow some flexibility here; as long as the
14569 "key" operand has a type, we can infer the others. */
14570 for (j
= 0; j
< els
; j
++)
14571 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14572 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14574 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14576 for (j
= 0; j
< els
; j
++)
14577 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14578 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14583 first_error (_("operand types can't be inferred"));
14587 else if (inst
.vectype
.elems
!= els
)
14589 first_error (_("type specifier has the wrong number of parts"));
14593 for (pass
= 0; pass
< 2; pass
++)
14595 for (i
= 0; i
< els
; i
++)
14597 unsigned thisarg
= types
[i
];
14598 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14599 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14600 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14601 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14603 /* Decay more-specific signed & unsigned types to sign-insensitive
14604 integer types if sign-specific variants are unavailable. */
14605 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14606 && (types_allowed
& N_SU_ALL
) == 0)
14607 g_type
= NT_integer
;
14609 /* If only untyped args are allowed, decay any more specific types to
14610 them. Some instructions only care about signs for some element
14611 sizes, so handle that properly. */
14612 if (((types_allowed
& N_UNT
) == 0)
14613 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14614 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14615 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14616 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14617 g_type
= NT_untyped
;
14621 if ((thisarg
& N_KEY
) != 0)
14625 key_allowed
= thisarg
& ~N_KEY
;
14627 /* Check architecture constraint on FP16 extension. */
14629 && k_type
== NT_float
14630 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14632 inst
.error
= _(BAD_FP16
);
14639 if ((thisarg
& N_VFP
) != 0)
14641 enum neon_shape_el regshape
;
14642 unsigned regwidth
, match
;
14644 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14647 first_error (_("invalid instruction shape"));
14650 regshape
= neon_shape_tab
[ns
].el
[i
];
14651 regwidth
= neon_shape_el_size
[regshape
];
14653 /* In VFP mode, operands must match register widths. If we
14654 have a key operand, use its width, else use the width of
14655 the current operand. */
14661 /* FP16 will use a single precision register. */
14662 if (regwidth
== 32 && match
== 16)
14664 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14668 inst
.error
= _(BAD_FP16
);
14673 if (regwidth
!= match
)
14675 first_error (_("operand size must match register width"));
14680 if ((thisarg
& N_EQK
) == 0)
14682 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14684 if ((given_type
& types_allowed
) == 0)
14686 first_error (_("bad type in SIMD instruction"));
14692 enum neon_el_type mod_k_type
= k_type
;
14693 unsigned mod_k_size
= k_size
;
14694 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14695 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14697 first_error (_("inconsistent types in Neon instruction"));
14705 return inst
.vectype
.el
[key_el
];
14708 /* Neon-style VFP instruction forwarding. */
14710 /* Thumb VFP instructions have 0xE in the condition field. */
14713 do_vfp_cond_or_thumb (void)
14718 inst
.instruction
|= 0xe0000000;
14720 inst
.instruction
|= inst
.cond
<< 28;
14723 /* Look up and encode a simple mnemonic, for use as a helper function for the
14724 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14725 etc. It is assumed that operand parsing has already been done, and that the
14726 operands are in the form expected by the given opcode (this isn't necessarily
14727 the same as the form in which they were parsed, hence some massaging must
14728 take place before this function is called).
14729 Checks current arch version against that in the looked-up opcode. */
14732 do_vfp_nsyn_opcode (const char *opname
)
14734 const struct asm_opcode
*opcode
;
14736 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14741 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14742 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14749 inst
.instruction
= opcode
->tvalue
;
14750 opcode
->tencode ();
14754 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14755 opcode
->aencode ();
14760 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14762 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14764 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14767 do_vfp_nsyn_opcode ("fadds");
14769 do_vfp_nsyn_opcode ("fsubs");
14771 /* ARMv8.2 fp16 instruction. */
14773 do_scalar_fp16_v82_encode ();
14778 do_vfp_nsyn_opcode ("faddd");
14780 do_vfp_nsyn_opcode ("fsubd");
14784 /* Check operand types to see if this is a VFP instruction, and if so call
14788 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14790 enum neon_shape rs
;
14791 struct neon_type_el et
;
14796 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14797 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14801 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14802 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14803 N_F_ALL
| N_KEY
| N_VFP
);
14810 if (et
.type
!= NT_invtype
)
14821 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14823 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14825 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14828 do_vfp_nsyn_opcode ("fmacs");
14830 do_vfp_nsyn_opcode ("fnmacs");
14832 /* ARMv8.2 fp16 instruction. */
14834 do_scalar_fp16_v82_encode ();
14839 do_vfp_nsyn_opcode ("fmacd");
14841 do_vfp_nsyn_opcode ("fnmacd");
14846 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14848 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14850 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14853 do_vfp_nsyn_opcode ("ffmas");
14855 do_vfp_nsyn_opcode ("ffnmas");
14857 /* ARMv8.2 fp16 instruction. */
14859 do_scalar_fp16_v82_encode ();
14864 do_vfp_nsyn_opcode ("ffmad");
14866 do_vfp_nsyn_opcode ("ffnmad");
14871 do_vfp_nsyn_mul (enum neon_shape rs
)
14873 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14875 do_vfp_nsyn_opcode ("fmuls");
14877 /* ARMv8.2 fp16 instruction. */
14879 do_scalar_fp16_v82_encode ();
14882 do_vfp_nsyn_opcode ("fmuld");
14886 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14888 int is_neg
= (inst
.instruction
& 0x80) != 0;
14889 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14891 if (rs
== NS_FF
|| rs
== NS_HH
)
14894 do_vfp_nsyn_opcode ("fnegs");
14896 do_vfp_nsyn_opcode ("fabss");
14898 /* ARMv8.2 fp16 instruction. */
14900 do_scalar_fp16_v82_encode ();
14905 do_vfp_nsyn_opcode ("fnegd");
14907 do_vfp_nsyn_opcode ("fabsd");
14911 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14912 insns belong to Neon, and are handled elsewhere. */
14915 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14917 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14921 do_vfp_nsyn_opcode ("fldmdbs");
14923 do_vfp_nsyn_opcode ("fldmias");
14928 do_vfp_nsyn_opcode ("fstmdbs");
14930 do_vfp_nsyn_opcode ("fstmias");
14935 do_vfp_nsyn_sqrt (void)
14937 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14938 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14940 if (rs
== NS_FF
|| rs
== NS_HH
)
14942 do_vfp_nsyn_opcode ("fsqrts");
14944 /* ARMv8.2 fp16 instruction. */
14946 do_scalar_fp16_v82_encode ();
14949 do_vfp_nsyn_opcode ("fsqrtd");
14953 do_vfp_nsyn_div (void)
14955 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14956 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14957 N_F_ALL
| N_KEY
| N_VFP
);
14959 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14961 do_vfp_nsyn_opcode ("fdivs");
14963 /* ARMv8.2 fp16 instruction. */
14965 do_scalar_fp16_v82_encode ();
14968 do_vfp_nsyn_opcode ("fdivd");
14972 do_vfp_nsyn_nmul (void)
14974 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14975 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14976 N_F_ALL
| N_KEY
| N_VFP
);
14978 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14980 NEON_ENCODE (SINGLE
, inst
);
14981 do_vfp_sp_dyadic ();
14983 /* ARMv8.2 fp16 instruction. */
14985 do_scalar_fp16_v82_encode ();
14989 NEON_ENCODE (DOUBLE
, inst
);
14990 do_vfp_dp_rd_rn_rm ();
14992 do_vfp_cond_or_thumb ();
14997 do_vfp_nsyn_cmp (void)
14999 enum neon_shape rs
;
15000 if (inst
.operands
[1].isreg
)
15002 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15003 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15005 if (rs
== NS_FF
|| rs
== NS_HH
)
15007 NEON_ENCODE (SINGLE
, inst
);
15008 do_vfp_sp_monadic ();
15012 NEON_ENCODE (DOUBLE
, inst
);
15013 do_vfp_dp_rd_rm ();
15018 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15019 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15021 switch (inst
.instruction
& 0x0fffffff)
15024 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15027 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15033 if (rs
== NS_FI
|| rs
== NS_HI
)
15035 NEON_ENCODE (SINGLE
, inst
);
15036 do_vfp_sp_compare_z ();
15040 NEON_ENCODE (DOUBLE
, inst
);
15044 do_vfp_cond_or_thumb ();
15046 /* ARMv8.2 fp16 instruction. */
15047 if (rs
== NS_HI
|| rs
== NS_HH
)
15048 do_scalar_fp16_v82_encode ();
15052 nsyn_insert_sp (void)
15054 inst
.operands
[1] = inst
.operands
[0];
15055 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15056 inst
.operands
[0].reg
= REG_SP
;
15057 inst
.operands
[0].isreg
= 1;
15058 inst
.operands
[0].writeback
= 1;
15059 inst
.operands
[0].present
= 1;
15063 do_vfp_nsyn_push (void)
15067 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15068 _("register list must contain at least 1 and at most 16 "
15071 if (inst
.operands
[1].issingle
)
15072 do_vfp_nsyn_opcode ("fstmdbs");
15074 do_vfp_nsyn_opcode ("fstmdbd");
15078 do_vfp_nsyn_pop (void)
15082 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15083 _("register list must contain at least 1 and at most 16 "
15086 if (inst
.operands
[1].issingle
)
15087 do_vfp_nsyn_opcode ("fldmias");
15089 do_vfp_nsyn_opcode ("fldmiad");
15092 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15093 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15096 neon_dp_fixup (struct arm_it
* insn
)
15098 unsigned int i
= insn
->instruction
;
15103 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15114 insn
->instruction
= i
;
15117 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15121 neon_logbits (unsigned x
)
15123 return ffs (x
) - 4;
15126 #define LOW4(R) ((R) & 0xf)
15127 #define HI1(R) (((R) >> 4) & 1)
15130 mve_encode_qqr (int size
, int fp
)
15132 if (inst
.operands
[2].reg
== REG_SP
)
15133 as_tsktsk (MVE_BAD_SP
);
15134 else if (inst
.operands
[2].reg
== REG_PC
)
15135 as_tsktsk (MVE_BAD_PC
);
15140 if (((unsigned)inst
.instruction
) == 0xd00)
15141 inst
.instruction
= 0xee300f40;
15143 else if (((unsigned)inst
.instruction
) == 0x200d00)
15144 inst
.instruction
= 0xee301f40;
15146 /* Setting size which is 1 for F16 and 0 for F32. */
15147 inst
.instruction
|= (size
== 16) << 28;
15152 if (((unsigned)inst
.instruction
) == 0x800)
15153 inst
.instruction
= 0xee010f40;
15155 else if (((unsigned)inst
.instruction
) == 0x1000800)
15156 inst
.instruction
= 0xee011f40;
15157 /* Setting bits for size. */
15158 inst
.instruction
|= neon_logbits (size
) << 20;
15160 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15161 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15162 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15163 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15164 inst
.instruction
|= inst
.operands
[2].reg
;
15168 /* Encode insns with bit pattern:
15170 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15171 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15173 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15174 different meaning for some instruction. */
15177 neon_three_same (int isquad
, int ubit
, int size
)
15179 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15180 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15181 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15182 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15183 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15184 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15185 inst
.instruction
|= (isquad
!= 0) << 6;
15186 inst
.instruction
|= (ubit
!= 0) << 24;
15188 inst
.instruction
|= neon_logbits (size
) << 20;
15190 neon_dp_fixup (&inst
);
15193 /* Encode instructions of the form:
15195 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15196 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15198 Don't write size if SIZE == -1. */
15201 neon_two_same (int qbit
, int ubit
, int size
)
15203 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15204 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15205 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15206 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15207 inst
.instruction
|= (qbit
!= 0) << 6;
15208 inst
.instruction
|= (ubit
!= 0) << 24;
15211 inst
.instruction
|= neon_logbits (size
) << 18;
15213 neon_dp_fixup (&inst
);
15216 /* Neon instruction encoders, in approximate order of appearance. */
15219 do_neon_dyadic_i_su (void)
15221 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15222 struct neon_type_el et
= neon_check_type (3, rs
,
15223 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15224 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15228 do_neon_dyadic_i64_su (void)
15230 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15231 struct neon_type_el et
= neon_check_type (3, rs
,
15232 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15233 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15237 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15240 unsigned size
= et
.size
>> 3;
15241 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15242 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15243 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15244 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15245 inst
.instruction
|= (isquad
!= 0) << 6;
15246 inst
.instruction
|= immbits
<< 16;
15247 inst
.instruction
|= (size
>> 3) << 7;
15248 inst
.instruction
|= (size
& 0x7) << 19;
15250 inst
.instruction
|= (uval
!= 0) << 24;
15252 neon_dp_fixup (&inst
);
15256 do_neon_shl_imm (void)
15258 if (!inst
.operands
[2].isreg
)
15260 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15261 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15262 int imm
= inst
.operands
[2].imm
;
15264 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15265 _("immediate out of range for shift"));
15266 NEON_ENCODE (IMMED
, inst
);
15267 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15271 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15272 struct neon_type_el et
= neon_check_type (3, rs
,
15273 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15276 /* VSHL/VQSHL 3-register variants have syntax such as:
15278 whereas other 3-register operations encoded by neon_three_same have
15281 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15283 tmp
= inst
.operands
[2].reg
;
15284 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15285 inst
.operands
[1].reg
= tmp
;
15286 NEON_ENCODE (INTEGER
, inst
);
15287 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15292 do_neon_qshl_imm (void)
15294 if (!inst
.operands
[2].isreg
)
15296 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15297 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15298 int imm
= inst
.operands
[2].imm
;
15300 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15301 _("immediate out of range for shift"));
15302 NEON_ENCODE (IMMED
, inst
);
15303 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15307 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15308 struct neon_type_el et
= neon_check_type (3, rs
,
15309 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15312 /* See note in do_neon_shl_imm. */
15313 tmp
= inst
.operands
[2].reg
;
15314 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15315 inst
.operands
[1].reg
= tmp
;
15316 NEON_ENCODE (INTEGER
, inst
);
15317 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15322 do_neon_rshl (void)
15324 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15325 struct neon_type_el et
= neon_check_type (3, rs
,
15326 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15329 tmp
= inst
.operands
[2].reg
;
15330 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15331 inst
.operands
[1].reg
= tmp
;
15332 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15336 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15338 /* Handle .I8 pseudo-instructions. */
15341 /* Unfortunately, this will make everything apart from zero out-of-range.
15342 FIXME is this the intended semantics? There doesn't seem much point in
15343 accepting .I8 if so. */
15344 immediate
|= immediate
<< 8;
15350 if (immediate
== (immediate
& 0x000000ff))
15352 *immbits
= immediate
;
15355 else if (immediate
== (immediate
& 0x0000ff00))
15357 *immbits
= immediate
>> 8;
15360 else if (immediate
== (immediate
& 0x00ff0000))
15362 *immbits
= immediate
>> 16;
15365 else if (immediate
== (immediate
& 0xff000000))
15367 *immbits
= immediate
>> 24;
15370 if ((immediate
& 0xffff) != (immediate
>> 16))
15371 goto bad_immediate
;
15372 immediate
&= 0xffff;
15375 if (immediate
== (immediate
& 0x000000ff))
15377 *immbits
= immediate
;
15380 else if (immediate
== (immediate
& 0x0000ff00))
15382 *immbits
= immediate
>> 8;
15387 first_error (_("immediate value out of range"));
15392 do_neon_logic (void)
15394 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
15396 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15397 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15398 /* U bit and size field were set as part of the bitmask. */
15399 NEON_ENCODE (INTEGER
, inst
);
15400 neon_three_same (neon_quad (rs
), 0, -1);
15404 const int three_ops_form
= (inst
.operands
[2].present
15405 && !inst
.operands
[2].isreg
);
15406 const int immoperand
= (three_ops_form
? 2 : 1);
15407 enum neon_shape rs
= (three_ops_form
15408 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
15409 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
15410 struct neon_type_el et
= neon_check_type (2, rs
,
15411 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15412 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
15416 if (et
.type
== NT_invtype
)
15419 if (three_ops_form
)
15420 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15421 _("first and second operands shall be the same register"));
15423 NEON_ENCODE (IMMED
, inst
);
15425 immbits
= inst
.operands
[immoperand
].imm
;
15428 /* .i64 is a pseudo-op, so the immediate must be a repeating
15430 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
15431 inst
.operands
[immoperand
].reg
: 0))
15433 /* Set immbits to an invalid constant. */
15434 immbits
= 0xdeadbeef;
15441 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15445 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15449 /* Pseudo-instruction for VBIC. */
15450 neon_invert_size (&immbits
, 0, et
.size
);
15451 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15455 /* Pseudo-instruction for VORR. */
15456 neon_invert_size (&immbits
, 0, et
.size
);
15457 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
15467 inst
.instruction
|= neon_quad (rs
) << 6;
15468 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15469 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15470 inst
.instruction
|= cmode
<< 8;
15471 neon_write_immbits (immbits
);
15473 neon_dp_fixup (&inst
);
15478 do_neon_bitfield (void)
15480 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15481 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15482 neon_three_same (neon_quad (rs
), 0, -1);
15486 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
15489 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
15490 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
15492 if (et
.type
== NT_float
)
15494 NEON_ENCODE (FLOAT
, inst
);
15496 mve_encode_qqr (et
.size
, 1);
15498 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15502 NEON_ENCODE (INTEGER
, inst
);
15504 mve_encode_qqr (et
.size
, 0);
15506 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
15512 do_neon_dyadic_if_su_d (void)
15514 /* This version only allow D registers, but that constraint is enforced during
15515 operand parsing so we don't need to do anything extra here. */
15516 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15520 do_neon_dyadic_if_i_d (void)
15522 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15523 affected if we specify unsigned args. */
15524 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15527 enum vfp_or_neon_is_neon_bits
15530 NEON_CHECK_ARCH
= 2,
15531 NEON_CHECK_ARCH8
= 4
15534 /* Call this function if an instruction which may have belonged to the VFP or
15535 Neon instruction sets, but turned out to be a Neon instruction (due to the
15536 operand types involved, etc.). We have to check and/or fix-up a couple of
15539 - Make sure the user hasn't attempted to make a Neon instruction
15541 - Alter the value in the condition code field if necessary.
15542 - Make sure that the arch supports Neon instructions.
15544 Which of these operations take place depends on bits from enum
15545 vfp_or_neon_is_neon_bits.
15547 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
15548 current instruction's condition is COND_ALWAYS, the condition field is
15549 changed to inst.uncond_value. This is necessary because instructions shared
15550 between VFP and Neon may be conditional for the VFP variants only, and the
15551 unconditional Neon version must have, e.g., 0xF in the condition field. */
15554 vfp_or_neon_is_neon (unsigned check
)
15556 /* Conditions are always legal in Thumb mode (IT blocks). */
15557 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
15559 if (inst
.cond
!= COND_ALWAYS
)
15561 first_error (_(BAD_COND
));
15564 if (inst
.uncond_value
!= -1)
15565 inst
.instruction
|= inst
.uncond_value
<< 28;
15569 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
15570 || ((check
& NEON_CHECK_ARCH8
)
15571 && !mark_feature_used (&fpu_neon_ext_armv8
)))
15573 first_error (_(BAD_FPU
));
15581 check_simd_pred_availability (int fp
, unsigned check
)
15583 if (inst
.cond
> COND_ALWAYS
)
15585 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15587 inst
.error
= BAD_FPU
;
15590 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15592 else if (inst
.cond
< COND_ALWAYS
)
15594 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15595 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15596 else if (vfp_or_neon_is_neon (check
) == FAIL
)
15601 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
15602 && vfp_or_neon_is_neon (check
) == FAIL
)
15605 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
15606 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15612 do_neon_dyadic_if_su (void)
15614 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
15615 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15618 if (check_simd_pred_availability (et
.type
== NT_float
,
15619 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
15622 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
15626 do_neon_addsub_if_i (void)
15628 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
15629 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15632 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
15633 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
15634 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
15636 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
15637 /* If we are parsing Q registers and the element types match MVE, which NEON
15638 also supports, then we must check whether this is an instruction that can
15639 be used by both MVE/NEON. This distinction can be made based on whether
15640 they are predicated or not. */
15641 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
15643 if (check_simd_pred_availability (et
.type
== NT_float
,
15644 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
15649 /* If they are either in a D register or are using an unsupported. */
15651 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15655 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15656 affected if we specify unsigned args. */
15657 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15660 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15662 V<op> A,B (A is operand 0, B is operand 2)
15667 so handle that case specially. */
15670 neon_exchange_operands (void)
15672 if (inst
.operands
[1].present
)
15674 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15676 /* Swap operands[1] and operands[2]. */
15677 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15678 inst
.operands
[1] = inst
.operands
[2];
15679 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15684 inst
.operands
[1] = inst
.operands
[2];
15685 inst
.operands
[2] = inst
.operands
[0];
15690 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15692 if (inst
.operands
[2].isreg
)
15695 neon_exchange_operands ();
15696 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15700 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15701 struct neon_type_el et
= neon_check_type (2, rs
,
15702 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15704 NEON_ENCODE (IMMED
, inst
);
15705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15707 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15708 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15709 inst
.instruction
|= neon_quad (rs
) << 6;
15710 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15711 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15713 neon_dp_fixup (&inst
);
15720 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15724 do_neon_cmp_inv (void)
15726 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15732 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15735 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15736 scalars, which are encoded in 5 bits, M : Rm.
15737 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15738 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15741 Dot Product instructions are similar to multiply instructions except elsize
15742 should always be 32.
15744 This function translates SCALAR, which is GAS's internal encoding of indexed
15745 scalar register, to raw encoding. There is also register and index range
15746 check based on ELSIZE. */
15749 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15751 unsigned regno
= NEON_SCALAR_REG (scalar
);
15752 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15757 if (regno
> 7 || elno
> 3)
15759 return regno
| (elno
<< 3);
15762 if (regno
> 15 || elno
> 1)
15764 return regno
| (elno
<< 4);
15768 first_error (_("scalar out of range for multiply instruction"));
15774 /* Encode multiply / multiply-accumulate scalar instructions. */
15777 neon_mul_mac (struct neon_type_el et
, int ubit
)
15781 /* Give a more helpful error message if we have an invalid type. */
15782 if (et
.type
== NT_invtype
)
15785 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15786 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15787 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15788 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15789 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15790 inst
.instruction
|= LOW4 (scalar
);
15791 inst
.instruction
|= HI1 (scalar
) << 5;
15792 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15793 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15794 inst
.instruction
|= (ubit
!= 0) << 24;
15796 neon_dp_fixup (&inst
);
15800 do_neon_mac_maybe_scalar (void)
15802 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15805 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15808 if (inst
.operands
[2].isscalar
)
15810 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15811 struct neon_type_el et
= neon_check_type (3, rs
,
15812 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15813 NEON_ENCODE (SCALAR
, inst
);
15814 neon_mul_mac (et
, neon_quad (rs
));
15818 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15819 affected if we specify unsigned args. */
15820 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15825 do_neon_fmac (void)
15827 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15830 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15833 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15839 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15840 struct neon_type_el et
= neon_check_type (3, rs
,
15841 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15842 neon_three_same (neon_quad (rs
), 0, et
.size
);
15845 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15846 same types as the MAC equivalents. The polynomial type for this instruction
15847 is encoded the same as the integer type. */
15852 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15855 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15858 if (inst
.operands
[2].isscalar
)
15859 do_neon_mac_maybe_scalar ();
15861 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15865 do_neon_qdmulh (void)
15867 if (inst
.operands
[2].isscalar
)
15869 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15870 struct neon_type_el et
= neon_check_type (3, rs
,
15871 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15872 NEON_ENCODE (SCALAR
, inst
);
15873 neon_mul_mac (et
, neon_quad (rs
));
15877 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15878 struct neon_type_el et
= neon_check_type (3, rs
,
15879 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15880 NEON_ENCODE (INTEGER
, inst
);
15881 /* The U bit (rounding) comes from bit mask. */
15882 neon_three_same (neon_quad (rs
), 0, et
.size
);
15887 do_neon_qrdmlah (void)
15889 /* Check we're on the correct architecture. */
15890 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15892 _("instruction form not available on this architecture.");
15893 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15895 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15896 record_feature_use (&fpu_neon_ext_v8_1
);
15899 if (inst
.operands
[2].isscalar
)
15901 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15902 struct neon_type_el et
= neon_check_type (3, rs
,
15903 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15904 NEON_ENCODE (SCALAR
, inst
);
15905 neon_mul_mac (et
, neon_quad (rs
));
15909 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15910 struct neon_type_el et
= neon_check_type (3, rs
,
15911 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15912 NEON_ENCODE (INTEGER
, inst
);
15913 /* The U bit (rounding) comes from bit mask. */
15914 neon_three_same (neon_quad (rs
), 0, et
.size
);
15919 do_neon_fcmp_absolute (void)
15921 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15922 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15923 N_F_16_32
| N_KEY
);
15924 /* Size field comes from bit mask. */
15925 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15929 do_neon_fcmp_absolute_inv (void)
15931 neon_exchange_operands ();
15932 do_neon_fcmp_absolute ();
15936 do_neon_step (void)
15938 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15939 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15940 N_F_16_32
| N_KEY
);
15941 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15945 do_neon_abs_neg (void)
15947 enum neon_shape rs
;
15948 struct neon_type_el et
;
15950 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15953 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15954 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15956 if (check_simd_pred_availability (et
.type
== NT_float
,
15957 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
15960 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15961 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15962 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15963 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15964 inst
.instruction
|= neon_quad (rs
) << 6;
15965 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15966 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15968 neon_dp_fixup (&inst
);
15974 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15975 struct neon_type_el et
= neon_check_type (2, rs
,
15976 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15977 int imm
= inst
.operands
[2].imm
;
15978 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15979 _("immediate out of range for insert"));
15980 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15986 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15987 struct neon_type_el et
= neon_check_type (2, rs
,
15988 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15989 int imm
= inst
.operands
[2].imm
;
15990 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15991 _("immediate out of range for insert"));
15992 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15996 do_neon_qshlu_imm (void)
15998 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15999 struct neon_type_el et
= neon_check_type (2, rs
,
16000 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
16001 int imm
= inst
.operands
[2].imm
;
16002 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16003 _("immediate out of range for shift"));
16004 /* Only encodes the 'U present' variant of the instruction.
16005 In this case, signed types have OP (bit 8) set to 0.
16006 Unsigned types have OP set to 1. */
16007 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
16008 /* The rest of the bits are the same as other immediate shifts. */
16009 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16013 do_neon_qmovn (void)
16015 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16016 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
16017 /* Saturating move where operands can be signed or unsigned, and the
16018 destination has the same signedness. */
16019 NEON_ENCODE (INTEGER
, inst
);
16020 if (et
.type
== NT_unsigned
)
16021 inst
.instruction
|= 0xc0;
16023 inst
.instruction
|= 0x80;
16024 neon_two_same (0, 1, et
.size
/ 2);
16028 do_neon_qmovun (void)
16030 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16031 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
16032 /* Saturating move with unsigned results. Operands must be signed. */
16033 NEON_ENCODE (INTEGER
, inst
);
16034 neon_two_same (0, 1, et
.size
/ 2);
16038 do_neon_rshift_sat_narrow (void)
16040 /* FIXME: Types for narrowing. If operands are signed, results can be signed
16041 or unsigned. If operands are unsigned, results must also be unsigned. */
16042 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16043 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
16044 int imm
= inst
.operands
[2].imm
;
16045 /* This gets the bounds check, size encoding and immediate bits calculation
16049 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
16050 VQMOVN.I<size> <Dd>, <Qm>. */
16053 inst
.operands
[2].present
= 0;
16054 inst
.instruction
= N_MNEM_vqmovn
;
16059 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16060 _("immediate out of range"));
16061 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
16065 do_neon_rshift_sat_narrow_u (void)
16067 /* FIXME: Types for narrowing. If operands are signed, results can be signed
16068 or unsigned. If operands are unsigned, results must also be unsigned. */
16069 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16070 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
16071 int imm
= inst
.operands
[2].imm
;
16072 /* This gets the bounds check, size encoding and immediate bits calculation
16076 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
16077 VQMOVUN.I<size> <Dd>, <Qm>. */
16080 inst
.operands
[2].present
= 0;
16081 inst
.instruction
= N_MNEM_vqmovun
;
16086 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16087 _("immediate out of range"));
16088 /* FIXME: The manual is kind of unclear about what value U should have in
16089 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
16091 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
16095 do_neon_movn (void)
16097 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
16098 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
16099 NEON_ENCODE (INTEGER
, inst
);
16100 neon_two_same (0, 1, et
.size
/ 2);
16104 do_neon_rshift_narrow (void)
16106 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
16107 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
16108 int imm
= inst
.operands
[2].imm
;
16109 /* This gets the bounds check, size encoding and immediate bits calculation
16113 /* If immediate is zero then we are a pseudo-instruction for
16114 VMOVN.I<size> <Dd>, <Qm> */
16117 inst
.operands
[2].present
= 0;
16118 inst
.instruction
= N_MNEM_vmovn
;
16123 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16124 _("immediate out of range for narrowing operation"));
16125 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
16129 do_neon_shll (void)
16131 /* FIXME: Type checking when lengthening. */
16132 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
16133 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
16134 unsigned imm
= inst
.operands
[2].imm
;
16136 if (imm
== et
.size
)
16138 /* Maximum shift variant. */
16139 NEON_ENCODE (INTEGER
, inst
);
16140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16142 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16143 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16144 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16146 neon_dp_fixup (&inst
);
16150 /* A more-specific type check for non-max versions. */
16151 et
= neon_check_type (2, NS_QDI
,
16152 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16153 NEON_ENCODE (IMMED
, inst
);
16154 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
16158 /* Check the various types for the VCVT instruction, and return which version
16159 the current instruction is. */
16161 #define CVT_FLAVOUR_VAR \
16162 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
16163 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
16164 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
16165 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
16166 /* Half-precision conversions. */ \
16167 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
16168 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
16169 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
16170 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
16171 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
16172 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
16173 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
16174 Compared with single/double precision variants, only the co-processor \
16175 field is different, so the encoding flow is reused here. */ \
16176 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
16177 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
16178 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
16179 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
16180 /* VFP instructions. */ \
16181 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
16182 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
16183 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
16184 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
16185 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
16186 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
16187 /* VFP instructions with bitshift. */ \
16188 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
16189 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
16190 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
16191 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
16192 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
16193 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
16194 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
16195 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
16197 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
16198 neon_cvt_flavour_##C,
16200 /* The different types of conversions we can do. */
16201 enum neon_cvt_flavour
16204 neon_cvt_flavour_invalid
,
16205 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
16210 static enum neon_cvt_flavour
16211 get_neon_cvt_flavour (enum neon_shape rs
)
16213 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
16214 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
16215 if (et.type != NT_invtype) \
16217 inst.error = NULL; \
16218 return (neon_cvt_flavour_##C); \
16221 struct neon_type_el et
;
16222 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
16223 || rs
== NS_FF
) ? N_VFP
: 0;
16224 /* The instruction versions which take an immediate take one register
16225 argument, which is extended to the width of the full register. Thus the
16226 "source" and "destination" registers must have the same width. Hack that
16227 here by making the size equal to the key (wider, in this case) operand. */
16228 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
16232 return neon_cvt_flavour_invalid
;
16247 /* Neon-syntax VFP conversions. */
16250 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
16252 const char *opname
= 0;
16254 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
16255 || rs
== NS_FHI
|| rs
== NS_HFI
)
16257 /* Conversions with immediate bitshift. */
16258 const char *enc
[] =
16260 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
16266 if (flavour
< (int) ARRAY_SIZE (enc
))
16268 opname
= enc
[flavour
];
16269 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16270 _("operands 0 and 1 must be the same register"));
16271 inst
.operands
[1] = inst
.operands
[2];
16272 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
16277 /* Conversions without bitshift. */
16278 const char *enc
[] =
16280 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
16286 if (flavour
< (int) ARRAY_SIZE (enc
))
16287 opname
= enc
[flavour
];
16291 do_vfp_nsyn_opcode (opname
);
16293 /* ARMv8.2 fp16 VCVT instruction. */
16294 if (flavour
== neon_cvt_flavour_s32_f16
16295 || flavour
== neon_cvt_flavour_u32_f16
16296 || flavour
== neon_cvt_flavour_f16_u32
16297 || flavour
== neon_cvt_flavour_f16_s32
)
16298 do_scalar_fp16_v82_encode ();
16302 do_vfp_nsyn_cvtz (void)
16304 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
16305 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
16306 const char *enc
[] =
16308 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
16314 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
16315 do_vfp_nsyn_opcode (enc
[flavour
]);
16319 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
16320 enum neon_cvt_mode mode
)
16325 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16326 D register operands. */
16327 if (flavour
== neon_cvt_flavour_s32_f64
16328 || flavour
== neon_cvt_flavour_u32_f64
)
16329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16332 if (flavour
== neon_cvt_flavour_s32_f16
16333 || flavour
== neon_cvt_flavour_u32_f16
)
16334 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
16337 set_pred_insn_type (OUTSIDE_PRED_INSN
);
16341 case neon_cvt_flavour_s32_f64
:
16345 case neon_cvt_flavour_s32_f32
:
16349 case neon_cvt_flavour_s32_f16
:
16353 case neon_cvt_flavour_u32_f64
:
16357 case neon_cvt_flavour_u32_f32
:
16361 case neon_cvt_flavour_u32_f16
:
16366 first_error (_("invalid instruction shape"));
16372 case neon_cvt_mode_a
: rm
= 0; break;
16373 case neon_cvt_mode_n
: rm
= 1; break;
16374 case neon_cvt_mode_p
: rm
= 2; break;
16375 case neon_cvt_mode_m
: rm
= 3; break;
16376 default: first_error (_("invalid rounding mode")); return;
16379 NEON_ENCODE (FPV8
, inst
);
16380 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
16381 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
16382 inst
.instruction
|= sz
<< 8;
16384 /* ARMv8.2 fp16 VCVT instruction. */
16385 if (flavour
== neon_cvt_flavour_s32_f16
16386 ||flavour
== neon_cvt_flavour_u32_f16
)
16387 do_scalar_fp16_v82_encode ();
16388 inst
.instruction
|= op
<< 7;
16389 inst
.instruction
|= rm
<< 16;
16390 inst
.instruction
|= 0xf0000000;
16391 inst
.is_neon
= TRUE
;
16395 do_neon_cvt_1 (enum neon_cvt_mode mode
)
16397 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
16398 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
16399 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
16401 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
16403 if (flavour
== neon_cvt_flavour_invalid
)
16406 /* PR11109: Handle round-to-zero for VCVT conversions. */
16407 if (mode
== neon_cvt_mode_z
16408 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
16409 && (flavour
== neon_cvt_flavour_s16_f16
16410 || flavour
== neon_cvt_flavour_u16_f16
16411 || flavour
== neon_cvt_flavour_s32_f32
16412 || flavour
== neon_cvt_flavour_u32_f32
16413 || flavour
== neon_cvt_flavour_s32_f64
16414 || flavour
== neon_cvt_flavour_u32_f64
)
16415 && (rs
== NS_FD
|| rs
== NS_FF
))
16417 do_vfp_nsyn_cvtz ();
16421 /* ARMv8.2 fp16 VCVT conversions. */
16422 if (mode
== neon_cvt_mode_z
16423 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
16424 && (flavour
== neon_cvt_flavour_s32_f16
16425 || flavour
== neon_cvt_flavour_u32_f16
)
16428 do_vfp_nsyn_cvtz ();
16429 do_scalar_fp16_v82_encode ();
16433 /* VFP rather than Neon conversions. */
16434 if (flavour
>= neon_cvt_flavour_first_fp
)
16436 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16437 do_vfp_nsyn_cvt (rs
, flavour
);
16439 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16450 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
16451 0x0000100, 0x1000100, 0x0, 0x1000000};
16453 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16456 /* Fixed-point conversion with #0 immediate is encoded as an
16457 integer conversion. */
16458 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
16460 NEON_ENCODE (IMMED
, inst
);
16461 if (flavour
!= neon_cvt_flavour_invalid
)
16462 inst
.instruction
|= enctab
[flavour
];
16463 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16465 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16466 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16467 inst
.instruction
|= neon_quad (rs
) << 6;
16468 inst
.instruction
|= 1 << 21;
16469 if (flavour
< neon_cvt_flavour_s16_f16
)
16471 inst
.instruction
|= 1 << 21;
16472 immbits
= 32 - inst
.operands
[2].imm
;
16473 inst
.instruction
|= immbits
<< 16;
16477 inst
.instruction
|= 3 << 20;
16478 immbits
= 16 - inst
.operands
[2].imm
;
16479 inst
.instruction
|= immbits
<< 16;
16480 inst
.instruction
&= ~(1 << 9);
16483 neon_dp_fixup (&inst
);
16489 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
16491 NEON_ENCODE (FLOAT
, inst
);
16492 set_pred_insn_type (OUTSIDE_PRED_INSN
);
16494 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16497 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16498 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16499 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16500 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16501 inst
.instruction
|= neon_quad (rs
) << 6;
16502 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
16503 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
16504 inst
.instruction
|= mode
<< 8;
16505 if (flavour
== neon_cvt_flavour_u16_f16
16506 || flavour
== neon_cvt_flavour_s16_f16
)
16507 /* Mask off the original size bits and reencode them. */
16508 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
16511 inst
.instruction
|= 0xfc000000;
16513 inst
.instruction
|= 0xf0000000;
16519 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
16520 0x100, 0x180, 0x0, 0x080};
16522 NEON_ENCODE (INTEGER
, inst
);
16524 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16527 if (flavour
!= neon_cvt_flavour_invalid
)
16528 inst
.instruction
|= enctab
[flavour
];
16530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16534 inst
.instruction
|= neon_quad (rs
) << 6;
16535 if (flavour
>= neon_cvt_flavour_s16_f16
16536 && flavour
<= neon_cvt_flavour_f16_u16
)
16537 /* Half precision. */
16538 inst
.instruction
|= 1 << 18;
16540 inst
.instruction
|= 2 << 18;
16542 neon_dp_fixup (&inst
);
16547 /* Half-precision conversions for Advanced SIMD -- neon. */
16550 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16554 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
16556 as_bad (_("operand size must match register width"));
16561 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
16563 as_bad (_("operand size must match register width"));
16568 inst
.instruction
= 0x3b60600;
16570 inst
.instruction
= 0x3b60700;
16572 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16573 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16574 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16575 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16576 neon_dp_fixup (&inst
);
16580 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
16581 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
16582 do_vfp_nsyn_cvt (rs
, flavour
);
16584 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
16589 do_neon_cvtr (void)
16591 do_neon_cvt_1 (neon_cvt_mode_x
);
16597 do_neon_cvt_1 (neon_cvt_mode_z
);
16601 do_neon_cvta (void)
16603 do_neon_cvt_1 (neon_cvt_mode_a
);
16607 do_neon_cvtn (void)
16609 do_neon_cvt_1 (neon_cvt_mode_n
);
16613 do_neon_cvtp (void)
16615 do_neon_cvt_1 (neon_cvt_mode_p
);
16619 do_neon_cvtm (void)
16621 do_neon_cvt_1 (neon_cvt_mode_m
);
16625 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16628 mark_feature_used (&fpu_vfp_ext_armv8
);
16630 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16631 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16632 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16633 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16634 inst
.instruction
|= to
? 0x10000 : 0;
16635 inst
.instruction
|= t
? 0x80 : 0;
16636 inst
.instruction
|= is_double
? 0x100 : 0;
16637 do_vfp_cond_or_thumb ();
16641 do_neon_cvttb_1 (bfd_boolean t
)
16643 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16644 NS_DF
, NS_DH
, NS_NULL
);
16648 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16651 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16653 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16656 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16658 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16660 /* The VCVTB and VCVTT instructions with D-register operands
16661 don't work for SP only targets. */
16662 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16666 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16668 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16670 /* The VCVTB and VCVTT instructions with D-register operands
16671 don't work for SP only targets. */
16672 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16676 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16683 do_neon_cvtb (void)
16685 do_neon_cvttb_1 (FALSE
);
16690 do_neon_cvtt (void)
16692 do_neon_cvttb_1 (TRUE
);
16696 neon_move_immediate (void)
16698 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16699 struct neon_type_el et
= neon_check_type (2, rs
,
16700 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16701 unsigned immlo
, immhi
= 0, immbits
;
16702 int op
, cmode
, float_p
;
16704 constraint (et
.type
== NT_invtype
,
16705 _("operand size must be specified for immediate VMOV"));
16707 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16708 op
= (inst
.instruction
& (1 << 5)) != 0;
16710 immlo
= inst
.operands
[1].imm
;
16711 if (inst
.operands
[1].regisimm
)
16712 immhi
= inst
.operands
[1].reg
;
16714 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16715 _("immediate has bits set outside the operand size"));
16717 float_p
= inst
.operands
[1].immisfloat
;
16719 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16720 et
.size
, et
.type
)) == FAIL
)
16722 /* Invert relevant bits only. */
16723 neon_invert_size (&immlo
, &immhi
, et
.size
);
16724 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16725 with one or the other; those cases are caught by
16726 neon_cmode_for_move_imm. */
16728 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16729 &op
, et
.size
, et
.type
)) == FAIL
)
16731 first_error (_("immediate out of range"));
16736 inst
.instruction
&= ~(1 << 5);
16737 inst
.instruction
|= op
<< 5;
16739 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16740 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16741 inst
.instruction
|= neon_quad (rs
) << 6;
16742 inst
.instruction
|= cmode
<< 8;
16744 neon_write_immbits (immbits
);
16750 if (inst
.operands
[1].isreg
)
16752 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16754 NEON_ENCODE (INTEGER
, inst
);
16755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16757 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16759 inst
.instruction
|= neon_quad (rs
) << 6;
16763 NEON_ENCODE (IMMED
, inst
);
16764 neon_move_immediate ();
16767 neon_dp_fixup (&inst
);
16770 /* Encode instructions of form:
16772 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16773 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16776 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16778 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16779 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16780 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16781 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16782 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16783 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16784 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16785 inst
.instruction
|= neon_logbits (size
) << 20;
16787 neon_dp_fixup (&inst
);
16791 do_neon_dyadic_long (void)
16793 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16796 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
16799 NEON_ENCODE (INTEGER
, inst
);
16800 /* FIXME: Type checking for lengthening op. */
16801 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16802 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16803 neon_mixed_length (et
, et
.size
);
16805 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
16806 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
16808 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
16809 in an IT block with le/lt conditions. */
16811 if (inst
.cond
== 0xf)
16813 else if (inst
.cond
== 0x10)
16816 inst
.pred_insn_type
= INSIDE_IT_INSN
;
16818 if (inst
.instruction
== N_MNEM_vaddl
)
16820 inst
.instruction
= N_MNEM_vadd
;
16821 do_neon_addsub_if_i ();
16823 else if (inst
.instruction
== N_MNEM_vsubl
)
16825 inst
.instruction
= N_MNEM_vsub
;
16826 do_neon_addsub_if_i ();
16828 else if (inst
.instruction
== N_MNEM_vabdl
)
16830 inst
.instruction
= N_MNEM_vabd
;
16831 do_neon_dyadic_if_su ();
16835 first_error (BAD_FPU
);
16839 do_neon_abal (void)
16841 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16842 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16843 neon_mixed_length (et
, et
.size
);
16847 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16849 if (inst
.operands
[2].isscalar
)
16851 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16852 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16853 NEON_ENCODE (SCALAR
, inst
);
16854 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16858 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16859 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16860 NEON_ENCODE (INTEGER
, inst
);
16861 neon_mixed_length (et
, et
.size
);
16866 do_neon_mac_maybe_scalar_long (void)
16868 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16871 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16872 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16875 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16877 unsigned regno
= NEON_SCALAR_REG (scalar
);
16878 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16882 if (regno
> 7 || elno
> 3)
16885 return ((regno
& 0x7)
16886 | ((elno
& 0x1) << 3)
16887 | (((elno
>> 1) & 0x1) << 5));
16891 if (regno
> 15 || elno
> 1)
16894 return (((regno
& 0x1) << 5)
16895 | ((regno
>> 1) & 0x7)
16896 | ((elno
& 0x1) << 3));
16900 first_error (_("scalar out of range for multiply instruction"));
16905 do_neon_fmac_maybe_scalar_long (int subtype
)
16907 enum neon_shape rs
;
16909 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16910 field (bits[21:20]) has different meaning. For scalar index variant, it's
16911 used to differentiate add and subtract, otherwise it's with fixed value
16915 if (inst
.cond
!= COND_ALWAYS
)
16916 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16917 "behaviour is UNPREDICTABLE"));
16919 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16925 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16926 be a scalar index register. */
16927 if (inst
.operands
[2].isscalar
)
16929 high8
= 0xfe000000;
16932 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16936 high8
= 0xfc000000;
16939 inst
.instruction
|= (0x1 << 23);
16940 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16943 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16945 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16946 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16947 so we simply pass -1 as size. */
16948 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16949 neon_three_same (quad_p
, 0, size
);
16951 /* Undo neon_dp_fixup. Redo the high eight bits. */
16952 inst
.instruction
&= 0x00ffffff;
16953 inst
.instruction
|= high8
;
16955 #define LOW1(R) ((R) & 0x1)
16956 #define HI4(R) (((R) >> 1) & 0xf)
16957 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16958 whether the instruction is in Q form and whether Vm is a scalar indexed
16960 if (inst
.operands
[2].isscalar
)
16963 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16964 inst
.instruction
&= 0xffffffd0;
16965 inst
.instruction
|= rm
;
16969 /* Redo Rn as well. */
16970 inst
.instruction
&= 0xfff0ff7f;
16971 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16972 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16977 /* Redo Rn and Rm. */
16978 inst
.instruction
&= 0xfff0ff50;
16979 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16980 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16981 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16982 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16987 do_neon_vfmal (void)
16989 return do_neon_fmac_maybe_scalar_long (0);
16993 do_neon_vfmsl (void)
16995 return do_neon_fmac_maybe_scalar_long (1);
16999 do_neon_dyadic_wide (void)
17001 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
17002 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17003 neon_mixed_length (et
, et
.size
);
17007 do_neon_dyadic_narrow (void)
17009 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17010 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
17011 /* Operand sign is unimportant, and the U bit is part of the opcode,
17012 so force the operand type to integer. */
17013 et
.type
= NT_integer
;
17014 neon_mixed_length (et
, et
.size
/ 2);
17018 do_neon_mul_sat_scalar_long (void)
17020 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
17024 do_neon_vmull (void)
17026 if (inst
.operands
[2].isscalar
)
17027 do_neon_mac_maybe_scalar_long ();
17030 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17031 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
17033 if (et
.type
== NT_poly
)
17034 NEON_ENCODE (POLY
, inst
);
17036 NEON_ENCODE (INTEGER
, inst
);
17038 /* For polynomial encoding the U bit must be zero, and the size must
17039 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
17040 obviously, as 0b10). */
17043 /* Check we're on the correct architecture. */
17044 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
17046 _("Instruction form not available on this architecture.");
17051 neon_mixed_length (et
, et
.size
);
17058 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17059 struct neon_type_el et
= neon_check_type (3, rs
,
17060 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17061 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
17063 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
17064 _("shift out of range"));
17065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17067 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17068 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17069 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17070 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17071 inst
.instruction
|= neon_quad (rs
) << 6;
17072 inst
.instruction
|= imm
<< 8;
17074 neon_dp_fixup (&inst
);
17080 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17081 struct neon_type_el et
= neon_check_type (2, rs
,
17082 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17083 unsigned op
= (inst
.instruction
>> 7) & 3;
17084 /* N (width of reversed regions) is encoded as part of the bitmask. We
17085 extract it here to check the elements to be reversed are smaller.
17086 Otherwise we'd get a reserved instruction. */
17087 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
17088 gas_assert (elsize
!= 0);
17089 constraint (et
.size
>= elsize
,
17090 _("elements must be smaller than reversal region"));
17091 neon_two_same (neon_quad (rs
), 1, et
.size
);
17097 if (inst
.operands
[1].isscalar
)
17099 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
17100 struct neon_type_el et
= neon_check_type (2, rs
,
17101 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17102 unsigned sizebits
= et
.size
>> 3;
17103 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
17104 int logsize
= neon_logbits (et
.size
);
17105 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
17107 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
17110 NEON_ENCODE (SCALAR
, inst
);
17111 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17112 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17113 inst
.instruction
|= LOW4 (dm
);
17114 inst
.instruction
|= HI1 (dm
) << 5;
17115 inst
.instruction
|= neon_quad (rs
) << 6;
17116 inst
.instruction
|= x
<< 17;
17117 inst
.instruction
|= sizebits
<< 16;
17119 neon_dp_fixup (&inst
);
17123 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
17124 struct neon_type_el et
= neon_check_type (2, rs
,
17125 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
17126 /* Duplicate ARM register to lanes of vector. */
17127 NEON_ENCODE (ARMREG
, inst
);
17130 case 8: inst
.instruction
|= 0x400000; break;
17131 case 16: inst
.instruction
|= 0x000020; break;
17132 case 32: inst
.instruction
|= 0x000000; break;
17135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17136 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
17137 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
17138 inst
.instruction
|= neon_quad (rs
) << 21;
17139 /* The encoding for this instruction is identical for the ARM and Thumb
17140 variants, except for the condition field. */
17141 do_vfp_cond_or_thumb ();
17145 /* VMOV has particularly many variations. It can be one of:
17146 0. VMOV<c><q> <Qd>, <Qm>
17147 1. VMOV<c><q> <Dd>, <Dm>
17148 (Register operations, which are VORR with Rm = Rn.)
17149 2. VMOV<c><q>.<dt> <Qd>, #<imm>
17150 3. VMOV<c><q>.<dt> <Dd>, #<imm>
17152 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
17153 (ARM register to scalar.)
17154 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
17155 (Two ARM registers to vector.)
17156 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
17157 (Scalar to ARM register.)
17158 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
17159 (Vector to two ARM registers.)
17160 8. VMOV.F32 <Sd>, <Sm>
17161 9. VMOV.F64 <Dd>, <Dm>
17162 (VFP register moves.)
17163 10. VMOV.F32 <Sd>, #imm
17164 11. VMOV.F64 <Dd>, #imm
17165 (VFP float immediate load.)
17166 12. VMOV <Rd>, <Sm>
17167 (VFP single to ARM reg.)
17168 13. VMOV <Sd>, <Rm>
17169 (ARM reg to VFP single.)
17170 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
17171 (Two ARM regs to two VFP singles.)
17172 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
17173 (Two VFP singles to two ARM regs.)
17175 These cases can be disambiguated using neon_select_shape, except cases 1/9
17176 and 3/11 which depend on the operand type too.
17178 All the encoded bits are hardcoded by this function.
17180 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
17181 Cases 5, 7 may be used with VFPv2 and above.
17183 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
17184 can specify a type where it doesn't make sense to, and is ignored). */
17189 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
17190 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
17191 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
17192 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
17193 struct neon_type_el et
;
17194 const char *ldconst
= 0;
17198 case NS_DD
: /* case 1/9. */
17199 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
17200 /* It is not an error here if no type is given. */
17202 if (et
.type
== NT_float
&& et
.size
== 64)
17204 do_vfp_nsyn_opcode ("fcpyd");
17207 /* fall through. */
17209 case NS_QQ
: /* case 0/1. */
17211 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17213 /* The architecture manual I have doesn't explicitly state which
17214 value the U bit should have for register->register moves, but
17215 the equivalent VORR instruction has U = 0, so do that. */
17216 inst
.instruction
= 0x0200110;
17217 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17218 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17219 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17220 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17221 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17222 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17223 inst
.instruction
|= neon_quad (rs
) << 6;
17225 neon_dp_fixup (&inst
);
17229 case NS_DI
: /* case 3/11. */
17230 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
17232 if (et
.type
== NT_float
&& et
.size
== 64)
17234 /* case 11 (fconstd). */
17235 ldconst
= "fconstd";
17236 goto encode_fconstd
;
17238 /* fall through. */
17240 case NS_QI
: /* case 2/3. */
17241 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17243 inst
.instruction
= 0x0800010;
17244 neon_move_immediate ();
17245 neon_dp_fixup (&inst
);
17248 case NS_SR
: /* case 4. */
17250 unsigned bcdebits
= 0;
17252 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
17253 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
17255 /* .<size> is optional here, defaulting to .32. */
17256 if (inst
.vectype
.elems
== 0
17257 && inst
.operands
[0].vectype
.type
== NT_invtype
17258 && inst
.operands
[1].vectype
.type
== NT_invtype
)
17260 inst
.vectype
.el
[0].type
= NT_untyped
;
17261 inst
.vectype
.el
[0].size
= 32;
17262 inst
.vectype
.elems
= 1;
17265 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
17266 logsize
= neon_logbits (et
.size
);
17268 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
17270 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
17271 && et
.size
!= 32, _(BAD_FPU
));
17272 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
17273 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
17277 case 8: bcdebits
= 0x8; break;
17278 case 16: bcdebits
= 0x1; break;
17279 case 32: bcdebits
= 0x0; break;
17283 bcdebits
|= x
<< logsize
;
17285 inst
.instruction
= 0xe000b10;
17286 do_vfp_cond_or_thumb ();
17287 inst
.instruction
|= LOW4 (dn
) << 16;
17288 inst
.instruction
|= HI1 (dn
) << 7;
17289 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
17290 inst
.instruction
|= (bcdebits
& 3) << 5;
17291 inst
.instruction
|= (bcdebits
>> 2) << 21;
17295 case NS_DRR
: /* case 5 (fmdrr). */
17296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
17299 inst
.instruction
= 0xc400b10;
17300 do_vfp_cond_or_thumb ();
17301 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
17302 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
17303 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
17304 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
17307 case NS_RS
: /* case 6. */
17310 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
17311 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
17312 unsigned abcdebits
= 0;
17314 /* .<dt> is optional here, defaulting to .32. */
17315 if (inst
.vectype
.elems
== 0
17316 && inst
.operands
[0].vectype
.type
== NT_invtype
17317 && inst
.operands
[1].vectype
.type
== NT_invtype
)
17319 inst
.vectype
.el
[0].type
= NT_untyped
;
17320 inst
.vectype
.el
[0].size
= 32;
17321 inst
.vectype
.elems
= 1;
17324 et
= neon_check_type (2, NS_NULL
,
17325 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
17326 logsize
= neon_logbits (et
.size
);
17328 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
17330 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
17331 && et
.size
!= 32, _(BAD_FPU
));
17332 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
17333 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
17337 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
17338 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
17339 case 32: abcdebits
= 0x00; break;
17343 abcdebits
|= x
<< logsize
;
17344 inst
.instruction
= 0xe100b10;
17345 do_vfp_cond_or_thumb ();
17346 inst
.instruction
|= LOW4 (dn
) << 16;
17347 inst
.instruction
|= HI1 (dn
) << 7;
17348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17349 inst
.instruction
|= (abcdebits
& 3) << 5;
17350 inst
.instruction
|= (abcdebits
>> 2) << 21;
17354 case NS_RRD
: /* case 7 (fmrrd). */
17355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
17358 inst
.instruction
= 0xc500b10;
17359 do_vfp_cond_or_thumb ();
17360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17361 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17362 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17363 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17366 case NS_FF
: /* case 8 (fcpys). */
17367 do_vfp_nsyn_opcode ("fcpys");
17371 case NS_FI
: /* case 10 (fconsts). */
17372 ldconst
= "fconsts";
17374 if (!inst
.operands
[1].immisfloat
)
17377 /* Immediate has to fit in 8 bits so float is enough. */
17378 float imm
= (float) inst
.operands
[1].imm
;
17379 memcpy (&new_imm
, &imm
, sizeof (float));
17380 /* But the assembly may have been written to provide an integer
17381 bit pattern that equates to a float, so check that the
17382 conversion has worked. */
17383 if (is_quarter_float (new_imm
))
17385 if (is_quarter_float (inst
.operands
[1].imm
))
17386 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
17388 inst
.operands
[1].imm
= new_imm
;
17389 inst
.operands
[1].immisfloat
= 1;
17393 if (is_quarter_float (inst
.operands
[1].imm
))
17395 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
17396 do_vfp_nsyn_opcode (ldconst
);
17398 /* ARMv8.2 fp16 vmov.f16 instruction. */
17400 do_scalar_fp16_v82_encode ();
17403 first_error (_("immediate out of range"));
17407 case NS_RF
: /* case 12 (fmrs). */
17408 do_vfp_nsyn_opcode ("fmrs");
17409 /* ARMv8.2 fp16 vmov.f16 instruction. */
17411 do_scalar_fp16_v82_encode ();
17415 case NS_FR
: /* case 13 (fmsr). */
17416 do_vfp_nsyn_opcode ("fmsr");
17417 /* ARMv8.2 fp16 vmov.f16 instruction. */
17419 do_scalar_fp16_v82_encode ();
17422 /* The encoders for the fmrrs and fmsrr instructions expect three operands
17423 (one of which is a list), but we have parsed four. Do some fiddling to
17424 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
17426 case NS_RRFF
: /* case 14 (fmrrs). */
17427 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
17428 _("VFP registers must be adjacent"));
17429 inst
.operands
[2].imm
= 2;
17430 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
17431 do_vfp_nsyn_opcode ("fmrrs");
17434 case NS_FFRR
: /* case 15 (fmsrr). */
17435 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
17436 _("VFP registers must be adjacent"));
17437 inst
.operands
[1] = inst
.operands
[2];
17438 inst
.operands
[2] = inst
.operands
[3];
17439 inst
.operands
[0].imm
= 2;
17440 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
17441 do_vfp_nsyn_opcode ("fmsrr");
17445 /* neon_select_shape has determined that the instruction
17446 shape is wrong and has already set the error message. */
17455 do_neon_rshift_round_imm (void)
17457 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17458 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17459 int imm
= inst
.operands
[2].imm
;
17461 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
17464 inst
.operands
[2].present
= 0;
17469 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17470 _("immediate out of range for shift"));
17471 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
17476 do_neon_movhf (void)
17478 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
17479 constraint (rs
!= NS_HH
, _("invalid suffix"));
17481 if (inst
.cond
!= COND_ALWAYS
)
17485 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
17486 " the behaviour is UNPREDICTABLE"));
17490 inst
.error
= BAD_COND
;
17495 do_vfp_sp_monadic ();
17498 inst
.instruction
|= 0xf0000000;
17502 do_neon_movl (void)
17504 struct neon_type_el et
= neon_check_type (2, NS_QD
,
17505 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17506 unsigned sizebits
= et
.size
>> 3;
17507 inst
.instruction
|= sizebits
<< 19;
17508 neon_two_same (0, et
.type
== NT_unsigned
, -1);
17514 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17515 struct neon_type_el et
= neon_check_type (2, rs
,
17516 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17517 NEON_ENCODE (INTEGER
, inst
);
17518 neon_two_same (neon_quad (rs
), 1, et
.size
);
17522 do_neon_zip_uzp (void)
17524 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17525 struct neon_type_el et
= neon_check_type (2, rs
,
17526 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17527 if (rs
== NS_DD
&& et
.size
== 32)
17529 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
17530 inst
.instruction
= N_MNEM_vtrn
;
17534 neon_two_same (neon_quad (rs
), 1, et
.size
);
17538 do_neon_sat_abs_neg (void)
17540 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17541 struct neon_type_el et
= neon_check_type (2, rs
,
17542 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17543 neon_two_same (neon_quad (rs
), 1, et
.size
);
17547 do_neon_pair_long (void)
17549 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17550 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17551 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
17552 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
17553 neon_two_same (neon_quad (rs
), 1, et
.size
);
17557 do_neon_recip_est (void)
17559 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17560 struct neon_type_el et
= neon_check_type (2, rs
,
17561 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
17562 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17563 neon_two_same (neon_quad (rs
), 1, et
.size
);
17569 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17570 struct neon_type_el et
= neon_check_type (2, rs
,
17571 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17572 neon_two_same (neon_quad (rs
), 1, et
.size
);
17578 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17579 struct neon_type_el et
= neon_check_type (2, rs
,
17580 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
17581 neon_two_same (neon_quad (rs
), 1, et
.size
);
17587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17588 struct neon_type_el et
= neon_check_type (2, rs
,
17589 N_EQK
| N_INT
, N_8
| N_KEY
);
17590 neon_two_same (neon_quad (rs
), 1, et
.size
);
17596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17597 neon_two_same (neon_quad (rs
), 1, -1);
17601 do_neon_tbl_tbx (void)
17603 unsigned listlenbits
;
17604 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
17606 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
17608 first_error (_("bad list length for table lookup"));
17612 listlenbits
= inst
.operands
[1].imm
- 1;
17613 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17614 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17617 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17618 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17619 inst
.instruction
|= listlenbits
<< 8;
17621 neon_dp_fixup (&inst
);
17625 do_neon_ldm_stm (void)
17627 /* P, U and L bits are part of bitmask. */
17628 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
17629 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
17631 if (inst
.operands
[1].issingle
)
17633 do_vfp_nsyn_ldm_stm (is_dbmode
);
17637 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
17638 _("writeback (!) must be used for VLDMDB and VSTMDB"));
17640 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
17641 _("register list must contain at least 1 and at most 16 "
17644 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
17645 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
17646 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
17647 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
17649 inst
.instruction
|= offsetbits
;
17651 do_vfp_cond_or_thumb ();
17655 do_neon_ldr_str (void)
17657 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
17659 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
17660 And is UNPREDICTABLE in thumb mode. */
17662 && inst
.operands
[1].reg
== REG_PC
17663 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
17666 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17667 else if (warn_on_deprecated
)
17668 as_tsktsk (_("Use of PC here is deprecated"));
17671 if (inst
.operands
[0].issingle
)
17674 do_vfp_nsyn_opcode ("flds");
17676 do_vfp_nsyn_opcode ("fsts");
17678 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17679 if (inst
.vectype
.el
[0].size
== 16)
17680 do_scalar_fp16_v82_encode ();
17685 do_vfp_nsyn_opcode ("fldd");
17687 do_vfp_nsyn_opcode ("fstd");
17692 do_t_vldr_vstr_sysreg (void)
17694 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
17695 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
17697 /* Use of PC is UNPREDICTABLE. */
17698 if (inst
.operands
[1].reg
== REG_PC
)
17699 inst
.error
= _("Use of PC here is UNPREDICTABLE");
17701 if (inst
.operands
[1].immisreg
)
17702 inst
.error
= _("instruction does not accept register index");
17704 if (!inst
.operands
[1].isreg
)
17705 inst
.error
= _("instruction does not accept PC-relative addressing");
17707 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
17708 inst
.error
= _("immediate value out of range");
17710 inst
.instruction
= 0xec000f80;
17712 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
17713 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
17714 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
17715 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
17719 do_vldr_vstr (void)
17721 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
17723 /* VLDR/VSTR (System Register). */
17726 if (!mark_feature_used (&arm_ext_v8_1m_main
))
17727 as_bad (_("Instruction not permitted on this architecture"));
17729 do_t_vldr_vstr_sysreg ();
17734 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
17735 as_bad (_("Instruction not permitted on this architecture"));
17736 do_neon_ldr_str ();
17740 /* "interleave" version also handles non-interleaving register VLD1/VST1
17744 do_neon_ld_st_interleave (void)
17746 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17747 N_8
| N_16
| N_32
| N_64
);
17748 unsigned alignbits
= 0;
17750 /* The bits in this table go:
17751 0: register stride of one (0) or two (1)
17752 1,2: register list length, minus one (1, 2, 3, 4).
17753 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17754 We use -1 for invalid entries. */
17755 const int typetable
[] =
17757 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17758 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17759 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17760 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17764 if (et
.type
== NT_invtype
)
17767 if (inst
.operands
[1].immisalign
)
17768 switch (inst
.operands
[1].imm
>> 8)
17770 case 64: alignbits
= 1; break;
17772 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17773 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17774 goto bad_alignment
;
17778 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17779 goto bad_alignment
;
17784 first_error (_("bad alignment"));
17788 inst
.instruction
|= alignbits
<< 4;
17789 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17791 /* Bits [4:6] of the immediate in a list specifier encode register stride
17792 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17793 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17794 up the right value for "type" in a table based on this value and the given
17795 list style, then stick it back. */
17796 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17797 | (((inst
.instruction
>> 8) & 3) << 3);
17799 typebits
= typetable
[idx
];
17801 constraint (typebits
== -1, _("bad list type for instruction"));
17802 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17803 _("bad element type for instruction"));
17805 inst
.instruction
&= ~0xf00;
17806 inst
.instruction
|= typebits
<< 8;
17809 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17810 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17811 otherwise. The variable arguments are a list of pairs of legal (size, align)
17812 values, terminated with -1. */
17815 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17818 int result
= FAIL
, thissize
, thisalign
;
17820 if (!inst
.operands
[1].immisalign
)
17826 va_start (ap
, do_alignment
);
17830 thissize
= va_arg (ap
, int);
17831 if (thissize
== -1)
17833 thisalign
= va_arg (ap
, int);
17835 if (size
== thissize
&& align
== thisalign
)
17838 while (result
!= SUCCESS
);
17842 if (result
== SUCCESS
)
17845 first_error (_("unsupported alignment for instruction"));
17851 do_neon_ld_st_lane (void)
17853 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17854 int align_good
, do_alignment
= 0;
17855 int logsize
= neon_logbits (et
.size
);
17856 int align
= inst
.operands
[1].imm
>> 8;
17857 int n
= (inst
.instruction
>> 8) & 3;
17858 int max_el
= 64 / et
.size
;
17860 if (et
.type
== NT_invtype
)
17863 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17864 _("bad list length"));
17865 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17866 _("scalar index out of range"));
17867 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17869 _("stride of 2 unavailable when element size is 8"));
17873 case 0: /* VLD1 / VST1. */
17874 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17876 if (align_good
== FAIL
)
17880 unsigned alignbits
= 0;
17883 case 16: alignbits
= 0x1; break;
17884 case 32: alignbits
= 0x3; break;
17887 inst
.instruction
|= alignbits
<< 4;
17891 case 1: /* VLD2 / VST2. */
17892 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17893 16, 32, 32, 64, -1);
17894 if (align_good
== FAIL
)
17897 inst
.instruction
|= 1 << 4;
17900 case 2: /* VLD3 / VST3. */
17901 constraint (inst
.operands
[1].immisalign
,
17902 _("can't use alignment with this instruction"));
17905 case 3: /* VLD4 / VST4. */
17906 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17907 16, 64, 32, 64, 32, 128, -1);
17908 if (align_good
== FAIL
)
17912 unsigned alignbits
= 0;
17915 case 8: alignbits
= 0x1; break;
17916 case 16: alignbits
= 0x1; break;
17917 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17920 inst
.instruction
|= alignbits
<< 4;
17927 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17928 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17929 inst
.instruction
|= 1 << (4 + logsize
);
17931 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17932 inst
.instruction
|= logsize
<< 10;
17935 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17938 do_neon_ld_dup (void)
17940 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17941 int align_good
, do_alignment
= 0;
17943 if (et
.type
== NT_invtype
)
17946 switch ((inst
.instruction
>> 8) & 3)
17948 case 0: /* VLD1. */
17949 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17950 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17951 &do_alignment
, 16, 16, 32, 32, -1);
17952 if (align_good
== FAIL
)
17954 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17957 case 2: inst
.instruction
|= 1 << 5; break;
17958 default: first_error (_("bad list length")); return;
17960 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17963 case 1: /* VLD2. */
17964 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17965 &do_alignment
, 8, 16, 16, 32, 32, 64,
17967 if (align_good
== FAIL
)
17969 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17970 _("bad list length"));
17971 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17972 inst
.instruction
|= 1 << 5;
17973 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17976 case 2: /* VLD3. */
17977 constraint (inst
.operands
[1].immisalign
,
17978 _("can't use alignment with this instruction"));
17979 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17980 _("bad list length"));
17981 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17982 inst
.instruction
|= 1 << 5;
17983 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17986 case 3: /* VLD4. */
17988 int align
= inst
.operands
[1].imm
>> 8;
17989 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17990 16, 64, 32, 64, 32, 128, -1);
17991 if (align_good
== FAIL
)
17993 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17994 _("bad list length"));
17995 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17996 inst
.instruction
|= 1 << 5;
17997 if (et
.size
== 32 && align
== 128)
17998 inst
.instruction
|= 0x3 << 6;
18000 inst
.instruction
|= neon_logbits (et
.size
) << 6;
18007 inst
.instruction
|= do_alignment
<< 4;
18010 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
18011 apart from bits [11:4]. */
18014 do_neon_ldx_stx (void)
18016 if (inst
.operands
[1].isreg
)
18017 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18019 switch (NEON_LANE (inst
.operands
[0].imm
))
18021 case NEON_INTERLEAVE_LANES
:
18022 NEON_ENCODE (INTERLV
, inst
);
18023 do_neon_ld_st_interleave ();
18026 case NEON_ALL_LANES
:
18027 NEON_ENCODE (DUP
, inst
);
18028 if (inst
.instruction
== N_INV
)
18030 first_error ("only loads support such operands");
18037 NEON_ENCODE (LANE
, inst
);
18038 do_neon_ld_st_lane ();
18041 /* L bit comes from bit mask. */
18042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18043 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
18046 if (inst
.operands
[1].postind
)
18048 int postreg
= inst
.operands
[1].imm
& 0xf;
18049 constraint (!inst
.operands
[1].immisreg
,
18050 _("post-index must be a register"));
18051 constraint (postreg
== 0xd || postreg
== 0xf,
18052 _("bad register for post-index"));
18053 inst
.instruction
|= postreg
;
18057 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
18058 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
18059 || inst
.relocs
[0].exp
.X_add_number
!= 0,
18062 if (inst
.operands
[1].writeback
)
18064 inst
.instruction
|= 0xd;
18067 inst
.instruction
|= 0xf;
18071 inst
.instruction
|= 0xf9000000;
18073 inst
.instruction
|= 0xf4000000;
18078 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
18080 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18081 D register operands. */
18082 if (neon_shape_class
[rs
] == SC_DOUBLE
)
18083 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18086 NEON_ENCODE (FPV8
, inst
);
18088 if (rs
== NS_FFF
|| rs
== NS_HHH
)
18090 do_vfp_sp_dyadic ();
18092 /* ARMv8.2 fp16 instruction. */
18094 do_scalar_fp16_v82_encode ();
18097 do_vfp_dp_rd_rn_rm ();
18100 inst
.instruction
|= 0x100;
18102 inst
.instruction
|= 0xf0000000;
18108 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18110 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
18111 first_error (_("invalid instruction shape"));
18117 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18119 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
18122 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
18125 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
18129 do_vrint_1 (enum neon_cvt_mode mode
)
18131 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
18132 struct neon_type_el et
;
18137 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18138 D register operands. */
18139 if (neon_shape_class
[rs
] == SC_DOUBLE
)
18140 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18143 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
18145 if (et
.type
!= NT_invtype
)
18147 /* VFP encodings. */
18148 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18149 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
18150 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18152 NEON_ENCODE (FPV8
, inst
);
18153 if (rs
== NS_FF
|| rs
== NS_HH
)
18154 do_vfp_sp_monadic ();
18156 do_vfp_dp_rd_rm ();
18160 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
18161 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
18162 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
18163 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
18164 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
18165 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
18166 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
18170 inst
.instruction
|= (rs
== NS_DD
) << 8;
18171 do_vfp_cond_or_thumb ();
18173 /* ARMv8.2 fp16 vrint instruction. */
18175 do_scalar_fp16_v82_encode ();
18179 /* Neon encodings (or something broken...). */
18181 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
18183 if (et
.type
== NT_invtype
)
18186 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18187 NEON_ENCODE (FLOAT
, inst
);
18189 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
18192 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18195 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18196 inst
.instruction
|= neon_quad (rs
) << 6;
18197 /* Mask off the original size bits and reencode them. */
18198 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
18199 | neon_logbits (et
.size
) << 18);
18203 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
18204 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
18205 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
18206 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
18207 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
18208 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
18209 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
18214 inst
.instruction
|= 0xfc000000;
18216 inst
.instruction
|= 0xf0000000;
18223 do_vrint_1 (neon_cvt_mode_x
);
18229 do_vrint_1 (neon_cvt_mode_z
);
18235 do_vrint_1 (neon_cvt_mode_r
);
18241 do_vrint_1 (neon_cvt_mode_a
);
18247 do_vrint_1 (neon_cvt_mode_n
);
18253 do_vrint_1 (neon_cvt_mode_p
);
18259 do_vrint_1 (neon_cvt_mode_m
);
18263 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
18265 unsigned regno
= NEON_SCALAR_REG (opnd
);
18266 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
18268 if (elsize
== 16 && elno
< 2 && regno
< 16)
18269 return regno
| (elno
<< 4);
18270 else if (elsize
== 32 && elno
== 0)
18273 first_error (_("scalar out of range"));
18280 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18282 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
18283 _("expression too complex"));
18284 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18285 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
18286 _("immediate out of range"));
18288 if (inst
.operands
[2].isscalar
)
18290 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
18291 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18292 N_KEY
| N_F16
| N_F32
).size
;
18293 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
18295 inst
.instruction
= 0xfe000800;
18296 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18297 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18298 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18299 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18300 inst
.instruction
|= LOW4 (m
);
18301 inst
.instruction
|= HI1 (m
) << 5;
18302 inst
.instruction
|= neon_quad (rs
) << 6;
18303 inst
.instruction
|= rot
<< 20;
18304 inst
.instruction
|= (size
== 32) << 23;
18308 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18309 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18310 N_KEY
| N_F16
| N_F32
).size
;
18311 neon_three_same (neon_quad (rs
), 0, -1);
18312 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
18313 inst
.instruction
|= 0xfc200800;
18314 inst
.instruction
|= rot
<< 23;
18315 inst
.instruction
|= (size
== 32) << 20;
18322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18324 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
18325 _("expression too complex"));
18326 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18327 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18328 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18329 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18330 N_KEY
| N_F16
| N_F32
).size
;
18331 neon_three_same (neon_quad (rs
), 0, -1);
18332 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
18333 inst
.instruction
|= 0xfc800800;
18334 inst
.instruction
|= (rot
== 270) << 24;
18335 inst
.instruction
|= (size
== 32) << 20;
18338 /* Dot Product instructions encoding support. */
18341 do_neon_dotproduct (int unsigned_p
)
18343 enum neon_shape rs
;
18344 unsigned scalar_oprd2
= 0;
18347 if (inst
.cond
!= COND_ALWAYS
)
18348 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
18349 "is UNPREDICTABLE"));
18351 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18354 /* Dot Product instructions are in three-same D/Q register format or the third
18355 operand can be a scalar index register. */
18356 if (inst
.operands
[2].isscalar
)
18358 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
18359 high8
= 0xfe000000;
18360 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18364 high8
= 0xfc000000;
18365 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18369 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
18371 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
18373 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
18374 Product instruction, so we pass 0 as the "ubit" parameter. And the
18375 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
18376 neon_three_same (neon_quad (rs
), 0, 32);
18378 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
18379 different NEON three-same encoding. */
18380 inst
.instruction
&= 0x00ffffff;
18381 inst
.instruction
|= high8
;
18382 /* Encode 'U' bit which indicates signedness. */
18383 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
18384 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
18385 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
18386 the instruction encoding. */
18387 if (inst
.operands
[2].isscalar
)
18389 inst
.instruction
&= 0xffffffd0;
18390 inst
.instruction
|= LOW4 (scalar_oprd2
);
18391 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
18395 /* Dot Product instructions for signed integer. */
18398 do_neon_dotproduct_s (void)
18400 return do_neon_dotproduct (0);
18403 /* Dot Product instructions for unsigned integer. */
18406 do_neon_dotproduct_u (void)
18408 return do_neon_dotproduct (1);
18411 /* Crypto v1 instructions. */
18413 do_crypto_2op_1 (unsigned elttype
, int op
)
18415 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18417 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
18423 NEON_ENCODE (INTEGER
, inst
);
18424 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18425 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18426 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18427 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18429 inst
.instruction
|= op
<< 6;
18432 inst
.instruction
|= 0xfc000000;
18434 inst
.instruction
|= 0xf0000000;
18438 do_crypto_3op_1 (int u
, int op
)
18440 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18442 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
18443 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
18448 NEON_ENCODE (INTEGER
, inst
);
18449 neon_three_same (1, u
, 8 << op
);
18455 do_crypto_2op_1 (N_8
, 0);
18461 do_crypto_2op_1 (N_8
, 1);
18467 do_crypto_2op_1 (N_8
, 2);
18473 do_crypto_2op_1 (N_8
, 3);
18479 do_crypto_3op_1 (0, 0);
18485 do_crypto_3op_1 (0, 1);
18491 do_crypto_3op_1 (0, 2);
18497 do_crypto_3op_1 (0, 3);
18503 do_crypto_3op_1 (1, 0);
18509 do_crypto_3op_1 (1, 1);
18513 do_sha256su1 (void)
18515 do_crypto_3op_1 (1, 2);
18521 do_crypto_2op_1 (N_32
, -1);
18527 do_crypto_2op_1 (N_32
, 0);
18531 do_sha256su0 (void)
18533 do_crypto_2op_1 (N_32
, 1);
18537 do_crc32_1 (unsigned int poly
, unsigned int sz
)
18539 unsigned int Rd
= inst
.operands
[0].reg
;
18540 unsigned int Rn
= inst
.operands
[1].reg
;
18541 unsigned int Rm
= inst
.operands
[2].reg
;
18543 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18544 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
18545 inst
.instruction
|= LOW4 (Rn
) << 16;
18546 inst
.instruction
|= LOW4 (Rm
);
18547 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
18548 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
18550 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
18551 as_warn (UNPRED_REG ("r15"));
18593 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18595 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
18596 do_vfp_sp_dp_cvt ();
18597 do_vfp_cond_or_thumb ();
18601 /* Overall per-instruction processing. */
18603 /* We need to be able to fix up arbitrary expressions in some statements.
18604 This is so that we can handle symbols that are an arbitrary distance from
18605 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
18606 which returns part of an address in a form which will be valid for
18607 a data instruction. We do this by pushing the expression into a symbol
18608 in the expr_section, and creating a fix for that. */
18611 fix_new_arm (fragS
* frag
,
18625 /* Create an absolute valued symbol, so we have something to
18626 refer to in the object file. Unfortunately for us, gas's
18627 generic expression parsing will already have folded out
18628 any use of .set foo/.type foo %function that may have
18629 been used to set type information of the target location,
18630 that's being specified symbolically. We have to presume
18631 the user knows what they are doing. */
18635 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
18637 symbol
= symbol_find_or_make (name
);
18638 S_SET_SEGMENT (symbol
, absolute_section
);
18639 symbol_set_frag (symbol
, &zero_address_frag
);
18640 S_SET_VALUE (symbol
, exp
->X_add_number
);
18641 exp
->X_op
= O_symbol
;
18642 exp
->X_add_symbol
= symbol
;
18643 exp
->X_add_number
= 0;
18649 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
18650 (enum bfd_reloc_code_real
) reloc
);
18654 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
18655 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
18659 /* Mark whether the fix is to a THUMB instruction, or an ARM
18661 new_fix
->tc_fix_data
= thumb_mode
;
18664 /* Create a frg for an instruction requiring relaxation. */
18666 output_relax_insn (void)
18672 /* The size of the instruction is unknown, so tie the debug info to the
18673 start of the instruction. */
18674 dwarf2_emit_insn (0);
18676 switch (inst
.relocs
[0].exp
.X_op
)
18679 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
18680 offset
= inst
.relocs
[0].exp
.X_add_number
;
18684 offset
= inst
.relocs
[0].exp
.X_add_number
;
18687 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
18691 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
18692 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
18693 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
18696 /* Write a 32-bit thumb instruction to buf. */
18698 put_thumb32_insn (char * buf
, unsigned long insn
)
18700 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
18701 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
18705 output_inst (const char * str
)
18711 as_bad ("%s -- `%s'", inst
.error
, str
);
18716 output_relax_insn ();
18719 if (inst
.size
== 0)
18722 to
= frag_more (inst
.size
);
18723 /* PR 9814: Record the thumb mode into the current frag so that we know
18724 what type of NOP padding to use, if necessary. We override any previous
18725 setting so that if the mode has changed then the NOPS that we use will
18726 match the encoding of the last instruction in the frag. */
18727 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18729 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18731 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18732 put_thumb32_insn (to
, inst
.instruction
);
18734 else if (inst
.size
> INSN_SIZE
)
18736 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18737 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18738 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18741 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18744 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
18746 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
18747 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18748 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
18749 inst
.relocs
[r
].type
);
18752 dwarf2_emit_insn (inst
.size
);
18756 output_it_inst (int cond
, int mask
, char * to
)
18758 unsigned long instruction
= 0xbf00;
18761 instruction
|= mask
;
18762 instruction
|= cond
<< 4;
18766 to
= frag_more (2);
18768 dwarf2_emit_insn (2);
18772 md_number_to_chars (to
, instruction
, 2);
18777 /* Tag values used in struct asm_opcode's tag field. */
18780 OT_unconditional
, /* Instruction cannot be conditionalized.
18781 The ARM condition field is still 0xE. */
18782 OT_unconditionalF
, /* Instruction cannot be conditionalized
18783 and carries 0xF in its ARM condition field. */
18784 OT_csuffix
, /* Instruction takes a conditional suffix. */
18785 OT_csuffixF
, /* Some forms of the instruction take a scalar
18786 conditional suffix, others place 0xF where the
18787 condition field would be, others take a vector
18788 conditional suffix. */
18789 OT_cinfix3
, /* Instruction takes a conditional infix,
18790 beginning at character index 3. (In
18791 unified mode, it becomes a suffix.) */
18792 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18793 tsts, cmps, cmns, and teqs. */
18794 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18795 character index 3, even in unified mode. Used for
18796 legacy instructions where suffix and infix forms
18797 may be ambiguous. */
18798 OT_csuf_or_in3
, /* Instruction takes either a conditional
18799 suffix or an infix at character index 3. */
18800 OT_odd_infix_unc
, /* This is the unconditional variant of an
18801 instruction that takes a conditional infix
18802 at an unusual position. In unified mode,
18803 this variant will accept a suffix. */
18804 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18805 are the conditional variants of instructions that
18806 take conditional infixes in unusual positions.
18807 The infix appears at character index
18808 (tag - OT_odd_infix_0). These are not accepted
18809 in unified mode. */
18812 /* Subroutine of md_assemble, responsible for looking up the primary
18813 opcode from the mnemonic the user wrote. STR points to the
18814 beginning of the mnemonic.
18816 This is not simply a hash table lookup, because of conditional
18817 variants. Most instructions have conditional variants, which are
18818 expressed with a _conditional affix_ to the mnemonic. If we were
18819 to encode each conditional variant as a literal string in the opcode
18820 table, it would have approximately 20,000 entries.
18822 Most mnemonics take this affix as a suffix, and in unified syntax,
18823 'most' is upgraded to 'all'. However, in the divided syntax, some
18824 instructions take the affix as an infix, notably the s-variants of
18825 the arithmetic instructions. Of those instructions, all but six
18826 have the infix appear after the third character of the mnemonic.
18828 Accordingly, the algorithm for looking up primary opcodes given
18831 1. Look up the identifier in the opcode table.
18832 If we find a match, go to step U.
18834 2. Look up the last two characters of the identifier in the
18835 conditions table. If we find a match, look up the first N-2
18836 characters of the identifier in the opcode table. If we
18837 find a match, go to step CE.
18839 3. Look up the fourth and fifth characters of the identifier in
18840 the conditions table. If we find a match, extract those
18841 characters from the identifier, and look up the remaining
18842 characters in the opcode table. If we find a match, go
18847 U. Examine the tag field of the opcode structure, in case this is
18848 one of the six instructions with its conditional infix in an
18849 unusual place. If it is, the tag tells us where to find the
18850 infix; look it up in the conditions table and set inst.cond
18851 accordingly. Otherwise, this is an unconditional instruction.
18852 Again set inst.cond accordingly. Return the opcode structure.
18854 CE. Examine the tag field to make sure this is an instruction that
18855 should receive a conditional suffix. If it is not, fail.
18856 Otherwise, set inst.cond from the suffix we already looked up,
18857 and return the opcode structure.
18859 CM. Examine the tag field to make sure this is an instruction that
18860 should receive a conditional infix after the third character.
18861 If it is not, fail. Otherwise, undo the edits to the current
18862 line of input and proceed as for case CE. */
18864 static const struct asm_opcode
*
18865 opcode_lookup (char **str
)
18869 const struct asm_opcode
*opcode
;
18870 const struct asm_cond
*cond
;
18873 /* Scan up to the end of the mnemonic, which must end in white space,
18874 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18875 for (base
= end
= *str
; *end
!= '\0'; end
++)
18876 if (*end
== ' ' || *end
== '.')
18882 /* Handle a possible width suffix and/or Neon type suffix. */
18887 /* The .w and .n suffixes are only valid if the unified syntax is in
18889 if (unified_syntax
&& end
[1] == 'w')
18891 else if (unified_syntax
&& end
[1] == 'n')
18896 inst
.vectype
.elems
= 0;
18898 *str
= end
+ offset
;
18900 if (end
[offset
] == '.')
18902 /* See if we have a Neon type suffix (possible in either unified or
18903 non-unified ARM syntax mode). */
18904 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18907 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18913 /* Look for unaffixed or special-case affixed mnemonic. */
18914 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18919 if (opcode
->tag
< OT_odd_infix_0
)
18921 inst
.cond
= COND_ALWAYS
;
18925 if (warn_on_deprecated
&& unified_syntax
)
18926 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18927 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18928 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18931 inst
.cond
= cond
->value
;
18934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18936 /* Cannot have a conditional suffix on a mnemonic of less than a character.
18938 if (end
- base
< 2)
18941 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
18942 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18944 /* If this opcode can not be vector predicated then don't accept it with a
18945 vector predication code. */
18946 if (opcode
&& !opcode
->mayBeVecPred
)
18949 if (!opcode
|| !cond
)
18951 /* Cannot have a conditional suffix on a mnemonic of less than two
18953 if (end
- base
< 3)
18956 /* Look for suffixed mnemonic. */
18958 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18959 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18963 if (opcode
&& cond
)
18966 switch (opcode
->tag
)
18968 case OT_cinfix3_legacy
:
18969 /* Ignore conditional suffixes matched on infix only mnemonics. */
18973 case OT_cinfix3_deprecated
:
18974 case OT_odd_infix_unc
:
18975 if (!unified_syntax
)
18977 /* Fall through. */
18981 case OT_csuf_or_in3
:
18982 inst
.cond
= cond
->value
;
18985 case OT_unconditional
:
18986 case OT_unconditionalF
:
18988 inst
.cond
= cond
->value
;
18991 /* Delayed diagnostic. */
18992 inst
.error
= BAD_COND
;
18993 inst
.cond
= COND_ALWAYS
;
19002 /* Cannot have a usual-position infix on a mnemonic of less than
19003 six characters (five would be a suffix). */
19004 if (end
- base
< 6)
19007 /* Look for infixed mnemonic in the usual position. */
19009 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
19013 memcpy (save
, affix
, 2);
19014 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
19015 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
19017 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
19018 memcpy (affix
, save
, 2);
19021 && (opcode
->tag
== OT_cinfix3
19022 || opcode
->tag
== OT_cinfix3_deprecated
19023 || opcode
->tag
== OT_csuf_or_in3
19024 || opcode
->tag
== OT_cinfix3_legacy
))
19027 if (warn_on_deprecated
&& unified_syntax
19028 && (opcode
->tag
== OT_cinfix3
19029 || opcode
->tag
== OT_cinfix3_deprecated
))
19030 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
19032 inst
.cond
= cond
->value
;
19039 /* This function generates an initial IT instruction, leaving its block
19040 virtually open for the new instructions. Eventually,
19041 the mask will be updated by now_pred_add_mask () each time
19042 a new instruction needs to be included in the IT block.
19043 Finally, the block is closed with close_automatic_it_block ().
19044 The block closure can be requested either from md_assemble (),
19045 a tencode (), or due to a label hook. */
19048 new_automatic_it_block (int cond
)
19050 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
19051 now_pred
.mask
= 0x18;
19052 now_pred
.cc
= cond
;
19053 now_pred
.block_length
= 1;
19054 mapping_state (MAP_THUMB
);
19055 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
19056 now_pred
.warn_deprecated
= FALSE
;
19057 now_pred
.insn_cond
= TRUE
;
19060 /* Close an automatic IT block.
19061 See comments in new_automatic_it_block (). */
19064 close_automatic_it_block (void)
19066 now_pred
.mask
= 0x10;
19067 now_pred
.block_length
= 0;
19070 /* Update the mask of the current automatically-generated IT
19071 instruction. See comments in new_automatic_it_block (). */
19074 now_pred_add_mask (int cond
)
19076 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
19077 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
19078 | ((bitvalue) << (nbit)))
19079 const int resulting_bit
= (cond
& 1);
19081 now_pred
.mask
&= 0xf;
19082 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
19084 (5 - now_pred
.block_length
));
19085 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
19087 ((5 - now_pred
.block_length
) - 1));
19088 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
19091 #undef SET_BIT_VALUE
19094 /* The IT blocks handling machinery is accessed through the these functions:
19095 it_fsm_pre_encode () from md_assemble ()
19096 set_pred_insn_type () optional, from the tencode functions
19097 set_pred_insn_type_last () ditto
19098 in_pred_block () ditto
19099 it_fsm_post_encode () from md_assemble ()
19100 force_automatic_it_block_close () from label handling functions
19103 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
19104 initializing the IT insn type with a generic initial value depending
19105 on the inst.condition.
19106 2) During the tencode function, two things may happen:
19107 a) The tencode function overrides the IT insn type by
19108 calling either set_pred_insn_type (type) or
19109 set_pred_insn_type_last ().
19110 b) The tencode function queries the IT block state by
19111 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
19113 Both set_pred_insn_type and in_pred_block run the internal FSM state
19114 handling function (handle_pred_state), because: a) setting the IT insn
19115 type may incur in an invalid state (exiting the function),
19116 and b) querying the state requires the FSM to be updated.
19117 Specifically we want to avoid creating an IT block for conditional
19118 branches, so it_fsm_pre_encode is actually a guess and we can't
19119 determine whether an IT block is required until the tencode () routine
19120 has decided what type of instruction this actually it.
19121 Because of this, if set_pred_insn_type and in_pred_block have to be
19122 used, set_pred_insn_type has to be called first.
19124 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
19125 that determines the insn IT type depending on the inst.cond code.
19126 When a tencode () routine encodes an instruction that can be
19127 either outside an IT block, or, in the case of being inside, has to be
19128 the last one, set_pred_insn_type_last () will determine the proper
19129 IT instruction type based on the inst.cond code. Otherwise,
19130 set_pred_insn_type can be called for overriding that logic or
19131 for covering other cases.
19133 Calling handle_pred_state () may not transition the IT block state to
19134 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
19135 still queried. Instead, if the FSM determines that the state should
19136 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
19137 after the tencode () function: that's what it_fsm_post_encode () does.
19139 Since in_pred_block () calls the state handling function to get an
19140 updated state, an error may occur (due to invalid insns combination).
19141 In that case, inst.error is set.
19142 Therefore, inst.error has to be checked after the execution of
19143 the tencode () routine.
19145 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
19146 any pending state change (if any) that didn't take place in
19147 handle_pred_state () as explained above. */
19150 it_fsm_pre_encode (void)
19152 if (inst
.cond
!= COND_ALWAYS
)
19153 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19155 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
19157 now_pred
.state_handled
= 0;
19160 /* IT state FSM handling function. */
19161 /* MVE instructions and non-MVE instructions are handled differently because of
19162 the introduction of VPT blocks.
19163 Specifications say that any non-MVE instruction inside a VPT block is
19164 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
19165 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
19166 few exceptions this will be handled at their respective handler functions.
19167 The error messages provided depending on the different combinations possible
19168 are described in the cases below:
19169 For 'most' MVE instructions:
19170 1) In an IT block, with an IT code: syntax error
19171 2) In an IT block, with a VPT code: error: must be in a VPT block
19172 3) In an IT block, with no code: warning: UNPREDICTABLE
19173 4) In a VPT block, with an IT code: syntax error
19174 5) In a VPT block, with a VPT code: OK!
19175 6) In a VPT block, with no code: error: missing code
19176 7) Outside a pred block, with an IT code: error: syntax error
19177 8) Outside a pred block, with a VPT code: error: should be in a VPT block
19178 9) Outside a pred block, with no code: OK!
19179 For non-MVE instructions:
19180 10) In an IT block, with an IT code: OK!
19181 11) In an IT block, with a VPT code: syntax error
19182 12) In an IT block, with no code: error: missing code
19183 13) In a VPT block, with an IT code: error: should be in an IT block
19184 14) In a VPT block, with a VPT code: syntax error
19185 15) In a VPT block, with no code: UNPREDICTABLE
19186 16) Outside a pred block, with an IT code: error: should be in an IT block
19187 17) Outside a pred block, with a VPT code: syntax error
19188 18) Outside a pred block, with no code: OK!
19193 handle_pred_state (void)
19195 now_pred
.state_handled
= 1;
19196 now_pred
.insn_cond
= FALSE
;
19198 switch (now_pred
.state
)
19200 case OUTSIDE_PRED_BLOCK
:
19201 switch (inst
.pred_insn_type
)
19203 case MVE_OUTSIDE_PRED_INSN
:
19204 if (inst
.cond
< COND_ALWAYS
)
19206 /* Case 7: Outside a pred block, with an IT code: error: syntax
19208 inst
.error
= BAD_SYNTAX
;
19211 /* Case 9: Outside a pred block, with no code: OK! */
19213 case OUTSIDE_PRED_INSN
:
19214 if (inst
.cond
> COND_ALWAYS
)
19216 /* Case 17: Outside a pred block, with a VPT code: syntax error.
19218 inst
.error
= BAD_SYNTAX
;
19221 /* Case 18: Outside a pred block, with no code: OK! */
19224 case INSIDE_VPT_INSN
:
19225 /* Case 8: Outside a pred block, with a VPT code: error: should be in
19227 inst
.error
= BAD_OUT_VPT
;
19230 case INSIDE_IT_INSN
:
19231 case INSIDE_IT_LAST_INSN
:
19232 if (inst
.cond
< COND_ALWAYS
)
19234 /* Case 16: Outside a pred block, with an IT code: error: should
19235 be in an IT block. */
19236 if (thumb_mode
== 0)
19239 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
19240 as_tsktsk (_("Warning: conditional outside an IT block"\
19245 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
19246 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
19248 /* Automatically generate the IT instruction. */
19249 new_automatic_it_block (inst
.cond
);
19250 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
19251 close_automatic_it_block ();
19255 inst
.error
= BAD_OUT_IT
;
19261 else if (inst
.cond
> COND_ALWAYS
)
19263 /* Case 17: Outside a pred block, with a VPT code: syntax error.
19265 inst
.error
= BAD_SYNTAX
;
19270 case IF_INSIDE_IT_LAST_INSN
:
19271 case NEUTRAL_IT_INSN
:
19275 if (inst
.cond
!= COND_ALWAYS
)
19276 first_error (BAD_SYNTAX
);
19277 now_pred
.state
= MANUAL_PRED_BLOCK
;
19278 now_pred
.block_length
= 0;
19279 now_pred
.type
= VECTOR_PRED
;
19283 now_pred
.state
= MANUAL_PRED_BLOCK
;
19284 now_pred
.block_length
= 0;
19285 now_pred
.type
= SCALAR_PRED
;
19290 case AUTOMATIC_PRED_BLOCK
:
19291 /* Three things may happen now:
19292 a) We should increment current it block size;
19293 b) We should close current it block (closing insn or 4 insns);
19294 c) We should close current it block and start a new one (due
19295 to incompatible conditions or
19296 4 insns-length block reached). */
19298 switch (inst
.pred_insn_type
)
19300 case INSIDE_VPT_INSN
:
19302 case MVE_OUTSIDE_PRED_INSN
:
19304 case OUTSIDE_PRED_INSN
:
19305 /* The closure of the block shall happen immediately,
19306 so any in_pred_block () call reports the block as closed. */
19307 force_automatic_it_block_close ();
19310 case INSIDE_IT_INSN
:
19311 case INSIDE_IT_LAST_INSN
:
19312 case IF_INSIDE_IT_LAST_INSN
:
19313 now_pred
.block_length
++;
19315 if (now_pred
.block_length
> 4
19316 || !now_pred_compatible (inst
.cond
))
19318 force_automatic_it_block_close ();
19319 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
19320 new_automatic_it_block (inst
.cond
);
19324 now_pred
.insn_cond
= TRUE
;
19325 now_pred_add_mask (inst
.cond
);
19328 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
19329 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
19330 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
19331 close_automatic_it_block ();
19334 case NEUTRAL_IT_INSN
:
19335 now_pred
.block_length
++;
19336 now_pred
.insn_cond
= TRUE
;
19338 if (now_pred
.block_length
> 4)
19339 force_automatic_it_block_close ();
19341 now_pred_add_mask (now_pred
.cc
& 1);
19345 close_automatic_it_block ();
19346 now_pred
.state
= MANUAL_PRED_BLOCK
;
19351 case MANUAL_PRED_BLOCK
:
19354 if (now_pred
.type
== SCALAR_PRED
)
19356 /* Check conditional suffixes. */
19357 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
19358 now_pred
.mask
<<= 1;
19359 now_pred
.mask
&= 0x1f;
19360 is_last
= (now_pred
.mask
== 0x10);
19364 now_pred
.cc
^= (now_pred
.mask
>> 4);
19365 cond
= now_pred
.cc
+ 0xf;
19366 now_pred
.mask
<<= 1;
19367 now_pred
.mask
&= 0x1f;
19368 is_last
= now_pred
.mask
== 0x10;
19370 now_pred
.insn_cond
= TRUE
;
19372 switch (inst
.pred_insn_type
)
19374 case OUTSIDE_PRED_INSN
:
19375 if (now_pred
.type
== SCALAR_PRED
)
19377 if (inst
.cond
== COND_ALWAYS
)
19379 /* Case 12: In an IT block, with no code: error: missing
19381 inst
.error
= BAD_NOT_IT
;
19384 else if (inst
.cond
> COND_ALWAYS
)
19386 /* Case 11: In an IT block, with a VPT code: syntax error.
19388 inst
.error
= BAD_SYNTAX
;
19391 else if (thumb_mode
)
19393 /* This is for some special cases where a non-MVE
19394 instruction is not allowed in an IT block, such as cbz,
19395 but are put into one with a condition code.
19396 You could argue this should be a syntax error, but we
19397 gave the 'not allowed in IT block' diagnostic in the
19398 past so we will keep doing so. */
19399 inst
.error
= BAD_NOT_IT
;
19406 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
19407 as_tsktsk (MVE_NOT_VPT
);
19410 case MVE_OUTSIDE_PRED_INSN
:
19411 if (now_pred
.type
== SCALAR_PRED
)
19413 if (inst
.cond
== COND_ALWAYS
)
19415 /* Case 3: In an IT block, with no code: warning:
19417 as_tsktsk (MVE_NOT_IT
);
19420 else if (inst
.cond
< COND_ALWAYS
)
19422 /* Case 1: In an IT block, with an IT code: syntax error.
19424 inst
.error
= BAD_SYNTAX
;
19432 if (inst
.cond
< COND_ALWAYS
)
19434 /* Case 4: In a VPT block, with an IT code: syntax error.
19436 inst
.error
= BAD_SYNTAX
;
19439 else if (inst
.cond
== COND_ALWAYS
)
19441 /* Case 6: In a VPT block, with no code: error: missing
19443 inst
.error
= BAD_NOT_VPT
;
19451 case INSIDE_IT_INSN
:
19452 if (inst
.cond
> COND_ALWAYS
)
19454 /* Case 11: In an IT block, with a VPT code: syntax error. */
19455 /* Case 14: In a VPT block, with a VPT code: syntax error. */
19456 inst
.error
= BAD_SYNTAX
;
19459 else if (now_pred
.type
== SCALAR_PRED
)
19461 /* Case 10: In an IT block, with an IT code: OK! */
19462 if (cond
!= inst
.cond
)
19464 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
19471 /* Case 13: In a VPT block, with an IT code: error: should be
19473 inst
.error
= BAD_OUT_IT
;
19478 case INSIDE_VPT_INSN
:
19479 if (now_pred
.type
== SCALAR_PRED
)
19481 /* Case 2: In an IT block, with a VPT code: error: must be in a
19483 inst
.error
= BAD_OUT_VPT
;
19486 /* Case 5: In a VPT block, with a VPT code: OK! */
19487 else if (cond
!= inst
.cond
)
19489 inst
.error
= BAD_VPT_COND
;
19493 case INSIDE_IT_LAST_INSN
:
19494 case IF_INSIDE_IT_LAST_INSN
:
19495 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
19497 /* Case 4: In a VPT block, with an IT code: syntax error. */
19498 /* Case 11: In an IT block, with a VPT code: syntax error. */
19499 inst
.error
= BAD_SYNTAX
;
19502 else if (cond
!= inst
.cond
)
19504 inst
.error
= BAD_IT_COND
;
19509 inst
.error
= BAD_BRANCH
;
19514 case NEUTRAL_IT_INSN
:
19515 /* The BKPT instruction is unconditional even in a IT or VPT
19520 if (now_pred
.type
== SCALAR_PRED
)
19522 inst
.error
= BAD_IT_IT
;
19525 /* fall through. */
19527 if (inst
.cond
== COND_ALWAYS
)
19529 /* Executing a VPT/VPST instruction inside an IT block or a
19530 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
19532 if (now_pred
.type
== SCALAR_PRED
)
19533 as_tsktsk (MVE_NOT_IT
);
19535 as_tsktsk (MVE_NOT_VPT
);
19540 /* VPT/VPST do not accept condition codes. */
19541 inst
.error
= BAD_SYNTAX
;
19552 struct depr_insn_mask
19554 unsigned long pattern
;
19555 unsigned long mask
;
19556 const char* description
;
19559 /* List of 16-bit instruction patterns deprecated in an IT block in
19561 static const struct depr_insn_mask depr_it_insns
[] = {
19562 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
19563 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
19564 { 0xa000, 0xb800, N_("ADR") },
19565 { 0x4800, 0xf800, N_("Literal loads") },
19566 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
19567 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
19568 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
19569 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
19570 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
19575 it_fsm_post_encode (void)
19579 if (!now_pred
.state_handled
)
19580 handle_pred_state ();
19582 if (now_pred
.insn_cond
19583 && !now_pred
.warn_deprecated
19584 && warn_on_deprecated
19585 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
19586 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
19588 if (inst
.instruction
>= 0x10000)
19590 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
19591 "performance deprecated in ARMv8-A and ARMv8-R"));
19592 now_pred
.warn_deprecated
= TRUE
;
19596 const struct depr_insn_mask
*p
= depr_it_insns
;
19598 while (p
->mask
!= 0)
19600 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
19602 as_tsktsk (_("IT blocks containing 16-bit Thumb "
19603 "instructions of the following class are "
19604 "performance deprecated in ARMv8-A and "
19605 "ARMv8-R: %s"), p
->description
);
19606 now_pred
.warn_deprecated
= TRUE
;
19614 if (now_pred
.block_length
> 1)
19616 as_tsktsk (_("IT blocks containing more than one conditional "
19617 "instruction are performance deprecated in ARMv8-A and "
19619 now_pred
.warn_deprecated
= TRUE
;
19623 is_last
= (now_pred
.mask
== 0x10);
19626 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
19632 force_automatic_it_block_close (void)
19634 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
19636 close_automatic_it_block ();
19637 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
19643 in_pred_block (void)
19645 if (!now_pred
.state_handled
)
19646 handle_pred_state ();
19648 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
19651 /* Whether OPCODE only has T32 encoding. Since this function is only used by
19652 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
19653 here, hence the "known" in the function name. */
19656 known_t32_only_insn (const struct asm_opcode
*opcode
)
19658 /* Original Thumb-1 wide instruction. */
19659 if (opcode
->tencode
== do_t_blx
19660 || opcode
->tencode
== do_t_branch23
19661 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
19662 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
19665 /* Wide-only instruction added to ARMv8-M Baseline. */
19666 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
19667 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
19668 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
19669 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
19675 /* Whether wide instruction variant can be used if available for a valid OPCODE
19679 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
19681 if (known_t32_only_insn (opcode
))
19684 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
19685 of variant T3 of B.W is checked in do_t_branch. */
19686 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
19687 && opcode
->tencode
== do_t_branch
)
19690 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
19691 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
19692 && opcode
->tencode
== do_t_mov_cmp
19693 /* Make sure CMP instruction is not affected. */
19694 && opcode
->aencode
== do_mov
)
19697 /* Wide instruction variants of all instructions with narrow *and* wide
19698 variants become available with ARMv6t2. Other opcodes are either
19699 narrow-only or wide-only and are thus available if OPCODE is valid. */
19700 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
19703 /* OPCODE with narrow only instruction variant or wide variant not
19709 md_assemble (char *str
)
19712 const struct asm_opcode
* opcode
;
19714 /* Align the previous label if needed. */
19715 if (last_label_seen
!= NULL
)
19717 symbol_set_frag (last_label_seen
, frag_now
);
19718 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
19719 S_SET_SEGMENT (last_label_seen
, now_seg
);
19722 memset (&inst
, '\0', sizeof (inst
));
19724 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
19725 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
19727 opcode
= opcode_lookup (&p
);
19730 /* It wasn't an instruction, but it might be a register alias of
19731 the form alias .req reg, or a Neon .dn/.qn directive. */
19732 if (! create_register_alias (str
, p
)
19733 && ! create_neon_reg_alias (str
, p
))
19734 as_bad (_("bad instruction `%s'"), str
);
19739 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
19740 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
19742 /* The value which unconditional instructions should have in place of the
19743 condition field. */
19744 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
19748 arm_feature_set variant
;
19750 variant
= cpu_variant
;
19751 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
19752 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
19753 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
19754 /* Check that this instruction is supported for this CPU. */
19755 if (!opcode
->tvariant
19756 || (thumb_mode
== 1
19757 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
19759 if (opcode
->tencode
== do_t_swi
)
19760 as_bad (_("SVC is not permitted on this architecture"));
19762 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
19765 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
19766 && opcode
->tencode
!= do_t_branch
)
19768 as_bad (_("Thumb does not support conditional execution"));
19772 /* Two things are addressed here:
19773 1) Implicit require narrow instructions on Thumb-1.
19774 This avoids relaxation accidentally introducing Thumb-2
19776 2) Reject wide instructions in non Thumb-2 cores.
19778 Only instructions with narrow and wide variants need to be handled
19779 but selecting all non wide-only instructions is easier. */
19780 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
19781 && !t32_insn_ok (variant
, opcode
))
19783 if (inst
.size_req
== 0)
19785 else if (inst
.size_req
== 4)
19787 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
19788 as_bad (_("selected processor does not support 32bit wide "
19789 "variant of instruction `%s'"), str
);
19791 as_bad (_("selected processor does not support `%s' in "
19792 "Thumb-2 mode"), str
);
19797 inst
.instruction
= opcode
->tvalue
;
19799 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
19801 /* Prepare the pred_insn_type for those encodings that don't set
19803 it_fsm_pre_encode ();
19805 opcode
->tencode ();
19807 it_fsm_post_encode ();
19810 if (!(inst
.error
|| inst
.relax
))
19812 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
19813 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
19814 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
19816 as_bad (_("cannot honor width suffix -- `%s'"), str
);
19821 /* Something has gone badly wrong if we try to relax a fixed size
19823 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
19825 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19826 *opcode
->tvariant
);
19827 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
19828 set those bits when Thumb-2 32-bit instructions are seen. The impact
19829 of relaxable instructions will be considered later after we finish all
19831 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
19832 variant
= arm_arch_none
;
19834 variant
= cpu_variant
;
19835 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
19836 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
19839 check_neon_suffixes
;
19843 mapping_state (MAP_THUMB
);
19846 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19850 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
19851 is_bx
= (opcode
->aencode
== do_bx
);
19853 /* Check that this instruction is supported for this CPU. */
19854 if (!(is_bx
&& fix_v4bx
)
19855 && !(opcode
->avariant
&&
19856 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
19858 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
19863 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
19867 inst
.instruction
= opcode
->avalue
;
19868 if (opcode
->tag
== OT_unconditionalF
)
19869 inst
.instruction
|= 0xFU
<< 28;
19871 inst
.instruction
|= inst
.cond
<< 28;
19872 inst
.size
= INSN_SIZE
;
19873 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
19875 it_fsm_pre_encode ();
19876 opcode
->aencode ();
19877 it_fsm_post_encode ();
19879 /* Arm mode bx is marked as both v4T and v5 because it's still required
19880 on a hypothetical non-thumb v5 core. */
19882 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
19884 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
19885 *opcode
->avariant
);
19887 check_neon_suffixes
;
19891 mapping_state (MAP_ARM
);
19896 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
19904 check_pred_blocks_finished (void)
19909 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
19910 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
19911 == MANUAL_PRED_BLOCK
)
19913 if (now_pred
.type
== SCALAR_PRED
)
19914 as_warn (_("section '%s' finished with an open IT block."),
19917 as_warn (_("section '%s' finished with an open VPT/VPST block."),
19921 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
19923 if (now_pred
.type
== SCALAR_PRED
)
19924 as_warn (_("file finished with an open IT block."));
19926 as_warn (_("file finished with an open VPT/VPST block."));
19931 /* Various frobbings of labels and their addresses. */
19934 arm_start_line_hook (void)
19936 last_label_seen
= NULL
;
19940 arm_frob_label (symbolS
* sym
)
19942 last_label_seen
= sym
;
19944 ARM_SET_THUMB (sym
, thumb_mode
);
19946 #if defined OBJ_COFF || defined OBJ_ELF
19947 ARM_SET_INTERWORK (sym
, support_interwork
);
19950 force_automatic_it_block_close ();
19952 /* Note - do not allow local symbols (.Lxxx) to be labelled
19953 as Thumb functions. This is because these labels, whilst
19954 they exist inside Thumb code, are not the entry points for
19955 possible ARM->Thumb calls. Also, these labels can be used
19956 as part of a computed goto or switch statement. eg gcc
19957 can generate code that looks like this:
19959 ldr r2, [pc, .Laaa]
19969 The first instruction loads the address of the jump table.
19970 The second instruction converts a table index into a byte offset.
19971 The third instruction gets the jump address out of the table.
19972 The fourth instruction performs the jump.
19974 If the address stored at .Laaa is that of a symbol which has the
19975 Thumb_Func bit set, then the linker will arrange for this address
19976 to have the bottom bit set, which in turn would mean that the
19977 address computation performed by the third instruction would end
19978 up with the bottom bit set. Since the ARM is capable of unaligned
19979 word loads, the instruction would then load the incorrect address
19980 out of the jump table, and chaos would ensue. */
19981 if (label_is_thumb_function_name
19982 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
19983 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
19985 /* When the address of a Thumb function is taken the bottom
19986 bit of that address should be set. This will allow
19987 interworking between Arm and Thumb functions to work
19990 THUMB_SET_FUNC (sym
, 1);
19992 label_is_thumb_function_name
= FALSE
;
19995 dwarf2_emit_label (sym
);
19999 arm_data_in_code (void)
20001 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
20003 *input_line_pointer
= '/';
20004 input_line_pointer
+= 5;
20005 *input_line_pointer
= 0;
20013 arm_canonicalize_symbol_name (char * name
)
20017 if (thumb_mode
&& (len
= strlen (name
)) > 5
20018 && streq (name
+ len
- 5, "/data"))
20019 *(name
+ len
- 5) = 0;
20024 /* Table of all register names defined by default. The user can
20025 define additional names with .req. Note that all register names
20026 should appear in both upper and lowercase variants. Some registers
20027 also have mixed-case names. */
20029 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
20030 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
20031 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
20032 #define REGSET(p,t) \
20033 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
20034 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
20035 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
20036 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
20037 #define REGSETH(p,t) \
20038 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
20039 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
20040 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
20041 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
20042 #define REGSET2(p,t) \
20043 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
20044 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
20045 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
20046 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
20047 #define SPLRBANK(base,bank,t) \
20048 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
20049 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
20050 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
20051 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
20052 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
20053 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
20055 static const struct reg_entry reg_names
[] =
20057 /* ARM integer registers. */
20058 REGSET(r
, RN
), REGSET(R
, RN
),
20060 /* ATPCS synonyms. */
20061 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
20062 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
20063 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
20065 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
20066 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
20067 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
20069 /* Well-known aliases. */
20070 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
20071 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
20073 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
20074 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
20076 /* Coprocessor numbers. */
20077 REGSET(p
, CP
), REGSET(P
, CP
),
20079 /* Coprocessor register numbers. The "cr" variants are for backward
20081 REGSET(c
, CN
), REGSET(C
, CN
),
20082 REGSET(cr
, CN
), REGSET(CR
, CN
),
20084 /* ARM banked registers. */
20085 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
20086 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
20087 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
20088 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
20089 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
20090 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
20091 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
20093 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
20094 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
20095 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
20096 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
20097 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
20098 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
20099 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
20100 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
20102 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
20103 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
20104 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
20105 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
20106 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
20107 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
20108 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
20109 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
20110 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
20112 /* FPA registers. */
20113 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
20114 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
20116 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
20117 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
20119 /* VFP SP registers. */
20120 REGSET(s
,VFS
), REGSET(S
,VFS
),
20121 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
20123 /* VFP DP Registers. */
20124 REGSET(d
,VFD
), REGSET(D
,VFD
),
20125 /* Extra Neon DP registers. */
20126 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
20128 /* Neon QP registers. */
20129 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
20131 /* VFP control registers. */
20132 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
20133 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
20134 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
20135 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
20136 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
20137 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
20138 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
20140 /* Maverick DSP coprocessor registers. */
20141 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
20142 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
20144 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
20145 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
20146 REGDEF(dspsc
,0,DSPSC
),
20148 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
20149 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
20150 REGDEF(DSPSC
,0,DSPSC
),
20152 /* iWMMXt data registers - p0, c0-15. */
20153 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
20155 /* iWMMXt control registers - p1, c0-3. */
20156 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
20157 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
20158 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
20159 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
20161 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
20162 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
20163 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
20164 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
20165 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
20167 /* XScale accumulator registers. */
20168 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
20174 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
20175 within psr_required_here. */
20176 static const struct asm_psr psrs
[] =
20178 /* Backward compatibility notation. Note that "all" is no longer
20179 truly all possible PSR bits. */
20180 {"all", PSR_c
| PSR_f
},
20184 /* Individual flags. */
20190 /* Combinations of flags. */
20191 {"fs", PSR_f
| PSR_s
},
20192 {"fx", PSR_f
| PSR_x
},
20193 {"fc", PSR_f
| PSR_c
},
20194 {"sf", PSR_s
| PSR_f
},
20195 {"sx", PSR_s
| PSR_x
},
20196 {"sc", PSR_s
| PSR_c
},
20197 {"xf", PSR_x
| PSR_f
},
20198 {"xs", PSR_x
| PSR_s
},
20199 {"xc", PSR_x
| PSR_c
},
20200 {"cf", PSR_c
| PSR_f
},
20201 {"cs", PSR_c
| PSR_s
},
20202 {"cx", PSR_c
| PSR_x
},
20203 {"fsx", PSR_f
| PSR_s
| PSR_x
},
20204 {"fsc", PSR_f
| PSR_s
| PSR_c
},
20205 {"fxs", PSR_f
| PSR_x
| PSR_s
},
20206 {"fxc", PSR_f
| PSR_x
| PSR_c
},
20207 {"fcs", PSR_f
| PSR_c
| PSR_s
},
20208 {"fcx", PSR_f
| PSR_c
| PSR_x
},
20209 {"sfx", PSR_s
| PSR_f
| PSR_x
},
20210 {"sfc", PSR_s
| PSR_f
| PSR_c
},
20211 {"sxf", PSR_s
| PSR_x
| PSR_f
},
20212 {"sxc", PSR_s
| PSR_x
| PSR_c
},
20213 {"scf", PSR_s
| PSR_c
| PSR_f
},
20214 {"scx", PSR_s
| PSR_c
| PSR_x
},
20215 {"xfs", PSR_x
| PSR_f
| PSR_s
},
20216 {"xfc", PSR_x
| PSR_f
| PSR_c
},
20217 {"xsf", PSR_x
| PSR_s
| PSR_f
},
20218 {"xsc", PSR_x
| PSR_s
| PSR_c
},
20219 {"xcf", PSR_x
| PSR_c
| PSR_f
},
20220 {"xcs", PSR_x
| PSR_c
| PSR_s
},
20221 {"cfs", PSR_c
| PSR_f
| PSR_s
},
20222 {"cfx", PSR_c
| PSR_f
| PSR_x
},
20223 {"csf", PSR_c
| PSR_s
| PSR_f
},
20224 {"csx", PSR_c
| PSR_s
| PSR_x
},
20225 {"cxf", PSR_c
| PSR_x
| PSR_f
},
20226 {"cxs", PSR_c
| PSR_x
| PSR_s
},
20227 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
20228 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
20229 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
20230 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
20231 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
20232 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
20233 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
20234 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
20235 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
20236 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
20237 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
20238 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
20239 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
20240 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
20241 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
20242 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
20243 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
20244 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
20245 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
20246 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
20247 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
20248 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
20249 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
20250 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
20253 /* Table of V7M psr names. */
20254 static const struct asm_psr v7m_psrs
[] =
20256 {"apsr", 0x0 }, {"APSR", 0x0 },
20257 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
20258 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
20259 {"psr", 0x3 }, {"PSR", 0x3 },
20260 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
20261 {"ipsr", 0x5 }, {"IPSR", 0x5 },
20262 {"epsr", 0x6 }, {"EPSR", 0x6 },
20263 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
20264 {"msp", 0x8 }, {"MSP", 0x8 },
20265 {"psp", 0x9 }, {"PSP", 0x9 },
20266 {"msplim", 0xa }, {"MSPLIM", 0xa },
20267 {"psplim", 0xb }, {"PSPLIM", 0xb },
20268 {"primask", 0x10}, {"PRIMASK", 0x10},
20269 {"basepri", 0x11}, {"BASEPRI", 0x11},
20270 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
20271 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
20272 {"control", 0x14}, {"CONTROL", 0x14},
20273 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
20274 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
20275 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
20276 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
20277 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
20278 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
20279 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
20280 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
20281 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
20284 /* Table of all shift-in-operand names. */
20285 static const struct asm_shift_name shift_names
[] =
20287 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
20288 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
20289 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
20290 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
20291 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
20292 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
20295 /* Table of all explicit relocation names. */
20297 static struct reloc_entry reloc_names
[] =
20299 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
20300 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
20301 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
20302 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
20303 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
20304 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
20305 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
20306 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
20307 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
20308 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
20309 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
20310 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
20311 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
20312 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
20313 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
20314 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
20315 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
20316 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
20317 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
20318 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
20319 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
20320 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
20321 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
20322 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
20323 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
20324 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
20325 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
20329 /* Table of all conditional affixes. */
20330 static const struct asm_cond conds
[] =
20334 {"cs", 0x2}, {"hs", 0x2},
20335 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
20348 static const struct asm_cond vconds
[] =
20354 #define UL_BARRIER(L,U,CODE,FEAT) \
20355 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
20356 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
20358 static struct asm_barrier_opt barrier_opt_names
[] =
20360 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
20361 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
20362 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
20363 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
20364 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
20365 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
20366 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
20367 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
20368 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
20369 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
20370 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
20371 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
20372 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
20373 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
20374 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
20375 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
20380 /* Table of ARM-format instructions. */
20382 /* Macros for gluing together operand strings. N.B. In all cases
20383 other than OPS0, the trailing OP_stop comes from default
20384 zero-initialization of the unspecified elements of the array. */
20385 #define OPS0() { OP_stop, }
20386 #define OPS1(a) { OP_##a, }
20387 #define OPS2(a,b) { OP_##a,OP_##b, }
20388 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
20389 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
20390 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
20391 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
20393 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
20394 This is useful when mixing operands for ARM and THUMB, i.e. using the
20395 MIX_ARM_THUMB_OPERANDS macro.
20396 In order to use these macros, prefix the number of operands with _
20398 #define OPS_1(a) { a, }
20399 #define OPS_2(a,b) { a,b, }
20400 #define OPS_3(a,b,c) { a,b,c, }
20401 #define OPS_4(a,b,c,d) { a,b,c,d, }
20402 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
20403 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
20405 /* These macros abstract out the exact format of the mnemonic table and
20406 save some repeated characters. */
20408 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
20409 #define TxCE(mnem, op, top, nops, ops, ae, te) \
20410 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
20411 THUMB_VARIANT, do_##ae, do_##te, 0 }
20413 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
20414 a T_MNEM_xyz enumerator. */
20415 #define TCE(mnem, aop, top, nops, ops, ae, te) \
20416 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
20417 #define tCE(mnem, aop, top, nops, ops, ae, te) \
20418 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
20420 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
20421 infix after the third character. */
20422 #define TxC3(mnem, op, top, nops, ops, ae, te) \
20423 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
20424 THUMB_VARIANT, do_##ae, do_##te, 0 }
20425 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
20426 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
20427 THUMB_VARIANT, do_##ae, do_##te, 0 }
20428 #define TC3(mnem, aop, top, nops, ops, ae, te) \
20429 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
20430 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
20431 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
20432 #define tC3(mnem, aop, top, nops, ops, ae, te) \
20433 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
20434 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
20435 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
20437 /* Mnemonic that cannot be conditionalized. The ARM condition-code
20438 field is still 0xE. Many of the Thumb variants can be executed
20439 conditionally, so this is checked separately. */
20440 #define TUE(mnem, op, top, nops, ops, ae, te) \
20441 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
20442 THUMB_VARIANT, do_##ae, do_##te, 0 }
20444 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
20445 Used by mnemonics that have very minimal differences in the encoding for
20446 ARM and Thumb variants and can be handled in a common function. */
20447 #define TUEc(mnem, op, top, nops, ops, en) \
20448 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
20449 THUMB_VARIANT, do_##en, do_##en, 0 }
20451 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
20452 condition code field. */
20453 #define TUF(mnem, op, top, nops, ops, ae, te) \
20454 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
20455 THUMB_VARIANT, do_##ae, do_##te, 0 }
20457 /* ARM-only variants of all the above. */
20458 #define CE(mnem, op, nops, ops, ae) \
20459 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20461 #define C3(mnem, op, nops, ops, ae) \
20462 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20464 /* Thumb-only variants of TCE and TUE. */
20465 #define ToC(mnem, top, nops, ops, te) \
20466 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
20469 #define ToU(mnem, top, nops, ops, te) \
20470 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
20473 /* T_MNEM_xyz enumerator variants of ToC. */
20474 #define toC(mnem, top, nops, ops, te) \
20475 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
20478 /* T_MNEM_xyz enumerator variants of ToU. */
20479 #define toU(mnem, top, nops, ops, te) \
20480 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
20483 /* Legacy mnemonics that always have conditional infix after the third
20485 #define CL(mnem, op, nops, ops, ae) \
20486 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
20487 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20489 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
20490 #define cCE(mnem, op, nops, ops, ae) \
20491 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
20493 /* Legacy coprocessor instructions where conditional infix and conditional
20494 suffix are ambiguous. For consistency this includes all FPA instructions,
20495 not just the potentially ambiguous ones. */
20496 #define cCL(mnem, op, nops, ops, ae) \
20497 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
20498 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
20500 /* Coprocessor, takes either a suffix or a position-3 infix
20501 (for an FPA corner case). */
20502 #define C3E(mnem, op, nops, ops, ae) \
20503 { mnem, OPS##nops ops, OT_csuf_or_in3, \
20504 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
20506 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
20507 { m1 #m2 m3, OPS##nops ops, \
20508 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
20509 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20511 #define CM(m1, m2, op, nops, ops, ae) \
20512 xCM_ (m1, , m2, op, nops, ops, ae), \
20513 xCM_ (m1, eq, m2, op, nops, ops, ae), \
20514 xCM_ (m1, ne, m2, op, nops, ops, ae), \
20515 xCM_ (m1, cs, m2, op, nops, ops, ae), \
20516 xCM_ (m1, hs, m2, op, nops, ops, ae), \
20517 xCM_ (m1, cc, m2, op, nops, ops, ae), \
20518 xCM_ (m1, ul, m2, op, nops, ops, ae), \
20519 xCM_ (m1, lo, m2, op, nops, ops, ae), \
20520 xCM_ (m1, mi, m2, op, nops, ops, ae), \
20521 xCM_ (m1, pl, m2, op, nops, ops, ae), \
20522 xCM_ (m1, vs, m2, op, nops, ops, ae), \
20523 xCM_ (m1, vc, m2, op, nops, ops, ae), \
20524 xCM_ (m1, hi, m2, op, nops, ops, ae), \
20525 xCM_ (m1, ls, m2, op, nops, ops, ae), \
20526 xCM_ (m1, ge, m2, op, nops, ops, ae), \
20527 xCM_ (m1, lt, m2, op, nops, ops, ae), \
20528 xCM_ (m1, gt, m2, op, nops, ops, ae), \
20529 xCM_ (m1, le, m2, op, nops, ops, ae), \
20530 xCM_ (m1, al, m2, op, nops, ops, ae)
20532 #define UE(mnem, op, nops, ops, ae) \
20533 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20535 #define UF(mnem, op, nops, ops, ae) \
20536 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
20538 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
20539 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
20540 use the same encoding function for each. */
20541 #define NUF(mnem, op, nops, ops, enc) \
20542 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
20543 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
20545 /* Neon data processing, version which indirects through neon_enc_tab for
20546 the various overloaded versions of opcodes. */
20547 #define nUF(mnem, op, nops, ops, enc) \
20548 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
20549 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
20551 /* Neon insn with conditional suffix for the ARM version, non-overloaded
20553 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
20554 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
20555 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
20557 #define NCE(mnem, op, nops, ops, enc) \
20558 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
20560 #define NCEF(mnem, op, nops, ops, enc) \
20561 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
20563 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
20564 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
20565 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
20566 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
20568 #define nCE(mnem, op, nops, ops, enc) \
20569 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
20571 #define nCEF(mnem, op, nops, ops, enc) \
20572 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
20575 #define mCEF(mnem, op, nops, ops, enc) \
20576 { #mnem, OPS##nops ops, OT_csuffixF, 0, M_MNEM##op, \
20577 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
20580 /* nCEF but for MVE predicated instructions. */
20581 #define mnCEF(mnem, op, nops, ops, enc) \
20582 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
20584 /* nCE but for MVE predicated instructions. */
20585 #define mnCE(mnem, op, nops, ops, enc) \
20586 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
20588 /* NUF but for potentially MVE predicated instructions. */
20589 #define MNUF(mnem, op, nops, ops, enc) \
20590 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
20591 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
20593 /* nUF but for potentially MVE predicated instructions. */
20594 #define mnUF(mnem, op, nops, ops, enc) \
20595 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
20596 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
20598 /* ToC but for potentially MVE predicated instructions. */
20599 #define mToC(mnem, top, nops, ops, te) \
20600 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
20603 /* NCE but for MVE predicated instructions. */
20604 #define MNCE(mnem, op, nops, ops, enc) \
20605 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
20607 /* NCEF but for MVE predicated instructions. */
20608 #define MNCEF(mnem, op, nops, ops, enc) \
20609 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
20612 static const struct asm_opcode insns
[] =
20614 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
20615 #define THUMB_VARIANT & arm_ext_v4t
20616 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20617 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20618 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20619 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20620 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
20621 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
20622 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
20623 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
20624 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20625 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20626 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
20627 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
20628 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20629 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
20630 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
20631 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
20633 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
20634 for setting PSR flag bits. They are obsolete in V6 and do not
20635 have Thumb equivalents. */
20636 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20637 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20638 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
20639 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
20640 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
20641 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
20642 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20643 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20644 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
20646 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
20647 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
20648 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
20649 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
20651 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
20652 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
20653 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
20655 OP_ADDRGLDR
),ldst
, t_ldst
),
20656 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
20658 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20659 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20660 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20661 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20662 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20663 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20665 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
20666 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
20669 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
20670 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
20671 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
20672 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
20674 /* Thumb-compatibility pseudo ops. */
20675 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20676 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20677 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20678 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20679 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20680 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20681 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20682 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
20683 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
20684 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
20685 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
20686 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
20688 /* These may simplify to neg. */
20689 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
20690 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
20692 #undef THUMB_VARIANT
20693 #define THUMB_VARIANT & arm_ext_os
20695 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
20696 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
20698 #undef THUMB_VARIANT
20699 #define THUMB_VARIANT & arm_ext_v6
20701 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
20703 /* V1 instructions with no Thumb analogue prior to V6T2. */
20704 #undef THUMB_VARIANT
20705 #define THUMB_VARIANT & arm_ext_v6t2
20707 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20708 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
20709 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
20711 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20712 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20713 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
20714 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
20716 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20717 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20719 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20720 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
20722 /* V1 instructions with no Thumb analogue at all. */
20723 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
20724 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
20726 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
20727 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
20728 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
20729 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
20730 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
20731 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
20732 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
20733 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
20736 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
20737 #undef THUMB_VARIANT
20738 #define THUMB_VARIANT & arm_ext_v4t
20740 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
20741 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
20743 #undef THUMB_VARIANT
20744 #define THUMB_VARIANT & arm_ext_v6t2
20746 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20747 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
20749 /* Generic coprocessor instructions. */
20750 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
20751 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20752 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20753 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20754 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20755 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20756 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20759 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
20761 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
20762 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
20765 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
20766 #undef THUMB_VARIANT
20767 #define THUMB_VARIANT & arm_ext_msr
20769 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
20770 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
20773 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
20774 #undef THUMB_VARIANT
20775 #define THUMB_VARIANT & arm_ext_v6t2
20777 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20778 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20779 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20780 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20781 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20782 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20783 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
20784 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
20787 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
20788 #undef THUMB_VARIANT
20789 #define THUMB_VARIANT & arm_ext_v4t
20791 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20792 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20793 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20794 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20795 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20796 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
20799 #define ARM_VARIANT & arm_ext_v4t_5
20801 /* ARM Architecture 4T. */
20802 /* Note: bx (and blx) are required on V5, even if the processor does
20803 not support Thumb. */
20804 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
20807 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
20808 #undef THUMB_VARIANT
20809 #define THUMB_VARIANT & arm_ext_v5t
20811 /* Note: blx has 2 variants; the .value coded here is for
20812 BLX(2). Only this variant has conditional execution. */
20813 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
20814 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
20816 #undef THUMB_VARIANT
20817 #define THUMB_VARIANT & arm_ext_v6t2
20819 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
20820 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20821 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20822 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20823 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
20824 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
20825 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20826 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
20829 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
20830 #undef THUMB_VARIANT
20831 #define THUMB_VARIANT & arm_ext_v5exp
20833 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20834 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20835 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20836 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20838 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20839 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
20841 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20842 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20843 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20844 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
20846 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20847 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20848 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20849 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20851 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20852 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
20854 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20855 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20856 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20857 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
20860 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
20861 #undef THUMB_VARIANT
20862 #define THUMB_VARIANT & arm_ext_v6t2
20864 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
20865 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
20867 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
20868 ADDRGLDRS
), ldrd
, t_ldstd
),
20870 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20871 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20874 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
20876 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
20879 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
20880 #undef THUMB_VARIANT
20881 #define THUMB_VARIANT & arm_ext_v6
20883 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20884 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
20885 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20886 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20887 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
20888 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20889 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20890 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20891 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
20892 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
20894 #undef THUMB_VARIANT
20895 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20897 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
20898 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20900 #undef THUMB_VARIANT
20901 #define THUMB_VARIANT & arm_ext_v6t2
20903 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20904 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
20906 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
20907 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
20909 /* ARM V6 not included in V7M. */
20910 #undef THUMB_VARIANT
20911 #define THUMB_VARIANT & arm_ext_v6_notm
20912 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20913 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20914 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
20915 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
20916 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20917 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
20918 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
20919 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
20920 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
20921 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20922 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20923 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
20924 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20925 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
20926 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
20927 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
20928 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20929 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
20930 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
20932 /* ARM V6 not included in V7M (eg. integer SIMD). */
20933 #undef THUMB_VARIANT
20934 #define THUMB_VARIANT & arm_ext_v6_dsp
20935 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
20936 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
20937 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20938 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20939 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20940 /* Old name for QASX. */
20941 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20942 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20943 /* Old name for QSAX. */
20944 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20945 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20946 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20947 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20948 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20949 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20950 /* Old name for SASX. */
20951 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20952 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20953 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20954 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20955 /* Old name for SHASX. */
20956 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20957 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20958 /* Old name for SHSAX. */
20959 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20960 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20961 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20962 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20963 /* Old name for SSAX. */
20964 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20965 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20966 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20967 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20968 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20969 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20970 /* Old name for UASX. */
20971 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20972 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20973 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20974 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20975 /* Old name for UHASX. */
20976 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20977 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20978 /* Old name for UHSAX. */
20979 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20980 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20981 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20982 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20983 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20984 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20985 /* Old name for UQASX. */
20986 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20987 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20988 /* Old name for UQSAX. */
20989 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20990 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20991 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20992 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20993 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20994 /* Old name for USAX. */
20995 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20996 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
20997 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20998 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
20999 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
21000 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21001 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
21002 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
21003 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
21004 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
21005 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
21006 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21007 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21008 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
21009 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
21010 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21011 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21012 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
21013 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
21014 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21015 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21016 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21017 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21018 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21019 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21020 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21021 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21022 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21023 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21024 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
21025 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
21026 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
21027 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
21028 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
21031 #define ARM_VARIANT & arm_ext_v6k_v6t2
21032 #undef THUMB_VARIANT
21033 #define THUMB_VARIANT & arm_ext_v6k_v6t2
21035 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
21036 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
21037 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
21038 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
21040 #undef THUMB_VARIANT
21041 #define THUMB_VARIANT & arm_ext_v6_notm
21042 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
21044 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
21045 RRnpcb
), strexd
, t_strexd
),
21047 #undef THUMB_VARIANT
21048 #define THUMB_VARIANT & arm_ext_v6t2_v8m
21049 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
21051 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
21053 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
21055 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
21057 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
21060 #define ARM_VARIANT & arm_ext_sec
21061 #undef THUMB_VARIANT
21062 #define THUMB_VARIANT & arm_ext_sec
21064 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
21067 #define ARM_VARIANT & arm_ext_virt
21068 #undef THUMB_VARIANT
21069 #define THUMB_VARIANT & arm_ext_virt
21071 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
21072 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
21075 #define ARM_VARIANT & arm_ext_pan
21076 #undef THUMB_VARIANT
21077 #define THUMB_VARIANT & arm_ext_pan
21079 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
21082 #define ARM_VARIANT & arm_ext_v6t2
21083 #undef THUMB_VARIANT
21084 #define THUMB_VARIANT & arm_ext_v6t2
21086 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
21087 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
21088 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
21089 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
21091 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
21092 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
21094 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
21095 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
21096 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
21097 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
21100 #define ARM_VARIANT & arm_ext_v3
21101 #undef THUMB_VARIANT
21102 #define THUMB_VARIANT & arm_ext_v6t2
21104 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
21105 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
21106 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
21109 #define ARM_VARIANT & arm_ext_v6t2
21110 #undef THUMB_VARIANT
21111 #define THUMB_VARIANT & arm_ext_v6t2_v8m
21112 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
21113 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
21115 /* Thumb-only instructions. */
21117 #define ARM_VARIANT NULL
21118 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
21119 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
21121 /* ARM does not really have an IT instruction, so always allow it.
21122 The opcode is copied from Thumb in order to allow warnings in
21123 -mimplicit-it=[never | arm] modes. */
21125 #define ARM_VARIANT & arm_ext_v1
21126 #undef THUMB_VARIANT
21127 #define THUMB_VARIANT & arm_ext_v6t2
21129 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
21130 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
21131 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
21132 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
21133 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
21134 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
21135 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
21136 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
21137 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
21138 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
21139 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
21140 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
21141 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
21142 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
21143 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
21144 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21145 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
21146 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
21148 /* Thumb2 only instructions. */
21150 #define ARM_VARIANT NULL
21152 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
21153 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
21154 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
21155 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
21156 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
21157 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
21159 /* Hardware division instructions. */
21161 #define ARM_VARIANT & arm_ext_adiv
21162 #undef THUMB_VARIANT
21163 #define THUMB_VARIANT & arm_ext_div
21165 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
21166 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
21168 /* ARM V6M/V7 instructions. */
21170 #define ARM_VARIANT & arm_ext_barrier
21171 #undef THUMB_VARIANT
21172 #define THUMB_VARIANT & arm_ext_barrier
21174 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
21175 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
21176 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
21178 /* ARM V7 instructions. */
21180 #define ARM_VARIANT & arm_ext_v7
21181 #undef THUMB_VARIANT
21182 #define THUMB_VARIANT & arm_ext_v7
21184 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
21185 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
21188 #define ARM_VARIANT & arm_ext_mp
21189 #undef THUMB_VARIANT
21190 #define THUMB_VARIANT & arm_ext_mp
21192 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
21194 /* AArchv8 instructions. */
21196 #define ARM_VARIANT & arm_ext_v8
21198 /* Instructions shared between armv8-a and armv8-m. */
21199 #undef THUMB_VARIANT
21200 #define THUMB_VARIANT & arm_ext_atomics
21202 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
21203 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
21204 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
21205 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
21206 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
21207 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
21208 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
21209 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
21210 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
21211 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
21213 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
21215 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
21217 #undef THUMB_VARIANT
21218 #define THUMB_VARIANT & arm_ext_v8
21220 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
21221 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
21223 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
21226 /* Defined in V8 but is in undefined encoding space for earlier
21227 architectures. However earlier architectures are required to treat
21228 this instuction as a semihosting trap as well. Hence while not explicitly
21229 defined as such, it is in fact correct to define the instruction for all
21231 #undef THUMB_VARIANT
21232 #define THUMB_VARIANT & arm_ext_v1
21234 #define ARM_VARIANT & arm_ext_v1
21235 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
21237 /* ARMv8 T32 only. */
21239 #define ARM_VARIANT NULL
21240 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
21241 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
21242 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
21244 /* FP for ARMv8. */
21246 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
21247 #undef THUMB_VARIANT
21248 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
21250 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
21251 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
21252 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
21253 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
21254 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
21255 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
21256 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
21257 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
21258 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
21259 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
21260 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
21261 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
21262 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
21263 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
21264 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
21265 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
21266 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
21268 /* Crypto v1 extensions. */
21270 #define ARM_VARIANT & fpu_crypto_ext_armv8
21271 #undef THUMB_VARIANT
21272 #define THUMB_VARIANT & fpu_crypto_ext_armv8
21274 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
21275 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
21276 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
21277 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
21278 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
21279 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
21280 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
21281 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
21282 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
21283 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
21284 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
21285 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
21286 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
21287 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
21290 #define ARM_VARIANT & crc_ext_armv8
21291 #undef THUMB_VARIANT
21292 #define THUMB_VARIANT & crc_ext_armv8
21293 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
21294 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
21295 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
21296 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
21297 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
21298 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
21300 /* ARMv8.2 RAS extension. */
21302 #define ARM_VARIANT & arm_ext_ras
21303 #undef THUMB_VARIANT
21304 #define THUMB_VARIANT & arm_ext_ras
21305 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
21308 #define ARM_VARIANT & arm_ext_v8_3
21309 #undef THUMB_VARIANT
21310 #define THUMB_VARIANT & arm_ext_v8_3
21311 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
21312 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
21313 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
21316 #define ARM_VARIANT & fpu_neon_ext_dotprod
21317 #undef THUMB_VARIANT
21318 #define THUMB_VARIANT & fpu_neon_ext_dotprod
21319 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
21320 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
21323 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
21324 #undef THUMB_VARIANT
21325 #define THUMB_VARIANT NULL
21327 cCE("wfs", e200110
, 1, (RR
), rd
),
21328 cCE("rfs", e300110
, 1, (RR
), rd
),
21329 cCE("wfc", e400110
, 1, (RR
), rd
),
21330 cCE("rfc", e500110
, 1, (RR
), rd
),
21332 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21333 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21334 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21335 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21337 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21338 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21339 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21340 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
21342 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
21343 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
21344 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
21345 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
21346 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
21347 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
21348 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
21349 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
21350 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
21351 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
21352 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
21353 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
21355 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
21356 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
21357 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
21358 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
21359 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
21360 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
21361 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
21362 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
21363 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
21364 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
21365 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
21366 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
21368 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
21369 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
21370 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
21371 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
21372 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
21373 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
21374 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
21375 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
21376 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
21377 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
21378 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
21379 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
21381 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
21382 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
21383 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
21384 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
21385 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
21386 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
21387 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
21388 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
21389 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
21390 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
21391 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
21392 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
21394 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
21395 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
21396 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
21397 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
21398 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
21399 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
21400 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
21401 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
21402 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
21403 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
21404 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
21405 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
21407 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
21408 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
21409 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
21410 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
21411 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
21412 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
21413 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
21414 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
21415 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
21416 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
21417 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
21418 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
21420 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
21421 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
21422 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
21423 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
21424 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
21425 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
21426 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
21427 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
21428 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
21429 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
21430 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
21431 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
21433 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
21434 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
21435 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
21436 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
21437 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
21438 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
21439 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
21440 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
21441 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
21442 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
21443 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
21444 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
21446 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
21447 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
21448 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
21449 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
21450 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
21451 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
21452 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
21453 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
21454 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
21455 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
21456 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
21457 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
21459 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
21460 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
21461 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
21462 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
21463 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
21464 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
21465 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
21466 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
21467 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
21468 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
21469 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
21470 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
21472 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
21473 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
21474 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
21475 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
21476 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
21477 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
21478 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
21479 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
21480 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
21481 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
21482 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
21483 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
21485 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
21486 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
21487 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
21488 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
21489 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
21490 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
21491 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
21492 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
21493 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
21494 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
21495 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
21496 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
21498 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
21499 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
21500 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
21501 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
21502 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
21503 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
21504 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
21505 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
21506 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
21507 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
21508 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
21509 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
21511 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
21512 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
21513 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
21514 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
21515 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
21516 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
21517 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
21518 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
21519 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
21520 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
21521 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
21522 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
21524 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
21525 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
21526 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
21527 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
21528 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
21529 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
21530 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
21531 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
21532 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
21533 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
21534 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
21535 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
21537 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
21538 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
21539 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
21540 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
21541 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
21542 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
21543 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
21544 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
21545 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
21546 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
21547 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
21548 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
21550 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21551 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21552 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21553 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21554 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21555 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21556 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21557 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21558 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21559 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21560 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21561 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21563 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21564 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21565 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21566 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21567 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21568 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21569 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21570 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21571 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21572 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21573 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21574 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21576 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21577 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21578 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21579 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21580 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21581 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21582 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21583 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21584 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21585 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21586 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21587 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21589 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21590 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21591 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21592 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21593 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21594 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21595 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21596 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21597 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21598 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21599 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21600 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21602 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21603 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21604 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21605 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21606 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21607 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21608 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21609 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21610 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21611 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21612 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21613 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21615 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21616 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21617 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21618 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21619 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21620 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21621 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21622 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21623 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21624 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21625 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21626 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21628 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21629 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21630 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21631 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21632 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21633 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21634 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21635 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21636 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21637 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21638 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21639 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21641 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21642 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21643 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21644 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21645 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21646 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21647 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21648 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21649 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21650 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21651 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21652 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21654 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21655 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21656 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21657 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21658 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21659 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21660 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21661 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21662 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21663 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21664 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21665 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21667 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21668 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21669 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21670 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21671 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21672 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21673 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21674 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21675 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21676 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21677 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21678 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21680 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21681 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21682 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21683 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21684 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21685 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21686 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21687 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21688 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21689 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21690 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21691 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21693 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21694 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21695 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21696 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21697 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21698 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21699 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21700 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21701 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21702 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21703 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21704 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21706 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21707 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21708 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21709 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21710 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21711 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21712 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21713 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21714 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21715 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21716 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21717 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
21719 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21720 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21721 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21722 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
21724 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
21725 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
21726 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
21727 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
21728 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
21729 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
21730 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
21731 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
21732 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
21733 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
21734 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
21735 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
21737 /* The implementation of the FIX instruction is broken on some
21738 assemblers, in that it accepts a precision specifier as well as a
21739 rounding specifier, despite the fact that this is meaningless.
21740 To be more compatible, we accept it as well, though of course it
21741 does not set any bits. */
21742 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
21743 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
21744 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
21745 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
21746 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
21747 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
21748 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
21749 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
21750 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
21751 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
21752 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
21753 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
21754 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
21756 /* Instructions that were new with the real FPA, call them V2. */
21758 #define ARM_VARIANT & fpu_fpa_ext_v2
21760 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21761 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21762 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21763 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21764 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21765 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
21768 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
21770 /* Moves and type conversions. */
21771 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21772 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
21773 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
21774 cCE("fmstat", ef1fa10
, 0, (), noargs
),
21775 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
21776 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
21777 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21778 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21779 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21780 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21781 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21782 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21783 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
21784 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
21786 /* Memory operations. */
21787 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21788 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
21789 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21790 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21791 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21792 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21793 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21794 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21795 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21796 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21797 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21798 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
21799 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21800 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
21801 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21802 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
21803 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21804 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
21806 /* Monadic operations. */
21807 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21808 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21809 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21811 /* Dyadic operations. */
21812 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21813 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21814 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21815 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21816 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21817 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21818 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21819 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21820 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21823 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21824 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
21825 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
21826 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
21828 /* Double precision load/store are still present on single precision
21829 implementations. */
21830 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21831 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
21832 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21833 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21834 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21835 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21836 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21837 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
21838 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21839 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
21842 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
21844 /* Moves and type conversions. */
21845 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21846 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21847 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21848 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21849 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
21850 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21851 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
21852 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21853 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
21854 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21855 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21856 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21857 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
21859 /* Monadic operations. */
21860 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21861 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21862 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21864 /* Dyadic operations. */
21865 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21866 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21867 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21868 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21869 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21870 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21871 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21872 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21873 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21876 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21877 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
21878 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
21879 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
21882 #define ARM_VARIANT & fpu_vfp_ext_v2
21884 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
21885 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
21886 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
21887 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
21889 /* Instructions which may belong to either the Neon or VFP instruction sets.
21890 Individual encoder functions perform additional architecture checks. */
21892 #define ARM_VARIANT & fpu_vfp_ext_v1xd
21893 #undef THUMB_VARIANT
21894 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
21896 /* These mnemonics are unique to VFP. */
21897 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
21898 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
21899 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21900 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21901 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21902 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21903 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
21904 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
21905 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
21906 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
21908 /* Mnemonics shared by Neon and VFP. */
21909 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
21910 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21911 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
21913 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21914 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21915 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21916 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21917 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21918 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
21920 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
21921 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
21922 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
21923 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
21926 /* NOTE: All VMOV encoding is special-cased! */
21927 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
21928 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
21930 #undef THUMB_VARIANT
21931 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
21932 by different feature bits. Since we are setting the Thumb guard, we can
21933 require Thumb-1 which makes it a nop guard and set the right feature bit in
21934 do_vldr_vstr (). */
21935 #define THUMB_VARIANT & arm_ext_v4t
21936 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
21937 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
21940 #define ARM_VARIANT & arm_ext_fp16
21941 #undef THUMB_VARIANT
21942 #define THUMB_VARIANT & arm_ext_fp16
21943 /* New instructions added from v8.2, allowing the extraction and insertion of
21944 the upper 16 bits of a 32-bit vector register. */
21945 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
21946 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
21948 /* New backported fma/fms instructions optional in v8.2. */
21949 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
21950 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
21952 #undef THUMB_VARIANT
21953 #define THUMB_VARIANT & fpu_neon_ext_v1
21955 #define ARM_VARIANT & fpu_neon_ext_v1
21957 /* Data processing with three registers of the same length. */
21958 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
21959 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
21960 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
21961 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21962 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21963 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21964 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21965 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
21966 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
21967 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
21968 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21969 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21970 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
21971 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
21972 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21973 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21974 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
21975 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
21976 /* If not immediate, fall back to neon_dyadic_i64_su.
21977 shl_imm should accept I8 I16 I32 I64,
21978 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21979 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
21980 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
21981 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
21982 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
21983 /* Logic ops, types optional & ignored. */
21984 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21985 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21986 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21987 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21988 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21989 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21990 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
21991 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
21992 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
21993 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
21994 /* Bitfield ops, untyped. */
21995 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21996 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21997 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
21998 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
21999 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
22000 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
22001 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
22002 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
22003 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
22004 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
22005 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
22006 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
22007 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
22008 back to neon_dyadic_if_su. */
22009 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
22010 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
22011 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
22012 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
22013 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
22014 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
22015 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
22016 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
22017 /* Comparison. Type I8 I16 I32 F32. */
22018 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
22019 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
22020 /* As above, D registers only. */
22021 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
22022 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
22023 /* Int and float variants, signedness unimportant. */
22024 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
22025 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
22026 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
22027 /* Add/sub take types I8 I16 I32 I64 F32. */
22028 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
22029 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
22030 /* vtst takes sizes 8, 16, 32. */
22031 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
22032 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
22033 /* VMUL takes I8 I16 I32 F32 P8. */
22034 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
22035 /* VQD{R}MULH takes S16 S32. */
22036 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
22037 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
22038 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
22039 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
22040 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
22041 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
22042 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
22043 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
22044 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
22045 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
22046 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
22047 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
22048 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
22049 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
22050 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
22051 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
22052 /* ARM v8.1 extension. */
22053 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
22054 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
22055 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
22056 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
22058 /* Two address, int/float. Types S8 S16 S32 F32. */
22059 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
22060 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
22062 /* Data processing with two registers and a shift amount. */
22063 /* Right shifts, and variants with rounding.
22064 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
22065 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
22066 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
22067 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
22068 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
22069 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
22070 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
22071 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
22072 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
22073 /* Shift and insert. Sizes accepted 8 16 32 64. */
22074 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
22075 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
22076 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
22077 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
22078 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
22079 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
22080 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
22081 /* Right shift immediate, saturating & narrowing, with rounding variants.
22082 Types accepted S16 S32 S64 U16 U32 U64. */
22083 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
22084 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
22085 /* As above, unsigned. Types accepted S16 S32 S64. */
22086 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
22087 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
22088 /* Right shift narrowing. Types accepted I16 I32 I64. */
22089 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
22090 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
22091 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
22092 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
22093 /* CVT with optional immediate for fixed-point variant. */
22094 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
22096 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
22097 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
22099 /* Data processing, three registers of different lengths. */
22100 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
22101 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
22102 /* If not scalar, fall back to neon_dyadic_long.
22103 Vector types as above, scalar types S16 S32 U16 U32. */
22104 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
22105 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
22106 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
22107 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
22108 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
22109 /* Dyadic, narrowing insns. Types I16 I32 I64. */
22110 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
22111 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
22112 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
22113 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
22114 /* Saturating doubling multiplies. Types S16 S32. */
22115 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
22116 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
22117 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
22118 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
22119 S16 S32 U16 U32. */
22120 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
22122 /* Extract. Size 8. */
22123 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
22124 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
22126 /* Two registers, miscellaneous. */
22127 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
22128 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
22129 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
22130 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
22131 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
22132 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
22133 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
22134 /* Vector replicate. Sizes 8 16 32. */
22135 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
22136 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
22137 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
22138 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
22139 /* VMOVN. Types I16 I32 I64. */
22140 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
22141 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
22142 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
22143 /* VQMOVUN. Types S16 S32 S64. */
22144 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
22145 /* VZIP / VUZP. Sizes 8 16 32. */
22146 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
22147 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
22148 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
22149 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
22150 /* VQABS / VQNEG. Types S8 S16 S32. */
22151 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
22152 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
22153 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
22154 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
22155 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
22156 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
22157 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
22158 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
22159 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
22160 /* Reciprocal estimates. Types U32 F16 F32. */
22161 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
22162 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
22163 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
22164 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
22165 /* VCLS. Types S8 S16 S32. */
22166 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
22167 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
22168 /* VCLZ. Types I8 I16 I32. */
22169 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
22170 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
22171 /* VCNT. Size 8. */
22172 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
22173 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
22174 /* Two address, untyped. */
22175 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
22176 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
22177 /* VTRN. Sizes 8 16 32. */
22178 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
22179 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
22181 /* Table lookup. Size 8. */
22182 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
22183 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
22185 #undef THUMB_VARIANT
22186 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
22188 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
22190 /* Neon element/structure load/store. */
22191 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22192 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22193 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22194 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22195 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22196 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22197 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22198 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
22200 #undef THUMB_VARIANT
22201 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
22203 #define ARM_VARIANT & fpu_vfp_ext_v3xd
22204 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
22205 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
22206 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
22207 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
22208 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
22209 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
22210 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
22211 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
22212 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
22214 #undef THUMB_VARIANT
22215 #define THUMB_VARIANT & fpu_vfp_ext_v3
22217 #define ARM_VARIANT & fpu_vfp_ext_v3
22219 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
22220 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
22221 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
22222 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
22223 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
22224 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
22225 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
22226 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
22227 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
22230 #define ARM_VARIANT & fpu_vfp_ext_fma
22231 #undef THUMB_VARIANT
22232 #define THUMB_VARIANT & fpu_vfp_ext_fma
22233 /* Mnemonics shared by Neon and VFP. These are included in the
22234 VFP FMA variant; NEON and VFP FMA always includes the NEON
22235 FMA instructions. */
22236 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
22237 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
22238 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
22239 the v form should always be used. */
22240 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22241 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
22242 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22243 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
22244 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
22245 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
22247 #undef THUMB_VARIANT
22249 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
22251 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22252 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22253 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22254 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22255 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22256 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
22257 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
22258 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
22261 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
22263 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
22264 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
22265 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
22266 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
22267 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
22268 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
22269 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
22270 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
22271 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
22272 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22273 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22274 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22275 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22276 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22277 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
22278 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
22279 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
22280 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
22281 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
22282 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
22283 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22284 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22285 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22286 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22287 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22288 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
22289 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
22290 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
22291 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
22292 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
22293 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
22294 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
22295 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
22296 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
22297 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22298 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22299 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22300 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22301 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22302 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22303 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22304 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22305 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22306 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22307 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22308 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22309 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
22310 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22311 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22312 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22313 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22314 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22315 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22316 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22317 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22318 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22319 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22320 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22321 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22322 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22323 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22324 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22325 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22326 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22327 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22328 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22329 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
22330 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
22331 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
22332 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
22333 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22334 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22335 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22336 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22337 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22338 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22339 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22340 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22341 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22342 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22343 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22344 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22345 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22346 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22347 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22348 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22349 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22350 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22351 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
22352 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22353 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22354 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22355 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22356 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22357 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22358 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22359 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22360 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22361 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22362 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22363 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22364 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22365 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22366 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22367 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22368 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22369 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22370 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22371 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22372 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22373 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
22374 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22375 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22376 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22377 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22378 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22379 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22380 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22381 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22382 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22383 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22384 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22385 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22386 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22387 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22388 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22389 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22390 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
22391 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
22392 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
22393 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
22394 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
22395 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
22396 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22397 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22398 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22399 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22400 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22401 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22402 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22403 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22404 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22405 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22406 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22407 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22408 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22409 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22410 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
22411 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22412 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22413 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22414 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22415 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22416 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22417 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22418 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22419 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
22420 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22421 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22422 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22423 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22424 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
22427 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
22429 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
22430 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
22431 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
22432 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22433 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22434 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
22435 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22436 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22437 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22438 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22439 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22440 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22441 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22442 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22443 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22444 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22445 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22446 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22447 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22448 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22449 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
22450 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22451 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22452 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22453 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22454 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22455 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22456 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22457 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22458 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22459 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22460 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22461 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22462 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22463 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22464 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22465 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22466 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22467 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22468 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22469 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22470 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22471 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22472 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22473 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22474 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22475 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22476 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22477 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22478 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22479 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22480 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22481 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22482 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22483 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22484 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22485 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
22488 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
22490 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
22491 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
22492 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
22493 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
22494 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
22495 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
22496 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
22497 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
22498 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
22499 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
22500 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
22501 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
22502 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
22503 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
22504 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
22505 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
22506 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
22507 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
22508 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
22509 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
22510 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
22511 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
22512 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
22513 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
22514 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
22515 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
22516 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
22517 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
22518 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
22519 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
22520 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
22521 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
22522 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
22523 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
22524 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
22525 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
22526 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
22527 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
22528 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
22529 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
22530 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
22531 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
22532 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
22533 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
22534 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
22535 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
22536 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
22537 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
22538 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
22539 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
22540 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
22541 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
22542 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
22543 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
22544 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
22545 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
22546 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
22547 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
22548 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
22549 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
22550 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
22551 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
22552 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
22553 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
22554 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
22555 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
22556 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
22557 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
22558 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
22559 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
22560 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
22561 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
22562 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
22563 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
22564 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
22565 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
22567 /* ARMv8.5-A instructions. */
22569 #define ARM_VARIANT & arm_ext_sb
22570 #undef THUMB_VARIANT
22571 #define THUMB_VARIANT & arm_ext_sb
22572 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
22575 #define ARM_VARIANT & arm_ext_predres
22576 #undef THUMB_VARIANT
22577 #define THUMB_VARIANT & arm_ext_predres
22578 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
22579 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
22580 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
22582 /* ARMv8-M instructions. */
22584 #define ARM_VARIANT NULL
22585 #undef THUMB_VARIANT
22586 #define THUMB_VARIANT & arm_ext_v8m
22587 ToU("sg", e97fe97f
, 0, (), noargs
),
22588 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
22589 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
22590 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
22591 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
22592 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
22593 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
22595 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
22596 instructions behave as nop if no VFP is present. */
22597 #undef THUMB_VARIANT
22598 #define THUMB_VARIANT & arm_ext_v8m_main
22599 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
22600 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
22602 /* Armv8.1-M Mainline instructions. */
22603 #undef THUMB_VARIANT
22604 #define THUMB_VARIANT & arm_ext_v8_1m_main
22605 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
22606 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
22607 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
22608 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
22609 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
22611 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
22612 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
22613 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
22615 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
22616 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
22618 #undef THUMB_VARIANT
22619 #define THUMB_VARIANT & mve_ext
22620 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
22621 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
22622 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
22623 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
22624 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
22625 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
22626 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
22627 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
22628 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
22629 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
22630 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
22631 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
22632 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
22633 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
22634 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
22637 #define ARM_VARIANT & fpu_vfp_ext_v1xd
22638 #undef THUMB_VARIANT
22639 #define THUMB_VARIANT & arm_ext_v6t2
22641 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
22642 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
22644 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
22645 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
22648 #define ARM_VARIANT & fpu_neon_ext_v1
22649 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
22650 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
22651 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
22652 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
22655 #undef THUMB_VARIANT
22687 /* MD interface: bits in the object file. */
22689 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
22690 for use in the a.out file, and stores them in the array pointed to by buf.
22691 This knows about the endian-ness of the target machine and does
22692 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
22693 2 (short) and 4 (long) Floating numbers are put out as a series of
22694 LITTLENUMS (shorts, here at least). */
22697 md_number_to_chars (char * buf
, valueT val
, int n
)
22699 if (target_big_endian
)
22700 number_to_chars_bigendian (buf
, val
, n
);
22702 number_to_chars_littleendian (buf
, val
, n
);
22706 md_chars_to_number (char * buf
, int n
)
22709 unsigned char * where
= (unsigned char *) buf
;
22711 if (target_big_endian
)
22716 result
|= (*where
++ & 255);
22724 result
|= (where
[n
] & 255);
22731 /* MD interface: Sections. */
22733 /* Calculate the maximum variable size (i.e., excluding fr_fix)
22734 that an rs_machine_dependent frag may reach. */
22737 arm_frag_max_var (fragS
*fragp
)
22739 /* We only use rs_machine_dependent for variable-size Thumb instructions,
22740 which are either THUMB_SIZE (2) or INSN_SIZE (4).
22742 Note that we generate relaxable instructions even for cases that don't
22743 really need it, like an immediate that's a trivial constant. So we're
22744 overestimating the instruction size for some of those cases. Rather
22745 than putting more intelligence here, it would probably be better to
22746 avoid generating a relaxation frag in the first place when it can be
22747 determined up front that a short instruction will suffice. */
22749 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
22753 /* Estimate the size of a frag before relaxing. Assume everything fits in
22757 md_estimate_size_before_relax (fragS
* fragp
,
22758 segT segtype ATTRIBUTE_UNUSED
)
22764 /* Convert a machine dependent frag. */
22767 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
22769 unsigned long insn
;
22770 unsigned long old_op
;
22778 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
22780 old_op
= bfd_get_16(abfd
, buf
);
22781 if (fragp
->fr_symbol
)
22783 exp
.X_op
= O_symbol
;
22784 exp
.X_add_symbol
= fragp
->fr_symbol
;
22788 exp
.X_op
= O_constant
;
22790 exp
.X_add_number
= fragp
->fr_offset
;
22791 opcode
= fragp
->fr_subtype
;
22794 case T_MNEM_ldr_pc
:
22795 case T_MNEM_ldr_pc2
:
22796 case T_MNEM_ldr_sp
:
22797 case T_MNEM_str_sp
:
22804 if (fragp
->fr_var
== 4)
22806 insn
= THUMB_OP32 (opcode
);
22807 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
22809 insn
|= (old_op
& 0x700) << 4;
22813 insn
|= (old_op
& 7) << 12;
22814 insn
|= (old_op
& 0x38) << 13;
22816 insn
|= 0x00000c00;
22817 put_thumb32_insn (buf
, insn
);
22818 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
22822 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
22824 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
22827 if (fragp
->fr_var
== 4)
22829 insn
= THUMB_OP32 (opcode
);
22830 insn
|= (old_op
& 0xf0) << 4;
22831 put_thumb32_insn (buf
, insn
);
22832 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
22836 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22837 exp
.X_add_number
-= 4;
22845 if (fragp
->fr_var
== 4)
22847 int r0off
= (opcode
== T_MNEM_mov
22848 || opcode
== T_MNEM_movs
) ? 0 : 8;
22849 insn
= THUMB_OP32 (opcode
);
22850 insn
= (insn
& 0xe1ffffff) | 0x10000000;
22851 insn
|= (old_op
& 0x700) << r0off
;
22852 put_thumb32_insn (buf
, insn
);
22853 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22857 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
22862 if (fragp
->fr_var
== 4)
22864 insn
= THUMB_OP32(opcode
);
22865 put_thumb32_insn (buf
, insn
);
22866 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
22869 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
22873 if (fragp
->fr_var
== 4)
22875 insn
= THUMB_OP32(opcode
);
22876 insn
|= (old_op
& 0xf00) << 14;
22877 put_thumb32_insn (buf
, insn
);
22878 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
22881 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
22884 case T_MNEM_add_sp
:
22885 case T_MNEM_add_pc
:
22886 case T_MNEM_inc_sp
:
22887 case T_MNEM_dec_sp
:
22888 if (fragp
->fr_var
== 4)
22890 /* ??? Choose between add and addw. */
22891 insn
= THUMB_OP32 (opcode
);
22892 insn
|= (old_op
& 0xf0) << 4;
22893 put_thumb32_insn (buf
, insn
);
22894 if (opcode
== T_MNEM_add_pc
)
22895 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
22897 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22900 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22908 if (fragp
->fr_var
== 4)
22910 insn
= THUMB_OP32 (opcode
);
22911 insn
|= (old_op
& 0xf0) << 4;
22912 insn
|= (old_op
& 0xf) << 16;
22913 put_thumb32_insn (buf
, insn
);
22914 if (insn
& (1 << 20))
22915 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
22917 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
22920 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
22926 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
22927 (enum bfd_reloc_code_real
) reloc_type
);
22928 fixp
->fx_file
= fragp
->fr_file
;
22929 fixp
->fx_line
= fragp
->fr_line
;
22930 fragp
->fr_fix
+= fragp
->fr_var
;
22932 /* Set whether we use thumb-2 ISA based on final relaxation results. */
22933 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
22934 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
22935 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
22938 /* Return the size of a relaxable immediate operand instruction.
22939 SHIFT and SIZE specify the form of the allowable immediate. */
22941 relax_immediate (fragS
*fragp
, int size
, int shift
)
22947 /* ??? Should be able to do better than this. */
22948 if (fragp
->fr_symbol
)
22951 low
= (1 << shift
) - 1;
22952 mask
= (1 << (shift
+ size
)) - (1 << shift
);
22953 offset
= fragp
->fr_offset
;
22954 /* Force misaligned offsets to 32-bit variant. */
22957 if (offset
& ~mask
)
22962 /* Get the address of a symbol during relaxation. */
22964 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
22970 sym
= fragp
->fr_symbol
;
22971 sym_frag
= symbol_get_frag (sym
);
22972 know (S_GET_SEGMENT (sym
) != absolute_section
22973 || sym_frag
== &zero_address_frag
);
22974 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
22976 /* If frag has yet to be reached on this pass, assume it will
22977 move by STRETCH just as we did. If this is not so, it will
22978 be because some frag between grows, and that will force
22982 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
22986 /* Adjust stretch for any alignment frag. Note that if have
22987 been expanding the earlier code, the symbol may be
22988 defined in what appears to be an earlier frag. FIXME:
22989 This doesn't handle the fr_subtype field, which specifies
22990 a maximum number of bytes to skip when doing an
22992 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
22994 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
22997 stretch
= - ((- stretch
)
22998 & ~ ((1 << (int) f
->fr_offset
) - 1));
23000 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
23012 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
23015 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
23020 /* Assume worst case for symbols not known to be in the same section. */
23021 if (fragp
->fr_symbol
== NULL
23022 || !S_IS_DEFINED (fragp
->fr_symbol
)
23023 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
23024 || S_IS_WEAK (fragp
->fr_symbol
))
23027 val
= relaxed_symbol_addr (fragp
, stretch
);
23028 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
23029 addr
= (addr
+ 4) & ~3;
23030 /* Force misaligned targets to 32-bit variant. */
23034 if (val
< 0 || val
> 1020)
23039 /* Return the size of a relaxable add/sub immediate instruction. */
23041 relax_addsub (fragS
*fragp
, asection
*sec
)
23046 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
23047 op
= bfd_get_16(sec
->owner
, buf
);
23048 if ((op
& 0xf) == ((op
>> 4) & 0xf))
23049 return relax_immediate (fragp
, 8, 0);
23051 return relax_immediate (fragp
, 3, 0);
23054 /* Return TRUE iff the definition of symbol S could be pre-empted
23055 (overridden) at link or load time. */
23057 symbol_preemptible (symbolS
*s
)
23059 /* Weak symbols can always be pre-empted. */
23063 /* Non-global symbols cannot be pre-empted. */
23064 if (! S_IS_EXTERNAL (s
))
23068 /* In ELF, a global symbol can be marked protected, or private. In that
23069 case it can't be pre-empted (other definitions in the same link unit
23070 would violate the ODR). */
23071 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
23075 /* Other global symbols might be pre-empted. */
23079 /* Return the size of a relaxable branch instruction. BITS is the
23080 size of the offset field in the narrow instruction. */
23083 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
23089 /* Assume worst case for symbols not known to be in the same section. */
23090 if (!S_IS_DEFINED (fragp
->fr_symbol
)
23091 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
23092 || S_IS_WEAK (fragp
->fr_symbol
))
23096 /* A branch to a function in ARM state will require interworking. */
23097 if (S_IS_DEFINED (fragp
->fr_symbol
)
23098 && ARM_IS_FUNC (fragp
->fr_symbol
))
23102 if (symbol_preemptible (fragp
->fr_symbol
))
23105 val
= relaxed_symbol_addr (fragp
, stretch
);
23106 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
23109 /* Offset is a signed value *2 */
23111 if (val
>= limit
|| val
< -limit
)
23117 /* Relax a machine dependent frag. This returns the amount by which
23118 the current size of the frag should change. */
23121 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
23126 oldsize
= fragp
->fr_var
;
23127 switch (fragp
->fr_subtype
)
23129 case T_MNEM_ldr_pc2
:
23130 newsize
= relax_adr (fragp
, sec
, stretch
);
23132 case T_MNEM_ldr_pc
:
23133 case T_MNEM_ldr_sp
:
23134 case T_MNEM_str_sp
:
23135 newsize
= relax_immediate (fragp
, 8, 2);
23139 newsize
= relax_immediate (fragp
, 5, 2);
23143 newsize
= relax_immediate (fragp
, 5, 1);
23147 newsize
= relax_immediate (fragp
, 5, 0);
23150 newsize
= relax_adr (fragp
, sec
, stretch
);
23156 newsize
= relax_immediate (fragp
, 8, 0);
23159 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
23162 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
23164 case T_MNEM_add_sp
:
23165 case T_MNEM_add_pc
:
23166 newsize
= relax_immediate (fragp
, 8, 2);
23168 case T_MNEM_inc_sp
:
23169 case T_MNEM_dec_sp
:
23170 newsize
= relax_immediate (fragp
, 7, 2);
23176 newsize
= relax_addsub (fragp
, sec
);
23182 fragp
->fr_var
= newsize
;
23183 /* Freeze wide instructions that are at or before the same location as
23184 in the previous pass. This avoids infinite loops.
23185 Don't freeze them unconditionally because targets may be artificially
23186 misaligned by the expansion of preceding frags. */
23187 if (stretch
<= 0 && newsize
> 2)
23189 md_convert_frag (sec
->owner
, sec
, fragp
);
23193 return newsize
- oldsize
;
23196 /* Round up a section size to the appropriate boundary. */
23199 md_section_align (segT segment ATTRIBUTE_UNUSED
,
23205 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
23206 of an rs_align_code fragment. */
23209 arm_handle_align (fragS
* fragP
)
23211 static unsigned char const arm_noop
[2][2][4] =
23214 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
23215 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
23218 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
23219 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
23222 static unsigned char const thumb_noop
[2][2][2] =
23225 {0xc0, 0x46}, /* LE */
23226 {0x46, 0xc0}, /* BE */
23229 {0x00, 0xbf}, /* LE */
23230 {0xbf, 0x00} /* BE */
23233 static unsigned char const wide_thumb_noop
[2][4] =
23234 { /* Wide Thumb-2 */
23235 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
23236 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
23239 unsigned bytes
, fix
, noop_size
;
23241 const unsigned char * noop
;
23242 const unsigned char *narrow_noop
= NULL
;
23247 if (fragP
->fr_type
!= rs_align_code
)
23250 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
23251 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
23254 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
23255 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
23257 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
23259 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
23261 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
23262 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
23264 narrow_noop
= thumb_noop
[1][target_big_endian
];
23265 noop
= wide_thumb_noop
[target_big_endian
];
23268 noop
= thumb_noop
[0][target_big_endian
];
23276 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
23277 ? selected_cpu
: arm_arch_none
,
23279 [target_big_endian
];
23286 fragP
->fr_var
= noop_size
;
23288 if (bytes
& (noop_size
- 1))
23290 fix
= bytes
& (noop_size
- 1);
23292 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
23294 memset (p
, 0, fix
);
23301 if (bytes
& noop_size
)
23303 /* Insert a narrow noop. */
23304 memcpy (p
, narrow_noop
, noop_size
);
23306 bytes
-= noop_size
;
23310 /* Use wide noops for the remainder */
23314 while (bytes
>= noop_size
)
23316 memcpy (p
, noop
, noop_size
);
23318 bytes
-= noop_size
;
23322 fragP
->fr_fix
+= fix
;
23325 /* Called from md_do_align. Used to create an alignment
23326 frag in a code section. */
23329 arm_frag_align_code (int n
, int max
)
23333 /* We assume that there will never be a requirement
23334 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
23335 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
23340 _("alignments greater than %d bytes not supported in .text sections."),
23341 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
23342 as_fatal ("%s", err_msg
);
23345 p
= frag_var (rs_align_code
,
23346 MAX_MEM_FOR_RS_ALIGN_CODE
,
23348 (relax_substateT
) max
,
23355 /* Perform target specific initialisation of a frag.
23356 Note - despite the name this initialisation is not done when the frag
23357 is created, but only when its type is assigned. A frag can be created
23358 and used a long time before its type is set, so beware of assuming that
23359 this initialisation is performed first. */
23363 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
23365 /* Record whether this frag is in an ARM or a THUMB area. */
23366 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
23369 #else /* OBJ_ELF is defined. */
23371 arm_init_frag (fragS
* fragP
, int max_chars
)
23373 bfd_boolean frag_thumb_mode
;
23375 /* If the current ARM vs THUMB mode has not already
23376 been recorded into this frag then do so now. */
23377 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
23378 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
23380 /* PR 21809: Do not set a mapping state for debug sections
23381 - it just confuses other tools. */
23382 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
23385 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
23387 /* Record a mapping symbol for alignment frags. We will delete this
23388 later if the alignment ends up empty. */
23389 switch (fragP
->fr_type
)
23392 case rs_align_test
:
23394 mapping_state_2 (MAP_DATA
, max_chars
);
23396 case rs_align_code
:
23397 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
23404 /* When we change sections we need to issue a new mapping symbol. */
23407 arm_elf_change_section (void)
23409 /* Link an unlinked unwind index table section to the .text section. */
23410 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
23411 && elf_linked_to_section (now_seg
) == NULL
)
23412 elf_linked_to_section (now_seg
) = text_section
;
23416 arm_elf_section_type (const char * str
, size_t len
)
23418 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
23419 return SHT_ARM_EXIDX
;
23424 /* Code to deal with unwinding tables. */
23426 static void add_unwind_adjustsp (offsetT
);
23428 /* Generate any deferred unwind frame offset. */
23431 flush_pending_unwind (void)
23435 offset
= unwind
.pending_offset
;
23436 unwind
.pending_offset
= 0;
23438 add_unwind_adjustsp (offset
);
23441 /* Add an opcode to this list for this function. Two-byte opcodes should
23442 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
23446 add_unwind_opcode (valueT op
, int length
)
23448 /* Add any deferred stack adjustment. */
23449 if (unwind
.pending_offset
)
23450 flush_pending_unwind ();
23452 unwind
.sp_restored
= 0;
23454 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
23456 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
23457 if (unwind
.opcodes
)
23458 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
23459 unwind
.opcode_alloc
);
23461 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
23466 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
23468 unwind
.opcode_count
++;
23472 /* Add unwind opcodes to adjust the stack pointer. */
23475 add_unwind_adjustsp (offsetT offset
)
23479 if (offset
> 0x200)
23481 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
23486 /* Long form: 0xb2, uleb128. */
23487 /* This might not fit in a word so add the individual bytes,
23488 remembering the list is built in reverse order. */
23489 o
= (valueT
) ((offset
- 0x204) >> 2);
23491 add_unwind_opcode (0, 1);
23493 /* Calculate the uleb128 encoding of the offset. */
23497 bytes
[n
] = o
& 0x7f;
23503 /* Add the insn. */
23505 add_unwind_opcode (bytes
[n
- 1], 1);
23506 add_unwind_opcode (0xb2, 1);
23508 else if (offset
> 0x100)
23510 /* Two short opcodes. */
23511 add_unwind_opcode (0x3f, 1);
23512 op
= (offset
- 0x104) >> 2;
23513 add_unwind_opcode (op
, 1);
23515 else if (offset
> 0)
23517 /* Short opcode. */
23518 op
= (offset
- 4) >> 2;
23519 add_unwind_opcode (op
, 1);
23521 else if (offset
< 0)
23524 while (offset
> 0x100)
23526 add_unwind_opcode (0x7f, 1);
23529 op
= ((offset
- 4) >> 2) | 0x40;
23530 add_unwind_opcode (op
, 1);
23534 /* Finish the list of unwind opcodes for this function. */
23537 finish_unwind_opcodes (void)
23541 if (unwind
.fp_used
)
23543 /* Adjust sp as necessary. */
23544 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
23545 flush_pending_unwind ();
23547 /* After restoring sp from the frame pointer. */
23548 op
= 0x90 | unwind
.fp_reg
;
23549 add_unwind_opcode (op
, 1);
23552 flush_pending_unwind ();
23556 /* Start an exception table entry. If idx is nonzero this is an index table
23560 start_unwind_section (const segT text_seg
, int idx
)
23562 const char * text_name
;
23563 const char * prefix
;
23564 const char * prefix_once
;
23565 const char * group_name
;
23573 prefix
= ELF_STRING_ARM_unwind
;
23574 prefix_once
= ELF_STRING_ARM_unwind_once
;
23575 type
= SHT_ARM_EXIDX
;
23579 prefix
= ELF_STRING_ARM_unwind_info
;
23580 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
23581 type
= SHT_PROGBITS
;
23584 text_name
= segment_name (text_seg
);
23585 if (streq (text_name
, ".text"))
23588 if (strncmp (text_name
, ".gnu.linkonce.t.",
23589 strlen (".gnu.linkonce.t.")) == 0)
23591 prefix
= prefix_once
;
23592 text_name
+= strlen (".gnu.linkonce.t.");
23595 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
23601 /* Handle COMDAT group. */
23602 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
23604 group_name
= elf_group_name (text_seg
);
23605 if (group_name
== NULL
)
23607 as_bad (_("Group section `%s' has no group signature"),
23608 segment_name (text_seg
));
23609 ignore_rest_of_line ();
23612 flags
|= SHF_GROUP
;
23616 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
23619 /* Set the section link for index tables. */
23621 elf_linked_to_section (now_seg
) = text_seg
;
23625 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
23626 personality routine data. Returns zero, or the index table value for
23627 an inline entry. */
23630 create_unwind_entry (int have_data
)
23635 /* The current word of data. */
23637 /* The number of bytes left in this word. */
23640 finish_unwind_opcodes ();
23642 /* Remember the current text section. */
23643 unwind
.saved_seg
= now_seg
;
23644 unwind
.saved_subseg
= now_subseg
;
23646 start_unwind_section (now_seg
, 0);
23648 if (unwind
.personality_routine
== NULL
)
23650 if (unwind
.personality_index
== -2)
23653 as_bad (_("handlerdata in cantunwind frame"));
23654 return 1; /* EXIDX_CANTUNWIND. */
23657 /* Use a default personality routine if none is specified. */
23658 if (unwind
.personality_index
== -1)
23660 if (unwind
.opcode_count
> 3)
23661 unwind
.personality_index
= 1;
23663 unwind
.personality_index
= 0;
23666 /* Space for the personality routine entry. */
23667 if (unwind
.personality_index
== 0)
23669 if (unwind
.opcode_count
> 3)
23670 as_bad (_("too many unwind opcodes for personality routine 0"));
23674 /* All the data is inline in the index table. */
23677 while (unwind
.opcode_count
> 0)
23679 unwind
.opcode_count
--;
23680 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
23684 /* Pad with "finish" opcodes. */
23686 data
= (data
<< 8) | 0xb0;
23693 /* We get two opcodes "free" in the first word. */
23694 size
= unwind
.opcode_count
- 2;
23698 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
23699 if (unwind
.personality_index
!= -1)
23701 as_bad (_("attempt to recreate an unwind entry"));
23705 /* An extra byte is required for the opcode count. */
23706 size
= unwind
.opcode_count
+ 1;
23709 size
= (size
+ 3) >> 2;
23711 as_bad (_("too many unwind opcodes"));
23713 frag_align (2, 0, 0);
23714 record_alignment (now_seg
, 2);
23715 unwind
.table_entry
= expr_build_dot ();
23717 /* Allocate the table entry. */
23718 ptr
= frag_more ((size
<< 2) + 4);
23719 /* PR 13449: Zero the table entries in case some of them are not used. */
23720 memset (ptr
, 0, (size
<< 2) + 4);
23721 where
= frag_now_fix () - ((size
<< 2) + 4);
23723 switch (unwind
.personality_index
)
23726 /* ??? Should this be a PLT generating relocation? */
23727 /* Custom personality routine. */
23728 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
23729 BFD_RELOC_ARM_PREL31
);
23734 /* Set the first byte to the number of additional words. */
23735 data
= size
> 0 ? size
- 1 : 0;
23739 /* ABI defined personality routines. */
23741 /* Three opcodes bytes are packed into the first word. */
23748 /* The size and first two opcode bytes go in the first word. */
23749 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
23754 /* Should never happen. */
23758 /* Pack the opcodes into words (MSB first), reversing the list at the same
23760 while (unwind
.opcode_count
> 0)
23764 md_number_to_chars (ptr
, data
, 4);
23769 unwind
.opcode_count
--;
23771 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
23774 /* Finish off the last word. */
23777 /* Pad with "finish" opcodes. */
23779 data
= (data
<< 8) | 0xb0;
23781 md_number_to_chars (ptr
, data
, 4);
23786 /* Add an empty descriptor if there is no user-specified data. */
23787 ptr
= frag_more (4);
23788 md_number_to_chars (ptr
, 0, 4);
23795 /* Initialize the DWARF-2 unwind information for this procedure. */
23798 tc_arm_frame_initial_instructions (void)
23800 cfi_add_CFA_def_cfa (REG_SP
, 0);
23802 #endif /* OBJ_ELF */
23804 /* Convert REGNAME to a DWARF-2 register number. */
23807 tc_arm_regname_to_dw2regnum (char *regname
)
23809 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
23813 /* PR 16694: Allow VFP registers as well. */
23814 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
23818 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
23827 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
23831 exp
.X_op
= O_secrel
;
23832 exp
.X_add_symbol
= symbol
;
23833 exp
.X_add_number
= 0;
23834 emit_expr (&exp
, size
);
23838 /* MD interface: Symbol and relocation handling. */
23840 /* Return the address within the segment that a PC-relative fixup is
23841 relative to. For ARM, PC-relative fixups applied to instructions
23842 are generally relative to the location of the fixup plus 8 bytes.
23843 Thumb branches are offset by 4, and Thumb loads relative to PC
23844 require special handling. */
23847 md_pcrel_from_section (fixS
* fixP
, segT seg
)
23849 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23851 /* If this is pc-relative and we are going to emit a relocation
23852 then we just want to put out any pipeline compensation that the linker
23853 will need. Otherwise we want to use the calculated base.
23854 For WinCE we skip the bias for externals as well, since this
23855 is how the MS ARM-CE assembler behaves and we want to be compatible. */
23857 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23858 || (arm_force_relocation (fixP
)
23860 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
23866 switch (fixP
->fx_r_type
)
23868 /* PC relative addressing on the Thumb is slightly odd as the
23869 bottom two bits of the PC are forced to zero for the
23870 calculation. This happens *after* application of the
23871 pipeline offset. However, Thumb adrl already adjusts for
23872 this, so we need not do it again. */
23873 case BFD_RELOC_ARM_THUMB_ADD
:
23876 case BFD_RELOC_ARM_THUMB_OFFSET
:
23877 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23878 case BFD_RELOC_ARM_T32_ADD_PC12
:
23879 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23880 return (base
+ 4) & ~3;
23882 /* Thumb branches are simply offset by +4. */
23883 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
23884 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23885 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23886 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23887 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23888 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23889 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
23890 case BFD_RELOC_ARM_THUMB_BF17
:
23891 case BFD_RELOC_ARM_THUMB_BF19
:
23892 case BFD_RELOC_ARM_THUMB_BF13
:
23893 case BFD_RELOC_ARM_THUMB_LOOP12
:
23896 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23898 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23900 && ARM_IS_FUNC (fixP
->fx_addsy
)
23901 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23902 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23905 /* BLX is like branches above, but forces the low two bits of PC to
23907 case BFD_RELOC_THUMB_PCREL_BLX
:
23909 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23910 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23911 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23912 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23913 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23914 return (base
+ 4) & ~3;
23916 /* ARM mode branches are offset by +8. However, the Windows CE
23917 loader expects the relocation not to take this into account. */
23918 case BFD_RELOC_ARM_PCREL_BLX
:
23920 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23921 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23922 && ARM_IS_FUNC (fixP
->fx_addsy
)
23923 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23924 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23927 case BFD_RELOC_ARM_PCREL_CALL
:
23929 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23930 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23931 && THUMB_IS_FUNC (fixP
->fx_addsy
)
23932 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23933 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23936 case BFD_RELOC_ARM_PCREL_BRANCH
:
23937 case BFD_RELOC_ARM_PCREL_JUMP
:
23938 case BFD_RELOC_ARM_PLT32
:
23940 /* When handling fixups immediately, because we have already
23941 discovered the value of a symbol, or the address of the frag involved
23942 we must account for the offset by +8, as the OS loader will never see the reloc.
23943 see fixup_segment() in write.c
23944 The S_IS_EXTERNAL test handles the case of global symbols.
23945 Those need the calculated base, not just the pipe compensation the linker will need. */
23947 && fixP
->fx_addsy
!= NULL
23948 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23949 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
23957 /* ARM mode loads relative to PC are also offset by +8. Unlike
23958 branches, the Windows CE loader *does* expect the relocation
23959 to take this into account. */
23960 case BFD_RELOC_ARM_OFFSET_IMM
:
23961 case BFD_RELOC_ARM_OFFSET_IMM8
:
23962 case BFD_RELOC_ARM_HWLITERAL
:
23963 case BFD_RELOC_ARM_LITERAL
:
23964 case BFD_RELOC_ARM_CP_OFF_IMM
:
23968 /* Other PC-relative relocations are un-offset. */
23974 static bfd_boolean flag_warn_syms
= TRUE
;
23977 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
23979 /* PR 18347 - Warn if the user attempts to create a symbol with the same
23980 name as an ARM instruction. Whilst strictly speaking it is allowed, it
23981 does mean that the resulting code might be very confusing to the reader.
23982 Also this warning can be triggered if the user omits an operand before
23983 an immediate address, eg:
23987 GAS treats this as an assignment of the value of the symbol foo to a
23988 symbol LDR, and so (without this code) it will not issue any kind of
23989 warning or error message.
23991 Note - ARM instructions are case-insensitive but the strings in the hash
23992 table are all stored in lower case, so we must first ensure that name is
23994 if (flag_warn_syms
&& arm_ops_hsh
)
23996 char * nbuf
= strdup (name
);
23999 for (p
= nbuf
; *p
; p
++)
24001 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
24003 static struct hash_control
* already_warned
= NULL
;
24005 if (already_warned
== NULL
)
24006 already_warned
= hash_new ();
24007 /* Only warn about the symbol once. To keep the code
24008 simple we let hash_insert do the lookup for us. */
24009 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
24010 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
24019 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
24020 Otherwise we have no need to default values of symbols. */
24023 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
24026 if (name
[0] == '_' && name
[1] == 'G'
24027 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
24031 if (symbol_find (name
))
24032 as_bad (_("GOT already in the symbol table"));
24034 GOT_symbol
= symbol_new (name
, undefined_section
,
24035 (valueT
) 0, & zero_address_frag
);
24045 /* Subroutine of md_apply_fix. Check to see if an immediate can be
24046 computed as two separate immediate values, added together. We
24047 already know that this value cannot be computed by just one ARM
24050 static unsigned int
24051 validate_immediate_twopart (unsigned int val
,
24052 unsigned int * highpart
)
24057 for (i
= 0; i
< 32; i
+= 2)
24058 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
24064 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
24066 else if (a
& 0xff0000)
24068 if (a
& 0xff000000)
24070 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
24074 gas_assert (a
& 0xff000000);
24075 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
24078 return (a
& 0xff) | (i
<< 7);
24085 validate_offset_imm (unsigned int val
, int hwse
)
24087 if ((hwse
&& val
> 255) || val
> 4095)
24092 /* Subroutine of md_apply_fix. Do those data_ops which can take a
24093 negative immediate constant by altering the instruction. A bit of
24098 by inverting the second operand, and
24101 by negating the second operand. */
24104 negate_data_op (unsigned long * instruction
,
24105 unsigned long value
)
24108 unsigned long negated
, inverted
;
24110 negated
= encode_arm_immediate (-value
);
24111 inverted
= encode_arm_immediate (~value
);
24113 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
24116 /* First negates. */
24117 case OPCODE_SUB
: /* ADD <-> SUB */
24118 new_inst
= OPCODE_ADD
;
24123 new_inst
= OPCODE_SUB
;
24127 case OPCODE_CMP
: /* CMP <-> CMN */
24128 new_inst
= OPCODE_CMN
;
24133 new_inst
= OPCODE_CMP
;
24137 /* Now Inverted ops. */
24138 case OPCODE_MOV
: /* MOV <-> MVN */
24139 new_inst
= OPCODE_MVN
;
24144 new_inst
= OPCODE_MOV
;
24148 case OPCODE_AND
: /* AND <-> BIC */
24149 new_inst
= OPCODE_BIC
;
24154 new_inst
= OPCODE_AND
;
24158 case OPCODE_ADC
: /* ADC <-> SBC */
24159 new_inst
= OPCODE_SBC
;
24164 new_inst
= OPCODE_ADC
;
24168 /* We cannot do anything. */
24173 if (value
== (unsigned) FAIL
)
24176 *instruction
&= OPCODE_MASK
;
24177 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
24181 /* Like negate_data_op, but for Thumb-2. */
24183 static unsigned int
24184 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
24188 unsigned int negated
, inverted
;
24190 negated
= encode_thumb32_immediate (-value
);
24191 inverted
= encode_thumb32_immediate (~value
);
24193 rd
= (*instruction
>> 8) & 0xf;
24194 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
24197 /* ADD <-> SUB. Includes CMP <-> CMN. */
24198 case T2_OPCODE_SUB
:
24199 new_inst
= T2_OPCODE_ADD
;
24203 case T2_OPCODE_ADD
:
24204 new_inst
= T2_OPCODE_SUB
;
24208 /* ORR <-> ORN. Includes MOV <-> MVN. */
24209 case T2_OPCODE_ORR
:
24210 new_inst
= T2_OPCODE_ORN
;
24214 case T2_OPCODE_ORN
:
24215 new_inst
= T2_OPCODE_ORR
;
24219 /* AND <-> BIC. TST has no inverted equivalent. */
24220 case T2_OPCODE_AND
:
24221 new_inst
= T2_OPCODE_BIC
;
24228 case T2_OPCODE_BIC
:
24229 new_inst
= T2_OPCODE_AND
;
24234 case T2_OPCODE_ADC
:
24235 new_inst
= T2_OPCODE_SBC
;
24239 case T2_OPCODE_SBC
:
24240 new_inst
= T2_OPCODE_ADC
;
24244 /* We cannot do anything. */
24249 if (value
== (unsigned int)FAIL
)
24252 *instruction
&= T2_OPCODE_MASK
;
24253 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
24257 /* Read a 32-bit thumb instruction from buf. */
24259 static unsigned long
24260 get_thumb32_insn (char * buf
)
24262 unsigned long insn
;
24263 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
24264 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24269 /* We usually want to set the low bit on the address of thumb function
24270 symbols. In particular .word foo - . should have the low bit set.
24271 Generic code tries to fold the difference of two symbols to
24272 a constant. Prevent this and force a relocation when the first symbols
24273 is a thumb function. */
24276 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
24278 if (op
== O_subtract
24279 && l
->X_op
== O_symbol
24280 && r
->X_op
== O_symbol
24281 && THUMB_IS_FUNC (l
->X_add_symbol
))
24283 l
->X_op
= O_subtract
;
24284 l
->X_op_symbol
= r
->X_add_symbol
;
24285 l
->X_add_number
-= r
->X_add_number
;
24289 /* Process as normal. */
24293 /* Encode Thumb2 unconditional branches and calls. The encoding
24294 for the 2 are identical for the immediate values. */
24297 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
24299 #define T2I1I2MASK ((1 << 13) | (1 << 11))
24302 addressT S
, I1
, I2
, lo
, hi
;
24304 S
= (value
>> 24) & 0x01;
24305 I1
= (value
>> 23) & 0x01;
24306 I2
= (value
>> 22) & 0x01;
24307 hi
= (value
>> 12) & 0x3ff;
24308 lo
= (value
>> 1) & 0x7ff;
24309 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24310 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
24311 newval
|= (S
<< 10) | hi
;
24312 newval2
&= ~T2I1I2MASK
;
24313 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
24314 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24315 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
24319 md_apply_fix (fixS
* fixP
,
24323 offsetT value
= * valP
;
24325 unsigned int newimm
;
24326 unsigned long temp
;
24328 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
24330 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
24332 /* Note whether this will delete the relocation. */
24334 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
24337 /* On a 64-bit host, silently truncate 'value' to 32 bits for
24338 consistency with the behaviour on 32-bit hosts. Remember value
24340 value
&= 0xffffffff;
24341 value
^= 0x80000000;
24342 value
-= 0x80000000;
24345 fixP
->fx_addnumber
= value
;
24347 /* Same treatment for fixP->fx_offset. */
24348 fixP
->fx_offset
&= 0xffffffff;
24349 fixP
->fx_offset
^= 0x80000000;
24350 fixP
->fx_offset
-= 0x80000000;
24352 switch (fixP
->fx_r_type
)
24354 case BFD_RELOC_NONE
:
24355 /* This will need to go in the object file. */
24359 case BFD_RELOC_ARM_IMMEDIATE
:
24360 /* We claim that this fixup has been processed here,
24361 even if in fact we generate an error because we do
24362 not have a reloc for it, so tc_gen_reloc will reject it. */
24365 if (fixP
->fx_addsy
)
24367 const char *msg
= 0;
24369 if (! S_IS_DEFINED (fixP
->fx_addsy
))
24370 msg
= _("undefined symbol %s used as an immediate value");
24371 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
24372 msg
= _("symbol %s is in a different section");
24373 else if (S_IS_WEAK (fixP
->fx_addsy
))
24374 msg
= _("symbol %s is weak and may be overridden later");
24378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24379 msg
, S_GET_NAME (fixP
->fx_addsy
));
24384 temp
= md_chars_to_number (buf
, INSN_SIZE
);
24386 /* If the offset is negative, we should use encoding A2 for ADR. */
24387 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
24388 newimm
= negate_data_op (&temp
, value
);
24391 newimm
= encode_arm_immediate (value
);
24393 /* If the instruction will fail, see if we can fix things up by
24394 changing the opcode. */
24395 if (newimm
== (unsigned int) FAIL
)
24396 newimm
= negate_data_op (&temp
, value
);
24397 /* MOV accepts both ARM modified immediate (A1 encoding) and
24398 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
24399 When disassembling, MOV is preferred when there is no encoding
24401 if (newimm
== (unsigned int) FAIL
24402 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
24403 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
24404 && !((temp
>> SBIT_SHIFT
) & 0x1)
24405 && value
>= 0 && value
<= 0xffff)
24407 /* Clear bits[23:20] to change encoding from A1 to A2. */
24408 temp
&= 0xff0fffff;
24409 /* Encoding high 4bits imm. Code below will encode the remaining
24411 temp
|= (value
& 0x0000f000) << 4;
24412 newimm
= value
& 0x00000fff;
24416 if (newimm
== (unsigned int) FAIL
)
24418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24419 _("invalid constant (%lx) after fixup"),
24420 (unsigned long) value
);
24424 newimm
|= (temp
& 0xfffff000);
24425 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
24428 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24430 unsigned int highpart
= 0;
24431 unsigned int newinsn
= 0xe1a00000; /* nop. */
24433 if (fixP
->fx_addsy
)
24435 const char *msg
= 0;
24437 if (! S_IS_DEFINED (fixP
->fx_addsy
))
24438 msg
= _("undefined symbol %s used as an immediate value");
24439 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
24440 msg
= _("symbol %s is in a different section");
24441 else if (S_IS_WEAK (fixP
->fx_addsy
))
24442 msg
= _("symbol %s is weak and may be overridden later");
24446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24447 msg
, S_GET_NAME (fixP
->fx_addsy
));
24452 newimm
= encode_arm_immediate (value
);
24453 temp
= md_chars_to_number (buf
, INSN_SIZE
);
24455 /* If the instruction will fail, see if we can fix things up by
24456 changing the opcode. */
24457 if (newimm
== (unsigned int) FAIL
24458 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
24460 /* No ? OK - try using two ADD instructions to generate
24462 newimm
= validate_immediate_twopart (value
, & highpart
);
24464 /* Yes - then make sure that the second instruction is
24466 if (newimm
!= (unsigned int) FAIL
)
24468 /* Still No ? Try using a negated value. */
24469 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
24470 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
24471 /* Otherwise - give up. */
24474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24475 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
24480 /* Replace the first operand in the 2nd instruction (which
24481 is the PC) with the destination register. We have
24482 already added in the PC in the first instruction and we
24483 do not want to do it again. */
24484 newinsn
&= ~ 0xf0000;
24485 newinsn
|= ((newinsn
& 0x0f000) << 4);
24488 newimm
|= (temp
& 0xfffff000);
24489 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
24491 highpart
|= (newinsn
& 0xfffff000);
24492 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
24496 case BFD_RELOC_ARM_OFFSET_IMM
:
24497 if (!fixP
->fx_done
&& seg
->use_rela_p
)
24499 /* Fall through. */
24501 case BFD_RELOC_ARM_LITERAL
:
24507 if (validate_offset_imm (value
, 0) == FAIL
)
24509 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
24510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24511 _("invalid literal constant: pool needs to be closer"));
24513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24514 _("bad immediate value for offset (%ld)"),
24519 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24521 newval
&= 0xfffff000;
24524 newval
&= 0xff7ff000;
24525 newval
|= value
| (sign
? INDEX_UP
: 0);
24527 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24530 case BFD_RELOC_ARM_OFFSET_IMM8
:
24531 case BFD_RELOC_ARM_HWLITERAL
:
24537 if (validate_offset_imm (value
, 1) == FAIL
)
24539 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
24540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24541 _("invalid literal constant: pool needs to be closer"));
24543 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24544 _("bad immediate value for 8-bit offset (%ld)"),
24549 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24551 newval
&= 0xfffff0f0;
24554 newval
&= 0xff7ff0f0;
24555 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
24557 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24560 case BFD_RELOC_ARM_T32_OFFSET_U8
:
24561 if (value
< 0 || value
> 1020 || value
% 4 != 0)
24562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24563 _("bad immediate value for offset (%ld)"), (long) value
);
24566 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
24568 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
24571 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
24572 /* This is a complicated relocation used for all varieties of Thumb32
24573 load/store instruction with immediate offset:
24575 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
24576 *4, optional writeback(W)
24577 (doubleword load/store)
24579 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
24580 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
24581 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
24582 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
24583 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
24585 Uppercase letters indicate bits that are already encoded at
24586 this point. Lowercase letters are our problem. For the
24587 second block of instructions, the secondary opcode nybble
24588 (bits 8..11) is present, and bit 23 is zero, even if this is
24589 a PC-relative operation. */
24590 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24592 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
24594 if ((newval
& 0xf0000000) == 0xe0000000)
24596 /* Doubleword load/store: 8-bit offset, scaled by 4. */
24598 newval
|= (1 << 23);
24601 if (value
% 4 != 0)
24603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24604 _("offset not a multiple of 4"));
24610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24611 _("offset out of range"));
24616 else if ((newval
& 0x000f0000) == 0x000f0000)
24618 /* PC-relative, 12-bit offset. */
24620 newval
|= (1 << 23);
24625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24626 _("offset out of range"));
24631 else if ((newval
& 0x00000100) == 0x00000100)
24633 /* Writeback: 8-bit, +/- offset. */
24635 newval
|= (1 << 9);
24640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24641 _("offset out of range"));
24646 else if ((newval
& 0x00000f00) == 0x00000e00)
24648 /* T-instruction: positive 8-bit offset. */
24649 if (value
< 0 || value
> 0xff)
24651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24652 _("offset out of range"));
24660 /* Positive 12-bit or negative 8-bit offset. */
24664 newval
|= (1 << 23);
24674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24675 _("offset out of range"));
24682 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
24683 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
24686 case BFD_RELOC_ARM_SHIFT_IMM
:
24687 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24688 if (((unsigned long) value
) > 32
24690 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
24692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24693 _("shift expression is too large"));
24698 /* Shifts of zero must be done as lsl. */
24700 else if (value
== 32)
24702 newval
&= 0xfffff07f;
24703 newval
|= (value
& 0x1f) << 7;
24704 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24707 case BFD_RELOC_ARM_T32_IMMEDIATE
:
24708 case BFD_RELOC_ARM_T32_ADD_IMM
:
24709 case BFD_RELOC_ARM_T32_IMM12
:
24710 case BFD_RELOC_ARM_T32_ADD_PC12
:
24711 /* We claim that this fixup has been processed here,
24712 even if in fact we generate an error because we do
24713 not have a reloc for it, so tc_gen_reloc will reject it. */
24717 && ! S_IS_DEFINED (fixP
->fx_addsy
))
24719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24720 _("undefined symbol %s used as an immediate value"),
24721 S_GET_NAME (fixP
->fx_addsy
));
24725 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24727 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
24730 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24731 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
24732 Thumb2 modified immediate encoding (T2). */
24733 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
24734 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
24736 newimm
= encode_thumb32_immediate (value
);
24737 if (newimm
== (unsigned int) FAIL
)
24738 newimm
= thumb32_negate_data_op (&newval
, value
);
24740 if (newimm
== (unsigned int) FAIL
)
24742 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
24744 /* Turn add/sum into addw/subw. */
24745 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
24746 newval
= (newval
& 0xfeffffff) | 0x02000000;
24747 /* No flat 12-bit imm encoding for addsw/subsw. */
24748 if ((newval
& 0x00100000) == 0)
24750 /* 12 bit immediate for addw/subw. */
24754 newval
^= 0x00a00000;
24757 newimm
= (unsigned int) FAIL
;
24764 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
24765 UINT16 (T3 encoding), MOVW only accepts UINT16. When
24766 disassembling, MOV is preferred when there is no encoding
24768 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
24769 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
24770 but with the Rn field [19:16] set to 1111. */
24771 && (((newval
>> 16) & 0xf) == 0xf)
24772 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
24773 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
24774 && value
>= 0 && value
<= 0xffff)
24776 /* Toggle bit[25] to change encoding from T2 to T3. */
24778 /* Clear bits[19:16]. */
24779 newval
&= 0xfff0ffff;
24780 /* Encoding high 4bits imm. Code below will encode the
24781 remaining low 12bits. */
24782 newval
|= (value
& 0x0000f000) << 4;
24783 newimm
= value
& 0x00000fff;
24788 if (newimm
== (unsigned int)FAIL
)
24790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24791 _("invalid constant (%lx) after fixup"),
24792 (unsigned long) value
);
24796 newval
|= (newimm
& 0x800) << 15;
24797 newval
|= (newimm
& 0x700) << 4;
24798 newval
|= (newimm
& 0x0ff);
24800 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
24801 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
24804 case BFD_RELOC_ARM_SMC
:
24805 if (((unsigned long) value
) > 0xffff)
24806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24807 _("invalid smc expression"));
24808 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24809 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
24810 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24813 case BFD_RELOC_ARM_HVC
:
24814 if (((unsigned long) value
) > 0xffff)
24815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24816 _("invalid hvc expression"));
24817 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24818 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
24819 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24822 case BFD_RELOC_ARM_SWI
:
24823 if (fixP
->tc_fix_data
!= 0)
24825 if (((unsigned long) value
) > 0xff)
24826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24827 _("invalid swi expression"));
24828 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24830 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24834 if (((unsigned long) value
) > 0x00ffffff)
24835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24836 _("invalid swi expression"));
24837 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24839 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24843 case BFD_RELOC_ARM_MULTI
:
24844 if (((unsigned long) value
) > 0xffff)
24845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24846 _("invalid expression in load/store multiple"));
24847 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
24848 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24852 case BFD_RELOC_ARM_PCREL_CALL
:
24854 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24856 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24857 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24858 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24859 /* Flip the bl to blx. This is a simple flip
24860 bit here because we generate PCREL_CALL for
24861 unconditional bls. */
24863 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24864 newval
= newval
| 0x10000000;
24865 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24871 goto arm_branch_common
;
24873 case BFD_RELOC_ARM_PCREL_JUMP
:
24874 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24876 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24877 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24878 && THUMB_IS_FUNC (fixP
->fx_addsy
))
24880 /* This would map to a bl<cond>, b<cond>,
24881 b<always> to a Thumb function. We
24882 need to force a relocation for this particular
24884 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24887 /* Fall through. */
24889 case BFD_RELOC_ARM_PLT32
:
24891 case BFD_RELOC_ARM_PCREL_BRANCH
:
24893 goto arm_branch_common
;
24895 case BFD_RELOC_ARM_PCREL_BLX
:
24898 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24900 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
24901 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
24902 && ARM_IS_FUNC (fixP
->fx_addsy
))
24904 /* Flip the blx to a bl and warn. */
24905 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
24906 newval
= 0xeb000000;
24907 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
24908 _("blx to '%s' an ARM ISA state function changed to bl"),
24910 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24916 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24917 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
24921 /* We are going to store value (shifted right by two) in the
24922 instruction, in a 24 bit, signed field. Bits 26 through 32 either
24923 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
24926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24927 _("misaligned branch destination"));
24928 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
24929 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
24930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24932 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24934 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24935 newval
|= (value
>> 2) & 0x00ffffff;
24936 /* Set the H bit on BLX instructions. */
24940 newval
|= 0x01000000;
24942 newval
&= ~0x01000000;
24944 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24948 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
24949 /* CBZ can only branch forward. */
24951 /* Attempts to use CBZ to branch to the next instruction
24952 (which, strictly speaking, are prohibited) will be turned into
24955 FIXME: It may be better to remove the instruction completely and
24956 perform relaxation. */
24959 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24960 newval
= 0xbf00; /* NOP encoding T1 */
24961 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24968 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24970 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24971 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
24972 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24977 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
24978 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
24979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24981 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24983 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24984 newval
|= (value
& 0x1ff) >> 1;
24985 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24989 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
24990 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
24991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
24993 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24995 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24996 newval
|= (value
& 0xfff) >> 1;
24997 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25001 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25003 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25004 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25005 && ARM_IS_FUNC (fixP
->fx_addsy
)
25006 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25008 /* Force a relocation for a branch 20 bits wide. */
25011 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
25012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25013 _("conditional branch out of range"));
25015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25018 addressT S
, J1
, J2
, lo
, hi
;
25020 S
= (value
& 0x00100000) >> 20;
25021 J2
= (value
& 0x00080000) >> 19;
25022 J1
= (value
& 0x00040000) >> 18;
25023 hi
= (value
& 0x0003f000) >> 12;
25024 lo
= (value
& 0x00000ffe) >> 1;
25026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25027 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25028 newval
|= (S
<< 10) | hi
;
25029 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
25030 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25031 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25035 case BFD_RELOC_THUMB_PCREL_BLX
:
25036 /* If there is a blx from a thumb state function to
25037 another thumb function flip this to a bl and warn
25041 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25043 && THUMB_IS_FUNC (fixP
->fx_addsy
))
25045 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
25046 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
25047 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
25049 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25050 newval
= newval
| 0x1000;
25051 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
25052 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25057 goto thumb_bl_common
;
25059 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25060 /* A bl from Thumb state ISA to an internal ARM state function
25061 is converted to a blx. */
25063 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25064 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25065 && ARM_IS_FUNC (fixP
->fx_addsy
)
25066 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25068 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25069 newval
= newval
& ~0x1000;
25070 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
25071 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
25077 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
25078 /* For a BLX instruction, make sure that the relocation is rounded up
25079 to a word boundary. This follows the semantics of the instruction
25080 which specifies that bit 1 of the target address will come from bit
25081 1 of the base address. */
25082 value
= (value
+ 3) & ~ 3;
25085 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
25086 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
25087 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
25090 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
25092 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
25093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
25094 else if ((value
& ~0x1ffffff)
25095 && ((value
& ~0x1ffffff) != ~0x1ffffff))
25096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25097 _("Thumb2 branch out of range"));
25100 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25101 encode_thumb2_b_bl_offset (buf
, value
);
25105 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25106 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
25107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
25109 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25110 encode_thumb2_b_bl_offset (buf
, value
);
25115 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25120 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25121 md_number_to_chars (buf
, value
, 2);
25125 case BFD_RELOC_ARM_TLS_CALL
:
25126 case BFD_RELOC_ARM_THM_TLS_CALL
:
25127 case BFD_RELOC_ARM_TLS_DESCSEQ
:
25128 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
25129 case BFD_RELOC_ARM_TLS_GOTDESC
:
25130 case BFD_RELOC_ARM_TLS_GD32
:
25131 case BFD_RELOC_ARM_TLS_LE32
:
25132 case BFD_RELOC_ARM_TLS_IE32
:
25133 case BFD_RELOC_ARM_TLS_LDM32
:
25134 case BFD_RELOC_ARM_TLS_LDO32
:
25135 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
25138 /* Same handling as above, but with the arm_fdpic guard. */
25139 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
25140 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
25141 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
25144 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
25148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25149 _("Relocation supported only in FDPIC mode"));
25153 case BFD_RELOC_ARM_GOT32
:
25154 case BFD_RELOC_ARM_GOTOFF
:
25157 case BFD_RELOC_ARM_GOT_PREL
:
25158 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25159 md_number_to_chars (buf
, value
, 4);
25162 case BFD_RELOC_ARM_TARGET2
:
25163 /* TARGET2 is not partial-inplace, so we need to write the
25164 addend here for REL targets, because it won't be written out
25165 during reloc processing later. */
25166 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25167 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
25170 /* Relocations for FDPIC. */
25171 case BFD_RELOC_ARM_GOTFUNCDESC
:
25172 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
25173 case BFD_RELOC_ARM_FUNCDESC
:
25176 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25177 md_number_to_chars (buf
, 0, 4);
25181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25182 _("Relocation supported only in FDPIC mode"));
25187 case BFD_RELOC_RVA
:
25189 case BFD_RELOC_ARM_TARGET1
:
25190 case BFD_RELOC_ARM_ROSEGREL32
:
25191 case BFD_RELOC_ARM_SBREL32
:
25192 case BFD_RELOC_32_PCREL
:
25194 case BFD_RELOC_32_SECREL
:
25196 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25198 /* For WinCE we only do this for pcrel fixups. */
25199 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
25201 md_number_to_chars (buf
, value
, 4);
25205 case BFD_RELOC_ARM_PREL31
:
25206 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25208 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
25209 if ((value
^ (value
>> 1)) & 0x40000000)
25211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25212 _("rel31 relocation overflow"));
25214 newval
|= value
& 0x7fffffff;
25215 md_number_to_chars (buf
, newval
, 4);
25220 case BFD_RELOC_ARM_CP_OFF_IMM
:
25221 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
25222 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
25223 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
25224 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25226 newval
= get_thumb32_insn (buf
);
25227 if ((newval
& 0x0f200f00) == 0x0d000900)
25229 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
25230 has permitted values that are multiples of 2, in the range 0
25232 if (value
< -510 || value
> 510 || (value
& 1))
25233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25234 _("co-processor offset out of range"));
25236 else if ((newval
& 0xfe001f80) == 0xec000f80)
25238 if (value
< -511 || value
> 512 || (value
& 3))
25239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25240 _("co-processor offset out of range"));
25242 else if (value
< -1023 || value
> 1023 || (value
& 3))
25243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25244 _("co-processor offset out of range"));
25249 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25250 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
25251 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25253 newval
= get_thumb32_insn (buf
);
25256 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
25257 newval
&= 0xffffff80;
25259 newval
&= 0xffffff00;
25263 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
25264 newval
&= 0xff7fff80;
25266 newval
&= 0xff7fff00;
25267 if ((newval
& 0x0f200f00) == 0x0d000900)
25269 /* This is a fp16 vstr/vldr.
25271 It requires the immediate offset in the instruction is shifted
25272 left by 1 to be a half-word offset.
25274 Here, left shift by 1 first, and later right shift by 2
25275 should get the right offset. */
25278 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
25280 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25281 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
25282 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25284 put_thumb32_insn (buf
, newval
);
25287 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
25288 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
25289 if (value
< -255 || value
> 255)
25290 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25291 _("co-processor offset out of range"));
25293 goto cp_off_common
;
25295 case BFD_RELOC_ARM_THUMB_OFFSET
:
25296 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25297 /* Exactly what ranges, and where the offset is inserted depends
25298 on the type of instruction, we can establish this from the
25300 switch (newval
>> 12)
25302 case 4: /* PC load. */
25303 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
25304 forced to zero for these loads; md_pcrel_from has already
25305 compensated for this. */
25307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25308 _("invalid offset, target not word aligned (0x%08lX)"),
25309 (((unsigned long) fixP
->fx_frag
->fr_address
25310 + (unsigned long) fixP
->fx_where
) & ~3)
25311 + (unsigned long) value
);
25313 if (value
& ~0x3fc)
25314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25315 _("invalid offset, value too big (0x%08lX)"),
25318 newval
|= value
>> 2;
25321 case 9: /* SP load/store. */
25322 if (value
& ~0x3fc)
25323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25324 _("invalid offset, value too big (0x%08lX)"),
25326 newval
|= value
>> 2;
25329 case 6: /* Word load/store. */
25331 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25332 _("invalid offset, value too big (0x%08lX)"),
25334 newval
|= value
<< 4; /* 6 - 2. */
25337 case 7: /* Byte load/store. */
25339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25340 _("invalid offset, value too big (0x%08lX)"),
25342 newval
|= value
<< 6;
25345 case 8: /* Halfword load/store. */
25347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25348 _("invalid offset, value too big (0x%08lX)"),
25350 newval
|= value
<< 5; /* 6 - 1. */
25354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25355 "Unable to process relocation for thumb opcode: %lx",
25356 (unsigned long) newval
);
25359 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25362 case BFD_RELOC_ARM_THUMB_ADD
:
25363 /* This is a complicated relocation, since we use it for all of
25364 the following immediate relocations:
25368 9bit ADD/SUB SP word-aligned
25369 10bit ADD PC/SP word-aligned
25371 The type of instruction being processed is encoded in the
25378 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25380 int rd
= (newval
>> 4) & 0xf;
25381 int rs
= newval
& 0xf;
25382 int subtract
= !!(newval
& 0x8000);
25384 /* Check for HI regs, only very restricted cases allowed:
25385 Adjusting SP, and using PC or SP to get an address. */
25386 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
25387 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
25388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25389 _("invalid Hi register with immediate"));
25391 /* If value is negative, choose the opposite instruction. */
25395 subtract
= !subtract
;
25397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25398 _("immediate value out of range"));
25403 if (value
& ~0x1fc)
25404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25405 _("invalid immediate for stack address calculation"));
25406 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
25407 newval
|= value
>> 2;
25409 else if (rs
== REG_PC
|| rs
== REG_SP
)
25411 /* PR gas/18541. If the addition is for a defined symbol
25412 within range of an ADR instruction then accept it. */
25415 && fixP
->fx_addsy
!= NULL
)
25419 if (! S_IS_DEFINED (fixP
->fx_addsy
)
25420 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
25421 || S_IS_WEAK (fixP
->fx_addsy
))
25423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25424 _("address calculation needs a strongly defined nearby symbol"));
25428 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25430 /* Round up to the next 4-byte boundary. */
25435 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
25439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25440 _("symbol too far away"));
25450 if (subtract
|| value
& ~0x3fc)
25451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25452 _("invalid immediate for address calculation (value = 0x%08lX)"),
25453 (unsigned long) (subtract
? - value
: value
));
25454 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
25456 newval
|= value
>> 2;
25461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25462 _("immediate value out of range"));
25463 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
25464 newval
|= (rd
<< 8) | value
;
25469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25470 _("immediate value out of range"));
25471 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
25472 newval
|= rd
| (rs
<< 3) | (value
<< 6);
25475 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25478 case BFD_RELOC_ARM_THUMB_IMM
:
25479 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25480 if (value
< 0 || value
> 255)
25481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25482 _("invalid immediate: %ld is out of range"),
25485 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25488 case BFD_RELOC_ARM_THUMB_SHIFT
:
25489 /* 5bit shift value (0..32). LSL cannot take 32. */
25490 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
25491 temp
= newval
& 0xf800;
25492 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
25493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25494 _("invalid shift value: %ld"), (long) value
);
25495 /* Shifts of zero must be encoded as LSL. */
25497 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
25498 /* Shifts of 32 are encoded as zero. */
25499 else if (value
== 32)
25501 newval
|= value
<< 6;
25502 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25505 case BFD_RELOC_VTABLE_INHERIT
:
25506 case BFD_RELOC_VTABLE_ENTRY
:
25510 case BFD_RELOC_ARM_MOVW
:
25511 case BFD_RELOC_ARM_MOVT
:
25512 case BFD_RELOC_ARM_THUMB_MOVW
:
25513 case BFD_RELOC_ARM_THUMB_MOVT
:
25514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25516 /* REL format relocations are limited to a 16-bit addend. */
25517 if (!fixP
->fx_done
)
25519 if (value
< -0x8000 || value
> 0x7fff)
25520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25521 _("offset out of range"));
25523 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25524 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
25529 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25530 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
25532 newval
= get_thumb32_insn (buf
);
25533 newval
&= 0xfbf08f00;
25534 newval
|= (value
& 0xf000) << 4;
25535 newval
|= (value
& 0x0800) << 15;
25536 newval
|= (value
& 0x0700) << 4;
25537 newval
|= (value
& 0x00ff);
25538 put_thumb32_insn (buf
, newval
);
25542 newval
= md_chars_to_number (buf
, 4);
25543 newval
&= 0xfff0f000;
25544 newval
|= value
& 0x0fff;
25545 newval
|= (value
& 0xf000) << 4;
25546 md_number_to_chars (buf
, newval
, 4);
25551 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
25552 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
25553 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
25554 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
25555 gas_assert (!fixP
->fx_done
);
25558 bfd_boolean is_mov
;
25559 bfd_vma encoded_addend
= value
;
25561 /* Check that addend can be encoded in instruction. */
25562 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
25563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25564 _("the offset 0x%08lX is not representable"),
25565 (unsigned long) encoded_addend
);
25567 /* Extract the instruction. */
25568 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
25569 is_mov
= (insn
& 0xf800) == 0x2000;
25574 if (!seg
->use_rela_p
)
25575 insn
|= encoded_addend
;
25581 /* Extract the instruction. */
25582 /* Encoding is the following
25587 /* The following conditions must be true :
25592 rd
= (insn
>> 4) & 0xf;
25594 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
25595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25596 _("Unable to process relocation for thumb opcode: %lx"),
25597 (unsigned long) insn
);
25599 /* Encode as ADD immediate8 thumb 1 code. */
25600 insn
= 0x3000 | (rd
<< 8);
25602 /* Place the encoded addend into the first 8 bits of the
25604 if (!seg
->use_rela_p
)
25605 insn
|= encoded_addend
;
25608 /* Update the instruction. */
25609 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
25613 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
25614 case BFD_RELOC_ARM_ALU_PC_G0
:
25615 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
25616 case BFD_RELOC_ARM_ALU_PC_G1
:
25617 case BFD_RELOC_ARM_ALU_PC_G2
:
25618 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
25619 case BFD_RELOC_ARM_ALU_SB_G0
:
25620 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
25621 case BFD_RELOC_ARM_ALU_SB_G1
:
25622 case BFD_RELOC_ARM_ALU_SB_G2
:
25623 gas_assert (!fixP
->fx_done
);
25624 if (!seg
->use_rela_p
)
25627 bfd_vma encoded_addend
;
25628 bfd_vma addend_abs
= llabs (value
);
25630 /* Check that the absolute value of the addend can be
25631 expressed as an 8-bit constant plus a rotation. */
25632 encoded_addend
= encode_arm_immediate (addend_abs
);
25633 if (encoded_addend
== (unsigned int) FAIL
)
25634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25635 _("the offset 0x%08lX is not representable"),
25636 (unsigned long) addend_abs
);
25638 /* Extract the instruction. */
25639 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25641 /* If the addend is positive, use an ADD instruction.
25642 Otherwise use a SUB. Take care not to destroy the S bit. */
25643 insn
&= 0xff1fffff;
25649 /* Place the encoded addend into the first 12 bits of the
25651 insn
&= 0xfffff000;
25652 insn
|= encoded_addend
;
25654 /* Update the instruction. */
25655 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25659 case BFD_RELOC_ARM_LDR_PC_G0
:
25660 case BFD_RELOC_ARM_LDR_PC_G1
:
25661 case BFD_RELOC_ARM_LDR_PC_G2
:
25662 case BFD_RELOC_ARM_LDR_SB_G0
:
25663 case BFD_RELOC_ARM_LDR_SB_G1
:
25664 case BFD_RELOC_ARM_LDR_SB_G2
:
25665 gas_assert (!fixP
->fx_done
);
25666 if (!seg
->use_rela_p
)
25669 bfd_vma addend_abs
= llabs (value
);
25671 /* Check that the absolute value of the addend can be
25672 encoded in 12 bits. */
25673 if (addend_abs
>= 0x1000)
25674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25675 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
25676 (unsigned long) addend_abs
);
25678 /* Extract the instruction. */
25679 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25681 /* If the addend is negative, clear bit 23 of the instruction.
25682 Otherwise set it. */
25684 insn
&= ~(1 << 23);
25688 /* Place the absolute value of the addend into the first 12 bits
25689 of the instruction. */
25690 insn
&= 0xfffff000;
25691 insn
|= addend_abs
;
25693 /* Update the instruction. */
25694 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25698 case BFD_RELOC_ARM_LDRS_PC_G0
:
25699 case BFD_RELOC_ARM_LDRS_PC_G1
:
25700 case BFD_RELOC_ARM_LDRS_PC_G2
:
25701 case BFD_RELOC_ARM_LDRS_SB_G0
:
25702 case BFD_RELOC_ARM_LDRS_SB_G1
:
25703 case BFD_RELOC_ARM_LDRS_SB_G2
:
25704 gas_assert (!fixP
->fx_done
);
25705 if (!seg
->use_rela_p
)
25708 bfd_vma addend_abs
= llabs (value
);
25710 /* Check that the absolute value of the addend can be
25711 encoded in 8 bits. */
25712 if (addend_abs
>= 0x100)
25713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25714 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
25715 (unsigned long) addend_abs
);
25717 /* Extract the instruction. */
25718 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25720 /* If the addend is negative, clear bit 23 of the instruction.
25721 Otherwise set it. */
25723 insn
&= ~(1 << 23);
25727 /* Place the first four bits of the absolute value of the addend
25728 into the first 4 bits of the instruction, and the remaining
25729 four into bits 8 .. 11. */
25730 insn
&= 0xfffff0f0;
25731 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
25733 /* Update the instruction. */
25734 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25738 case BFD_RELOC_ARM_LDC_PC_G0
:
25739 case BFD_RELOC_ARM_LDC_PC_G1
:
25740 case BFD_RELOC_ARM_LDC_PC_G2
:
25741 case BFD_RELOC_ARM_LDC_SB_G0
:
25742 case BFD_RELOC_ARM_LDC_SB_G1
:
25743 case BFD_RELOC_ARM_LDC_SB_G2
:
25744 gas_assert (!fixP
->fx_done
);
25745 if (!seg
->use_rela_p
)
25748 bfd_vma addend_abs
= llabs (value
);
25750 /* Check that the absolute value of the addend is a multiple of
25751 four and, when divided by four, fits in 8 bits. */
25752 if (addend_abs
& 0x3)
25753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25754 _("bad offset 0x%08lX (must be word-aligned)"),
25755 (unsigned long) addend_abs
);
25757 if ((addend_abs
>> 2) > 0xff)
25758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25759 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
25760 (unsigned long) addend_abs
);
25762 /* Extract the instruction. */
25763 insn
= md_chars_to_number (buf
, INSN_SIZE
);
25765 /* If the addend is negative, clear bit 23 of the instruction.
25766 Otherwise set it. */
25768 insn
&= ~(1 << 23);
25772 /* Place the addend (divided by four) into the first eight
25773 bits of the instruction. */
25774 insn
&= 0xfffffff0;
25775 insn
|= addend_abs
>> 2;
25777 /* Update the instruction. */
25778 md_number_to_chars (buf
, insn
, INSN_SIZE
);
25782 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25784 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25785 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25786 && ARM_IS_FUNC (fixP
->fx_addsy
)
25787 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25789 /* Force a relocation for a branch 5 bits wide. */
25792 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
25793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25796 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25798 addressT boff
= value
>> 1;
25800 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25801 newval
|= (boff
<< 7);
25802 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25806 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25808 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25809 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25810 && ARM_IS_FUNC (fixP
->fx_addsy
)
25811 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25815 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
25816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25817 _("branch out of range"));
25819 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25821 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25823 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
25824 addressT diff
= value
- boff
;
25828 newval
|= 1 << 1; /* T bit. */
25830 else if (diff
!= 2)
25832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25833 _("out of range label-relative fixup value"));
25835 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25839 case BFD_RELOC_ARM_THUMB_BF17
:
25841 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25842 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25843 && ARM_IS_FUNC (fixP
->fx_addsy
)
25844 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25846 /* Force a relocation for a branch 17 bits wide. */
25850 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
25851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25857 addressT immA
, immB
, immC
;
25859 immA
= (value
& 0x0001f000) >> 12;
25860 immB
= (value
& 0x00000ffc) >> 2;
25861 immC
= (value
& 0x00000002) >> 1;
25863 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25864 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25866 newval2
|= (immC
<< 11) | (immB
<< 1);
25867 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25868 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25872 case BFD_RELOC_ARM_THUMB_BF19
:
25874 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25875 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25876 && ARM_IS_FUNC (fixP
->fx_addsy
)
25877 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25879 /* Force a relocation for a branch 19 bits wide. */
25883 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
25884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25887 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25890 addressT immA
, immB
, immC
;
25892 immA
= (value
& 0x0007f000) >> 12;
25893 immB
= (value
& 0x00000ffc) >> 2;
25894 immC
= (value
& 0x00000002) >> 1;
25896 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25897 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25899 newval2
|= (immC
<< 11) | (immB
<< 1);
25900 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25901 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25905 case BFD_RELOC_ARM_THUMB_BF13
:
25907 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25908 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25909 && ARM_IS_FUNC (fixP
->fx_addsy
)
25910 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25912 /* Force a relocation for a branch 13 bits wide. */
25916 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
25917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25920 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25923 addressT immA
, immB
, immC
;
25925 immA
= (value
& 0x00001000) >> 12;
25926 immB
= (value
& 0x00000ffc) >> 2;
25927 immC
= (value
& 0x00000002) >> 1;
25929 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25930 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25932 newval2
|= (immC
<< 11) | (immB
<< 1);
25933 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25934 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25938 case BFD_RELOC_ARM_THUMB_LOOP12
:
25940 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25941 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25942 && ARM_IS_FUNC (fixP
->fx_addsy
)
25943 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
25945 /* Force a relocation for a branch 12 bits wide. */
25949 bfd_vma insn
= get_thumb32_insn (buf
);
25950 /* le lr, <label> or le <label> */
25951 if (((insn
& 0xffffffff) == 0xf00fc001)
25952 || ((insn
& 0xffffffff) == 0xf02fc001))
25955 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
25956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
25960 addressT imml
, immh
;
25962 immh
= (value
& 0x00000ffc) >> 2;
25963 imml
= (value
& 0x00000002) >> 1;
25965 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25966 newval
|= (imml
<< 11) | (immh
<< 1);
25967 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
25971 case BFD_RELOC_ARM_V4BX
:
25972 /* This will need to go in the object file. */
25976 case BFD_RELOC_UNUSED
:
25978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25979 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
25983 /* Translate internal representation of relocation info to BFD target
25987 tc_gen_reloc (asection
*section
, fixS
*fixp
)
25990 bfd_reloc_code_real_type code
;
25992 reloc
= XNEW (arelent
);
25994 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
25995 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
25996 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
25998 if (fixp
->fx_pcrel
)
26000 if (section
->use_rela_p
)
26001 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
26003 fixp
->fx_offset
= reloc
->address
;
26005 reloc
->addend
= fixp
->fx_offset
;
26007 switch (fixp
->fx_r_type
)
26010 if (fixp
->fx_pcrel
)
26012 code
= BFD_RELOC_8_PCREL
;
26015 /* Fall through. */
26018 if (fixp
->fx_pcrel
)
26020 code
= BFD_RELOC_16_PCREL
;
26023 /* Fall through. */
26026 if (fixp
->fx_pcrel
)
26028 code
= BFD_RELOC_32_PCREL
;
26031 /* Fall through. */
26033 case BFD_RELOC_ARM_MOVW
:
26034 if (fixp
->fx_pcrel
)
26036 code
= BFD_RELOC_ARM_MOVW_PCREL
;
26039 /* Fall through. */
26041 case BFD_RELOC_ARM_MOVT
:
26042 if (fixp
->fx_pcrel
)
26044 code
= BFD_RELOC_ARM_MOVT_PCREL
;
26047 /* Fall through. */
26049 case BFD_RELOC_ARM_THUMB_MOVW
:
26050 if (fixp
->fx_pcrel
)
26052 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
26055 /* Fall through. */
26057 case BFD_RELOC_ARM_THUMB_MOVT
:
26058 if (fixp
->fx_pcrel
)
26060 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
26063 /* Fall through. */
26065 case BFD_RELOC_NONE
:
26066 case BFD_RELOC_ARM_PCREL_BRANCH
:
26067 case BFD_RELOC_ARM_PCREL_BLX
:
26068 case BFD_RELOC_RVA
:
26069 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26070 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26071 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26072 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26073 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26074 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26075 case BFD_RELOC_VTABLE_ENTRY
:
26076 case BFD_RELOC_VTABLE_INHERIT
:
26078 case BFD_RELOC_32_SECREL
:
26080 code
= fixp
->fx_r_type
;
26083 case BFD_RELOC_THUMB_PCREL_BLX
:
26085 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
26086 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26089 code
= BFD_RELOC_THUMB_PCREL_BLX
;
26092 case BFD_RELOC_ARM_LITERAL
:
26093 case BFD_RELOC_ARM_HWLITERAL
:
26094 /* If this is called then the a literal has
26095 been referenced across a section boundary. */
26096 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26097 _("literal referenced across section boundary"));
26101 case BFD_RELOC_ARM_TLS_CALL
:
26102 case BFD_RELOC_ARM_THM_TLS_CALL
:
26103 case BFD_RELOC_ARM_TLS_DESCSEQ
:
26104 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
26105 case BFD_RELOC_ARM_GOT32
:
26106 case BFD_RELOC_ARM_GOTOFF
:
26107 case BFD_RELOC_ARM_GOT_PREL
:
26108 case BFD_RELOC_ARM_PLT32
:
26109 case BFD_RELOC_ARM_TARGET1
:
26110 case BFD_RELOC_ARM_ROSEGREL32
:
26111 case BFD_RELOC_ARM_SBREL32
:
26112 case BFD_RELOC_ARM_PREL31
:
26113 case BFD_RELOC_ARM_TARGET2
:
26114 case BFD_RELOC_ARM_TLS_LDO32
:
26115 case BFD_RELOC_ARM_PCREL_CALL
:
26116 case BFD_RELOC_ARM_PCREL_JUMP
:
26117 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
26118 case BFD_RELOC_ARM_ALU_PC_G0
:
26119 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
26120 case BFD_RELOC_ARM_ALU_PC_G1
:
26121 case BFD_RELOC_ARM_ALU_PC_G2
:
26122 case BFD_RELOC_ARM_LDR_PC_G0
:
26123 case BFD_RELOC_ARM_LDR_PC_G1
:
26124 case BFD_RELOC_ARM_LDR_PC_G2
:
26125 case BFD_RELOC_ARM_LDRS_PC_G0
:
26126 case BFD_RELOC_ARM_LDRS_PC_G1
:
26127 case BFD_RELOC_ARM_LDRS_PC_G2
:
26128 case BFD_RELOC_ARM_LDC_PC_G0
:
26129 case BFD_RELOC_ARM_LDC_PC_G1
:
26130 case BFD_RELOC_ARM_LDC_PC_G2
:
26131 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
26132 case BFD_RELOC_ARM_ALU_SB_G0
:
26133 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
26134 case BFD_RELOC_ARM_ALU_SB_G1
:
26135 case BFD_RELOC_ARM_ALU_SB_G2
:
26136 case BFD_RELOC_ARM_LDR_SB_G0
:
26137 case BFD_RELOC_ARM_LDR_SB_G1
:
26138 case BFD_RELOC_ARM_LDR_SB_G2
:
26139 case BFD_RELOC_ARM_LDRS_SB_G0
:
26140 case BFD_RELOC_ARM_LDRS_SB_G1
:
26141 case BFD_RELOC_ARM_LDRS_SB_G2
:
26142 case BFD_RELOC_ARM_LDC_SB_G0
:
26143 case BFD_RELOC_ARM_LDC_SB_G1
:
26144 case BFD_RELOC_ARM_LDC_SB_G2
:
26145 case BFD_RELOC_ARM_V4BX
:
26146 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
26147 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
26148 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
26149 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
26150 case BFD_RELOC_ARM_GOTFUNCDESC
:
26151 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
26152 case BFD_RELOC_ARM_FUNCDESC
:
26153 case BFD_RELOC_ARM_THUMB_BF17
:
26154 case BFD_RELOC_ARM_THUMB_BF19
:
26155 case BFD_RELOC_ARM_THUMB_BF13
:
26156 code
= fixp
->fx_r_type
;
26159 case BFD_RELOC_ARM_TLS_GOTDESC
:
26160 case BFD_RELOC_ARM_TLS_GD32
:
26161 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
26162 case BFD_RELOC_ARM_TLS_LE32
:
26163 case BFD_RELOC_ARM_TLS_IE32
:
26164 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
26165 case BFD_RELOC_ARM_TLS_LDM32
:
26166 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
26167 /* BFD will include the symbol's address in the addend.
26168 But we don't want that, so subtract it out again here. */
26169 if (!S_IS_COMMON (fixp
->fx_addsy
))
26170 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
26171 code
= fixp
->fx_r_type
;
26175 case BFD_RELOC_ARM_IMMEDIATE
:
26176 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26177 _("internal relocation (type: IMMEDIATE) not fixed up"));
26180 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
26181 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26182 _("ADRL used for a symbol not defined in the same file"));
26185 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26186 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26187 case BFD_RELOC_ARM_THUMB_LOOP12
:
26188 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26189 _("%s used for a symbol not defined in the same file"),
26190 bfd_get_reloc_code_name (fixp
->fx_r_type
));
26193 case BFD_RELOC_ARM_OFFSET_IMM
:
26194 if (section
->use_rela_p
)
26196 code
= fixp
->fx_r_type
;
26200 if (fixp
->fx_addsy
!= NULL
26201 && !S_IS_DEFINED (fixp
->fx_addsy
)
26202 && S_IS_LOCAL (fixp
->fx_addsy
))
26204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26205 _("undefined local label `%s'"),
26206 S_GET_NAME (fixp
->fx_addsy
));
26210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26211 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
26218 switch (fixp
->fx_r_type
)
26220 case BFD_RELOC_NONE
: type
= "NONE"; break;
26221 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
26222 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
26223 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
26224 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
26225 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
26226 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
26227 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
26228 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
26229 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
26230 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
26231 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
26232 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
26233 default: type
= _("<unknown>"); break;
26235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26236 _("cannot represent %s relocation in this object file format"),
26243 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
26245 && fixp
->fx_addsy
== GOT_symbol
)
26247 code
= BFD_RELOC_ARM_GOTPC
;
26248 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
26252 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
26254 if (reloc
->howto
== NULL
)
26256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
26257 _("cannot represent %s relocation in this object file format"),
26258 bfd_get_reloc_code_name (code
));
26262 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
26263 vtable entry to be used in the relocation's section offset. */
26264 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
26265 reloc
->address
= fixp
->fx_offset
;
26270 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
26273 cons_fix_new_arm (fragS
* frag
,
26277 bfd_reloc_code_real_type reloc
)
26282 FIXME: @@ Should look at CPU word size. */
26286 reloc
= BFD_RELOC_8
;
26289 reloc
= BFD_RELOC_16
;
26293 reloc
= BFD_RELOC_32
;
26296 reloc
= BFD_RELOC_64
;
26301 if (exp
->X_op
== O_secrel
)
26303 exp
->X_op
= O_symbol
;
26304 reloc
= BFD_RELOC_32_SECREL
;
26308 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
26311 #if defined (OBJ_COFF)
26313 arm_validate_fix (fixS
* fixP
)
26315 /* If the destination of the branch is a defined symbol which does not have
26316 the THUMB_FUNC attribute, then we must be calling a function which has
26317 the (interfacearm) attribute. We look for the Thumb entry point to that
26318 function and change the branch to refer to that function instead. */
26319 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
26320 && fixP
->fx_addsy
!= NULL
26321 && S_IS_DEFINED (fixP
->fx_addsy
)
26322 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
26324 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
26331 arm_force_relocation (struct fix
* fixp
)
26333 #if defined (OBJ_COFF) && defined (TE_PE)
26334 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
26338 /* In case we have a call or a branch to a function in ARM ISA mode from
26339 a thumb function or vice-versa force the relocation. These relocations
26340 are cleared off for some cores that might have blx and simple transformations
26344 switch (fixp
->fx_r_type
)
26346 case BFD_RELOC_ARM_PCREL_JUMP
:
26347 case BFD_RELOC_ARM_PCREL_CALL
:
26348 case BFD_RELOC_THUMB_PCREL_BLX
:
26349 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
26353 case BFD_RELOC_ARM_PCREL_BLX
:
26354 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26355 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26356 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26357 if (ARM_IS_FUNC (fixp
->fx_addsy
))
26366 /* Resolve these relocations even if the symbol is extern or weak.
26367 Technically this is probably wrong due to symbol preemption.
26368 In practice these relocations do not have enough range to be useful
26369 at dynamic link time, and some code (e.g. in the Linux kernel)
26370 expects these references to be resolved. */
26371 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
26372 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
26373 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
26374 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
26375 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26376 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
26377 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
26378 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
26379 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
26381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
26382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
26383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
26384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
26387 /* Always leave these relocations for the linker. */
26388 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
26389 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
26390 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
26393 /* Always generate relocations against function symbols. */
26394 if (fixp
->fx_r_type
== BFD_RELOC_32
26396 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
26399 return generic_force_reloc (fixp
);
26402 #if defined (OBJ_ELF) || defined (OBJ_COFF)
26403 /* Relocations against function names must be left unadjusted,
26404 so that the linker can use this information to generate interworking
26405 stubs. The MIPS version of this function
26406 also prevents relocations that are mips-16 specific, but I do not
26407 know why it does this.
26410 There is one other problem that ought to be addressed here, but
26411 which currently is not: Taking the address of a label (rather
26412 than a function) and then later jumping to that address. Such
26413 addresses also ought to have their bottom bit set (assuming that
26414 they reside in Thumb code), but at the moment they will not. */
26417 arm_fix_adjustable (fixS
* fixP
)
26419 if (fixP
->fx_addsy
== NULL
)
26422 /* Preserve relocations against symbols with function type. */
26423 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
26426 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
26427 && fixP
->fx_subsy
== NULL
)
26430 /* We need the symbol name for the VTABLE entries. */
26431 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
26432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
26435 /* Don't allow symbols to be discarded on GOT related relocs. */
26436 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
26437 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
26438 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
26439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
26440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
26441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
26442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
26443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
26444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
26445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
26446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
26447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
26448 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
26449 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
26450 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
26451 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
26452 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
26455 /* Similarly for group relocations. */
26456 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
26457 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
26458 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
26461 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
26462 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
26463 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
26464 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
26465 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
26466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
26467 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
26468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
26469 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
26472 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
26473 offsets, so keep these symbols. */
26474 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
26475 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
26480 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
26484 elf32_arm_target_format (void)
26487 return (target_big_endian
26488 ? "elf32-bigarm-symbian"
26489 : "elf32-littlearm-symbian");
26490 #elif defined (TE_VXWORKS)
26491 return (target_big_endian
26492 ? "elf32-bigarm-vxworks"
26493 : "elf32-littlearm-vxworks");
26494 #elif defined (TE_NACL)
26495 return (target_big_endian
26496 ? "elf32-bigarm-nacl"
26497 : "elf32-littlearm-nacl");
26501 if (target_big_endian
)
26502 return "elf32-bigarm-fdpic";
26504 return "elf32-littlearm-fdpic";
26508 if (target_big_endian
)
26509 return "elf32-bigarm";
26511 return "elf32-littlearm";
26517 armelf_frob_symbol (symbolS
* symp
,
26520 elf_frob_symbol (symp
, puntp
);
26524 /* MD interface: Finalization. */
26529 literal_pool
* pool
;
26531 /* Ensure that all the predication blocks are properly closed. */
26532 check_pred_blocks_finished ();
26534 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
26536 /* Put it at the end of the relevant section. */
26537 subseg_set (pool
->section
, pool
->sub_section
);
26539 arm_elf_change_section ();
26546 /* Remove any excess mapping symbols generated for alignment frags in
26547 SEC. We may have created a mapping symbol before a zero byte
26548 alignment; remove it if there's a mapping symbol after the
26551 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
26552 void *dummy ATTRIBUTE_UNUSED
)
26554 segment_info_type
*seginfo
= seg_info (sec
);
26557 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
26560 for (fragp
= seginfo
->frchainP
->frch_root
;
26562 fragp
= fragp
->fr_next
)
26564 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
26565 fragS
*next
= fragp
->fr_next
;
26567 /* Variable-sized frags have been converted to fixed size by
26568 this point. But if this was variable-sized to start with,
26569 there will be a fixed-size frag after it. So don't handle
26571 if (sym
== NULL
|| next
== NULL
)
26574 if (S_GET_VALUE (sym
) < next
->fr_address
)
26575 /* Not at the end of this frag. */
26577 know (S_GET_VALUE (sym
) == next
->fr_address
);
26581 if (next
->tc_frag_data
.first_map
!= NULL
)
26583 /* Next frag starts with a mapping symbol. Discard this
26585 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
26589 if (next
->fr_next
== NULL
)
26591 /* This mapping symbol is at the end of the section. Discard
26593 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
26594 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
26598 /* As long as we have empty frags without any mapping symbols,
26600 /* If the next frag is non-empty and does not start with a
26601 mapping symbol, then this mapping symbol is required. */
26602 if (next
->fr_address
!= next
->fr_next
->fr_address
)
26605 next
= next
->fr_next
;
26607 while (next
!= NULL
);
26612 /* Adjust the symbol table. This marks Thumb symbols as distinct from
26616 arm_adjust_symtab (void)
26621 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
26623 if (ARM_IS_THUMB (sym
))
26625 if (THUMB_IS_FUNC (sym
))
26627 /* Mark the symbol as a Thumb function. */
26628 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
26629 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
26630 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
26632 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
26633 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
26635 as_bad (_("%s: unexpected function type: %d"),
26636 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
26638 else switch (S_GET_STORAGE_CLASS (sym
))
26641 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
26644 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
26647 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
26655 if (ARM_IS_INTERWORK (sym
))
26656 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
26663 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
26665 if (ARM_IS_THUMB (sym
))
26667 elf_symbol_type
* elf_sym
;
26669 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
26670 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
26672 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
26673 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
26675 /* If it's a .thumb_func, declare it as so,
26676 otherwise tag label as .code 16. */
26677 if (THUMB_IS_FUNC (sym
))
26678 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
26679 ST_BRANCH_TO_THUMB
);
26680 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26681 elf_sym
->internal_elf_sym
.st_info
=
26682 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
26687 /* Remove any overlapping mapping symbols generated by alignment frags. */
26688 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
26689 /* Now do generic ELF adjustments. */
26690 elf_adjust_symtab ();
26694 /* MD interface: Initialization. */
26697 set_constant_flonums (void)
26701 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
26702 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
26706 /* Auto-select Thumb mode if it's the only available instruction set for the
26707 given architecture. */
26710 autoselect_thumb_from_cpu_variant (void)
26712 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
26713 opcode_select (16);
26722 if ( (arm_ops_hsh
= hash_new ()) == NULL
26723 || (arm_cond_hsh
= hash_new ()) == NULL
26724 || (arm_vcond_hsh
= hash_new ()) == NULL
26725 || (arm_shift_hsh
= hash_new ()) == NULL
26726 || (arm_psr_hsh
= hash_new ()) == NULL
26727 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
26728 || (arm_reg_hsh
= hash_new ()) == NULL
26729 || (arm_reloc_hsh
= hash_new ()) == NULL
26730 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
26731 as_fatal (_("virtual memory exhausted"));
26733 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
26734 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
26735 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
26736 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
26737 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
26738 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
26739 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
26740 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
26741 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
26742 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
26743 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
26744 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
26745 (void *) (v7m_psrs
+ i
));
26746 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
26747 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
26749 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
26751 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
26752 (void *) (barrier_opt_names
+ i
));
26754 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
26756 struct reloc_entry
* entry
= reloc_names
+ i
;
26758 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
26759 /* This makes encode_branch() use the EABI versions of this relocation. */
26760 entry
->reloc
= BFD_RELOC_UNUSED
;
26762 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
26766 set_constant_flonums ();
26768 /* Set the cpu variant based on the command-line options. We prefer
26769 -mcpu= over -march= if both are set (as for GCC); and we prefer
26770 -mfpu= over any other way of setting the floating point unit.
26771 Use of legacy options with new options are faulted. */
26774 if (mcpu_cpu_opt
|| march_cpu_opt
)
26775 as_bad (_("use of old and new-style options to set CPU type"));
26777 selected_arch
= *legacy_cpu
;
26779 else if (mcpu_cpu_opt
)
26781 selected_arch
= *mcpu_cpu_opt
;
26782 selected_ext
= *mcpu_ext_opt
;
26784 else if (march_cpu_opt
)
26786 selected_arch
= *march_cpu_opt
;
26787 selected_ext
= *march_ext_opt
;
26789 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
26794 as_bad (_("use of old and new-style options to set FPU type"));
26796 selected_fpu
= *legacy_fpu
;
26799 selected_fpu
= *mfpu_opt
;
26802 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
26803 || defined (TE_NetBSD) || defined (TE_VXWORKS))
26804 /* Some environments specify a default FPU. If they don't, infer it
26805 from the processor. */
26807 selected_fpu
= *mcpu_fpu_opt
;
26808 else if (march_fpu_opt
)
26809 selected_fpu
= *march_fpu_opt
;
26811 selected_fpu
= fpu_default
;
26815 if (ARM_FEATURE_ZERO (selected_fpu
))
26817 if (!no_cpu_selected ())
26818 selected_fpu
= fpu_default
;
26820 selected_fpu
= fpu_arch_fpa
;
26824 if (ARM_FEATURE_ZERO (selected_arch
))
26826 selected_arch
= cpu_default
;
26827 selected_cpu
= selected_arch
;
26829 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
26831 /* Autodection of feature mode: allow all features in cpu_variant but leave
26832 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
26833 after all instruction have been processed and we can decide what CPU
26834 should be selected. */
26835 if (ARM_FEATURE_ZERO (selected_arch
))
26836 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
26838 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
26841 autoselect_thumb_from_cpu_variant ();
26843 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
26845 #if defined OBJ_COFF || defined OBJ_ELF
26847 unsigned int flags
= 0;
26849 #if defined OBJ_ELF
26850 flags
= meabi_flags
;
26852 switch (meabi_flags
)
26854 case EF_ARM_EABI_UNKNOWN
:
26856 /* Set the flags in the private structure. */
26857 if (uses_apcs_26
) flags
|= F_APCS26
;
26858 if (support_interwork
) flags
|= F_INTERWORK
;
26859 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
26860 if (pic_code
) flags
|= F_PIC
;
26861 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
26862 flags
|= F_SOFT_FLOAT
;
26864 switch (mfloat_abi_opt
)
26866 case ARM_FLOAT_ABI_SOFT
:
26867 case ARM_FLOAT_ABI_SOFTFP
:
26868 flags
|= F_SOFT_FLOAT
;
26871 case ARM_FLOAT_ABI_HARD
:
26872 if (flags
& F_SOFT_FLOAT
)
26873 as_bad (_("hard-float conflicts with specified fpu"));
26877 /* Using pure-endian doubles (even if soft-float). */
26878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
26879 flags
|= F_VFP_FLOAT
;
26881 #if defined OBJ_ELF
26882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
26883 flags
|= EF_ARM_MAVERICK_FLOAT
;
26886 case EF_ARM_EABI_VER4
:
26887 case EF_ARM_EABI_VER5
:
26888 /* No additional flags to set. */
26895 bfd_set_private_flags (stdoutput
, flags
);
26897 /* We have run out flags in the COFF header to encode the
26898 status of ATPCS support, so instead we create a dummy,
26899 empty, debug section called .arm.atpcs. */
26904 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
26908 bfd_set_section_flags
26909 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
26910 bfd_set_section_size (stdoutput
, sec
, 0);
26911 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
26917 /* Record the CPU type as well. */
26918 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
26919 mach
= bfd_mach_arm_iWMMXt2
;
26920 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
26921 mach
= bfd_mach_arm_iWMMXt
;
26922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
26923 mach
= bfd_mach_arm_XScale
;
26924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
26925 mach
= bfd_mach_arm_ep9312
;
26926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
26927 mach
= bfd_mach_arm_5TE
;
26928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
26930 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26931 mach
= bfd_mach_arm_5T
;
26933 mach
= bfd_mach_arm_5
;
26935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
26937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
26938 mach
= bfd_mach_arm_4T
;
26940 mach
= bfd_mach_arm_4
;
26942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
26943 mach
= bfd_mach_arm_3M
;
26944 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
26945 mach
= bfd_mach_arm_3
;
26946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
26947 mach
= bfd_mach_arm_2a
;
26948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
26949 mach
= bfd_mach_arm_2
;
26951 mach
= bfd_mach_arm_unknown
;
26953 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
26956 /* Command line processing. */
26959 Invocation line includes a switch not recognized by the base assembler.
26960 See if it's a processor-specific option.
26962 This routine is somewhat complicated by the need for backwards
26963 compatibility (since older releases of gcc can't be changed).
26964 The new options try to make the interface as compatible as
26967 New options (supported) are:
26969 -mcpu=<cpu name> Assemble for selected processor
26970 -march=<architecture name> Assemble for selected architecture
26971 -mfpu=<fpu architecture> Assemble for selected FPU.
26972 -EB/-mbig-endian Big-endian
26973 -EL/-mlittle-endian Little-endian
26974 -k Generate PIC code
26975 -mthumb Start in Thumb mode
26976 -mthumb-interwork Code supports ARM/Thumb interworking
26978 -m[no-]warn-deprecated Warn about deprecated features
26979 -m[no-]warn-syms Warn when symbols match instructions
26981 For now we will also provide support for:
26983 -mapcs-32 32-bit Program counter
26984 -mapcs-26 26-bit Program counter
26985 -macps-float Floats passed in FP registers
26986 -mapcs-reentrant Reentrant code
26988 (sometime these will probably be replaced with -mapcs=<list of options>
26989 and -matpcs=<list of options>)
26991 The remaining options are only supported for back-wards compatibility.
26992 Cpu variants, the arm part is optional:
26993 -m[arm]1 Currently not supported.
26994 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
26995 -m[arm]3 Arm 3 processor
26996 -m[arm]6[xx], Arm 6 processors
26997 -m[arm]7[xx][t][[d]m] Arm 7 processors
26998 -m[arm]8[10] Arm 8 processors
26999 -m[arm]9[20][tdmi] Arm 9 processors
27000 -mstrongarm[110[0]] StrongARM processors
27001 -mxscale XScale processors
27002 -m[arm]v[2345[t[e]]] Arm architectures
27003 -mall All (except the ARM1)
27005 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
27006 -mfpe-old (No float load/store multiples)
27007 -mvfpxd VFP Single precision
27009 -mno-fpu Disable all floating point instructions
27011 The following CPU names are recognized:
27012 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
27013 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
27014 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
27015 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
27016 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
27017 arm10t arm10e, arm1020t, arm1020e, arm10200e,
27018 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
27022 const char * md_shortopts
= "m:k";
27024 #ifdef ARM_BI_ENDIAN
27025 #define OPTION_EB (OPTION_MD_BASE + 0)
27026 #define OPTION_EL (OPTION_MD_BASE + 1)
27028 #if TARGET_BYTES_BIG_ENDIAN
27029 #define OPTION_EB (OPTION_MD_BASE + 0)
27031 #define OPTION_EL (OPTION_MD_BASE + 1)
27034 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
27035 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
27037 struct option md_longopts
[] =
27040 {"EB", no_argument
, NULL
, OPTION_EB
},
27043 {"EL", no_argument
, NULL
, OPTION_EL
},
27045 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
27047 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
27049 {NULL
, no_argument
, NULL
, 0}
27052 size_t md_longopts_size
= sizeof (md_longopts
);
27054 struct arm_option_table
27056 const char * option
; /* Option name to match. */
27057 const char * help
; /* Help information. */
27058 int * var
; /* Variable to change. */
27059 int value
; /* What to change it to. */
27060 const char * deprecated
; /* If non-null, print this message. */
27063 struct arm_option_table arm_opts
[] =
27065 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
27066 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
27067 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
27068 &support_interwork
, 1, NULL
},
27069 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
27070 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
27071 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
27073 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
27074 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
27075 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
27076 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
27079 /* These are recognized by the assembler, but have no affect on code. */
27080 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
27081 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
27083 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
27084 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
27085 &warn_on_deprecated
, 0, NULL
},
27086 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
27087 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
27088 {NULL
, NULL
, NULL
, 0, NULL
}
27091 struct arm_legacy_option_table
27093 const char * option
; /* Option name to match. */
27094 const arm_feature_set
** var
; /* Variable to change. */
27095 const arm_feature_set value
; /* What to change it to. */
27096 const char * deprecated
; /* If non-null, print this message. */
27099 const struct arm_legacy_option_table arm_legacy_opts
[] =
27101 /* DON'T add any new processors to this list -- we want the whole list
27102 to go away... Add them to the processors table instead. */
27103 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
27104 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
27105 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
27106 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
27107 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
27108 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
27109 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
27110 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
27111 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
27112 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
27113 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
27114 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
27115 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
27116 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
27117 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
27118 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
27119 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
27120 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
27121 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
27122 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
27123 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
27124 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
27125 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
27126 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
27127 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
27128 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
27129 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
27130 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
27131 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
27132 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
27133 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
27134 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
27135 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
27136 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
27137 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
27138 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
27139 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
27140 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
27141 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
27142 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
27143 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
27144 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
27145 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
27146 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
27147 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
27148 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
27149 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
27150 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
27151 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
27152 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
27153 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
27154 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
27155 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
27156 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
27157 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
27158 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
27159 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
27160 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
27161 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
27162 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
27163 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
27164 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
27165 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
27166 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
27167 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
27168 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
27169 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
27170 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
27171 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
27172 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
27173 N_("use -mcpu=strongarm110")},
27174 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
27175 N_("use -mcpu=strongarm1100")},
27176 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
27177 N_("use -mcpu=strongarm1110")},
27178 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
27179 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
27180 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
27182 /* Architecture variants -- don't add any more to this list either. */
27183 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
27184 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
27185 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
27186 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
27187 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
27188 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
27189 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
27190 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
27191 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
27192 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
27193 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
27194 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
27195 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
27196 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
27197 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
27198 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
27199 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
27200 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
27202 /* Floating point variants -- don't add any more to this list either. */
27203 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
27204 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
27205 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
27206 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
27207 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
27209 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
27212 struct arm_cpu_option_table
27216 const arm_feature_set value
;
27217 const arm_feature_set ext
;
27218 /* For some CPUs we assume an FPU unless the user explicitly sets
27220 const arm_feature_set default_fpu
;
27221 /* The canonical name of the CPU, or NULL to use NAME converted to upper
27223 const char * canonical_name
;
27226 /* This list should, at a minimum, contain all the cpu names
27227 recognized by GCC. */
27228 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
27230 static const struct arm_cpu_option_table arm_cpus
[] =
27232 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
27235 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
27238 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
27241 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
27244 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
27247 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
27250 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
27253 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
27256 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
27259 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
27262 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
27265 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
27268 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
27271 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
27274 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
27277 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
27280 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
27283 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
27286 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
27289 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
27292 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
27295 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
27298 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
27301 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
27304 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
27307 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
27310 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
27313 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
27316 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
27319 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
27322 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
27325 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
27328 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
27331 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
27334 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
27337 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
27340 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
27343 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
27346 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
27349 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
27352 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
27355 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
27358 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
27361 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
27364 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
27367 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
27371 /* For V5 or later processors we default to using VFP; but the user
27372 should really set the FPU type explicitly. */
27373 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
27376 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
27379 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
27382 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
27385 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
27388 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
27391 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
27394 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
27397 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
27400 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
27403 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
27406 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
27409 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
27412 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
27415 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
27418 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
27421 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
27424 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
27427 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
27430 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
27433 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
27436 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
27439 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
27442 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
27445 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
27448 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
27451 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
27454 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
27457 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
27460 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
27463 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
27466 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
27469 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
27472 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
27475 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
27478 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
27481 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
27482 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
27484 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
27486 FPU_ARCH_NEON_VFP_V4
),
27487 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
27488 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
27489 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
27490 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
27491 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
27492 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
27493 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
27495 FPU_ARCH_NEON_VFP_V4
),
27496 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
27498 FPU_ARCH_NEON_VFP_V4
),
27499 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
27501 FPU_ARCH_NEON_VFP_V4
),
27502 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
27503 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27504 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27505 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
27506 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27507 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27508 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
27509 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27510 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27511 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
27512 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27513 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
27514 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
27515 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27516 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27517 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
27518 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27519 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27520 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
27521 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27522 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27523 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
27524 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27525 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
27526 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
27527 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27528 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
27529 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
27530 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27531 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
27532 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
27535 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
27537 FPU_ARCH_VFP_V3D16
),
27538 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
27539 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
27541 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
27542 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
27543 FPU_ARCH_VFP_V3D16
),
27544 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
27545 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
27546 FPU_ARCH_VFP_V3D16
),
27547 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
27548 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27549 FPU_ARCH_NEON_VFP_ARMV8
),
27550 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
27551 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27553 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
27556 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
27559 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
27562 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
27565 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
27568 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
27571 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
27574 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
27575 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27576 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27577 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
27578 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27579 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
27580 /* ??? XSCALE is really an architecture. */
27581 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
27585 /* ??? iwmmxt is not a processor. */
27586 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
27589 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
27592 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
27597 ARM_CPU_OPT ("ep9312", "ARM920T",
27598 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
27599 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
27601 /* Marvell processors. */
27602 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
27603 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
27604 FPU_ARCH_VFP_V3D16
),
27605 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
27606 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
27607 FPU_ARCH_NEON_VFP_V4
),
27609 /* APM X-Gene family. */
27610 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
27612 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27613 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
27614 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27615 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
27617 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
27621 struct arm_ext_table
27625 const arm_feature_set merge
;
27626 const arm_feature_set clear
;
27629 struct arm_arch_option_table
27633 const arm_feature_set value
;
27634 const arm_feature_set default_fpu
;
27635 const struct arm_ext_table
* ext_table
;
27638 /* Used to add support for +E and +noE extension. */
27639 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
27640 /* Used to add support for a +E extension. */
27641 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
27642 /* Used to add support for a +noE extension. */
27643 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
27645 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
27646 ~0 & ~FPU_ENDIAN_PURE)
27648 static const struct arm_ext_table armv5te_ext_table
[] =
27650 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
27651 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27654 static const struct arm_ext_table armv7_ext_table
[] =
27656 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
27657 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27660 static const struct arm_ext_table armv7ve_ext_table
[] =
27662 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
27663 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
27664 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
27665 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
27666 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
27667 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
27668 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
27670 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
27671 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
27673 /* Aliases for +simd. */
27674 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
27676 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27677 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27678 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
27680 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27683 static const struct arm_ext_table armv7a_ext_table
[] =
27685 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
27686 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
27687 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
27688 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
27689 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
27690 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
27691 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
27693 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
27694 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
27696 /* Aliases for +simd. */
27697 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27698 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
27700 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
27701 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
27703 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
27704 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
27705 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27708 static const struct arm_ext_table armv7r_ext_table
[] =
27710 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
27711 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
27712 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
27713 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
27714 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
27715 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
27716 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27717 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
27718 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27721 static const struct arm_ext_table armv7em_ext_table
[] =
27723 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
27724 /* Alias for +fp, used to be known as fpv4-sp-d16. */
27725 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
27726 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
27727 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
27728 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
27729 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27732 static const struct arm_ext_table armv8a_ext_table
[] =
27734 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
27735 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
27736 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27737 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27739 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27740 should use the +simd option to turn on FP. */
27741 ARM_REMOVE ("fp", ALL_FP
),
27742 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27743 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27744 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27748 static const struct arm_ext_table armv81a_ext_table
[] =
27750 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
27751 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
27752 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27754 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27755 should use the +simd option to turn on FP. */
27756 ARM_REMOVE ("fp", ALL_FP
),
27757 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27758 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27759 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27762 static const struct arm_ext_table armv82a_ext_table
[] =
27764 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
27765 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
27766 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
27767 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
27768 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27769 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27771 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27772 should use the +simd option to turn on FP. */
27773 ARM_REMOVE ("fp", ALL_FP
),
27774 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27775 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27776 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27779 static const struct arm_ext_table armv84a_ext_table
[] =
27781 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27782 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
27783 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
27784 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27786 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27787 should use the +simd option to turn on FP. */
27788 ARM_REMOVE ("fp", ALL_FP
),
27789 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
27790 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
27791 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27794 static const struct arm_ext_table armv85a_ext_table
[] =
27796 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
27797 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
27798 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
27799 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27801 /* Armv8-a does not allow an FP implementation without SIMD, so the user
27802 should use the +simd option to turn on FP. */
27803 ARM_REMOVE ("fp", ALL_FP
),
27804 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27807 static const struct arm_ext_table armv8m_main_ext_table
[] =
27809 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27810 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
27811 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
27812 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
27813 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27816 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
27818 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27819 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
27821 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
27822 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
27825 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
27826 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
27827 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
27828 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
27830 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
27831 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
27832 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
27833 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27836 static const struct arm_ext_table armv8r_ext_table
[] =
27838 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
27839 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
27840 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27841 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
27842 ARM_REMOVE ("fp", ALL_FP
),
27843 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
27844 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
27847 /* This list should, at a minimum, contain all the architecture names
27848 recognized by GCC. */
27849 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
27850 #define ARM_ARCH_OPT2(N, V, DF, ext) \
27851 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
27853 static const struct arm_arch_option_table arm_archs
[] =
27855 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
27856 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
27857 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
27858 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27859 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
27860 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
27861 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
27862 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
27863 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
27864 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
27865 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
27866 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
27867 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
27868 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
27869 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
27870 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
27871 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
27872 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27873 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
27874 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
27875 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
27876 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
27877 kept to preserve existing behaviour. */
27878 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27879 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
27880 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
27881 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
27882 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
27883 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
27884 kept to preserve existing behaviour. */
27885 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27886 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
27887 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
27888 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
27889 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
27890 /* The official spelling of the ARMv7 profile variants is the dashed form.
27891 Accept the non-dashed form for compatibility with old toolchains. */
27892 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27893 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
27894 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27895 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27896 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
27897 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
27898 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
27899 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
27900 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
27901 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
27903 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
27905 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
27906 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
27907 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
27908 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
27909 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
27910 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
27911 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
27912 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
27913 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
27914 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
27915 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
27917 #undef ARM_ARCH_OPT
27919 /* ISA extensions in the co-processor and main instruction set space. */
27921 struct arm_option_extension_value_table
27925 const arm_feature_set merge_value
;
27926 const arm_feature_set clear_value
;
27927 /* List of architectures for which an extension is available. ARM_ARCH_NONE
27928 indicates that an extension is available for all architectures while
27929 ARM_ANY marks an empty entry. */
27930 const arm_feature_set allowed_archs
[2];
27933 /* The following table must be in alphabetical order with a NULL last entry. */
27935 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
27936 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
27938 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
27939 use the context sensitive approach using arm_ext_table's. */
27940 static const struct arm_option_extension_value_table arm_extensions
[] =
27942 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
27943 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27944 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
27945 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
27946 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27947 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
27948 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
27950 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27951 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
27952 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
27953 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
27954 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
27955 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27956 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
27958 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27959 | ARM_EXT2_FP16_FML
),
27960 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
27961 | ARM_EXT2_FP16_FML
),
27963 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27964 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
27965 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27966 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27967 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
27968 Thumb divide instruction. Due to this having the same name as the
27969 previous entry, this will be ignored when doing command-line parsing and
27970 only considered by build attribute selection code. */
27971 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27972 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
27973 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
27974 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
27975 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
27976 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
27977 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
27978 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
27979 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
27980 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27981 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
27982 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
27983 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
27984 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27985 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
27986 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
27987 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
27988 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
27989 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27990 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27991 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
27993 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
27994 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
27995 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27996 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
27997 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
27998 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
27999 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
28000 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
28002 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
28003 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
28004 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
28005 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
28006 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
28007 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
28008 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
28009 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
28011 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
28012 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
28013 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
28014 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
28015 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
28019 /* ISA floating-point and Advanced SIMD extensions. */
28020 struct arm_option_fpu_value_table
28023 const arm_feature_set value
;
28026 /* This list should, at a minimum, contain all the fpu names
28027 recognized by GCC. */
28028 static const struct arm_option_fpu_value_table arm_fpus
[] =
28030 {"softfpa", FPU_NONE
},
28031 {"fpe", FPU_ARCH_FPE
},
28032 {"fpe2", FPU_ARCH_FPE
},
28033 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
28034 {"fpa", FPU_ARCH_FPA
},
28035 {"fpa10", FPU_ARCH_FPA
},
28036 {"fpa11", FPU_ARCH_FPA
},
28037 {"arm7500fe", FPU_ARCH_FPA
},
28038 {"softvfp", FPU_ARCH_VFP
},
28039 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
28040 {"vfp", FPU_ARCH_VFP_V2
},
28041 {"vfp9", FPU_ARCH_VFP_V2
},
28042 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
28043 {"vfp10", FPU_ARCH_VFP_V2
},
28044 {"vfp10-r0", FPU_ARCH_VFP_V1
},
28045 {"vfpxd", FPU_ARCH_VFP_V1xD
},
28046 {"vfpv2", FPU_ARCH_VFP_V2
},
28047 {"vfpv3", FPU_ARCH_VFP_V3
},
28048 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
28049 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
28050 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
28051 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
28052 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
28053 {"arm1020t", FPU_ARCH_VFP_V1
},
28054 {"arm1020e", FPU_ARCH_VFP_V2
},
28055 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
28056 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
28057 {"maverick", FPU_ARCH_MAVERICK
},
28058 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
28059 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
28060 {"neon-fp16", FPU_ARCH_NEON_FP16
},
28061 {"vfpv4", FPU_ARCH_VFP_V4
},
28062 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
28063 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
28064 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
28065 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
28066 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
28067 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
28068 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
28069 {"crypto-neon-fp-armv8",
28070 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
28071 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
28072 {"crypto-neon-fp-armv8.1",
28073 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
28074 {NULL
, ARM_ARCH_NONE
}
28077 struct arm_option_value_table
28083 static const struct arm_option_value_table arm_float_abis
[] =
28085 {"hard", ARM_FLOAT_ABI_HARD
},
28086 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
28087 {"soft", ARM_FLOAT_ABI_SOFT
},
28092 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
28093 static const struct arm_option_value_table arm_eabis
[] =
28095 {"gnu", EF_ARM_EABI_UNKNOWN
},
28096 {"4", EF_ARM_EABI_VER4
},
28097 {"5", EF_ARM_EABI_VER5
},
28102 struct arm_long_option_table
28104 const char * option
; /* Substring to match. */
28105 const char * help
; /* Help information. */
28106 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
28107 const char * deprecated
; /* If non-null, print this message. */
28111 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
28112 arm_feature_set
*ext_set
,
28113 const struct arm_ext_table
*ext_table
)
28115 /* We insist on extensions being specified in alphabetical order, and with
28116 extensions being added before being removed. We achieve this by having
28117 the global ARM_EXTENSIONS table in alphabetical order, and using the
28118 ADDING_VALUE variable to indicate whether we are adding an extension (1)
28119 or removing it (0) and only allowing it to change in the order
28121 const struct arm_option_extension_value_table
* opt
= NULL
;
28122 const arm_feature_set arm_any
= ARM_ANY
;
28123 int adding_value
= -1;
28125 while (str
!= NULL
&& *str
!= 0)
28132 as_bad (_("invalid architectural extension"));
28137 ext
= strchr (str
, '+');
28142 len
= strlen (str
);
28144 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
28146 if (adding_value
!= 0)
28149 opt
= arm_extensions
;
28157 if (adding_value
== -1)
28160 opt
= arm_extensions
;
28162 else if (adding_value
!= 1)
28164 as_bad (_("must specify extensions to add before specifying "
28165 "those to remove"));
28172 as_bad (_("missing architectural extension"));
28176 gas_assert (adding_value
!= -1);
28177 gas_assert (opt
!= NULL
);
28179 if (ext_table
!= NULL
)
28181 const struct arm_ext_table
* ext_opt
= ext_table
;
28182 bfd_boolean found
= FALSE
;
28183 for (; ext_opt
->name
!= NULL
; ext_opt
++)
28184 if (ext_opt
->name_len
== len
28185 && strncmp (ext_opt
->name
, str
, len
) == 0)
28189 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
28190 /* TODO: Option not supported. When we remove the
28191 legacy table this case should error out. */
28194 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
28198 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
28199 /* TODO: Option not supported. When we remove the
28200 legacy table this case should error out. */
28202 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
28214 /* Scan over the options table trying to find an exact match. */
28215 for (; opt
->name
!= NULL
; opt
++)
28216 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
28218 int i
, nb_allowed_archs
=
28219 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
28220 /* Check we can apply the extension to this architecture. */
28221 for (i
= 0; i
< nb_allowed_archs
; i
++)
28224 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
28226 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
28229 if (i
== nb_allowed_archs
)
28231 as_bad (_("extension does not apply to the base architecture"));
28235 /* Add or remove the extension. */
28237 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
28239 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
28241 /* Allowing Thumb division instructions for ARMv7 in autodetection
28242 rely on this break so that duplicate extensions (extensions
28243 with the same name as a previous extension in the list) are not
28244 considered for command-line parsing. */
28248 if (opt
->name
== NULL
)
28250 /* Did we fail to find an extension because it wasn't specified in
28251 alphabetical order, or because it does not exist? */
28253 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28254 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
28257 if (opt
->name
== NULL
)
28258 as_bad (_("unknown architectural extension `%s'"), str
);
28260 as_bad (_("architectural extensions must be specified in "
28261 "alphabetical order"));
28267 /* We should skip the extension we've just matched the next time
28279 arm_parse_cpu (const char *str
)
28281 const struct arm_cpu_option_table
*opt
;
28282 const char *ext
= strchr (str
, '+');
28288 len
= strlen (str
);
28292 as_bad (_("missing cpu name `%s'"), str
);
28296 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
28297 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
28299 mcpu_cpu_opt
= &opt
->value
;
28300 if (mcpu_ext_opt
== NULL
)
28301 mcpu_ext_opt
= XNEW (arm_feature_set
);
28302 *mcpu_ext_opt
= opt
->ext
;
28303 mcpu_fpu_opt
= &opt
->default_fpu
;
28304 if (opt
->canonical_name
)
28306 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
28307 strcpy (selected_cpu_name
, opt
->canonical_name
);
28313 if (len
>= sizeof selected_cpu_name
)
28314 len
= (sizeof selected_cpu_name
) - 1;
28316 for (i
= 0; i
< len
; i
++)
28317 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
28318 selected_cpu_name
[i
] = 0;
28322 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
28327 as_bad (_("unknown cpu `%s'"), str
);
28332 arm_parse_arch (const char *str
)
28334 const struct arm_arch_option_table
*opt
;
28335 const char *ext
= strchr (str
, '+');
28341 len
= strlen (str
);
28345 as_bad (_("missing architecture name `%s'"), str
);
28349 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
28350 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
28352 march_cpu_opt
= &opt
->value
;
28353 if (march_ext_opt
== NULL
)
28354 march_ext_opt
= XNEW (arm_feature_set
);
28355 *march_ext_opt
= arm_arch_none
;
28356 march_fpu_opt
= &opt
->default_fpu
;
28357 strcpy (selected_cpu_name
, opt
->name
);
28360 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
28366 as_bad (_("unknown architecture `%s'\n"), str
);
28371 arm_parse_fpu (const char * str
)
28373 const struct arm_option_fpu_value_table
* opt
;
28375 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
28376 if (streq (opt
->name
, str
))
28378 mfpu_opt
= &opt
->value
;
28382 as_bad (_("unknown floating point format `%s'\n"), str
);
28387 arm_parse_float_abi (const char * str
)
28389 const struct arm_option_value_table
* opt
;
28391 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
28392 if (streq (opt
->name
, str
))
28394 mfloat_abi_opt
= opt
->value
;
28398 as_bad (_("unknown floating point abi `%s'\n"), str
);
28404 arm_parse_eabi (const char * str
)
28406 const struct arm_option_value_table
*opt
;
28408 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
28409 if (streq (opt
->name
, str
))
28411 meabi_flags
= opt
->value
;
28414 as_bad (_("unknown EABI `%s'\n"), str
);
28420 arm_parse_it_mode (const char * str
)
28422 bfd_boolean ret
= TRUE
;
28424 if (streq ("arm", str
))
28425 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
28426 else if (streq ("thumb", str
))
28427 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
28428 else if (streq ("always", str
))
28429 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
28430 else if (streq ("never", str
))
28431 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
28434 as_bad (_("unknown implicit IT mode `%s', should be "\
28435 "arm, thumb, always, or never."), str
);
28443 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
28445 codecomposer_syntax
= TRUE
;
28446 arm_comment_chars
[0] = ';';
28447 arm_line_separator_chars
[0] = 0;
28451 struct arm_long_option_table arm_long_opts
[] =
28453 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
28454 arm_parse_cpu
, NULL
},
28455 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
28456 arm_parse_arch
, NULL
},
28457 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
28458 arm_parse_fpu
, NULL
},
28459 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
28460 arm_parse_float_abi
, NULL
},
28462 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
28463 arm_parse_eabi
, NULL
},
28465 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
28466 arm_parse_it_mode
, NULL
},
28467 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
28468 arm_ccs_mode
, NULL
},
28469 {NULL
, NULL
, 0, NULL
}
28473 md_parse_option (int c
, const char * arg
)
28475 struct arm_option_table
*opt
;
28476 const struct arm_legacy_option_table
*fopt
;
28477 struct arm_long_option_table
*lopt
;
28483 target_big_endian
= 1;
28489 target_big_endian
= 0;
28493 case OPTION_FIX_V4BX
:
28501 #endif /* OBJ_ELF */
28504 /* Listing option. Just ignore these, we don't support additional
28509 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
28511 if (c
== opt
->option
[0]
28512 && ((arg
== NULL
&& opt
->option
[1] == 0)
28513 || streq (arg
, opt
->option
+ 1)))
28515 /* If the option is deprecated, tell the user. */
28516 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
28517 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
28518 arg
? arg
: "", _(opt
->deprecated
));
28520 if (opt
->var
!= NULL
)
28521 *opt
->var
= opt
->value
;
28527 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
28529 if (c
== fopt
->option
[0]
28530 && ((arg
== NULL
&& fopt
->option
[1] == 0)
28531 || streq (arg
, fopt
->option
+ 1)))
28533 /* If the option is deprecated, tell the user. */
28534 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
28535 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
28536 arg
? arg
: "", _(fopt
->deprecated
));
28538 if (fopt
->var
!= NULL
)
28539 *fopt
->var
= &fopt
->value
;
28545 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
28547 /* These options are expected to have an argument. */
28548 if (c
== lopt
->option
[0]
28550 && strncmp (arg
, lopt
->option
+ 1,
28551 strlen (lopt
->option
+ 1)) == 0)
28553 /* If the option is deprecated, tell the user. */
28554 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
28555 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
28556 _(lopt
->deprecated
));
28558 /* Call the sup-option parser. */
28559 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
28570 md_show_usage (FILE * fp
)
28572 struct arm_option_table
*opt
;
28573 struct arm_long_option_table
*lopt
;
28575 fprintf (fp
, _(" ARM-specific assembler options:\n"));
28577 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
28578 if (opt
->help
!= NULL
)
28579 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
28581 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
28582 if (lopt
->help
!= NULL
)
28583 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
28587 -EB assemble code for a big-endian cpu\n"));
28592 -EL assemble code for a little-endian cpu\n"));
28596 --fix-v4bx Allow BX in ARMv4 code\n"));
28600 --fdpic generate an FDPIC object file\n"));
28601 #endif /* OBJ_ELF */
28609 arm_feature_set flags
;
28610 } cpu_arch_ver_table
;
28612 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
28613 chronologically for architectures, with an exception for ARMv6-M and
28614 ARMv6S-M due to legacy reasons. No new architecture should have a
28615 special case. This allows for build attribute selection results to be
28616 stable when new architectures are added. */
28617 static const cpu_arch_ver_table cpu_arch_ver
[] =
28619 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
28620 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
28621 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
28622 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
28623 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
28624 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
28625 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
28626 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
28627 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
28628 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
28629 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
28630 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
28631 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
28632 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
28633 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
28634 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
28635 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
28636 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
28637 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
28638 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
28639 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
28640 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
28641 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
28642 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
28644 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
28645 always selected build attributes to match those of ARMv6-M
28646 (resp. ARMv6S-M). However, due to these architectures being a strict
28647 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
28648 would be selected when fully respecting chronology of architectures.
28649 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
28650 move them before ARMv7 architectures. */
28651 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
28652 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
28654 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
28655 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
28656 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
28657 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
28658 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
28659 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
28660 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
28661 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
28662 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
28663 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
28664 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
28665 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
28666 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
28667 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
28668 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
28669 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
28670 {-1, ARM_ARCH_NONE
}
28673 /* Set an attribute if it has not already been set by the user. */
28676 aeabi_set_attribute_int (int tag
, int value
)
28679 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
28680 || !attributes_set_explicitly
[tag
])
28681 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
28685 aeabi_set_attribute_string (int tag
, const char *value
)
28688 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
28689 || !attributes_set_explicitly
[tag
])
28690 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
28693 /* Return whether features in the *NEEDED feature set are available via
28694 extensions for the architecture whose feature set is *ARCH_FSET. */
28697 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
28698 const arm_feature_set
*needed
)
28700 int i
, nb_allowed_archs
;
28701 arm_feature_set ext_fset
;
28702 const struct arm_option_extension_value_table
*opt
;
28704 ext_fset
= arm_arch_none
;
28705 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
28707 /* Extension does not provide any feature we need. */
28708 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
28712 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
28713 for (i
= 0; i
< nb_allowed_archs
; i
++)
28716 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
28719 /* Extension is available, add it. */
28720 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
28721 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
28725 /* Can we enable all features in *needed? */
28726 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
28729 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
28730 a given architecture feature set *ARCH_EXT_FSET including extension feature
28731 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
28732 - if true, check for an exact match of the architecture modulo extensions;
28733 - otherwise, select build attribute value of the first superset
28734 architecture released so that results remains stable when new architectures
28736 For -march/-mcpu=all the build attribute value of the most featureful
28737 architecture is returned. Tag_CPU_arch_profile result is returned in
28741 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
28742 const arm_feature_set
*ext_fset
,
28743 char *profile
, int exact_match
)
28745 arm_feature_set arch_fset
;
28746 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
28748 /* Select most featureful architecture with all its extensions if building
28749 for -march=all as the feature sets used to set build attributes. */
28750 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
28752 /* Force revisiting of decision for each new architecture. */
28753 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
28755 return TAG_CPU_ARCH_V8
;
28758 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
28760 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
28762 arm_feature_set known_arch_fset
;
28764 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
28767 /* Base architecture match user-specified architecture and
28768 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
28769 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
28774 /* Base architecture match user-specified architecture only
28775 (eg. ARMv6-M in the same case as above). Record it in case we
28776 find a match with above condition. */
28777 else if (p_ver_ret
== NULL
28778 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
28784 /* Architecture has all features wanted. */
28785 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
28787 arm_feature_set added_fset
;
28789 /* Compute features added by this architecture over the one
28790 recorded in p_ver_ret. */
28791 if (p_ver_ret
!= NULL
)
28792 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
28794 /* First architecture that match incl. with extensions, or the
28795 only difference in features over the recorded match is
28796 features that were optional and are now mandatory. */
28797 if (p_ver_ret
== NULL
28798 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
28804 else if (p_ver_ret
== NULL
)
28806 arm_feature_set needed_ext_fset
;
28808 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
28810 /* Architecture has all features needed when using some
28811 extensions. Record it and continue searching in case there
28812 exist an architecture providing all needed features without
28813 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
28815 if (have_ext_for_needed_feat_p (&known_arch_fset
,
28822 if (p_ver_ret
== NULL
)
28826 /* Tag_CPU_arch_profile. */
28827 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
28828 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
28829 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
28830 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
28832 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
28834 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
28838 return p_ver_ret
->val
;
28841 /* Set the public EABI object attributes. */
28844 aeabi_set_public_attributes (void)
28846 char profile
= '\0';
28849 int fp16_optional
= 0;
28850 int skip_exact_match
= 0;
28851 arm_feature_set flags
, flags_arch
, flags_ext
;
28853 /* Autodetection mode, choose the architecture based the instructions
28855 if (no_cpu_selected ())
28857 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
28859 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
28860 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
28862 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
28863 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
28865 /* Code run during relaxation relies on selected_cpu being set. */
28866 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28867 flags_ext
= arm_arch_none
;
28868 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
28869 selected_ext
= flags_ext
;
28870 selected_cpu
= flags
;
28872 /* Otherwise, choose the architecture based on the capabilities of the
28876 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
28877 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
28878 flags_ext
= selected_ext
;
28879 flags
= selected_cpu
;
28881 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
28883 /* Allow the user to override the reported architecture. */
28884 if (!ARM_FEATURE_ZERO (selected_object_arch
))
28886 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
28887 flags_ext
= arm_arch_none
;
28890 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
28892 /* When this function is run again after relaxation has happened there is no
28893 way to determine whether an architecture or CPU was specified by the user:
28894 - selected_cpu is set above for relaxation to work;
28895 - march_cpu_opt is not set if only -mcpu or .cpu is used;
28896 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
28897 Therefore, if not in -march=all case we first try an exact match and fall
28898 back to autodetection. */
28899 if (!skip_exact_match
)
28900 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
28902 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
28904 as_bad (_("no architecture contains all the instructions used\n"));
28906 /* Tag_CPU_name. */
28907 if (selected_cpu_name
[0])
28911 q
= selected_cpu_name
;
28912 if (strncmp (q
, "armv", 4) == 0)
28917 for (i
= 0; q
[i
]; i
++)
28918 q
[i
] = TOUPPER (q
[i
]);
28920 aeabi_set_attribute_string (Tag_CPU_name
, q
);
28923 /* Tag_CPU_arch. */
28924 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
28926 /* Tag_CPU_arch_profile. */
28927 if (profile
!= '\0')
28928 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
28930 /* Tag_DSP_extension. */
28931 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
28932 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
28934 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
28935 /* Tag_ARM_ISA_use. */
28936 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
28937 || ARM_FEATURE_ZERO (flags_arch
))
28938 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
28940 /* Tag_THUMB_ISA_use. */
28941 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
28942 || ARM_FEATURE_ZERO (flags_arch
))
28946 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
28947 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
28949 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
28953 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
28956 /* Tag_VFP_arch. */
28957 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
28958 aeabi_set_attribute_int (Tag_VFP_arch
,
28959 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28961 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
28962 aeabi_set_attribute_int (Tag_VFP_arch
,
28963 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
28965 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
28968 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
28970 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
28972 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
28975 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
28976 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
28977 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
28978 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
28979 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
28981 /* Tag_ABI_HardFP_use. */
28982 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
28983 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
28984 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
28986 /* Tag_WMMX_arch. */
28987 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
28988 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
28989 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
28990 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
28992 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
28993 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
28994 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
28995 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
28996 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
28997 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
28999 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
29001 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
29005 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
29010 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
29011 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
29012 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
29013 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
29015 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
29016 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
29017 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
29021 We set Tag_DIV_use to two when integer divide instructions have been used
29022 in ARM state, or when Thumb integer divide instructions have been used,
29023 but we have no architecture profile set, nor have we any ARM instructions.
29025 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
29026 by the base architecture.
29028 For new architectures we will have to check these tests. */
29029 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
29030 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
29031 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
29032 aeabi_set_attribute_int (Tag_DIV_use
, 0);
29033 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
29034 || (profile
== '\0'
29035 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
29036 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
29037 aeabi_set_attribute_int (Tag_DIV_use
, 2);
29039 /* Tag_MP_extension_use. */
29040 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
29041 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
29043 /* Tag Virtualization_use. */
29044 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
29046 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
29049 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
29052 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
29053 finished and free extension feature bits which will not be used anymore. */
29056 arm_md_post_relax (void)
29058 aeabi_set_public_attributes ();
29059 XDELETE (mcpu_ext_opt
);
29060 mcpu_ext_opt
= NULL
;
29061 XDELETE (march_ext_opt
);
29062 march_ext_opt
= NULL
;
29065 /* Add the default contents for the .ARM.attributes section. */
29070 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29073 aeabi_set_public_attributes ();
29075 #endif /* OBJ_ELF */
29077 /* Parse a .cpu directive. */
29080 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
29082 const struct arm_cpu_option_table
*opt
;
29086 name
= input_line_pointer
;
29087 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
29088 input_line_pointer
++;
29089 saved_char
= *input_line_pointer
;
29090 *input_line_pointer
= 0;
29092 /* Skip the first "all" entry. */
29093 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
29094 if (streq (opt
->name
, name
))
29096 selected_arch
= opt
->value
;
29097 selected_ext
= opt
->ext
;
29098 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29099 if (opt
->canonical_name
)
29100 strcpy (selected_cpu_name
, opt
->canonical_name
);
29104 for (i
= 0; opt
->name
[i
]; i
++)
29105 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
29107 selected_cpu_name
[i
] = 0;
29109 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29111 *input_line_pointer
= saved_char
;
29112 demand_empty_rest_of_line ();
29115 as_bad (_("unknown cpu `%s'"), name
);
29116 *input_line_pointer
= saved_char
;
29117 ignore_rest_of_line ();
29120 /* Parse a .arch directive. */
29123 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
29125 const struct arm_arch_option_table
*opt
;
29129 name
= input_line_pointer
;
29130 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
29131 input_line_pointer
++;
29132 saved_char
= *input_line_pointer
;
29133 *input_line_pointer
= 0;
29135 /* Skip the first "all" entry. */
29136 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
29137 if (streq (opt
->name
, name
))
29139 selected_arch
= opt
->value
;
29140 selected_ext
= arm_arch_none
;
29141 selected_cpu
= selected_arch
;
29142 strcpy (selected_cpu_name
, opt
->name
);
29143 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29144 *input_line_pointer
= saved_char
;
29145 demand_empty_rest_of_line ();
29149 as_bad (_("unknown architecture `%s'\n"), name
);
29150 *input_line_pointer
= saved_char
;
29151 ignore_rest_of_line ();
29154 /* Parse a .object_arch directive. */
29157 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
29159 const struct arm_arch_option_table
*opt
;
29163 name
= input_line_pointer
;
29164 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
29165 input_line_pointer
++;
29166 saved_char
= *input_line_pointer
;
29167 *input_line_pointer
= 0;
29169 /* Skip the first "all" entry. */
29170 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
29171 if (streq (opt
->name
, name
))
29173 selected_object_arch
= opt
->value
;
29174 *input_line_pointer
= saved_char
;
29175 demand_empty_rest_of_line ();
29179 as_bad (_("unknown architecture `%s'\n"), name
);
29180 *input_line_pointer
= saved_char
;
29181 ignore_rest_of_line ();
29184 /* Parse a .arch_extension directive. */
29187 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
29189 const struct arm_option_extension_value_table
*opt
;
29192 int adding_value
= 1;
29194 name
= input_line_pointer
;
29195 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
29196 input_line_pointer
++;
29197 saved_char
= *input_line_pointer
;
29198 *input_line_pointer
= 0;
29200 if (strlen (name
) >= 2
29201 && strncmp (name
, "no", 2) == 0)
29207 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29208 if (streq (opt
->name
, name
))
29210 int i
, nb_allowed_archs
=
29211 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
29212 for (i
= 0; i
< nb_allowed_archs
; i
++)
29215 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
29217 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
29221 if (i
== nb_allowed_archs
)
29223 as_bad (_("architectural extension `%s' is not allowed for the "
29224 "current base architecture"), name
);
29229 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
29232 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
29234 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29235 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29236 *input_line_pointer
= saved_char
;
29237 demand_empty_rest_of_line ();
29238 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
29239 on this return so that duplicate extensions (extensions with the
29240 same name as a previous extension in the list) are not considered
29241 for command-line parsing. */
29245 if (opt
->name
== NULL
)
29246 as_bad (_("unknown architecture extension `%s'\n"), name
);
29248 *input_line_pointer
= saved_char
;
29249 ignore_rest_of_line ();
29252 /* Parse a .fpu directive. */
29255 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
29257 const struct arm_option_fpu_value_table
*opt
;
29261 name
= input_line_pointer
;
29262 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
29263 input_line_pointer
++;
29264 saved_char
= *input_line_pointer
;
29265 *input_line_pointer
= 0;
29267 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
29268 if (streq (opt
->name
, name
))
29270 selected_fpu
= opt
->value
;
29271 #ifndef CPU_DEFAULT
29272 if (no_cpu_selected ())
29273 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29276 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29277 *input_line_pointer
= saved_char
;
29278 demand_empty_rest_of_line ();
29282 as_bad (_("unknown floating point format `%s'\n"), name
);
29283 *input_line_pointer
= saved_char
;
29284 ignore_rest_of_line ();
29287 /* Copy symbol information. */
29290 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
29292 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
29296 /* Given a symbolic attribute NAME, return the proper integer value.
29297 Returns -1 if the attribute is not known. */
29300 arm_convert_symbolic_attribute (const char *name
)
29302 static const struct
29307 attribute_table
[] =
29309 /* When you modify this table you should
29310 also modify the list in doc/c-arm.texi. */
29311 #define T(tag) {#tag, tag}
29312 T (Tag_CPU_raw_name
),
29315 T (Tag_CPU_arch_profile
),
29316 T (Tag_ARM_ISA_use
),
29317 T (Tag_THUMB_ISA_use
),
29321 T (Tag_Advanced_SIMD_arch
),
29322 T (Tag_PCS_config
),
29323 T (Tag_ABI_PCS_R9_use
),
29324 T (Tag_ABI_PCS_RW_data
),
29325 T (Tag_ABI_PCS_RO_data
),
29326 T (Tag_ABI_PCS_GOT_use
),
29327 T (Tag_ABI_PCS_wchar_t
),
29328 T (Tag_ABI_FP_rounding
),
29329 T (Tag_ABI_FP_denormal
),
29330 T (Tag_ABI_FP_exceptions
),
29331 T (Tag_ABI_FP_user_exceptions
),
29332 T (Tag_ABI_FP_number_model
),
29333 T (Tag_ABI_align_needed
),
29334 T (Tag_ABI_align8_needed
),
29335 T (Tag_ABI_align_preserved
),
29336 T (Tag_ABI_align8_preserved
),
29337 T (Tag_ABI_enum_size
),
29338 T (Tag_ABI_HardFP_use
),
29339 T (Tag_ABI_VFP_args
),
29340 T (Tag_ABI_WMMX_args
),
29341 T (Tag_ABI_optimization_goals
),
29342 T (Tag_ABI_FP_optimization_goals
),
29343 T (Tag_compatibility
),
29344 T (Tag_CPU_unaligned_access
),
29345 T (Tag_FP_HP_extension
),
29346 T (Tag_VFP_HP_extension
),
29347 T (Tag_ABI_FP_16bit_format
),
29348 T (Tag_MPextension_use
),
29350 T (Tag_nodefaults
),
29351 T (Tag_also_compatible_with
),
29352 T (Tag_conformance
),
29354 T (Tag_Virtualization_use
),
29355 T (Tag_DSP_extension
),
29357 /* We deliberately do not include Tag_MPextension_use_legacy. */
29365 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
29366 if (streq (name
, attribute_table
[i
].name
))
29367 return attribute_table
[i
].tag
;
29372 /* Apply sym value for relocations only in the case that they are for
29373 local symbols in the same segment as the fixup and you have the
29374 respective architectural feature for blx and simple switches. */
29377 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
29380 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
29381 /* PR 17444: If the local symbol is in a different section then a reloc
29382 will always be generated for it, so applying the symbol value now
29383 will result in a double offset being stored in the relocation. */
29384 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
29385 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
29387 switch (fixP
->fx_r_type
)
29389 case BFD_RELOC_ARM_PCREL_BLX
:
29390 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29391 if (ARM_IS_FUNC (fixP
->fx_addsy
))
29395 case BFD_RELOC_ARM_PCREL_CALL
:
29396 case BFD_RELOC_THUMB_PCREL_BLX
:
29397 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
29408 #endif /* OBJ_ELF */