1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control
* arm_ops_hsh
;
729 static struct hash_control
* arm_cond_hsh
;
730 static struct hash_control
* arm_shift_hsh
;
731 static struct hash_control
* arm_psr_hsh
;
732 static struct hash_control
* arm_v7m_psr_hsh
;
733 static struct hash_control
* arm_reg_hsh
;
734 static struct hash_control
* arm_reloc_hsh
;
735 static struct hash_control
* arm_barrier_opt_hsh
;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS
* last_label_seen
;
747 static int label_is_thumb_function_name
= FALSE
;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
756 unsigned int next_free_entry
;
761 struct literal_pool
* next
;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool
* list_of_pools
= NULL
;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it
;
774 now_it_compatible (int cond
)
776 return (cond
& ~1) == (now_it
.cc
& ~1);
780 conditional_insn (void)
782 return inst
.cond
!= COND_ALWAYS
;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars
[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars
[] = "#";
836 const char line_separator_chars
[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS
[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str
, char c
)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS
* sp
)
877 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
880 if (symbol_get_value_expression (sp
)->X_add_symbol
)
882 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
883 || (symbol_get_value_expression (sp
)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
890 static int in_my_get_expression
= 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
913 case GE_NO_PREFIX
: break;
915 if (!is_immediate_prefix (**str
))
917 inst
.error
= _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG
:
924 if (is_immediate_prefix (**str
))
930 memset (ep
, 0, sizeof (expressionS
));
932 save_in
= input_line_pointer
;
933 input_line_pointer
= *str
;
934 in_my_get_expression
= 1;
935 seg
= expression (ep
);
936 in_my_get_expression
= 0;
938 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
940 /* We found a bad or missing expression in md_operand(). */
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
943 if (inst
.error
== NULL
)
944 inst
.error
= (ep
->X_op
== O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg
!= absolute_section
951 && seg
!= text_section
952 && seg
!= data_section
953 && seg
!= bss_section
954 && seg
!= undefined_section
)
956 inst
.error
= _("bad segment");
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode
!= GE_OPT_PREFIX_BIG
969 && (ep
->X_op
== O_big
971 && (walk_no_bignums (ep
->X_add_symbol
)
973 && walk_no_bignums (ep
->X_op_symbol
))))))
975 inst
.error
= _("invalid constant");
976 *str
= input_line_pointer
;
977 input_line_pointer
= save_in
;
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type
, char * litP
, int * sizeP
)
1004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t
= atof_ieee (input_line_pointer
, type
, words
);
1041 input_line_pointer
= t
;
1042 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1044 if (target_big_endian
)
1046 for (i
= 0; i
< prec
; i
++)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1055 for (i
= prec
- 1; i
>= 0; i
--)
1057 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1058 litP
+= sizeof (LITTLENUM_TYPE
);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i
= 0; i
< prec
; i
+= 2)
1065 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1066 sizeof (LITTLENUM_TYPE
));
1067 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1068 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1069 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS
* exp
)
1081 if (in_my_get_expression
)
1082 exp
->X_op
= O_illegal
;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val
)
1095 exp
.X_op
= O_illegal
;
1097 if (is_immediate_prefix (*input_line_pointer
))
1099 input_line_pointer
++;
1103 if (exp
.X_op
!= O_constant
)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val
= exp
.X_add_number
;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry
*
1122 arm_reg_parse_multi (char **ccp
)
1126 struct reg_entry
*reg
;
1128 #ifdef REGISTER_PREFIX
1129 if (*start
!= REGISTER_PREFIX
)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1139 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1144 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1146 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1156 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1157 enum arm_reg_type type
)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg
&& reg
->type
== REG_TYPE_CN
)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor
= strtoul (start
, ccp
, 10);
1175 if (*ccp
!= start
&& processor
<= 15)
1179 case REG_TYPE_MMXWC
:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1200 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1207 if (reg
&& reg
->type
== type
)
1210 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type
*type
, char **str
)
1239 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1241 enum neon_el_type thistype
= NT_untyped
;
1242 unsigned thissize
= -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr
))
1255 case 'i': thistype
= NT_integer
; break;
1256 case 'f': thistype
= NT_float
; break;
1257 case 'p': thistype
= NT_poly
; break;
1258 case 's': thistype
= NT_signed
; break;
1259 case 'u': thistype
= NT_unsigned
; break;
1261 thistype
= NT_float
;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1278 thissize
= strtoul (ptr
, &ptr
, 10);
1280 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1283 as_bad (_("bad size %d in type specifier"), thissize
);
1291 type
->el
[type
->elems
].type
= thistype
;
1292 type
->el
[type
->elems
].size
= thissize
;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type
->elems
== 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err
)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1323 struct neon_type optype
;
1327 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1329 if (optype
.elems
== 1)
1330 *vectype
= optype
.el
[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
,
1365 struct neon_typed_alias
*typeinfo
)
1368 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1369 struct neon_typed_alias atype
;
1370 struct neon_type_el parsetype
;
1374 atype
.eltype
.type
= NT_invtype
;
1375 atype
.eltype
.size
= -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type
== REG_TYPE_NDQ
1391 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1392 || (type
== REG_TYPE_VFSD
1393 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1394 || (type
== REG_TYPE_NSDQ
1395 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1396 || reg
->type
== REG_TYPE_NQ
))
1397 || (type
== REG_TYPE_MMXWC
1398 && (reg
->type
== REG_TYPE_MMXWCG
)))
1399 type
= (enum arm_reg_type
) reg
->type
;
1401 if (type
!= reg
->type
)
1407 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1409 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype
.defined
|= NTA_HASTYPE
;
1415 atype
.eltype
= parsetype
;
1418 if (skip_past_char (&str
, '[') == SUCCESS
)
1420 if (type
!= REG_TYPE_VFD
)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype
.defined
|= NTA_HASINDEX
;
1434 if (skip_past_char (&str
, ']') == SUCCESS
)
1435 atype
.index
= NEON_ALL_LANES
;
1440 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1442 if (exp
.X_op
!= O_constant
)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str
, ']') == FAIL
)
1451 atype
.index
= exp
.X_add_number
;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1475 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1477 struct neon_typed_alias atype
;
1479 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype
= atype
.eltype
;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1515 struct neon_typed_alias atype
;
1517 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1519 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1522 if (atype
.index
== NEON_ALL_LANES
)
1524 first_error (_("scalar must have an index"));
1527 else if (atype
.index
>= 64 / elsize
)
1529 first_error (_("scalar index out of range"));
1534 *type
= atype
.eltype
;
1538 return reg
* 16 + atype
.index
;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp
)
1546 char * str
= * strp
;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1567 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1577 first_error (_("bad range in register list"));
1581 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1583 if (range
& (1 << i
))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range
& (1 << reg
))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg
<= cur_reg
)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str
) != FAIL
1603 || (in_range
= 1, *str
++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1619 if (exp
.X_op
== O_constant
)
1621 if (exp
.X_add_number
1622 != (exp
.X_add_number
& 0x0000ffff))
1624 inst
.error
= _("invalid register mask");
1628 if ((range
& exp
.X_add_number
) != 0)
1630 int regno
= range
& exp
.X_add_number
;
1633 regno
= (1 << regno
) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range
|= exp
.X_add_number
;
1643 if (inst
.reloc
.type
!= 0)
1645 inst
.error
= _("expression too complex");
1649 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1650 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1651 inst
.reloc
.pc_rel
= 0;
1655 if (*str
== '|' || *str
== '+')
1661 while (another_range
);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1697 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1701 unsigned long mask
= 0;
1706 inst
.error
= _("expecting {");
1715 regtype
= REG_TYPE_VFS
;
1720 regtype
= REG_TYPE_VFD
;
1723 case REGLIST_NEON_D
:
1724 regtype
= REG_TYPE_NDQ
;
1728 if (etype
!= REGLIST_VFP_S
)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1745 base_reg
= max_regs
;
1749 int setmask
= 1, addregs
= 1;
1751 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1753 if (new_base
== FAIL
)
1755 first_error (_(reg_expected_msgs
[regtype
]));
1759 if (new_base
>= max_regs
)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype
== REG_TYPE_NQ
)
1772 if (new_base
< base_reg
)
1773 base_reg
= new_base
;
1775 if (mask
& (setmask
<< new_base
))
1777 first_error (_("invalid register list"));
1781 if ((mask
>> new_base
) != 0 && ! warned
)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask
|= setmask
<< new_base
;
1790 if (*str
== '-') /* We have the start of a range expression */
1796 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1799 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1803 if (high_range
>= max_regs
)
1805 first_error (_("register out of range in list"));
1809 if (regtype
== REG_TYPE_NQ
)
1810 high_range
= high_range
+ 1;
1812 if (high_range
<= new_base
)
1814 inst
.error
= _("register range not in ascending order");
1818 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1820 if (mask
& (setmask
<< new_base
))
1822 inst
.error
= _("invalid register list");
1826 mask
|= setmask
<< new_base
;
1831 while (skip_past_comma (&str
) != FAIL
);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count
== 0 || count
> max_regs
)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i
= 0; i
< count
; i
++)
1845 if ((mask
& (1u << i
)) == 0)
1847 inst
.error
= _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1868 if (a
->defined
!= b
->defined
)
1871 if ((a
->defined
& NTA_HASTYPE
) != 0
1872 && (a
->eltype
.type
!= b
->eltype
.type
1873 || a
->eltype
.size
!= b
->eltype
.size
))
1876 if ((a
->defined
& NTA_HASINDEX
) != 0
1877 && (a
->index
!= b
->index
))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1897 struct neon_type_el
*eltype
)
1904 int leading_brace
= 0;
1905 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1906 const char *const incr_error
= _("register stride must be 1 or 2");
1907 const char *const type_error
= _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype
;
1910 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1915 struct neon_typed_alias atype
;
1916 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1920 first_error (_(reg_expected_msgs
[rtype
]));
1927 if (rtype
== REG_TYPE_NQ
)
1933 else if (reg_incr
== -1)
1935 reg_incr
= getreg
- base_reg
;
1936 if (reg_incr
< 1 || reg_incr
> 2)
1938 first_error (_(incr_error
));
1942 else if (getreg
!= base_reg
+ reg_incr
* count
)
1944 first_error (_(incr_error
));
1948 if (! neon_alias_types_same (&atype
, &firsttype
))
1950 first_error (_(type_error
));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype
;
1959 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1961 lane
= NEON_INTERLEAVE_LANES
;
1962 else if (lane
!= NEON_INTERLEAVE_LANES
)
1964 first_error (_(type_error
));
1969 else if (reg_incr
!= 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1978 first_error (_(reg_expected_msgs
[rtype
]));
1981 if (! neon_alias_types_same (&htype
, &firsttype
))
1983 first_error (_(type_error
));
1986 count
+= hireg
+ dregs
- getreg
;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype
== REG_TYPE_NQ
)
1997 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2001 else if (lane
!= atype
.index
)
2003 first_error (_(type_error
));
2007 else if (lane
== -1)
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane
= NEON_INTERLEAVE_LANES
;
2023 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2024 || (count
> 1 && reg_incr
== -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2032 first_error (_("expected }"));
2040 *eltype
= firsttype
.eltype
;
2045 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str
)
2056 struct reloc_entry
*r
;
2060 return BFD_RELOC_UNUSED
;
2065 while (*q
&& *q
!= ')' && *q
!= ',')
2070 if ((r
= (struct reloc_entry
*)
2071 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2078 /* Directives: register aliases. */
2080 static struct reg_entry
*
2081 insert_reg_alias (char *str
, unsigned number
, int type
)
2083 struct reg_entry
*new_reg
;
2086 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2088 if (new_reg
->builtin
)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2099 name
= xstrdup (str
);
2100 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2102 new_reg
->name
= name
;
2103 new_reg
->number
= number
;
2104 new_reg
->type
= type
;
2105 new_reg
->builtin
= FALSE
;
2106 new_reg
->neon
= NULL
;
2108 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2115 insert_neon_reg_alias (char *str
, int number
, int type
,
2116 struct neon_typed_alias
*atype
)
2118 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg
->neon
= (struct neon_typed_alias
*)
2129 xmalloc (sizeof (struct neon_typed_alias
));
2130 *reg
->neon
= *atype
;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname
, char *p
)
2144 struct reg_entry
*old
;
2145 char *oldname
, *nbuf
;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname
, " .req ", 6) != 0)
2155 if (*oldname
== '\0')
2158 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname
= original_case_string
;
2172 nlen
= strlen (newname
);
2175 nbuf
= (char *) alloca (nlen
+ 1);
2176 memcpy (nbuf
, newname
, nlen
);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2184 for (p
= nbuf
; *p
; p
++)
2187 if (strncmp (nbuf
, newname
, nlen
))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2202 for (p
= nbuf
; *p
; p
++)
2205 if (strncmp (nbuf
, newname
, nlen
))
2206 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname
, char *p
)
2225 enum arm_reg_type basetype
;
2226 struct reg_entry
*basereg
;
2227 struct reg_entry mybasereg
;
2228 struct neon_type ntype
;
2229 struct neon_typed_alias typeinfo
;
2230 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2233 typeinfo
.defined
= 0;
2234 typeinfo
.eltype
.type
= NT_invtype
;
2235 typeinfo
.eltype
.size
= -1;
2236 typeinfo
.index
= -1;
2240 if (strncmp (p
, " .dn ", 5) == 0)
2241 basetype
= REG_TYPE_VFD
;
2242 else if (strncmp (p
, " .qn ", 5) == 0)
2243 basetype
= REG_TYPE_NQ
;
2252 basereg
= arm_reg_parse_multi (&p
);
2254 if (basereg
&& basereg
->type
!= basetype
)
2256 as_bad (_("bad type for register"));
2260 if (basereg
== NULL
)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2265 if (exp
.X_op
!= O_constant
)
2267 as_bad (_("expression must be constant"));
2270 basereg
= &mybasereg
;
2271 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2277 typeinfo
= *basereg
->neon
;
2279 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2281 /* We got a type. */
2282 if (typeinfo
.defined
& NTA_HASTYPE
)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo
.defined
|= NTA_HASTYPE
;
2289 if (ntype
.elems
!= 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo
.eltype
= ntype
.el
[0];
2297 if (skip_past_char (&p
, '[') == SUCCESS
)
2300 /* We got a scalar index. */
2302 if (typeinfo
.defined
& NTA_HASINDEX
)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2310 if (exp
.X_op
!= O_constant
)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo
.defined
|= NTA_HASINDEX
;
2317 typeinfo
.index
= exp
.X_add_number
;
2319 if (skip_past_char (&p
, ']') == FAIL
)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen
= nameend
- newname
;
2332 newname
= original_case_string
;
2333 namelen
= strlen (newname
);
2336 namebuf
= (char *) alloca (namelen
+ 1);
2337 strncpy (namebuf
, newname
, namelen
);
2338 namebuf
[namelen
] = '\0';
2340 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2341 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Insert name in all uppercase. */
2344 for (p
= namebuf
; *p
; p
++)
2347 if (strncmp (namebuf
, newname
, namelen
))
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all lowercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED
)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED
)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED
)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED
)
2395 name
= input_line_pointer
;
2397 while (*input_line_pointer
!= 0
2398 && *input_line_pointer
!= ' '
2399 && *input_line_pointer
!= '\n')
2400 ++input_line_pointer
;
2402 saved_char
= *input_line_pointer
;
2403 *input_line_pointer
= 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2413 as_bad (_("unknown register alias '%s'"), name
);
2414 else if (reg
->builtin
)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh
, name
, FALSE
);
2423 free ((char *) reg
->name
);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf
= strdup (name
);
2433 for (p
= nbuf
; *p
; p
++)
2435 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2438 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2439 free ((char *) reg
->name
);
2445 for (p
= nbuf
; *p
; p
++)
2447 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2450 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2451 free ((char *) reg
->name
);
2461 *input_line_pointer
= saved_char
;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2479 const char * symname
;
2486 type
= BSF_NO_FLAGS
;
2490 type
= BSF_NO_FLAGS
;
2494 type
= BSF_NO_FLAGS
;
2500 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2506 THUMB_SET_FUNC (symbolP
, 0);
2507 ARM_SET_THUMB (symbolP
, 0);
2508 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2512 THUMB_SET_FUNC (symbolP
, 1);
2513 ARM_SET_THUMB (symbolP
, 1);
2514 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag
->tc_frag_data
.first_map
!= NULL
)
2535 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2536 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2538 frag
->tc_frag_data
.first_map
= symbolP
;
2540 if (frag
->tc_frag_data
.last_map
!= NULL
)
2542 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2543 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2544 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.last_map
= symbolP
;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state
,
2555 valueT value
, fragS
*frag
, offsetT bytes
)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag
->tc_frag_data
.last_map
!= NULL
2559 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2561 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2565 know (frag
->tc_frag_data
.first_map
== symp
);
2566 frag
->tc_frag_data
.first_map
= NULL
;
2568 frag
->tc_frag_data
.last_map
= NULL
;
2569 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2572 make_mapping_symbol (MAP_DATA
, value
, frag
);
2573 make_mapping_symbol (state
, value
+ bytes
, frag
);
2576 static void mapping_state_2 (enum mstate state
, int max_chars
);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state
)
2584 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate
== state
)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2596 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2603 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2609 mapping_state_2 (state
, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state
, int max_chars
)
2619 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2621 if (!SEG_NORMAL (now_seg
))
2624 if (mapstate
== state
)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2630 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS
* symbolP
)
2644 const char * name
= S_GET_NAME (symbolP
);
2645 symbolS
* new_target
;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2661 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2662 new_target
= symbol_find (real_start
);
2664 if (new_target
== NULL
)
2666 as_warn (_("Failed to find real start of function: %s\n"), name
);
2667 new_target
= symbolP
;
2675 opcode_select (int width
)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg
, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg
, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width
);
2713 s_arm (int ignore ATTRIBUTE_UNUSED
)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED
)
2731 temp
= get_absolute_expression ();
2736 opcode_select (temp
);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg
, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name
= TRUE
;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv
)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name
= input_line_pointer
;
2789 delim
= get_symbol_end ();
2790 end_name
= input_line_pointer
;
2793 if (*input_line_pointer
!= ',')
2796 as_bad (_("expected comma after name \"%s\""), name
);
2798 ignore_rest_of_line ();
2802 input_line_pointer
++;
2805 if (name
[0] == '.' && name
[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP
= symbol_find (name
)) == NULL
2812 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing
& LISTING_SYMBOLS
)
2820 extern struct list_info_struct
* listing_tail
;
2821 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2823 memset (dummy_frag
, 0, sizeof (fragS
));
2824 dummy_frag
->fr_type
= rs_fill
;
2825 dummy_frag
->line
= listing_tail
;
2826 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2827 dummy_frag
->fr_symbol
= symbolP
;
2831 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP
);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP
);
2844 && S_IS_DEFINED (symbolP
)
2845 && S_GET_SEGMENT (symbolP
) != reg_section
)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2848 pseudo_set (symbolP
);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP
, 1);
2855 ARM_SET_THUMB (symbolP
, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED
)
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2874 if (!strcasecmp (name
, "unified"))
2875 unified_syntax
= TRUE
;
2876 else if (!strcasecmp (name
, "divided"))
2877 unified_syntax
= FALSE
;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2883 *input_line_pointer
= delim
;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED
)
2897 long max_alignment
= 15;
2899 temp
= get_absolute_expression ();
2900 if (temp
> max_alignment
)
2901 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer
== ',')
2910 input_line_pointer
++;
2911 temp_fill
= get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp
&& !need_pass_2
)
2926 if (!fill_p
&& subseg_text_p (now_seg
))
2927 frag_align_code (temp
, 0);
2929 frag_align (temp
, (int) temp_fill
, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg
, temp
);
2937 s_bss (int ignore ATTRIBUTE_UNUSED
)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section
, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED
)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg
, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool
*
2964 find_literal_pool (void)
2966 literal_pool
* pool
;
2968 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2970 if (pool
->section
== now_seg
2971 && pool
->sub_section
== now_subseg
)
2978 static literal_pool
*
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num
= 1;
2983 literal_pool
* pool
;
2985 pool
= find_literal_pool ();
2989 /* Create a new pool. */
2990 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2994 pool
->next_free_entry
= 0;
2995 pool
->section
= now_seg
;
2996 pool
->sub_section
= now_subseg
;
2997 pool
->next
= list_of_pools
;
2998 pool
->symbol
= NULL
;
3000 /* Add it to the list. */
3001 list_of_pools
= pool
;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool
->symbol
== NULL
)
3007 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3008 (valueT
) 0, &zero_address_frag
);
3009 pool
->id
= latest_pool_num
++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool
* pool
;
3025 pool
= find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3030 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3031 && (inst
.reloc
.exp
.X_op
== O_constant
)
3032 && (pool
->literals
[entry
].X_add_number
3033 == inst
.reloc
.exp
.X_add_number
)
3034 && (pool
->literals
[entry
].X_unsigned
3035 == inst
.reloc
.exp
.X_unsigned
))
3038 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3039 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3040 && (pool
->literals
[entry
].X_add_number
3041 == inst
.reloc
.exp
.X_add_number
)
3042 && (pool
->literals
[entry
].X_add_symbol
3043 == inst
.reloc
.exp
.X_add_symbol
)
3044 && (pool
->literals
[entry
].X_op_symbol
3045 == inst
.reloc
.exp
.X_op_symbol
))
3049 /* Do we need to create a new entry? */
3050 if (entry
== pool
->next_free_entry
)
3052 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3054 inst
.error
= _("literal pool overflow");
3058 pool
->literals
[entry
] = inst
.reloc
.exp
;
3059 pool
->next_free_entry
+= 1;
3062 inst
.reloc
.exp
.X_op
= O_symbol
;
3063 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3064 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS
* symbolP
,
3074 const char * name
, /* It is copied, the caller can modify. */
3075 segT segment
, /* Segment identifier (SEG_<something>). */
3076 valueT valu
, /* Symbol value. */
3077 fragS
* frag
) /* Associated fragment. */
3079 unsigned int name_length
;
3080 char * preserved_copy_of_name
;
3082 name_length
= strlen (name
) + 1; /* +1 for \0. */
3083 obstack_grow (¬es
, name
, name_length
);
3084 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name
=
3088 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3091 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3093 S_SET_SEGMENT (symbolP
, segment
);
3094 S_SET_VALUE (symbolP
, valu
);
3095 symbol_clear_list_pointers (symbolP
);
3097 symbol_set_frag (symbolP
, frag
);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen
;
3103 if (symbol_table_frozen
)
3107 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3109 obj_symbol_new_hook (symbolP
);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP
);
3116 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3125 literal_pool
* pool
;
3128 pool
= find_literal_pool ();
3130 || pool
->symbol
== NULL
3131 || pool
->next_free_entry
== 0)
3134 mapping_state (MAP_DATA
);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3145 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3146 (valueT
) frag_now_fix (), frag_now
);
3147 symbol_table_insert (pool
->symbol
);
3149 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3155 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool
->next_free_entry
= 0;
3161 pool
->symbol
= NULL
;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3168 static valueT
create_unwind_entry (int);
3169 static void start_unwind_section (const segT
, int);
3170 static void add_unwind_opcode (valueT
, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes
)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes
);
3194 mapping_state (MAP_DATA
);
3198 char *base
= input_line_pointer
;
3202 if (exp
.X_op
!= O_symbol
)
3203 emit_expr (&exp
, (unsigned int) nbytes
);
3206 char *before_reloc
= input_line_pointer
;
3207 reloc
= parse_reloc (&input_line_pointer
);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc
== BFD_RELOC_UNUSED
)
3215 emit_expr (&exp
, (unsigned int) nbytes
);
3218 reloc_howto_type
*howto
= (reloc_howto_type
*)
3219 bfd_reloc_type_lookup (stdoutput
,
3220 (bfd_reloc_code_real_type
) reloc
);
3221 int size
= bfd_get_reloc_size (howto
);
3223 if (reloc
== BFD_RELOC_ARM_PLT32
)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc
= BFD_RELOC_UNUSED
;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto
->name
, nbytes
);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p
= input_line_pointer
;
3241 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3242 memcpy (save_buf
, base
, input_line_pointer
- base
);
3243 memmove (base
+ (input_line_pointer
- before_reloc
),
3244 base
, before_reloc
- base
);
3246 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3248 memcpy (base
, save_buf
, p
- base
);
3250 offset
= nbytes
- size
;
3251 p
= frag_more ((int) nbytes
);
3252 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3253 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3258 while (*input_line_pointer
++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer
--;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS
* exp
)
3271 expressionS exp_high
= *exp
;
3273 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3274 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3275 exp
->X_add_number
&= 0xffff;
3276 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode
)
3284 if ((unsigned int) opcode
< 0xe800u
)
3286 else if ((unsigned int) opcode
>= 0xe8000000u
)
3293 emit_insn (expressionS
*exp
, int nbytes
)
3297 if (exp
->X_op
== O_constant
)
3302 size
= thumb_insn_size (exp
->X_add_number
);
3306 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3319 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3320 emit_thumb32_expr (exp
);
3322 emit_expr (exp
, (unsigned int) size
);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes
)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB
);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM
);
3374 if (! emit_insn (& exp
, nbytes
))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer
++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer
--;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3397 if (*input_line_pointer
== '1')
3398 highbit
= 0x80000000;
3399 else if (*input_line_pointer
!= '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer
++;
3403 if (*input_line_pointer
!= ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer
++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA
);
3420 md_number_to_chars (p
, highbit
, 4);
3421 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3422 BFD_RELOC_ARM_PREL31
);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (unwind
.proc_start
)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind
.proc_start
= expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind
.opcode_count
= 0;
3446 unwind
.table_entry
= NULL
;
3447 unwind
.personality_routine
= NULL
;
3448 unwind
.personality_index
= -1;
3449 unwind
.frame_size
= 0;
3450 unwind
.fp_offset
= 0;
3451 unwind
.fp_reg
= REG_SP
;
3453 unwind
.sp_restored
= 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3463 demand_empty_rest_of_line ();
3464 if (!unwind
.proc_start
)
3465 as_bad (MISSING_FNSTART
);
3467 if (unwind
.table_entry
)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3481 unsigned int marked_pr_dependency
;
3483 demand_empty_rest_of_line ();
3485 if (!unwind
.proc_start
)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind
.table_entry
== NULL
)
3493 val
= create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind
.saved_seg
, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg
, 2);
3502 ptr
= frag_more (8);
3503 where
= frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3507 BFD_RELOC_ARM_PREL31
);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3513 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3514 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3516 static const char *const name
[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3523 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3524 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3525 |= 1 << unwind
.personality_index
;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr
+ 4, val
, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3534 BFD_RELOC_ARM_PREL31
);
3536 /* Restore the original section. */
3537 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3539 unwind
.proc_start
= NULL
;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3548 demand_empty_rest_of_line ();
3549 if (!unwind
.proc_start
)
3550 as_bad (MISSING_FNSTART
);
3552 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind
.personality_index
= -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp
.X_op
!= O_constant
3575 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind
.personality_index
= exp
.X_add_number
;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3595 if (!unwind
.proc_start
)
3596 as_bad (MISSING_FNSTART
);
3598 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name
= input_line_pointer
;
3602 c
= get_symbol_end ();
3603 p
= input_line_pointer
;
3604 unwind
.personality_routine
= symbol_find_or_make (name
);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range
= parse_reg_list (&input_line_pointer
);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3633 && (range
& 0x3000) == 0x1000)
3635 unwind
.opcode_count
--;
3636 unwind
.sp_restored
= 0;
3637 range
= (range
| 0x2000) & ~0x1000;
3638 unwind
.pending_offset
= 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n
= 0; n
< 8; n
++)
3648 /* Break at the first non-saved register. */
3649 if ((range
& (1 << (n
+ 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op
= 0x8000 | ((range
>> 4) & 0xfff);
3657 add_unwind_opcode (op
, 2);
3661 /* Use the short form. */
3663 op
= 0xa8; /* Pop r14. */
3665 op
= 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op
, 1);
3674 op
= 0xb100 | (range
& 0xf);
3675 add_unwind_opcode (op
, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n
= 0; n
< 16; n
++)
3681 if (range
& (1 << n
))
3682 unwind
.frame_size
+= 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg
)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3700 exp
.X_op
= O_illegal
;
3702 if (exp
.X_op
!= O_constant
)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs
= exp
.X_add_number
;
3711 if (num_regs
< 1 || num_regs
> 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op
= 0xb4 | (num_regs
- 1);
3724 add_unwind_opcode (op
, 1);
3729 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3730 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= num_regs
* 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs
= 0;
3745 int num_regs_below_16
;
3747 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs
= count
;
3763 else if (start
+ count
> 16)
3764 num_vfpv3_regs
= start
+ count
- 16;
3766 if (num_vfpv3_regs
> 0)
3768 int start_offset
= start
> 16 ? start
- 16 : 0;
3769 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3770 add_unwind_opcode (op
, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3775 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3776 if (num_regs_below_16
> 0)
3778 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3779 add_unwind_opcode (op
, 2);
3782 unwind
.frame_size
+= count
* 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op
= 0xb8 | (count
- 1);
3809 add_unwind_opcode (op
, 1);
3814 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3815 add_unwind_opcode (op
, 2);
3817 unwind
.frame_size
+= count
* 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer
== '{')
3833 input_line_pointer
++;
3837 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3841 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer
== '-')
3851 input_line_pointer
++;
3852 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3855 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3858 else if (reg
>= hi_reg
)
3860 as_bad (_("bad register range"));
3863 for (; reg
< hi_reg
; reg
++)
3867 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3869 if (*input_line_pointer
== '}')
3870 input_line_pointer
++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i
= 0; i
< 16; i
++)
3880 if (mask
& (1 << i
))
3881 unwind
.frame_size
+= 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind
.opcode_count
> 0)
3889 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3890 if ((i
& 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask
& 0xfe00) == (1 << 9))
3898 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3899 unwind
.opcode_count
--;
3902 else if (i
== 6 && unwind
.opcode_count
>= 2)
3904 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3908 op
= 0xffff << (reg
- 1);
3910 && ((mask
& op
) == (1u << (reg
- 1))))
3912 op
= (1 << (reg
+ i
+ 1)) - 1;
3913 op
&= ~((1 << reg
) - 1);
3915 unwind
.opcode_count
-= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg
= 15; reg
>= -1; reg
--)
3926 /* Save registers in blocks. */
3928 || !(mask
& (1 << reg
)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op
= 0xc0 | (hi_reg
- 10);
3938 add_unwind_opcode (op
, 1);
3943 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3944 add_unwind_opcode (op
, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer
== '{')
3965 input_line_pointer
++;
3969 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3973 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer
== '-')
3984 input_line_pointer
++;
3985 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3988 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3991 else if (reg
>= hi_reg
)
3993 as_bad (_("bad register range"));
3996 for (; reg
< hi_reg
; reg
++)
4000 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4002 if (*input_line_pointer
== '}')
4003 input_line_pointer
++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg
= 0; reg
< 16; reg
++)
4013 if (mask
& (1 << reg
))
4014 unwind
.frame_size
+= 4;
4017 add_unwind_opcode (op
, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6
)
4031 struct reg_entry
*reg
;
4032 bfd_boolean had_brace
= FALSE
;
4034 if (!unwind
.proc_start
)
4035 as_bad (MISSING_FNSTART
);
4037 /* Figure out what sort of save we have. */
4038 peek
= input_line_pointer
;
4046 reg
= arm_reg_parse_multi (&peek
);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer
= peek
;
4065 s_arm_unwind_save_fpa (reg
->number
);
4068 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4100 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4108 if (immediate_for_directive (&offset
) == FAIL
)
4114 demand_empty_rest_of_line ();
4116 if (reg
== REG_SP
|| reg
== REG_PC
)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind
.fp_reg
!= REG_SP
)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op
, 1);
4129 /* Record the information for later. */
4130 unwind
.fp_reg
= reg
;
4131 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4132 unwind
.sp_restored
= 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 if (immediate_for_directive (&offset
) == FAIL
)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind
.frame_size
+= offset
;
4157 unwind
.pending_offset
+= offset
;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4171 if (!unwind
.proc_start
)
4172 as_bad (MISSING_FNSTART
);
4174 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4175 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4178 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4180 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4190 if (immediate_for_directive (&offset
) == FAIL
)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind
.fp_reg
= fp_reg
;
4208 if (sp_reg
== REG_SP
)
4209 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4211 unwind
.fp_offset
-= offset
;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4220 /* This is an arbitrary limit. */
4221 unsigned char op
[16];
4224 if (!unwind
.proc_start
)
4225 as_bad (MISSING_FNSTART
);
4228 if (exp
.X_op
== O_constant
4229 && skip_past_comma (&input_line_pointer
) != FAIL
)
4231 unwind
.frame_size
+= exp
.X_add_number
;
4235 exp
.X_op
= O_illegal
;
4237 if (exp
.X_op
!= O_constant
)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op
[count
++] = exp
.X_add_number
;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op
[count
], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4282 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4284 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4285 attributes_set_explicitly
[tag
] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4307 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4308 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4329 if (exp
.X_op
== O_symbol
)
4330 exp
.X_op
= O_secrel
;
4332 emit_expr (&exp
, 4);
4334 while (*input_line_pointer
++ == ',');
4336 input_line_pointer
--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table
[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req
, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq
, 0 },
4355 { "bss", s_bss
, 0 },
4356 { "align", s_align
, 0 },
4357 { "arm", s_arm
, 0 },
4358 { "thumb", s_thumb
, 0 },
4359 { "code", s_code
, 0 },
4360 { "force_thumb", s_force_thumb
, 0 },
4361 { "thumb_func", s_thumb_func
, 0 },
4362 { "thumb_set", s_thumb_set
, 0 },
4363 { "even", s_even
, 0 },
4364 { "ltorg", s_ltorg
, 0 },
4365 { "pool", s_ltorg
, 0 },
4366 { "syntax", s_syntax
, 0 },
4367 { "cpu", s_arm_cpu
, 0 },
4368 { "arch", s_arm_arch
, 0 },
4369 { "object_arch", s_arm_object_arch
, 0 },
4370 { "fpu", s_arm_fpu
, 0 },
4371 { "arch_extension", s_arm_arch_extension
, 0 },
4373 { "word", s_arm_elf_cons
, 4 },
4374 { "long", s_arm_elf_cons
, 4 },
4375 { "inst.n", s_arm_elf_inst
, 2 },
4376 { "inst.w", s_arm_elf_inst
, 4 },
4377 { "inst", s_arm_elf_inst
, 0 },
4378 { "rel31", s_arm_rel31
, 0 },
4379 { "fnstart", s_arm_unwind_fnstart
, 0 },
4380 { "fnend", s_arm_unwind_fnend
, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4382 { "personality", s_arm_unwind_personality
, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4385 { "save", s_arm_unwind_save
, 0 },
4386 { "vsave", s_arm_unwind_save
, 1 },
4387 { "movsp", s_arm_unwind_movsp
, 0 },
4388 { "pad", s_arm_unwind_pad
, 0 },
4389 { "setfp", s_arm_unwind_setfp
, 0 },
4390 { "unwind_raw", s_arm_unwind_raw
, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4402 { "loc", dwarf2_directive_loc
, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4405 { "extend", float_cons
, 'x' },
4406 { "ldouble", float_cons
, 'x' },
4407 { "packed", float_cons
, 'p' },
4409 {"secrel32", pe_directive_secrel
, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str
, int *val
, int min
, int max
,
4424 bfd_boolean prefix_opt
)
4427 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4428 if (exp
.X_op
!= O_constant
)
4430 inst
.error
= _("constant expression required");
4434 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4436 inst
.error
= _("immediate value out of range");
4440 *val
= exp
.X_add_number
;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str
, int i
)
4454 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4456 if (exp
.X_op
== O_constant
)
4458 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4466 inst
.operands
[i
].regisimm
= 1;
4469 else if (exp
.X_op
== O_big
4470 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4472 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts
!= 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4485 LITTLENUM_TYPE m
= -1;
4487 if (generic_bignum
[parts
* 2] != 0
4488 && generic_bignum
[parts
* 2] != m
)
4491 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4492 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4496 inst
.operands
[i
].imm
= 0;
4497 for (j
= 0; j
< parts
; j
++, idx
++)
4498 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4499 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4500 inst
.operands
[i
].reg
= 0;
4501 for (j
= 0; j
< parts
; j
++, idx
++)
4502 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4503 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4504 inst
.operands
[i
].regisimm
= 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str
)
4520 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i
= 0; fp_const
[i
]; i
++)
4531 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4535 *str
+= strlen (fp_const
[i
]);
4536 if (is_end_of_line
[(unsigned char) **str
])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4549 /* Look for a raw floating point number. */
4550 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4551 && is_end_of_line
[(unsigned char) *save_in
])
4553 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4555 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4557 if (words
[j
] != fp_values
[i
][j
])
4561 if (j
== MAX_LITTLENUMS
)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in
= input_line_pointer
;
4572 input_line_pointer
= *str
;
4573 if (expression (&exp
) == absolute_section
4574 && exp
.X_op
== O_big
4575 && exp
.X_add_number
< 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words
, 5, (long) 15) == 0)
4581 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4583 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4585 if (words
[j
] != fp_values
[i
][j
])
4589 if (j
== MAX_LITTLENUMS
)
4591 *str
= input_line_pointer
;
4592 input_line_pointer
= save_in
;
4599 *str
= input_line_pointer
;
4600 input_line_pointer
= save_in
;
4601 inst
.error
= _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm
)
4611 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp
, int *immed
)
4626 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4627 int found_fpchar
= 0;
4629 skip_past_char (&str
, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum
);
4639 if (strncmp (fpnum
, "0x", 2) == 0)
4643 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4644 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4654 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4656 unsigned fpword
= 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4662 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4666 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind
;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4714 const struct asm_shift_name
*shift_name
;
4715 enum shift_kind shift
;
4720 for (p
= *str
; ISALPHA (*p
); p
++)
4725 inst
.error
= _("shift expression expected");
4729 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4732 if (shift_name
== NULL
)
4734 inst
.error
= _("shift expression expected");
4738 shift
= shift_name
->kind
;
4742 case NO_SHIFT_RESTRICT
:
4743 case SHIFT_IMMEDIATE
: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4746 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4748 inst
.error
= _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE
:
4754 if (shift
!= SHIFT_LSL
)
4756 inst
.error
= _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE
:
4762 if (shift
!= SHIFT_ASR
)
4764 inst
.error
= _("'ASR' required");
4772 if (shift
!= SHIFT_RRX
)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p
);
4777 if (mode
== NO_SHIFT_RESTRICT
4778 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4780 inst
.operands
[i
].imm
= reg
;
4781 inst
.operands
[i
].immisreg
= 1;
4783 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4786 inst
.operands
[i
].shift_kind
= shift
;
4787 inst
.operands
[i
].shifted
= 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str
, int i
)
4809 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4811 inst
.operands
[i
].reg
= value
;
4812 inst
.operands
[i
].isreg
= 1;
4814 /* parse_shift will override this if appropriate */
4815 inst
.reloc
.exp
.X_op
= O_constant
;
4816 inst
.reloc
.exp
.X_add_number
= 0;
4818 if (skip_past_comma (str
) == FAIL
)
4821 /* Shift operation on register. */
4822 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4825 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4828 if (skip_past_comma (str
) == SUCCESS
)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4834 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4836 inst
.error
= _("constant expression expected");
4840 value
= exp
.X_add_number
;
4841 if (value
< 0 || value
> 30 || value
% 2 != 0)
4843 inst
.error
= _("invalid rotation");
4846 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4848 inst
.error
= _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst
.reloc
.exp
.X_add_number
4854 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4855 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4858 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4859 inst
.reloc
.pc_rel
= 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table
[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4953 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4955 int length
= strlen (group_reloc_table
[i
].name
);
4957 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4958 && (*str
)[length
] == ':')
4960 *out
= &group_reloc_table
[i
];
4961 *str
+= (length
+ 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str
, int i
)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4991 || (*str
)[0] == ':')
4993 struct group_reloc_table_entry
*entry
;
4995 if ((*str
)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5003 inst
.error
= _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5014 gas_assert (inst
.reloc
.type
!= 0);
5016 return PARSE_OPERAND_SUCCESS
;
5019 return parse_shifter_operand (str
, i
) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str
, int i
)
5035 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5037 if (exp
.X_op
!= O_constant
)
5039 inst
.error
= _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL
;
5043 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5044 inst
.operands
[i
].immisalign
= 1;
5045 /* Alignments are not pre-indexes. */
5046 inst
.operands
[i
].preind
= 0;
5049 return PARSE_OPERAND_SUCCESS
;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str
, int i
, int group_relocations
,
5086 group_reloc_type group_type
)
5091 if (skip_past_char (&p
, '[') == FAIL
)
5093 if (skip_past_char (&p
, '=') == FAIL
)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst
.reloc
.pc_rel
= 1;
5097 inst
.operands
[i
].reg
= REG_PC
;
5098 inst
.operands
[i
].isreg
= 1;
5099 inst
.operands
[i
].preind
= 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5104 return PARSE_OPERAND_FAIL
;
5107 return PARSE_OPERAND_SUCCESS
;
5110 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5112 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5113 return PARSE_OPERAND_FAIL
;
5115 inst
.operands
[i
].reg
= reg
;
5116 inst
.operands
[i
].isreg
= 1;
5118 if (skip_past_comma (&p
) == SUCCESS
)
5120 inst
.operands
[i
].preind
= 1;
5123 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5127 inst
.operands
[i
].imm
= reg
;
5128 inst
.operands
[i
].immisreg
= 1;
5130 if (skip_past_comma (&p
) == SUCCESS
)
5131 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5132 return PARSE_OPERAND_FAIL
;
5134 else if (skip_past_char (&p
, ':') == SUCCESS
)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5141 if (result
!= PARSE_OPERAND_SUCCESS
)
5146 if (inst
.operands
[i
].negative
)
5148 inst
.operands
[i
].negative
= 0;
5152 if (group_relocations
5153 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5155 struct group_reloc_table_entry
*entry
;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5167 inst
.error
= _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5177 /* Record the relocation type. */
5181 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5185 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5189 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5196 if (inst
.reloc
.type
== 0)
5198 inst
.error
= _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5203 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5204 return PARSE_OPERAND_FAIL
;
5207 else if (skip_past_char (&p
, ':') == SUCCESS
)
5209 /* FIXME: '@' should be used here, but it's filtered out by generic code
5210 before we get to see it here. This may be subject to change. */
5211 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5213 if (result
!= PARSE_OPERAND_SUCCESS
)
5217 if (skip_past_char (&p
, ']') == FAIL
)
5219 inst
.error
= _("']' expected");
5220 return PARSE_OPERAND_FAIL
;
5223 if (skip_past_char (&p
, '!') == SUCCESS
)
5224 inst
.operands
[i
].writeback
= 1;
5226 else if (skip_past_comma (&p
) == SUCCESS
)
5228 if (skip_past_char (&p
, '{') == SUCCESS
)
5230 /* [Rn], {expr} - unindexed, with option */
5231 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5232 0, 255, TRUE
) == FAIL
)
5233 return PARSE_OPERAND_FAIL
;
5235 if (skip_past_char (&p
, '}') == FAIL
)
5237 inst
.error
= _("'}' expected at end of 'option' field");
5238 return PARSE_OPERAND_FAIL
;
5240 if (inst
.operands
[i
].preind
)
5242 inst
.error
= _("cannot combine index with option");
5243 return PARSE_OPERAND_FAIL
;
5246 return PARSE_OPERAND_SUCCESS
;
5250 inst
.operands
[i
].postind
= 1;
5251 inst
.operands
[i
].writeback
= 1;
5253 if (inst
.operands
[i
].preind
)
5255 inst
.error
= _("cannot combine pre- and post-indexing");
5256 return PARSE_OPERAND_FAIL
;
5260 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5262 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5264 /* We might be using the immediate for alignment already. If we
5265 are, OR the register number into the low-order bits. */
5266 if (inst
.operands
[i
].immisalign
)
5267 inst
.operands
[i
].imm
|= reg
;
5269 inst
.operands
[i
].imm
= reg
;
5270 inst
.operands
[i
].immisreg
= 1;
5272 if (skip_past_comma (&p
) == SUCCESS
)
5273 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5274 return PARSE_OPERAND_FAIL
;
5278 if (inst
.operands
[i
].negative
)
5280 inst
.operands
[i
].negative
= 0;
5283 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5284 return PARSE_OPERAND_FAIL
;
5289 /* If at this point neither .preind nor .postind is set, we have a
5290 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5291 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5293 inst
.operands
[i
].preind
= 1;
5294 inst
.reloc
.exp
.X_op
= O_constant
;
5295 inst
.reloc
.exp
.X_add_number
= 0;
5298 return PARSE_OPERAND_SUCCESS
;
5302 parse_address (char **str
, int i
)
5304 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5308 static parse_operand_result
5309 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5311 return parse_address_main (str
, i
, 1, type
);
5314 /* Parse an operand for a MOVW or MOVT instruction. */
5316 parse_half (char **str
)
5321 skip_past_char (&p
, '#');
5322 if (strncasecmp (p
, ":lower16:", 9) == 0)
5323 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5324 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5325 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5327 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5330 skip_whitespace (p
);
5333 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5336 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5338 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5340 inst
.error
= _("constant expression expected");
5343 if (inst
.reloc
.exp
.X_add_number
< 0
5344 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5346 inst
.error
= _("immediate value out of range");
5354 /* Miscellaneous. */
5356 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5357 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5359 parse_psr (char **str
, bfd_boolean lhs
)
5362 unsigned long psr_field
;
5363 const struct asm_psr
*psr
;
5365 bfd_boolean is_apsr
= FALSE
;
5366 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5368 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5369 feature for ease of use and backwards compatibility. */
5371 if (strncasecmp (p
, "SPSR", 4) == 0)
5374 goto unsupported_psr
;
5376 psr_field
= SPSR_BIT
;
5378 else if (strncasecmp (p
, "CPSR", 4) == 0)
5381 goto unsupported_psr
;
5385 else if (strncasecmp (p
, "APSR", 4) == 0)
5387 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5388 and ARMv7-R architecture CPUs. */
5397 while (ISALNUM (*p
) || *p
== '_');
5399 if (strncasecmp (start
, "iapsr", 5) == 0
5400 || strncasecmp (start
, "eapsr", 5) == 0
5401 || strncasecmp (start
, "xpsr", 4) == 0
5402 || strncasecmp (start
, "psr", 3) == 0)
5403 p
= start
+ strcspn (start
, "rR") + 1;
5405 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5411 /* If APSR is being written, a bitfield may be specified. Note that
5412 APSR itself is handled above. */
5413 if (psr
->field
<= 3)
5415 psr_field
= psr
->field
;
5421 /* M-profile MSR instructions have the mask field set to "10", except
5422 *PSR variants which modify APSR, which may use a different mask (and
5423 have been handled already). Do that by setting the PSR_f field
5425 return psr
->field
| (lhs
? PSR_f
: 0);
5428 goto unsupported_psr
;
5434 /* A suffix follows. */
5440 while (ISALNUM (*p
) || *p
== '_');
5444 /* APSR uses a notation for bits, rather than fields. */
5445 unsigned int nzcvq_bits
= 0;
5446 unsigned int g_bit
= 0;
5449 for (bit
= start
; bit
!= p
; bit
++)
5451 switch (TOLOWER (*bit
))
5454 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5458 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5462 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5466 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5470 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5474 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5478 inst
.error
= _("unexpected bit specified after APSR");
5483 if (nzcvq_bits
== 0x1f)
5488 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5490 inst
.error
= _("selected processor does not "
5491 "support DSP extension");
5498 if ((nzcvq_bits
& 0x20) != 0
5499 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5500 || (g_bit
& 0x2) != 0)
5502 inst
.error
= _("bad bitmask specified after APSR");
5508 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5513 psr_field
|= psr
->field
;
5519 goto error
; /* Garbage after "[CS]PSR". */
5521 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5522 is deprecated, but allow it anyway. */
5526 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5529 else if (!m_profile
)
5530 /* These bits are never right for M-profile devices: don't set them
5531 (only code paths which read/write APSR reach here). */
5532 psr_field
|= (PSR_c
| PSR_f
);
5538 inst
.error
= _("selected processor does not support requested special "
5539 "purpose register");
5543 inst
.error
= _("flag for {c}psr instruction expected");
5547 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5548 value suitable for splatting into the AIF field of the instruction. */
5551 parse_cps_flags (char **str
)
5560 case '\0': case ',':
5563 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5564 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5565 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5568 inst
.error
= _("unrecognized CPS flag");
5573 if (saw_a_flag
== 0)
5575 inst
.error
= _("missing CPS flags");
5583 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5584 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5587 parse_endian_specifier (char **str
)
5592 if (strncasecmp (s
, "BE", 2))
5594 else if (strncasecmp (s
, "LE", 2))
5598 inst
.error
= _("valid endian specifiers are be or le");
5602 if (ISALNUM (s
[2]) || s
[2] == '_')
5604 inst
.error
= _("valid endian specifiers are be or le");
5609 return little_endian
;
5612 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5613 value suitable for poking into the rotate field of an sxt or sxta
5614 instruction, or FAIL on error. */
5617 parse_ror (char **str
)
5622 if (strncasecmp (s
, "ROR", 3) == 0)
5626 inst
.error
= _("missing rotation field after comma");
5630 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5635 case 0: *str
= s
; return 0x0;
5636 case 8: *str
= s
; return 0x1;
5637 case 16: *str
= s
; return 0x2;
5638 case 24: *str
= s
; return 0x3;
5641 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5646 /* Parse a conditional code (from conds[] below). The value returned is in the
5647 range 0 .. 14, or FAIL. */
5649 parse_cond (char **str
)
5652 const struct asm_cond
*c
;
5654 /* Condition codes are always 2 characters, so matching up to
5655 3 characters is sufficient. */
5660 while (ISALPHA (*q
) && n
< 3)
5662 cond
[n
] = TOLOWER (*q
);
5667 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5670 inst
.error
= _("condition required");
5678 /* Parse an option for a barrier instruction. Returns the encoding for the
5681 parse_barrier (char **str
)
5684 const struct asm_barrier_opt
*o
;
5687 while (ISALPHA (*q
))
5690 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5699 /* Parse the operands of a table branch instruction. Similar to a memory
5702 parse_tb (char **str
)
5707 if (skip_past_char (&p
, '[') == FAIL
)
5709 inst
.error
= _("'[' expected");
5713 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5715 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5718 inst
.operands
[0].reg
= reg
;
5720 if (skip_past_comma (&p
) == FAIL
)
5722 inst
.error
= _("',' expected");
5726 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5728 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5731 inst
.operands
[0].imm
= reg
;
5733 if (skip_past_comma (&p
) == SUCCESS
)
5735 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5737 if (inst
.reloc
.exp
.X_add_number
!= 1)
5739 inst
.error
= _("invalid shift");
5742 inst
.operands
[0].shifted
= 1;
5745 if (skip_past_char (&p
, ']') == FAIL
)
5747 inst
.error
= _("']' expected");
5754 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5755 information on the types the operands can take and how they are encoded.
5756 Up to four operands may be read; this function handles setting the
5757 ".present" field for each read operand itself.
5758 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5759 else returns FAIL. */
5762 parse_neon_mov (char **str
, int *which_operand
)
5764 int i
= *which_operand
, val
;
5765 enum arm_reg_type rtype
;
5767 struct neon_type_el optype
;
5769 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5771 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5772 inst
.operands
[i
].reg
= val
;
5773 inst
.operands
[i
].isscalar
= 1;
5774 inst
.operands
[i
].vectype
= optype
;
5775 inst
.operands
[i
++].present
= 1;
5777 if (skip_past_comma (&ptr
) == FAIL
)
5780 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5783 inst
.operands
[i
].reg
= val
;
5784 inst
.operands
[i
].isreg
= 1;
5785 inst
.operands
[i
].present
= 1;
5787 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5790 /* Cases 0, 1, 2, 3, 5 (D only). */
5791 if (skip_past_comma (&ptr
) == FAIL
)
5794 inst
.operands
[i
].reg
= val
;
5795 inst
.operands
[i
].isreg
= 1;
5796 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5797 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5798 inst
.operands
[i
].isvec
= 1;
5799 inst
.operands
[i
].vectype
= optype
;
5800 inst
.operands
[i
++].present
= 1;
5802 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5804 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5805 Case 13: VMOV <Sd>, <Rm> */
5806 inst
.operands
[i
].reg
= val
;
5807 inst
.operands
[i
].isreg
= 1;
5808 inst
.operands
[i
].present
= 1;
5810 if (rtype
== REG_TYPE_NQ
)
5812 first_error (_("can't use Neon quad register here"));
5815 else if (rtype
!= REG_TYPE_VFS
)
5818 if (skip_past_comma (&ptr
) == FAIL
)
5820 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5822 inst
.operands
[i
].reg
= val
;
5823 inst
.operands
[i
].isreg
= 1;
5824 inst
.operands
[i
].present
= 1;
5827 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5830 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5831 Case 1: VMOV<c><q> <Dd>, <Dm>
5832 Case 8: VMOV.F32 <Sd>, <Sm>
5833 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5835 inst
.operands
[i
].reg
= val
;
5836 inst
.operands
[i
].isreg
= 1;
5837 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5838 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5839 inst
.operands
[i
].isvec
= 1;
5840 inst
.operands
[i
].vectype
= optype
;
5841 inst
.operands
[i
].present
= 1;
5843 if (skip_past_comma (&ptr
) == SUCCESS
)
5848 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5851 inst
.operands
[i
].reg
= val
;
5852 inst
.operands
[i
].isreg
= 1;
5853 inst
.operands
[i
++].present
= 1;
5855 if (skip_past_comma (&ptr
) == FAIL
)
5858 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5861 inst
.operands
[i
].reg
= val
;
5862 inst
.operands
[i
].isreg
= 1;
5863 inst
.operands
[i
++].present
= 1;
5866 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5867 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5868 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5869 Case 10: VMOV.F32 <Sd>, #<imm>
5870 Case 11: VMOV.F64 <Dd>, #<imm> */
5871 inst
.operands
[i
].immisfloat
= 1;
5872 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5873 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5874 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5878 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5882 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5885 inst
.operands
[i
].reg
= val
;
5886 inst
.operands
[i
].isreg
= 1;
5887 inst
.operands
[i
++].present
= 1;
5889 if (skip_past_comma (&ptr
) == FAIL
)
5892 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5894 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5895 inst
.operands
[i
].reg
= val
;
5896 inst
.operands
[i
].isscalar
= 1;
5897 inst
.operands
[i
].present
= 1;
5898 inst
.operands
[i
].vectype
= optype
;
5900 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5902 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5903 inst
.operands
[i
].reg
= val
;
5904 inst
.operands
[i
].isreg
= 1;
5905 inst
.operands
[i
++].present
= 1;
5907 if (skip_past_comma (&ptr
) == FAIL
)
5910 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5913 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5917 inst
.operands
[i
].reg
= val
;
5918 inst
.operands
[i
].isreg
= 1;
5919 inst
.operands
[i
].isvec
= 1;
5920 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5921 inst
.operands
[i
].vectype
= optype
;
5922 inst
.operands
[i
].present
= 1;
5924 if (rtype
== REG_TYPE_VFS
)
5928 if (skip_past_comma (&ptr
) == FAIL
)
5930 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5933 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5936 inst
.operands
[i
].reg
= val
;
5937 inst
.operands
[i
].isreg
= 1;
5938 inst
.operands
[i
].isvec
= 1;
5939 inst
.operands
[i
].issingle
= 1;
5940 inst
.operands
[i
].vectype
= optype
;
5941 inst
.operands
[i
].present
= 1;
5944 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5948 inst
.operands
[i
].reg
= val
;
5949 inst
.operands
[i
].isreg
= 1;
5950 inst
.operands
[i
].isvec
= 1;
5951 inst
.operands
[i
].issingle
= 1;
5952 inst
.operands
[i
].vectype
= optype
;
5953 inst
.operands
[i
++].present
= 1;
5958 first_error (_("parse error"));
5962 /* Successfully parsed the operands. Update args. */
5968 first_error (_("expected comma"));
5972 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5976 /* Use this macro when the operand constraints are different
5977 for ARM and THUMB (e.g. ldrd). */
5978 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5979 ((arm_operand) | ((thumb_operand) << 16))
5981 /* Matcher codes for parse_operands. */
5982 enum operand_parse_code
5984 OP_stop
, /* end of line */
5986 OP_RR
, /* ARM register */
5987 OP_RRnpc
, /* ARM register, not r15 */
5988 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5989 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5990 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5991 optional trailing ! */
5992 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5993 OP_RCP
, /* Coprocessor number */
5994 OP_RCN
, /* Coprocessor register */
5995 OP_RF
, /* FPA register */
5996 OP_RVS
, /* VFP single precision register */
5997 OP_RVD
, /* VFP double precision register (0..15) */
5998 OP_RND
, /* Neon double precision register (0..31) */
5999 OP_RNQ
, /* Neon quad precision register */
6000 OP_RVSD
, /* VFP single or double precision register */
6001 OP_RNDQ
, /* Neon double or quad precision register */
6002 OP_RNSDQ
, /* Neon single, double or quad precision register */
6003 OP_RNSC
, /* Neon scalar D[X] */
6004 OP_RVC
, /* VFP control register */
6005 OP_RMF
, /* Maverick F register */
6006 OP_RMD
, /* Maverick D register */
6007 OP_RMFX
, /* Maverick FX register */
6008 OP_RMDX
, /* Maverick DX register */
6009 OP_RMAX
, /* Maverick AX register */
6010 OP_RMDS
, /* Maverick DSPSC register */
6011 OP_RIWR
, /* iWMMXt wR register */
6012 OP_RIWC
, /* iWMMXt wC register */
6013 OP_RIWG
, /* iWMMXt wCG register */
6014 OP_RXA
, /* XScale accumulator register */
6016 OP_REGLST
, /* ARM register list */
6017 OP_VRSLST
, /* VFP single-precision register list */
6018 OP_VRDLST
, /* VFP double-precision register list */
6019 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6020 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6021 OP_NSTRLST
, /* Neon element/structure list */
6023 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6024 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6025 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6026 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6027 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6028 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6029 OP_VMOV
, /* Neon VMOV operands. */
6030 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6031 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6032 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6034 OP_I0
, /* immediate zero */
6035 OP_I7
, /* immediate value 0 .. 7 */
6036 OP_I15
, /* 0 .. 15 */
6037 OP_I16
, /* 1 .. 16 */
6038 OP_I16z
, /* 0 .. 16 */
6039 OP_I31
, /* 0 .. 31 */
6040 OP_I31w
, /* 0 .. 31, optional trailing ! */
6041 OP_I32
, /* 1 .. 32 */
6042 OP_I32z
, /* 0 .. 32 */
6043 OP_I63
, /* 0 .. 63 */
6044 OP_I63s
, /* -64 .. 63 */
6045 OP_I64
, /* 1 .. 64 */
6046 OP_I64z
, /* 0 .. 64 */
6047 OP_I255
, /* 0 .. 255 */
6049 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6050 OP_I7b
, /* 0 .. 7 */
6051 OP_I15b
, /* 0 .. 15 */
6052 OP_I31b
, /* 0 .. 31 */
6054 OP_SH
, /* shifter operand */
6055 OP_SHG
, /* shifter operand with possible group relocation */
6056 OP_ADDR
, /* Memory address expression (any mode) */
6057 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6058 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6059 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6060 OP_EXP
, /* arbitrary expression */
6061 OP_EXPi
, /* same, with optional immediate prefix */
6062 OP_EXPr
, /* same, with optional relocation suffix */
6063 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6065 OP_CPSF
, /* CPS flags */
6066 OP_ENDI
, /* Endianness specifier */
6067 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6068 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6069 OP_COND
, /* conditional code */
6070 OP_TB
, /* Table branch. */
6072 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6074 OP_RRnpc_I0
, /* ARM register or literal 0 */
6075 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6076 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6077 OP_RF_IF
, /* FPA register or immediate */
6078 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6079 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6081 /* Optional operands. */
6082 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6083 OP_oI31b
, /* 0 .. 31 */
6084 OP_oI32b
, /* 1 .. 32 */
6085 OP_oIffffb
, /* 0 .. 65535 */
6086 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6088 OP_oRR
, /* ARM register */
6089 OP_oRRnpc
, /* ARM register, not the PC */
6090 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6091 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6092 OP_oRND
, /* Optional Neon double precision register */
6093 OP_oRNQ
, /* Optional Neon quad precision register */
6094 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6095 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6096 OP_oSHll
, /* LSL immediate */
6097 OP_oSHar
, /* ASR immediate */
6098 OP_oSHllar
, /* LSL or ASR immediate */
6099 OP_oROR
, /* ROR 0/8/16/24 */
6100 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6102 /* Some pre-defined mixed (ARM/THUMB) operands. */
6103 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6104 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6105 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6107 OP_FIRST_OPTIONAL
= OP_oI7b
6110 /* Generic instruction operand parser. This does no encoding and no
6111 semantic validation; it merely squirrels values away in the inst
6112 structure. Returns SUCCESS or FAIL depending on whether the
6113 specified grammar matched. */
6115 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6117 unsigned const int *upat
= pattern
;
6118 char *backtrack_pos
= 0;
6119 const char *backtrack_error
= 0;
6120 int i
, val
, backtrack_index
= 0;
6121 enum arm_reg_type rtype
;
6122 parse_operand_result result
;
6123 unsigned int op_parse_code
;
6125 #define po_char_or_fail(chr) \
6128 if (skip_past_char (&str, chr) == FAIL) \
6133 #define po_reg_or_fail(regtype) \
6136 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6137 & inst.operands[i].vectype); \
6140 first_error (_(reg_expected_msgs[regtype])); \
6143 inst.operands[i].reg = val; \
6144 inst.operands[i].isreg = 1; \
6145 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6146 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6147 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6148 || rtype == REG_TYPE_VFD \
6149 || rtype == REG_TYPE_NQ); \
6153 #define po_reg_or_goto(regtype, label) \
6156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6157 & inst.operands[i].vectype); \
6161 inst.operands[i].reg = val; \
6162 inst.operands[i].isreg = 1; \
6163 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6164 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6165 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6166 || rtype == REG_TYPE_VFD \
6167 || rtype == REG_TYPE_NQ); \
6171 #define po_imm_or_fail(min, max, popt) \
6174 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6176 inst.operands[i].imm = val; \
6180 #define po_scalar_or_goto(elsz, label) \
6183 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6186 inst.operands[i].reg = val; \
6187 inst.operands[i].isscalar = 1; \
6191 #define po_misc_or_fail(expr) \
6199 #define po_misc_or_fail_no_backtrack(expr) \
6203 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6204 backtrack_pos = 0; \
6205 if (result != PARSE_OPERAND_SUCCESS) \
6210 #define po_barrier_or_imm(str) \
6213 val = parse_barrier (&str); \
6216 if (ISALPHA (*str)) \
6223 if ((inst.instruction & 0xf0) == 0x60 \
6226 /* ISB can only take SY as an option. */ \
6227 inst.error = _("invalid barrier type"); \
6234 skip_whitespace (str
);
6236 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6238 op_parse_code
= upat
[i
];
6239 if (op_parse_code
>= 1<<16)
6240 op_parse_code
= thumb
? (op_parse_code
>> 16)
6241 : (op_parse_code
& ((1<<16)-1));
6243 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6245 /* Remember where we are in case we need to backtrack. */
6246 gas_assert (!backtrack_pos
);
6247 backtrack_pos
= str
;
6248 backtrack_error
= inst
.error
;
6249 backtrack_index
= i
;
6252 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6253 po_char_or_fail (',');
6255 switch (op_parse_code
)
6263 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6264 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6265 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6266 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6267 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6268 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6270 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6272 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6274 /* Also accept generic coprocessor regs for unknown registers. */
6276 po_reg_or_fail (REG_TYPE_CN
);
6278 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6279 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6280 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6281 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6282 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6283 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6284 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6285 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6286 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6287 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6289 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6291 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6292 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6294 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6296 /* Neon scalar. Using an element size of 8 means that some invalid
6297 scalars are accepted here, so deal with those in later code. */
6298 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6302 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6305 po_imm_or_fail (0, 0, TRUE
);
6310 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6315 po_scalar_or_goto (8, try_rr
);
6318 po_reg_or_fail (REG_TYPE_RN
);
6324 po_scalar_or_goto (8, try_nsdq
);
6327 po_reg_or_fail (REG_TYPE_NSDQ
);
6333 po_scalar_or_goto (8, try_ndq
);
6336 po_reg_or_fail (REG_TYPE_NDQ
);
6342 po_scalar_or_goto (8, try_vfd
);
6345 po_reg_or_fail (REG_TYPE_VFD
);
6350 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6351 not careful then bad things might happen. */
6352 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6357 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6360 /* There's a possibility of getting a 64-bit immediate here, so
6361 we need special handling. */
6362 if (parse_big_immediate (&str
, i
) == FAIL
)
6364 inst
.error
= _("immediate value is out of range");
6372 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6375 po_imm_or_fail (0, 63, TRUE
);
6380 po_char_or_fail ('[');
6381 po_reg_or_fail (REG_TYPE_RN
);
6382 po_char_or_fail (']');
6388 po_reg_or_fail (REG_TYPE_RN
);
6389 if (skip_past_char (&str
, '!') == SUCCESS
)
6390 inst
.operands
[i
].writeback
= 1;
6394 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6395 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6396 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6397 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6398 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6399 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6400 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6401 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6402 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6403 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6404 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6405 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6407 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6409 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6410 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6412 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6413 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6414 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6416 /* Immediate variants */
6418 po_char_or_fail ('{');
6419 po_imm_or_fail (0, 255, TRUE
);
6420 po_char_or_fail ('}');
6424 /* The expression parser chokes on a trailing !, so we have
6425 to find it first and zap it. */
6428 while (*s
&& *s
!= ',')
6433 inst
.operands
[i
].writeback
= 1;
6435 po_imm_or_fail (0, 31, TRUE
);
6443 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6448 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6453 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6455 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6457 val
= parse_reloc (&str
);
6460 inst
.error
= _("unrecognized relocation suffix");
6463 else if (val
!= BFD_RELOC_UNUSED
)
6465 inst
.operands
[i
].imm
= val
;
6466 inst
.operands
[i
].hasreloc
= 1;
6471 /* Operand for MOVW or MOVT. */
6473 po_misc_or_fail (parse_half (&str
));
6476 /* Register or expression. */
6477 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6478 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6480 /* Register or immediate. */
6481 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6482 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6484 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6486 if (!is_immediate_prefix (*str
))
6489 val
= parse_fpa_immediate (&str
);
6492 /* FPA immediates are encoded as registers 8-15.
6493 parse_fpa_immediate has already applied the offset. */
6494 inst
.operands
[i
].reg
= val
;
6495 inst
.operands
[i
].isreg
= 1;
6498 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6499 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6501 /* Two kinds of register. */
6504 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6506 || (rege
->type
!= REG_TYPE_MMXWR
6507 && rege
->type
!= REG_TYPE_MMXWC
6508 && rege
->type
!= REG_TYPE_MMXWCG
))
6510 inst
.error
= _("iWMMXt data or control register expected");
6513 inst
.operands
[i
].reg
= rege
->number
;
6514 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6520 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6522 || (rege
->type
!= REG_TYPE_MMXWC
6523 && rege
->type
!= REG_TYPE_MMXWCG
))
6525 inst
.error
= _("iWMMXt control register expected");
6528 inst
.operands
[i
].reg
= rege
->number
;
6529 inst
.operands
[i
].isreg
= 1;
6534 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6535 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6536 case OP_oROR
: val
= parse_ror (&str
); break;
6537 case OP_COND
: val
= parse_cond (&str
); break;
6538 case OP_oBARRIER_I15
:
6539 po_barrier_or_imm (str
); break;
6541 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6547 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6548 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6550 inst
.error
= _("Banked registers are not available with this "
6556 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6560 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6563 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6565 if (strncasecmp (str
, "APSR_", 5) == 0)
6572 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6573 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6574 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6575 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6576 default: found
= 16;
6580 inst
.operands
[i
].isvec
= 1;
6581 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6582 inst
.operands
[i
].reg
= REG_PC
;
6589 po_misc_or_fail (parse_tb (&str
));
6592 /* Register lists. */
6594 val
= parse_reg_list (&str
);
6597 inst
.operands
[1].writeback
= 1;
6603 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6607 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6611 /* Allow Q registers too. */
6612 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6617 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6619 inst
.operands
[i
].issingle
= 1;
6624 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6629 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6630 &inst
.operands
[i
].vectype
);
6633 /* Addressing modes */
6635 po_misc_or_fail (parse_address (&str
, i
));
6639 po_misc_or_fail_no_backtrack (
6640 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6644 po_misc_or_fail_no_backtrack (
6645 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6649 po_misc_or_fail_no_backtrack (
6650 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6654 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6658 po_misc_or_fail_no_backtrack (
6659 parse_shifter_operand_group_reloc (&str
, i
));
6663 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6667 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6671 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6675 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6678 /* Various value-based sanity checks and shared operations. We
6679 do not signal immediate failures for the register constraints;
6680 this allows a syntax error to take precedence. */
6681 switch (op_parse_code
)
6689 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6690 inst
.error
= BAD_PC
;
6695 if (inst
.operands
[i
].isreg
)
6697 if (inst
.operands
[i
].reg
== REG_PC
)
6698 inst
.error
= BAD_PC
;
6699 else if (inst
.operands
[i
].reg
== REG_SP
)
6700 inst
.error
= BAD_SP
;
6705 if (inst
.operands
[i
].isreg
6706 && inst
.operands
[i
].reg
== REG_PC
6707 && (inst
.operands
[i
].writeback
|| thumb
))
6708 inst
.error
= BAD_PC
;
6717 case OP_oBARRIER_I15
:
6726 inst
.operands
[i
].imm
= val
;
6733 /* If we get here, this operand was successfully parsed. */
6734 inst
.operands
[i
].present
= 1;
6738 inst
.error
= BAD_ARGS
;
6743 /* The parse routine should already have set inst.error, but set a
6744 default here just in case. */
6746 inst
.error
= _("syntax error");
6750 /* Do not backtrack over a trailing optional argument that
6751 absorbed some text. We will only fail again, with the
6752 'garbage following instruction' error message, which is
6753 probably less helpful than the current one. */
6754 if (backtrack_index
== i
&& backtrack_pos
!= str
6755 && upat
[i
+1] == OP_stop
)
6758 inst
.error
= _("syntax error");
6762 /* Try again, skipping the optional argument at backtrack_pos. */
6763 str
= backtrack_pos
;
6764 inst
.error
= backtrack_error
;
6765 inst
.operands
[backtrack_index
].present
= 0;
6766 i
= backtrack_index
;
6770 /* Check that we have parsed all the arguments. */
6771 if (*str
!= '\0' && !inst
.error
)
6772 inst
.error
= _("garbage following instruction");
6774 return inst
.error
? FAIL
: SUCCESS
;
6777 #undef po_char_or_fail
6778 #undef po_reg_or_fail
6779 #undef po_reg_or_goto
6780 #undef po_imm_or_fail
6781 #undef po_scalar_or_fail
6782 #undef po_barrier_or_imm
6784 /* Shorthand macro for instruction encoding functions issuing errors. */
6785 #define constraint(expr, err) \
6796 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6797 instructions are unpredictable if these registers are used. This
6798 is the BadReg predicate in ARM's Thumb-2 documentation. */
6799 #define reject_bad_reg(reg) \
6801 if (reg == REG_SP || reg == REG_PC) \
6803 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6808 /* If REG is R13 (the stack pointer), warn that its use is
6810 #define warn_deprecated_sp(reg) \
6812 if (warn_on_deprecated && reg == REG_SP) \
6813 as_warn (_("use of r13 is deprecated")); \
6816 /* Functions for operand encoding. ARM, then Thumb. */
6818 #define rotate_left(v, n) (v << n | v >> (32 - n))
6820 /* If VAL can be encoded in the immediate field of an ARM instruction,
6821 return the encoded form. Otherwise, return FAIL. */
6824 encode_arm_immediate (unsigned int val
)
6828 for (i
= 0; i
< 32; i
+= 2)
6829 if ((a
= rotate_left (val
, i
)) <= 0xff)
6830 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6835 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6836 return the encoded form. Otherwise, return FAIL. */
6838 encode_thumb32_immediate (unsigned int val
)
6845 for (i
= 1; i
<= 24; i
++)
6848 if ((val
& ~(0xff << i
)) == 0)
6849 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6853 if (val
== ((a
<< 16) | a
))
6855 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6859 if (val
== ((a
<< 16) | a
))
6860 return 0x200 | (a
>> 8);
6864 /* Encode a VFP SP or DP register number into inst.instruction. */
6867 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6869 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6875 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6878 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6883 first_error (_("D register out of range for selected VFP version"));
6891 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6895 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6899 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6903 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6907 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6911 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6919 /* Encode a <shift> in an ARM-format instruction. The immediate,
6920 if any, is handled by md_apply_fix. */
6922 encode_arm_shift (int i
)
6924 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6925 inst
.instruction
|= SHIFT_ROR
<< 5;
6928 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6929 if (inst
.operands
[i
].immisreg
)
6931 inst
.instruction
|= SHIFT_BY_REG
;
6932 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6935 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6940 encode_arm_shifter_operand (int i
)
6942 if (inst
.operands
[i
].isreg
)
6944 inst
.instruction
|= inst
.operands
[i
].reg
;
6945 encode_arm_shift (i
);
6948 inst
.instruction
|= INST_IMMEDIATE
;
6951 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6953 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6955 gas_assert (inst
.operands
[i
].isreg
);
6956 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6958 if (inst
.operands
[i
].preind
)
6962 inst
.error
= _("instruction does not accept preindexed addressing");
6965 inst
.instruction
|= PRE_INDEX
;
6966 if (inst
.operands
[i
].writeback
)
6967 inst
.instruction
|= WRITE_BACK
;
6970 else if (inst
.operands
[i
].postind
)
6972 gas_assert (inst
.operands
[i
].writeback
);
6974 inst
.instruction
|= WRITE_BACK
;
6976 else /* unindexed - only for coprocessor */
6978 inst
.error
= _("instruction does not accept unindexed addressing");
6982 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6983 && (((inst
.instruction
& 0x000f0000) >> 16)
6984 == ((inst
.instruction
& 0x0000f000) >> 12)))
6985 as_warn ((inst
.instruction
& LOAD_BIT
)
6986 ? _("destination register same as write-back base")
6987 : _("source register same as write-back base"));
6990 /* inst.operands[i] was set up by parse_address. Encode it into an
6991 ARM-format mode 2 load or store instruction. If is_t is true,
6992 reject forms that cannot be used with a T instruction (i.e. not
6995 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6997 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6999 encode_arm_addr_mode_common (i
, is_t
);
7001 if (inst
.operands
[i
].immisreg
)
7003 constraint ((inst
.operands
[i
].imm
== REG_PC
7004 || (is_pc
&& inst
.operands
[i
].writeback
)),
7006 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7007 inst
.instruction
|= inst
.operands
[i
].imm
;
7008 if (!inst
.operands
[i
].negative
)
7009 inst
.instruction
|= INDEX_UP
;
7010 if (inst
.operands
[i
].shifted
)
7012 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7013 inst
.instruction
|= SHIFT_ROR
<< 5;
7016 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7017 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7021 else /* immediate offset in inst.reloc */
7023 if (is_pc
&& !inst
.reloc
.pc_rel
)
7025 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7027 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7028 cannot use PC in addressing.
7029 PC cannot be used in writeback addressing, either. */
7030 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7033 /* Use of PC in str is deprecated for ARMv7. */
7034 if (warn_on_deprecated
7036 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7037 as_warn (_("use of PC in this instruction is deprecated"));
7040 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7041 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7045 /* inst.operands[i] was set up by parse_address. Encode it into an
7046 ARM-format mode 3 load or store instruction. Reject forms that
7047 cannot be used with such instructions. If is_t is true, reject
7048 forms that cannot be used with a T instruction (i.e. not
7051 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7053 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7055 inst
.error
= _("instruction does not accept scaled register index");
7059 encode_arm_addr_mode_common (i
, is_t
);
7061 if (inst
.operands
[i
].immisreg
)
7063 constraint ((inst
.operands
[i
].imm
== REG_PC
7064 || inst
.operands
[i
].reg
== REG_PC
),
7066 inst
.instruction
|= inst
.operands
[i
].imm
;
7067 if (!inst
.operands
[i
].negative
)
7068 inst
.instruction
|= INDEX_UP
;
7070 else /* immediate offset in inst.reloc */
7072 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7073 && inst
.operands
[i
].writeback
),
7075 inst
.instruction
|= HWOFFSET_IMM
;
7076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7077 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7081 /* inst.operands[i] was set up by parse_address. Encode it into an
7082 ARM-format instruction. Reject all forms which cannot be encoded
7083 into a coprocessor load/store instruction. If wb_ok is false,
7084 reject use of writeback; if unind_ok is false, reject use of
7085 unindexed addressing. If reloc_override is not 0, use it instead
7086 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7087 (in which case it is preserved). */
7090 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7092 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7094 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7096 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7098 gas_assert (!inst
.operands
[i
].writeback
);
7101 inst
.error
= _("instruction does not support unindexed addressing");
7104 inst
.instruction
|= inst
.operands
[i
].imm
;
7105 inst
.instruction
|= INDEX_UP
;
7109 if (inst
.operands
[i
].preind
)
7110 inst
.instruction
|= PRE_INDEX
;
7112 if (inst
.operands
[i
].writeback
)
7114 if (inst
.operands
[i
].reg
== REG_PC
)
7116 inst
.error
= _("pc may not be used with write-back");
7121 inst
.error
= _("instruction does not support writeback");
7124 inst
.instruction
|= WRITE_BACK
;
7128 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7129 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7130 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7131 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7134 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7136 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7142 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7143 Determine whether it can be performed with a move instruction; if
7144 it can, convert inst.instruction to that move instruction and
7145 return TRUE; if it can't, convert inst.instruction to a literal-pool
7146 load and return FALSE. If this is not a valid thing to do in the
7147 current context, set inst.error and return TRUE.
7149 inst.operands[i] describes the destination register. */
7152 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7157 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7161 if ((inst
.instruction
& tbit
) == 0)
7163 inst
.error
= _("invalid pseudo operation");
7166 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7168 inst
.error
= _("constant expression expected");
7171 if (inst
.reloc
.exp
.X_op
== O_constant
)
7175 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7177 /* This can be done with a mov(1) instruction. */
7178 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7179 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7185 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7188 /* This can be done with a mov instruction. */
7189 inst
.instruction
&= LITERAL_MASK
;
7190 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7191 inst
.instruction
|= value
& 0xfff;
7195 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7198 /* This can be done with a mvn instruction. */
7199 inst
.instruction
&= LITERAL_MASK
;
7200 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7201 inst
.instruction
|= value
& 0xfff;
7207 if (add_to_lit_pool () == FAIL
)
7209 inst
.error
= _("literal pool insertion failed");
7212 inst
.operands
[1].reg
= REG_PC
;
7213 inst
.operands
[1].isreg
= 1;
7214 inst
.operands
[1].preind
= 1;
7215 inst
.reloc
.pc_rel
= 1;
7216 inst
.reloc
.type
= (thumb_p
7217 ? BFD_RELOC_ARM_THUMB_OFFSET
7219 ? BFD_RELOC_ARM_HWLITERAL
7220 : BFD_RELOC_ARM_LITERAL
));
7224 /* Functions for instruction encoding, sorted by sub-architecture.
7225 First some generics; their names are taken from the conventional
7226 bit positions for register arguments in ARM format instructions. */
7236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7243 inst
.instruction
|= inst
.operands
[1].reg
;
7249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7250 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7256 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7257 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7263 unsigned Rn
= inst
.operands
[2].reg
;
7264 /* Enforce restrictions on SWP instruction. */
7265 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7267 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7268 _("Rn must not overlap other operands"));
7270 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7271 if (warn_on_deprecated
7272 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7273 as_warn (_("swp{b} use is deprecated for this architecture"));
7276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7277 inst
.instruction
|= inst
.operands
[1].reg
;
7278 inst
.instruction
|= Rn
<< 16;
7284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7286 inst
.instruction
|= inst
.operands
[2].reg
;
7292 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7293 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7294 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7295 || inst
.reloc
.exp
.X_add_number
!= 0),
7297 inst
.instruction
|= inst
.operands
[0].reg
;
7298 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7299 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7305 inst
.instruction
|= inst
.operands
[0].imm
;
7311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7312 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7315 /* ARM instructions, in alphabetical order by function name (except
7316 that wrapper functions appear immediately after the function they
7319 /* This is a pseudo-op of the form "adr rd, label" to be converted
7320 into a relative address of the form "add rd, pc, #label-.-8". */
7325 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7327 /* Frag hacking will turn this into a sub instruction if the offset turns
7328 out to be negative. */
7329 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7330 inst
.reloc
.pc_rel
= 1;
7331 inst
.reloc
.exp
.X_add_number
-= 8;
7334 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7335 into a relative address of the form:
7336 add rd, pc, #low(label-.-8)"
7337 add rd, rd, #high(label-.-8)" */
7342 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7344 /* Frag hacking will turn this into a sub instruction if the offset turns
7345 out to be negative. */
7346 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7347 inst
.reloc
.pc_rel
= 1;
7348 inst
.size
= INSN_SIZE
* 2;
7349 inst
.reloc
.exp
.X_add_number
-= 8;
7355 if (!inst
.operands
[1].present
)
7356 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7358 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7359 encode_arm_shifter_operand (2);
7365 if (inst
.operands
[0].present
)
7367 constraint ((inst
.instruction
& 0xf0) != 0x40
7368 && inst
.operands
[0].imm
> 0xf
7369 && inst
.operands
[0].imm
< 0x0,
7370 _("bad barrier type"));
7371 inst
.instruction
|= inst
.operands
[0].imm
;
7374 inst
.instruction
|= 0xf;
7380 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7381 constraint (msb
> 32, _("bit-field extends past end of register"));
7382 /* The instruction encoding stores the LSB and MSB,
7383 not the LSB and width. */
7384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7385 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7386 inst
.instruction
|= (msb
- 1) << 16;
7394 /* #0 in second position is alternative syntax for bfc, which is
7395 the same instruction but with REG_PC in the Rm field. */
7396 if (!inst
.operands
[1].isreg
)
7397 inst
.operands
[1].reg
= REG_PC
;
7399 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7400 constraint (msb
> 32, _("bit-field extends past end of register"));
7401 /* The instruction encoding stores the LSB and MSB,
7402 not the LSB and width. */
7403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7404 inst
.instruction
|= inst
.operands
[1].reg
;
7405 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7406 inst
.instruction
|= (msb
- 1) << 16;
7412 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7413 _("bit-field extends past end of register"));
7414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7415 inst
.instruction
|= inst
.operands
[1].reg
;
7416 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7417 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7420 /* ARM V5 breakpoint instruction (argument parse)
7421 BKPT <16 bit unsigned immediate>
7422 Instruction is not conditional.
7423 The bit pattern given in insns[] has the COND_ALWAYS condition,
7424 and it is an error if the caller tried to override that. */
7429 /* Top 12 of 16 bits to bits 19:8. */
7430 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7432 /* Bottom 4 of 16 bits to bits 3:0. */
7433 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7437 encode_branch (int default_reloc
)
7439 if (inst
.operands
[0].hasreloc
)
7441 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7442 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7443 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7444 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7445 ? BFD_RELOC_ARM_PLT32
7446 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7449 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7450 inst
.reloc
.pc_rel
= 1;
7457 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7458 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7461 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7468 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7470 if (inst
.cond
== COND_ALWAYS
)
7471 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7473 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7477 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7480 /* ARM V5 branch-link-exchange instruction (argument parse)
7481 BLX <target_addr> ie BLX(1)
7482 BLX{<condition>} <Rm> ie BLX(2)
7483 Unfortunately, there are two different opcodes for this mnemonic.
7484 So, the insns[].value is not used, and the code here zaps values
7485 into inst.instruction.
7486 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7491 if (inst
.operands
[0].isreg
)
7493 /* Arg is a register; the opcode provided by insns[] is correct.
7494 It is not illegal to do "blx pc", just useless. */
7495 if (inst
.operands
[0].reg
== REG_PC
)
7496 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7498 inst
.instruction
|= inst
.operands
[0].reg
;
7502 /* Arg is an address; this instruction cannot be executed
7503 conditionally, and the opcode must be adjusted.
7504 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7505 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7506 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7507 inst
.instruction
= 0xfa000000;
7508 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7515 bfd_boolean want_reloc
;
7517 if (inst
.operands
[0].reg
== REG_PC
)
7518 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7520 inst
.instruction
|= inst
.operands
[0].reg
;
7521 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7522 it is for ARMv4t or earlier. */
7523 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7524 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7528 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7533 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7537 /* ARM v5TEJ. Jump to Jazelle code. */
7542 if (inst
.operands
[0].reg
== REG_PC
)
7543 as_tsktsk (_("use of r15 in bxj is not really useful"));
7545 inst
.instruction
|= inst
.operands
[0].reg
;
7548 /* Co-processor data operation:
7549 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7550 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7555 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7556 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7557 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7558 inst
.instruction
|= inst
.operands
[4].reg
;
7559 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7566 encode_arm_shifter_operand (1);
7569 /* Transfer between coprocessor and ARM registers.
7570 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7575 No special properties. */
7582 Rd
= inst
.operands
[2].reg
;
7585 if (inst
.instruction
== 0xee000010
7586 || inst
.instruction
== 0xfe000010)
7588 reject_bad_reg (Rd
);
7591 constraint (Rd
== REG_SP
, BAD_SP
);
7596 if (inst
.instruction
== 0xe000010)
7597 constraint (Rd
== REG_PC
, BAD_PC
);
7601 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7602 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7603 inst
.instruction
|= Rd
<< 12;
7604 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7605 inst
.instruction
|= inst
.operands
[4].reg
;
7606 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7609 /* Transfer between coprocessor register and pair of ARM registers.
7610 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7615 Two XScale instructions are special cases of these:
7617 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7618 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7620 Result unpredictable if Rd or Rn is R15. */
7627 Rd
= inst
.operands
[2].reg
;
7628 Rn
= inst
.operands
[3].reg
;
7632 reject_bad_reg (Rd
);
7633 reject_bad_reg (Rn
);
7637 constraint (Rd
== REG_PC
, BAD_PC
);
7638 constraint (Rn
== REG_PC
, BAD_PC
);
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7642 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7643 inst
.instruction
|= Rd
<< 12;
7644 inst
.instruction
|= Rn
<< 16;
7645 inst
.instruction
|= inst
.operands
[4].reg
;
7651 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7652 if (inst
.operands
[1].present
)
7654 inst
.instruction
|= CPSI_MMOD
;
7655 inst
.instruction
|= inst
.operands
[1].imm
;
7662 inst
.instruction
|= inst
.operands
[0].imm
;
7668 unsigned Rd
, Rn
, Rm
;
7670 Rd
= inst
.operands
[0].reg
;
7671 Rn
= (inst
.operands
[1].present
7672 ? inst
.operands
[1].reg
: Rd
);
7673 Rm
= inst
.operands
[2].reg
;
7675 constraint ((Rd
== REG_PC
), BAD_PC
);
7676 constraint ((Rn
== REG_PC
), BAD_PC
);
7677 constraint ((Rm
== REG_PC
), BAD_PC
);
7679 inst
.instruction
|= Rd
<< 16;
7680 inst
.instruction
|= Rn
<< 0;
7681 inst
.instruction
|= Rm
<< 8;
7687 /* There is no IT instruction in ARM mode. We
7688 process it to do the validation as if in
7689 thumb mode, just in case the code gets
7690 assembled for thumb using the unified syntax. */
7695 set_it_insn_type (IT_INSN
);
7696 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7697 now_it
.cc
= inst
.operands
[0].imm
;
7704 int base_reg
= inst
.operands
[0].reg
;
7705 int range
= inst
.operands
[1].imm
;
7707 inst
.instruction
|= base_reg
<< 16;
7708 inst
.instruction
|= range
;
7710 if (inst
.operands
[1].writeback
)
7711 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7713 if (inst
.operands
[0].writeback
)
7715 inst
.instruction
|= WRITE_BACK
;
7716 /* Check for unpredictable uses of writeback. */
7717 if (inst
.instruction
& LOAD_BIT
)
7719 /* Not allowed in LDM type 2. */
7720 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7721 && ((range
& (1 << REG_PC
)) == 0))
7722 as_warn (_("writeback of base register is UNPREDICTABLE"));
7723 /* Only allowed if base reg not in list for other types. */
7724 else if (range
& (1 << base_reg
))
7725 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7729 /* Not allowed for type 2. */
7730 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7731 as_warn (_("writeback of base register is UNPREDICTABLE"));
7732 /* Only allowed if base reg not in list, or first in list. */
7733 else if ((range
& (1 << base_reg
))
7734 && (range
& ((1 << base_reg
) - 1)))
7735 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7740 /* ARMv5TE load-consecutive (argument parse)
7749 constraint (inst
.operands
[0].reg
% 2 != 0,
7750 _("first destination register must be even"));
7751 constraint (inst
.operands
[1].present
7752 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7753 _("can only load two consecutive registers"));
7754 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7755 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7757 if (!inst
.operands
[1].present
)
7758 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7760 if (inst
.instruction
& LOAD_BIT
)
7762 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7763 register and the first register written; we have to diagnose
7764 overlap between the base and the second register written here. */
7766 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7767 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7768 as_warn (_("base register written back, and overlaps "
7769 "second destination register"));
7771 /* For an index-register load, the index register must not overlap the
7772 destination (even if not write-back). */
7773 else if (inst
.operands
[2].immisreg
7774 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7775 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7776 as_warn (_("index register overlaps destination register"));
7779 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7780 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7786 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7787 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7788 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7789 || inst
.operands
[1].negative
7790 /* This can arise if the programmer has written
7792 or if they have mistakenly used a register name as the last
7795 It is very difficult to distinguish between these two cases
7796 because "rX" might actually be a label. ie the register
7797 name has been occluded by a symbol of the same name. So we
7798 just generate a general 'bad addressing mode' type error
7799 message and leave it up to the programmer to discover the
7800 true cause and fix their mistake. */
7801 || (inst
.operands
[1].reg
== REG_PC
),
7804 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7805 || inst
.reloc
.exp
.X_add_number
!= 0,
7806 _("offset must be zero in ARM encoding"));
7808 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7811 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7812 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7818 constraint (inst
.operands
[0].reg
% 2 != 0,
7819 _("even register required"));
7820 constraint (inst
.operands
[1].present
7821 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7822 _("can only load two consecutive registers"));
7823 /* If op 1 were present and equal to PC, this function wouldn't
7824 have been called in the first place. */
7825 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7827 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7828 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7835 if (!inst
.operands
[1].isreg
)
7836 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7838 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7844 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7846 if (inst
.operands
[1].preind
)
7848 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7849 || inst
.reloc
.exp
.X_add_number
!= 0,
7850 _("this instruction requires a post-indexed address"));
7852 inst
.operands
[1].preind
= 0;
7853 inst
.operands
[1].postind
= 1;
7854 inst
.operands
[1].writeback
= 1;
7856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7857 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7860 /* Halfword and signed-byte load/store operations. */
7865 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7867 if (!inst
.operands
[1].isreg
)
7868 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7870 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7876 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7878 if (inst
.operands
[1].preind
)
7880 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7881 || inst
.reloc
.exp
.X_add_number
!= 0,
7882 _("this instruction requires a post-indexed address"));
7884 inst
.operands
[1].preind
= 0;
7885 inst
.operands
[1].postind
= 1;
7886 inst
.operands
[1].writeback
= 1;
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7892 /* Co-processor register load/store.
7893 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7897 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7898 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7899 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7905 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7906 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7907 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7908 && !(inst
.instruction
& 0x00400000))
7909 as_tsktsk (_("Rd and Rm should be different in mla"));
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7912 inst
.instruction
|= inst
.operands
[1].reg
;
7913 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7914 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7921 encode_arm_shifter_operand (1);
7924 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7931 top
= (inst
.instruction
& 0x00400000) != 0;
7932 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7933 _(":lower16: not allowed this instruction"));
7934 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7935 _(":upper16: not allowed instruction"));
7936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7937 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7939 imm
= inst
.reloc
.exp
.X_add_number
;
7940 /* The value is in two pieces: 0:11, 16:19. */
7941 inst
.instruction
|= (imm
& 0x00000fff);
7942 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7946 static void do_vfp_nsyn_opcode (const char *);
7949 do_vfp_nsyn_mrs (void)
7951 if (inst
.operands
[0].isvec
)
7953 if (inst
.operands
[1].reg
!= 1)
7954 first_error (_("operand 1 must be FPSCR"));
7955 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7956 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7957 do_vfp_nsyn_opcode ("fmstat");
7959 else if (inst
.operands
[1].isvec
)
7960 do_vfp_nsyn_opcode ("fmrx");
7968 do_vfp_nsyn_msr (void)
7970 if (inst
.operands
[0].isvec
)
7971 do_vfp_nsyn_opcode ("fmxr");
7981 unsigned Rt
= inst
.operands
[0].reg
;
7983 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7985 inst
.error
= BAD_SP
;
7989 /* APSR_ sets isvec. All other refs to PC are illegal. */
7990 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7992 inst
.error
= BAD_PC
;
7996 if (inst
.operands
[1].reg
!= 1)
7997 first_error (_("operand 1 must be FPSCR"));
7999 inst
.instruction
|= (Rt
<< 12);
8005 unsigned Rt
= inst
.operands
[1].reg
;
8008 reject_bad_reg (Rt
);
8009 else if (Rt
== REG_PC
)
8011 inst
.error
= BAD_PC
;
8015 if (inst
.operands
[0].reg
!= 1)
8016 first_error (_("operand 0 must be FPSCR"));
8018 inst
.instruction
|= (Rt
<< 12);
8026 if (do_vfp_nsyn_mrs () == SUCCESS
)
8029 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8032 if (inst
.operands
[1].isreg
)
8034 br
= inst
.operands
[1].reg
;
8035 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8036 as_bad (_("bad register for mrs"));
8040 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8041 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8043 _("'APSR', 'CPSR' or 'SPSR' expected"));
8044 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8047 inst
.instruction
|= br
;
8050 /* Two possible forms:
8051 "{C|S}PSR_<field>, Rm",
8052 "{C|S}PSR_f, #expression". */
8057 if (do_vfp_nsyn_msr () == SUCCESS
)
8060 inst
.instruction
|= inst
.operands
[0].imm
;
8061 if (inst
.operands
[1].isreg
)
8062 inst
.instruction
|= inst
.operands
[1].reg
;
8065 inst
.instruction
|= INST_IMMEDIATE
;
8066 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8067 inst
.reloc
.pc_rel
= 0;
8074 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8076 if (!inst
.operands
[2].present
)
8077 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8078 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8079 inst
.instruction
|= inst
.operands
[1].reg
;
8080 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8082 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8083 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8084 as_tsktsk (_("Rd and Rm should be different in mul"));
8087 /* Long Multiply Parser
8088 UMULL RdLo, RdHi, Rm, Rs
8089 SMULL RdLo, RdHi, Rm, Rs
8090 UMLAL RdLo, RdHi, Rm, Rs
8091 SMLAL RdLo, RdHi, Rm, Rs. */
8096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8098 inst
.instruction
|= inst
.operands
[2].reg
;
8099 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8101 /* rdhi and rdlo must be different. */
8102 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8103 as_tsktsk (_("rdhi and rdlo must be different"));
8105 /* rdhi, rdlo and rm must all be different before armv6. */
8106 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8107 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8108 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8109 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8115 if (inst
.operands
[0].present
8116 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8118 /* Architectural NOP hints are CPSR sets with no bits selected. */
8119 inst
.instruction
&= 0xf0000000;
8120 inst
.instruction
|= 0x0320f000;
8121 if (inst
.operands
[0].present
)
8122 inst
.instruction
|= inst
.operands
[0].imm
;
8126 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8127 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8128 Condition defaults to COND_ALWAYS.
8129 Error if Rd, Rn or Rm are R15. */
8134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8135 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8136 inst
.instruction
|= inst
.operands
[2].reg
;
8137 if (inst
.operands
[3].present
)
8138 encode_arm_shift (3);
8141 /* ARM V6 PKHTB (Argument Parse). */
8146 if (!inst
.operands
[3].present
)
8148 /* If the shift specifier is omitted, turn the instruction
8149 into pkhbt rd, rm, rn. */
8150 inst
.instruction
&= 0xfff00010;
8151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8152 inst
.instruction
|= inst
.operands
[1].reg
;
8153 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8158 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8159 inst
.instruction
|= inst
.operands
[2].reg
;
8160 encode_arm_shift (3);
8164 /* ARMv5TE: Preload-Cache
8165 MP Extensions: Preload for write
8169 Syntactically, like LDR with B=1, W=0, L=1. */
8174 constraint (!inst
.operands
[0].isreg
,
8175 _("'[' expected after PLD mnemonic"));
8176 constraint (inst
.operands
[0].postind
,
8177 _("post-indexed expression used in preload instruction"));
8178 constraint (inst
.operands
[0].writeback
,
8179 _("writeback used in preload instruction"));
8180 constraint (!inst
.operands
[0].preind
,
8181 _("unindexed addressing used in preload instruction"));
8182 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8185 /* ARMv7: PLI <addr_mode> */
8189 constraint (!inst
.operands
[0].isreg
,
8190 _("'[' expected after PLI mnemonic"));
8191 constraint (inst
.operands
[0].postind
,
8192 _("post-indexed expression used in preload instruction"));
8193 constraint (inst
.operands
[0].writeback
,
8194 _("writeback used in preload instruction"));
8195 constraint (!inst
.operands
[0].preind
,
8196 _("unindexed addressing used in preload instruction"));
8197 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8198 inst
.instruction
&= ~PRE_INDEX
;
8204 inst
.operands
[1] = inst
.operands
[0];
8205 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8206 inst
.operands
[0].isreg
= 1;
8207 inst
.operands
[0].writeback
= 1;
8208 inst
.operands
[0].reg
= REG_SP
;
8212 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8213 word at the specified address and the following word
8215 Unconditionally executed.
8216 Error if Rn is R15. */
8221 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8222 if (inst
.operands
[0].writeback
)
8223 inst
.instruction
|= WRITE_BACK
;
8226 /* ARM V6 ssat (argument parse). */
8231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8232 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8233 inst
.instruction
|= inst
.operands
[2].reg
;
8235 if (inst
.operands
[3].present
)
8236 encode_arm_shift (3);
8239 /* ARM V6 usat (argument parse). */
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8246 inst
.instruction
|= inst
.operands
[2].reg
;
8248 if (inst
.operands
[3].present
)
8249 encode_arm_shift (3);
8252 /* ARM V6 ssat16 (argument parse). */
8257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8258 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8259 inst
.instruction
|= inst
.operands
[2].reg
;
8265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8266 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8267 inst
.instruction
|= inst
.operands
[2].reg
;
8270 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8271 preserving the other bits.
8273 setend <endian_specifier>, where <endian_specifier> is either
8279 if (inst
.operands
[0].imm
)
8280 inst
.instruction
|= 0x200;
8286 unsigned int Rm
= (inst
.operands
[1].present
8287 ? inst
.operands
[1].reg
8288 : inst
.operands
[0].reg
);
8290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8291 inst
.instruction
|= Rm
;
8292 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8294 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8295 inst
.instruction
|= SHIFT_BY_REG
;
8298 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8304 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8305 inst
.reloc
.pc_rel
= 0;
8311 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8312 inst
.reloc
.pc_rel
= 0;
8318 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8319 inst
.reloc
.pc_rel
= 0;
8322 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8323 SMLAxy{cond} Rd,Rm,Rs,Rn
8324 SMLAWy{cond} Rd,Rm,Rs,Rn
8325 Error if any register is R15. */
8330 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8331 inst
.instruction
|= inst
.operands
[1].reg
;
8332 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8333 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8336 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8337 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8338 Error if any register is R15.
8339 Warning if Rdlo == Rdhi. */
8344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8345 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8346 inst
.instruction
|= inst
.operands
[2].reg
;
8347 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8349 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8350 as_tsktsk (_("rdhi and rdlo must be different"));
8353 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8354 SMULxy{cond} Rd,Rm,Rs
8355 Error if any register is R15. */
8360 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8361 inst
.instruction
|= inst
.operands
[1].reg
;
8362 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8365 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8366 the same for both ARM and Thumb-2. */
8373 if (inst
.operands
[0].present
)
8375 reg
= inst
.operands
[0].reg
;
8376 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8381 inst
.instruction
|= reg
<< 16;
8382 inst
.instruction
|= inst
.operands
[1].imm
;
8383 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8384 inst
.instruction
|= WRITE_BACK
;
8387 /* ARM V6 strex (argument parse). */
8392 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8393 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8394 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8395 || inst
.operands
[2].negative
8396 /* See comment in do_ldrex(). */
8397 || (inst
.operands
[2].reg
== REG_PC
),
8400 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8401 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8403 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8404 || inst
.reloc
.exp
.X_add_number
!= 0,
8405 _("offset must be zero in ARM encoding"));
8407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8408 inst
.instruction
|= inst
.operands
[1].reg
;
8409 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8410 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8416 constraint (inst
.operands
[1].reg
% 2 != 0,
8417 _("even register required"));
8418 constraint (inst
.operands
[2].present
8419 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8420 _("can only store two consecutive registers"));
8421 /* If op 2 were present and equal to PC, this function wouldn't
8422 have been called in the first place. */
8423 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8425 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8426 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8427 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8431 inst
.instruction
|= inst
.operands
[1].reg
;
8432 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8435 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8436 extends it to 32-bits, and adds the result to a value in another
8437 register. You can specify a rotation by 0, 8, 16, or 24 bits
8438 before extracting the 16-bit value.
8439 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8440 Condition defaults to COND_ALWAYS.
8441 Error if any register uses R15. */
8446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8447 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8448 inst
.instruction
|= inst
.operands
[2].reg
;
8449 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8454 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8455 Condition defaults to COND_ALWAYS.
8456 Error if any register uses R15. */
8461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[1].reg
;
8463 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8466 /* VFP instructions. In a logical order: SP variant first, monad
8467 before dyad, arithmetic then move then load/store. */
8470 do_vfp_sp_monadic (void)
8472 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8473 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8477 do_vfp_sp_dyadic (void)
8479 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8480 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8481 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8485 do_vfp_sp_compare_z (void)
8487 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8491 do_vfp_dp_sp_cvt (void)
8493 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8494 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8498 do_vfp_sp_dp_cvt (void)
8500 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8501 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8505 do_vfp_reg_from_sp (void)
8507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8508 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8512 do_vfp_reg2_from_sp2 (void)
8514 constraint (inst
.operands
[2].imm
!= 2,
8515 _("only two consecutive VFP SP registers allowed here"));
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8517 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8518 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8522 do_vfp_sp_from_reg (void)
8524 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8525 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8529 do_vfp_sp2_from_reg2 (void)
8531 constraint (inst
.operands
[0].imm
!= 2,
8532 _("only two consecutive VFP SP registers allowed here"));
8533 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8534 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8535 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8539 do_vfp_sp_ldst (void)
8541 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8542 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8546 do_vfp_dp_ldst (void)
8548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8549 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8554 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8556 if (inst
.operands
[0].writeback
)
8557 inst
.instruction
|= WRITE_BACK
;
8559 constraint (ldstm_type
!= VFP_LDSTMIA
,
8560 _("this addressing mode requires base-register writeback"));
8561 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8562 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8563 inst
.instruction
|= inst
.operands
[1].imm
;
8567 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8571 if (inst
.operands
[0].writeback
)
8572 inst
.instruction
|= WRITE_BACK
;
8574 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8575 _("this addressing mode requires base-register writeback"));
8577 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8580 count
= inst
.operands
[1].imm
<< 1;
8581 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8584 inst
.instruction
|= count
;
8588 do_vfp_sp_ldstmia (void)
8590 vfp_sp_ldstm (VFP_LDSTMIA
);
8594 do_vfp_sp_ldstmdb (void)
8596 vfp_sp_ldstm (VFP_LDSTMDB
);
8600 do_vfp_dp_ldstmia (void)
8602 vfp_dp_ldstm (VFP_LDSTMIA
);
8606 do_vfp_dp_ldstmdb (void)
8608 vfp_dp_ldstm (VFP_LDSTMDB
);
8612 do_vfp_xp_ldstmia (void)
8614 vfp_dp_ldstm (VFP_LDSTMIAX
);
8618 do_vfp_xp_ldstmdb (void)
8620 vfp_dp_ldstm (VFP_LDSTMDBX
);
8624 do_vfp_dp_rd_rm (void)
8626 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8627 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8631 do_vfp_dp_rn_rd (void)
8633 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8634 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8638 do_vfp_dp_rd_rn (void)
8640 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8641 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8645 do_vfp_dp_rd_rn_rm (void)
8647 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8648 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8649 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8659 do_vfp_dp_rm_rd_rn (void)
8661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8662 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8663 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8666 /* VFPv3 instructions. */
8668 do_vfp_sp_const (void)
8670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8671 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8672 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8676 do_vfp_dp_const (void)
8678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8679 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8680 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8684 vfp_conv (int srcsize
)
8686 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8687 inst
.instruction
|= (immbits
& 1) << 5;
8688 inst
.instruction
|= (immbits
>> 1);
8692 do_vfp_sp_conv_16 (void)
8694 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8699 do_vfp_dp_conv_16 (void)
8701 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8706 do_vfp_sp_conv_32 (void)
8708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8713 do_vfp_dp_conv_32 (void)
8715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8719 /* FPA instructions. Also in a logical order. */
8724 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8725 inst
.instruction
|= inst
.operands
[1].reg
;
8729 do_fpa_ldmstm (void)
8731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8732 switch (inst
.operands
[1].imm
)
8734 case 1: inst
.instruction
|= CP_T_X
; break;
8735 case 2: inst
.instruction
|= CP_T_Y
; break;
8736 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8741 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8743 /* The instruction specified "ea" or "fd", so we can only accept
8744 [Rn]{!}. The instruction does not really support stacking or
8745 unstacking, so we have to emulate these by setting appropriate
8746 bits and offsets. */
8747 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8748 || inst
.reloc
.exp
.X_add_number
!= 0,
8749 _("this instruction does not support indexing"));
8751 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8752 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8754 if (!(inst
.instruction
& INDEX_UP
))
8755 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8757 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8759 inst
.operands
[2].preind
= 0;
8760 inst
.operands
[2].postind
= 1;
8764 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8767 /* iWMMXt instructions: strictly in alphabetical order. */
8770 do_iwmmxt_tandorc (void)
8772 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8776 do_iwmmxt_textrc (void)
8778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8779 inst
.instruction
|= inst
.operands
[1].imm
;
8783 do_iwmmxt_textrm (void)
8785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8786 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8787 inst
.instruction
|= inst
.operands
[2].imm
;
8791 do_iwmmxt_tinsr (void)
8793 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8794 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8795 inst
.instruction
|= inst
.operands
[2].imm
;
8799 do_iwmmxt_tmia (void)
8801 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8802 inst
.instruction
|= inst
.operands
[1].reg
;
8803 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8807 do_iwmmxt_waligni (void)
8809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8811 inst
.instruction
|= inst
.operands
[2].reg
;
8812 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8816 do_iwmmxt_wmerge (void)
8818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8820 inst
.instruction
|= inst
.operands
[2].reg
;
8821 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8825 do_iwmmxt_wmov (void)
8827 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8829 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8830 inst
.instruction
|= inst
.operands
[1].reg
;
8834 do_iwmmxt_wldstbh (void)
8837 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8839 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8841 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8842 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8846 do_iwmmxt_wldstw (void)
8848 /* RIWR_RIWC clears .isreg for a control register. */
8849 if (!inst
.operands
[0].isreg
)
8851 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8852 inst
.instruction
|= 0xf0000000;
8855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8856 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8860 do_iwmmxt_wldstd (void)
8862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8863 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8864 && inst
.operands
[1].immisreg
)
8866 inst
.instruction
&= ~0x1a000ff;
8867 inst
.instruction
|= (0xf << 28);
8868 if (inst
.operands
[1].preind
)
8869 inst
.instruction
|= PRE_INDEX
;
8870 if (!inst
.operands
[1].negative
)
8871 inst
.instruction
|= INDEX_UP
;
8872 if (inst
.operands
[1].writeback
)
8873 inst
.instruction
|= WRITE_BACK
;
8874 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8875 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8876 inst
.instruction
|= inst
.operands
[1].imm
;
8879 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8883 do_iwmmxt_wshufh (void)
8885 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8886 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8887 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8888 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8892 do_iwmmxt_wzero (void)
8894 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8895 inst
.instruction
|= inst
.operands
[0].reg
;
8896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8901 do_iwmmxt_wrwrwr_or_imm5 (void)
8903 if (inst
.operands
[2].isreg
)
8906 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8907 _("immediate operand requires iWMMXt2"));
8909 if (inst
.operands
[2].imm
== 0)
8911 switch ((inst
.instruction
>> 20) & 0xf)
8917 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8918 inst
.operands
[2].imm
= 16;
8919 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8925 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8926 inst
.operands
[2].imm
= 32;
8927 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8934 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8936 wrn
= (inst
.instruction
>> 16) & 0xf;
8937 inst
.instruction
&= 0xff0fff0f;
8938 inst
.instruction
|= wrn
;
8939 /* Bail out here; the instruction is now assembled. */
8944 /* Map 32 -> 0, etc. */
8945 inst
.operands
[2].imm
&= 0x1f;
8946 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8950 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8951 operations first, then control, shift, and load/store. */
8953 /* Insns like "foo X,Y,Z". */
8956 do_mav_triple (void)
8958 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8959 inst
.instruction
|= inst
.operands
[1].reg
;
8960 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8963 /* Insns like "foo W,X,Y,Z".
8964 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8970 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8971 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8972 inst
.instruction
|= inst
.operands
[3].reg
;
8975 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8979 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8982 /* Maverick shift immediate instructions.
8983 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8984 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8989 int imm
= inst
.operands
[2].imm
;
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8994 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8995 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8996 Bit 4 should be 0. */
8997 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8999 inst
.instruction
|= imm
;
9002 /* XScale instructions. Also sorted arithmetic before move. */
9004 /* Xscale multiply-accumulate (argument parse)
9007 MIAxycc acc0,Rm,Rs. */
9012 inst
.instruction
|= inst
.operands
[1].reg
;
9013 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9016 /* Xscale move-accumulator-register (argument parse)
9018 MARcc acc0,RdLo,RdHi. */
9023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9027 /* Xscale move-register-accumulator (argument parse)
9029 MRAcc RdLo,RdHi,acc0. */
9034 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9039 /* Encoding functions relevant only to Thumb. */
9041 /* inst.operands[i] is a shifted-register operand; encode
9042 it into inst.instruction in the format used by Thumb32. */
9045 encode_thumb32_shifted_operand (int i
)
9047 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9048 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9050 constraint (inst
.operands
[i
].immisreg
,
9051 _("shift by register not allowed in thumb mode"));
9052 inst
.instruction
|= inst
.operands
[i
].reg
;
9053 if (shift
== SHIFT_RRX
)
9054 inst
.instruction
|= SHIFT_ROR
<< 4;
9057 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9058 _("expression too complex"));
9060 constraint (value
> 32
9061 || (value
== 32 && (shift
== SHIFT_LSL
9062 || shift
== SHIFT_ROR
)),
9063 _("shift expression is too large"));
9067 else if (value
== 32)
9070 inst
.instruction
|= shift
<< 4;
9071 inst
.instruction
|= (value
& 0x1c) << 10;
9072 inst
.instruction
|= (value
& 0x03) << 6;
9077 /* inst.operands[i] was set up by parse_address. Encode it into a
9078 Thumb32 format load or store instruction. Reject forms that cannot
9079 be used with such instructions. If is_t is true, reject forms that
9080 cannot be used with a T instruction; if is_d is true, reject forms
9081 that cannot be used with a D instruction. If it is a store insn,
9085 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9087 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9089 constraint (!inst
.operands
[i
].isreg
,
9090 _("Instruction does not support =N addresses"));
9092 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9093 if (inst
.operands
[i
].immisreg
)
9095 constraint (is_pc
, BAD_PC_ADDRESSING
);
9096 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9097 constraint (inst
.operands
[i
].negative
,
9098 _("Thumb does not support negative register indexing"));
9099 constraint (inst
.operands
[i
].postind
,
9100 _("Thumb does not support register post-indexing"));
9101 constraint (inst
.operands
[i
].writeback
,
9102 _("Thumb does not support register indexing with writeback"));
9103 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9104 _("Thumb supports only LSL in shifted register indexing"));
9106 inst
.instruction
|= inst
.operands
[i
].imm
;
9107 if (inst
.operands
[i
].shifted
)
9109 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9110 _("expression too complex"));
9111 constraint (inst
.reloc
.exp
.X_add_number
< 0
9112 || inst
.reloc
.exp
.X_add_number
> 3,
9113 _("shift out of range"));
9114 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9116 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9118 else if (inst
.operands
[i
].preind
)
9120 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9121 constraint (is_t
&& inst
.operands
[i
].writeback
,
9122 _("cannot use writeback with this instruction"));
9123 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9124 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9128 inst
.instruction
|= 0x01000000;
9129 if (inst
.operands
[i
].writeback
)
9130 inst
.instruction
|= 0x00200000;
9134 inst
.instruction
|= 0x00000c00;
9135 if (inst
.operands
[i
].writeback
)
9136 inst
.instruction
|= 0x00000100;
9138 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9140 else if (inst
.operands
[i
].postind
)
9142 gas_assert (inst
.operands
[i
].writeback
);
9143 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9144 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9147 inst
.instruction
|= 0x00200000;
9149 inst
.instruction
|= 0x00000900;
9150 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9152 else /* unindexed - only for coprocessor */
9153 inst
.error
= _("instruction does not accept unindexed addressing");
9156 /* Table of Thumb instructions which exist in both 16- and 32-bit
9157 encodings (the latter only in post-V6T2 cores). The index is the
9158 value used in the insns table below. When there is more than one
9159 possible 16-bit encoding for the instruction, this table always
9161 Also contains several pseudo-instructions used during relaxation. */
9162 #define T16_32_TAB \
9163 X(_adc, 4140, eb400000), \
9164 X(_adcs, 4140, eb500000), \
9165 X(_add, 1c00, eb000000), \
9166 X(_adds, 1c00, eb100000), \
9167 X(_addi, 0000, f1000000), \
9168 X(_addis, 0000, f1100000), \
9169 X(_add_pc,000f, f20f0000), \
9170 X(_add_sp,000d, f10d0000), \
9171 X(_adr, 000f, f20f0000), \
9172 X(_and, 4000, ea000000), \
9173 X(_ands, 4000, ea100000), \
9174 X(_asr, 1000, fa40f000), \
9175 X(_asrs, 1000, fa50f000), \
9176 X(_b, e000, f000b000), \
9177 X(_bcond, d000, f0008000), \
9178 X(_bic, 4380, ea200000), \
9179 X(_bics, 4380, ea300000), \
9180 X(_cmn, 42c0, eb100f00), \
9181 X(_cmp, 2800, ebb00f00), \
9182 X(_cpsie, b660, f3af8400), \
9183 X(_cpsid, b670, f3af8600), \
9184 X(_cpy, 4600, ea4f0000), \
9185 X(_dec_sp,80dd, f1ad0d00), \
9186 X(_eor, 4040, ea800000), \
9187 X(_eors, 4040, ea900000), \
9188 X(_inc_sp,00dd, f10d0d00), \
9189 X(_ldmia, c800, e8900000), \
9190 X(_ldr, 6800, f8500000), \
9191 X(_ldrb, 7800, f8100000), \
9192 X(_ldrh, 8800, f8300000), \
9193 X(_ldrsb, 5600, f9100000), \
9194 X(_ldrsh, 5e00, f9300000), \
9195 X(_ldr_pc,4800, f85f0000), \
9196 X(_ldr_pc2,4800, f85f0000), \
9197 X(_ldr_sp,9800, f85d0000), \
9198 X(_lsl, 0000, fa00f000), \
9199 X(_lsls, 0000, fa10f000), \
9200 X(_lsr, 0800, fa20f000), \
9201 X(_lsrs, 0800, fa30f000), \
9202 X(_mov, 2000, ea4f0000), \
9203 X(_movs, 2000, ea5f0000), \
9204 X(_mul, 4340, fb00f000), \
9205 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9206 X(_mvn, 43c0, ea6f0000), \
9207 X(_mvns, 43c0, ea7f0000), \
9208 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9209 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9210 X(_orr, 4300, ea400000), \
9211 X(_orrs, 4300, ea500000), \
9212 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9213 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9214 X(_rev, ba00, fa90f080), \
9215 X(_rev16, ba40, fa90f090), \
9216 X(_revsh, bac0, fa90f0b0), \
9217 X(_ror, 41c0, fa60f000), \
9218 X(_rors, 41c0, fa70f000), \
9219 X(_sbc, 4180, eb600000), \
9220 X(_sbcs, 4180, eb700000), \
9221 X(_stmia, c000, e8800000), \
9222 X(_str, 6000, f8400000), \
9223 X(_strb, 7000, f8000000), \
9224 X(_strh, 8000, f8200000), \
9225 X(_str_sp,9000, f84d0000), \
9226 X(_sub, 1e00, eba00000), \
9227 X(_subs, 1e00, ebb00000), \
9228 X(_subi, 8000, f1a00000), \
9229 X(_subis, 8000, f1b00000), \
9230 X(_sxtb, b240, fa4ff080), \
9231 X(_sxth, b200, fa0ff080), \
9232 X(_tst, 4200, ea100f00), \
9233 X(_uxtb, b2c0, fa5ff080), \
9234 X(_uxth, b280, fa1ff080), \
9235 X(_nop, bf00, f3af8000), \
9236 X(_yield, bf10, f3af8001), \
9237 X(_wfe, bf20, f3af8002), \
9238 X(_wfi, bf30, f3af8003), \
9239 X(_sev, bf40, f3af8004),
9241 /* To catch errors in encoding functions, the codes are all offset by
9242 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9243 as 16-bit instructions. */
9244 #define X(a,b,c) T_MNEM##a
9245 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9248 #define X(a,b,c) 0x##b
9249 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9250 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9253 #define X(a,b,c) 0x##c
9254 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9255 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9256 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9260 /* Thumb instruction encoders, in alphabetical order. */
9265 do_t_add_sub_w (void)
9269 Rd
= inst
.operands
[0].reg
;
9270 Rn
= inst
.operands
[1].reg
;
9272 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9273 is the SP-{plus,minus}-immediate form of the instruction. */
9275 constraint (Rd
== REG_PC
, BAD_PC
);
9277 reject_bad_reg (Rd
);
9279 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9283 /* Parse an add or subtract instruction. We get here with inst.instruction
9284 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9291 Rd
= inst
.operands
[0].reg
;
9292 Rs
= (inst
.operands
[1].present
9293 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9294 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9297 set_it_insn_type_last ();
9305 flags
= (inst
.instruction
== T_MNEM_adds
9306 || inst
.instruction
== T_MNEM_subs
);
9308 narrow
= !in_it_block ();
9310 narrow
= in_it_block ();
9311 if (!inst
.operands
[2].isreg
)
9315 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9317 add
= (inst
.instruction
== T_MNEM_add
9318 || inst
.instruction
== T_MNEM_adds
);
9320 if (inst
.size_req
!= 4)
9322 /* Attempt to use a narrow opcode, with relaxation if
9324 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9325 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9326 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9327 opcode
= T_MNEM_add_sp
;
9328 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9329 opcode
= T_MNEM_add_pc
;
9330 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9333 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9335 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9339 inst
.instruction
= THUMB_OP16(opcode
);
9340 inst
.instruction
|= (Rd
<< 4) | Rs
;
9341 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9342 if (inst
.size_req
!= 2)
9343 inst
.relax
= opcode
;
9346 constraint (inst
.size_req
== 2, BAD_HIREG
);
9348 if (inst
.size_req
== 4
9349 || (inst
.size_req
!= 2 && !opcode
))
9353 constraint (add
, BAD_PC
);
9354 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9355 _("only SUBS PC, LR, #const allowed"));
9356 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9357 _("expression too complex"));
9358 constraint (inst
.reloc
.exp
.X_add_number
< 0
9359 || inst
.reloc
.exp
.X_add_number
> 0xff,
9360 _("immediate value out of range"));
9361 inst
.instruction
= T2_SUBS_PC_LR
9362 | inst
.reloc
.exp
.X_add_number
;
9363 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9366 else if (Rs
== REG_PC
)
9368 /* Always use addw/subw. */
9369 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9370 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9374 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9375 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9378 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9382 inst
.instruction
|= Rd
<< 8;
9383 inst
.instruction
|= Rs
<< 16;
9388 Rn
= inst
.operands
[2].reg
;
9389 /* See if we can do this with a 16-bit instruction. */
9390 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9392 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9397 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9398 || inst
.instruction
== T_MNEM_add
)
9401 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9405 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9407 /* Thumb-1 cores (except v6-M) require at least one high
9408 register in a narrow non flag setting add. */
9409 if (Rd
> 7 || Rn
> 7
9410 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9411 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9418 inst
.instruction
= T_OPCODE_ADD_HI
;
9419 inst
.instruction
|= (Rd
& 8) << 4;
9420 inst
.instruction
|= (Rd
& 7);
9421 inst
.instruction
|= Rn
<< 3;
9427 constraint (Rd
== REG_PC
, BAD_PC
);
9428 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9429 constraint (Rs
== REG_PC
, BAD_PC
);
9430 reject_bad_reg (Rn
);
9432 /* If we get here, it can't be done in 16 bits. */
9433 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9434 _("shift must be constant"));
9435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9436 inst
.instruction
|= Rd
<< 8;
9437 inst
.instruction
|= Rs
<< 16;
9438 encode_thumb32_shifted_operand (2);
9443 constraint (inst
.instruction
== T_MNEM_adds
9444 || inst
.instruction
== T_MNEM_subs
,
9447 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9449 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9450 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9453 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9455 inst
.instruction
|= (Rd
<< 4) | Rs
;
9456 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9460 Rn
= inst
.operands
[2].reg
;
9461 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9463 /* We now have Rd, Rs, and Rn set to registers. */
9464 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9466 /* Can't do this for SUB. */
9467 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9468 inst
.instruction
= T_OPCODE_ADD_HI
;
9469 inst
.instruction
|= (Rd
& 8) << 4;
9470 inst
.instruction
|= (Rd
& 7);
9472 inst
.instruction
|= Rn
<< 3;
9474 inst
.instruction
|= Rs
<< 3;
9476 constraint (1, _("dest must overlap one source register"));
9480 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9481 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9482 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9492 Rd
= inst
.operands
[0].reg
;
9493 reject_bad_reg (Rd
);
9495 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9497 /* Defer to section relaxation. */
9498 inst
.relax
= inst
.instruction
;
9499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9500 inst
.instruction
|= Rd
<< 4;
9502 else if (unified_syntax
&& inst
.size_req
!= 2)
9504 /* Generate a 32-bit opcode. */
9505 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9506 inst
.instruction
|= Rd
<< 8;
9507 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9508 inst
.reloc
.pc_rel
= 1;
9512 /* Generate a 16-bit opcode. */
9513 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9514 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9515 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9516 inst
.reloc
.pc_rel
= 1;
9518 inst
.instruction
|= Rd
<< 4;
9522 /* Arithmetic instructions for which there is just one 16-bit
9523 instruction encoding, and it allows only two low registers.
9524 For maximal compatibility with ARM syntax, we allow three register
9525 operands even when Thumb-32 instructions are not available, as long
9526 as the first two are identical. For instance, both "sbc r0,r1" and
9527 "sbc r0,r0,r1" are allowed. */
9533 Rd
= inst
.operands
[0].reg
;
9534 Rs
= (inst
.operands
[1].present
9535 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9536 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9537 Rn
= inst
.operands
[2].reg
;
9539 reject_bad_reg (Rd
);
9540 reject_bad_reg (Rs
);
9541 if (inst
.operands
[2].isreg
)
9542 reject_bad_reg (Rn
);
9546 if (!inst
.operands
[2].isreg
)
9548 /* For an immediate, we always generate a 32-bit opcode;
9549 section relaxation will shrink it later if possible. */
9550 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9551 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9552 inst
.instruction
|= Rd
<< 8;
9553 inst
.instruction
|= Rs
<< 16;
9554 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9560 /* See if we can do this with a 16-bit instruction. */
9561 if (THUMB_SETS_FLAGS (inst
.instruction
))
9562 narrow
= !in_it_block ();
9564 narrow
= in_it_block ();
9566 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9568 if (inst
.operands
[2].shifted
)
9570 if (inst
.size_req
== 4)
9576 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9577 inst
.instruction
|= Rd
;
9578 inst
.instruction
|= Rn
<< 3;
9582 /* If we get here, it can't be done in 16 bits. */
9583 constraint (inst
.operands
[2].shifted
9584 && inst
.operands
[2].immisreg
,
9585 _("shift must be constant"));
9586 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9587 inst
.instruction
|= Rd
<< 8;
9588 inst
.instruction
|= Rs
<< 16;
9589 encode_thumb32_shifted_operand (2);
9594 /* On its face this is a lie - the instruction does set the
9595 flags. However, the only supported mnemonic in this mode
9597 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9599 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9600 _("unshifted register required"));
9601 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9602 constraint (Rd
!= Rs
,
9603 _("dest and source1 must be the same register"));
9605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9606 inst
.instruction
|= Rd
;
9607 inst
.instruction
|= Rn
<< 3;
9611 /* Similarly, but for instructions where the arithmetic operation is
9612 commutative, so we can allow either of them to be different from
9613 the destination operand in a 16-bit instruction. For instance, all
9614 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9621 Rd
= inst
.operands
[0].reg
;
9622 Rs
= (inst
.operands
[1].present
9623 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9624 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9625 Rn
= inst
.operands
[2].reg
;
9627 reject_bad_reg (Rd
);
9628 reject_bad_reg (Rs
);
9629 if (inst
.operands
[2].isreg
)
9630 reject_bad_reg (Rn
);
9634 if (!inst
.operands
[2].isreg
)
9636 /* For an immediate, we always generate a 32-bit opcode;
9637 section relaxation will shrink it later if possible. */
9638 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9639 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9640 inst
.instruction
|= Rd
<< 8;
9641 inst
.instruction
|= Rs
<< 16;
9642 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9648 /* See if we can do this with a 16-bit instruction. */
9649 if (THUMB_SETS_FLAGS (inst
.instruction
))
9650 narrow
= !in_it_block ();
9652 narrow
= in_it_block ();
9654 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9656 if (inst
.operands
[2].shifted
)
9658 if (inst
.size_req
== 4)
9665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9666 inst
.instruction
|= Rd
;
9667 inst
.instruction
|= Rn
<< 3;
9672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9673 inst
.instruction
|= Rd
;
9674 inst
.instruction
|= Rs
<< 3;
9679 /* If we get here, it can't be done in 16 bits. */
9680 constraint (inst
.operands
[2].shifted
9681 && inst
.operands
[2].immisreg
,
9682 _("shift must be constant"));
9683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9684 inst
.instruction
|= Rd
<< 8;
9685 inst
.instruction
|= Rs
<< 16;
9686 encode_thumb32_shifted_operand (2);
9691 /* On its face this is a lie - the instruction does set the
9692 flags. However, the only supported mnemonic in this mode
9694 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9696 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9697 _("unshifted register required"));
9698 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9701 inst
.instruction
|= Rd
;
9704 inst
.instruction
|= Rn
<< 3;
9706 inst
.instruction
|= Rs
<< 3;
9708 constraint (1, _("dest must overlap one source register"));
9715 if (inst
.operands
[0].present
)
9717 constraint ((inst
.instruction
& 0xf0) != 0x40
9718 && inst
.operands
[0].imm
> 0xf
9719 && inst
.operands
[0].imm
< 0x0,
9720 _("bad barrier type"));
9721 inst
.instruction
|= inst
.operands
[0].imm
;
9724 inst
.instruction
|= 0xf;
9731 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9732 constraint (msb
> 32, _("bit-field extends past end of register"));
9733 /* The instruction encoding stores the LSB and MSB,
9734 not the LSB and width. */
9735 Rd
= inst
.operands
[0].reg
;
9736 reject_bad_reg (Rd
);
9737 inst
.instruction
|= Rd
<< 8;
9738 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9739 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9740 inst
.instruction
|= msb
- 1;
9749 Rd
= inst
.operands
[0].reg
;
9750 reject_bad_reg (Rd
);
9752 /* #0 in second position is alternative syntax for bfc, which is
9753 the same instruction but with REG_PC in the Rm field. */
9754 if (!inst
.operands
[1].isreg
)
9758 Rn
= inst
.operands
[1].reg
;
9759 reject_bad_reg (Rn
);
9762 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9763 constraint (msb
> 32, _("bit-field extends past end of register"));
9764 /* The instruction encoding stores the LSB and MSB,
9765 not the LSB and width. */
9766 inst
.instruction
|= Rd
<< 8;
9767 inst
.instruction
|= Rn
<< 16;
9768 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9769 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9770 inst
.instruction
|= msb
- 1;
9778 Rd
= inst
.operands
[0].reg
;
9779 Rn
= inst
.operands
[1].reg
;
9781 reject_bad_reg (Rd
);
9782 reject_bad_reg (Rn
);
9784 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9785 _("bit-field extends past end of register"));
9786 inst
.instruction
|= Rd
<< 8;
9787 inst
.instruction
|= Rn
<< 16;
9788 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9789 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9790 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9793 /* ARM V5 Thumb BLX (argument parse)
9794 BLX <target_addr> which is BLX(1)
9795 BLX <Rm> which is BLX(2)
9796 Unfortunately, there are two different opcodes for this mnemonic.
9797 So, the insns[].value is not used, and the code here zaps values
9798 into inst.instruction.
9800 ??? How to take advantage of the additional two bits of displacement
9801 available in Thumb32 mode? Need new relocation? */
9806 set_it_insn_type_last ();
9808 if (inst
.operands
[0].isreg
)
9810 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9811 /* We have a register, so this is BLX(2). */
9812 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9816 /* No register. This must be BLX(1). */
9817 inst
.instruction
= 0xf000e800;
9818 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9830 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9834 /* Conditional branches inside IT blocks are encoded as unconditional
9841 if (cond
!= COND_ALWAYS
)
9842 opcode
= T_MNEM_bcond
;
9844 opcode
= inst
.instruction
;
9847 && (inst
.size_req
== 4
9848 || (inst
.size_req
!= 2 && inst
.operands
[0].hasreloc
)))
9850 inst
.instruction
= THUMB_OP32(opcode
);
9851 if (cond
== COND_ALWAYS
)
9852 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9855 gas_assert (cond
!= 0xF);
9856 inst
.instruction
|= cond
<< 22;
9857 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9862 inst
.instruction
= THUMB_OP16(opcode
);
9863 if (cond
== COND_ALWAYS
)
9864 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9867 inst
.instruction
|= cond
<< 8;
9868 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9870 /* Allow section relaxation. */
9871 if (unified_syntax
&& inst
.size_req
!= 2)
9872 inst
.relax
= opcode
;
9874 inst
.reloc
.type
= reloc
;
9875 inst
.reloc
.pc_rel
= 1;
9881 constraint (inst
.cond
!= COND_ALWAYS
,
9882 _("instruction is always unconditional"));
9883 if (inst
.operands
[0].present
)
9885 constraint (inst
.operands
[0].imm
> 255,
9886 _("immediate value out of range"));
9887 inst
.instruction
|= inst
.operands
[0].imm
;
9888 set_it_insn_type (NEUTRAL_IT_INSN
);
9893 do_t_branch23 (void)
9895 set_it_insn_type_last ();
9896 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9898 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9899 this file. We used to simply ignore the PLT reloc type here --
9900 the branch encoding is now needed to deal with TLSCALL relocs.
9901 So if we see a PLT reloc now, put it back to how it used to be to
9902 keep the preexisting behaviour. */
9903 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9904 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9906 #if defined(OBJ_COFF)
9907 /* If the destination of the branch is a defined symbol which does not have
9908 the THUMB_FUNC attribute, then we must be calling a function which has
9909 the (interfacearm) attribute. We look for the Thumb entry point to that
9910 function and change the branch to refer to that function instead. */
9911 if ( inst
.reloc
.exp
.X_op
== O_symbol
9912 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9913 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9914 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9915 inst
.reloc
.exp
.X_add_symbol
=
9916 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9923 set_it_insn_type_last ();
9924 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9925 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9926 should cause the alignment to be checked once it is known. This is
9927 because BX PC only works if the instruction is word aligned. */
9935 set_it_insn_type_last ();
9936 Rm
= inst
.operands
[0].reg
;
9937 reject_bad_reg (Rm
);
9938 inst
.instruction
|= Rm
<< 16;
9947 Rd
= inst
.operands
[0].reg
;
9948 Rm
= inst
.operands
[1].reg
;
9950 reject_bad_reg (Rd
);
9951 reject_bad_reg (Rm
);
9953 inst
.instruction
|= Rd
<< 8;
9954 inst
.instruction
|= Rm
<< 16;
9955 inst
.instruction
|= Rm
;
9961 set_it_insn_type (OUTSIDE_IT_INSN
);
9962 inst
.instruction
|= inst
.operands
[0].imm
;
9968 set_it_insn_type (OUTSIDE_IT_INSN
);
9970 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9971 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9973 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9974 inst
.instruction
= 0xf3af8000;
9975 inst
.instruction
|= imod
<< 9;
9976 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9977 if (inst
.operands
[1].present
)
9978 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9982 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9983 && (inst
.operands
[0].imm
& 4),
9984 _("selected processor does not support 'A' form "
9985 "of this instruction"));
9986 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9987 _("Thumb does not support the 2-argument "
9988 "form of this instruction"));
9989 inst
.instruction
|= inst
.operands
[0].imm
;
9993 /* THUMB CPY instruction (argument parse). */
9998 if (inst
.size_req
== 4)
10000 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10002 inst
.instruction
|= inst
.operands
[1].reg
;
10006 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10007 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10008 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10015 set_it_insn_type (OUTSIDE_IT_INSN
);
10016 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10017 inst
.instruction
|= inst
.operands
[0].reg
;
10018 inst
.reloc
.pc_rel
= 1;
10019 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10025 inst
.instruction
|= inst
.operands
[0].imm
;
10031 unsigned Rd
, Rn
, Rm
;
10033 Rd
= inst
.operands
[0].reg
;
10034 Rn
= (inst
.operands
[1].present
10035 ? inst
.operands
[1].reg
: Rd
);
10036 Rm
= inst
.operands
[2].reg
;
10038 reject_bad_reg (Rd
);
10039 reject_bad_reg (Rn
);
10040 reject_bad_reg (Rm
);
10042 inst
.instruction
|= Rd
<< 8;
10043 inst
.instruction
|= Rn
<< 16;
10044 inst
.instruction
|= Rm
;
10050 if (unified_syntax
&& inst
.size_req
== 4)
10051 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10053 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10059 unsigned int cond
= inst
.operands
[0].imm
;
10061 set_it_insn_type (IT_INSN
);
10062 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10065 /* If the condition is a negative condition, invert the mask. */
10066 if ((cond
& 0x1) == 0x0)
10068 unsigned int mask
= inst
.instruction
& 0x000f;
10070 if ((mask
& 0x7) == 0)
10071 /* no conversion needed */;
10072 else if ((mask
& 0x3) == 0)
10074 else if ((mask
& 0x1) == 0)
10079 inst
.instruction
&= 0xfff0;
10080 inst
.instruction
|= mask
;
10083 inst
.instruction
|= cond
<< 4;
10086 /* Helper function used for both push/pop and ldm/stm. */
10088 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10092 load
= (inst
.instruction
& (1 << 20)) != 0;
10094 if (mask
& (1 << 13))
10095 inst
.error
= _("SP not allowed in register list");
10097 if ((mask
& (1 << base
)) != 0
10099 inst
.error
= _("having the base register in the register list when "
10100 "using write back is UNPREDICTABLE");
10104 if (mask
& (1 << 15))
10106 if (mask
& (1 << 14))
10107 inst
.error
= _("LR and PC should not both be in register list");
10109 set_it_insn_type_last ();
10114 if (mask
& (1 << 15))
10115 inst
.error
= _("PC not allowed in register list");
10118 if ((mask
& (mask
- 1)) == 0)
10120 /* Single register transfers implemented as str/ldr. */
10123 if (inst
.instruction
& (1 << 23))
10124 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10126 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10130 if (inst
.instruction
& (1 << 23))
10131 inst
.instruction
= 0x00800000; /* ia -> [base] */
10133 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10136 inst
.instruction
|= 0xf8400000;
10138 inst
.instruction
|= 0x00100000;
10140 mask
= ffs (mask
) - 1;
10143 else if (writeback
)
10144 inst
.instruction
|= WRITE_BACK
;
10146 inst
.instruction
|= mask
;
10147 inst
.instruction
|= base
<< 16;
10153 /* This really doesn't seem worth it. */
10154 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10155 _("expression too complex"));
10156 constraint (inst
.operands
[1].writeback
,
10157 _("Thumb load/store multiple does not support {reglist}^"));
10159 if (unified_syntax
)
10161 bfd_boolean narrow
;
10165 /* See if we can use a 16-bit instruction. */
10166 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10167 && inst
.size_req
!= 4
10168 && !(inst
.operands
[1].imm
& ~0xff))
10170 mask
= 1 << inst
.operands
[0].reg
;
10172 if (inst
.operands
[0].reg
<= 7)
10174 if (inst
.instruction
== T_MNEM_stmia
10175 ? inst
.operands
[0].writeback
10176 : (inst
.operands
[0].writeback
10177 == !(inst
.operands
[1].imm
& mask
)))
10179 if (inst
.instruction
== T_MNEM_stmia
10180 && (inst
.operands
[1].imm
& mask
)
10181 && (inst
.operands
[1].imm
& (mask
- 1)))
10182 as_warn (_("value stored for r%d is UNKNOWN"),
10183 inst
.operands
[0].reg
);
10185 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10186 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10187 inst
.instruction
|= inst
.operands
[1].imm
;
10190 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10192 /* This means 1 register in reg list one of 3 situations:
10193 1. Instruction is stmia, but without writeback.
10194 2. lmdia without writeback, but with Rn not in
10196 3. ldmia with writeback, but with Rn in reglist.
10197 Case 3 is UNPREDICTABLE behaviour, so we handle
10198 case 1 and 2 which can be converted into a 16-bit
10199 str or ldr. The SP cases are handled below. */
10200 unsigned long opcode
;
10201 /* First, record an error for Case 3. */
10202 if (inst
.operands
[1].imm
& mask
10203 && inst
.operands
[0].writeback
)
10205 _("having the base register in the register list when "
10206 "using write back is UNPREDICTABLE");
10208 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10210 inst
.instruction
= THUMB_OP16 (opcode
);
10211 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10212 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10216 else if (inst
.operands
[0] .reg
== REG_SP
)
10218 if (inst
.operands
[0].writeback
)
10221 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10222 ? T_MNEM_push
: T_MNEM_pop
);
10223 inst
.instruction
|= inst
.operands
[1].imm
;
10226 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10229 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10230 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10231 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10239 if (inst
.instruction
< 0xffff)
10240 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10242 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10243 inst
.operands
[0].writeback
);
10248 constraint (inst
.operands
[0].reg
> 7
10249 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10250 constraint (inst
.instruction
!= T_MNEM_ldmia
10251 && inst
.instruction
!= T_MNEM_stmia
,
10252 _("Thumb-2 instruction only valid in unified syntax"));
10253 if (inst
.instruction
== T_MNEM_stmia
)
10255 if (!inst
.operands
[0].writeback
)
10256 as_warn (_("this instruction will write back the base register"));
10257 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10258 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10259 as_warn (_("value stored for r%d is UNKNOWN"),
10260 inst
.operands
[0].reg
);
10264 if (!inst
.operands
[0].writeback
10265 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10266 as_warn (_("this instruction will write back the base register"));
10267 else if (inst
.operands
[0].writeback
10268 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10269 as_warn (_("this instruction will not write back the base register"));
10272 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10273 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10274 inst
.instruction
|= inst
.operands
[1].imm
;
10281 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10282 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10283 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10284 || inst
.operands
[1].negative
,
10287 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10291 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10297 if (!inst
.operands
[1].present
)
10299 constraint (inst
.operands
[0].reg
== REG_LR
,
10300 _("r14 not allowed as first register "
10301 "when second register is omitted"));
10302 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10304 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10308 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10309 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10315 unsigned long opcode
;
10318 if (inst
.operands
[0].isreg
10319 && !inst
.operands
[0].preind
10320 && inst
.operands
[0].reg
== REG_PC
)
10321 set_it_insn_type_last ();
10323 opcode
= inst
.instruction
;
10324 if (unified_syntax
)
10326 if (!inst
.operands
[1].isreg
)
10328 if (opcode
<= 0xffff)
10329 inst
.instruction
= THUMB_OP32 (opcode
);
10330 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10333 if (inst
.operands
[1].isreg
10334 && !inst
.operands
[1].writeback
10335 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10336 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10337 && opcode
<= 0xffff
10338 && inst
.size_req
!= 4)
10340 /* Insn may have a 16-bit form. */
10341 Rn
= inst
.operands
[1].reg
;
10342 if (inst
.operands
[1].immisreg
)
10344 inst
.instruction
= THUMB_OP16 (opcode
);
10346 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10348 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10349 reject_bad_reg (inst
.operands
[1].imm
);
10351 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10352 && opcode
!= T_MNEM_ldrsb
)
10353 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10354 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10361 if (inst
.reloc
.pc_rel
)
10362 opcode
= T_MNEM_ldr_pc2
;
10364 opcode
= T_MNEM_ldr_pc
;
10368 if (opcode
== T_MNEM_ldr
)
10369 opcode
= T_MNEM_ldr_sp
;
10371 opcode
= T_MNEM_str_sp
;
10373 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10377 inst
.instruction
= inst
.operands
[0].reg
;
10378 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10380 inst
.instruction
|= THUMB_OP16 (opcode
);
10381 if (inst
.size_req
== 2)
10382 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10384 inst
.relax
= opcode
;
10388 /* Definitely a 32-bit variant. */
10390 /* Warning for Erratum 752419. */
10391 if (opcode
== T_MNEM_ldr
10392 && inst
.operands
[0].reg
== REG_SP
10393 && inst
.operands
[1].writeback
== 1
10394 && !inst
.operands
[1].immisreg
)
10396 if (no_cpu_selected ()
10397 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10398 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10399 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10400 as_warn (_("This instruction may be unpredictable "
10401 "if executed on M-profile cores "
10402 "with interrupts enabled."));
10405 /* Do some validations regarding addressing modes. */
10406 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10407 && opcode
!= T_MNEM_str
)
10408 reject_bad_reg (inst
.operands
[1].imm
);
10410 inst
.instruction
= THUMB_OP32 (opcode
);
10411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10412 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10416 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10418 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10420 /* Only [Rn,Rm] is acceptable. */
10421 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10422 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10423 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10424 || inst
.operands
[1].negative
,
10425 _("Thumb does not support this addressing mode"));
10426 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10430 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10431 if (!inst
.operands
[1].isreg
)
10432 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10435 constraint (!inst
.operands
[1].preind
10436 || inst
.operands
[1].shifted
10437 || inst
.operands
[1].writeback
,
10438 _("Thumb does not support this addressing mode"));
10439 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10441 constraint (inst
.instruction
& 0x0600,
10442 _("byte or halfword not valid for base register"));
10443 constraint (inst
.operands
[1].reg
== REG_PC
10444 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10445 _("r15 based store not allowed"));
10446 constraint (inst
.operands
[1].immisreg
,
10447 _("invalid base register for register offset"));
10449 if (inst
.operands
[1].reg
== REG_PC
)
10450 inst
.instruction
= T_OPCODE_LDR_PC
;
10451 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10452 inst
.instruction
= T_OPCODE_LDR_SP
;
10454 inst
.instruction
= T_OPCODE_STR_SP
;
10456 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10457 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10461 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10462 if (!inst
.operands
[1].immisreg
)
10464 /* Immediate offset. */
10465 inst
.instruction
|= inst
.operands
[0].reg
;
10466 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10467 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10471 /* Register offset. */
10472 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10473 constraint (inst
.operands
[1].negative
,
10474 _("Thumb does not support this addressing mode"));
10477 switch (inst
.instruction
)
10479 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10480 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10481 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10482 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10483 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10484 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10485 case 0x5600 /* ldrsb */:
10486 case 0x5e00 /* ldrsh */: break;
10490 inst
.instruction
|= inst
.operands
[0].reg
;
10491 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10492 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10498 if (!inst
.operands
[1].present
)
10500 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10501 constraint (inst
.operands
[0].reg
== REG_LR
,
10502 _("r14 not allowed here"));
10504 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10505 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10506 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10513 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10519 unsigned Rd
, Rn
, Rm
, Ra
;
10521 Rd
= inst
.operands
[0].reg
;
10522 Rn
= inst
.operands
[1].reg
;
10523 Rm
= inst
.operands
[2].reg
;
10524 Ra
= inst
.operands
[3].reg
;
10526 reject_bad_reg (Rd
);
10527 reject_bad_reg (Rn
);
10528 reject_bad_reg (Rm
);
10529 reject_bad_reg (Ra
);
10531 inst
.instruction
|= Rd
<< 8;
10532 inst
.instruction
|= Rn
<< 16;
10533 inst
.instruction
|= Rm
;
10534 inst
.instruction
|= Ra
<< 12;
10540 unsigned RdLo
, RdHi
, Rn
, Rm
;
10542 RdLo
= inst
.operands
[0].reg
;
10543 RdHi
= inst
.operands
[1].reg
;
10544 Rn
= inst
.operands
[2].reg
;
10545 Rm
= inst
.operands
[3].reg
;
10547 reject_bad_reg (RdLo
);
10548 reject_bad_reg (RdHi
);
10549 reject_bad_reg (Rn
);
10550 reject_bad_reg (Rm
);
10552 inst
.instruction
|= RdLo
<< 12;
10553 inst
.instruction
|= RdHi
<< 8;
10554 inst
.instruction
|= Rn
<< 16;
10555 inst
.instruction
|= Rm
;
10559 do_t_mov_cmp (void)
10563 Rn
= inst
.operands
[0].reg
;
10564 Rm
= inst
.operands
[1].reg
;
10567 set_it_insn_type_last ();
10569 if (unified_syntax
)
10571 int r0off
= (inst
.instruction
== T_MNEM_mov
10572 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10573 unsigned long opcode
;
10574 bfd_boolean narrow
;
10575 bfd_boolean low_regs
;
10577 low_regs
= (Rn
<= 7 && Rm
<= 7);
10578 opcode
= inst
.instruction
;
10579 if (in_it_block ())
10580 narrow
= opcode
!= T_MNEM_movs
;
10582 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10583 if (inst
.size_req
== 4
10584 || inst
.operands
[1].shifted
)
10587 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10588 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10589 && !inst
.operands
[1].shifted
10593 inst
.instruction
= T2_SUBS_PC_LR
;
10597 if (opcode
== T_MNEM_cmp
)
10599 constraint (Rn
== REG_PC
, BAD_PC
);
10602 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10604 warn_deprecated_sp (Rm
);
10605 /* R15 was documented as a valid choice for Rm in ARMv6,
10606 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10607 tools reject R15, so we do too. */
10608 constraint (Rm
== REG_PC
, BAD_PC
);
10611 reject_bad_reg (Rm
);
10613 else if (opcode
== T_MNEM_mov
10614 || opcode
== T_MNEM_movs
)
10616 if (inst
.operands
[1].isreg
)
10618 if (opcode
== T_MNEM_movs
)
10620 reject_bad_reg (Rn
);
10621 reject_bad_reg (Rm
);
10625 /* This is mov.n. */
10626 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10627 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10629 as_warn (_("Use of r%u as a source register is "
10630 "deprecated when r%u is the destination "
10631 "register."), Rm
, Rn
);
10636 /* This is mov.w. */
10637 constraint (Rn
== REG_PC
, BAD_PC
);
10638 constraint (Rm
== REG_PC
, BAD_PC
);
10639 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10643 reject_bad_reg (Rn
);
10646 if (!inst
.operands
[1].isreg
)
10648 /* Immediate operand. */
10649 if (!in_it_block () && opcode
== T_MNEM_mov
)
10651 if (low_regs
&& narrow
)
10653 inst
.instruction
= THUMB_OP16 (opcode
);
10654 inst
.instruction
|= Rn
<< 8;
10655 if (inst
.size_req
== 2)
10656 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10658 inst
.relax
= opcode
;
10662 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10663 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10664 inst
.instruction
|= Rn
<< r0off
;
10665 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10668 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10669 && (inst
.instruction
== T_MNEM_mov
10670 || inst
.instruction
== T_MNEM_movs
))
10672 /* Register shifts are encoded as separate shift instructions. */
10673 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10675 if (in_it_block ())
10680 if (inst
.size_req
== 4)
10683 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10689 switch (inst
.operands
[1].shift_kind
)
10692 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10695 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10698 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10701 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10707 inst
.instruction
= opcode
;
10710 inst
.instruction
|= Rn
;
10711 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10716 inst
.instruction
|= CONDS_BIT
;
10718 inst
.instruction
|= Rn
<< 8;
10719 inst
.instruction
|= Rm
<< 16;
10720 inst
.instruction
|= inst
.operands
[1].imm
;
10725 /* Some mov with immediate shift have narrow variants.
10726 Register shifts are handled above. */
10727 if (low_regs
&& inst
.operands
[1].shifted
10728 && (inst
.instruction
== T_MNEM_mov
10729 || inst
.instruction
== T_MNEM_movs
))
10731 if (in_it_block ())
10732 narrow
= (inst
.instruction
== T_MNEM_mov
);
10734 narrow
= (inst
.instruction
== T_MNEM_movs
);
10739 switch (inst
.operands
[1].shift_kind
)
10741 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10742 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10743 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10744 default: narrow
= FALSE
; break;
10750 inst
.instruction
|= Rn
;
10751 inst
.instruction
|= Rm
<< 3;
10752 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10756 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10757 inst
.instruction
|= Rn
<< r0off
;
10758 encode_thumb32_shifted_operand (1);
10762 switch (inst
.instruction
)
10765 inst
.instruction
= T_OPCODE_MOV_HR
;
10766 inst
.instruction
|= (Rn
& 0x8) << 4;
10767 inst
.instruction
|= (Rn
& 0x7);
10768 inst
.instruction
|= Rm
<< 3;
10772 /* We know we have low registers at this point.
10773 Generate LSLS Rd, Rs, #0. */
10774 inst
.instruction
= T_OPCODE_LSL_I
;
10775 inst
.instruction
|= Rn
;
10776 inst
.instruction
|= Rm
<< 3;
10782 inst
.instruction
= T_OPCODE_CMP_LR
;
10783 inst
.instruction
|= Rn
;
10784 inst
.instruction
|= Rm
<< 3;
10788 inst
.instruction
= T_OPCODE_CMP_HR
;
10789 inst
.instruction
|= (Rn
& 0x8) << 4;
10790 inst
.instruction
|= (Rn
& 0x7);
10791 inst
.instruction
|= Rm
<< 3;
10798 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10800 /* PR 10443: Do not silently ignore shifted operands. */
10801 constraint (inst
.operands
[1].shifted
,
10802 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10804 if (inst
.operands
[1].isreg
)
10806 if (Rn
< 8 && Rm
< 8)
10808 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10809 since a MOV instruction produces unpredictable results. */
10810 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10811 inst
.instruction
= T_OPCODE_ADD_I3
;
10813 inst
.instruction
= T_OPCODE_CMP_LR
;
10815 inst
.instruction
|= Rn
;
10816 inst
.instruction
|= Rm
<< 3;
10820 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10821 inst
.instruction
= T_OPCODE_MOV_HR
;
10823 inst
.instruction
= T_OPCODE_CMP_HR
;
10829 constraint (Rn
> 7,
10830 _("only lo regs allowed with immediate"));
10831 inst
.instruction
|= Rn
<< 8;
10832 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10843 top
= (inst
.instruction
& 0x00800000) != 0;
10844 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10846 constraint (top
, _(":lower16: not allowed this instruction"));
10847 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10849 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10851 constraint (!top
, _(":upper16: not allowed this instruction"));
10852 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10855 Rd
= inst
.operands
[0].reg
;
10856 reject_bad_reg (Rd
);
10858 inst
.instruction
|= Rd
<< 8;
10859 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10861 imm
= inst
.reloc
.exp
.X_add_number
;
10862 inst
.instruction
|= (imm
& 0xf000) << 4;
10863 inst
.instruction
|= (imm
& 0x0800) << 15;
10864 inst
.instruction
|= (imm
& 0x0700) << 4;
10865 inst
.instruction
|= (imm
& 0x00ff);
10870 do_t_mvn_tst (void)
10874 Rn
= inst
.operands
[0].reg
;
10875 Rm
= inst
.operands
[1].reg
;
10877 if (inst
.instruction
== T_MNEM_cmp
10878 || inst
.instruction
== T_MNEM_cmn
)
10879 constraint (Rn
== REG_PC
, BAD_PC
);
10881 reject_bad_reg (Rn
);
10882 reject_bad_reg (Rm
);
10884 if (unified_syntax
)
10886 int r0off
= (inst
.instruction
== T_MNEM_mvn
10887 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10888 bfd_boolean narrow
;
10890 if (inst
.size_req
== 4
10891 || inst
.instruction
> 0xffff
10892 || inst
.operands
[1].shifted
10893 || Rn
> 7 || Rm
> 7)
10895 else if (inst
.instruction
== T_MNEM_cmn
)
10897 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10898 narrow
= !in_it_block ();
10900 narrow
= in_it_block ();
10902 if (!inst
.operands
[1].isreg
)
10904 /* For an immediate, we always generate a 32-bit opcode;
10905 section relaxation will shrink it later if possible. */
10906 if (inst
.instruction
< 0xffff)
10907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10908 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10909 inst
.instruction
|= Rn
<< r0off
;
10910 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10914 /* See if we can do this with a 16-bit instruction. */
10917 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10918 inst
.instruction
|= Rn
;
10919 inst
.instruction
|= Rm
<< 3;
10923 constraint (inst
.operands
[1].shifted
10924 && inst
.operands
[1].immisreg
,
10925 _("shift must be constant"));
10926 if (inst
.instruction
< 0xffff)
10927 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10928 inst
.instruction
|= Rn
<< r0off
;
10929 encode_thumb32_shifted_operand (1);
10935 constraint (inst
.instruction
> 0xffff
10936 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10937 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10938 _("unshifted register required"));
10939 constraint (Rn
> 7 || Rm
> 7,
10942 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10943 inst
.instruction
|= Rn
;
10944 inst
.instruction
|= Rm
<< 3;
10953 if (do_vfp_nsyn_mrs () == SUCCESS
)
10956 Rd
= inst
.operands
[0].reg
;
10957 reject_bad_reg (Rd
);
10958 inst
.instruction
|= Rd
<< 8;
10960 if (inst
.operands
[1].isreg
)
10962 unsigned br
= inst
.operands
[1].reg
;
10963 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
10964 as_bad (_("bad register for mrs"));
10966 inst
.instruction
|= br
& (0xf << 16);
10967 inst
.instruction
|= (br
& 0x300) >> 4;
10968 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
10972 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10974 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
10975 constraint (flags
!= 0, _("selected processor does not support "
10976 "requested special purpose register"));
10978 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
10980 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10981 _("'APSR', 'CPSR' or 'SPSR' expected"));
10983 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10984 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10985 inst
.instruction
|= 0xf0000;
10995 if (do_vfp_nsyn_msr () == SUCCESS
)
10998 constraint (!inst
.operands
[1].isreg
,
10999 _("Thumb encoding does not support an immediate here"));
11001 if (inst
.operands
[0].isreg
)
11002 flags
= (int)(inst
.operands
[0].reg
);
11004 flags
= inst
.operands
[0].imm
;
11006 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11008 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11010 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11011 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11012 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11014 _("selected processor does not support requested special "
11015 "purpose register"));
11018 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11019 "requested special purpose register"));
11021 Rn
= inst
.operands
[1].reg
;
11022 reject_bad_reg (Rn
);
11024 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11025 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11026 inst
.instruction
|= (flags
& 0x300) >> 4;
11027 inst
.instruction
|= (flags
& 0xff);
11028 inst
.instruction
|= Rn
<< 16;
11034 bfd_boolean narrow
;
11035 unsigned Rd
, Rn
, Rm
;
11037 if (!inst
.operands
[2].present
)
11038 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11040 Rd
= inst
.operands
[0].reg
;
11041 Rn
= inst
.operands
[1].reg
;
11042 Rm
= inst
.operands
[2].reg
;
11044 if (unified_syntax
)
11046 if (inst
.size_req
== 4
11052 else if (inst
.instruction
== T_MNEM_muls
)
11053 narrow
= !in_it_block ();
11055 narrow
= in_it_block ();
11059 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11060 constraint (Rn
> 7 || Rm
> 7,
11067 /* 16-bit MULS/Conditional MUL. */
11068 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11069 inst
.instruction
|= Rd
;
11072 inst
.instruction
|= Rm
<< 3;
11074 inst
.instruction
|= Rn
<< 3;
11076 constraint (1, _("dest must overlap one source register"));
11080 constraint (inst
.instruction
!= T_MNEM_mul
,
11081 _("Thumb-2 MUL must not set flags"));
11083 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11084 inst
.instruction
|= Rd
<< 8;
11085 inst
.instruction
|= Rn
<< 16;
11086 inst
.instruction
|= Rm
<< 0;
11088 reject_bad_reg (Rd
);
11089 reject_bad_reg (Rn
);
11090 reject_bad_reg (Rm
);
11097 unsigned RdLo
, RdHi
, Rn
, Rm
;
11099 RdLo
= inst
.operands
[0].reg
;
11100 RdHi
= inst
.operands
[1].reg
;
11101 Rn
= inst
.operands
[2].reg
;
11102 Rm
= inst
.operands
[3].reg
;
11104 reject_bad_reg (RdLo
);
11105 reject_bad_reg (RdHi
);
11106 reject_bad_reg (Rn
);
11107 reject_bad_reg (Rm
);
11109 inst
.instruction
|= RdLo
<< 12;
11110 inst
.instruction
|= RdHi
<< 8;
11111 inst
.instruction
|= Rn
<< 16;
11112 inst
.instruction
|= Rm
;
11115 as_tsktsk (_("rdhi and rdlo must be different"));
11121 set_it_insn_type (NEUTRAL_IT_INSN
);
11123 if (unified_syntax
)
11125 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11127 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11128 inst
.instruction
|= inst
.operands
[0].imm
;
11132 /* PR9722: Check for Thumb2 availability before
11133 generating a thumb2 nop instruction. */
11134 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11136 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11137 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11140 inst
.instruction
= 0x46c0;
11145 constraint (inst
.operands
[0].present
,
11146 _("Thumb does not support NOP with hints"));
11147 inst
.instruction
= 0x46c0;
11154 if (unified_syntax
)
11156 bfd_boolean narrow
;
11158 if (THUMB_SETS_FLAGS (inst
.instruction
))
11159 narrow
= !in_it_block ();
11161 narrow
= in_it_block ();
11162 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11164 if (inst
.size_req
== 4)
11169 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11170 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11175 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11176 inst
.instruction
|= inst
.operands
[0].reg
;
11177 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11182 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11184 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11186 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11187 inst
.instruction
|= inst
.operands
[0].reg
;
11188 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11197 Rd
= inst
.operands
[0].reg
;
11198 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11200 reject_bad_reg (Rd
);
11201 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11202 reject_bad_reg (Rn
);
11204 inst
.instruction
|= Rd
<< 8;
11205 inst
.instruction
|= Rn
<< 16;
11207 if (!inst
.operands
[2].isreg
)
11209 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11210 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11216 Rm
= inst
.operands
[2].reg
;
11217 reject_bad_reg (Rm
);
11219 constraint (inst
.operands
[2].shifted
11220 && inst
.operands
[2].immisreg
,
11221 _("shift must be constant"));
11222 encode_thumb32_shifted_operand (2);
11229 unsigned Rd
, Rn
, Rm
;
11231 Rd
= inst
.operands
[0].reg
;
11232 Rn
= inst
.operands
[1].reg
;
11233 Rm
= inst
.operands
[2].reg
;
11235 reject_bad_reg (Rd
);
11236 reject_bad_reg (Rn
);
11237 reject_bad_reg (Rm
);
11239 inst
.instruction
|= Rd
<< 8;
11240 inst
.instruction
|= Rn
<< 16;
11241 inst
.instruction
|= Rm
;
11242 if (inst
.operands
[3].present
)
11244 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11245 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11246 _("expression too complex"));
11247 inst
.instruction
|= (val
& 0x1c) << 10;
11248 inst
.instruction
|= (val
& 0x03) << 6;
11255 if (!inst
.operands
[3].present
)
11259 inst
.instruction
&= ~0x00000020;
11261 /* PR 10168. Swap the Rm and Rn registers. */
11262 Rtmp
= inst
.operands
[1].reg
;
11263 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11264 inst
.operands
[2].reg
= Rtmp
;
11272 if (inst
.operands
[0].immisreg
)
11273 reject_bad_reg (inst
.operands
[0].imm
);
11275 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11279 do_t_push_pop (void)
11283 constraint (inst
.operands
[0].writeback
,
11284 _("push/pop do not support {reglist}^"));
11285 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11286 _("expression too complex"));
11288 mask
= inst
.operands
[0].imm
;
11289 if ((mask
& ~0xff) == 0)
11290 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11291 else if ((inst
.instruction
== T_MNEM_push
11292 && (mask
& ~0xff) == 1 << REG_LR
)
11293 || (inst
.instruction
== T_MNEM_pop
11294 && (mask
& ~0xff) == 1 << REG_PC
))
11296 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11297 inst
.instruction
|= THUMB_PP_PC_LR
;
11298 inst
.instruction
|= mask
& 0xff;
11300 else if (unified_syntax
)
11302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11303 encode_thumb2_ldmstm (13, mask
, TRUE
);
11307 inst
.error
= _("invalid register list to push/pop instruction");
11317 Rd
= inst
.operands
[0].reg
;
11318 Rm
= inst
.operands
[1].reg
;
11320 reject_bad_reg (Rd
);
11321 reject_bad_reg (Rm
);
11323 inst
.instruction
|= Rd
<< 8;
11324 inst
.instruction
|= Rm
<< 16;
11325 inst
.instruction
|= Rm
;
11333 Rd
= inst
.operands
[0].reg
;
11334 Rm
= inst
.operands
[1].reg
;
11336 reject_bad_reg (Rd
);
11337 reject_bad_reg (Rm
);
11339 if (Rd
<= 7 && Rm
<= 7
11340 && inst
.size_req
!= 4)
11342 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11343 inst
.instruction
|= Rd
;
11344 inst
.instruction
|= Rm
<< 3;
11346 else if (unified_syntax
)
11348 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11349 inst
.instruction
|= Rd
<< 8;
11350 inst
.instruction
|= Rm
<< 16;
11351 inst
.instruction
|= Rm
;
11354 inst
.error
= BAD_HIREG
;
11362 Rd
= inst
.operands
[0].reg
;
11363 Rm
= inst
.operands
[1].reg
;
11365 reject_bad_reg (Rd
);
11366 reject_bad_reg (Rm
);
11368 inst
.instruction
|= Rd
<< 8;
11369 inst
.instruction
|= Rm
;
11377 Rd
= inst
.operands
[0].reg
;
11378 Rs
= (inst
.operands
[1].present
11379 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11380 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11382 reject_bad_reg (Rd
);
11383 reject_bad_reg (Rs
);
11384 if (inst
.operands
[2].isreg
)
11385 reject_bad_reg (inst
.operands
[2].reg
);
11387 inst
.instruction
|= Rd
<< 8;
11388 inst
.instruction
|= Rs
<< 16;
11389 if (!inst
.operands
[2].isreg
)
11391 bfd_boolean narrow
;
11393 if ((inst
.instruction
& 0x00100000) != 0)
11394 narrow
= !in_it_block ();
11396 narrow
= in_it_block ();
11398 if (Rd
> 7 || Rs
> 7)
11401 if (inst
.size_req
== 4 || !unified_syntax
)
11404 if (inst
.reloc
.exp
.X_op
!= O_constant
11405 || inst
.reloc
.exp
.X_add_number
!= 0)
11408 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11409 relaxation, but it doesn't seem worth the hassle. */
11412 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11413 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11414 inst
.instruction
|= Rs
<< 3;
11415 inst
.instruction
|= Rd
;
11419 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11420 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11424 encode_thumb32_shifted_operand (2);
11430 set_it_insn_type (OUTSIDE_IT_INSN
);
11431 if (inst
.operands
[0].imm
)
11432 inst
.instruction
|= 0x8;
11438 if (!inst
.operands
[1].present
)
11439 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11441 if (unified_syntax
)
11443 bfd_boolean narrow
;
11446 switch (inst
.instruction
)
11449 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11451 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11453 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11455 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11459 if (THUMB_SETS_FLAGS (inst
.instruction
))
11460 narrow
= !in_it_block ();
11462 narrow
= in_it_block ();
11463 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11465 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11467 if (inst
.operands
[2].isreg
11468 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11469 || inst
.operands
[2].reg
> 7))
11471 if (inst
.size_req
== 4)
11474 reject_bad_reg (inst
.operands
[0].reg
);
11475 reject_bad_reg (inst
.operands
[1].reg
);
11479 if (inst
.operands
[2].isreg
)
11481 reject_bad_reg (inst
.operands
[2].reg
);
11482 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11483 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11484 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11485 inst
.instruction
|= inst
.operands
[2].reg
;
11489 inst
.operands
[1].shifted
= 1;
11490 inst
.operands
[1].shift_kind
= shift_kind
;
11491 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11492 ? T_MNEM_movs
: T_MNEM_mov
);
11493 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11494 encode_thumb32_shifted_operand (1);
11495 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11496 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11501 if (inst
.operands
[2].isreg
)
11503 switch (shift_kind
)
11505 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11506 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11507 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11508 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11512 inst
.instruction
|= inst
.operands
[0].reg
;
11513 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11517 switch (shift_kind
)
11519 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11520 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11521 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11524 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11525 inst
.instruction
|= inst
.operands
[0].reg
;
11526 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11532 constraint (inst
.operands
[0].reg
> 7
11533 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11534 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11536 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11538 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11539 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11540 _("source1 and dest must be same register"));
11542 switch (inst
.instruction
)
11544 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11545 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11546 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11547 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11551 inst
.instruction
|= inst
.operands
[0].reg
;
11552 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11556 switch (inst
.instruction
)
11558 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11559 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11560 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11561 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11564 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11565 inst
.instruction
|= inst
.operands
[0].reg
;
11566 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11574 unsigned Rd
, Rn
, Rm
;
11576 Rd
= inst
.operands
[0].reg
;
11577 Rn
= inst
.operands
[1].reg
;
11578 Rm
= inst
.operands
[2].reg
;
11580 reject_bad_reg (Rd
);
11581 reject_bad_reg (Rn
);
11582 reject_bad_reg (Rm
);
11584 inst
.instruction
|= Rd
<< 8;
11585 inst
.instruction
|= Rn
<< 16;
11586 inst
.instruction
|= Rm
;
11592 unsigned Rd
, Rn
, Rm
;
11594 Rd
= inst
.operands
[0].reg
;
11595 Rm
= inst
.operands
[1].reg
;
11596 Rn
= inst
.operands
[2].reg
;
11598 reject_bad_reg (Rd
);
11599 reject_bad_reg (Rn
);
11600 reject_bad_reg (Rm
);
11602 inst
.instruction
|= Rd
<< 8;
11603 inst
.instruction
|= Rn
<< 16;
11604 inst
.instruction
|= Rm
;
11610 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11612 _("SMC is not permitted on this architecture"));
11613 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11614 _("expression too complex"));
11615 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11616 inst
.instruction
|= (value
& 0xf000) >> 12;
11617 inst
.instruction
|= (value
& 0x0ff0);
11618 inst
.instruction
|= (value
& 0x000f) << 16;
11624 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11626 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11627 inst
.instruction
|= (value
& 0x0fff);
11628 inst
.instruction
|= (value
& 0xf000) << 4;
11632 do_t_ssat_usat (int bias
)
11636 Rd
= inst
.operands
[0].reg
;
11637 Rn
= inst
.operands
[2].reg
;
11639 reject_bad_reg (Rd
);
11640 reject_bad_reg (Rn
);
11642 inst
.instruction
|= Rd
<< 8;
11643 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11644 inst
.instruction
|= Rn
<< 16;
11646 if (inst
.operands
[3].present
)
11648 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11650 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11652 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11653 _("expression too complex"));
11655 if (shift_amount
!= 0)
11657 constraint (shift_amount
> 31,
11658 _("shift expression is too large"));
11660 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11661 inst
.instruction
|= 0x00200000; /* sh bit. */
11663 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11664 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11672 do_t_ssat_usat (1);
11680 Rd
= inst
.operands
[0].reg
;
11681 Rn
= inst
.operands
[2].reg
;
11683 reject_bad_reg (Rd
);
11684 reject_bad_reg (Rn
);
11686 inst
.instruction
|= Rd
<< 8;
11687 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11688 inst
.instruction
|= Rn
<< 16;
11694 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11695 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11696 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11697 || inst
.operands
[2].negative
,
11700 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11702 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11703 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11704 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11705 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11711 if (!inst
.operands
[2].present
)
11712 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11714 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11715 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11716 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11719 inst
.instruction
|= inst
.operands
[0].reg
;
11720 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11721 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11722 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11728 unsigned Rd
, Rn
, Rm
;
11730 Rd
= inst
.operands
[0].reg
;
11731 Rn
= inst
.operands
[1].reg
;
11732 Rm
= inst
.operands
[2].reg
;
11734 reject_bad_reg (Rd
);
11735 reject_bad_reg (Rn
);
11736 reject_bad_reg (Rm
);
11738 inst
.instruction
|= Rd
<< 8;
11739 inst
.instruction
|= Rn
<< 16;
11740 inst
.instruction
|= Rm
;
11741 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11749 Rd
= inst
.operands
[0].reg
;
11750 Rm
= inst
.operands
[1].reg
;
11752 reject_bad_reg (Rd
);
11753 reject_bad_reg (Rm
);
11755 if (inst
.instruction
<= 0xffff
11756 && inst
.size_req
!= 4
11757 && Rd
<= 7 && Rm
<= 7
11758 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11761 inst
.instruction
|= Rd
;
11762 inst
.instruction
|= Rm
<< 3;
11764 else if (unified_syntax
)
11766 if (inst
.instruction
<= 0xffff)
11767 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11768 inst
.instruction
|= Rd
<< 8;
11769 inst
.instruction
|= Rm
;
11770 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11774 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11775 _("Thumb encoding does not support rotation"));
11776 constraint (1, BAD_HIREG
);
11783 /* We have to do the following check manually as ARM_EXT_OS only applies
11785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11787 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11788 /* This only applies to the v6m howver, not later architectures. */
11789 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11790 as_bad (_("SVC is not permitted on this architecture"));
11791 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11794 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11803 half
= (inst
.instruction
& 0x10) != 0;
11804 set_it_insn_type_last ();
11805 constraint (inst
.operands
[0].immisreg
,
11806 _("instruction requires register index"));
11808 Rn
= inst
.operands
[0].reg
;
11809 Rm
= inst
.operands
[0].imm
;
11811 constraint (Rn
== REG_SP
, BAD_SP
);
11812 reject_bad_reg (Rm
);
11814 constraint (!half
&& inst
.operands
[0].shifted
,
11815 _("instruction does not allow shifted index"));
11816 inst
.instruction
|= (Rn
<< 16) | Rm
;
11822 do_t_ssat_usat (0);
11830 Rd
= inst
.operands
[0].reg
;
11831 Rn
= inst
.operands
[2].reg
;
11833 reject_bad_reg (Rd
);
11834 reject_bad_reg (Rn
);
11836 inst
.instruction
|= Rd
<< 8;
11837 inst
.instruction
|= inst
.operands
[1].imm
;
11838 inst
.instruction
|= Rn
<< 16;
11841 /* Neon instruction encoder helpers. */
11843 /* Encodings for the different types for various Neon opcodes. */
11845 /* An "invalid" code for the following tables. */
11848 struct neon_tab_entry
11851 unsigned float_or_poly
;
11852 unsigned scalar_or_imm
;
11855 /* Map overloaded Neon opcodes to their respective encodings. */
11856 #define NEON_ENC_TAB \
11857 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11858 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11859 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11860 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11861 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11862 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11863 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11864 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11865 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11866 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11867 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11868 /* Register variants of the following two instructions are encoded as
11869 vcge / vcgt with the operands reversed. */ \
11870 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11871 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11872 X(vfma, N_INV, 0x0000c10, N_INV), \
11873 X(vfms, N_INV, 0x0200c10, N_INV), \
11874 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11875 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11876 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11877 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11878 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11879 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11880 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11881 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11882 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11883 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11884 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11885 X(vshl, 0x0000400, N_INV, 0x0800510), \
11886 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11887 X(vand, 0x0000110, N_INV, 0x0800030), \
11888 X(vbic, 0x0100110, N_INV, 0x0800030), \
11889 X(veor, 0x1000110, N_INV, N_INV), \
11890 X(vorn, 0x0300110, N_INV, 0x0800010), \
11891 X(vorr, 0x0200110, N_INV, 0x0800010), \
11892 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11893 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11894 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11895 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11896 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11897 X(vst1, 0x0000000, 0x0800000, N_INV), \
11898 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11899 X(vst2, 0x0000100, 0x0800100, N_INV), \
11900 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11901 X(vst3, 0x0000200, 0x0800200, N_INV), \
11902 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11903 X(vst4, 0x0000300, 0x0800300, N_INV), \
11904 X(vmovn, 0x1b20200, N_INV, N_INV), \
11905 X(vtrn, 0x1b20080, N_INV, N_INV), \
11906 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11907 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11908 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11909 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11910 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11911 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11912 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11913 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11914 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11915 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11916 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11920 #define X(OPC,I,F,S) N_MNEM_##OPC
11925 static const struct neon_tab_entry neon_enc_tab
[] =
11927 #define X(OPC,I,F,S) { (I), (F), (S) }
11932 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11933 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11934 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11935 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11936 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11937 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11938 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11939 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11940 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11941 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11942 #define NEON_ENC_SINGLE_(X) \
11943 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11944 #define NEON_ENC_DOUBLE_(X) \
11945 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11947 #define NEON_ENCODE(type, inst) \
11950 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11951 inst.is_neon = 1; \
11955 #define check_neon_suffixes \
11958 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11960 as_bad (_("invalid neon suffix for non neon instruction")); \
11966 /* Define shapes for instruction operands. The following mnemonic characters
11967 are used in this table:
11969 F - VFP S<n> register
11970 D - Neon D<n> register
11971 Q - Neon Q<n> register
11975 L - D<n> register list
11977 This table is used to generate various data:
11978 - enumerations of the form NS_DDR to be used as arguments to
11980 - a table classifying shapes into single, double, quad, mixed.
11981 - a table used to drive neon_select_shape. */
11983 #define NEON_SHAPE_DEF \
11984 X(3, (D, D, D), DOUBLE), \
11985 X(3, (Q, Q, Q), QUAD), \
11986 X(3, (D, D, I), DOUBLE), \
11987 X(3, (Q, Q, I), QUAD), \
11988 X(3, (D, D, S), DOUBLE), \
11989 X(3, (Q, Q, S), QUAD), \
11990 X(2, (D, D), DOUBLE), \
11991 X(2, (Q, Q), QUAD), \
11992 X(2, (D, S), DOUBLE), \
11993 X(2, (Q, S), QUAD), \
11994 X(2, (D, R), DOUBLE), \
11995 X(2, (Q, R), QUAD), \
11996 X(2, (D, I), DOUBLE), \
11997 X(2, (Q, I), QUAD), \
11998 X(3, (D, L, D), DOUBLE), \
11999 X(2, (D, Q), MIXED), \
12000 X(2, (Q, D), MIXED), \
12001 X(3, (D, Q, I), MIXED), \
12002 X(3, (Q, D, I), MIXED), \
12003 X(3, (Q, D, D), MIXED), \
12004 X(3, (D, Q, Q), MIXED), \
12005 X(3, (Q, Q, D), MIXED), \
12006 X(3, (Q, D, S), MIXED), \
12007 X(3, (D, Q, S), MIXED), \
12008 X(4, (D, D, D, I), DOUBLE), \
12009 X(4, (Q, Q, Q, I), QUAD), \
12010 X(2, (F, F), SINGLE), \
12011 X(3, (F, F, F), SINGLE), \
12012 X(2, (F, I), SINGLE), \
12013 X(2, (F, D), MIXED), \
12014 X(2, (D, F), MIXED), \
12015 X(3, (F, F, I), MIXED), \
12016 X(4, (R, R, F, F), SINGLE), \
12017 X(4, (F, F, R, R), SINGLE), \
12018 X(3, (D, R, R), DOUBLE), \
12019 X(3, (R, R, D), DOUBLE), \
12020 X(2, (S, R), SINGLE), \
12021 X(2, (R, S), SINGLE), \
12022 X(2, (F, R), SINGLE), \
12023 X(2, (R, F), SINGLE)
12025 #define S2(A,B) NS_##A##B
12026 #define S3(A,B,C) NS_##A##B##C
12027 #define S4(A,B,C,D) NS_##A##B##C##D
12029 #define X(N, L, C) S##N L
12042 enum neon_shape_class
12050 #define X(N, L, C) SC_##C
12052 static enum neon_shape_class neon_shape_class
[] =
12070 /* Register widths of above. */
12071 static unsigned neon_shape_el_size
[] =
12082 struct neon_shape_info
12085 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12088 #define S2(A,B) { SE_##A, SE_##B }
12089 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12090 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12092 #define X(N, L, C) { N, S##N L }
12094 static struct neon_shape_info neon_shape_tab
[] =
12104 /* Bit masks used in type checking given instructions.
12105 'N_EQK' means the type must be the same as (or based on in some way) the key
12106 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12107 set, various other bits can be set as well in order to modify the meaning of
12108 the type constraint. */
12110 enum neon_type_mask
12133 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12134 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12135 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12136 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12137 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12138 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12139 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12140 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12141 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12142 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12144 N_MAX_NONSPECIAL
= N_F64
12147 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12149 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12150 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12151 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12152 #define N_SUF_32 (N_SU_32 | N_F32)
12153 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12154 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12156 /* Pass this as the first type argument to neon_check_type to ignore types
12158 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12160 /* Select a "shape" for the current instruction (describing register types or
12161 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12162 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12163 function of operand parsing, so this function doesn't need to be called.
12164 Shapes should be listed in order of decreasing length. */
12166 static enum neon_shape
12167 neon_select_shape (enum neon_shape shape
, ...)
12170 enum neon_shape first_shape
= shape
;
12172 /* Fix missing optional operands. FIXME: we don't know at this point how
12173 many arguments we should have, so this makes the assumption that we have
12174 > 1. This is true of all current Neon opcodes, I think, but may not be
12175 true in the future. */
12176 if (!inst
.operands
[1].present
)
12177 inst
.operands
[1] = inst
.operands
[0];
12179 va_start (ap
, shape
);
12181 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12186 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12188 if (!inst
.operands
[j
].present
)
12194 switch (neon_shape_tab
[shape
].el
[j
])
12197 if (!(inst
.operands
[j
].isreg
12198 && inst
.operands
[j
].isvec
12199 && inst
.operands
[j
].issingle
12200 && !inst
.operands
[j
].isquad
))
12205 if (!(inst
.operands
[j
].isreg
12206 && inst
.operands
[j
].isvec
12207 && !inst
.operands
[j
].isquad
12208 && !inst
.operands
[j
].issingle
))
12213 if (!(inst
.operands
[j
].isreg
12214 && !inst
.operands
[j
].isvec
))
12219 if (!(inst
.operands
[j
].isreg
12220 && inst
.operands
[j
].isvec
12221 && inst
.operands
[j
].isquad
12222 && !inst
.operands
[j
].issingle
))
12227 if (!(!inst
.operands
[j
].isreg
12228 && !inst
.operands
[j
].isscalar
))
12233 if (!(!inst
.operands
[j
].isreg
12234 && inst
.operands
[j
].isscalar
))
12250 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12251 first_error (_("invalid instruction shape"));
12256 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12257 means the Q bit should be set). */
12260 neon_quad (enum neon_shape shape
)
12262 return neon_shape_class
[shape
] == SC_QUAD
;
12266 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12269 /* Allow modification to be made to types which are constrained to be
12270 based on the key element, based on bits set alongside N_EQK. */
12271 if ((typebits
& N_EQK
) != 0)
12273 if ((typebits
& N_HLF
) != 0)
12275 else if ((typebits
& N_DBL
) != 0)
12277 if ((typebits
& N_SGN
) != 0)
12278 *g_type
= NT_signed
;
12279 else if ((typebits
& N_UNS
) != 0)
12280 *g_type
= NT_unsigned
;
12281 else if ((typebits
& N_INT
) != 0)
12282 *g_type
= NT_integer
;
12283 else if ((typebits
& N_FLT
) != 0)
12284 *g_type
= NT_float
;
12285 else if ((typebits
& N_SIZ
) != 0)
12286 *g_type
= NT_untyped
;
12290 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12291 operand type, i.e. the single type specified in a Neon instruction when it
12292 is the only one given. */
12294 static struct neon_type_el
12295 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12297 struct neon_type_el dest
= *key
;
12299 gas_assert ((thisarg
& N_EQK
) != 0);
12301 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12306 /* Convert Neon type and size into compact bitmask representation. */
12308 static enum neon_type_mask
12309 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12316 case 8: return N_8
;
12317 case 16: return N_16
;
12318 case 32: return N_32
;
12319 case 64: return N_64
;
12327 case 8: return N_I8
;
12328 case 16: return N_I16
;
12329 case 32: return N_I32
;
12330 case 64: return N_I64
;
12338 case 16: return N_F16
;
12339 case 32: return N_F32
;
12340 case 64: return N_F64
;
12348 case 8: return N_P8
;
12349 case 16: return N_P16
;
12357 case 8: return N_S8
;
12358 case 16: return N_S16
;
12359 case 32: return N_S32
;
12360 case 64: return N_S64
;
12368 case 8: return N_U8
;
12369 case 16: return N_U16
;
12370 case 32: return N_U32
;
12371 case 64: return N_U64
;
12382 /* Convert compact Neon bitmask type representation to a type and size. Only
12383 handles the case where a single bit is set in the mask. */
12386 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12387 enum neon_type_mask mask
)
12389 if ((mask
& N_EQK
) != 0)
12392 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12394 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12396 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12398 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12403 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12405 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12406 *type
= NT_unsigned
;
12407 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12408 *type
= NT_integer
;
12409 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12410 *type
= NT_untyped
;
12411 else if ((mask
& (N_P8
| N_P16
)) != 0)
12413 else if ((mask
& (N_F32
| N_F64
)) != 0)
12421 /* Modify a bitmask of allowed types. This is only needed for type
12425 modify_types_allowed (unsigned allowed
, unsigned mods
)
12428 enum neon_el_type type
;
12434 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12436 if (el_type_of_type_chk (&type
, &size
,
12437 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12439 neon_modify_type_size (mods
, &type
, &size
);
12440 destmask
|= type_chk_of_el_type (type
, size
);
12447 /* Check type and return type classification.
12448 The manual states (paraphrase): If one datatype is given, it indicates the
12450 - the second operand, if there is one
12451 - the operand, if there is no second operand
12452 - the result, if there are no operands.
12453 This isn't quite good enough though, so we use a concept of a "key" datatype
12454 which is set on a per-instruction basis, which is the one which matters when
12455 only one data type is written.
12456 Note: this function has side-effects (e.g. filling in missing operands). All
12457 Neon instructions should call it before performing bit encoding. */
12459 static struct neon_type_el
12460 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12463 unsigned i
, pass
, key_el
= 0;
12464 unsigned types
[NEON_MAX_TYPE_ELS
];
12465 enum neon_el_type k_type
= NT_invtype
;
12466 unsigned k_size
= -1u;
12467 struct neon_type_el badtype
= {NT_invtype
, -1};
12468 unsigned key_allowed
= 0;
12470 /* Optional registers in Neon instructions are always (not) in operand 1.
12471 Fill in the missing operand here, if it was omitted. */
12472 if (els
> 1 && !inst
.operands
[1].present
)
12473 inst
.operands
[1] = inst
.operands
[0];
12475 /* Suck up all the varargs. */
12477 for (i
= 0; i
< els
; i
++)
12479 unsigned thisarg
= va_arg (ap
, unsigned);
12480 if (thisarg
== N_IGNORE_TYPE
)
12485 types
[i
] = thisarg
;
12486 if ((thisarg
& N_KEY
) != 0)
12491 if (inst
.vectype
.elems
> 0)
12492 for (i
= 0; i
< els
; i
++)
12493 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12495 first_error (_("types specified in both the mnemonic and operands"));
12499 /* Duplicate inst.vectype elements here as necessary.
12500 FIXME: No idea if this is exactly the same as the ARM assembler,
12501 particularly when an insn takes one register and one non-register
12503 if (inst
.vectype
.elems
== 1 && els
> 1)
12506 inst
.vectype
.elems
= els
;
12507 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12508 for (j
= 0; j
< els
; j
++)
12510 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12513 else if (inst
.vectype
.elems
== 0 && els
> 0)
12516 /* No types were given after the mnemonic, so look for types specified
12517 after each operand. We allow some flexibility here; as long as the
12518 "key" operand has a type, we can infer the others. */
12519 for (j
= 0; j
< els
; j
++)
12520 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12521 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12523 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12525 for (j
= 0; j
< els
; j
++)
12526 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12527 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12532 first_error (_("operand types can't be inferred"));
12536 else if (inst
.vectype
.elems
!= els
)
12538 first_error (_("type specifier has the wrong number of parts"));
12542 for (pass
= 0; pass
< 2; pass
++)
12544 for (i
= 0; i
< els
; i
++)
12546 unsigned thisarg
= types
[i
];
12547 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12548 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12549 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12550 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12552 /* Decay more-specific signed & unsigned types to sign-insensitive
12553 integer types if sign-specific variants are unavailable. */
12554 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12555 && (types_allowed
& N_SU_ALL
) == 0)
12556 g_type
= NT_integer
;
12558 /* If only untyped args are allowed, decay any more specific types to
12559 them. Some instructions only care about signs for some element
12560 sizes, so handle that properly. */
12561 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12562 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12563 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12564 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12565 g_type
= NT_untyped
;
12569 if ((thisarg
& N_KEY
) != 0)
12573 key_allowed
= thisarg
& ~N_KEY
;
12578 if ((thisarg
& N_VFP
) != 0)
12580 enum neon_shape_el regshape
;
12581 unsigned regwidth
, match
;
12583 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12586 first_error (_("invalid instruction shape"));
12589 regshape
= neon_shape_tab
[ns
].el
[i
];
12590 regwidth
= neon_shape_el_size
[regshape
];
12592 /* In VFP mode, operands must match register widths. If we
12593 have a key operand, use its width, else use the width of
12594 the current operand. */
12600 if (regwidth
!= match
)
12602 first_error (_("operand size must match register width"));
12607 if ((thisarg
& N_EQK
) == 0)
12609 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12611 if ((given_type
& types_allowed
) == 0)
12613 first_error (_("bad type in Neon instruction"));
12619 enum neon_el_type mod_k_type
= k_type
;
12620 unsigned mod_k_size
= k_size
;
12621 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12622 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12624 first_error (_("inconsistent types in Neon instruction"));
12632 return inst
.vectype
.el
[key_el
];
12635 /* Neon-style VFP instruction forwarding. */
12637 /* Thumb VFP instructions have 0xE in the condition field. */
12640 do_vfp_cond_or_thumb (void)
12645 inst
.instruction
|= 0xe0000000;
12647 inst
.instruction
|= inst
.cond
<< 28;
12650 /* Look up and encode a simple mnemonic, for use as a helper function for the
12651 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12652 etc. It is assumed that operand parsing has already been done, and that the
12653 operands are in the form expected by the given opcode (this isn't necessarily
12654 the same as the form in which they were parsed, hence some massaging must
12655 take place before this function is called).
12656 Checks current arch version against that in the looked-up opcode. */
12659 do_vfp_nsyn_opcode (const char *opname
)
12661 const struct asm_opcode
*opcode
;
12663 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12668 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12669 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12676 inst
.instruction
= opcode
->tvalue
;
12677 opcode
->tencode ();
12681 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12682 opcode
->aencode ();
12687 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12689 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12694 do_vfp_nsyn_opcode ("fadds");
12696 do_vfp_nsyn_opcode ("fsubs");
12701 do_vfp_nsyn_opcode ("faddd");
12703 do_vfp_nsyn_opcode ("fsubd");
12707 /* Check operand types to see if this is a VFP instruction, and if so call
12711 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12713 enum neon_shape rs
;
12714 struct neon_type_el et
;
12719 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12720 et
= neon_check_type (2, rs
,
12721 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12725 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12726 et
= neon_check_type (3, rs
,
12727 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12734 if (et
.type
!= NT_invtype
)
12745 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12747 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12752 do_vfp_nsyn_opcode ("fmacs");
12754 do_vfp_nsyn_opcode ("fnmacs");
12759 do_vfp_nsyn_opcode ("fmacd");
12761 do_vfp_nsyn_opcode ("fnmacd");
12766 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12768 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12773 do_vfp_nsyn_opcode ("ffmas");
12775 do_vfp_nsyn_opcode ("ffnmas");
12780 do_vfp_nsyn_opcode ("ffmad");
12782 do_vfp_nsyn_opcode ("ffnmad");
12787 do_vfp_nsyn_mul (enum neon_shape rs
)
12790 do_vfp_nsyn_opcode ("fmuls");
12792 do_vfp_nsyn_opcode ("fmuld");
12796 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12798 int is_neg
= (inst
.instruction
& 0x80) != 0;
12799 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12804 do_vfp_nsyn_opcode ("fnegs");
12806 do_vfp_nsyn_opcode ("fabss");
12811 do_vfp_nsyn_opcode ("fnegd");
12813 do_vfp_nsyn_opcode ("fabsd");
12817 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12818 insns belong to Neon, and are handled elsewhere. */
12821 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12823 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12827 do_vfp_nsyn_opcode ("fldmdbs");
12829 do_vfp_nsyn_opcode ("fldmias");
12834 do_vfp_nsyn_opcode ("fstmdbs");
12836 do_vfp_nsyn_opcode ("fstmias");
12841 do_vfp_nsyn_sqrt (void)
12843 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12844 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12847 do_vfp_nsyn_opcode ("fsqrts");
12849 do_vfp_nsyn_opcode ("fsqrtd");
12853 do_vfp_nsyn_div (void)
12855 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12856 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12857 N_F32
| N_F64
| N_KEY
| N_VFP
);
12860 do_vfp_nsyn_opcode ("fdivs");
12862 do_vfp_nsyn_opcode ("fdivd");
12866 do_vfp_nsyn_nmul (void)
12868 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12869 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12870 N_F32
| N_F64
| N_KEY
| N_VFP
);
12874 NEON_ENCODE (SINGLE
, inst
);
12875 do_vfp_sp_dyadic ();
12879 NEON_ENCODE (DOUBLE
, inst
);
12880 do_vfp_dp_rd_rn_rm ();
12882 do_vfp_cond_or_thumb ();
12886 do_vfp_nsyn_cmp (void)
12888 if (inst
.operands
[1].isreg
)
12890 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12891 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12895 NEON_ENCODE (SINGLE
, inst
);
12896 do_vfp_sp_monadic ();
12900 NEON_ENCODE (DOUBLE
, inst
);
12901 do_vfp_dp_rd_rm ();
12906 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12907 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12909 switch (inst
.instruction
& 0x0fffffff)
12912 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12915 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12923 NEON_ENCODE (SINGLE
, inst
);
12924 do_vfp_sp_compare_z ();
12928 NEON_ENCODE (DOUBLE
, inst
);
12932 do_vfp_cond_or_thumb ();
12936 nsyn_insert_sp (void)
12938 inst
.operands
[1] = inst
.operands
[0];
12939 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12940 inst
.operands
[0].reg
= REG_SP
;
12941 inst
.operands
[0].isreg
= 1;
12942 inst
.operands
[0].writeback
= 1;
12943 inst
.operands
[0].present
= 1;
12947 do_vfp_nsyn_push (void)
12950 if (inst
.operands
[1].issingle
)
12951 do_vfp_nsyn_opcode ("fstmdbs");
12953 do_vfp_nsyn_opcode ("fstmdbd");
12957 do_vfp_nsyn_pop (void)
12960 if (inst
.operands
[1].issingle
)
12961 do_vfp_nsyn_opcode ("fldmias");
12963 do_vfp_nsyn_opcode ("fldmiad");
12966 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12967 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12970 neon_dp_fixup (struct arm_it
* insn
)
12972 unsigned int i
= insn
->instruction
;
12977 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12988 insn
->instruction
= i
;
12991 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12995 neon_logbits (unsigned x
)
12997 return ffs (x
) - 4;
13000 #define LOW4(R) ((R) & 0xf)
13001 #define HI1(R) (((R) >> 4) & 1)
13003 /* Encode insns with bit pattern:
13005 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13006 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13008 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13009 different meaning for some instruction. */
13012 neon_three_same (int isquad
, int ubit
, int size
)
13014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13016 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13017 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13018 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13019 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13020 inst
.instruction
|= (isquad
!= 0) << 6;
13021 inst
.instruction
|= (ubit
!= 0) << 24;
13023 inst
.instruction
|= neon_logbits (size
) << 20;
13025 neon_dp_fixup (&inst
);
13028 /* Encode instructions of the form:
13030 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13031 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13033 Don't write size if SIZE == -1. */
13036 neon_two_same (int qbit
, int ubit
, int size
)
13038 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13039 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13040 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13041 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13042 inst
.instruction
|= (qbit
!= 0) << 6;
13043 inst
.instruction
|= (ubit
!= 0) << 24;
13046 inst
.instruction
|= neon_logbits (size
) << 18;
13048 neon_dp_fixup (&inst
);
13051 /* Neon instruction encoders, in approximate order of appearance. */
13054 do_neon_dyadic_i_su (void)
13056 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13057 struct neon_type_el et
= neon_check_type (3, rs
,
13058 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13059 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13063 do_neon_dyadic_i64_su (void)
13065 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13066 struct neon_type_el et
= neon_check_type (3, rs
,
13067 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13068 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13072 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13075 unsigned size
= et
.size
>> 3;
13076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13080 inst
.instruction
|= (isquad
!= 0) << 6;
13081 inst
.instruction
|= immbits
<< 16;
13082 inst
.instruction
|= (size
>> 3) << 7;
13083 inst
.instruction
|= (size
& 0x7) << 19;
13085 inst
.instruction
|= (uval
!= 0) << 24;
13087 neon_dp_fixup (&inst
);
13091 do_neon_shl_imm (void)
13093 if (!inst
.operands
[2].isreg
)
13095 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13096 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13097 NEON_ENCODE (IMMED
, inst
);
13098 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13102 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13103 struct neon_type_el et
= neon_check_type (3, rs
,
13104 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13107 /* VSHL/VQSHL 3-register variants have syntax such as:
13109 whereas other 3-register operations encoded by neon_three_same have
13112 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13114 tmp
= inst
.operands
[2].reg
;
13115 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13116 inst
.operands
[1].reg
= tmp
;
13117 NEON_ENCODE (INTEGER
, inst
);
13118 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13123 do_neon_qshl_imm (void)
13125 if (!inst
.operands
[2].isreg
)
13127 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13128 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13130 NEON_ENCODE (IMMED
, inst
);
13131 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13132 inst
.operands
[2].imm
);
13136 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13137 struct neon_type_el et
= neon_check_type (3, rs
,
13138 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13141 /* See note in do_neon_shl_imm. */
13142 tmp
= inst
.operands
[2].reg
;
13143 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13144 inst
.operands
[1].reg
= tmp
;
13145 NEON_ENCODE (INTEGER
, inst
);
13146 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13151 do_neon_rshl (void)
13153 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13154 struct neon_type_el et
= neon_check_type (3, rs
,
13155 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13158 tmp
= inst
.operands
[2].reg
;
13159 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13160 inst
.operands
[1].reg
= tmp
;
13161 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13165 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13167 /* Handle .I8 pseudo-instructions. */
13170 /* Unfortunately, this will make everything apart from zero out-of-range.
13171 FIXME is this the intended semantics? There doesn't seem much point in
13172 accepting .I8 if so. */
13173 immediate
|= immediate
<< 8;
13179 if (immediate
== (immediate
& 0x000000ff))
13181 *immbits
= immediate
;
13184 else if (immediate
== (immediate
& 0x0000ff00))
13186 *immbits
= immediate
>> 8;
13189 else if (immediate
== (immediate
& 0x00ff0000))
13191 *immbits
= immediate
>> 16;
13194 else if (immediate
== (immediate
& 0xff000000))
13196 *immbits
= immediate
>> 24;
13199 if ((immediate
& 0xffff) != (immediate
>> 16))
13200 goto bad_immediate
;
13201 immediate
&= 0xffff;
13204 if (immediate
== (immediate
& 0x000000ff))
13206 *immbits
= immediate
;
13209 else if (immediate
== (immediate
& 0x0000ff00))
13211 *immbits
= immediate
>> 8;
13216 first_error (_("immediate value out of range"));
13220 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13224 neon_bits_same_in_bytes (unsigned imm
)
13226 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13227 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13228 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13229 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13232 /* For immediate of above form, return 0bABCD. */
13235 neon_squash_bits (unsigned imm
)
13237 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13238 | ((imm
& 0x01000000) >> 21);
13241 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13244 neon_qfloat_bits (unsigned imm
)
13246 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13249 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13250 the instruction. *OP is passed as the initial value of the op field, and
13251 may be set to a different value depending on the constant (i.e.
13252 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13253 MVN). If the immediate looks like a repeated pattern then also
13254 try smaller element sizes. */
13257 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13258 unsigned *immbits
, int *op
, int size
,
13259 enum neon_el_type type
)
13261 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13263 if (type
== NT_float
&& !float_p
)
13266 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13268 if (size
!= 32 || *op
== 1)
13270 *immbits
= neon_qfloat_bits (immlo
);
13276 if (neon_bits_same_in_bytes (immhi
)
13277 && neon_bits_same_in_bytes (immlo
))
13281 *immbits
= (neon_squash_bits (immhi
) << 4)
13282 | neon_squash_bits (immlo
);
13287 if (immhi
!= immlo
)
13293 if (immlo
== (immlo
& 0x000000ff))
13298 else if (immlo
== (immlo
& 0x0000ff00))
13300 *immbits
= immlo
>> 8;
13303 else if (immlo
== (immlo
& 0x00ff0000))
13305 *immbits
= immlo
>> 16;
13308 else if (immlo
== (immlo
& 0xff000000))
13310 *immbits
= immlo
>> 24;
13313 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13315 *immbits
= (immlo
>> 8) & 0xff;
13318 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13320 *immbits
= (immlo
>> 16) & 0xff;
13324 if ((immlo
& 0xffff) != (immlo
>> 16))
13331 if (immlo
== (immlo
& 0x000000ff))
13336 else if (immlo
== (immlo
& 0x0000ff00))
13338 *immbits
= immlo
>> 8;
13342 if ((immlo
& 0xff) != (immlo
>> 8))
13347 if (immlo
== (immlo
& 0x000000ff))
13349 /* Don't allow MVN with 8-bit immediate. */
13359 /* Write immediate bits [7:0] to the following locations:
13361 |28/24|23 19|18 16|15 4|3 0|
13362 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13364 This function is used by VMOV/VMVN/VORR/VBIC. */
13367 neon_write_immbits (unsigned immbits
)
13369 inst
.instruction
|= immbits
& 0xf;
13370 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13371 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13374 /* Invert low-order SIZE bits of XHI:XLO. */
13377 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13379 unsigned immlo
= xlo
? *xlo
: 0;
13380 unsigned immhi
= xhi
? *xhi
: 0;
13385 immlo
= (~immlo
) & 0xff;
13389 immlo
= (~immlo
) & 0xffff;
13393 immhi
= (~immhi
) & 0xffffffff;
13394 /* fall through. */
13397 immlo
= (~immlo
) & 0xffffffff;
13412 do_neon_logic (void)
13414 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13416 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13417 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13418 /* U bit and size field were set as part of the bitmask. */
13419 NEON_ENCODE (INTEGER
, inst
);
13420 neon_three_same (neon_quad (rs
), 0, -1);
13424 const int three_ops_form
= (inst
.operands
[2].present
13425 && !inst
.operands
[2].isreg
);
13426 const int immoperand
= (three_ops_form
? 2 : 1);
13427 enum neon_shape rs
= (three_ops_form
13428 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13429 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13430 struct neon_type_el et
= neon_check_type (2, rs
,
13431 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13432 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13436 if (et
.type
== NT_invtype
)
13439 if (three_ops_form
)
13440 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13441 _("first and second operands shall be the same register"));
13443 NEON_ENCODE (IMMED
, inst
);
13445 immbits
= inst
.operands
[immoperand
].imm
;
13448 /* .i64 is a pseudo-op, so the immediate must be a repeating
13450 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13451 inst
.operands
[immoperand
].reg
: 0))
13453 /* Set immbits to an invalid constant. */
13454 immbits
= 0xdeadbeef;
13461 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13465 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13469 /* Pseudo-instruction for VBIC. */
13470 neon_invert_size (&immbits
, 0, et
.size
);
13471 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13475 /* Pseudo-instruction for VORR. */
13476 neon_invert_size (&immbits
, 0, et
.size
);
13477 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13487 inst
.instruction
|= neon_quad (rs
) << 6;
13488 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13489 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13490 inst
.instruction
|= cmode
<< 8;
13491 neon_write_immbits (immbits
);
13493 neon_dp_fixup (&inst
);
13498 do_neon_bitfield (void)
13500 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13501 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13502 neon_three_same (neon_quad (rs
), 0, -1);
13506 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13509 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13510 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13512 if (et
.type
== NT_float
)
13514 NEON_ENCODE (FLOAT
, inst
);
13515 neon_three_same (neon_quad (rs
), 0, -1);
13519 NEON_ENCODE (INTEGER
, inst
);
13520 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13525 do_neon_dyadic_if_su (void)
13527 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13531 do_neon_dyadic_if_su_d (void)
13533 /* This version only allow D registers, but that constraint is enforced during
13534 operand parsing so we don't need to do anything extra here. */
13535 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13539 do_neon_dyadic_if_i_d (void)
13541 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13542 affected if we specify unsigned args. */
13543 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13546 enum vfp_or_neon_is_neon_bits
13549 NEON_CHECK_ARCH
= 2
13552 /* Call this function if an instruction which may have belonged to the VFP or
13553 Neon instruction sets, but turned out to be a Neon instruction (due to the
13554 operand types involved, etc.). We have to check and/or fix-up a couple of
13557 - Make sure the user hasn't attempted to make a Neon instruction
13559 - Alter the value in the condition code field if necessary.
13560 - Make sure that the arch supports Neon instructions.
13562 Which of these operations take place depends on bits from enum
13563 vfp_or_neon_is_neon_bits.
13565 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13566 current instruction's condition is COND_ALWAYS, the condition field is
13567 changed to inst.uncond_value. This is necessary because instructions shared
13568 between VFP and Neon may be conditional for the VFP variants only, and the
13569 unconditional Neon version must have, e.g., 0xF in the condition field. */
13572 vfp_or_neon_is_neon (unsigned check
)
13574 /* Conditions are always legal in Thumb mode (IT blocks). */
13575 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13577 if (inst
.cond
!= COND_ALWAYS
)
13579 first_error (_(BAD_COND
));
13582 if (inst
.uncond_value
!= -1)
13583 inst
.instruction
|= inst
.uncond_value
<< 28;
13586 if ((check
& NEON_CHECK_ARCH
)
13587 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13589 first_error (_(BAD_FPU
));
13597 do_neon_addsub_if_i (void)
13599 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13602 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13605 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13606 affected if we specify unsigned args. */
13607 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13610 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13612 V<op> A,B (A is operand 0, B is operand 2)
13617 so handle that case specially. */
13620 neon_exchange_operands (void)
13622 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13623 if (inst
.operands
[1].present
)
13625 /* Swap operands[1] and operands[2]. */
13626 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13627 inst
.operands
[1] = inst
.operands
[2];
13628 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13632 inst
.operands
[1] = inst
.operands
[2];
13633 inst
.operands
[2] = inst
.operands
[0];
13638 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13640 if (inst
.operands
[2].isreg
)
13643 neon_exchange_operands ();
13644 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13648 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13649 struct neon_type_el et
= neon_check_type (2, rs
,
13650 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13652 NEON_ENCODE (IMMED
, inst
);
13653 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13654 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13655 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13656 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13657 inst
.instruction
|= neon_quad (rs
) << 6;
13658 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13659 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13661 neon_dp_fixup (&inst
);
13668 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13672 do_neon_cmp_inv (void)
13674 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13680 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13683 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13684 scalars, which are encoded in 5 bits, M : Rm.
13685 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13686 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13690 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13692 unsigned regno
= NEON_SCALAR_REG (scalar
);
13693 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13698 if (regno
> 7 || elno
> 3)
13700 return regno
| (elno
<< 3);
13703 if (regno
> 15 || elno
> 1)
13705 return regno
| (elno
<< 4);
13709 first_error (_("scalar out of range for multiply instruction"));
13715 /* Encode multiply / multiply-accumulate scalar instructions. */
13718 neon_mul_mac (struct neon_type_el et
, int ubit
)
13722 /* Give a more helpful error message if we have an invalid type. */
13723 if (et
.type
== NT_invtype
)
13726 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13727 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13728 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13729 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13730 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13731 inst
.instruction
|= LOW4 (scalar
);
13732 inst
.instruction
|= HI1 (scalar
) << 5;
13733 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13734 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13735 inst
.instruction
|= (ubit
!= 0) << 24;
13737 neon_dp_fixup (&inst
);
13741 do_neon_mac_maybe_scalar (void)
13743 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13746 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13749 if (inst
.operands
[2].isscalar
)
13751 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13752 struct neon_type_el et
= neon_check_type (3, rs
,
13753 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13754 NEON_ENCODE (SCALAR
, inst
);
13755 neon_mul_mac (et
, neon_quad (rs
));
13759 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13760 affected if we specify unsigned args. */
13761 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13766 do_neon_fmac (void)
13768 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13771 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13774 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13780 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13781 struct neon_type_el et
= neon_check_type (3, rs
,
13782 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13783 neon_three_same (neon_quad (rs
), 0, et
.size
);
13786 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13787 same types as the MAC equivalents. The polynomial type for this instruction
13788 is encoded the same as the integer type. */
13793 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13796 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13799 if (inst
.operands
[2].isscalar
)
13800 do_neon_mac_maybe_scalar ();
13802 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13806 do_neon_qdmulh (void)
13808 if (inst
.operands
[2].isscalar
)
13810 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13811 struct neon_type_el et
= neon_check_type (3, rs
,
13812 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13813 NEON_ENCODE (SCALAR
, inst
);
13814 neon_mul_mac (et
, neon_quad (rs
));
13818 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13819 struct neon_type_el et
= neon_check_type (3, rs
,
13820 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13821 NEON_ENCODE (INTEGER
, inst
);
13822 /* The U bit (rounding) comes from bit mask. */
13823 neon_three_same (neon_quad (rs
), 0, et
.size
);
13828 do_neon_fcmp_absolute (void)
13830 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13831 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13832 /* Size field comes from bit mask. */
13833 neon_three_same (neon_quad (rs
), 1, -1);
13837 do_neon_fcmp_absolute_inv (void)
13839 neon_exchange_operands ();
13840 do_neon_fcmp_absolute ();
13844 do_neon_step (void)
13846 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13847 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13848 neon_three_same (neon_quad (rs
), 0, -1);
13852 do_neon_abs_neg (void)
13854 enum neon_shape rs
;
13855 struct neon_type_el et
;
13857 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13860 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13863 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13864 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13866 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13867 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13868 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13869 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13870 inst
.instruction
|= neon_quad (rs
) << 6;
13871 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13872 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13874 neon_dp_fixup (&inst
);
13880 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13881 struct neon_type_el et
= neon_check_type (2, rs
,
13882 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13883 int imm
= inst
.operands
[2].imm
;
13884 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13885 _("immediate out of range for insert"));
13886 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13892 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13893 struct neon_type_el et
= neon_check_type (2, rs
,
13894 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13895 int imm
= inst
.operands
[2].imm
;
13896 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13897 _("immediate out of range for insert"));
13898 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13902 do_neon_qshlu_imm (void)
13904 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13905 struct neon_type_el et
= neon_check_type (2, rs
,
13906 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13907 int imm
= inst
.operands
[2].imm
;
13908 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13909 _("immediate out of range for shift"));
13910 /* Only encodes the 'U present' variant of the instruction.
13911 In this case, signed types have OP (bit 8) set to 0.
13912 Unsigned types have OP set to 1. */
13913 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13914 /* The rest of the bits are the same as other immediate shifts. */
13915 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13919 do_neon_qmovn (void)
13921 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13922 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13923 /* Saturating move where operands can be signed or unsigned, and the
13924 destination has the same signedness. */
13925 NEON_ENCODE (INTEGER
, inst
);
13926 if (et
.type
== NT_unsigned
)
13927 inst
.instruction
|= 0xc0;
13929 inst
.instruction
|= 0x80;
13930 neon_two_same (0, 1, et
.size
/ 2);
13934 do_neon_qmovun (void)
13936 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13937 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13938 /* Saturating move with unsigned results. Operands must be signed. */
13939 NEON_ENCODE (INTEGER
, inst
);
13940 neon_two_same (0, 1, et
.size
/ 2);
13944 do_neon_rshift_sat_narrow (void)
13946 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13947 or unsigned. If operands are unsigned, results must also be unsigned. */
13948 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13949 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13950 int imm
= inst
.operands
[2].imm
;
13951 /* This gets the bounds check, size encoding and immediate bits calculation
13955 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13956 VQMOVN.I<size> <Dd>, <Qm>. */
13959 inst
.operands
[2].present
= 0;
13960 inst
.instruction
= N_MNEM_vqmovn
;
13965 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13966 _("immediate out of range"));
13967 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13971 do_neon_rshift_sat_narrow_u (void)
13973 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13974 or unsigned. If operands are unsigned, results must also be unsigned. */
13975 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13976 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13977 int imm
= inst
.operands
[2].imm
;
13978 /* This gets the bounds check, size encoding and immediate bits calculation
13982 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13983 VQMOVUN.I<size> <Dd>, <Qm>. */
13986 inst
.operands
[2].present
= 0;
13987 inst
.instruction
= N_MNEM_vqmovun
;
13992 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13993 _("immediate out of range"));
13994 /* FIXME: The manual is kind of unclear about what value U should have in
13995 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13997 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14001 do_neon_movn (void)
14003 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14004 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14005 NEON_ENCODE (INTEGER
, inst
);
14006 neon_two_same (0, 1, et
.size
/ 2);
14010 do_neon_rshift_narrow (void)
14012 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14013 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14014 int imm
= inst
.operands
[2].imm
;
14015 /* This gets the bounds check, size encoding and immediate bits calculation
14019 /* If immediate is zero then we are a pseudo-instruction for
14020 VMOVN.I<size> <Dd>, <Qm> */
14023 inst
.operands
[2].present
= 0;
14024 inst
.instruction
= N_MNEM_vmovn
;
14029 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14030 _("immediate out of range for narrowing operation"));
14031 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14035 do_neon_shll (void)
14037 /* FIXME: Type checking when lengthening. */
14038 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14039 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14040 unsigned imm
= inst
.operands
[2].imm
;
14042 if (imm
== et
.size
)
14044 /* Maximum shift variant. */
14045 NEON_ENCODE (INTEGER
, inst
);
14046 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14047 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14048 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14049 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14050 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14052 neon_dp_fixup (&inst
);
14056 /* A more-specific type check for non-max versions. */
14057 et
= neon_check_type (2, NS_QDI
,
14058 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14059 NEON_ENCODE (IMMED
, inst
);
14060 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14064 /* Check the various types for the VCVT instruction, and return which version
14065 the current instruction is. */
14068 neon_cvt_flavour (enum neon_shape rs
)
14070 #define CVT_VAR(C,X,Y) \
14071 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14072 if (et.type != NT_invtype) \
14074 inst.error = NULL; \
14077 struct neon_type_el et
;
14078 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14079 || rs
== NS_FF
) ? N_VFP
: 0;
14080 /* The instruction versions which take an immediate take one register
14081 argument, which is extended to the width of the full register. Thus the
14082 "source" and "destination" registers must have the same width. Hack that
14083 here by making the size equal to the key (wider, in this case) operand. */
14084 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14086 CVT_VAR (0, N_S32
, N_F32
);
14087 CVT_VAR (1, N_U32
, N_F32
);
14088 CVT_VAR (2, N_F32
, N_S32
);
14089 CVT_VAR (3, N_F32
, N_U32
);
14090 /* Half-precision conversions. */
14091 CVT_VAR (4, N_F32
, N_F16
);
14092 CVT_VAR (5, N_F16
, N_F32
);
14096 /* VFP instructions. */
14097 CVT_VAR (6, N_F32
, N_F64
);
14098 CVT_VAR (7, N_F64
, N_F32
);
14099 CVT_VAR (8, N_S32
, N_F64
| key
);
14100 CVT_VAR (9, N_U32
, N_F64
| key
);
14101 CVT_VAR (10, N_F64
| key
, N_S32
);
14102 CVT_VAR (11, N_F64
| key
, N_U32
);
14103 /* VFP instructions with bitshift. */
14104 CVT_VAR (12, N_F32
| key
, N_S16
);
14105 CVT_VAR (13, N_F32
| key
, N_U16
);
14106 CVT_VAR (14, N_F64
| key
, N_S16
);
14107 CVT_VAR (15, N_F64
| key
, N_U16
);
14108 CVT_VAR (16, N_S16
, N_F32
| key
);
14109 CVT_VAR (17, N_U16
, N_F32
| key
);
14110 CVT_VAR (18, N_S16
, N_F64
| key
);
14111 CVT_VAR (19, N_U16
, N_F64
| key
);
14117 /* Neon-syntax VFP conversions. */
14120 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14122 const char *opname
= 0;
14124 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14126 /* Conversions with immediate bitshift. */
14127 const char *enc
[] =
14151 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14153 opname
= enc
[flavour
];
14154 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14155 _("operands 0 and 1 must be the same register"));
14156 inst
.operands
[1] = inst
.operands
[2];
14157 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14162 /* Conversions without bitshift. */
14163 const char *enc
[] =
14179 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14180 opname
= enc
[flavour
];
14184 do_vfp_nsyn_opcode (opname
);
14188 do_vfp_nsyn_cvtz (void)
14190 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14191 int flavour
= neon_cvt_flavour (rs
);
14192 const char *enc
[] =
14206 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14207 do_vfp_nsyn_opcode (enc
[flavour
]);
14211 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14213 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14214 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14215 int flavour
= neon_cvt_flavour (rs
);
14217 /* PR11109: Handle round-to-zero for VCVT conversions. */
14219 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14220 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14221 && (rs
== NS_FD
|| rs
== NS_FF
))
14223 do_vfp_nsyn_cvtz ();
14227 /* VFP rather than Neon conversions. */
14230 do_vfp_nsyn_cvt (rs
, flavour
);
14240 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14242 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14245 /* Fixed-point conversion with #0 immediate is encoded as an
14246 integer conversion. */
14247 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14249 immbits
= 32 - inst
.operands
[2].imm
;
14250 NEON_ENCODE (IMMED
, inst
);
14252 inst
.instruction
|= enctab
[flavour
];
14253 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14254 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14257 inst
.instruction
|= neon_quad (rs
) << 6;
14258 inst
.instruction
|= 1 << 21;
14259 inst
.instruction
|= immbits
<< 16;
14261 neon_dp_fixup (&inst
);
14269 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14271 NEON_ENCODE (INTEGER
, inst
);
14273 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14277 inst
.instruction
|= enctab
[flavour
];
14279 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14280 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14281 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14282 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14283 inst
.instruction
|= neon_quad (rs
) << 6;
14284 inst
.instruction
|= 2 << 18;
14286 neon_dp_fixup (&inst
);
14290 /* Half-precision conversions for Advanced SIMD -- neon. */
14295 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14297 as_bad (_("operand size must match register width"));
14302 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14304 as_bad (_("operand size must match register width"));
14309 inst
.instruction
= 0x3b60600;
14311 inst
.instruction
= 0x3b60700;
14313 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14314 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14315 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14316 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14317 neon_dp_fixup (&inst
);
14321 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14322 do_vfp_nsyn_cvt (rs
, flavour
);
14327 do_neon_cvtr (void)
14329 do_neon_cvt_1 (FALSE
);
14335 do_neon_cvt_1 (TRUE
);
14339 do_neon_cvtb (void)
14341 inst
.instruction
= 0xeb20a40;
14343 /* The sizes are attached to the mnemonic. */
14344 if (inst
.vectype
.el
[0].type
!= NT_invtype
14345 && inst
.vectype
.el
[0].size
== 16)
14346 inst
.instruction
|= 0x00010000;
14348 /* Programmer's syntax: the sizes are attached to the operands. */
14349 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14350 && inst
.operands
[0].vectype
.size
== 16)
14351 inst
.instruction
|= 0x00010000;
14353 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14354 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14355 do_vfp_cond_or_thumb ();
14360 do_neon_cvtt (void)
14363 inst
.instruction
|= 0x80;
14367 neon_move_immediate (void)
14369 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14370 struct neon_type_el et
= neon_check_type (2, rs
,
14371 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14372 unsigned immlo
, immhi
= 0, immbits
;
14373 int op
, cmode
, float_p
;
14375 constraint (et
.type
== NT_invtype
,
14376 _("operand size must be specified for immediate VMOV"));
14378 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14379 op
= (inst
.instruction
& (1 << 5)) != 0;
14381 immlo
= inst
.operands
[1].imm
;
14382 if (inst
.operands
[1].regisimm
)
14383 immhi
= inst
.operands
[1].reg
;
14385 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14386 _("immediate has bits set outside the operand size"));
14388 float_p
= inst
.operands
[1].immisfloat
;
14390 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14391 et
.size
, et
.type
)) == FAIL
)
14393 /* Invert relevant bits only. */
14394 neon_invert_size (&immlo
, &immhi
, et
.size
);
14395 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14396 with one or the other; those cases are caught by
14397 neon_cmode_for_move_imm. */
14399 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14400 &op
, et
.size
, et
.type
)) == FAIL
)
14402 first_error (_("immediate out of range"));
14407 inst
.instruction
&= ~(1 << 5);
14408 inst
.instruction
|= op
<< 5;
14410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14411 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14412 inst
.instruction
|= neon_quad (rs
) << 6;
14413 inst
.instruction
|= cmode
<< 8;
14415 neon_write_immbits (immbits
);
14421 if (inst
.operands
[1].isreg
)
14423 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14425 NEON_ENCODE (INTEGER
, inst
);
14426 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14427 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14428 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14429 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14430 inst
.instruction
|= neon_quad (rs
) << 6;
14434 NEON_ENCODE (IMMED
, inst
);
14435 neon_move_immediate ();
14438 neon_dp_fixup (&inst
);
14441 /* Encode instructions of form:
14443 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14444 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14447 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14449 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14450 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14451 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14453 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14454 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14455 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14456 inst
.instruction
|= neon_logbits (size
) << 20;
14458 neon_dp_fixup (&inst
);
14462 do_neon_dyadic_long (void)
14464 /* FIXME: Type checking for lengthening op. */
14465 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14466 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14467 neon_mixed_length (et
, et
.size
);
14471 do_neon_abal (void)
14473 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14474 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14475 neon_mixed_length (et
, et
.size
);
14479 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14481 if (inst
.operands
[2].isscalar
)
14483 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14484 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14485 NEON_ENCODE (SCALAR
, inst
);
14486 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14490 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14491 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14492 NEON_ENCODE (INTEGER
, inst
);
14493 neon_mixed_length (et
, et
.size
);
14498 do_neon_mac_maybe_scalar_long (void)
14500 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14504 do_neon_dyadic_wide (void)
14506 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14507 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14508 neon_mixed_length (et
, et
.size
);
14512 do_neon_dyadic_narrow (void)
14514 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14515 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14516 /* Operand sign is unimportant, and the U bit is part of the opcode,
14517 so force the operand type to integer. */
14518 et
.type
= NT_integer
;
14519 neon_mixed_length (et
, et
.size
/ 2);
14523 do_neon_mul_sat_scalar_long (void)
14525 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14529 do_neon_vmull (void)
14531 if (inst
.operands
[2].isscalar
)
14532 do_neon_mac_maybe_scalar_long ();
14535 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14536 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14537 if (et
.type
== NT_poly
)
14538 NEON_ENCODE (POLY
, inst
);
14540 NEON_ENCODE (INTEGER
, inst
);
14541 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14542 zero. Should be OK as-is. */
14543 neon_mixed_length (et
, et
.size
);
14550 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14551 struct neon_type_el et
= neon_check_type (3, rs
,
14552 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14553 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14555 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14556 _("shift out of range"));
14557 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14558 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14559 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14560 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14561 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14562 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14563 inst
.instruction
|= neon_quad (rs
) << 6;
14564 inst
.instruction
|= imm
<< 8;
14566 neon_dp_fixup (&inst
);
14572 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14573 struct neon_type_el et
= neon_check_type (2, rs
,
14574 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14575 unsigned op
= (inst
.instruction
>> 7) & 3;
14576 /* N (width of reversed regions) is encoded as part of the bitmask. We
14577 extract it here to check the elements to be reversed are smaller.
14578 Otherwise we'd get a reserved instruction. */
14579 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14580 gas_assert (elsize
!= 0);
14581 constraint (et
.size
>= elsize
,
14582 _("elements must be smaller than reversal region"));
14583 neon_two_same (neon_quad (rs
), 1, et
.size
);
14589 if (inst
.operands
[1].isscalar
)
14591 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14592 struct neon_type_el et
= neon_check_type (2, rs
,
14593 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14594 unsigned sizebits
= et
.size
>> 3;
14595 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14596 int logsize
= neon_logbits (et
.size
);
14597 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14599 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14602 NEON_ENCODE (SCALAR
, inst
);
14603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14605 inst
.instruction
|= LOW4 (dm
);
14606 inst
.instruction
|= HI1 (dm
) << 5;
14607 inst
.instruction
|= neon_quad (rs
) << 6;
14608 inst
.instruction
|= x
<< 17;
14609 inst
.instruction
|= sizebits
<< 16;
14611 neon_dp_fixup (&inst
);
14615 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14616 struct neon_type_el et
= neon_check_type (2, rs
,
14617 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14618 /* Duplicate ARM register to lanes of vector. */
14619 NEON_ENCODE (ARMREG
, inst
);
14622 case 8: inst
.instruction
|= 0x400000; break;
14623 case 16: inst
.instruction
|= 0x000020; break;
14624 case 32: inst
.instruction
|= 0x000000; break;
14627 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14628 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14629 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14630 inst
.instruction
|= neon_quad (rs
) << 21;
14631 /* The encoding for this instruction is identical for the ARM and Thumb
14632 variants, except for the condition field. */
14633 do_vfp_cond_or_thumb ();
14637 /* VMOV has particularly many variations. It can be one of:
14638 0. VMOV<c><q> <Qd>, <Qm>
14639 1. VMOV<c><q> <Dd>, <Dm>
14640 (Register operations, which are VORR with Rm = Rn.)
14641 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14642 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14644 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14645 (ARM register to scalar.)
14646 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14647 (Two ARM registers to vector.)
14648 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14649 (Scalar to ARM register.)
14650 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14651 (Vector to two ARM registers.)
14652 8. VMOV.F32 <Sd>, <Sm>
14653 9. VMOV.F64 <Dd>, <Dm>
14654 (VFP register moves.)
14655 10. VMOV.F32 <Sd>, #imm
14656 11. VMOV.F64 <Dd>, #imm
14657 (VFP float immediate load.)
14658 12. VMOV <Rd>, <Sm>
14659 (VFP single to ARM reg.)
14660 13. VMOV <Sd>, <Rm>
14661 (ARM reg to VFP single.)
14662 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14663 (Two ARM regs to two VFP singles.)
14664 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14665 (Two VFP singles to two ARM regs.)
14667 These cases can be disambiguated using neon_select_shape, except cases 1/9
14668 and 3/11 which depend on the operand type too.
14670 All the encoded bits are hardcoded by this function.
14672 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14673 Cases 5, 7 may be used with VFPv2 and above.
14675 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14676 can specify a type where it doesn't make sense to, and is ignored). */
14681 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14682 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14684 struct neon_type_el et
;
14685 const char *ldconst
= 0;
14689 case NS_DD
: /* case 1/9. */
14690 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14691 /* It is not an error here if no type is given. */
14693 if (et
.type
== NT_float
&& et
.size
== 64)
14695 do_vfp_nsyn_opcode ("fcpyd");
14698 /* fall through. */
14700 case NS_QQ
: /* case 0/1. */
14702 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14704 /* The architecture manual I have doesn't explicitly state which
14705 value the U bit should have for register->register moves, but
14706 the equivalent VORR instruction has U = 0, so do that. */
14707 inst
.instruction
= 0x0200110;
14708 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14709 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14710 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14711 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14714 inst
.instruction
|= neon_quad (rs
) << 6;
14716 neon_dp_fixup (&inst
);
14720 case NS_DI
: /* case 3/11. */
14721 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14723 if (et
.type
== NT_float
&& et
.size
== 64)
14725 /* case 11 (fconstd). */
14726 ldconst
= "fconstd";
14727 goto encode_fconstd
;
14729 /* fall through. */
14731 case NS_QI
: /* case 2/3. */
14732 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14734 inst
.instruction
= 0x0800010;
14735 neon_move_immediate ();
14736 neon_dp_fixup (&inst
);
14739 case NS_SR
: /* case 4. */
14741 unsigned bcdebits
= 0;
14743 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14744 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14746 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14747 logsize
= neon_logbits (et
.size
);
14749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14752 && et
.size
!= 32, _(BAD_FPU
));
14753 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14754 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14758 case 8: bcdebits
= 0x8; break;
14759 case 16: bcdebits
= 0x1; break;
14760 case 32: bcdebits
= 0x0; break;
14764 bcdebits
|= x
<< logsize
;
14766 inst
.instruction
= 0xe000b10;
14767 do_vfp_cond_or_thumb ();
14768 inst
.instruction
|= LOW4 (dn
) << 16;
14769 inst
.instruction
|= HI1 (dn
) << 7;
14770 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14771 inst
.instruction
|= (bcdebits
& 3) << 5;
14772 inst
.instruction
|= (bcdebits
>> 2) << 21;
14776 case NS_DRR
: /* case 5 (fmdrr). */
14777 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14780 inst
.instruction
= 0xc400b10;
14781 do_vfp_cond_or_thumb ();
14782 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14783 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14784 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14785 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14788 case NS_RS
: /* case 6. */
14791 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14792 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14793 unsigned abcdebits
= 0;
14795 et
= neon_check_type (2, NS_NULL
,
14796 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14797 logsize
= neon_logbits (et
.size
);
14799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14802 && et
.size
!= 32, _(BAD_FPU
));
14803 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14804 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14808 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14809 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14810 case 32: abcdebits
= 0x00; break;
14814 abcdebits
|= x
<< logsize
;
14815 inst
.instruction
= 0xe100b10;
14816 do_vfp_cond_or_thumb ();
14817 inst
.instruction
|= LOW4 (dn
) << 16;
14818 inst
.instruction
|= HI1 (dn
) << 7;
14819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14820 inst
.instruction
|= (abcdebits
& 3) << 5;
14821 inst
.instruction
|= (abcdebits
>> 2) << 21;
14825 case NS_RRD
: /* case 7 (fmrrd). */
14826 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14829 inst
.instruction
= 0xc500b10;
14830 do_vfp_cond_or_thumb ();
14831 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14832 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14833 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14834 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14837 case NS_FF
: /* case 8 (fcpys). */
14838 do_vfp_nsyn_opcode ("fcpys");
14841 case NS_FI
: /* case 10 (fconsts). */
14842 ldconst
= "fconsts";
14844 if (is_quarter_float (inst
.operands
[1].imm
))
14846 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14847 do_vfp_nsyn_opcode (ldconst
);
14850 first_error (_("immediate out of range"));
14853 case NS_RF
: /* case 12 (fmrs). */
14854 do_vfp_nsyn_opcode ("fmrs");
14857 case NS_FR
: /* case 13 (fmsr). */
14858 do_vfp_nsyn_opcode ("fmsr");
14861 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14862 (one of which is a list), but we have parsed four. Do some fiddling to
14863 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14865 case NS_RRFF
: /* case 14 (fmrrs). */
14866 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14867 _("VFP registers must be adjacent"));
14868 inst
.operands
[2].imm
= 2;
14869 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14870 do_vfp_nsyn_opcode ("fmrrs");
14873 case NS_FFRR
: /* case 15 (fmsrr). */
14874 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14875 _("VFP registers must be adjacent"));
14876 inst
.operands
[1] = inst
.operands
[2];
14877 inst
.operands
[2] = inst
.operands
[3];
14878 inst
.operands
[0].imm
= 2;
14879 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14880 do_vfp_nsyn_opcode ("fmsrr");
14889 do_neon_rshift_round_imm (void)
14891 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14892 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14893 int imm
= inst
.operands
[2].imm
;
14895 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14898 inst
.operands
[2].present
= 0;
14903 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14904 _("immediate out of range for shift"));
14905 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14910 do_neon_movl (void)
14912 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14913 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14914 unsigned sizebits
= et
.size
>> 3;
14915 inst
.instruction
|= sizebits
<< 19;
14916 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14922 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14923 struct neon_type_el et
= neon_check_type (2, rs
,
14924 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14925 NEON_ENCODE (INTEGER
, inst
);
14926 neon_two_same (neon_quad (rs
), 1, et
.size
);
14930 do_neon_zip_uzp (void)
14932 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14933 struct neon_type_el et
= neon_check_type (2, rs
,
14934 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14935 if (rs
== NS_DD
&& et
.size
== 32)
14937 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14938 inst
.instruction
= N_MNEM_vtrn
;
14942 neon_two_same (neon_quad (rs
), 1, et
.size
);
14946 do_neon_sat_abs_neg (void)
14948 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14949 struct neon_type_el et
= neon_check_type (2, rs
,
14950 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14951 neon_two_same (neon_quad (rs
), 1, et
.size
);
14955 do_neon_pair_long (void)
14957 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14958 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14959 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14960 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14961 neon_two_same (neon_quad (rs
), 1, et
.size
);
14965 do_neon_recip_est (void)
14967 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14968 struct neon_type_el et
= neon_check_type (2, rs
,
14969 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14970 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14971 neon_two_same (neon_quad (rs
), 1, et
.size
);
14977 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14978 struct neon_type_el et
= neon_check_type (2, rs
,
14979 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14980 neon_two_same (neon_quad (rs
), 1, et
.size
);
14986 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14987 struct neon_type_el et
= neon_check_type (2, rs
,
14988 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14989 neon_two_same (neon_quad (rs
), 1, et
.size
);
14995 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14996 struct neon_type_el et
= neon_check_type (2, rs
,
14997 N_EQK
| N_INT
, N_8
| N_KEY
);
14998 neon_two_same (neon_quad (rs
), 1, et
.size
);
15004 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15005 neon_two_same (neon_quad (rs
), 1, -1);
15009 do_neon_tbl_tbx (void)
15011 unsigned listlenbits
;
15012 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15014 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15016 first_error (_("bad list length for table lookup"));
15020 listlenbits
= inst
.operands
[1].imm
- 1;
15021 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15022 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15023 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15024 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15025 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15026 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15027 inst
.instruction
|= listlenbits
<< 8;
15029 neon_dp_fixup (&inst
);
15033 do_neon_ldm_stm (void)
15035 /* P, U and L bits are part of bitmask. */
15036 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15037 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15039 if (inst
.operands
[1].issingle
)
15041 do_vfp_nsyn_ldm_stm (is_dbmode
);
15045 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15046 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15048 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15049 _("register list must contain at least 1 and at most 16 "
15052 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15053 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15055 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15057 inst
.instruction
|= offsetbits
;
15059 do_vfp_cond_or_thumb ();
15063 do_neon_ldr_str (void)
15065 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15067 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15068 And is UNPREDICTABLE in thumb mode. */
15070 && inst
.operands
[1].reg
== REG_PC
15071 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15073 if (!thumb_mode
&& warn_on_deprecated
)
15074 as_warn (_("Use of PC here is deprecated"));
15076 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15079 if (inst
.operands
[0].issingle
)
15082 do_vfp_nsyn_opcode ("flds");
15084 do_vfp_nsyn_opcode ("fsts");
15089 do_vfp_nsyn_opcode ("fldd");
15091 do_vfp_nsyn_opcode ("fstd");
15095 /* "interleave" version also handles non-interleaving register VLD1/VST1
15099 do_neon_ld_st_interleave (void)
15101 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15102 N_8
| N_16
| N_32
| N_64
);
15103 unsigned alignbits
= 0;
15105 /* The bits in this table go:
15106 0: register stride of one (0) or two (1)
15107 1,2: register list length, minus one (1, 2, 3, 4).
15108 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15109 We use -1 for invalid entries. */
15110 const int typetable
[] =
15112 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15113 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15114 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15115 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15119 if (et
.type
== NT_invtype
)
15122 if (inst
.operands
[1].immisalign
)
15123 switch (inst
.operands
[1].imm
>> 8)
15125 case 64: alignbits
= 1; break;
15127 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15128 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15129 goto bad_alignment
;
15133 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15134 goto bad_alignment
;
15139 first_error (_("bad alignment"));
15143 inst
.instruction
|= alignbits
<< 4;
15144 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15146 /* Bits [4:6] of the immediate in a list specifier encode register stride
15147 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15148 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15149 up the right value for "type" in a table based on this value and the given
15150 list style, then stick it back. */
15151 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15152 | (((inst
.instruction
>> 8) & 3) << 3);
15154 typebits
= typetable
[idx
];
15156 constraint (typebits
== -1, _("bad list type for instruction"));
15158 inst
.instruction
&= ~0xf00;
15159 inst
.instruction
|= typebits
<< 8;
15162 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15163 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15164 otherwise. The variable arguments are a list of pairs of legal (size, align)
15165 values, terminated with -1. */
15168 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15171 int result
= FAIL
, thissize
, thisalign
;
15173 if (!inst
.operands
[1].immisalign
)
15179 va_start (ap
, do_align
);
15183 thissize
= va_arg (ap
, int);
15184 if (thissize
== -1)
15186 thisalign
= va_arg (ap
, int);
15188 if (size
== thissize
&& align
== thisalign
)
15191 while (result
!= SUCCESS
);
15195 if (result
== SUCCESS
)
15198 first_error (_("unsupported alignment for instruction"));
15204 do_neon_ld_st_lane (void)
15206 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15207 int align_good
, do_align
= 0;
15208 int logsize
= neon_logbits (et
.size
);
15209 int align
= inst
.operands
[1].imm
>> 8;
15210 int n
= (inst
.instruction
>> 8) & 3;
15211 int max_el
= 64 / et
.size
;
15213 if (et
.type
== NT_invtype
)
15216 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15217 _("bad list length"));
15218 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15219 _("scalar index out of range"));
15220 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15222 _("stride of 2 unavailable when element size is 8"));
15226 case 0: /* VLD1 / VST1. */
15227 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15229 if (align_good
== FAIL
)
15233 unsigned alignbits
= 0;
15236 case 16: alignbits
= 0x1; break;
15237 case 32: alignbits
= 0x3; break;
15240 inst
.instruction
|= alignbits
<< 4;
15244 case 1: /* VLD2 / VST2. */
15245 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15247 if (align_good
== FAIL
)
15250 inst
.instruction
|= 1 << 4;
15253 case 2: /* VLD3 / VST3. */
15254 constraint (inst
.operands
[1].immisalign
,
15255 _("can't use alignment with this instruction"));
15258 case 3: /* VLD4 / VST4. */
15259 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15260 16, 64, 32, 64, 32, 128, -1);
15261 if (align_good
== FAIL
)
15265 unsigned alignbits
= 0;
15268 case 8: alignbits
= 0x1; break;
15269 case 16: alignbits
= 0x1; break;
15270 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15273 inst
.instruction
|= alignbits
<< 4;
15280 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15281 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15282 inst
.instruction
|= 1 << (4 + logsize
);
15284 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15285 inst
.instruction
|= logsize
<< 10;
15288 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15291 do_neon_ld_dup (void)
15293 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15294 int align_good
, do_align
= 0;
15296 if (et
.type
== NT_invtype
)
15299 switch ((inst
.instruction
>> 8) & 3)
15301 case 0: /* VLD1. */
15302 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15303 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15304 &do_align
, 16, 16, 32, 32, -1);
15305 if (align_good
== FAIL
)
15307 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15310 case 2: inst
.instruction
|= 1 << 5; break;
15311 default: first_error (_("bad list length")); return;
15313 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15316 case 1: /* VLD2. */
15317 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15318 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15319 if (align_good
== FAIL
)
15321 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15322 _("bad list length"));
15323 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15324 inst
.instruction
|= 1 << 5;
15325 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15328 case 2: /* VLD3. */
15329 constraint (inst
.operands
[1].immisalign
,
15330 _("can't use alignment with this instruction"));
15331 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15332 _("bad list length"));
15333 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15334 inst
.instruction
|= 1 << 5;
15335 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15338 case 3: /* VLD4. */
15340 int align
= inst
.operands
[1].imm
>> 8;
15341 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15342 16, 64, 32, 64, 32, 128, -1);
15343 if (align_good
== FAIL
)
15345 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15346 _("bad list length"));
15347 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15348 inst
.instruction
|= 1 << 5;
15349 if (et
.size
== 32 && align
== 128)
15350 inst
.instruction
|= 0x3 << 6;
15352 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15359 inst
.instruction
|= do_align
<< 4;
15362 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15363 apart from bits [11:4]. */
15366 do_neon_ldx_stx (void)
15368 if (inst
.operands
[1].isreg
)
15369 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15371 switch (NEON_LANE (inst
.operands
[0].imm
))
15373 case NEON_INTERLEAVE_LANES
:
15374 NEON_ENCODE (INTERLV
, inst
);
15375 do_neon_ld_st_interleave ();
15378 case NEON_ALL_LANES
:
15379 NEON_ENCODE (DUP
, inst
);
15384 NEON_ENCODE (LANE
, inst
);
15385 do_neon_ld_st_lane ();
15388 /* L bit comes from bit mask. */
15389 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15390 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15391 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15393 if (inst
.operands
[1].postind
)
15395 int postreg
= inst
.operands
[1].imm
& 0xf;
15396 constraint (!inst
.operands
[1].immisreg
,
15397 _("post-index must be a register"));
15398 constraint (postreg
== 0xd || postreg
== 0xf,
15399 _("bad register for post-index"));
15400 inst
.instruction
|= postreg
;
15402 else if (inst
.operands
[1].writeback
)
15404 inst
.instruction
|= 0xd;
15407 inst
.instruction
|= 0xf;
15410 inst
.instruction
|= 0xf9000000;
15412 inst
.instruction
|= 0xf4000000;
15415 /* Overall per-instruction processing. */
15417 /* We need to be able to fix up arbitrary expressions in some statements.
15418 This is so that we can handle symbols that are an arbitrary distance from
15419 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15420 which returns part of an address in a form which will be valid for
15421 a data instruction. We do this by pushing the expression into a symbol
15422 in the expr_section, and creating a fix for that. */
15425 fix_new_arm (fragS
* frag
,
15440 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15441 (enum bfd_reloc_code_real
) reloc
);
15445 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15446 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15450 /* Mark whether the fix is to a THUMB instruction, or an ARM
15452 new_fix
->tc_fix_data
= thumb_mode
;
15455 /* Create a frg for an instruction requiring relaxation. */
15457 output_relax_insn (void)
15463 /* The size of the instruction is unknown, so tie the debug info to the
15464 start of the instruction. */
15465 dwarf2_emit_insn (0);
15467 switch (inst
.reloc
.exp
.X_op
)
15470 sym
= inst
.reloc
.exp
.X_add_symbol
;
15471 offset
= inst
.reloc
.exp
.X_add_number
;
15475 offset
= inst
.reloc
.exp
.X_add_number
;
15478 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15482 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15483 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15484 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15487 /* Write a 32-bit thumb instruction to buf. */
15489 put_thumb32_insn (char * buf
, unsigned long insn
)
15491 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15492 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15496 output_inst (const char * str
)
15502 as_bad ("%s -- `%s'", inst
.error
, str
);
15507 output_relax_insn ();
15510 if (inst
.size
== 0)
15513 to
= frag_more (inst
.size
);
15514 /* PR 9814: Record the thumb mode into the current frag so that we know
15515 what type of NOP padding to use, if necessary. We override any previous
15516 setting so that if the mode has changed then the NOPS that we use will
15517 match the encoding of the last instruction in the frag. */
15518 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15520 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15522 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15523 put_thumb32_insn (to
, inst
.instruction
);
15525 else if (inst
.size
> INSN_SIZE
)
15527 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15528 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15529 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15532 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15534 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15535 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15536 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15539 dwarf2_emit_insn (inst
.size
);
15543 output_it_inst (int cond
, int mask
, char * to
)
15545 unsigned long instruction
= 0xbf00;
15548 instruction
|= mask
;
15549 instruction
|= cond
<< 4;
15553 to
= frag_more (2);
15555 dwarf2_emit_insn (2);
15559 md_number_to_chars (to
, instruction
, 2);
15564 /* Tag values used in struct asm_opcode's tag field. */
15567 OT_unconditional
, /* Instruction cannot be conditionalized.
15568 The ARM condition field is still 0xE. */
15569 OT_unconditionalF
, /* Instruction cannot be conditionalized
15570 and carries 0xF in its ARM condition field. */
15571 OT_csuffix
, /* Instruction takes a conditional suffix. */
15572 OT_csuffixF
, /* Some forms of the instruction take a conditional
15573 suffix, others place 0xF where the condition field
15575 OT_cinfix3
, /* Instruction takes a conditional infix,
15576 beginning at character index 3. (In
15577 unified mode, it becomes a suffix.) */
15578 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15579 tsts, cmps, cmns, and teqs. */
15580 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15581 character index 3, even in unified mode. Used for
15582 legacy instructions where suffix and infix forms
15583 may be ambiguous. */
15584 OT_csuf_or_in3
, /* Instruction takes either a conditional
15585 suffix or an infix at character index 3. */
15586 OT_odd_infix_unc
, /* This is the unconditional variant of an
15587 instruction that takes a conditional infix
15588 at an unusual position. In unified mode,
15589 this variant will accept a suffix. */
15590 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15591 are the conditional variants of instructions that
15592 take conditional infixes in unusual positions.
15593 The infix appears at character index
15594 (tag - OT_odd_infix_0). These are not accepted
15595 in unified mode. */
15598 /* Subroutine of md_assemble, responsible for looking up the primary
15599 opcode from the mnemonic the user wrote. STR points to the
15600 beginning of the mnemonic.
15602 This is not simply a hash table lookup, because of conditional
15603 variants. Most instructions have conditional variants, which are
15604 expressed with a _conditional affix_ to the mnemonic. If we were
15605 to encode each conditional variant as a literal string in the opcode
15606 table, it would have approximately 20,000 entries.
15608 Most mnemonics take this affix as a suffix, and in unified syntax,
15609 'most' is upgraded to 'all'. However, in the divided syntax, some
15610 instructions take the affix as an infix, notably the s-variants of
15611 the arithmetic instructions. Of those instructions, all but six
15612 have the infix appear after the third character of the mnemonic.
15614 Accordingly, the algorithm for looking up primary opcodes given
15617 1. Look up the identifier in the opcode table.
15618 If we find a match, go to step U.
15620 2. Look up the last two characters of the identifier in the
15621 conditions table. If we find a match, look up the first N-2
15622 characters of the identifier in the opcode table. If we
15623 find a match, go to step CE.
15625 3. Look up the fourth and fifth characters of the identifier in
15626 the conditions table. If we find a match, extract those
15627 characters from the identifier, and look up the remaining
15628 characters in the opcode table. If we find a match, go
15633 U. Examine the tag field of the opcode structure, in case this is
15634 one of the six instructions with its conditional infix in an
15635 unusual place. If it is, the tag tells us where to find the
15636 infix; look it up in the conditions table and set inst.cond
15637 accordingly. Otherwise, this is an unconditional instruction.
15638 Again set inst.cond accordingly. Return the opcode structure.
15640 CE. Examine the tag field to make sure this is an instruction that
15641 should receive a conditional suffix. If it is not, fail.
15642 Otherwise, set inst.cond from the suffix we already looked up,
15643 and return the opcode structure.
15645 CM. Examine the tag field to make sure this is an instruction that
15646 should receive a conditional infix after the third character.
15647 If it is not, fail. Otherwise, undo the edits to the current
15648 line of input and proceed as for case CE. */
15650 static const struct asm_opcode
*
15651 opcode_lookup (char **str
)
15655 const struct asm_opcode
*opcode
;
15656 const struct asm_cond
*cond
;
15659 /* Scan up to the end of the mnemonic, which must end in white space,
15660 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15661 for (base
= end
= *str
; *end
!= '\0'; end
++)
15662 if (*end
== ' ' || *end
== '.')
15668 /* Handle a possible width suffix and/or Neon type suffix. */
15673 /* The .w and .n suffixes are only valid if the unified syntax is in
15675 if (unified_syntax
&& end
[1] == 'w')
15677 else if (unified_syntax
&& end
[1] == 'n')
15682 inst
.vectype
.elems
= 0;
15684 *str
= end
+ offset
;
15686 if (end
[offset
] == '.')
15688 /* See if we have a Neon type suffix (possible in either unified or
15689 non-unified ARM syntax mode). */
15690 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15693 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15699 /* Look for unaffixed or special-case affixed mnemonic. */
15700 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15705 if (opcode
->tag
< OT_odd_infix_0
)
15707 inst
.cond
= COND_ALWAYS
;
15711 if (warn_on_deprecated
&& unified_syntax
)
15712 as_warn (_("conditional infixes are deprecated in unified syntax"));
15713 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15714 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15717 inst
.cond
= cond
->value
;
15721 /* Cannot have a conditional suffix on a mnemonic of less than two
15723 if (end
- base
< 3)
15726 /* Look for suffixed mnemonic. */
15728 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15729 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15731 if (opcode
&& cond
)
15734 switch (opcode
->tag
)
15736 case OT_cinfix3_legacy
:
15737 /* Ignore conditional suffixes matched on infix only mnemonics. */
15741 case OT_cinfix3_deprecated
:
15742 case OT_odd_infix_unc
:
15743 if (!unified_syntax
)
15745 /* else fall through */
15749 case OT_csuf_or_in3
:
15750 inst
.cond
= cond
->value
;
15753 case OT_unconditional
:
15754 case OT_unconditionalF
:
15756 inst
.cond
= cond
->value
;
15759 /* Delayed diagnostic. */
15760 inst
.error
= BAD_COND
;
15761 inst
.cond
= COND_ALWAYS
;
15770 /* Cannot have a usual-position infix on a mnemonic of less than
15771 six characters (five would be a suffix). */
15772 if (end
- base
< 6)
15775 /* Look for infixed mnemonic in the usual position. */
15777 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15781 memcpy (save
, affix
, 2);
15782 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15783 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15785 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15786 memcpy (affix
, save
, 2);
15789 && (opcode
->tag
== OT_cinfix3
15790 || opcode
->tag
== OT_cinfix3_deprecated
15791 || opcode
->tag
== OT_csuf_or_in3
15792 || opcode
->tag
== OT_cinfix3_legacy
))
15795 if (warn_on_deprecated
&& unified_syntax
15796 && (opcode
->tag
== OT_cinfix3
15797 || opcode
->tag
== OT_cinfix3_deprecated
))
15798 as_warn (_("conditional infixes are deprecated in unified syntax"));
15800 inst
.cond
= cond
->value
;
15807 /* This function generates an initial IT instruction, leaving its block
15808 virtually open for the new instructions. Eventually,
15809 the mask will be updated by now_it_add_mask () each time
15810 a new instruction needs to be included in the IT block.
15811 Finally, the block is closed with close_automatic_it_block ().
15812 The block closure can be requested either from md_assemble (),
15813 a tencode (), or due to a label hook. */
15816 new_automatic_it_block (int cond
)
15818 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15819 now_it
.mask
= 0x18;
15821 now_it
.block_length
= 1;
15822 mapping_state (MAP_THUMB
);
15823 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15826 /* Close an automatic IT block.
15827 See comments in new_automatic_it_block (). */
15830 close_automatic_it_block (void)
15832 now_it
.mask
= 0x10;
15833 now_it
.block_length
= 0;
15836 /* Update the mask of the current automatically-generated IT
15837 instruction. See comments in new_automatic_it_block (). */
15840 now_it_add_mask (int cond
)
15842 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15843 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15844 | ((bitvalue) << (nbit)))
15845 const int resulting_bit
= (cond
& 1);
15847 now_it
.mask
&= 0xf;
15848 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15850 (5 - now_it
.block_length
));
15851 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15853 ((5 - now_it
.block_length
) - 1) );
15854 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15857 #undef SET_BIT_VALUE
15860 /* The IT blocks handling machinery is accessed through the these functions:
15861 it_fsm_pre_encode () from md_assemble ()
15862 set_it_insn_type () optional, from the tencode functions
15863 set_it_insn_type_last () ditto
15864 in_it_block () ditto
15865 it_fsm_post_encode () from md_assemble ()
15866 force_automatic_it_block_close () from label habdling functions
15869 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15870 initializing the IT insn type with a generic initial value depending
15871 on the inst.condition.
15872 2) During the tencode function, two things may happen:
15873 a) The tencode function overrides the IT insn type by
15874 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15875 b) The tencode function queries the IT block state by
15876 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15878 Both set_it_insn_type and in_it_block run the internal FSM state
15879 handling function (handle_it_state), because: a) setting the IT insn
15880 type may incur in an invalid state (exiting the function),
15881 and b) querying the state requires the FSM to be updated.
15882 Specifically we want to avoid creating an IT block for conditional
15883 branches, so it_fsm_pre_encode is actually a guess and we can't
15884 determine whether an IT block is required until the tencode () routine
15885 has decided what type of instruction this actually it.
15886 Because of this, if set_it_insn_type and in_it_block have to be used,
15887 set_it_insn_type has to be called first.
15889 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15890 determines the insn IT type depending on the inst.cond code.
15891 When a tencode () routine encodes an instruction that can be
15892 either outside an IT block, or, in the case of being inside, has to be
15893 the last one, set_it_insn_type_last () will determine the proper
15894 IT instruction type based on the inst.cond code. Otherwise,
15895 set_it_insn_type can be called for overriding that logic or
15896 for covering other cases.
15898 Calling handle_it_state () may not transition the IT block state to
15899 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15900 still queried. Instead, if the FSM determines that the state should
15901 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15902 after the tencode () function: that's what it_fsm_post_encode () does.
15904 Since in_it_block () calls the state handling function to get an
15905 updated state, an error may occur (due to invalid insns combination).
15906 In that case, inst.error is set.
15907 Therefore, inst.error has to be checked after the execution of
15908 the tencode () routine.
15910 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15911 any pending state change (if any) that didn't take place in
15912 handle_it_state () as explained above. */
15915 it_fsm_pre_encode (void)
15917 if (inst
.cond
!= COND_ALWAYS
)
15918 inst
.it_insn_type
= INSIDE_IT_INSN
;
15920 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15922 now_it
.state_handled
= 0;
15925 /* IT state FSM handling function. */
15928 handle_it_state (void)
15930 now_it
.state_handled
= 1;
15932 switch (now_it
.state
)
15934 case OUTSIDE_IT_BLOCK
:
15935 switch (inst
.it_insn_type
)
15937 case OUTSIDE_IT_INSN
:
15940 case INSIDE_IT_INSN
:
15941 case INSIDE_IT_LAST_INSN
:
15942 if (thumb_mode
== 0)
15945 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15946 as_tsktsk (_("Warning: conditional outside an IT block"\
15951 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15952 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15954 /* Automatically generate the IT instruction. */
15955 new_automatic_it_block (inst
.cond
);
15956 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15957 close_automatic_it_block ();
15961 inst
.error
= BAD_OUT_IT
;
15967 case IF_INSIDE_IT_LAST_INSN
:
15968 case NEUTRAL_IT_INSN
:
15972 now_it
.state
= MANUAL_IT_BLOCK
;
15973 now_it
.block_length
= 0;
15978 case AUTOMATIC_IT_BLOCK
:
15979 /* Three things may happen now:
15980 a) We should increment current it block size;
15981 b) We should close current it block (closing insn or 4 insns);
15982 c) We should close current it block and start a new one (due
15983 to incompatible conditions or
15984 4 insns-length block reached). */
15986 switch (inst
.it_insn_type
)
15988 case OUTSIDE_IT_INSN
:
15989 /* The closure of the block shall happen immediatelly,
15990 so any in_it_block () call reports the block as closed. */
15991 force_automatic_it_block_close ();
15994 case INSIDE_IT_INSN
:
15995 case INSIDE_IT_LAST_INSN
:
15996 case IF_INSIDE_IT_LAST_INSN
:
15997 now_it
.block_length
++;
15999 if (now_it
.block_length
> 4
16000 || !now_it_compatible (inst
.cond
))
16002 force_automatic_it_block_close ();
16003 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16004 new_automatic_it_block (inst
.cond
);
16008 now_it_add_mask (inst
.cond
);
16011 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16012 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16013 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16014 close_automatic_it_block ();
16017 case NEUTRAL_IT_INSN
:
16018 now_it
.block_length
++;
16020 if (now_it
.block_length
> 4)
16021 force_automatic_it_block_close ();
16023 now_it_add_mask (now_it
.cc
& 1);
16027 close_automatic_it_block ();
16028 now_it
.state
= MANUAL_IT_BLOCK
;
16033 case MANUAL_IT_BLOCK
:
16035 /* Check conditional suffixes. */
16036 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16039 now_it
.mask
&= 0x1f;
16040 is_last
= (now_it
.mask
== 0x10);
16042 switch (inst
.it_insn_type
)
16044 case OUTSIDE_IT_INSN
:
16045 inst
.error
= BAD_NOT_IT
;
16048 case INSIDE_IT_INSN
:
16049 if (cond
!= inst
.cond
)
16051 inst
.error
= BAD_IT_COND
;
16056 case INSIDE_IT_LAST_INSN
:
16057 case IF_INSIDE_IT_LAST_INSN
:
16058 if (cond
!= inst
.cond
)
16060 inst
.error
= BAD_IT_COND
;
16065 inst
.error
= BAD_BRANCH
;
16070 case NEUTRAL_IT_INSN
:
16071 /* The BKPT instruction is unconditional even in an IT block. */
16075 inst
.error
= BAD_IT_IT
;
16086 it_fsm_post_encode (void)
16090 if (!now_it
.state_handled
)
16091 handle_it_state ();
16093 is_last
= (now_it
.mask
== 0x10);
16096 now_it
.state
= OUTSIDE_IT_BLOCK
;
16102 force_automatic_it_block_close (void)
16104 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16106 close_automatic_it_block ();
16107 now_it
.state
= OUTSIDE_IT_BLOCK
;
16115 if (!now_it
.state_handled
)
16116 handle_it_state ();
16118 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16122 md_assemble (char *str
)
16125 const struct asm_opcode
* opcode
;
16127 /* Align the previous label if needed. */
16128 if (last_label_seen
!= NULL
)
16130 symbol_set_frag (last_label_seen
, frag_now
);
16131 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16132 S_SET_SEGMENT (last_label_seen
, now_seg
);
16135 memset (&inst
, '\0', sizeof (inst
));
16136 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16138 opcode
= opcode_lookup (&p
);
16141 /* It wasn't an instruction, but it might be a register alias of
16142 the form alias .req reg, or a Neon .dn/.qn directive. */
16143 if (! create_register_alias (str
, p
)
16144 && ! create_neon_reg_alias (str
, p
))
16145 as_bad (_("bad instruction `%s'"), str
);
16150 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16151 as_warn (_("s suffix on comparison instruction is deprecated"));
16153 /* The value which unconditional instructions should have in place of the
16154 condition field. */
16155 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16159 arm_feature_set variant
;
16161 variant
= cpu_variant
;
16162 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16163 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16164 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16165 /* Check that this instruction is supported for this CPU. */
16166 if (!opcode
->tvariant
16167 || (thumb_mode
== 1
16168 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16170 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16173 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16174 && opcode
->tencode
!= do_t_branch
)
16176 as_bad (_("Thumb does not support conditional execution"));
16180 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16182 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16183 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16184 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16186 /* Two things are addressed here.
16187 1) Implicit require narrow instructions on Thumb-1.
16188 This avoids relaxation accidentally introducing Thumb-2
16190 2) Reject wide instructions in non Thumb-2 cores. */
16191 if (inst
.size_req
== 0)
16193 else if (inst
.size_req
== 4)
16195 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16201 inst
.instruction
= opcode
->tvalue
;
16203 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16205 /* Prepare the it_insn_type for those encodings that don't set
16207 it_fsm_pre_encode ();
16209 opcode
->tencode ();
16211 it_fsm_post_encode ();
16214 if (!(inst
.error
|| inst
.relax
))
16216 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16217 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16218 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16220 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16225 /* Something has gone badly wrong if we try to relax a fixed size
16227 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16229 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16230 *opcode
->tvariant
);
16231 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16232 set those bits when Thumb-2 32-bit instructions are seen. ie.
16233 anything other than bl/blx and v6-M instructions.
16234 This is overly pessimistic for relaxable instructions. */
16235 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16237 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16238 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16239 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16242 check_neon_suffixes
;
16246 mapping_state (MAP_THUMB
);
16249 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16253 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16254 is_bx
= (opcode
->aencode
== do_bx
);
16256 /* Check that this instruction is supported for this CPU. */
16257 if (!(is_bx
&& fix_v4bx
)
16258 && !(opcode
->avariant
&&
16259 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16261 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16266 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16270 inst
.instruction
= opcode
->avalue
;
16271 if (opcode
->tag
== OT_unconditionalF
)
16272 inst
.instruction
|= 0xF << 28;
16274 inst
.instruction
|= inst
.cond
<< 28;
16275 inst
.size
= INSN_SIZE
;
16276 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16278 it_fsm_pre_encode ();
16279 opcode
->aencode ();
16280 it_fsm_post_encode ();
16282 /* Arm mode bx is marked as both v4T and v5 because it's still required
16283 on a hypothetical non-thumb v5 core. */
16285 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16287 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16288 *opcode
->avariant
);
16290 check_neon_suffixes
;
16294 mapping_state (MAP_ARM
);
16299 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16307 check_it_blocks_finished (void)
16312 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16313 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16314 == MANUAL_IT_BLOCK
)
16316 as_warn (_("section '%s' finished with an open IT block."),
16320 if (now_it
.state
== MANUAL_IT_BLOCK
)
16321 as_warn (_("file finished with an open IT block."));
16325 /* Various frobbings of labels and their addresses. */
16328 arm_start_line_hook (void)
16330 last_label_seen
= NULL
;
16334 arm_frob_label (symbolS
* sym
)
16336 last_label_seen
= sym
;
16338 ARM_SET_THUMB (sym
, thumb_mode
);
16340 #if defined OBJ_COFF || defined OBJ_ELF
16341 ARM_SET_INTERWORK (sym
, support_interwork
);
16344 force_automatic_it_block_close ();
16346 /* Note - do not allow local symbols (.Lxxx) to be labelled
16347 as Thumb functions. This is because these labels, whilst
16348 they exist inside Thumb code, are not the entry points for
16349 possible ARM->Thumb calls. Also, these labels can be used
16350 as part of a computed goto or switch statement. eg gcc
16351 can generate code that looks like this:
16353 ldr r2, [pc, .Laaa]
16363 The first instruction loads the address of the jump table.
16364 The second instruction converts a table index into a byte offset.
16365 The third instruction gets the jump address out of the table.
16366 The fourth instruction performs the jump.
16368 If the address stored at .Laaa is that of a symbol which has the
16369 Thumb_Func bit set, then the linker will arrange for this address
16370 to have the bottom bit set, which in turn would mean that the
16371 address computation performed by the third instruction would end
16372 up with the bottom bit set. Since the ARM is capable of unaligned
16373 word loads, the instruction would then load the incorrect address
16374 out of the jump table, and chaos would ensue. */
16375 if (label_is_thumb_function_name
16376 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16377 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16379 /* When the address of a Thumb function is taken the bottom
16380 bit of that address should be set. This will allow
16381 interworking between Arm and Thumb functions to work
16384 THUMB_SET_FUNC (sym
, 1);
16386 label_is_thumb_function_name
= FALSE
;
16389 dwarf2_emit_label (sym
);
16393 arm_data_in_code (void)
16395 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16397 *input_line_pointer
= '/';
16398 input_line_pointer
+= 5;
16399 *input_line_pointer
= 0;
16407 arm_canonicalize_symbol_name (char * name
)
16411 if (thumb_mode
&& (len
= strlen (name
)) > 5
16412 && streq (name
+ len
- 5, "/data"))
16413 *(name
+ len
- 5) = 0;
16418 /* Table of all register names defined by default. The user can
16419 define additional names with .req. Note that all register names
16420 should appear in both upper and lowercase variants. Some registers
16421 also have mixed-case names. */
16423 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16424 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16425 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16426 #define REGSET(p,t) \
16427 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16428 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16429 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16430 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16431 #define REGSETH(p,t) \
16432 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16433 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16434 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16435 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16436 #define REGSET2(p,t) \
16437 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16438 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16439 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16440 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16441 #define SPLRBANK(base,bank,t) \
16442 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16443 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16444 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16445 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16446 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16447 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16449 static const struct reg_entry reg_names
[] =
16451 /* ARM integer registers. */
16452 REGSET(r
, RN
), REGSET(R
, RN
),
16454 /* ATPCS synonyms. */
16455 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16456 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16457 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16459 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16460 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16461 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16463 /* Well-known aliases. */
16464 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16465 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16467 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16468 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16470 /* Coprocessor numbers. */
16471 REGSET(p
, CP
), REGSET(P
, CP
),
16473 /* Coprocessor register numbers. The "cr" variants are for backward
16475 REGSET(c
, CN
), REGSET(C
, CN
),
16476 REGSET(cr
, CN
), REGSET(CR
, CN
),
16478 /* ARM banked registers. */
16479 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16480 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16481 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16482 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16483 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16484 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16485 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16487 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16488 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16489 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16490 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16491 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16492 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16493 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16494 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16496 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16497 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16498 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16499 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16500 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16501 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16502 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16503 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16504 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16506 /* FPA registers. */
16507 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16508 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16510 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16511 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16513 /* VFP SP registers. */
16514 REGSET(s
,VFS
), REGSET(S
,VFS
),
16515 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16517 /* VFP DP Registers. */
16518 REGSET(d
,VFD
), REGSET(D
,VFD
),
16519 /* Extra Neon DP registers. */
16520 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16522 /* Neon QP registers. */
16523 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16525 /* VFP control registers. */
16526 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16527 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16528 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16529 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16530 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16531 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16533 /* Maverick DSP coprocessor registers. */
16534 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16535 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16537 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16538 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16539 REGDEF(dspsc
,0,DSPSC
),
16541 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16542 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16543 REGDEF(DSPSC
,0,DSPSC
),
16545 /* iWMMXt data registers - p0, c0-15. */
16546 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16548 /* iWMMXt control registers - p1, c0-3. */
16549 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16550 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16551 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16552 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16554 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16555 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16556 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16557 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16558 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16560 /* XScale accumulator registers. */
16561 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16567 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16568 within psr_required_here. */
16569 static const struct asm_psr psrs
[] =
16571 /* Backward compatibility notation. Note that "all" is no longer
16572 truly all possible PSR bits. */
16573 {"all", PSR_c
| PSR_f
},
16577 /* Individual flags. */
16583 /* Combinations of flags. */
16584 {"fs", PSR_f
| PSR_s
},
16585 {"fx", PSR_f
| PSR_x
},
16586 {"fc", PSR_f
| PSR_c
},
16587 {"sf", PSR_s
| PSR_f
},
16588 {"sx", PSR_s
| PSR_x
},
16589 {"sc", PSR_s
| PSR_c
},
16590 {"xf", PSR_x
| PSR_f
},
16591 {"xs", PSR_x
| PSR_s
},
16592 {"xc", PSR_x
| PSR_c
},
16593 {"cf", PSR_c
| PSR_f
},
16594 {"cs", PSR_c
| PSR_s
},
16595 {"cx", PSR_c
| PSR_x
},
16596 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16597 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16598 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16599 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16600 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16601 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16602 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16603 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16604 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16605 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16606 {"scf", PSR_s
| PSR_c
| PSR_f
},
16607 {"scx", PSR_s
| PSR_c
| PSR_x
},
16608 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16609 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16610 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16611 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16612 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16613 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16614 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16615 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16616 {"csf", PSR_c
| PSR_s
| PSR_f
},
16617 {"csx", PSR_c
| PSR_s
| PSR_x
},
16618 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16619 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16620 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16621 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16622 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16623 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16624 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16625 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16626 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16627 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16628 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16629 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16630 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16631 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16632 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16633 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16634 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16635 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16636 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16637 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16638 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16639 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16640 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16641 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16642 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16643 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16646 /* Table of V7M psr names. */
16647 static const struct asm_psr v7m_psrs
[] =
16649 {"apsr", 0 }, {"APSR", 0 },
16650 {"iapsr", 1 }, {"IAPSR", 1 },
16651 {"eapsr", 2 }, {"EAPSR", 2 },
16652 {"psr", 3 }, {"PSR", 3 },
16653 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16654 {"ipsr", 5 }, {"IPSR", 5 },
16655 {"epsr", 6 }, {"EPSR", 6 },
16656 {"iepsr", 7 }, {"IEPSR", 7 },
16657 {"msp", 8 }, {"MSP", 8 },
16658 {"psp", 9 }, {"PSP", 9 },
16659 {"primask", 16}, {"PRIMASK", 16},
16660 {"basepri", 17}, {"BASEPRI", 17},
16661 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16662 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16663 {"faultmask", 19}, {"FAULTMASK", 19},
16664 {"control", 20}, {"CONTROL", 20}
16667 /* Table of all shift-in-operand names. */
16668 static const struct asm_shift_name shift_names
[] =
16670 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16671 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16672 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16673 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16674 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16675 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16678 /* Table of all explicit relocation names. */
16680 static struct reloc_entry reloc_names
[] =
16682 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16683 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16684 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16685 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16686 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16687 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16688 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16689 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16690 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16691 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16692 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16693 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16694 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16695 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16696 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16697 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16698 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16699 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16703 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16704 static const struct asm_cond conds
[] =
16708 {"cs", 0x2}, {"hs", 0x2},
16709 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16723 static struct asm_barrier_opt barrier_opt_names
[] =
16725 { "sy", 0xf }, { "SY", 0xf },
16726 { "un", 0x7 }, { "UN", 0x7 },
16727 { "st", 0xe }, { "ST", 0xe },
16728 { "unst", 0x6 }, { "UNST", 0x6 },
16729 { "ish", 0xb }, { "ISH", 0xb },
16730 { "sh", 0xb }, { "SH", 0xb },
16731 { "ishst", 0xa }, { "ISHST", 0xa },
16732 { "shst", 0xa }, { "SHST", 0xa },
16733 { "nsh", 0x7 }, { "NSH", 0x7 },
16734 { "nshst", 0x6 }, { "NSHST", 0x6 },
16735 { "osh", 0x3 }, { "OSH", 0x3 },
16736 { "oshst", 0x2 }, { "OSHST", 0x2 }
16739 /* Table of ARM-format instructions. */
16741 /* Macros for gluing together operand strings. N.B. In all cases
16742 other than OPS0, the trailing OP_stop comes from default
16743 zero-initialization of the unspecified elements of the array. */
16744 #define OPS0() { OP_stop, }
16745 #define OPS1(a) { OP_##a, }
16746 #define OPS2(a,b) { OP_##a,OP_##b, }
16747 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16748 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16749 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16750 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16752 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16753 This is useful when mixing operands for ARM and THUMB, i.e. using the
16754 MIX_ARM_THUMB_OPERANDS macro.
16755 In order to use these macros, prefix the number of operands with _
16757 #define OPS_1(a) { a, }
16758 #define OPS_2(a,b) { a,b, }
16759 #define OPS_3(a,b,c) { a,b,c, }
16760 #define OPS_4(a,b,c,d) { a,b,c,d, }
16761 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16762 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16764 /* These macros abstract out the exact format of the mnemonic table and
16765 save some repeated characters. */
16767 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16768 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16769 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16770 THUMB_VARIANT, do_##ae, do_##te }
16772 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16773 a T_MNEM_xyz enumerator. */
16774 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16775 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16776 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16777 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16779 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16780 infix after the third character. */
16781 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16782 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16783 THUMB_VARIANT, do_##ae, do_##te }
16784 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16785 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16786 THUMB_VARIANT, do_##ae, do_##te }
16787 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16788 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16789 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16790 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16791 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16792 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16793 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16794 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16796 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16797 appear in the condition table. */
16798 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16799 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16800 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16802 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16803 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16804 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16805 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16806 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16807 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16808 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16809 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16810 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16811 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16812 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16813 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16814 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16815 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16816 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16817 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16818 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16819 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16820 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16821 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16823 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16824 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16825 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16826 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16828 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16829 field is still 0xE. Many of the Thumb variants can be executed
16830 conditionally, so this is checked separately. */
16831 #define TUE(mnem, op, top, nops, ops, ae, te) \
16832 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16833 THUMB_VARIANT, do_##ae, do_##te }
16835 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16836 condition code field. */
16837 #define TUF(mnem, op, top, nops, ops, ae, te) \
16838 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16839 THUMB_VARIANT, do_##ae, do_##te }
16841 /* ARM-only variants of all the above. */
16842 #define CE(mnem, op, nops, ops, ae) \
16843 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16845 #define C3(mnem, op, nops, ops, ae) \
16846 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16848 /* Legacy mnemonics that always have conditional infix after the third
16850 #define CL(mnem, op, nops, ops, ae) \
16851 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16852 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16854 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16855 #define cCE(mnem, op, nops, ops, ae) \
16856 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16858 /* Legacy coprocessor instructions where conditional infix and conditional
16859 suffix are ambiguous. For consistency this includes all FPA instructions,
16860 not just the potentially ambiguous ones. */
16861 #define cCL(mnem, op, nops, ops, ae) \
16862 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16863 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16865 /* Coprocessor, takes either a suffix or a position-3 infix
16866 (for an FPA corner case). */
16867 #define C3E(mnem, op, nops, ops, ae) \
16868 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16869 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16871 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16872 { m1 #m2 m3, OPS##nops ops, \
16873 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16874 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16876 #define CM(m1, m2, op, nops, ops, ae) \
16877 xCM_ (m1, , m2, op, nops, ops, ae), \
16878 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16879 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16880 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16881 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16882 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16883 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16884 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16885 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16886 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16887 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16888 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16889 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16890 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16891 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16892 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16893 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16894 xCM_ (m1, le, m2, op, nops, ops, ae), \
16895 xCM_ (m1, al, m2, op, nops, ops, ae)
16897 #define UE(mnem, op, nops, ops, ae) \
16898 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16900 #define UF(mnem, op, nops, ops, ae) \
16901 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16903 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16904 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16905 use the same encoding function for each. */
16906 #define NUF(mnem, op, nops, ops, enc) \
16907 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16908 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16910 /* Neon data processing, version which indirects through neon_enc_tab for
16911 the various overloaded versions of opcodes. */
16912 #define nUF(mnem, op, nops, ops, enc) \
16913 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16914 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16916 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16918 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16919 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16920 THUMB_VARIANT, do_##enc, do_##enc }
16922 #define NCE(mnem, op, nops, ops, enc) \
16923 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16925 #define NCEF(mnem, op, nops, ops, enc) \
16926 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16928 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16929 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16930 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16931 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16933 #define nCE(mnem, op, nops, ops, enc) \
16934 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16936 #define nCEF(mnem, op, nops, ops, enc) \
16937 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16941 static const struct asm_opcode insns
[] =
16943 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16944 #define THUMB_VARIANT &arm_ext_v4t
16945 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16946 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16947 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16948 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16949 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16950 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16951 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16952 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16953 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16954 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16955 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16956 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16957 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16958 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16959 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16960 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16962 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16963 for setting PSR flag bits. They are obsolete in V6 and do not
16964 have Thumb equivalents. */
16965 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16966 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16967 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16968 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16969 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16970 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16971 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16972 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16973 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16975 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16976 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16977 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16978 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16980 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16981 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16982 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16984 OP_ADDRGLDR
),ldst
, t_ldst
),
16985 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16987 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16988 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16989 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16990 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16991 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16992 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16994 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16995 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16996 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16997 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17000 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17001 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17002 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17004 /* Thumb-compatibility pseudo ops. */
17005 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17006 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17007 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17008 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17009 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17010 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17011 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17012 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17013 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17014 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17015 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17016 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17018 /* These may simplify to neg. */
17019 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17020 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17022 #undef THUMB_VARIANT
17023 #define THUMB_VARIANT & arm_ext_v6
17025 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17027 /* V1 instructions with no Thumb analogue prior to V6T2. */
17028 #undef THUMB_VARIANT
17029 #define THUMB_VARIANT & arm_ext_v6t2
17031 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17032 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17033 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17035 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17036 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17037 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17038 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17040 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17041 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17043 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17044 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17046 /* V1 instructions with no Thumb analogue at all. */
17047 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17048 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17050 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17051 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17052 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17053 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17054 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17055 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17056 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17057 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17060 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17061 #undef THUMB_VARIANT
17062 #define THUMB_VARIANT & arm_ext_v4t
17064 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17065 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17067 #undef THUMB_VARIANT
17068 #define THUMB_VARIANT & arm_ext_v6t2
17070 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17071 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17073 /* Generic coprocessor instructions. */
17074 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17075 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17076 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17077 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17078 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17079 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17080 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17083 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17085 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17086 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17089 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17090 #undef THUMB_VARIANT
17091 #define THUMB_VARIANT & arm_ext_msr
17093 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17094 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17097 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17098 #undef THUMB_VARIANT
17099 #define THUMB_VARIANT & arm_ext_v6t2
17101 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17102 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17103 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17104 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17105 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17106 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17107 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17108 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17111 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17112 #undef THUMB_VARIANT
17113 #define THUMB_VARIANT & arm_ext_v4t
17115 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17116 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17117 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17118 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17119 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17120 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17123 #define ARM_VARIANT & arm_ext_v4t_5
17125 /* ARM Architecture 4T. */
17126 /* Note: bx (and blx) are required on V5, even if the processor does
17127 not support Thumb. */
17128 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17131 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17132 #undef THUMB_VARIANT
17133 #define THUMB_VARIANT & arm_ext_v5t
17135 /* Note: blx has 2 variants; the .value coded here is for
17136 BLX(2). Only this variant has conditional execution. */
17137 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17138 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17140 #undef THUMB_VARIANT
17141 #define THUMB_VARIANT & arm_ext_v6t2
17143 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17144 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17145 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17146 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17147 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17148 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17149 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17150 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17153 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17154 #undef THUMB_VARIANT
17155 #define THUMB_VARIANT &arm_ext_v5exp
17157 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17158 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17159 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17160 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17162 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17163 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17165 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17166 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17167 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17168 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17170 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17171 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17172 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17173 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17175 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17176 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17178 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17179 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17180 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17181 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17184 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17185 #undef THUMB_VARIANT
17186 #define THUMB_VARIANT &arm_ext_v6t2
17188 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17189 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17191 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17192 ADDRGLDRS
), ldrd
, t_ldstd
),
17194 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17195 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17198 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17200 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17203 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17204 #undef THUMB_VARIANT
17205 #define THUMB_VARIANT & arm_ext_v6
17207 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17208 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17209 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17210 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17211 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17212 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17213 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17214 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17215 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17216 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17218 #undef THUMB_VARIANT
17219 #define THUMB_VARIANT & arm_ext_v6t2
17221 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17222 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17224 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17225 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17227 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17228 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17230 /* ARM V6 not included in V7M. */
17231 #undef THUMB_VARIANT
17232 #define THUMB_VARIANT & arm_ext_v6_notm
17233 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17234 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17235 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17236 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17237 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17238 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17239 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17240 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17241 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17242 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17243 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17244 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17246 /* ARM V6 not included in V7M (eg. integer SIMD). */
17247 #undef THUMB_VARIANT
17248 #define THUMB_VARIANT & arm_ext_v6_dsp
17249 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17250 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17251 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17252 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17253 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17254 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17255 /* Old name for QASX. */
17256 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17257 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17258 /* Old name for QSAX. */
17259 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17260 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17261 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17262 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17263 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17264 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17265 /* Old name for SASX. */
17266 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17267 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17268 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17269 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17270 /* Old name for SHASX. */
17271 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17272 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17273 /* Old name for SHSAX. */
17274 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17275 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17276 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17277 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17278 /* Old name for SSAX. */
17279 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17280 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17281 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17282 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17283 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17284 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17285 /* Old name for UASX. */
17286 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17287 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17288 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17289 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17290 /* Old name for UHASX. */
17291 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17292 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17293 /* Old name for UHSAX. */
17294 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17295 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17296 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17297 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17298 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17299 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17300 /* Old name for UQASX. */
17301 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17302 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17303 /* Old name for UQSAX. */
17304 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17305 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17306 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17307 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17308 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17309 /* Old name for USAX. */
17310 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17311 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17312 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17313 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17314 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17315 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17316 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17317 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17318 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17319 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17320 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17321 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17322 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17323 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17324 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17325 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17326 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17327 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17328 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17329 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17330 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17331 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17332 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17333 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17334 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17335 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17336 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17337 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17338 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17339 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17340 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17341 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17342 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17343 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17346 #define ARM_VARIANT & arm_ext_v6k
17347 #undef THUMB_VARIANT
17348 #define THUMB_VARIANT & arm_ext_v6k
17350 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17351 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17352 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17353 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17355 #undef THUMB_VARIANT
17356 #define THUMB_VARIANT & arm_ext_v6_notm
17357 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17359 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17360 RRnpcb
), strexd
, t_strexd
),
17362 #undef THUMB_VARIANT
17363 #define THUMB_VARIANT & arm_ext_v6t2
17364 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17366 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17368 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17370 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17372 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17375 #define ARM_VARIANT & arm_ext_sec
17376 #undef THUMB_VARIANT
17377 #define THUMB_VARIANT & arm_ext_sec
17379 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17382 #define ARM_VARIANT & arm_ext_virt
17383 #undef THUMB_VARIANT
17384 #define THUMB_VARIANT & arm_ext_virt
17386 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17387 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17390 #define ARM_VARIANT & arm_ext_v6t2
17391 #undef THUMB_VARIANT
17392 #define THUMB_VARIANT & arm_ext_v6t2
17394 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17395 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17396 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17397 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17399 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17400 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17401 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17402 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17404 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17405 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17406 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17407 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17409 /* Thumb-only instructions. */
17411 #define ARM_VARIANT NULL
17412 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17413 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17415 /* ARM does not really have an IT instruction, so always allow it.
17416 The opcode is copied from Thumb in order to allow warnings in
17417 -mimplicit-it=[never | arm] modes. */
17419 #define ARM_VARIANT & arm_ext_v1
17421 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17422 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17423 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17424 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17425 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17426 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17427 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17428 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17429 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17430 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17431 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17432 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17433 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17434 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17435 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17436 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17437 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17438 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17440 /* Thumb2 only instructions. */
17442 #define ARM_VARIANT NULL
17444 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17445 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17446 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17447 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17448 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17449 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17451 /* Hardware division instructions. */
17453 #define ARM_VARIANT & arm_ext_adiv
17454 #undef THUMB_VARIANT
17455 #define THUMB_VARIANT & arm_ext_div
17457 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17458 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17460 /* ARM V6M/V7 instructions. */
17462 #define ARM_VARIANT & arm_ext_barrier
17463 #undef THUMB_VARIANT
17464 #define THUMB_VARIANT & arm_ext_barrier
17466 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17467 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17468 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17470 /* ARM V7 instructions. */
17472 #define ARM_VARIANT & arm_ext_v7
17473 #undef THUMB_VARIANT
17474 #define THUMB_VARIANT & arm_ext_v7
17476 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17477 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17480 #define ARM_VARIANT & arm_ext_mp
17481 #undef THUMB_VARIANT
17482 #define THUMB_VARIANT & arm_ext_mp
17484 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17487 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17489 cCE("wfs", e200110
, 1, (RR
), rd
),
17490 cCE("rfs", e300110
, 1, (RR
), rd
),
17491 cCE("wfc", e400110
, 1, (RR
), rd
),
17492 cCE("rfc", e500110
, 1, (RR
), rd
),
17494 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17495 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17496 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17497 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17499 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17500 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17501 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17502 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17504 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17505 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17506 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17507 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17508 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17509 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17510 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17511 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17512 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17513 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17514 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17515 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17517 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17518 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17519 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17520 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17521 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17522 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17523 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17524 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17525 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17526 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17527 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17528 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17530 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17531 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17532 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17533 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17534 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17535 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17536 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17537 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17538 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17539 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17540 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17541 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17543 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17544 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17545 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17546 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17547 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17548 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17549 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17550 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17551 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17552 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17553 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17554 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17556 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17557 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17558 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17559 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17560 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17561 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17562 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17563 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17564 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17565 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17566 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17567 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17569 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17570 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17571 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17572 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17573 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17574 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17575 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17576 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17577 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17578 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17579 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17580 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17582 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17583 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17584 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17585 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17586 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17587 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17588 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17589 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17590 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17591 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17592 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17593 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17595 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17596 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17597 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17598 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17599 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17600 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17601 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17602 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17603 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17604 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17605 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17606 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17608 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17609 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17610 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17611 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17612 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17613 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17614 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17615 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17616 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17617 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17618 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17619 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17621 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17622 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17623 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17624 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17625 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17626 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17627 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17628 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17629 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17632 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17637 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17645 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17658 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17671 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17684 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17688 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17689 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17693 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17697 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17701 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17702 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17706 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17710 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17713 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17714 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17715 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17716 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17717 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17718 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17719 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17720 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17721 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17722 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17723 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17725 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17726 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17727 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17728 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17729 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17730 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17731 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17732 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17733 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17734 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17735 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17736 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17738 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17739 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17740 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17741 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17742 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17743 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17744 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17745 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17746 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17747 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17748 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17749 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17751 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17752 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17753 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17754 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17755 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17756 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17757 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17758 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17759 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17760 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17761 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17762 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17764 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17765 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17766 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17767 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17768 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17769 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17770 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17771 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17772 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17773 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17774 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17775 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17777 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17778 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17779 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17780 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17781 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17782 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17783 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17784 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17785 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17786 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17787 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17788 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17790 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17791 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17792 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17793 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17794 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17795 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17796 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17797 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17798 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17799 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17800 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17801 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17803 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17804 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17805 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17806 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17807 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17808 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17809 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17810 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17811 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17812 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17813 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17814 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17816 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17817 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17818 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17819 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17820 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17821 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17822 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17823 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17824 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17825 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17826 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17827 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17829 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17830 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17831 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17832 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17833 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17834 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17835 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17836 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17837 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17840 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17845 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17853 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17857 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17858 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17862 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17866 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17870 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17871 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17875 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17879 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17882 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17883 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17884 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17886 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17887 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17888 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17889 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17890 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17891 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17892 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17893 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17894 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17895 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17896 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17897 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17899 /* The implementation of the FIX instruction is broken on some
17900 assemblers, in that it accepts a precision specifier as well as a
17901 rounding specifier, despite the fact that this is meaningless.
17902 To be more compatible, we accept it as well, though of course it
17903 does not set any bits. */
17904 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17905 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17906 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17907 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17908 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17909 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17910 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17911 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17912 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17913 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17914 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17915 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17916 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17918 /* Instructions that were new with the real FPA, call them V2. */
17920 #define ARM_VARIANT & fpu_fpa_ext_v2
17922 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17923 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17924 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17925 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17926 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17927 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17930 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17932 /* Moves and type conversions. */
17933 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17934 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17935 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17936 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17937 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17938 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17939 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17940 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17941 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17942 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17943 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17944 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17945 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17946 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17948 /* Memory operations. */
17949 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17950 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17951 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17952 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17953 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17954 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17955 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17956 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17957 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17958 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17959 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17960 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17961 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17962 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17963 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17964 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17965 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17966 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17968 /* Monadic operations. */
17969 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17970 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17971 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17973 /* Dyadic operations. */
17974 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17975 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17976 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17977 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17978 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17979 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17980 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17981 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17982 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17985 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17986 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17987 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17988 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17990 /* Double precision load/store are still present on single precision
17991 implementations. */
17992 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17993 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17994 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17995 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17996 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17997 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17998 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17999 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18000 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18001 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18004 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18006 /* Moves and type conversions. */
18007 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18008 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18009 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18010 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18011 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18012 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18013 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18014 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18015 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18016 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18017 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18018 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18019 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18021 /* Monadic operations. */
18022 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18023 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18024 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18026 /* Dyadic operations. */
18027 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18028 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18029 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18030 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18031 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18032 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18033 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18034 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18035 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18038 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18039 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18040 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18041 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18044 #define ARM_VARIANT & fpu_vfp_ext_v2
18046 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18047 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18048 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18049 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18051 /* Instructions which may belong to either the Neon or VFP instruction sets.
18052 Individual encoder functions perform additional architecture checks. */
18054 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18055 #undef THUMB_VARIANT
18056 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18058 /* These mnemonics are unique to VFP. */
18059 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18060 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18061 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18062 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18063 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18064 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18065 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18066 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18067 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18068 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18070 /* Mnemonics shared by Neon and VFP. */
18071 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18072 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18073 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18075 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18076 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18078 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18079 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18081 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18082 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18083 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18084 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18085 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18086 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18087 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18088 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18090 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
18091 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18092 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18093 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18096 /* NOTE: All VMOV encoding is special-cased! */
18097 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18098 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18100 #undef THUMB_VARIANT
18101 #define THUMB_VARIANT & fpu_neon_ext_v1
18103 #define ARM_VARIANT & fpu_neon_ext_v1
18105 /* Data processing with three registers of the same length. */
18106 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18107 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18108 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18109 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18110 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18111 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18112 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18113 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18114 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18115 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18116 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18117 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18118 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18119 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18120 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18121 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18122 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18123 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18124 /* If not immediate, fall back to neon_dyadic_i64_su.
18125 shl_imm should accept I8 I16 I32 I64,
18126 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18127 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18128 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18129 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18130 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18131 /* Logic ops, types optional & ignored. */
18132 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18133 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18134 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18135 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18136 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18137 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18138 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18139 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18140 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18141 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18142 /* Bitfield ops, untyped. */
18143 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18144 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18145 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18146 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18147 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18148 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18149 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18150 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18151 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18152 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18153 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18154 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18155 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18156 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18157 back to neon_dyadic_if_su. */
18158 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18159 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18160 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18161 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18162 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18163 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18164 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18165 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18166 /* Comparison. Type I8 I16 I32 F32. */
18167 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18168 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18169 /* As above, D registers only. */
18170 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18171 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18172 /* Int and float variants, signedness unimportant. */
18173 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18174 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18175 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18176 /* Add/sub take types I8 I16 I32 I64 F32. */
18177 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18178 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18179 /* vtst takes sizes 8, 16, 32. */
18180 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18181 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18182 /* VMUL takes I8 I16 I32 F32 P8. */
18183 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18184 /* VQD{R}MULH takes S16 S32. */
18185 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18186 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18187 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18188 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18189 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18190 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18191 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18192 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18193 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18194 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18195 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18196 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18197 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18198 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18199 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18200 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18202 /* Two address, int/float. Types S8 S16 S32 F32. */
18203 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18204 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18206 /* Data processing with two registers and a shift amount. */
18207 /* Right shifts, and variants with rounding.
18208 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18209 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18210 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18211 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18212 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18213 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18214 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18215 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18216 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18217 /* Shift and insert. Sizes accepted 8 16 32 64. */
18218 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18219 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18220 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18221 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18222 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18223 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18224 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18225 /* Right shift immediate, saturating & narrowing, with rounding variants.
18226 Types accepted S16 S32 S64 U16 U32 U64. */
18227 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18228 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18229 /* As above, unsigned. Types accepted S16 S32 S64. */
18230 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18231 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18232 /* Right shift narrowing. Types accepted I16 I32 I64. */
18233 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18234 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18235 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18236 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18237 /* CVT with optional immediate for fixed-point variant. */
18238 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18240 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18241 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18243 /* Data processing, three registers of different lengths. */
18244 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18245 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18246 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18247 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18248 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18249 /* If not scalar, fall back to neon_dyadic_long.
18250 Vector types as above, scalar types S16 S32 U16 U32. */
18251 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18252 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18253 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18254 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18255 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18256 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18257 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18258 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18259 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18260 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18261 /* Saturating doubling multiplies. Types S16 S32. */
18262 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18263 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18264 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18265 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18266 S16 S32 U16 U32. */
18267 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18269 /* Extract. Size 8. */
18270 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18271 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18273 /* Two registers, miscellaneous. */
18274 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18275 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18276 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18277 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18278 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18279 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18280 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18281 /* Vector replicate. Sizes 8 16 32. */
18282 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18283 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18284 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18285 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18286 /* VMOVN. Types I16 I32 I64. */
18287 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18288 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18289 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18290 /* VQMOVUN. Types S16 S32 S64. */
18291 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18292 /* VZIP / VUZP. Sizes 8 16 32. */
18293 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18294 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18295 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18296 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18297 /* VQABS / VQNEG. Types S8 S16 S32. */
18298 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18299 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18300 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18301 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18302 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18303 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18304 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18305 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18306 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18307 /* Reciprocal estimates. Types U32 F32. */
18308 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18309 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18310 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18311 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18312 /* VCLS. Types S8 S16 S32. */
18313 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18314 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18315 /* VCLZ. Types I8 I16 I32. */
18316 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18317 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18318 /* VCNT. Size 8. */
18319 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18320 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18321 /* Two address, untyped. */
18322 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18323 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18324 /* VTRN. Sizes 8 16 32. */
18325 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18326 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18328 /* Table lookup. Size 8. */
18329 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18330 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18332 #undef THUMB_VARIANT
18333 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18335 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18337 /* Neon element/structure load/store. */
18338 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18339 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18340 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18341 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18342 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18343 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18344 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18345 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18347 #undef THUMB_VARIANT
18348 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18350 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18351 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18352 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18353 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18354 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18355 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18356 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18357 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18358 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18359 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18361 #undef THUMB_VARIANT
18362 #define THUMB_VARIANT & fpu_vfp_ext_v3
18364 #define ARM_VARIANT & fpu_vfp_ext_v3
18366 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18367 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18368 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18369 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18370 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18371 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18372 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18373 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18374 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18377 #define ARM_VARIANT &fpu_vfp_ext_fma
18378 #undef THUMB_VARIANT
18379 #define THUMB_VARIANT &fpu_vfp_ext_fma
18380 /* Mnemonics shared by Neon and VFP. These are included in the
18381 VFP FMA variant; NEON and VFP FMA always includes the NEON
18382 FMA instructions. */
18383 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18384 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18385 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18386 the v form should always be used. */
18387 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18388 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18389 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18390 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18391 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18392 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18394 #undef THUMB_VARIANT
18396 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18398 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18399 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18400 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18401 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18402 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18403 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18404 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18405 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18408 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18410 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18411 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18412 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18413 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18414 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18415 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18416 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18417 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18418 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18419 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18420 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18421 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18422 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18423 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18424 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18425 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18426 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18427 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18428 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18429 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18430 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18431 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18432 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18433 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18434 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18435 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18436 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18437 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18438 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18439 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18440 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18441 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18442 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18443 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18444 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18445 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18446 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18447 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18448 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18449 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18450 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18451 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18452 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18453 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18454 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18455 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18456 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18457 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18458 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18459 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18460 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18461 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18462 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18463 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18464 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18465 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18466 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18467 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18468 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18469 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18470 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18471 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18472 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18473 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18474 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18475 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18476 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18477 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18478 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18479 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18480 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18481 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18482 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18483 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18484 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18485 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18486 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18487 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18488 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18489 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18490 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18491 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18492 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18493 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18494 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18495 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18496 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18497 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18498 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18499 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18500 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18501 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18502 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18503 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18504 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18505 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18506 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18507 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18508 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18509 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18510 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18511 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18512 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18513 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18514 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18515 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18516 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18517 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18518 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18519 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18520 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18521 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18522 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18523 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18524 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18525 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18526 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18527 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18528 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18529 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18530 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18531 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18532 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18533 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18534 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18535 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18536 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18537 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18538 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18539 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18540 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18541 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18542 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18543 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18544 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18545 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18546 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18547 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18548 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18549 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18550 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18551 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18552 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18553 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18554 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18555 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18556 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18557 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18558 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18559 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18560 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18561 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18562 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18563 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18564 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18565 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18566 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18567 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18568 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18569 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18570 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18571 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18574 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18576 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18577 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18578 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18579 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18580 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18581 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18582 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18587 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18588 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18589 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18590 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18597 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18601 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18602 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18603 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18604 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18605 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18606 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18607 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18610 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18611 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18612 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18613 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18614 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18615 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18616 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18617 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18618 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18619 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18620 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18621 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18622 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18623 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18624 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18625 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18626 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18627 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18628 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18629 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18630 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18631 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18632 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18635 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18637 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18638 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18639 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18640 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18641 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18642 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18643 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18644 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18645 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18646 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18647 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18648 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18649 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18650 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18651 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18652 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18653 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18654 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18655 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18656 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18657 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18658 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18659 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18660 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18661 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18662 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18663 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18664 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18665 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18666 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18667 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18668 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18669 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18670 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18671 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18672 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18673 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18674 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18675 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18676 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18677 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18678 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18679 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18680 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18681 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18682 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18683 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18684 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18685 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18686 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18687 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18688 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18689 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18690 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18691 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18692 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18693 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18694 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18695 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18696 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18697 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18698 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18699 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18700 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18701 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18702 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18703 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18704 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18705 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18706 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18707 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18708 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18709 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18710 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18711 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18712 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18715 #undef THUMB_VARIANT
18742 /* MD interface: bits in the object file. */
18744 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18745 for use in the a.out file, and stores them in the array pointed to by buf.
18746 This knows about the endian-ness of the target machine and does
18747 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18748 2 (short) and 4 (long) Floating numbers are put out as a series of
18749 LITTLENUMS (shorts, here at least). */
18752 md_number_to_chars (char * buf
, valueT val
, int n
)
18754 if (target_big_endian
)
18755 number_to_chars_bigendian (buf
, val
, n
);
18757 number_to_chars_littleendian (buf
, val
, n
);
18761 md_chars_to_number (char * buf
, int n
)
18764 unsigned char * where
= (unsigned char *) buf
;
18766 if (target_big_endian
)
18771 result
|= (*where
++ & 255);
18779 result
|= (where
[n
] & 255);
18786 /* MD interface: Sections. */
18788 /* Estimate the size of a frag before relaxing. Assume everything fits in
18792 md_estimate_size_before_relax (fragS
* fragp
,
18793 segT segtype ATTRIBUTE_UNUSED
)
18799 /* Convert a machine dependent frag. */
18802 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18804 unsigned long insn
;
18805 unsigned long old_op
;
18813 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18815 old_op
= bfd_get_16(abfd
, buf
);
18816 if (fragp
->fr_symbol
)
18818 exp
.X_op
= O_symbol
;
18819 exp
.X_add_symbol
= fragp
->fr_symbol
;
18823 exp
.X_op
= O_constant
;
18825 exp
.X_add_number
= fragp
->fr_offset
;
18826 opcode
= fragp
->fr_subtype
;
18829 case T_MNEM_ldr_pc
:
18830 case T_MNEM_ldr_pc2
:
18831 case T_MNEM_ldr_sp
:
18832 case T_MNEM_str_sp
:
18839 if (fragp
->fr_var
== 4)
18841 insn
= THUMB_OP32 (opcode
);
18842 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18844 insn
|= (old_op
& 0x700) << 4;
18848 insn
|= (old_op
& 7) << 12;
18849 insn
|= (old_op
& 0x38) << 13;
18851 insn
|= 0x00000c00;
18852 put_thumb32_insn (buf
, insn
);
18853 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18857 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18859 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18862 if (fragp
->fr_var
== 4)
18864 insn
= THUMB_OP32 (opcode
);
18865 insn
|= (old_op
& 0xf0) << 4;
18866 put_thumb32_insn (buf
, insn
);
18867 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18871 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18872 exp
.X_add_number
-= 4;
18880 if (fragp
->fr_var
== 4)
18882 int r0off
= (opcode
== T_MNEM_mov
18883 || opcode
== T_MNEM_movs
) ? 0 : 8;
18884 insn
= THUMB_OP32 (opcode
);
18885 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18886 insn
|= (old_op
& 0x700) << r0off
;
18887 put_thumb32_insn (buf
, insn
);
18888 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18892 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18897 if (fragp
->fr_var
== 4)
18899 insn
= THUMB_OP32(opcode
);
18900 put_thumb32_insn (buf
, insn
);
18901 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18904 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18908 if (fragp
->fr_var
== 4)
18910 insn
= THUMB_OP32(opcode
);
18911 insn
|= (old_op
& 0xf00) << 14;
18912 put_thumb32_insn (buf
, insn
);
18913 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18916 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18919 case T_MNEM_add_sp
:
18920 case T_MNEM_add_pc
:
18921 case T_MNEM_inc_sp
:
18922 case T_MNEM_dec_sp
:
18923 if (fragp
->fr_var
== 4)
18925 /* ??? Choose between add and addw. */
18926 insn
= THUMB_OP32 (opcode
);
18927 insn
|= (old_op
& 0xf0) << 4;
18928 put_thumb32_insn (buf
, insn
);
18929 if (opcode
== T_MNEM_add_pc
)
18930 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18932 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18935 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18943 if (fragp
->fr_var
== 4)
18945 insn
= THUMB_OP32 (opcode
);
18946 insn
|= (old_op
& 0xf0) << 4;
18947 insn
|= (old_op
& 0xf) << 16;
18948 put_thumb32_insn (buf
, insn
);
18949 if (insn
& (1 << 20))
18950 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18952 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18955 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18961 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18962 (enum bfd_reloc_code_real
) reloc_type
);
18963 fixp
->fx_file
= fragp
->fr_file
;
18964 fixp
->fx_line
= fragp
->fr_line
;
18965 fragp
->fr_fix
+= fragp
->fr_var
;
18968 /* Return the size of a relaxable immediate operand instruction.
18969 SHIFT and SIZE specify the form of the allowable immediate. */
18971 relax_immediate (fragS
*fragp
, int size
, int shift
)
18977 /* ??? Should be able to do better than this. */
18978 if (fragp
->fr_symbol
)
18981 low
= (1 << shift
) - 1;
18982 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18983 offset
= fragp
->fr_offset
;
18984 /* Force misaligned offsets to 32-bit variant. */
18987 if (offset
& ~mask
)
18992 /* Get the address of a symbol during relaxation. */
18994 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19000 sym
= fragp
->fr_symbol
;
19001 sym_frag
= symbol_get_frag (sym
);
19002 know (S_GET_SEGMENT (sym
) != absolute_section
19003 || sym_frag
== &zero_address_frag
);
19004 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19006 /* If frag has yet to be reached on this pass, assume it will
19007 move by STRETCH just as we did. If this is not so, it will
19008 be because some frag between grows, and that will force
19012 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19016 /* Adjust stretch for any alignment frag. Note that if have
19017 been expanding the earlier code, the symbol may be
19018 defined in what appears to be an earlier frag. FIXME:
19019 This doesn't handle the fr_subtype field, which specifies
19020 a maximum number of bytes to skip when doing an
19022 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19024 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19027 stretch
= - ((- stretch
)
19028 & ~ ((1 << (int) f
->fr_offset
) - 1));
19030 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19042 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19045 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19050 /* Assume worst case for symbols not known to be in the same section. */
19051 if (fragp
->fr_symbol
== NULL
19052 || !S_IS_DEFINED (fragp
->fr_symbol
)
19053 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19054 || S_IS_WEAK (fragp
->fr_symbol
))
19057 val
= relaxed_symbol_addr (fragp
, stretch
);
19058 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19059 addr
= (addr
+ 4) & ~3;
19060 /* Force misaligned targets to 32-bit variant. */
19064 if (val
< 0 || val
> 1020)
19069 /* Return the size of a relaxable add/sub immediate instruction. */
19071 relax_addsub (fragS
*fragp
, asection
*sec
)
19076 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19077 op
= bfd_get_16(sec
->owner
, buf
);
19078 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19079 return relax_immediate (fragp
, 8, 0);
19081 return relax_immediate (fragp
, 3, 0);
19085 /* Return the size of a relaxable branch instruction. BITS is the
19086 size of the offset field in the narrow instruction. */
19089 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19095 /* Assume worst case for symbols not known to be in the same section. */
19096 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19097 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19098 || S_IS_WEAK (fragp
->fr_symbol
))
19102 if (S_IS_DEFINED (fragp
->fr_symbol
)
19103 && ARM_IS_FUNC (fragp
->fr_symbol
))
19106 /* PR 12532. Global symbols with default visibility might
19107 be preempted, so do not relax relocations to them. */
19108 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19109 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19113 val
= relaxed_symbol_addr (fragp
, stretch
);
19114 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19117 /* Offset is a signed value *2 */
19119 if (val
>= limit
|| val
< -limit
)
19125 /* Relax a machine dependent frag. This returns the amount by which
19126 the current size of the frag should change. */
19129 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19134 oldsize
= fragp
->fr_var
;
19135 switch (fragp
->fr_subtype
)
19137 case T_MNEM_ldr_pc2
:
19138 newsize
= relax_adr (fragp
, sec
, stretch
);
19140 case T_MNEM_ldr_pc
:
19141 case T_MNEM_ldr_sp
:
19142 case T_MNEM_str_sp
:
19143 newsize
= relax_immediate (fragp
, 8, 2);
19147 newsize
= relax_immediate (fragp
, 5, 2);
19151 newsize
= relax_immediate (fragp
, 5, 1);
19155 newsize
= relax_immediate (fragp
, 5, 0);
19158 newsize
= relax_adr (fragp
, sec
, stretch
);
19164 newsize
= relax_immediate (fragp
, 8, 0);
19167 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19170 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19172 case T_MNEM_add_sp
:
19173 case T_MNEM_add_pc
:
19174 newsize
= relax_immediate (fragp
, 8, 2);
19176 case T_MNEM_inc_sp
:
19177 case T_MNEM_dec_sp
:
19178 newsize
= relax_immediate (fragp
, 7, 2);
19184 newsize
= relax_addsub (fragp
, sec
);
19190 fragp
->fr_var
= newsize
;
19191 /* Freeze wide instructions that are at or before the same location as
19192 in the previous pass. This avoids infinite loops.
19193 Don't freeze them unconditionally because targets may be artificially
19194 misaligned by the expansion of preceding frags. */
19195 if (stretch
<= 0 && newsize
> 2)
19197 md_convert_frag (sec
->owner
, sec
, fragp
);
19201 return newsize
- oldsize
;
19204 /* Round up a section size to the appropriate boundary. */
19207 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19210 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19211 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19213 /* For a.out, force the section size to be aligned. If we don't do
19214 this, BFD will align it for us, but it will not write out the
19215 final bytes of the section. This may be a bug in BFD, but it is
19216 easier to fix it here since that is how the other a.out targets
19220 align
= bfd_get_section_alignment (stdoutput
, segment
);
19221 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19228 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19229 of an rs_align_code fragment. */
19232 arm_handle_align (fragS
* fragP
)
19234 static char const arm_noop
[2][2][4] =
19237 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19238 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19241 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19242 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19245 static char const thumb_noop
[2][2][2] =
19248 {0xc0, 0x46}, /* LE */
19249 {0x46, 0xc0}, /* BE */
19252 {0x00, 0xbf}, /* LE */
19253 {0xbf, 0x00} /* BE */
19256 static char const wide_thumb_noop
[2][4] =
19257 { /* Wide Thumb-2 */
19258 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19259 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19262 unsigned bytes
, fix
, noop_size
;
19265 const char *narrow_noop
= NULL
;
19270 if (fragP
->fr_type
!= rs_align_code
)
19273 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19274 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19277 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19278 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19280 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19282 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19284 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19286 narrow_noop
= thumb_noop
[1][target_big_endian
];
19287 noop
= wide_thumb_noop
[target_big_endian
];
19290 noop
= thumb_noop
[0][target_big_endian
];
19298 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19299 [target_big_endian
];
19306 fragP
->fr_var
= noop_size
;
19308 if (bytes
& (noop_size
- 1))
19310 fix
= bytes
& (noop_size
- 1);
19312 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19314 memset (p
, 0, fix
);
19321 if (bytes
& noop_size
)
19323 /* Insert a narrow noop. */
19324 memcpy (p
, narrow_noop
, noop_size
);
19326 bytes
-= noop_size
;
19330 /* Use wide noops for the remainder */
19334 while (bytes
>= noop_size
)
19336 memcpy (p
, noop
, noop_size
);
19338 bytes
-= noop_size
;
19342 fragP
->fr_fix
+= fix
;
19345 /* Called from md_do_align. Used to create an alignment
19346 frag in a code section. */
19349 arm_frag_align_code (int n
, int max
)
19353 /* We assume that there will never be a requirement
19354 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19355 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19360 _("alignments greater than %d bytes not supported in .text sections."),
19361 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19362 as_fatal ("%s", err_msg
);
19365 p
= frag_var (rs_align_code
,
19366 MAX_MEM_FOR_RS_ALIGN_CODE
,
19368 (relax_substateT
) max
,
19375 /* Perform target specific initialisation of a frag.
19376 Note - despite the name this initialisation is not done when the frag
19377 is created, but only when its type is assigned. A frag can be created
19378 and used a long time before its type is set, so beware of assuming that
19379 this initialisationis performed first. */
19383 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19385 /* Record whether this frag is in an ARM or a THUMB area. */
19386 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19389 #else /* OBJ_ELF is defined. */
19391 arm_init_frag (fragS
* fragP
, int max_chars
)
19393 /* If the current ARM vs THUMB mode has not already
19394 been recorded into this frag then do so now. */
19395 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19397 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19399 /* Record a mapping symbol for alignment frags. We will delete this
19400 later if the alignment ends up empty. */
19401 switch (fragP
->fr_type
)
19404 case rs_align_test
:
19406 mapping_state_2 (MAP_DATA
, max_chars
);
19408 case rs_align_code
:
19409 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19417 /* When we change sections we need to issue a new mapping symbol. */
19420 arm_elf_change_section (void)
19422 /* Link an unlinked unwind index table section to the .text section. */
19423 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19424 && elf_linked_to_section (now_seg
) == NULL
)
19425 elf_linked_to_section (now_seg
) = text_section
;
19429 arm_elf_section_type (const char * str
, size_t len
)
19431 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19432 return SHT_ARM_EXIDX
;
19437 /* Code to deal with unwinding tables. */
19439 static void add_unwind_adjustsp (offsetT
);
19441 /* Generate any deferred unwind frame offset. */
19444 flush_pending_unwind (void)
19448 offset
= unwind
.pending_offset
;
19449 unwind
.pending_offset
= 0;
19451 add_unwind_adjustsp (offset
);
19454 /* Add an opcode to this list for this function. Two-byte opcodes should
19455 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19459 add_unwind_opcode (valueT op
, int length
)
19461 /* Add any deferred stack adjustment. */
19462 if (unwind
.pending_offset
)
19463 flush_pending_unwind ();
19465 unwind
.sp_restored
= 0;
19467 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19469 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19470 if (unwind
.opcodes
)
19471 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19472 unwind
.opcode_alloc
);
19474 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19479 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19481 unwind
.opcode_count
++;
19485 /* Add unwind opcodes to adjust the stack pointer. */
19488 add_unwind_adjustsp (offsetT offset
)
19492 if (offset
> 0x200)
19494 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19499 /* Long form: 0xb2, uleb128. */
19500 /* This might not fit in a word so add the individual bytes,
19501 remembering the list is built in reverse order. */
19502 o
= (valueT
) ((offset
- 0x204) >> 2);
19504 add_unwind_opcode (0, 1);
19506 /* Calculate the uleb128 encoding of the offset. */
19510 bytes
[n
] = o
& 0x7f;
19516 /* Add the insn. */
19518 add_unwind_opcode (bytes
[n
- 1], 1);
19519 add_unwind_opcode (0xb2, 1);
19521 else if (offset
> 0x100)
19523 /* Two short opcodes. */
19524 add_unwind_opcode (0x3f, 1);
19525 op
= (offset
- 0x104) >> 2;
19526 add_unwind_opcode (op
, 1);
19528 else if (offset
> 0)
19530 /* Short opcode. */
19531 op
= (offset
- 4) >> 2;
19532 add_unwind_opcode (op
, 1);
19534 else if (offset
< 0)
19537 while (offset
> 0x100)
19539 add_unwind_opcode (0x7f, 1);
19542 op
= ((offset
- 4) >> 2) | 0x40;
19543 add_unwind_opcode (op
, 1);
19547 /* Finish the list of unwind opcodes for this function. */
19549 finish_unwind_opcodes (void)
19553 if (unwind
.fp_used
)
19555 /* Adjust sp as necessary. */
19556 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19557 flush_pending_unwind ();
19559 /* After restoring sp from the frame pointer. */
19560 op
= 0x90 | unwind
.fp_reg
;
19561 add_unwind_opcode (op
, 1);
19564 flush_pending_unwind ();
19568 /* Start an exception table entry. If idx is nonzero this is an index table
19572 start_unwind_section (const segT text_seg
, int idx
)
19574 const char * text_name
;
19575 const char * prefix
;
19576 const char * prefix_once
;
19577 const char * group_name
;
19581 size_t sec_name_len
;
19588 prefix
= ELF_STRING_ARM_unwind
;
19589 prefix_once
= ELF_STRING_ARM_unwind_once
;
19590 type
= SHT_ARM_EXIDX
;
19594 prefix
= ELF_STRING_ARM_unwind_info
;
19595 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19596 type
= SHT_PROGBITS
;
19599 text_name
= segment_name (text_seg
);
19600 if (streq (text_name
, ".text"))
19603 if (strncmp (text_name
, ".gnu.linkonce.t.",
19604 strlen (".gnu.linkonce.t.")) == 0)
19606 prefix
= prefix_once
;
19607 text_name
+= strlen (".gnu.linkonce.t.");
19610 prefix_len
= strlen (prefix
);
19611 text_len
= strlen (text_name
);
19612 sec_name_len
= prefix_len
+ text_len
;
19613 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19614 memcpy (sec_name
, prefix
, prefix_len
);
19615 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19616 sec_name
[prefix_len
+ text_len
] = '\0';
19622 /* Handle COMDAT group. */
19623 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19625 group_name
= elf_group_name (text_seg
);
19626 if (group_name
== NULL
)
19628 as_bad (_("Group section `%s' has no group signature"),
19629 segment_name (text_seg
));
19630 ignore_rest_of_line ();
19633 flags
|= SHF_GROUP
;
19637 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19639 /* Set the section link for index tables. */
19641 elf_linked_to_section (now_seg
) = text_seg
;
19645 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19646 personality routine data. Returns zero, or the index table value for
19647 and inline entry. */
19650 create_unwind_entry (int have_data
)
19655 /* The current word of data. */
19657 /* The number of bytes left in this word. */
19660 finish_unwind_opcodes ();
19662 /* Remember the current text section. */
19663 unwind
.saved_seg
= now_seg
;
19664 unwind
.saved_subseg
= now_subseg
;
19666 start_unwind_section (now_seg
, 0);
19668 if (unwind
.personality_routine
== NULL
)
19670 if (unwind
.personality_index
== -2)
19673 as_bad (_("handlerdata in cantunwind frame"));
19674 return 1; /* EXIDX_CANTUNWIND. */
19677 /* Use a default personality routine if none is specified. */
19678 if (unwind
.personality_index
== -1)
19680 if (unwind
.opcode_count
> 3)
19681 unwind
.personality_index
= 1;
19683 unwind
.personality_index
= 0;
19686 /* Space for the personality routine entry. */
19687 if (unwind
.personality_index
== 0)
19689 if (unwind
.opcode_count
> 3)
19690 as_bad (_("too many unwind opcodes for personality routine 0"));
19694 /* All the data is inline in the index table. */
19697 while (unwind
.opcode_count
> 0)
19699 unwind
.opcode_count
--;
19700 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19704 /* Pad with "finish" opcodes. */
19706 data
= (data
<< 8) | 0xb0;
19713 /* We get two opcodes "free" in the first word. */
19714 size
= unwind
.opcode_count
- 2;
19717 /* An extra byte is required for the opcode count. */
19718 size
= unwind
.opcode_count
+ 1;
19720 size
= (size
+ 3) >> 2;
19722 as_bad (_("too many unwind opcodes"));
19724 frag_align (2, 0, 0);
19725 record_alignment (now_seg
, 2);
19726 unwind
.table_entry
= expr_build_dot ();
19728 /* Allocate the table entry. */
19729 ptr
= frag_more ((size
<< 2) + 4);
19730 where
= frag_now_fix () - ((size
<< 2) + 4);
19732 switch (unwind
.personality_index
)
19735 /* ??? Should this be a PLT generating relocation? */
19736 /* Custom personality routine. */
19737 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19738 BFD_RELOC_ARM_PREL31
);
19743 /* Set the first byte to the number of additional words. */
19748 /* ABI defined personality routines. */
19750 /* Three opcodes bytes are packed into the first word. */
19757 /* The size and first two opcode bytes go in the first word. */
19758 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19763 /* Should never happen. */
19767 /* Pack the opcodes into words (MSB first), reversing the list at the same
19769 while (unwind
.opcode_count
> 0)
19773 md_number_to_chars (ptr
, data
, 4);
19778 unwind
.opcode_count
--;
19780 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19783 /* Finish off the last word. */
19786 /* Pad with "finish" opcodes. */
19788 data
= (data
<< 8) | 0xb0;
19790 md_number_to_chars (ptr
, data
, 4);
19795 /* Add an empty descriptor if there is no user-specified data. */
19796 ptr
= frag_more (4);
19797 md_number_to_chars (ptr
, 0, 4);
19804 /* Initialize the DWARF-2 unwind information for this procedure. */
19807 tc_arm_frame_initial_instructions (void)
19809 cfi_add_CFA_def_cfa (REG_SP
, 0);
19811 #endif /* OBJ_ELF */
19813 /* Convert REGNAME to a DWARF-2 register number. */
19816 tc_arm_regname_to_dw2regnum (char *regname
)
19818 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19828 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19832 exp
.X_op
= O_secrel
;
19833 exp
.X_add_symbol
= symbol
;
19834 exp
.X_add_number
= 0;
19835 emit_expr (&exp
, size
);
19839 /* MD interface: Symbol and relocation handling. */
19841 /* Return the address within the segment that a PC-relative fixup is
19842 relative to. For ARM, PC-relative fixups applied to instructions
19843 are generally relative to the location of the fixup plus 8 bytes.
19844 Thumb branches are offset by 4, and Thumb loads relative to PC
19845 require special handling. */
19848 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19850 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19852 /* If this is pc-relative and we are going to emit a relocation
19853 then we just want to put out any pipeline compensation that the linker
19854 will need. Otherwise we want to use the calculated base.
19855 For WinCE we skip the bias for externals as well, since this
19856 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19858 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19859 || (arm_force_relocation (fixP
)
19861 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19867 switch (fixP
->fx_r_type
)
19869 /* PC relative addressing on the Thumb is slightly odd as the
19870 bottom two bits of the PC are forced to zero for the
19871 calculation. This happens *after* application of the
19872 pipeline offset. However, Thumb adrl already adjusts for
19873 this, so we need not do it again. */
19874 case BFD_RELOC_ARM_THUMB_ADD
:
19877 case BFD_RELOC_ARM_THUMB_OFFSET
:
19878 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19879 case BFD_RELOC_ARM_T32_ADD_PC12
:
19880 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19881 return (base
+ 4) & ~3;
19883 /* Thumb branches are simply offset by +4. */
19884 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19885 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19886 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19887 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19888 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19891 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19893 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19894 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19895 && ARM_IS_FUNC (fixP
->fx_addsy
)
19896 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19897 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19900 /* BLX is like branches above, but forces the low two bits of PC to
19902 case BFD_RELOC_THUMB_PCREL_BLX
:
19904 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19905 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19906 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19907 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19908 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19909 return (base
+ 4) & ~3;
19911 /* ARM mode branches are offset by +8. However, the Windows CE
19912 loader expects the relocation not to take this into account. */
19913 case BFD_RELOC_ARM_PCREL_BLX
:
19915 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19916 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19917 && ARM_IS_FUNC (fixP
->fx_addsy
)
19918 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19919 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19922 case BFD_RELOC_ARM_PCREL_CALL
:
19924 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19925 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19926 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19927 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19928 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19931 case BFD_RELOC_ARM_PCREL_BRANCH
:
19932 case BFD_RELOC_ARM_PCREL_JUMP
:
19933 case BFD_RELOC_ARM_PLT32
:
19935 /* When handling fixups immediately, because we have already
19936 discovered the value of a symbol, or the address of the frag involved
19937 we must account for the offset by +8, as the OS loader will never see the reloc.
19938 see fixup_segment() in write.c
19939 The S_IS_EXTERNAL test handles the case of global symbols.
19940 Those need the calculated base, not just the pipe compensation the linker will need. */
19942 && fixP
->fx_addsy
!= NULL
19943 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19944 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19952 /* ARM mode loads relative to PC are also offset by +8. Unlike
19953 branches, the Windows CE loader *does* expect the relocation
19954 to take this into account. */
19955 case BFD_RELOC_ARM_OFFSET_IMM
:
19956 case BFD_RELOC_ARM_OFFSET_IMM8
:
19957 case BFD_RELOC_ARM_HWLITERAL
:
19958 case BFD_RELOC_ARM_LITERAL
:
19959 case BFD_RELOC_ARM_CP_OFF_IMM
:
19963 /* Other PC-relative relocations are un-offset. */
19969 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19970 Otherwise we have no need to default values of symbols. */
19973 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19976 if (name
[0] == '_' && name
[1] == 'G'
19977 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19981 if (symbol_find (name
))
19982 as_bad (_("GOT already in the symbol table"));
19984 GOT_symbol
= symbol_new (name
, undefined_section
,
19985 (valueT
) 0, & zero_address_frag
);
19995 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19996 computed as two separate immediate values, added together. We
19997 already know that this value cannot be computed by just one ARM
20000 static unsigned int
20001 validate_immediate_twopart (unsigned int val
,
20002 unsigned int * highpart
)
20007 for (i
= 0; i
< 32; i
+= 2)
20008 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20014 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20016 else if (a
& 0xff0000)
20018 if (a
& 0xff000000)
20020 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20024 gas_assert (a
& 0xff000000);
20025 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20028 return (a
& 0xff) | (i
<< 7);
20035 validate_offset_imm (unsigned int val
, int hwse
)
20037 if ((hwse
&& val
> 255) || val
> 4095)
20042 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20043 negative immediate constant by altering the instruction. A bit of
20048 by inverting the second operand, and
20051 by negating the second operand. */
20054 negate_data_op (unsigned long * instruction
,
20055 unsigned long value
)
20058 unsigned long negated
, inverted
;
20060 negated
= encode_arm_immediate (-value
);
20061 inverted
= encode_arm_immediate (~value
);
20063 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20066 /* First negates. */
20067 case OPCODE_SUB
: /* ADD <-> SUB */
20068 new_inst
= OPCODE_ADD
;
20073 new_inst
= OPCODE_SUB
;
20077 case OPCODE_CMP
: /* CMP <-> CMN */
20078 new_inst
= OPCODE_CMN
;
20083 new_inst
= OPCODE_CMP
;
20087 /* Now Inverted ops. */
20088 case OPCODE_MOV
: /* MOV <-> MVN */
20089 new_inst
= OPCODE_MVN
;
20094 new_inst
= OPCODE_MOV
;
20098 case OPCODE_AND
: /* AND <-> BIC */
20099 new_inst
= OPCODE_BIC
;
20104 new_inst
= OPCODE_AND
;
20108 case OPCODE_ADC
: /* ADC <-> SBC */
20109 new_inst
= OPCODE_SBC
;
20114 new_inst
= OPCODE_ADC
;
20118 /* We cannot do anything. */
20123 if (value
== (unsigned) FAIL
)
20126 *instruction
&= OPCODE_MASK
;
20127 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20131 /* Like negate_data_op, but for Thumb-2. */
20133 static unsigned int
20134 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20138 unsigned int negated
, inverted
;
20140 negated
= encode_thumb32_immediate (-value
);
20141 inverted
= encode_thumb32_immediate (~value
);
20143 rd
= (*instruction
>> 8) & 0xf;
20144 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20147 /* ADD <-> SUB. Includes CMP <-> CMN. */
20148 case T2_OPCODE_SUB
:
20149 new_inst
= T2_OPCODE_ADD
;
20153 case T2_OPCODE_ADD
:
20154 new_inst
= T2_OPCODE_SUB
;
20158 /* ORR <-> ORN. Includes MOV <-> MVN. */
20159 case T2_OPCODE_ORR
:
20160 new_inst
= T2_OPCODE_ORN
;
20164 case T2_OPCODE_ORN
:
20165 new_inst
= T2_OPCODE_ORR
;
20169 /* AND <-> BIC. TST has no inverted equivalent. */
20170 case T2_OPCODE_AND
:
20171 new_inst
= T2_OPCODE_BIC
;
20178 case T2_OPCODE_BIC
:
20179 new_inst
= T2_OPCODE_AND
;
20184 case T2_OPCODE_ADC
:
20185 new_inst
= T2_OPCODE_SBC
;
20189 case T2_OPCODE_SBC
:
20190 new_inst
= T2_OPCODE_ADC
;
20194 /* We cannot do anything. */
20199 if (value
== (unsigned int)FAIL
)
20202 *instruction
&= T2_OPCODE_MASK
;
20203 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20207 /* Read a 32-bit thumb instruction from buf. */
20208 static unsigned long
20209 get_thumb32_insn (char * buf
)
20211 unsigned long insn
;
20212 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20213 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20219 /* We usually want to set the low bit on the address of thumb function
20220 symbols. In particular .word foo - . should have the low bit set.
20221 Generic code tries to fold the difference of two symbols to
20222 a constant. Prevent this and force a relocation when the first symbols
20223 is a thumb function. */
20226 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20228 if (op
== O_subtract
20229 && l
->X_op
== O_symbol
20230 && r
->X_op
== O_symbol
20231 && THUMB_IS_FUNC (l
->X_add_symbol
))
20233 l
->X_op
= O_subtract
;
20234 l
->X_op_symbol
= r
->X_add_symbol
;
20235 l
->X_add_number
-= r
->X_add_number
;
20239 /* Process as normal. */
20243 /* Encode Thumb2 unconditional branches and calls. The encoding
20244 for the 2 are identical for the immediate values. */
20247 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20249 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20252 addressT S
, I1
, I2
, lo
, hi
;
20254 S
= (value
>> 24) & 0x01;
20255 I1
= (value
>> 23) & 0x01;
20256 I2
= (value
>> 22) & 0x01;
20257 hi
= (value
>> 12) & 0x3ff;
20258 lo
= (value
>> 1) & 0x7ff;
20259 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20260 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20261 newval
|= (S
<< 10) | hi
;
20262 newval2
&= ~T2I1I2MASK
;
20263 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20265 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20269 md_apply_fix (fixS
* fixP
,
20273 offsetT value
= * valP
;
20275 unsigned int newimm
;
20276 unsigned long temp
;
20278 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20280 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20282 /* Note whether this will delete the relocation. */
20284 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20287 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20288 consistency with the behaviour on 32-bit hosts. Remember value
20290 value
&= 0xffffffff;
20291 value
^= 0x80000000;
20292 value
-= 0x80000000;
20295 fixP
->fx_addnumber
= value
;
20297 /* Same treatment for fixP->fx_offset. */
20298 fixP
->fx_offset
&= 0xffffffff;
20299 fixP
->fx_offset
^= 0x80000000;
20300 fixP
->fx_offset
-= 0x80000000;
20302 switch (fixP
->fx_r_type
)
20304 case BFD_RELOC_NONE
:
20305 /* This will need to go in the object file. */
20309 case BFD_RELOC_ARM_IMMEDIATE
:
20310 /* We claim that this fixup has been processed here,
20311 even if in fact we generate an error because we do
20312 not have a reloc for it, so tc_gen_reloc will reject it. */
20315 if (fixP
->fx_addsy
)
20317 const char *msg
= 0;
20319 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20320 msg
= _("undefined symbol %s used as an immediate value");
20321 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20322 msg
= _("symbol %s is in a different section");
20323 else if (S_IS_WEAK (fixP
->fx_addsy
))
20324 msg
= _("symbol %s is weak and may be overridden later");
20328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20329 msg
, S_GET_NAME (fixP
->fx_addsy
));
20334 newimm
= encode_arm_immediate (value
);
20335 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20337 /* If the instruction will fail, see if we can fix things up by
20338 changing the opcode. */
20339 if (newimm
== (unsigned int) FAIL
20340 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20343 _("invalid constant (%lx) after fixup"),
20344 (unsigned long) value
);
20348 newimm
|= (temp
& 0xfffff000);
20349 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20352 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20354 unsigned int highpart
= 0;
20355 unsigned int newinsn
= 0xe1a00000; /* nop. */
20357 if (fixP
->fx_addsy
)
20359 const char *msg
= 0;
20361 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20362 msg
= _("undefined symbol %s used as an immediate value");
20363 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20364 msg
= _("symbol %s is in a different section");
20365 else if (S_IS_WEAK (fixP
->fx_addsy
))
20366 msg
= _("symbol %s is weak and may be overridden later");
20370 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20371 msg
, S_GET_NAME (fixP
->fx_addsy
));
20376 newimm
= encode_arm_immediate (value
);
20377 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20379 /* If the instruction will fail, see if we can fix things up by
20380 changing the opcode. */
20381 if (newimm
== (unsigned int) FAIL
20382 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20384 /* No ? OK - try using two ADD instructions to generate
20386 newimm
= validate_immediate_twopart (value
, & highpart
);
20388 /* Yes - then make sure that the second instruction is
20390 if (newimm
!= (unsigned int) FAIL
)
20392 /* Still No ? Try using a negated value. */
20393 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20394 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20395 /* Otherwise - give up. */
20398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20399 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20404 /* Replace the first operand in the 2nd instruction (which
20405 is the PC) with the destination register. We have
20406 already added in the PC in the first instruction and we
20407 do not want to do it again. */
20408 newinsn
&= ~ 0xf0000;
20409 newinsn
|= ((newinsn
& 0x0f000) << 4);
20412 newimm
|= (temp
& 0xfffff000);
20413 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20415 highpart
|= (newinsn
& 0xfffff000);
20416 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20420 case BFD_RELOC_ARM_OFFSET_IMM
:
20421 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20424 case BFD_RELOC_ARM_LITERAL
:
20430 if (validate_offset_imm (value
, 0) == FAIL
)
20432 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20434 _("invalid literal constant: pool needs to be closer"));
20436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20437 _("bad immediate value for offset (%ld)"),
20442 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20443 newval
&= 0xff7ff000;
20444 newval
|= value
| (sign
? INDEX_UP
: 0);
20445 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20448 case BFD_RELOC_ARM_OFFSET_IMM8
:
20449 case BFD_RELOC_ARM_HWLITERAL
:
20455 if (validate_offset_imm (value
, 1) == FAIL
)
20457 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20459 _("invalid literal constant: pool needs to be closer"));
20461 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20466 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20467 newval
&= 0xff7ff0f0;
20468 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20469 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20472 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20473 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20475 _("bad immediate value for offset (%ld)"), (long) value
);
20478 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20480 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20483 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20484 /* This is a complicated relocation used for all varieties of Thumb32
20485 load/store instruction with immediate offset:
20487 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20488 *4, optional writeback(W)
20489 (doubleword load/store)
20491 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20492 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20493 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20494 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20495 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20497 Uppercase letters indicate bits that are already encoded at
20498 this point. Lowercase letters are our problem. For the
20499 second block of instructions, the secondary opcode nybble
20500 (bits 8..11) is present, and bit 23 is zero, even if this is
20501 a PC-relative operation. */
20502 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20504 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20506 if ((newval
& 0xf0000000) == 0xe0000000)
20508 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20510 newval
|= (1 << 23);
20513 if (value
% 4 != 0)
20515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20516 _("offset not a multiple of 4"));
20522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20523 _("offset out of range"));
20528 else if ((newval
& 0x000f0000) == 0x000f0000)
20530 /* PC-relative, 12-bit offset. */
20532 newval
|= (1 << 23);
20537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20538 _("offset out of range"));
20543 else if ((newval
& 0x00000100) == 0x00000100)
20545 /* Writeback: 8-bit, +/- offset. */
20547 newval
|= (1 << 9);
20552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20553 _("offset out of range"));
20558 else if ((newval
& 0x00000f00) == 0x00000e00)
20560 /* T-instruction: positive 8-bit offset. */
20561 if (value
< 0 || value
> 0xff)
20563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20564 _("offset out of range"));
20572 /* Positive 12-bit or negative 8-bit offset. */
20576 newval
|= (1 << 23);
20586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20587 _("offset out of range"));
20594 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20595 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20598 case BFD_RELOC_ARM_SHIFT_IMM
:
20599 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20600 if (((unsigned long) value
) > 32
20602 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20605 _("shift expression is too large"));
20610 /* Shifts of zero must be done as lsl. */
20612 else if (value
== 32)
20614 newval
&= 0xfffff07f;
20615 newval
|= (value
& 0x1f) << 7;
20616 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20619 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20620 case BFD_RELOC_ARM_T32_ADD_IMM
:
20621 case BFD_RELOC_ARM_T32_IMM12
:
20622 case BFD_RELOC_ARM_T32_ADD_PC12
:
20623 /* We claim that this fixup has been processed here,
20624 even if in fact we generate an error because we do
20625 not have a reloc for it, so tc_gen_reloc will reject it. */
20629 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20632 _("undefined symbol %s used as an immediate value"),
20633 S_GET_NAME (fixP
->fx_addsy
));
20637 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20639 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20642 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20643 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20645 newimm
= encode_thumb32_immediate (value
);
20646 if (newimm
== (unsigned int) FAIL
)
20647 newimm
= thumb32_negate_data_op (&newval
, value
);
20649 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20650 && newimm
== (unsigned int) FAIL
)
20652 /* Turn add/sum into addw/subw. */
20653 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20654 newval
= (newval
& 0xfeffffff) | 0x02000000;
20655 /* No flat 12-bit imm encoding for addsw/subsw. */
20656 if ((newval
& 0x00100000) == 0)
20658 /* 12 bit immediate for addw/subw. */
20662 newval
^= 0x00a00000;
20665 newimm
= (unsigned int) FAIL
;
20671 if (newimm
== (unsigned int)FAIL
)
20673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20674 _("invalid constant (%lx) after fixup"),
20675 (unsigned long) value
);
20679 newval
|= (newimm
& 0x800) << 15;
20680 newval
|= (newimm
& 0x700) << 4;
20681 newval
|= (newimm
& 0x0ff);
20683 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20684 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20687 case BFD_RELOC_ARM_SMC
:
20688 if (((unsigned long) value
) > 0xffff)
20689 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20690 _("invalid smc expression"));
20691 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20692 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20693 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20696 case BFD_RELOC_ARM_HVC
:
20697 if (((unsigned long) value
) > 0xffff)
20698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20699 _("invalid hvc expression"));
20700 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20701 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20702 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20705 case BFD_RELOC_ARM_SWI
:
20706 if (fixP
->tc_fix_data
!= 0)
20708 if (((unsigned long) value
) > 0xff)
20709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20710 _("invalid swi expression"));
20711 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20713 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20717 if (((unsigned long) value
) > 0x00ffffff)
20718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20719 _("invalid swi expression"));
20720 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20722 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20726 case BFD_RELOC_ARM_MULTI
:
20727 if (((unsigned long) value
) > 0xffff)
20728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20729 _("invalid expression in load/store multiple"));
20730 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20731 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20735 case BFD_RELOC_ARM_PCREL_CALL
:
20737 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20739 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20740 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20741 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20742 /* Flip the bl to blx. This is a simple flip
20743 bit here because we generate PCREL_CALL for
20744 unconditional bls. */
20746 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20747 newval
= newval
| 0x10000000;
20748 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20754 goto arm_branch_common
;
20756 case BFD_RELOC_ARM_PCREL_JUMP
:
20757 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20759 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20760 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20761 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20763 /* This would map to a bl<cond>, b<cond>,
20764 b<always> to a Thumb function. We
20765 need to force a relocation for this particular
20767 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20771 case BFD_RELOC_ARM_PLT32
:
20773 case BFD_RELOC_ARM_PCREL_BRANCH
:
20775 goto arm_branch_common
;
20777 case BFD_RELOC_ARM_PCREL_BLX
:
20780 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20782 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20783 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20784 && ARM_IS_FUNC (fixP
->fx_addsy
))
20786 /* Flip the blx to a bl and warn. */
20787 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20788 newval
= 0xeb000000;
20789 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20790 _("blx to '%s' an ARM ISA state function changed to bl"),
20792 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20798 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20799 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20803 /* We are going to store value (shifted right by two) in the
20804 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20805 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20806 also be be clear. */
20808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20809 _("misaligned branch destination"));
20810 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20811 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20813 _("branch out of range"));
20815 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20817 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20818 newval
|= (value
>> 2) & 0x00ffffff;
20819 /* Set the H bit on BLX instructions. */
20823 newval
|= 0x01000000;
20825 newval
&= ~0x01000000;
20827 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20831 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20832 /* CBZ can only branch forward. */
20834 /* Attempts to use CBZ to branch to the next instruction
20835 (which, strictly speaking, are prohibited) will be turned into
20838 FIXME: It may be better to remove the instruction completely and
20839 perform relaxation. */
20842 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20843 newval
= 0xbf00; /* NOP encoding T1 */
20844 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20850 _("branch out of range"));
20852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20854 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20855 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20856 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20861 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20862 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20864 _("branch out of range"));
20866 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20868 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20869 newval
|= (value
& 0x1ff) >> 1;
20870 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20874 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20875 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20877 _("branch out of range"));
20879 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20881 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20882 newval
|= (value
& 0xfff) >> 1;
20883 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20887 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20889 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20890 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20891 && ARM_IS_FUNC (fixP
->fx_addsy
)
20892 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20894 /* Force a relocation for a branch 20 bits wide. */
20897 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20899 _("conditional branch out of range"));
20901 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20904 addressT S
, J1
, J2
, lo
, hi
;
20906 S
= (value
& 0x00100000) >> 20;
20907 J2
= (value
& 0x00080000) >> 19;
20908 J1
= (value
& 0x00040000) >> 18;
20909 hi
= (value
& 0x0003f000) >> 12;
20910 lo
= (value
& 0x00000ffe) >> 1;
20912 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20913 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20914 newval
|= (S
<< 10) | hi
;
20915 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20916 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20917 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20921 case BFD_RELOC_THUMB_PCREL_BLX
:
20923 /* If there is a blx from a thumb state function to
20924 another thumb function flip this to a bl and warn
20928 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20929 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20930 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20932 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20933 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20934 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20936 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20937 newval
= newval
| 0x1000;
20938 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20939 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20944 goto thumb_bl_common
;
20946 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20948 /* A bl from Thumb state ISA to an internal ARM state function
20949 is converted to a blx. */
20951 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20952 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20953 && ARM_IS_FUNC (fixP
->fx_addsy
)
20954 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20956 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20957 newval
= newval
& ~0x1000;
20958 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20959 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20966 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20967 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20968 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20971 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20972 /* For a BLX instruction, make sure that the relocation is rounded up
20973 to a word boundary. This follows the semantics of the instruction
20974 which specifies that bit 1 of the target address will come from bit
20975 1 of the base address. */
20976 value
= (value
+ 1) & ~ 1;
20979 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20981 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20984 _("branch out of range"));
20986 else if ((value
& ~0x1ffffff)
20987 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20990 _("Thumb2 branch out of range"));
20994 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20995 encode_thumb2_b_bl_offset (buf
, value
);
20999 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21000 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
21001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21002 _("branch out of range"));
21004 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21005 encode_thumb2_b_bl_offset (buf
, value
);
21010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21011 md_number_to_chars (buf
, value
, 1);
21015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21016 md_number_to_chars (buf
, value
, 2);
21020 case BFD_RELOC_ARM_TLS_CALL
:
21021 case BFD_RELOC_ARM_THM_TLS_CALL
:
21022 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21023 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21024 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21027 case BFD_RELOC_ARM_TLS_GOTDESC
:
21028 case BFD_RELOC_ARM_TLS_GD32
:
21029 case BFD_RELOC_ARM_TLS_LE32
:
21030 case BFD_RELOC_ARM_TLS_IE32
:
21031 case BFD_RELOC_ARM_TLS_LDM32
:
21032 case BFD_RELOC_ARM_TLS_LDO32
:
21033 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21036 case BFD_RELOC_ARM_GOT32
:
21037 case BFD_RELOC_ARM_GOTOFF
:
21038 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21039 md_number_to_chars (buf
, 0, 4);
21042 case BFD_RELOC_ARM_GOT_PREL
:
21043 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21044 md_number_to_chars (buf
, value
, 4);
21047 case BFD_RELOC_ARM_TARGET2
:
21048 /* TARGET2 is not partial-inplace, so we need to write the
21049 addend here for REL targets, because it won't be written out
21050 during reloc processing later. */
21051 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21052 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21056 case BFD_RELOC_RVA
:
21058 case BFD_RELOC_ARM_TARGET1
:
21059 case BFD_RELOC_ARM_ROSEGREL32
:
21060 case BFD_RELOC_ARM_SBREL32
:
21061 case BFD_RELOC_32_PCREL
:
21063 case BFD_RELOC_32_SECREL
:
21065 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21067 /* For WinCE we only do this for pcrel fixups. */
21068 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21070 md_number_to_chars (buf
, value
, 4);
21074 case BFD_RELOC_ARM_PREL31
:
21075 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21077 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21078 if ((value
^ (value
>> 1)) & 0x40000000)
21080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21081 _("rel31 relocation overflow"));
21083 newval
|= value
& 0x7fffffff;
21084 md_number_to_chars (buf
, newval
, 4);
21089 case BFD_RELOC_ARM_CP_OFF_IMM
:
21090 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21091 if (value
< -1023 || value
> 1023 || (value
& 3))
21092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21093 _("co-processor offset out of range"));
21098 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21099 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21100 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21102 newval
= get_thumb32_insn (buf
);
21103 newval
&= 0xff7fff00;
21104 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21105 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21106 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21107 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21109 put_thumb32_insn (buf
, newval
);
21112 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21113 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21114 if (value
< -255 || value
> 255)
21115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21116 _("co-processor offset out of range"));
21118 goto cp_off_common
;
21120 case BFD_RELOC_ARM_THUMB_OFFSET
:
21121 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21122 /* Exactly what ranges, and where the offset is inserted depends
21123 on the type of instruction, we can establish this from the
21125 switch (newval
>> 12)
21127 case 4: /* PC load. */
21128 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21129 forced to zero for these loads; md_pcrel_from has already
21130 compensated for this. */
21132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21133 _("invalid offset, target not word aligned (0x%08lX)"),
21134 (((unsigned long) fixP
->fx_frag
->fr_address
21135 + (unsigned long) fixP
->fx_where
) & ~3)
21136 + (unsigned long) value
);
21138 if (value
& ~0x3fc)
21139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21140 _("invalid offset, value too big (0x%08lX)"),
21143 newval
|= value
>> 2;
21146 case 9: /* SP load/store. */
21147 if (value
& ~0x3fc)
21148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21149 _("invalid offset, value too big (0x%08lX)"),
21151 newval
|= value
>> 2;
21154 case 6: /* Word load/store. */
21156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21157 _("invalid offset, value too big (0x%08lX)"),
21159 newval
|= value
<< 4; /* 6 - 2. */
21162 case 7: /* Byte load/store. */
21164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21165 _("invalid offset, value too big (0x%08lX)"),
21167 newval
|= value
<< 6;
21170 case 8: /* Halfword load/store. */
21172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21173 _("invalid offset, value too big (0x%08lX)"),
21175 newval
|= value
<< 5; /* 6 - 1. */
21179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21180 "Unable to process relocation for thumb opcode: %lx",
21181 (unsigned long) newval
);
21184 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21187 case BFD_RELOC_ARM_THUMB_ADD
:
21188 /* This is a complicated relocation, since we use it for all of
21189 the following immediate relocations:
21193 9bit ADD/SUB SP word-aligned
21194 10bit ADD PC/SP word-aligned
21196 The type of instruction being processed is encoded in the
21203 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21205 int rd
= (newval
>> 4) & 0xf;
21206 int rs
= newval
& 0xf;
21207 int subtract
= !!(newval
& 0x8000);
21209 /* Check for HI regs, only very restricted cases allowed:
21210 Adjusting SP, and using PC or SP to get an address. */
21211 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21212 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21214 _("invalid Hi register with immediate"));
21216 /* If value is negative, choose the opposite instruction. */
21220 subtract
= !subtract
;
21222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21223 _("immediate value out of range"));
21228 if (value
& ~0x1fc)
21229 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21230 _("invalid immediate for stack address calculation"));
21231 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21232 newval
|= value
>> 2;
21234 else if (rs
== REG_PC
|| rs
== REG_SP
)
21236 if (subtract
|| value
& ~0x3fc)
21237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21238 _("invalid immediate for address calculation (value = 0x%08lX)"),
21239 (unsigned long) value
);
21240 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21242 newval
|= value
>> 2;
21247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21248 _("immediate value out of range"));
21249 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21250 newval
|= (rd
<< 8) | value
;
21255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21256 _("immediate value out of range"));
21257 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21258 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21261 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21264 case BFD_RELOC_ARM_THUMB_IMM
:
21265 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21266 if (value
< 0 || value
> 255)
21267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21268 _("invalid immediate: %ld is out of range"),
21271 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21274 case BFD_RELOC_ARM_THUMB_SHIFT
:
21275 /* 5bit shift value (0..32). LSL cannot take 32. */
21276 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21277 temp
= newval
& 0xf800;
21278 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21280 _("invalid shift value: %ld"), (long) value
);
21281 /* Shifts of zero must be encoded as LSL. */
21283 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21284 /* Shifts of 32 are encoded as zero. */
21285 else if (value
== 32)
21287 newval
|= value
<< 6;
21288 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21291 case BFD_RELOC_VTABLE_INHERIT
:
21292 case BFD_RELOC_VTABLE_ENTRY
:
21296 case BFD_RELOC_ARM_MOVW
:
21297 case BFD_RELOC_ARM_MOVT
:
21298 case BFD_RELOC_ARM_THUMB_MOVW
:
21299 case BFD_RELOC_ARM_THUMB_MOVT
:
21300 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21302 /* REL format relocations are limited to a 16-bit addend. */
21303 if (!fixP
->fx_done
)
21305 if (value
< -0x8000 || value
> 0x7fff)
21306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21307 _("offset out of range"));
21309 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21310 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21315 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21316 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21318 newval
= get_thumb32_insn (buf
);
21319 newval
&= 0xfbf08f00;
21320 newval
|= (value
& 0xf000) << 4;
21321 newval
|= (value
& 0x0800) << 15;
21322 newval
|= (value
& 0x0700) << 4;
21323 newval
|= (value
& 0x00ff);
21324 put_thumb32_insn (buf
, newval
);
21328 newval
= md_chars_to_number (buf
, 4);
21329 newval
&= 0xfff0f000;
21330 newval
|= value
& 0x0fff;
21331 newval
|= (value
& 0xf000) << 4;
21332 md_number_to_chars (buf
, newval
, 4);
21337 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21338 case BFD_RELOC_ARM_ALU_PC_G0
:
21339 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21340 case BFD_RELOC_ARM_ALU_PC_G1
:
21341 case BFD_RELOC_ARM_ALU_PC_G2
:
21342 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21343 case BFD_RELOC_ARM_ALU_SB_G0
:
21344 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21345 case BFD_RELOC_ARM_ALU_SB_G1
:
21346 case BFD_RELOC_ARM_ALU_SB_G2
:
21347 gas_assert (!fixP
->fx_done
);
21348 if (!seg
->use_rela_p
)
21351 bfd_vma encoded_addend
;
21352 bfd_vma addend_abs
= abs (value
);
21354 /* Check that the absolute value of the addend can be
21355 expressed as an 8-bit constant plus a rotation. */
21356 encoded_addend
= encode_arm_immediate (addend_abs
);
21357 if (encoded_addend
== (unsigned int) FAIL
)
21358 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21359 _("the offset 0x%08lX is not representable"),
21360 (unsigned long) addend_abs
);
21362 /* Extract the instruction. */
21363 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21365 /* If the addend is positive, use an ADD instruction.
21366 Otherwise use a SUB. Take care not to destroy the S bit. */
21367 insn
&= 0xff1fffff;
21373 /* Place the encoded addend into the first 12 bits of the
21375 insn
&= 0xfffff000;
21376 insn
|= encoded_addend
;
21378 /* Update the instruction. */
21379 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21383 case BFD_RELOC_ARM_LDR_PC_G0
:
21384 case BFD_RELOC_ARM_LDR_PC_G1
:
21385 case BFD_RELOC_ARM_LDR_PC_G2
:
21386 case BFD_RELOC_ARM_LDR_SB_G0
:
21387 case BFD_RELOC_ARM_LDR_SB_G1
:
21388 case BFD_RELOC_ARM_LDR_SB_G2
:
21389 gas_assert (!fixP
->fx_done
);
21390 if (!seg
->use_rela_p
)
21393 bfd_vma addend_abs
= abs (value
);
21395 /* Check that the absolute value of the addend can be
21396 encoded in 12 bits. */
21397 if (addend_abs
>= 0x1000)
21398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21399 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21400 (unsigned long) addend_abs
);
21402 /* Extract the instruction. */
21403 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21405 /* If the addend is negative, clear bit 23 of the instruction.
21406 Otherwise set it. */
21408 insn
&= ~(1 << 23);
21412 /* Place the absolute value of the addend into the first 12 bits
21413 of the instruction. */
21414 insn
&= 0xfffff000;
21415 insn
|= addend_abs
;
21417 /* Update the instruction. */
21418 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21422 case BFD_RELOC_ARM_LDRS_PC_G0
:
21423 case BFD_RELOC_ARM_LDRS_PC_G1
:
21424 case BFD_RELOC_ARM_LDRS_PC_G2
:
21425 case BFD_RELOC_ARM_LDRS_SB_G0
:
21426 case BFD_RELOC_ARM_LDRS_SB_G1
:
21427 case BFD_RELOC_ARM_LDRS_SB_G2
:
21428 gas_assert (!fixP
->fx_done
);
21429 if (!seg
->use_rela_p
)
21432 bfd_vma addend_abs
= abs (value
);
21434 /* Check that the absolute value of the addend can be
21435 encoded in 8 bits. */
21436 if (addend_abs
>= 0x100)
21437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21438 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21439 (unsigned long) addend_abs
);
21441 /* Extract the instruction. */
21442 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21444 /* If the addend is negative, clear bit 23 of the instruction.
21445 Otherwise set it. */
21447 insn
&= ~(1 << 23);
21451 /* Place the first four bits of the absolute value of the addend
21452 into the first 4 bits of the instruction, and the remaining
21453 four into bits 8 .. 11. */
21454 insn
&= 0xfffff0f0;
21455 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21457 /* Update the instruction. */
21458 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21462 case BFD_RELOC_ARM_LDC_PC_G0
:
21463 case BFD_RELOC_ARM_LDC_PC_G1
:
21464 case BFD_RELOC_ARM_LDC_PC_G2
:
21465 case BFD_RELOC_ARM_LDC_SB_G0
:
21466 case BFD_RELOC_ARM_LDC_SB_G1
:
21467 case BFD_RELOC_ARM_LDC_SB_G2
:
21468 gas_assert (!fixP
->fx_done
);
21469 if (!seg
->use_rela_p
)
21472 bfd_vma addend_abs
= abs (value
);
21474 /* Check that the absolute value of the addend is a multiple of
21475 four and, when divided by four, fits in 8 bits. */
21476 if (addend_abs
& 0x3)
21477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21478 _("bad offset 0x%08lX (must be word-aligned)"),
21479 (unsigned long) addend_abs
);
21481 if ((addend_abs
>> 2) > 0xff)
21482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21483 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21484 (unsigned long) addend_abs
);
21486 /* Extract the instruction. */
21487 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21489 /* If the addend is negative, clear bit 23 of the instruction.
21490 Otherwise set it. */
21492 insn
&= ~(1 << 23);
21496 /* Place the addend (divided by four) into the first eight
21497 bits of the instruction. */
21498 insn
&= 0xfffffff0;
21499 insn
|= addend_abs
>> 2;
21501 /* Update the instruction. */
21502 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21506 case BFD_RELOC_ARM_V4BX
:
21507 /* This will need to go in the object file. */
21511 case BFD_RELOC_UNUSED
:
21513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21514 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21518 /* Translate internal representation of relocation info to BFD target
21522 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21525 bfd_reloc_code_real_type code
;
21527 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21529 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21530 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21531 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21533 if (fixp
->fx_pcrel
)
21535 if (section
->use_rela_p
)
21536 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21538 fixp
->fx_offset
= reloc
->address
;
21540 reloc
->addend
= fixp
->fx_offset
;
21542 switch (fixp
->fx_r_type
)
21545 if (fixp
->fx_pcrel
)
21547 code
= BFD_RELOC_8_PCREL
;
21552 if (fixp
->fx_pcrel
)
21554 code
= BFD_RELOC_16_PCREL
;
21559 if (fixp
->fx_pcrel
)
21561 code
= BFD_RELOC_32_PCREL
;
21565 case BFD_RELOC_ARM_MOVW
:
21566 if (fixp
->fx_pcrel
)
21568 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21572 case BFD_RELOC_ARM_MOVT
:
21573 if (fixp
->fx_pcrel
)
21575 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21579 case BFD_RELOC_ARM_THUMB_MOVW
:
21580 if (fixp
->fx_pcrel
)
21582 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21586 case BFD_RELOC_ARM_THUMB_MOVT
:
21587 if (fixp
->fx_pcrel
)
21589 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21593 case BFD_RELOC_NONE
:
21594 case BFD_RELOC_ARM_PCREL_BRANCH
:
21595 case BFD_RELOC_ARM_PCREL_BLX
:
21596 case BFD_RELOC_RVA
:
21597 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21598 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21599 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21600 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21601 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21602 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21603 case BFD_RELOC_VTABLE_ENTRY
:
21604 case BFD_RELOC_VTABLE_INHERIT
:
21606 case BFD_RELOC_32_SECREL
:
21608 code
= fixp
->fx_r_type
;
21611 case BFD_RELOC_THUMB_PCREL_BLX
:
21613 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21614 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21617 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21620 case BFD_RELOC_ARM_LITERAL
:
21621 case BFD_RELOC_ARM_HWLITERAL
:
21622 /* If this is called then the a literal has
21623 been referenced across a section boundary. */
21624 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21625 _("literal referenced across section boundary"));
21629 case BFD_RELOC_ARM_TLS_CALL
:
21630 case BFD_RELOC_ARM_THM_TLS_CALL
:
21631 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21632 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21633 case BFD_RELOC_ARM_GOT32
:
21634 case BFD_RELOC_ARM_GOTOFF
:
21635 case BFD_RELOC_ARM_GOT_PREL
:
21636 case BFD_RELOC_ARM_PLT32
:
21637 case BFD_RELOC_ARM_TARGET1
:
21638 case BFD_RELOC_ARM_ROSEGREL32
:
21639 case BFD_RELOC_ARM_SBREL32
:
21640 case BFD_RELOC_ARM_PREL31
:
21641 case BFD_RELOC_ARM_TARGET2
:
21642 case BFD_RELOC_ARM_TLS_LE32
:
21643 case BFD_RELOC_ARM_TLS_LDO32
:
21644 case BFD_RELOC_ARM_PCREL_CALL
:
21645 case BFD_RELOC_ARM_PCREL_JUMP
:
21646 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21647 case BFD_RELOC_ARM_ALU_PC_G0
:
21648 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21649 case BFD_RELOC_ARM_ALU_PC_G1
:
21650 case BFD_RELOC_ARM_ALU_PC_G2
:
21651 case BFD_RELOC_ARM_LDR_PC_G0
:
21652 case BFD_RELOC_ARM_LDR_PC_G1
:
21653 case BFD_RELOC_ARM_LDR_PC_G2
:
21654 case BFD_RELOC_ARM_LDRS_PC_G0
:
21655 case BFD_RELOC_ARM_LDRS_PC_G1
:
21656 case BFD_RELOC_ARM_LDRS_PC_G2
:
21657 case BFD_RELOC_ARM_LDC_PC_G0
:
21658 case BFD_RELOC_ARM_LDC_PC_G1
:
21659 case BFD_RELOC_ARM_LDC_PC_G2
:
21660 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21661 case BFD_RELOC_ARM_ALU_SB_G0
:
21662 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21663 case BFD_RELOC_ARM_ALU_SB_G1
:
21664 case BFD_RELOC_ARM_ALU_SB_G2
:
21665 case BFD_RELOC_ARM_LDR_SB_G0
:
21666 case BFD_RELOC_ARM_LDR_SB_G1
:
21667 case BFD_RELOC_ARM_LDR_SB_G2
:
21668 case BFD_RELOC_ARM_LDRS_SB_G0
:
21669 case BFD_RELOC_ARM_LDRS_SB_G1
:
21670 case BFD_RELOC_ARM_LDRS_SB_G2
:
21671 case BFD_RELOC_ARM_LDC_SB_G0
:
21672 case BFD_RELOC_ARM_LDC_SB_G1
:
21673 case BFD_RELOC_ARM_LDC_SB_G2
:
21674 case BFD_RELOC_ARM_V4BX
:
21675 code
= fixp
->fx_r_type
;
21678 case BFD_RELOC_ARM_TLS_GOTDESC
:
21679 case BFD_RELOC_ARM_TLS_GD32
:
21680 case BFD_RELOC_ARM_TLS_IE32
:
21681 case BFD_RELOC_ARM_TLS_LDM32
:
21682 /* BFD will include the symbol's address in the addend.
21683 But we don't want that, so subtract it out again here. */
21684 if (!S_IS_COMMON (fixp
->fx_addsy
))
21685 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21686 code
= fixp
->fx_r_type
;
21690 case BFD_RELOC_ARM_IMMEDIATE
:
21691 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21692 _("internal relocation (type: IMMEDIATE) not fixed up"));
21695 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21696 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21697 _("ADRL used for a symbol not defined in the same file"));
21700 case BFD_RELOC_ARM_OFFSET_IMM
:
21701 if (section
->use_rela_p
)
21703 code
= fixp
->fx_r_type
;
21707 if (fixp
->fx_addsy
!= NULL
21708 && !S_IS_DEFINED (fixp
->fx_addsy
)
21709 && S_IS_LOCAL (fixp
->fx_addsy
))
21711 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21712 _("undefined local label `%s'"),
21713 S_GET_NAME (fixp
->fx_addsy
));
21717 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21718 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21725 switch (fixp
->fx_r_type
)
21727 case BFD_RELOC_NONE
: type
= "NONE"; break;
21728 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21729 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21730 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21731 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21732 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21733 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21734 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21735 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21736 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21737 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21738 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21739 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21740 default: type
= _("<unknown>"); break;
21742 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21743 _("cannot represent %s relocation in this object file format"),
21750 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21752 && fixp
->fx_addsy
== GOT_symbol
)
21754 code
= BFD_RELOC_ARM_GOTPC
;
21755 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21759 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21761 if (reloc
->howto
== NULL
)
21763 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21764 _("cannot represent %s relocation in this object file format"),
21765 bfd_get_reloc_code_name (code
));
21769 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21770 vtable entry to be used in the relocation's section offset. */
21771 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21772 reloc
->address
= fixp
->fx_offset
;
21777 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21780 cons_fix_new_arm (fragS
* frag
,
21785 bfd_reloc_code_real_type type
;
21789 FIXME: @@ Should look at CPU word size. */
21793 type
= BFD_RELOC_8
;
21796 type
= BFD_RELOC_16
;
21800 type
= BFD_RELOC_32
;
21803 type
= BFD_RELOC_64
;
21808 if (exp
->X_op
== O_secrel
)
21810 exp
->X_op
= O_symbol
;
21811 type
= BFD_RELOC_32_SECREL
;
21815 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21818 #if defined (OBJ_COFF)
21820 arm_validate_fix (fixS
* fixP
)
21822 /* If the destination of the branch is a defined symbol which does not have
21823 the THUMB_FUNC attribute, then we must be calling a function which has
21824 the (interfacearm) attribute. We look for the Thumb entry point to that
21825 function and change the branch to refer to that function instead. */
21826 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21827 && fixP
->fx_addsy
!= NULL
21828 && S_IS_DEFINED (fixP
->fx_addsy
)
21829 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21831 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21838 arm_force_relocation (struct fix
* fixp
)
21840 #if defined (OBJ_COFF) && defined (TE_PE)
21841 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21845 /* In case we have a call or a branch to a function in ARM ISA mode from
21846 a thumb function or vice-versa force the relocation. These relocations
21847 are cleared off for some cores that might have blx and simple transformations
21851 switch (fixp
->fx_r_type
)
21853 case BFD_RELOC_ARM_PCREL_JUMP
:
21854 case BFD_RELOC_ARM_PCREL_CALL
:
21855 case BFD_RELOC_THUMB_PCREL_BLX
:
21856 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21860 case BFD_RELOC_ARM_PCREL_BLX
:
21861 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21862 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21863 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21864 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21873 /* Resolve these relocations even if the symbol is extern or weak. */
21874 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21875 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21876 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21877 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21878 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21879 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21880 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21883 /* Always leave these relocations for the linker. */
21884 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21885 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21886 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21889 /* Always generate relocations against function symbols. */
21890 if (fixp
->fx_r_type
== BFD_RELOC_32
21892 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21895 return generic_force_reloc (fixp
);
21898 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21899 /* Relocations against function names must be left unadjusted,
21900 so that the linker can use this information to generate interworking
21901 stubs. The MIPS version of this function
21902 also prevents relocations that are mips-16 specific, but I do not
21903 know why it does this.
21906 There is one other problem that ought to be addressed here, but
21907 which currently is not: Taking the address of a label (rather
21908 than a function) and then later jumping to that address. Such
21909 addresses also ought to have their bottom bit set (assuming that
21910 they reside in Thumb code), but at the moment they will not. */
21913 arm_fix_adjustable (fixS
* fixP
)
21915 if (fixP
->fx_addsy
== NULL
)
21918 /* Preserve relocations against symbols with function type. */
21919 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21922 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21923 && fixP
->fx_subsy
== NULL
)
21926 /* We need the symbol name for the VTABLE entries. */
21927 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21928 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21931 /* Don't allow symbols to be discarded on GOT related relocs. */
21932 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21933 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21934 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21935 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21936 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21937 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21938 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21939 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21940 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
21941 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
21942 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
21943 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
21944 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
21945 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21948 /* Similarly for group relocations. */
21949 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21950 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21951 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21954 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21955 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21956 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21957 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21958 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21959 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21960 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21961 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21962 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21967 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21972 elf32_arm_target_format (void)
21975 return (target_big_endian
21976 ? "elf32-bigarm-symbian"
21977 : "elf32-littlearm-symbian");
21978 #elif defined (TE_VXWORKS)
21979 return (target_big_endian
21980 ? "elf32-bigarm-vxworks"
21981 : "elf32-littlearm-vxworks");
21983 if (target_big_endian
)
21984 return "elf32-bigarm";
21986 return "elf32-littlearm";
21991 armelf_frob_symbol (symbolS
* symp
,
21994 elf_frob_symbol (symp
, puntp
);
21998 /* MD interface: Finalization. */
22003 literal_pool
* pool
;
22005 /* Ensure that all the IT blocks are properly closed. */
22006 check_it_blocks_finished ();
22008 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22010 /* Put it at the end of the relevant section. */
22011 subseg_set (pool
->section
, pool
->sub_section
);
22013 arm_elf_change_section ();
22020 /* Remove any excess mapping symbols generated for alignment frags in
22021 SEC. We may have created a mapping symbol before a zero byte
22022 alignment; remove it if there's a mapping symbol after the
22025 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22026 void *dummy ATTRIBUTE_UNUSED
)
22028 segment_info_type
*seginfo
= seg_info (sec
);
22031 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22034 for (fragp
= seginfo
->frchainP
->frch_root
;
22036 fragp
= fragp
->fr_next
)
22038 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22039 fragS
*next
= fragp
->fr_next
;
22041 /* Variable-sized frags have been converted to fixed size by
22042 this point. But if this was variable-sized to start with,
22043 there will be a fixed-size frag after it. So don't handle
22045 if (sym
== NULL
|| next
== NULL
)
22048 if (S_GET_VALUE (sym
) < next
->fr_address
)
22049 /* Not at the end of this frag. */
22051 know (S_GET_VALUE (sym
) == next
->fr_address
);
22055 if (next
->tc_frag_data
.first_map
!= NULL
)
22057 /* Next frag starts with a mapping symbol. Discard this
22059 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22063 if (next
->fr_next
== NULL
)
22065 /* This mapping symbol is at the end of the section. Discard
22067 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22068 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22072 /* As long as we have empty frags without any mapping symbols,
22074 /* If the next frag is non-empty and does not start with a
22075 mapping symbol, then this mapping symbol is required. */
22076 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22079 next
= next
->fr_next
;
22081 while (next
!= NULL
);
22086 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22090 arm_adjust_symtab (void)
22095 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22097 if (ARM_IS_THUMB (sym
))
22099 if (THUMB_IS_FUNC (sym
))
22101 /* Mark the symbol as a Thumb function. */
22102 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22103 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22104 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22106 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22107 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22109 as_bad (_("%s: unexpected function type: %d"),
22110 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22112 else switch (S_GET_STORAGE_CLASS (sym
))
22115 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22118 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22121 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22129 if (ARM_IS_INTERWORK (sym
))
22130 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22137 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22139 if (ARM_IS_THUMB (sym
))
22141 elf_symbol_type
* elf_sym
;
22143 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22144 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22146 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22147 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22149 /* If it's a .thumb_func, declare it as so,
22150 otherwise tag label as .code 16. */
22151 if (THUMB_IS_FUNC (sym
))
22152 elf_sym
->internal_elf_sym
.st_target_internal
22153 = ST_BRANCH_TO_THUMB
;
22154 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22155 elf_sym
->internal_elf_sym
.st_info
=
22156 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22161 /* Remove any overlapping mapping symbols generated by alignment frags. */
22162 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22163 /* Now do generic ELF adjustments. */
22164 elf_adjust_symtab ();
22168 /* MD interface: Initialization. */
22171 set_constant_flonums (void)
22175 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22176 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22180 /* Auto-select Thumb mode if it's the only available instruction set for the
22181 given architecture. */
22184 autoselect_thumb_from_cpu_variant (void)
22186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22187 opcode_select (16);
22196 if ( (arm_ops_hsh
= hash_new ()) == NULL
22197 || (arm_cond_hsh
= hash_new ()) == NULL
22198 || (arm_shift_hsh
= hash_new ()) == NULL
22199 || (arm_psr_hsh
= hash_new ()) == NULL
22200 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22201 || (arm_reg_hsh
= hash_new ()) == NULL
22202 || (arm_reloc_hsh
= hash_new ()) == NULL
22203 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22204 as_fatal (_("virtual memory exhausted"));
22206 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22207 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22208 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22209 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22210 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22211 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22212 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22213 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22214 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22215 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22216 (void *) (v7m_psrs
+ i
));
22217 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22218 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22220 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22222 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22223 (void *) (barrier_opt_names
+ i
));
22225 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22226 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22229 set_constant_flonums ();
22231 /* Set the cpu variant based on the command-line options. We prefer
22232 -mcpu= over -march= if both are set (as for GCC); and we prefer
22233 -mfpu= over any other way of setting the floating point unit.
22234 Use of legacy options with new options are faulted. */
22237 if (mcpu_cpu_opt
|| march_cpu_opt
)
22238 as_bad (_("use of old and new-style options to set CPU type"));
22240 mcpu_cpu_opt
= legacy_cpu
;
22242 else if (!mcpu_cpu_opt
)
22243 mcpu_cpu_opt
= march_cpu_opt
;
22248 as_bad (_("use of old and new-style options to set FPU type"));
22250 mfpu_opt
= legacy_fpu
;
22252 else if (!mfpu_opt
)
22254 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22255 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22256 /* Some environments specify a default FPU. If they don't, infer it
22257 from the processor. */
22259 mfpu_opt
= mcpu_fpu_opt
;
22261 mfpu_opt
= march_fpu_opt
;
22263 mfpu_opt
= &fpu_default
;
22269 if (mcpu_cpu_opt
!= NULL
)
22270 mfpu_opt
= &fpu_default
;
22271 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22272 mfpu_opt
= &fpu_arch_vfp_v2
;
22274 mfpu_opt
= &fpu_arch_fpa
;
22280 mcpu_cpu_opt
= &cpu_default
;
22281 selected_cpu
= cpu_default
;
22285 selected_cpu
= *mcpu_cpu_opt
;
22287 mcpu_cpu_opt
= &arm_arch_any
;
22290 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22292 autoselect_thumb_from_cpu_variant ();
22294 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22296 #if defined OBJ_COFF || defined OBJ_ELF
22298 unsigned int flags
= 0;
22300 #if defined OBJ_ELF
22301 flags
= meabi_flags
;
22303 switch (meabi_flags
)
22305 case EF_ARM_EABI_UNKNOWN
:
22307 /* Set the flags in the private structure. */
22308 if (uses_apcs_26
) flags
|= F_APCS26
;
22309 if (support_interwork
) flags
|= F_INTERWORK
;
22310 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22311 if (pic_code
) flags
|= F_PIC
;
22312 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22313 flags
|= F_SOFT_FLOAT
;
22315 switch (mfloat_abi_opt
)
22317 case ARM_FLOAT_ABI_SOFT
:
22318 case ARM_FLOAT_ABI_SOFTFP
:
22319 flags
|= F_SOFT_FLOAT
;
22322 case ARM_FLOAT_ABI_HARD
:
22323 if (flags
& F_SOFT_FLOAT
)
22324 as_bad (_("hard-float conflicts with specified fpu"));
22328 /* Using pure-endian doubles (even if soft-float). */
22329 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22330 flags
|= F_VFP_FLOAT
;
22332 #if defined OBJ_ELF
22333 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22334 flags
|= EF_ARM_MAVERICK_FLOAT
;
22337 case EF_ARM_EABI_VER4
:
22338 case EF_ARM_EABI_VER5
:
22339 /* No additional flags to set. */
22346 bfd_set_private_flags (stdoutput
, flags
);
22348 /* We have run out flags in the COFF header to encode the
22349 status of ATPCS support, so instead we create a dummy,
22350 empty, debug section called .arm.atpcs. */
22355 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22359 bfd_set_section_flags
22360 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22361 bfd_set_section_size (stdoutput
, sec
, 0);
22362 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22368 /* Record the CPU type as well. */
22369 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22370 mach
= bfd_mach_arm_iWMMXt2
;
22371 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22372 mach
= bfd_mach_arm_iWMMXt
;
22373 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22374 mach
= bfd_mach_arm_XScale
;
22375 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22376 mach
= bfd_mach_arm_ep9312
;
22377 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22378 mach
= bfd_mach_arm_5TE
;
22379 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22381 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22382 mach
= bfd_mach_arm_5T
;
22384 mach
= bfd_mach_arm_5
;
22386 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22389 mach
= bfd_mach_arm_4T
;
22391 mach
= bfd_mach_arm_4
;
22393 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22394 mach
= bfd_mach_arm_3M
;
22395 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22396 mach
= bfd_mach_arm_3
;
22397 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22398 mach
= bfd_mach_arm_2a
;
22399 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22400 mach
= bfd_mach_arm_2
;
22402 mach
= bfd_mach_arm_unknown
;
22404 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22407 /* Command line processing. */
22410 Invocation line includes a switch not recognized by the base assembler.
22411 See if it's a processor-specific option.
22413 This routine is somewhat complicated by the need for backwards
22414 compatibility (since older releases of gcc can't be changed).
22415 The new options try to make the interface as compatible as
22418 New options (supported) are:
22420 -mcpu=<cpu name> Assemble for selected processor
22421 -march=<architecture name> Assemble for selected architecture
22422 -mfpu=<fpu architecture> Assemble for selected FPU.
22423 -EB/-mbig-endian Big-endian
22424 -EL/-mlittle-endian Little-endian
22425 -k Generate PIC code
22426 -mthumb Start in Thumb mode
22427 -mthumb-interwork Code supports ARM/Thumb interworking
22429 -m[no-]warn-deprecated Warn about deprecated features
22431 For now we will also provide support for:
22433 -mapcs-32 32-bit Program counter
22434 -mapcs-26 26-bit Program counter
22435 -macps-float Floats passed in FP registers
22436 -mapcs-reentrant Reentrant code
22438 (sometime these will probably be replaced with -mapcs=<list of options>
22439 and -matpcs=<list of options>)
22441 The remaining options are only supported for back-wards compatibility.
22442 Cpu variants, the arm part is optional:
22443 -m[arm]1 Currently not supported.
22444 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22445 -m[arm]3 Arm 3 processor
22446 -m[arm]6[xx], Arm 6 processors
22447 -m[arm]7[xx][t][[d]m] Arm 7 processors
22448 -m[arm]8[10] Arm 8 processors
22449 -m[arm]9[20][tdmi] Arm 9 processors
22450 -mstrongarm[110[0]] StrongARM processors
22451 -mxscale XScale processors
22452 -m[arm]v[2345[t[e]]] Arm architectures
22453 -mall All (except the ARM1)
22455 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22456 -mfpe-old (No float load/store multiples)
22457 -mvfpxd VFP Single precision
22459 -mno-fpu Disable all floating point instructions
22461 The following CPU names are recognized:
22462 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22463 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22464 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22465 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22466 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22467 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22468 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22472 const char * md_shortopts
= "m:k";
22474 #ifdef ARM_BI_ENDIAN
22475 #define OPTION_EB (OPTION_MD_BASE + 0)
22476 #define OPTION_EL (OPTION_MD_BASE + 1)
22478 #if TARGET_BYTES_BIG_ENDIAN
22479 #define OPTION_EB (OPTION_MD_BASE + 0)
22481 #define OPTION_EL (OPTION_MD_BASE + 1)
22484 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22486 struct option md_longopts
[] =
22489 {"EB", no_argument
, NULL
, OPTION_EB
},
22492 {"EL", no_argument
, NULL
, OPTION_EL
},
22494 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22495 {NULL
, no_argument
, NULL
, 0}
22498 size_t md_longopts_size
= sizeof (md_longopts
);
22500 struct arm_option_table
22502 char *option
; /* Option name to match. */
22503 char *help
; /* Help information. */
22504 int *var
; /* Variable to change. */
22505 int value
; /* What to change it to. */
22506 char *deprecated
; /* If non-null, print this message. */
22509 struct arm_option_table arm_opts
[] =
22511 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22512 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22513 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22514 &support_interwork
, 1, NULL
},
22515 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22516 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22517 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22519 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22520 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22521 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22522 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22525 /* These are recognized by the assembler, but have no affect on code. */
22526 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22527 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22529 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22530 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22531 &warn_on_deprecated
, 0, NULL
},
22532 {NULL
, NULL
, NULL
, 0, NULL
}
22535 struct arm_legacy_option_table
22537 char *option
; /* Option name to match. */
22538 const arm_feature_set
**var
; /* Variable to change. */
22539 const arm_feature_set value
; /* What to change it to. */
22540 char *deprecated
; /* If non-null, print this message. */
22543 const struct arm_legacy_option_table arm_legacy_opts
[] =
22545 /* DON'T add any new processors to this list -- we want the whole list
22546 to go away... Add them to the processors table instead. */
22547 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22548 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22549 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22550 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22551 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22552 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22553 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22554 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22555 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22556 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22557 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22558 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22559 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22560 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22561 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22562 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22563 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22564 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22565 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22566 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22567 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22568 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22569 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22570 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22571 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22572 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22573 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22574 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22575 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22576 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22577 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22578 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22579 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22580 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22581 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22582 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22583 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22584 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22585 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22586 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22587 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22588 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22589 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22590 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22591 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22592 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22593 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22594 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22595 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22596 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22597 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22598 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22599 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22600 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22601 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22602 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22603 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22604 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22605 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22606 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22607 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22608 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22609 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22610 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22611 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22612 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22613 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22614 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22615 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22616 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22617 N_("use -mcpu=strongarm110")},
22618 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22619 N_("use -mcpu=strongarm1100")},
22620 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22621 N_("use -mcpu=strongarm1110")},
22622 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22623 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22624 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22626 /* Architecture variants -- don't add any more to this list either. */
22627 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22628 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22629 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22630 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22631 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22632 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22633 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22634 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22635 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22636 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22637 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22638 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22639 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22640 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22641 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22642 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22643 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22644 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22646 /* Floating point variants -- don't add any more to this list either. */
22647 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22648 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22649 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22650 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22651 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22653 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22656 struct arm_cpu_option_table
22659 const arm_feature_set value
;
22660 /* For some CPUs we assume an FPU unless the user explicitly sets
22662 const arm_feature_set default_fpu
;
22663 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22665 const char *canonical_name
;
22668 /* This list should, at a minimum, contain all the cpu names
22669 recognized by GCC. */
22670 static const struct arm_cpu_option_table arm_cpus
[] =
22672 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22673 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22674 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22675 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22676 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22677 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22678 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22679 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22680 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22681 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22682 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22683 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22684 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22685 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22686 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22687 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22688 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22689 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22690 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22691 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22692 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22693 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22694 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22695 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22696 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22697 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22698 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22699 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22700 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22701 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22702 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22703 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22704 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22705 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22706 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22707 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22708 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22709 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22710 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22711 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22712 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22713 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22714 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22715 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22716 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22717 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22718 /* For V5 or later processors we default to using VFP; but the user
22719 should really set the FPU type explicitly. */
22720 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22721 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22722 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22723 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22724 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22725 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22726 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22727 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22728 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22729 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22730 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22731 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22732 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22733 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22734 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22735 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22736 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22737 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22738 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22739 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22740 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22741 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22742 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22743 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22744 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22745 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22746 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22747 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22748 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22749 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22750 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22751 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22752 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22753 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22754 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22755 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22756 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22757 FPU_NONE
, "Cortex-A5"},
22758 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22759 ARM_FEATURE (0, FPU_VFP_V3
22760 | FPU_NEON_EXT_V1
),
22762 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22763 ARM_FEATURE (0, FPU_VFP_V3
22764 | FPU_NEON_EXT_V1
),
22766 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22767 FPU_ARCH_NEON_VFP_V4
,
22769 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22770 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22772 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22773 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22774 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22775 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22776 /* ??? XSCALE is really an architecture. */
22777 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22778 /* ??? iwmmxt is not a processor. */
22779 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22780 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22781 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22783 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22784 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22787 struct arm_arch_option_table
22790 const arm_feature_set value
;
22791 const arm_feature_set default_fpu
;
22794 /* This list should, at a minimum, contain all the architecture names
22795 recognized by GCC. */
22796 static const struct arm_arch_option_table arm_archs
[] =
22798 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22799 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22800 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22801 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22802 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22803 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22804 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22805 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22806 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22807 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22808 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22809 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22810 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22811 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22812 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22813 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22814 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22815 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22816 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22817 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22818 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22819 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22820 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22821 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22822 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22823 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22824 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22825 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22826 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22827 /* The official spelling of the ARMv7 profile variants is the dashed form.
22828 Accept the non-dashed form for compatibility with old toolchains. */
22829 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22830 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22831 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22832 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22833 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22834 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22835 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22836 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22837 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22838 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22839 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22842 /* ISA extensions in the co-processor and main instruction set space. */
22843 struct arm_option_extension_value_table
22846 const arm_feature_set value
;
22847 const arm_feature_set allowed_archs
;
22850 /* The following table must be in alphabetical order with a NULL last entry.
22852 static const struct arm_option_extension_value_table arm_extensions
[] =
22854 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22855 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22856 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22857 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22858 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22859 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22860 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22861 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22862 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22863 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22864 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22865 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22866 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22867 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22868 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22871 /* ISA floating-point and Advanced SIMD extensions. */
22872 struct arm_option_fpu_value_table
22875 const arm_feature_set value
;
22878 /* This list should, at a minimum, contain all the fpu names
22879 recognized by GCC. */
22880 static const struct arm_option_fpu_value_table arm_fpus
[] =
22882 {"softfpa", FPU_NONE
},
22883 {"fpe", FPU_ARCH_FPE
},
22884 {"fpe2", FPU_ARCH_FPE
},
22885 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22886 {"fpa", FPU_ARCH_FPA
},
22887 {"fpa10", FPU_ARCH_FPA
},
22888 {"fpa11", FPU_ARCH_FPA
},
22889 {"arm7500fe", FPU_ARCH_FPA
},
22890 {"softvfp", FPU_ARCH_VFP
},
22891 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22892 {"vfp", FPU_ARCH_VFP_V2
},
22893 {"vfp9", FPU_ARCH_VFP_V2
},
22894 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22895 {"vfp10", FPU_ARCH_VFP_V2
},
22896 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22897 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22898 {"vfpv2", FPU_ARCH_VFP_V2
},
22899 {"vfpv3", FPU_ARCH_VFP_V3
},
22900 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22901 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22902 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22903 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22904 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22905 {"arm1020t", FPU_ARCH_VFP_V1
},
22906 {"arm1020e", FPU_ARCH_VFP_V2
},
22907 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22908 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22909 {"maverick", FPU_ARCH_MAVERICK
},
22910 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22911 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22912 {"vfpv4", FPU_ARCH_VFP_V4
},
22913 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22914 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22915 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22916 {NULL
, ARM_ARCH_NONE
}
22919 struct arm_option_value_table
22925 static const struct arm_option_value_table arm_float_abis
[] =
22927 {"hard", ARM_FLOAT_ABI_HARD
},
22928 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22929 {"soft", ARM_FLOAT_ABI_SOFT
},
22934 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22935 static const struct arm_option_value_table arm_eabis
[] =
22937 {"gnu", EF_ARM_EABI_UNKNOWN
},
22938 {"4", EF_ARM_EABI_VER4
},
22939 {"5", EF_ARM_EABI_VER5
},
22944 struct arm_long_option_table
22946 char * option
; /* Substring to match. */
22947 char * help
; /* Help information. */
22948 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22949 char * deprecated
; /* If non-null, print this message. */
22953 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22955 arm_feature_set
*ext_set
= (arm_feature_set
*)
22956 xmalloc (sizeof (arm_feature_set
));
22958 /* We insist on extensions being specified in alphabetical order, and with
22959 extensions being added before being removed. We achieve this by having
22960 the global ARM_EXTENSIONS table in alphabetical order, and using the
22961 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22962 or removing it (0) and only allowing it to change in the order
22964 const struct arm_option_extension_value_table
* opt
= NULL
;
22965 int adding_value
= -1;
22967 /* Copy the feature set, so that we can modify it. */
22968 *ext_set
= **opt_p
;
22971 while (str
!= NULL
&& *str
!= 0)
22978 as_bad (_("invalid architectural extension"));
22983 ext
= strchr (str
, '+');
22986 optlen
= ext
- str
;
22988 optlen
= strlen (str
);
22991 && strncmp (str
, "no", 2) == 0)
22993 if (adding_value
!= 0)
22996 opt
= arm_extensions
;
23002 else if (optlen
> 0)
23004 if (adding_value
== -1)
23007 opt
= arm_extensions
;
23009 else if (adding_value
!= 1)
23011 as_bad (_("must specify extensions to add before specifying "
23012 "those to remove"));
23019 as_bad (_("missing architectural extension"));
23023 gas_assert (adding_value
!= -1);
23024 gas_assert (opt
!= NULL
);
23026 /* Scan over the options table trying to find an exact match. */
23027 for (; opt
->name
!= NULL
; opt
++)
23028 if (strncmp (opt
->name
, str
, optlen
) == 0
23029 && strlen (opt
->name
) == optlen
)
23031 /* Check we can apply the extension to this architecture. */
23032 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23034 as_bad (_("extension does not apply to the base architecture"));
23038 /* Add or remove the extension. */
23040 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23042 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23047 if (opt
->name
== NULL
)
23049 /* Did we fail to find an extension because it wasn't specified in
23050 alphabetical order, or because it does not exist? */
23052 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23053 if (strncmp (opt
->name
, str
, optlen
) == 0)
23056 if (opt
->name
== NULL
)
23057 as_bad (_("unknown architectural extension `%s'"), str
);
23059 as_bad (_("architectural extensions must be specified in "
23060 "alphabetical order"));
23066 /* We should skip the extension we've just matched the next time
23078 arm_parse_cpu (char * str
)
23080 const struct arm_cpu_option_table
* opt
;
23081 char * ext
= strchr (str
, '+');
23085 optlen
= ext
- str
;
23087 optlen
= strlen (str
);
23091 as_bad (_("missing cpu name `%s'"), str
);
23095 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23096 if (strncmp (opt
->name
, str
, optlen
) == 0)
23098 mcpu_cpu_opt
= &opt
->value
;
23099 mcpu_fpu_opt
= &opt
->default_fpu
;
23100 if (opt
->canonical_name
)
23101 strcpy (selected_cpu_name
, opt
->canonical_name
);
23106 for (i
= 0; i
< optlen
; i
++)
23107 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23108 selected_cpu_name
[i
] = 0;
23112 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23117 as_bad (_("unknown cpu `%s'"), str
);
23122 arm_parse_arch (char * str
)
23124 const struct arm_arch_option_table
*opt
;
23125 char *ext
= strchr (str
, '+');
23129 optlen
= ext
- str
;
23131 optlen
= strlen (str
);
23135 as_bad (_("missing architecture name `%s'"), str
);
23139 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23140 if (strncmp (opt
->name
, str
, optlen
) == 0)
23142 march_cpu_opt
= &opt
->value
;
23143 march_fpu_opt
= &opt
->default_fpu
;
23144 strcpy (selected_cpu_name
, opt
->name
);
23147 return arm_parse_extension (ext
, &march_cpu_opt
);
23152 as_bad (_("unknown architecture `%s'\n"), str
);
23157 arm_parse_fpu (char * str
)
23159 const struct arm_option_fpu_value_table
* opt
;
23161 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23162 if (streq (opt
->name
, str
))
23164 mfpu_opt
= &opt
->value
;
23168 as_bad (_("unknown floating point format `%s'\n"), str
);
23173 arm_parse_float_abi (char * str
)
23175 const struct arm_option_value_table
* opt
;
23177 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23178 if (streq (opt
->name
, str
))
23180 mfloat_abi_opt
= opt
->value
;
23184 as_bad (_("unknown floating point abi `%s'\n"), str
);
23190 arm_parse_eabi (char * str
)
23192 const struct arm_option_value_table
*opt
;
23194 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23195 if (streq (opt
->name
, str
))
23197 meabi_flags
= opt
->value
;
23200 as_bad (_("unknown EABI `%s'\n"), str
);
23206 arm_parse_it_mode (char * str
)
23208 bfd_boolean ret
= TRUE
;
23210 if (streq ("arm", str
))
23211 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23212 else if (streq ("thumb", str
))
23213 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23214 else if (streq ("always", str
))
23215 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23216 else if (streq ("never", str
))
23217 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23220 as_bad (_("unknown implicit IT mode `%s', should be "\
23221 "arm, thumb, always, or never."), str
);
23228 struct arm_long_option_table arm_long_opts
[] =
23230 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23231 arm_parse_cpu
, NULL
},
23232 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23233 arm_parse_arch
, NULL
},
23234 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23235 arm_parse_fpu
, NULL
},
23236 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23237 arm_parse_float_abi
, NULL
},
23239 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23240 arm_parse_eabi
, NULL
},
23242 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23243 arm_parse_it_mode
, NULL
},
23244 {NULL
, NULL
, 0, NULL
}
23248 md_parse_option (int c
, char * arg
)
23250 struct arm_option_table
*opt
;
23251 const struct arm_legacy_option_table
*fopt
;
23252 struct arm_long_option_table
*lopt
;
23258 target_big_endian
= 1;
23264 target_big_endian
= 0;
23268 case OPTION_FIX_V4BX
:
23273 /* Listing option. Just ignore these, we don't support additional
23278 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23280 if (c
== opt
->option
[0]
23281 && ((arg
== NULL
&& opt
->option
[1] == 0)
23282 || streq (arg
, opt
->option
+ 1)))
23284 /* If the option is deprecated, tell the user. */
23285 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23286 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23287 arg
? arg
: "", _(opt
->deprecated
));
23289 if (opt
->var
!= NULL
)
23290 *opt
->var
= opt
->value
;
23296 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23298 if (c
== fopt
->option
[0]
23299 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23300 || streq (arg
, fopt
->option
+ 1)))
23302 /* If the option is deprecated, tell the user. */
23303 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23304 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23305 arg
? arg
: "", _(fopt
->deprecated
));
23307 if (fopt
->var
!= NULL
)
23308 *fopt
->var
= &fopt
->value
;
23314 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23316 /* These options are expected to have an argument. */
23317 if (c
== lopt
->option
[0]
23319 && strncmp (arg
, lopt
->option
+ 1,
23320 strlen (lopt
->option
+ 1)) == 0)
23322 /* If the option is deprecated, tell the user. */
23323 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23324 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23325 _(lopt
->deprecated
));
23327 /* Call the sup-option parser. */
23328 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23339 md_show_usage (FILE * fp
)
23341 struct arm_option_table
*opt
;
23342 struct arm_long_option_table
*lopt
;
23344 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23346 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23347 if (opt
->help
!= NULL
)
23348 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23350 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23351 if (lopt
->help
!= NULL
)
23352 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23356 -EB assemble code for a big-endian cpu\n"));
23361 -EL assemble code for a little-endian cpu\n"));
23365 --fix-v4bx Allow BX in ARMv4 code\n"));
23373 arm_feature_set flags
;
23374 } cpu_arch_ver_table
;
23376 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23377 least features first. */
23378 static const cpu_arch_ver_table cpu_arch_ver
[] =
23384 {4, ARM_ARCH_V5TE
},
23385 {5, ARM_ARCH_V5TEJ
},
23389 {11, ARM_ARCH_V6M
},
23390 {12, ARM_ARCH_V6SM
},
23391 {8, ARM_ARCH_V6T2
},
23392 {10, ARM_ARCH_V7A
},
23393 {10, ARM_ARCH_V7R
},
23394 {10, ARM_ARCH_V7M
},
23398 /* Set an attribute if it has not already been set by the user. */
23400 aeabi_set_attribute_int (int tag
, int value
)
23403 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23404 || !attributes_set_explicitly
[tag
])
23405 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23409 aeabi_set_attribute_string (int tag
, const char *value
)
23412 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23413 || !attributes_set_explicitly
[tag
])
23414 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23417 /* Set the public EABI object attributes. */
23419 aeabi_set_public_attributes (void)
23423 arm_feature_set flags
;
23424 arm_feature_set tmp
;
23425 const cpu_arch_ver_table
*p
;
23427 /* Choose the architecture based on the capabilities of the requested cpu
23428 (if any) and/or the instructions actually used. */
23429 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23430 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23431 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23432 /*Allow the user to override the reported architecture. */
23435 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23436 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23439 /* We need to make sure that the attributes do not identify us as v6S-M
23440 when the only v6S-M feature in use is the Operating System Extensions. */
23441 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23442 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23443 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23447 for (p
= cpu_arch_ver
; p
->val
; p
++)
23449 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23452 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23456 /* The table lookup above finds the last architecture to contribute
23457 a new feature. Unfortunately, Tag13 is a subset of the union of
23458 v6T2 and v7-M, so it is never seen as contributing a new feature.
23459 We can not search for the last entry which is entirely used,
23460 because if no CPU is specified we build up only those flags
23461 actually used. Perhaps we should separate out the specified
23462 and implicit cases. Avoid taking this path for -march=all by
23463 checking for contradictory v7-A / v7-M features. */
23465 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23466 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23467 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23470 /* Tag_CPU_name. */
23471 if (selected_cpu_name
[0])
23475 q
= selected_cpu_name
;
23476 if (strncmp (q
, "armv", 4) == 0)
23481 for (i
= 0; q
[i
]; i
++)
23482 q
[i
] = TOUPPER (q
[i
]);
23484 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23487 /* Tag_CPU_arch. */
23488 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23490 /* Tag_CPU_arch_profile. */
23491 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23492 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23493 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23494 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23495 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23496 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23498 /* Tag_ARM_ISA_use. */
23499 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23501 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23503 /* Tag_THUMB_ISA_use. */
23504 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23506 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23507 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23509 /* Tag_VFP_arch. */
23510 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23511 aeabi_set_attribute_int (Tag_VFP_arch
,
23512 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23514 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23515 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23516 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23517 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23518 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23519 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23520 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23521 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23522 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23524 /* Tag_ABI_HardFP_use. */
23525 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23526 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23527 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23529 /* Tag_WMMX_arch. */
23530 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23531 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23532 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23533 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23535 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23536 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23537 aeabi_set_attribute_int
23538 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23541 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23542 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23543 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23546 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23547 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23548 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23549 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23551 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23553 /* Tag_MP_extension_use. */
23554 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23555 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23557 /* Tag Virtualization_use. */
23558 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23560 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23563 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23566 /* Add the default contents for the .ARM.attributes section. */
23570 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23573 aeabi_set_public_attributes ();
23575 #endif /* OBJ_ELF */
23578 /* Parse a .cpu directive. */
23581 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23583 const struct arm_cpu_option_table
*opt
;
23587 name
= input_line_pointer
;
23588 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23589 input_line_pointer
++;
23590 saved_char
= *input_line_pointer
;
23591 *input_line_pointer
= 0;
23593 /* Skip the first "all" entry. */
23594 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23595 if (streq (opt
->name
, name
))
23597 mcpu_cpu_opt
= &opt
->value
;
23598 selected_cpu
= opt
->value
;
23599 if (opt
->canonical_name
)
23600 strcpy (selected_cpu_name
, opt
->canonical_name
);
23604 for (i
= 0; opt
->name
[i
]; i
++)
23605 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23606 selected_cpu_name
[i
] = 0;
23608 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23609 *input_line_pointer
= saved_char
;
23610 demand_empty_rest_of_line ();
23613 as_bad (_("unknown cpu `%s'"), name
);
23614 *input_line_pointer
= saved_char
;
23615 ignore_rest_of_line ();
23619 /* Parse a .arch directive. */
23622 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23624 const struct arm_arch_option_table
*opt
;
23628 name
= input_line_pointer
;
23629 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23630 input_line_pointer
++;
23631 saved_char
= *input_line_pointer
;
23632 *input_line_pointer
= 0;
23634 /* Skip the first "all" entry. */
23635 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23636 if (streq (opt
->name
, name
))
23638 mcpu_cpu_opt
= &opt
->value
;
23639 selected_cpu
= opt
->value
;
23640 strcpy (selected_cpu_name
, opt
->name
);
23641 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23642 *input_line_pointer
= saved_char
;
23643 demand_empty_rest_of_line ();
23647 as_bad (_("unknown architecture `%s'\n"), name
);
23648 *input_line_pointer
= saved_char
;
23649 ignore_rest_of_line ();
23653 /* Parse a .object_arch directive. */
23656 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23658 const struct arm_arch_option_table
*opt
;
23662 name
= input_line_pointer
;
23663 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23664 input_line_pointer
++;
23665 saved_char
= *input_line_pointer
;
23666 *input_line_pointer
= 0;
23668 /* Skip the first "all" entry. */
23669 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23670 if (streq (opt
->name
, name
))
23672 object_arch
= &opt
->value
;
23673 *input_line_pointer
= saved_char
;
23674 demand_empty_rest_of_line ();
23678 as_bad (_("unknown architecture `%s'\n"), name
);
23679 *input_line_pointer
= saved_char
;
23680 ignore_rest_of_line ();
23683 /* Parse a .arch_extension directive. */
23686 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23688 const struct arm_option_extension_value_table
*opt
;
23691 int adding_value
= 1;
23693 name
= input_line_pointer
;
23694 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23695 input_line_pointer
++;
23696 saved_char
= *input_line_pointer
;
23697 *input_line_pointer
= 0;
23699 if (strlen (name
) >= 2
23700 && strncmp (name
, "no", 2) == 0)
23706 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23707 if (streq (opt
->name
, name
))
23709 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23711 as_bad (_("architectural extension `%s' is not allowed for the "
23712 "current base architecture"), name
);
23717 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23719 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23721 mcpu_cpu_opt
= &selected_cpu
;
23722 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23723 *input_line_pointer
= saved_char
;
23724 demand_empty_rest_of_line ();
23728 if (opt
->name
== NULL
)
23729 as_bad (_("unknown architecture `%s'\n"), name
);
23731 *input_line_pointer
= saved_char
;
23732 ignore_rest_of_line ();
23735 /* Parse a .fpu directive. */
23738 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23740 const struct arm_option_fpu_value_table
*opt
;
23744 name
= input_line_pointer
;
23745 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23746 input_line_pointer
++;
23747 saved_char
= *input_line_pointer
;
23748 *input_line_pointer
= 0;
23750 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23751 if (streq (opt
->name
, name
))
23753 mfpu_opt
= &opt
->value
;
23754 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23755 *input_line_pointer
= saved_char
;
23756 demand_empty_rest_of_line ();
23760 as_bad (_("unknown floating point format `%s'\n"), name
);
23761 *input_line_pointer
= saved_char
;
23762 ignore_rest_of_line ();
23765 /* Copy symbol information. */
23768 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23770 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23774 /* Given a symbolic attribute NAME, return the proper integer value.
23775 Returns -1 if the attribute is not known. */
23778 arm_convert_symbolic_attribute (const char *name
)
23780 static const struct
23785 attribute_table
[] =
23787 /* When you modify this table you should
23788 also modify the list in doc/c-arm.texi. */
23789 #define T(tag) {#tag, tag}
23790 T (Tag_CPU_raw_name
),
23793 T (Tag_CPU_arch_profile
),
23794 T (Tag_ARM_ISA_use
),
23795 T (Tag_THUMB_ISA_use
),
23799 T (Tag_Advanced_SIMD_arch
),
23800 T (Tag_PCS_config
),
23801 T (Tag_ABI_PCS_R9_use
),
23802 T (Tag_ABI_PCS_RW_data
),
23803 T (Tag_ABI_PCS_RO_data
),
23804 T (Tag_ABI_PCS_GOT_use
),
23805 T (Tag_ABI_PCS_wchar_t
),
23806 T (Tag_ABI_FP_rounding
),
23807 T (Tag_ABI_FP_denormal
),
23808 T (Tag_ABI_FP_exceptions
),
23809 T (Tag_ABI_FP_user_exceptions
),
23810 T (Tag_ABI_FP_number_model
),
23811 T (Tag_ABI_align_needed
),
23812 T (Tag_ABI_align8_needed
),
23813 T (Tag_ABI_align_preserved
),
23814 T (Tag_ABI_align8_preserved
),
23815 T (Tag_ABI_enum_size
),
23816 T (Tag_ABI_HardFP_use
),
23817 T (Tag_ABI_VFP_args
),
23818 T (Tag_ABI_WMMX_args
),
23819 T (Tag_ABI_optimization_goals
),
23820 T (Tag_ABI_FP_optimization_goals
),
23821 T (Tag_compatibility
),
23822 T (Tag_CPU_unaligned_access
),
23823 T (Tag_FP_HP_extension
),
23824 T (Tag_VFP_HP_extension
),
23825 T (Tag_ABI_FP_16bit_format
),
23826 T (Tag_MPextension_use
),
23828 T (Tag_nodefaults
),
23829 T (Tag_also_compatible_with
),
23830 T (Tag_conformance
),
23832 T (Tag_Virtualization_use
),
23833 /* We deliberately do not include Tag_MPextension_use_legacy. */
23841 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23842 if (streq (name
, attribute_table
[i
].name
))
23843 return attribute_table
[i
].tag
;
23849 /* Apply sym value for relocations only in the case that
23850 they are for local symbols and you have the respective
23851 architectural feature for blx and simple switches. */
23853 arm_apply_sym_value (struct fix
* fixP
)
23856 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23857 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
23859 switch (fixP
->fx_r_type
)
23861 case BFD_RELOC_ARM_PCREL_BLX
:
23862 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23863 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23867 case BFD_RELOC_ARM_PCREL_CALL
:
23868 case BFD_RELOC_THUMB_PCREL_BLX
:
23869 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23880 #endif /* OBJ_ELF */