1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "safe-ctype.h"
29 /* Need TARGET_CPU. */
38 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
42 #define ARM_1 0x00000001
43 #define ARM_2 0x00000002
44 #define ARM_3 0x00000004
46 #define ARM_6 0x00000008
47 #define ARM_7 ARM_6 /* Same core instruction set. */
48 #define ARM_8 ARM_6 /* Same core instruction set. */
49 #define ARM_9 ARM_6 /* Same core instruction set. */
50 #define ARM_CPU_MASK 0x0000000f
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
54 #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
55 #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
56 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
58 #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
60 /* Architectures are the sum of the base and extensions. */
61 #define ARM_ARCH_V3M ARM_EXT_LONGMUL
62 #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
63 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
64 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
65 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
66 #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
67 #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
69 /* Some useful combinations: */
70 #define ARM_ANY 0x00ffffff
71 #define ARM_2UP (ARM_ANY - ARM_1)
72 #define ARM_ALL ARM_2UP /* Not arm1 only. */
73 #define ARM_3UP 0x00fffffc
74 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
76 #define FPU_CORE 0x80000000
77 #define FPU_FPA10 0x40000000
78 #define FPU_FPA11 0x40000000
81 /* Some useful combinations. */
82 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
83 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
86 #if defined __XSCALE__
87 #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
90 #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
92 #define CPU_DEFAULT ARM_ALL
98 #define FPU_DEFAULT FPU_ALL
101 #define streq(a, b) (strcmp (a, b) == 0)
102 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
104 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
105 static int target_oabi
= 0;
107 #if defined OBJ_COFF || defined OBJ_ELF
108 /* Flags stored in private area of BFD structure. */
109 static boolean uses_apcs_26
= false;
110 static boolean atpcs
= false;
111 static boolean support_interwork
= false;
112 static boolean uses_apcs_float
= false;
113 static boolean pic_code
= false;
116 /* This array holds the chars that always start a comment. If the
117 pre-processor is disabled, these aren't very useful. */
118 CONST
char comment_chars
[] = "@";
120 /* This array holds the chars that only start a comment at the beginning of
121 a line. If the line seems to have the form '# 123 filename'
122 .line and .file directives will appear in the pre-processed output. */
123 /* Note that input_file.c hand checks for '#' at the beginning of the
124 first line of the input file. This is because the compiler outputs
125 #NO_APP at the beginning of its output. */
126 /* Also note that comments like this one will always work. */
127 CONST
char line_comment_chars
[] = "#";
129 CONST
char line_separator_chars
[] = ";";
131 /* Chars that can be used to separate mant
132 from exp in floating point numbers. */
133 CONST
char EXP_CHARS
[] = "eE";
135 /* Chars that mean this number is a floating point constant. */
139 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
141 /* Prefix characters that indicate the start of an immediate
143 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
146 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
147 symbolS
* GOT_symbol
;
150 /* Size of relocation record. */
151 CONST
int md_reloc_size
= 8;
153 /* 0: assemble for ARM,
154 1: assemble for Thumb,
155 2: assemble for Thumb even though target CPU does not support thumb
157 static int thumb_mode
= 0;
159 typedef struct arm_fix
167 unsigned long instruction
;
172 bfd_reloc_code_real_type type
;
189 struct asm_shift_properties
191 enum asm_shift_index index
;
192 unsigned long bit_field
;
193 unsigned int allows_0
: 1;
194 unsigned int allows_32
: 1;
197 static const struct asm_shift_properties shift_properties
[] =
199 { SHIFT_LSL
, 0, 1, 0},
200 { SHIFT_LSR
, 0x20, 0, 1},
201 { SHIFT_ASR
, 0x40, 0, 1},
202 { SHIFT_ROR
, 0x60, 0, 0},
203 { SHIFT_RRX
, 0x60, 0, 0}
206 struct asm_shift_name
209 const struct asm_shift_properties
* properties
;
212 static const struct asm_shift_name shift_names
[] =
214 { "asl", shift_properties
+ SHIFT_LSL
},
215 { "lsl", shift_properties
+ SHIFT_LSL
},
216 { "lsr", shift_properties
+ SHIFT_LSR
},
217 { "asr", shift_properties
+ SHIFT_ASR
},
218 { "ror", shift_properties
+ SHIFT_ROR
},
219 { "rrx", shift_properties
+ SHIFT_RRX
},
220 { "ASL", shift_properties
+ SHIFT_LSL
},
221 { "LSL", shift_properties
+ SHIFT_LSL
},
222 { "LSR", shift_properties
+ SHIFT_LSR
},
223 { "ASR", shift_properties
+ SHIFT_ASR
},
224 { "ROR", shift_properties
+ SHIFT_ROR
},
225 { "RRX", shift_properties
+ SHIFT_RRX
}
228 #define NO_SHIFT_RESTRICT 1
229 #define SHIFT_RESTRICT 0
231 #define NUM_FLOAT_VALS 8
233 CONST
char * fp_const
[] =
235 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
238 /* Number of littlenums required to hold an extended precision number. */
239 #define MAX_LITTLENUMS 6
241 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
251 #define CP_T_X 0x00008000
252 #define CP_T_Y 0x00400000
253 #define CP_T_Pre 0x01000000
254 #define CP_T_UD 0x00800000
255 #define CP_T_WB 0x00200000
257 #define CONDS_BIT 0x00100000
258 #define LOAD_BIT 0x00100000
259 #define TRANS_BIT 0x00200000
261 #define DOUBLE_LOAD_FLAG 0x00000001
265 CONST
char * template;
269 /* This is to save a hash look-up in the common case. */
270 #define COND_ALWAYS 0xe0000000
272 static CONST
struct asm_cond conds
[] =
276 {"cs", 0x20000000}, {"hs", 0x20000000},
277 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
292 /* Warning: If the top bit of the set_bits is set, then the standard
293 instruction bitmask is ignored, and the new bitmask is taken from
297 CONST
char * template; /* Basic flag string. */
298 unsigned long set_bits
; /* Bits to set. */
301 static CONST
struct asm_flg s_flag
[] =
307 static CONST
struct asm_flg ldr_flags
[] =
309 {"d", DOUBLE_LOAD_FLAG
},
312 {"bt", 0x00400000 | TRANS_BIT
},
319 static CONST
struct asm_flg str_flags
[] =
321 {"d", DOUBLE_LOAD_FLAG
},
324 {"bt", 0x00400000 | TRANS_BIT
},
329 static CONST
struct asm_flg byte_flag
[] =
335 static CONST
struct asm_flg cmp_flags
[] =
342 static CONST
struct asm_flg ldm_flags
[] =
355 static CONST
struct asm_flg stm_flags
[] =
368 static CONST
struct asm_flg lfm_flags
[] =
375 static CONST
struct asm_flg sfm_flags
[] =
382 static CONST
struct asm_flg round_flags
[] =
390 /* The implementation of the FIX instruction is broken on some assemblers,
391 in that it accepts a precision specifier as well as a rounding specifier,
392 despite the fact that this is meaningless. To be more compatible, we
393 accept it as well, though of course it does not set any bits. */
394 static CONST
struct asm_flg fix_flags
[] =
411 static CONST
struct asm_flg except_flag
[] =
417 static CONST
struct asm_flg long_flag
[] =
425 CONST
char * template;
430 /* The bit that distnguishes CPSR and SPSR. */
431 #define SPSR_BIT (1 << 22)
433 /* How many bits to shift the PSR_xxx bits up by. */
436 #define PSR_c (1 << 0)
437 #define PSR_x (1 << 1)
438 #define PSR_s (1 << 2)
439 #define PSR_f (1 << 3)
441 static CONST
struct asm_psr psrs
[] =
443 {"CPSR", true, PSR_c
| PSR_f
},
444 {"CPSR_all", true, PSR_c
| PSR_f
},
445 {"SPSR", false, PSR_c
| PSR_f
},
446 {"SPSR_all", false, PSR_c
| PSR_f
},
447 {"CPSR_flg", true, PSR_f
},
448 {"CPSR_f", true, PSR_f
},
449 {"SPSR_flg", false, PSR_f
},
450 {"SPSR_f", false, PSR_f
},
451 {"CPSR_c", true, PSR_c
},
452 {"CPSR_ctl", true, PSR_c
},
453 {"SPSR_c", false, PSR_c
},
454 {"SPSR_ctl", false, PSR_c
},
455 {"CPSR_x", true, PSR_x
},
456 {"CPSR_s", true, PSR_s
},
457 {"SPSR_x", false, PSR_x
},
458 {"SPSR_s", false, PSR_s
},
459 /* Combinations of flags. */
460 {"CPSR_fs", true, PSR_f
| PSR_s
},
461 {"CPSR_fx", true, PSR_f
| PSR_x
},
462 {"CPSR_fc", true, PSR_f
| PSR_c
},
463 {"CPSR_sf", true, PSR_s
| PSR_f
},
464 {"CPSR_sx", true, PSR_s
| PSR_x
},
465 {"CPSR_sc", true, PSR_s
| PSR_c
},
466 {"CPSR_xf", true, PSR_x
| PSR_f
},
467 {"CPSR_xs", true, PSR_x
| PSR_s
},
468 {"CPSR_xc", true, PSR_x
| PSR_c
},
469 {"CPSR_cf", true, PSR_c
| PSR_f
},
470 {"CPSR_cs", true, PSR_c
| PSR_s
},
471 {"CPSR_cx", true, PSR_c
| PSR_x
},
472 {"CPSR_fsx", true, PSR_f
| PSR_s
| PSR_x
},
473 {"CPSR_fsc", true, PSR_f
| PSR_s
| PSR_c
},
474 {"CPSR_fxs", true, PSR_f
| PSR_x
| PSR_s
},
475 {"CPSR_fxc", true, PSR_f
| PSR_x
| PSR_c
},
476 {"CPSR_fcs", true, PSR_f
| PSR_c
| PSR_s
},
477 {"CPSR_fcx", true, PSR_f
| PSR_c
| PSR_x
},
478 {"CPSR_sfx", true, PSR_s
| PSR_f
| PSR_x
},
479 {"CPSR_sfc", true, PSR_s
| PSR_f
| PSR_c
},
480 {"CPSR_sxf", true, PSR_s
| PSR_x
| PSR_f
},
481 {"CPSR_sxc", true, PSR_s
| PSR_x
| PSR_c
},
482 {"CPSR_scf", true, PSR_s
| PSR_c
| PSR_f
},
483 {"CPSR_scx", true, PSR_s
| PSR_c
| PSR_x
},
484 {"CPSR_xfs", true, PSR_x
| PSR_f
| PSR_s
},
485 {"CPSR_xfc", true, PSR_x
| PSR_f
| PSR_c
},
486 {"CPSR_xsf", true, PSR_x
| PSR_s
| PSR_f
},
487 {"CPSR_xsc", true, PSR_x
| PSR_s
| PSR_c
},
488 {"CPSR_xcf", true, PSR_x
| PSR_c
| PSR_f
},
489 {"CPSR_xcs", true, PSR_x
| PSR_c
| PSR_s
},
490 {"CPSR_cfs", true, PSR_c
| PSR_f
| PSR_s
},
491 {"CPSR_cfx", true, PSR_c
| PSR_f
| PSR_x
},
492 {"CPSR_csf", true, PSR_c
| PSR_s
| PSR_f
},
493 {"CPSR_csx", true, PSR_c
| PSR_s
| PSR_x
},
494 {"CPSR_cxf", true, PSR_c
| PSR_x
| PSR_f
},
495 {"CPSR_cxs", true, PSR_c
| PSR_x
| PSR_s
},
496 {"CPSR_fsxc", true, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
497 {"CPSR_fscx", true, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
498 {"CPSR_fxsc", true, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
499 {"CPSR_fxcs", true, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
500 {"CPSR_fcsx", true, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
501 {"CPSR_fcxs", true, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
502 {"CPSR_sfxc", true, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
503 {"CPSR_sfcx", true, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
504 {"CPSR_sxfc", true, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
505 {"CPSR_sxcf", true, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
506 {"CPSR_scfx", true, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
507 {"CPSR_scxf", true, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
508 {"CPSR_xfsc", true, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
509 {"CPSR_xfcs", true, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
510 {"CPSR_xsfc", true, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
511 {"CPSR_xscf", true, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
512 {"CPSR_xcfs", true, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
513 {"CPSR_xcsf", true, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
514 {"CPSR_cfsx", true, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
515 {"CPSR_cfxs", true, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
516 {"CPSR_csfx", true, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
517 {"CPSR_csxf", true, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
518 {"CPSR_cxfs", true, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
519 {"CPSR_cxsf", true, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
520 {"SPSR_fs", false, PSR_f
| PSR_s
},
521 {"SPSR_fx", false, PSR_f
| PSR_x
},
522 {"SPSR_fc", false, PSR_f
| PSR_c
},
523 {"SPSR_sf", false, PSR_s
| PSR_f
},
524 {"SPSR_sx", false, PSR_s
| PSR_x
},
525 {"SPSR_sc", false, PSR_s
| PSR_c
},
526 {"SPSR_xf", false, PSR_x
| PSR_f
},
527 {"SPSR_xs", false, PSR_x
| PSR_s
},
528 {"SPSR_xc", false, PSR_x
| PSR_c
},
529 {"SPSR_cf", false, PSR_c
| PSR_f
},
530 {"SPSR_cs", false, PSR_c
| PSR_s
},
531 {"SPSR_cx", false, PSR_c
| PSR_x
},
532 {"SPSR_fsx", false, PSR_f
| PSR_s
| PSR_x
},
533 {"SPSR_fsc", false, PSR_f
| PSR_s
| PSR_c
},
534 {"SPSR_fxs", false, PSR_f
| PSR_x
| PSR_s
},
535 {"SPSR_fxc", false, PSR_f
| PSR_x
| PSR_c
},
536 {"SPSR_fcs", false, PSR_f
| PSR_c
| PSR_s
},
537 {"SPSR_fcx", false, PSR_f
| PSR_c
| PSR_x
},
538 {"SPSR_sfx", false, PSR_s
| PSR_f
| PSR_x
},
539 {"SPSR_sfc", false, PSR_s
| PSR_f
| PSR_c
},
540 {"SPSR_sxf", false, PSR_s
| PSR_x
| PSR_f
},
541 {"SPSR_sxc", false, PSR_s
| PSR_x
| PSR_c
},
542 {"SPSR_scf", false, PSR_s
| PSR_c
| PSR_f
},
543 {"SPSR_scx", false, PSR_s
| PSR_c
| PSR_x
},
544 {"SPSR_xfs", false, PSR_x
| PSR_f
| PSR_s
},
545 {"SPSR_xfc", false, PSR_x
| PSR_f
| PSR_c
},
546 {"SPSR_xsf", false, PSR_x
| PSR_s
| PSR_f
},
547 {"SPSR_xsc", false, PSR_x
| PSR_s
| PSR_c
},
548 {"SPSR_xcf", false, PSR_x
| PSR_c
| PSR_f
},
549 {"SPSR_xcs", false, PSR_x
| PSR_c
| PSR_s
},
550 {"SPSR_cfs", false, PSR_c
| PSR_f
| PSR_s
},
551 {"SPSR_cfx", false, PSR_c
| PSR_f
| PSR_x
},
552 {"SPSR_csf", false, PSR_c
| PSR_s
| PSR_f
},
553 {"SPSR_csx", false, PSR_c
| PSR_s
| PSR_x
},
554 {"SPSR_cxf", false, PSR_c
| PSR_x
| PSR_f
},
555 {"SPSR_cxs", false, PSR_c
| PSR_x
| PSR_s
},
556 {"SPSR_fsxc", false, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
557 {"SPSR_fscx", false, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
558 {"SPSR_fxsc", false, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
559 {"SPSR_fxcs", false, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
560 {"SPSR_fcsx", false, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
561 {"SPSR_fcxs", false, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
562 {"SPSR_sfxc", false, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
563 {"SPSR_sfcx", false, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
564 {"SPSR_sxfc", false, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
565 {"SPSR_sxcf", false, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
566 {"SPSR_scfx", false, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
567 {"SPSR_scxf", false, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
568 {"SPSR_xfsc", false, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
569 {"SPSR_xfcs", false, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
570 {"SPSR_xsfc", false, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
571 {"SPSR_xscf", false, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
572 {"SPSR_xcfs", false, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
573 {"SPSR_xcsf", false, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
574 {"SPSR_cfsx", false, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
575 {"SPSR_cfxs", false, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
576 {"SPSR_csfx", false, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
577 {"SPSR_csxf", false, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
578 {"SPSR_cxfs", false, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
579 {"SPSR_cxsf", false, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
582 /* Functions called by parser. */
583 /* ARM instructions. */
584 static void do_arit
PARAMS ((char *, unsigned long));
585 static void do_cmp
PARAMS ((char *, unsigned long));
586 static void do_mov
PARAMS ((char *, unsigned long));
587 static void do_ldst
PARAMS ((char *, unsigned long));
588 static void do_ldmstm
PARAMS ((char *, unsigned long));
589 static void do_branch
PARAMS ((char *, unsigned long));
590 static void do_swi
PARAMS ((char *, unsigned long));
591 /* Pseudo Op codes. */
592 static void do_adr
PARAMS ((char *, unsigned long));
593 static void do_adrl
PARAMS ((char *, unsigned long));
594 static void do_nop
PARAMS ((char *, unsigned long));
596 static void do_mul
PARAMS ((char *, unsigned long));
597 static void do_mla
PARAMS ((char *, unsigned long));
599 static void do_swap
PARAMS ((char *, unsigned long));
601 static void do_msr
PARAMS ((char *, unsigned long));
602 static void do_mrs
PARAMS ((char *, unsigned long));
604 static void do_mull
PARAMS ((char *, unsigned long));
606 static void do_bx
PARAMS ((char *, unsigned long));
608 /* ARM_EXT_XScale. */
609 static void do_mia
PARAMS ((char *, unsigned long));
610 static void do_mar
PARAMS ((char *, unsigned long));
611 static void do_mra
PARAMS ((char *, unsigned long));
612 static void do_pld
PARAMS ((char *, unsigned long));
613 static void do_ldrd
PARAMS ((char *, unsigned long));
616 static void do_blx
PARAMS ((char *, unsigned long));
617 static void do_bkpt
PARAMS ((char *, unsigned long));
618 static void do_clz
PARAMS ((char *, unsigned long));
619 static void do_lstc2
PARAMS ((char *, unsigned long));
620 static void do_cdp2
PARAMS ((char *, unsigned long));
621 static void do_co_reg2
PARAMS ((char *, unsigned long));
623 static void do_t_blx
PARAMS ((char *));
624 static void do_t_bkpt
PARAMS ((char *));
627 static void do_smla
PARAMS ((char *, unsigned long));
628 static void do_smlal
PARAMS ((char *, unsigned long));
629 static void do_smul
PARAMS ((char *, unsigned long));
630 static void do_qadd
PARAMS ((char *, unsigned long));
631 static void do_co_reg2c
PARAMS ((char *, unsigned long));
633 /* Coprocessor Instructions. */
634 static void do_cdp
PARAMS ((char *, unsigned long));
635 static void do_lstc
PARAMS ((char *, unsigned long));
636 static void do_co_reg
PARAMS ((char *, unsigned long));
637 static void do_fp_ctrl
PARAMS ((char *, unsigned long));
638 static void do_fp_ldst
PARAMS ((char *, unsigned long));
639 static void do_fp_ldmstm
PARAMS ((char *, unsigned long));
640 static void do_fp_dyadic
PARAMS ((char *, unsigned long));
641 static void do_fp_monadic
PARAMS ((char *, unsigned long));
642 static void do_fp_cmp
PARAMS ((char *, unsigned long));
643 static void do_fp_from_reg
PARAMS ((char *, unsigned long));
644 static void do_fp_to_reg
PARAMS ((char *, unsigned long));
646 static void fix_new_arm
PARAMS ((fragS
*, int, short, expressionS
*, int, int));
647 static int arm_reg_parse
PARAMS ((char **));
648 static CONST
struct asm_psr
* arm_psr_parse
PARAMS ((char **));
649 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
, valueT
, fragS
*));
650 static int add_to_lit_pool
PARAMS ((void));
651 static unsigned validate_immediate
PARAMS ((unsigned));
652 static unsigned validate_immediate_twopart
PARAMS ((unsigned int, unsigned int *));
653 static int validate_offset_imm
PARAMS ((unsigned int, int));
654 static void opcode_select
PARAMS ((int));
655 static void end_of_line
PARAMS ((char *));
656 static int reg_required_here
PARAMS ((char **, int));
657 static int psr_required_here
PARAMS ((char **));
658 static int co_proc_number
PARAMS ((char **));
659 static int cp_opc_expr
PARAMS ((char **, int, int));
660 static int cp_reg_required_here
PARAMS ((char **, int));
661 static int fp_reg_required_here
PARAMS ((char **, int));
662 static int cp_address_offset
PARAMS ((char **));
663 static int cp_address_required_here
PARAMS ((char **));
664 static int my_get_float_expression
PARAMS ((char **));
665 static int skip_past_comma
PARAMS ((char **));
666 static int walk_no_bignums
PARAMS ((symbolS
*));
667 static int negate_data_op
PARAMS ((unsigned long *, unsigned long));
668 static int data_op2
PARAMS ((char **));
669 static int fp_op2
PARAMS ((char **));
670 static long reg_list
PARAMS ((char **));
671 static void thumb_load_store
PARAMS ((char *, int, int));
672 static int decode_shift
PARAMS ((char **, int));
673 static int ldst_extend
PARAMS ((char **, int));
674 static void thumb_add_sub
PARAMS ((char *, int));
675 static void insert_reg
PARAMS ((int));
676 static void thumb_shift
PARAMS ((char *, int));
677 static void thumb_mov_compare
PARAMS ((char *, int));
678 static void set_constant_flonums
PARAMS ((void));
679 static valueT md_chars_to_number
PARAMS ((char *, int));
680 static void insert_reg_alias
PARAMS ((char *, int));
681 static void output_inst
PARAMS ((void));
683 static bfd_reloc_code_real_type arm_parse_reloc
PARAMS ((void));
686 /* ARM instructions take 4bytes in the object file, Thumb instructions
690 /* LONGEST_INST is the longest basic instruction name without
691 conditions or flags. ARM7M has 4 of length 5. El Segundo
692 has one basic instruction name of length 7 (SMLALxy). */
693 #define LONGEST_INST 7
697 /* Basic string to match. */
698 CONST
char * template;
700 /* Basic instruction code. */
703 /* Compulsory suffix that must follow conds. If "", then the
704 instruction is not conditional and must have no suffix. */
705 CONST
char * comp_suffix
;
707 /* Bits to toggle if flag 'n' set. */
708 CONST
struct asm_flg
* flags
;
710 /* Which CPU variants this exists for. */
711 unsigned long variants
;
713 /* Function to call to parse args. */
714 void (* parms
) PARAMS ((char *, unsigned long));
717 static CONST
struct asm_opcode insns
[] =
719 /* Intel XScale extensions to ARM V5 ISA. */
720 {"mia", 0x0e200010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
721 {"miaph", 0x0e280010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
722 {"miabb", 0x0e2c0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
723 {"miabt", 0x0e2d0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
724 {"miatb", 0x0e2e0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
725 {"miatt", 0x0e2f0010, NULL
, NULL
, ARM_EXT_XSCALE
, do_mia
},
726 {"mar", 0x0c400000, NULL
, NULL
, ARM_EXT_XSCALE
, do_mar
},
727 {"mra", 0x0c500000, NULL
, NULL
, ARM_EXT_XSCALE
, do_mra
},
728 {"pld", 0xf450f000, "", NULL
, ARM_EXT_XSCALE
, do_pld
},
729 {"ldr", 0x000000d0, NULL
, ldr_flags
, ARM_ANY
, do_ldrd
},
730 {"str", 0x000000f0, NULL
, str_flags
, ARM_ANY
, do_ldrd
},
732 /* ARM Instructions. */
733 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
734 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
735 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
736 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
737 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
738 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
739 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
740 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
741 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
742 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
743 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
744 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
745 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
746 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
747 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
748 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
749 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
750 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
751 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
752 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
753 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
755 {"bl", 0x0b000000, NULL
, NULL
, ARM_ANY
, do_branch
},
756 {"b", 0x0a000000, NULL
, NULL
, ARM_ANY
, do_branch
},
758 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
759 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
763 {"adr", 0x028f0000, NULL
, long_flag
, ARM_ANY
, do_adr
},
764 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
766 /* ARM 2 multiplies. */
767 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
768 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
770 /* ARM 3 - swp instructions. */
771 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
773 /* ARM 6 Coprocessor instructions. */
774 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
775 {"msr", 0x0120f000, NULL
, NULL
, ARM_6UP
, do_msr
},
776 /* ScottB: our code uses 0x0128f000 for msr.
777 NickC: but this is wrong because the bits 16 through 19 are
778 handled by the PSR_xxx defines above. */
780 /* ARM 7M long multiplies - need signed/unsigned flags! */
781 {"smull", 0x00c00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
782 {"umull", 0x00800090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
783 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
784 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_EXT_LONGMUL
, do_mull
},
786 /* ARM THUMB interworking. */
787 {"bx", 0x012fff10, NULL
, NULL
, ARM_EXT_THUMB
, do_bx
},
789 /* Floating point instructions. */
790 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
791 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
792 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
793 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
794 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
795 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
796 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
797 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
798 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
799 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
800 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
801 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
802 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
803 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
804 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
805 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
806 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
807 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
808 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
809 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
810 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
811 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
812 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
813 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
814 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
815 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
816 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
817 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
818 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
819 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
820 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
821 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
822 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
823 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
824 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
825 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
826 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
827 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
828 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
829 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
830 be an optional suffix, but part of the instruction. To be compatible,
832 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
833 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
834 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
835 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
837 /* Generic copressor instructions. */
838 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
839 {"ldc", 0x0c100000, NULL
, long_flag
, ARM_2UP
, do_lstc
},
840 {"stc", 0x0c000000, NULL
, long_flag
, ARM_2UP
, do_lstc
},
841 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
842 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
844 /* ARM ISA extension 5. */
845 /* Note: blx is actually 2 opcodes, so the .value is set dynamically.
846 And it's sometimes conditional and sometimes not. */
847 {"blx", 0, NULL
, NULL
, ARM_EXT_V5
, do_blx
},
848 {"clz", 0x016f0f10, NULL
, NULL
, ARM_EXT_V5
, do_clz
},
849 {"bkpt", 0xe1200070, "", NULL
, ARM_EXT_V5
, do_bkpt
},
850 {"ldc2", 0xfc100000, "", long_flag
, ARM_EXT_V5
, do_lstc2
},
851 {"stc2", 0xfc000000, "", long_flag
, ARM_EXT_V5
, do_lstc2
},
852 {"cdp2", 0xfe000000, "", NULL
, ARM_EXT_V5
, do_cdp2
},
853 {"mcr2", 0xfe000010, "", NULL
, ARM_EXT_V5
, do_co_reg2
},
854 {"mrc2", 0xfe100010, "", NULL
, ARM_EXT_V5
, do_co_reg2
},
856 /* ARM ISA extension 5E, El Segundo. */
857 {"smlabb", 0x01000080, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
858 {"smlatb", 0x010000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
859 {"smlabt", 0x010000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
860 {"smlatt", 0x010000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
862 {"smlawb", 0x01200080, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
863 {"smlawt", 0x012000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smla
},
865 {"smlalbb",0x01400080, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
866 {"smlaltb",0x014000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
867 {"smlalbt",0x014000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
868 {"smlaltt",0x014000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smlal
},
870 {"smulbb", 0x01600080, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
871 {"smultb", 0x016000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
872 {"smulbt", 0x016000c0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
873 {"smultt", 0x016000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
875 {"smulwb", 0x012000a0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
876 {"smulwt", 0x012000e0, NULL
, NULL
, ARM_EXT_V5E
, do_smul
},
878 {"qadd", 0x01000050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
879 {"qdadd", 0x01400050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
880 {"qsub", 0x01200050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
881 {"qdsub", 0x01600050, NULL
, NULL
, ARM_EXT_V5E
, do_qadd
},
883 {"mcrr", 0x0c400000, NULL
, NULL
, ARM_EXT_V5E
, do_co_reg2c
},
884 {"mrrc", 0x0c500000, NULL
, NULL
, ARM_EXT_V5E
, do_co_reg2c
},
887 /* Defines for various bits that we will want to toggle. */
888 #define INST_IMMEDIATE 0x02000000
889 #define OFFSET_REG 0x02000000
890 #define HWOFFSET_IMM 0x00400000
891 #define SHIFT_BY_REG 0x00000010
892 #define PRE_INDEX 0x01000000
893 #define INDEX_UP 0x00800000
894 #define WRITE_BACK 0x00200000
895 #define LDM_TYPE_2_OR_3 0x00400000
897 #define LITERAL_MASK 0xf000f000
898 #define COND_MASK 0xf0000000
899 #define OPCODE_MASK 0xfe1fffff
900 #define DATA_OP_SHIFT 21
902 /* Codes to distinguish the arithmetic instructions. */
913 #define OPCODE_CMP 10
914 #define OPCODE_CMN 11
915 #define OPCODE_ORR 12
916 #define OPCODE_MOV 13
917 #define OPCODE_BIC 14
918 #define OPCODE_MVN 15
920 static void do_t_nop
PARAMS ((char *));
921 static void do_t_arit
PARAMS ((char *));
922 static void do_t_add
PARAMS ((char *));
923 static void do_t_asr
PARAMS ((char *));
924 static void do_t_branch9
PARAMS ((char *));
925 static void do_t_branch12
PARAMS ((char *));
926 static void do_t_branch23
PARAMS ((char *));
927 static void do_t_bx
PARAMS ((char *));
928 static void do_t_compare
PARAMS ((char *));
929 static void do_t_ldmstm
PARAMS ((char *));
930 static void do_t_ldr
PARAMS ((char *));
931 static void do_t_ldrb
PARAMS ((char *));
932 static void do_t_ldrh
PARAMS ((char *));
933 static void do_t_lds
PARAMS ((char *));
934 static void do_t_lsl
PARAMS ((char *));
935 static void do_t_lsr
PARAMS ((char *));
936 static void do_t_mov
PARAMS ((char *));
937 static void do_t_push_pop
PARAMS ((char *));
938 static void do_t_str
PARAMS ((char *));
939 static void do_t_strb
PARAMS ((char *));
940 static void do_t_strh
PARAMS ((char *));
941 static void do_t_sub
PARAMS ((char *));
942 static void do_t_swi
PARAMS ((char *));
943 static void do_t_adr
PARAMS ((char *));
945 #define T_OPCODE_MUL 0x4340
946 #define T_OPCODE_TST 0x4200
947 #define T_OPCODE_CMN 0x42c0
948 #define T_OPCODE_NEG 0x4240
949 #define T_OPCODE_MVN 0x43c0
951 #define T_OPCODE_ADD_R3 0x1800
952 #define T_OPCODE_SUB_R3 0x1a00
953 #define T_OPCODE_ADD_HI 0x4400
954 #define T_OPCODE_ADD_ST 0xb000
955 #define T_OPCODE_SUB_ST 0xb080
956 #define T_OPCODE_ADD_SP 0xa800
957 #define T_OPCODE_ADD_PC 0xa000
958 #define T_OPCODE_ADD_I8 0x3000
959 #define T_OPCODE_SUB_I8 0x3800
960 #define T_OPCODE_ADD_I3 0x1c00
961 #define T_OPCODE_SUB_I3 0x1e00
963 #define T_OPCODE_ASR_R 0x4100
964 #define T_OPCODE_LSL_R 0x4080
965 #define T_OPCODE_LSR_R 0x40c0
966 #define T_OPCODE_ASR_I 0x1000
967 #define T_OPCODE_LSL_I 0x0000
968 #define T_OPCODE_LSR_I 0x0800
970 #define T_OPCODE_MOV_I8 0x2000
971 #define T_OPCODE_CMP_I8 0x2800
972 #define T_OPCODE_CMP_LR 0x4280
973 #define T_OPCODE_MOV_HR 0x4600
974 #define T_OPCODE_CMP_HR 0x4500
976 #define T_OPCODE_LDR_PC 0x4800
977 #define T_OPCODE_LDR_SP 0x9800
978 #define T_OPCODE_STR_SP 0x9000
979 #define T_OPCODE_LDR_IW 0x6800
980 #define T_OPCODE_STR_IW 0x6000
981 #define T_OPCODE_LDR_IH 0x8800
982 #define T_OPCODE_STR_IH 0x8000
983 #define T_OPCODE_LDR_IB 0x7800
984 #define T_OPCODE_STR_IB 0x7000
985 #define T_OPCODE_LDR_RW 0x5800
986 #define T_OPCODE_STR_RW 0x5000
987 #define T_OPCODE_LDR_RH 0x5a00
988 #define T_OPCODE_STR_RH 0x5200
989 #define T_OPCODE_LDR_RB 0x5c00
990 #define T_OPCODE_STR_RB 0x5400
992 #define T_OPCODE_PUSH 0xb400
993 #define T_OPCODE_POP 0xbc00
995 #define T_OPCODE_BRANCH 0xe7fe
997 static int thumb_reg
PARAMS ((char ** str
, int hi_lo
));
999 #define THUMB_SIZE 2 /* Size of thumb instruction. */
1000 #define THUMB_REG_LO 0x1
1001 #define THUMB_REG_HI 0x2
1002 #define THUMB_REG_ANY 0x3
1004 #define THUMB_H1 0x0080
1005 #define THUMB_H2 0x0040
1011 #define THUMB_MOVE 0
1012 #define THUMB_COMPARE 1
1014 #define THUMB_LOAD 0
1015 #define THUMB_STORE 1
1017 #define THUMB_PP_PC_LR 0x0100
1019 /* These three are used for immediate shifts, do not alter. */
1020 #define THUMB_WORD 2
1021 #define THUMB_HALFWORD 1
1022 #define THUMB_BYTE 0
1026 /* Basic string to match. */
1027 CONST
char * template;
1029 /* Basic instruction code. */
1030 unsigned long value
;
1034 /* Which CPU variants this exists for. */
1035 unsigned long variants
;
1037 /* Function to call to parse args. */
1038 void (* parms
) PARAMS ((char *));
1041 static CONST
struct thumb_opcode tinsns
[] =
1043 {"adc", 0x4140, 2, ARM_EXT_THUMB
, do_t_arit
},
1044 {"add", 0x0000, 2, ARM_EXT_THUMB
, do_t_add
},
1045 {"and", 0x4000, 2, ARM_EXT_THUMB
, do_t_arit
},
1046 {"asr", 0x0000, 2, ARM_EXT_THUMB
, do_t_asr
},
1047 {"b", T_OPCODE_BRANCH
, 2, ARM_EXT_THUMB
, do_t_branch12
},
1048 {"beq", 0xd0fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1049 {"bne", 0xd1fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1050 {"bcs", 0xd2fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1051 {"bhs", 0xd2fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1052 {"bcc", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1053 {"bul", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1054 {"blo", 0xd3fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1055 {"bmi", 0xd4fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1056 {"bpl", 0xd5fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1057 {"bvs", 0xd6fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1058 {"bvc", 0xd7fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1059 {"bhi", 0xd8fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1060 {"bls", 0xd9fe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1061 {"bge", 0xdafe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1062 {"blt", 0xdbfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1063 {"bgt", 0xdcfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1064 {"ble", 0xddfe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1065 {"bal", 0xdefe, 2, ARM_EXT_THUMB
, do_t_branch9
},
1066 {"bic", 0x4380, 2, ARM_EXT_THUMB
, do_t_arit
},
1067 {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB
, do_t_branch23
},
1068 {"blx", 0, 0, ARM_EXT_V5
, do_t_blx
},
1069 {"bkpt", 0xbe00, 2, ARM_EXT_V5
, do_t_bkpt
},
1070 {"bx", 0x4700, 2, ARM_EXT_THUMB
, do_t_bx
},
1071 {"cmn", T_OPCODE_CMN
, 2, ARM_EXT_THUMB
, do_t_arit
},
1072 {"cmp", 0x0000, 2, ARM_EXT_THUMB
, do_t_compare
},
1073 {"eor", 0x4040, 2, ARM_EXT_THUMB
, do_t_arit
},
1074 {"ldmia", 0xc800, 2, ARM_EXT_THUMB
, do_t_ldmstm
},
1075 {"ldr", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldr
},
1076 {"ldrb", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldrb
},
1077 {"ldrh", 0x0000, 2, ARM_EXT_THUMB
, do_t_ldrh
},
1078 {"ldrsb", 0x5600, 2, ARM_EXT_THUMB
, do_t_lds
},
1079 {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB
, do_t_lds
},
1080 {"ldsb", 0x5600, 2, ARM_EXT_THUMB
, do_t_lds
},
1081 {"ldsh", 0x5e00, 2, ARM_EXT_THUMB
, do_t_lds
},
1082 {"lsl", 0x0000, 2, ARM_EXT_THUMB
, do_t_lsl
},
1083 {"lsr", 0x0000, 2, ARM_EXT_THUMB
, do_t_lsr
},
1084 {"mov", 0x0000, 2, ARM_EXT_THUMB
, do_t_mov
},
1085 {"mul", T_OPCODE_MUL
, 2, ARM_EXT_THUMB
, do_t_arit
},
1086 {"mvn", T_OPCODE_MVN
, 2, ARM_EXT_THUMB
, do_t_arit
},
1087 {"neg", T_OPCODE_NEG
, 2, ARM_EXT_THUMB
, do_t_arit
},
1088 {"orr", 0x4300, 2, ARM_EXT_THUMB
, do_t_arit
},
1089 {"pop", 0xbc00, 2, ARM_EXT_THUMB
, do_t_push_pop
},
1090 {"push", 0xb400, 2, ARM_EXT_THUMB
, do_t_push_pop
},
1091 {"ror", 0x41c0, 2, ARM_EXT_THUMB
, do_t_arit
},
1092 {"sbc", 0x4180, 2, ARM_EXT_THUMB
, do_t_arit
},
1093 {"stmia", 0xc000, 2, ARM_EXT_THUMB
, do_t_ldmstm
},
1094 {"str", 0x0000, 2, ARM_EXT_THUMB
, do_t_str
},
1095 {"strb", 0x0000, 2, ARM_EXT_THUMB
, do_t_strb
},
1096 {"strh", 0x0000, 2, ARM_EXT_THUMB
, do_t_strh
},
1097 {"swi", 0xdf00, 2, ARM_EXT_THUMB
, do_t_swi
},
1098 {"sub", 0x0000, 2, ARM_EXT_THUMB
, do_t_sub
},
1099 {"tst", T_OPCODE_TST
, 2, ARM_EXT_THUMB
, do_t_arit
},
1101 {"adr", 0x0000, 2, ARM_EXT_THUMB
, do_t_adr
},
1102 {"nop", 0x46C0, 2, ARM_EXT_THUMB
, do_t_nop
}, /* mov r8,r8 */
1111 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1112 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1113 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1119 /* These are the standard names. Users can add aliases with .req. */
1120 static CONST
struct reg_entry reg_table
[] =
1122 /* Processor Register Numbers. */
1123 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1124 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1125 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1126 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
1127 /* APCS conventions. */
1128 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1129 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1130 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1131 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
1132 /* ATPCS additions to APCS conventions. */
1133 {"wr", 7}, {"v8", 11},
1135 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1136 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1137 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1138 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1139 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1140 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1141 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1142 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1143 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1144 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1145 /* ATPCS additions to float register names. */
1146 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1147 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1148 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1149 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1150 /* FIXME: At some point we need to add VFP register names. */
1151 /* Array terminator. */
1155 #define BAD_ARGS _("Bad arguments to instruction")
1156 #define BAD_PC _("r15 not allowed here")
1157 #define BAD_FLAGS _("Instruction should not have flags")
1158 #define BAD_COND _("Instruction is not conditional")
1159 #define ERR_NO_ACCUM _("acc0 expected")
1161 static struct hash_control
* arm_ops_hsh
= NULL
;
1162 static struct hash_control
* arm_tops_hsh
= NULL
;
1163 static struct hash_control
* arm_cond_hsh
= NULL
;
1164 static struct hash_control
* arm_shift_hsh
= NULL
;
1165 static struct hash_control
* arm_reg_hsh
= NULL
;
1166 static struct hash_control
* arm_psr_hsh
= NULL
;
1168 /* This table describes all the machine specific pseudo-ops the assembler
1169 has to support. The fields are:
1170 pseudo-op name without dot
1171 function to call to execute this pseudo-op
1172 Integer arg to pass to the function. */
1174 static void s_req
PARAMS ((int));
1175 static void s_align
PARAMS ((int));
1176 static void s_bss
PARAMS ((int));
1177 static void s_even
PARAMS ((int));
1178 static void s_ltorg
PARAMS ((int));
1179 static void s_arm
PARAMS ((int));
1180 static void s_thumb
PARAMS ((int));
1181 static void s_code
PARAMS ((int));
1182 static void s_force_thumb
PARAMS ((int));
1183 static void s_thumb_func
PARAMS ((int));
1184 static void s_thumb_set
PARAMS ((int));
1185 static void arm_s_text
PARAMS ((int));
1186 static void arm_s_data
PARAMS ((int));
1188 static void arm_s_section
PARAMS ((int));
1189 static void s_arm_elf_cons
PARAMS ((int));
1192 static int my_get_expression
PARAMS ((expressionS
*, char **));
1194 CONST pseudo_typeS md_pseudo_table
[] =
1196 /* Never called becasue '.req' does not start line. */
1197 { "req", s_req
, 0 },
1198 { "bss", s_bss
, 0 },
1199 { "align", s_align
, 0 },
1200 { "arm", s_arm
, 0 },
1201 { "thumb", s_thumb
, 0 },
1202 { "code", s_code
, 0 },
1203 { "force_thumb", s_force_thumb
, 0 },
1204 { "thumb_func", s_thumb_func
, 0 },
1205 { "thumb_set", s_thumb_set
, 0 },
1206 { "even", s_even
, 0 },
1207 { "ltorg", s_ltorg
, 0 },
1208 { "pool", s_ltorg
, 0 },
1209 /* Allow for the effect of section changes. */
1210 { "text", arm_s_text
, 0 },
1211 { "data", arm_s_data
, 0 },
1213 { "section", arm_s_section
, 0 },
1214 { "section.s", arm_s_section
, 0 },
1215 { "sect", arm_s_section
, 0 },
1216 { "sect.s", arm_s_section
, 0 },
1217 { "word", s_arm_elf_cons
, 4 },
1218 { "long", s_arm_elf_cons
, 4 },
1219 { "file", dwarf2_directive_file
, 0 },
1220 { "loc", dwarf2_directive_loc
, 0 },
1224 { "extend", float_cons
, 'x' },
1225 { "ldouble", float_cons
, 'x' },
1226 { "packed", float_cons
, 'p' },
1230 /* Stuff needed to resolve the label ambiguity
1240 symbolS
* last_label_seen
;
1241 static int label_is_thumb_function_name
= false;
1243 /* Literal stuff. */
1245 #define MAX_LITERAL_POOL_SIZE 1024
1247 typedef struct literalS
1249 struct expressionS exp
;
1250 struct arm_it
* inst
;
1253 literalT literals
[MAX_LITERAL_POOL_SIZE
];
1255 /* Next free entry in the pool. */
1256 int next_literal_pool_place
= 0;
1258 /* Next literal pool number. */
1259 int lit_pool_num
= 1;
1261 symbolS
* current_poolP
= NULL
;
1268 if (current_poolP
== NULL
)
1269 current_poolP
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1270 (valueT
) 0, &zero_address_frag
);
1272 /* Check if this literal value is already in the pool: */
1273 while (lit_count
< next_literal_pool_place
)
1275 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1276 && inst
.reloc
.exp
.X_op
== O_constant
1277 && (literals
[lit_count
].exp
.X_add_number
1278 == inst
.reloc
.exp
.X_add_number
)
1279 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
1282 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1283 && inst
.reloc
.exp
.X_op
== O_symbol
1284 && (literals
[lit_count
].exp
.X_add_number
1285 == inst
.reloc
.exp
.X_add_number
)
1286 && (literals
[lit_count
].exp
.X_add_symbol
1287 == inst
.reloc
.exp
.X_add_symbol
)
1288 && (literals
[lit_count
].exp
.X_op_symbol
1289 == inst
.reloc
.exp
.X_op_symbol
))
1295 if (lit_count
== next_literal_pool_place
) /* New entry. */
1297 if (next_literal_pool_place
>= MAX_LITERAL_POOL_SIZE
)
1299 inst
.error
= _("Literal Pool Overflow");
1303 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
1304 lit_count
= next_literal_pool_place
++;
1307 inst
.reloc
.exp
.X_op
= O_symbol
;
1308 inst
.reloc
.exp
.X_add_number
= (lit_count
) * 4 - 8;
1309 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
1314 /* Can't use symbol_new here, so have to create a symbol and then at
1315 a later date assign it a value. Thats what these functions do. */
1318 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
1320 CONST
char * name
; /* It is copied, the caller can modify. */
1321 segT segment
; /* Segment identifier (SEG_<something>). */
1322 valueT valu
; /* Symbol value. */
1323 fragS
* frag
; /* Associated fragment. */
1325 unsigned int name_length
;
1326 char * preserved_copy_of_name
;
1328 name_length
= strlen (name
) + 1; /* +1 for \0. */
1329 obstack_grow (¬es
, name
, name_length
);
1330 preserved_copy_of_name
= obstack_finish (¬es
);
1331 #ifdef STRIP_UNDERSCORE
1332 if (preserved_copy_of_name
[0] == '_')
1333 preserved_copy_of_name
++;
1336 #ifdef tc_canonicalize_symbol_name
1337 preserved_copy_of_name
=
1338 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1341 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1343 S_SET_SEGMENT (symbolP
, segment
);
1344 S_SET_VALUE (symbolP
, valu
);
1345 symbol_clear_list_pointers(symbolP
);
1347 symbol_set_frag (symbolP
, frag
);
1349 /* Link to end of symbol chain. */
1351 extern int symbol_table_frozen
;
1352 if (symbol_table_frozen
)
1356 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1358 obj_symbol_new_hook (symbolP
);
1360 #ifdef tc_symbol_new_hook
1361 tc_symbol_new_hook (symbolP
);
1365 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1366 #endif /* DEBUG_SYMS */
1369 /* Check that an immediate is valid.
1370 If so, convert it to the right format. */
1373 validate_immediate (val
)
1379 #define rotate_left(v, n) (v << n | v >> (32 - n))
1381 for (i
= 0; i
< 32; i
+= 2)
1382 if ((a
= rotate_left (val
, i
)) <= 0xff)
1383 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
1388 /* Check to see if an immediate can be computed as two seperate immediate
1389 values, added together. We already know that this value cannot be
1390 computed by just one ARM instruction. */
1393 validate_immediate_twopart (val
, highpart
)
1395 unsigned int * highpart
;
1400 for (i
= 0; i
< 32; i
+= 2)
1401 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
1407 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
1409 else if (a
& 0xff0000)
1413 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
1417 assert (a
& 0xff000000);
1418 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
1421 return (a
& 0xff) | (i
<< 7);
1428 validate_offset_imm (val
, hwse
)
1432 if ((hwse
&& val
> 255) || val
> 4095)
1439 int a ATTRIBUTE_UNUSED
;
1441 as_bad (_("Invalid syntax for .req directive."));
1446 int ignore ATTRIBUTE_UNUSED
;
1448 /* We don't support putting frags in the BSS segment, we fake it by
1449 marking in_bss, then looking at s_skip for clues. */
1450 subseg_set (bss_section
, 0);
1451 demand_empty_rest_of_line ();
1456 int ignore ATTRIBUTE_UNUSED
;
1458 /* Never make frag if expect extra pass. */
1460 frag_align (1, 0, 0);
1462 record_alignment (now_seg
, 1);
1464 demand_empty_rest_of_line ();
1469 int ignored ATTRIBUTE_UNUSED
;
1474 if (current_poolP
== NULL
)
1477 /* Align pool as you have word accesses.
1478 Only make a frag if we have to. */
1480 frag_align (2, 0, 0);
1482 record_alignment (now_seg
, 2);
1484 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1486 symbol_locate (current_poolP
, sym_name
, now_seg
,
1487 (valueT
) frag_now_fix (), frag_now
);
1488 symbol_table_insert (current_poolP
);
1490 ARM_SET_THUMB (current_poolP
, thumb_mode
);
1492 #if defined OBJ_COFF || defined OBJ_ELF
1493 ARM_SET_INTERWORK (current_poolP
, support_interwork
);
1496 while (lit_count
< next_literal_pool_place
)
1497 /* First output the expression in the instruction to the pool. */
1498 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1500 next_literal_pool_place
= 0;
1501 current_poolP
= NULL
;
1504 /* Same as s_align_ptwo but align 0 => align 2. */
1508 int unused ATTRIBUTE_UNUSED
;
1511 register long temp_fill
;
1512 long max_alignment
= 15;
1514 temp
= get_absolute_expression ();
1515 if (temp
> max_alignment
)
1516 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
1519 as_bad (_("Alignment negative. 0 assumed."));
1523 if (*input_line_pointer
== ',')
1525 input_line_pointer
++;
1526 temp_fill
= get_absolute_expression ();
1534 /* Only make a frag if we HAVE to. */
1535 if (temp
&& !need_pass_2
)
1536 frag_align (temp
, (int) temp_fill
, 0);
1537 demand_empty_rest_of_line ();
1539 record_alignment (now_seg
, temp
);
1543 s_force_thumb (ignore
)
1544 int ignore ATTRIBUTE_UNUSED
;
1546 /* If we are not already in thumb mode go into it, EVEN if
1547 the target processor does not support thumb instructions.
1548 This is used by gcc/config/arm/lib1funcs.asm for example
1549 to compile interworking support functions even if the
1550 target processor should not support interworking. */
1555 record_alignment (now_seg
, 1);
1558 demand_empty_rest_of_line ();
1562 s_thumb_func (ignore
)
1563 int ignore ATTRIBUTE_UNUSED
;
1568 /* The following label is the name/address of the start of a Thumb function.
1569 We need to know this for the interworking support. */
1570 label_is_thumb_function_name
= true;
1572 demand_empty_rest_of_line ();
1575 /* Perform a .set directive, but also mark the alias as
1576 being a thumb function. */
1582 /* XXX the following is a duplicate of the code for s_set() in read.c
1583 We cannot just call that code as we need to get at the symbol that
1585 register char * name
;
1586 register char delim
;
1587 register char * end_name
;
1588 register symbolS
* symbolP
;
1590 /* Especial apologies for the random logic:
1591 This just grew, and could be parsed much more simply!
1593 name
= input_line_pointer
;
1594 delim
= get_symbol_end ();
1595 end_name
= input_line_pointer
;
1600 if (*input_line_pointer
!= ',')
1603 as_bad (_("Expected comma after name \"%s\""), name
);
1605 ignore_rest_of_line ();
1609 input_line_pointer
++;
1612 if (name
[0] == '.' && name
[1] == '\0')
1614 /* XXX - this should not happen to .thumb_set. */
1618 if ((symbolP
= symbol_find (name
)) == NULL
1619 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1622 /* When doing symbol listings, play games with dummy fragments living
1623 outside the normal fragment chain to record the file and line info
1625 if (listing
& LISTING_SYMBOLS
)
1627 extern struct list_info_struct
* listing_tail
;
1628 fragS
* dummy_frag
= (fragS
*) xmalloc (sizeof (fragS
));
1630 memset (dummy_frag
, 0, sizeof (fragS
));
1631 dummy_frag
->fr_type
= rs_fill
;
1632 dummy_frag
->line
= listing_tail
;
1633 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1634 dummy_frag
->fr_symbol
= symbolP
;
1638 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1641 /* "set" symbols are local unless otherwise specified. */
1642 SF_SET_LOCAL (symbolP
);
1643 #endif /* OBJ_COFF */
1644 } /* Make a new symbol. */
1646 symbol_table_insert (symbolP
);
1651 && S_IS_DEFINED (symbolP
)
1652 && S_GET_SEGMENT (symbolP
) != reg_section
)
1653 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1655 pseudo_set (symbolP
);
1657 demand_empty_rest_of_line ();
1659 /* XXX Now we come to the Thumb specific bit of code. */
1661 THUMB_SET_FUNC (symbolP
, 1);
1662 ARM_SET_THUMB (symbolP
, 1);
1663 #if defined OBJ_ELF || defined OBJ_COFF
1664 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1668 /* If we change section we must dump the literal pool first. */
1674 if (now_seg
!= text_section
)
1678 obj_elf_text (ignore
);
1688 if (flag_readonly_data_in_text
)
1690 if (now_seg
!= text_section
)
1693 else if (now_seg
!= data_section
)
1697 obj_elf_data (ignore
);
1705 arm_s_section (ignore
)
1710 obj_elf_section (ignore
);
1715 opcode_select (width
)
1723 if (! (cpu_variant
& ARM_EXT_THUMB
))
1724 as_bad (_("selected processor does not support THUMB opcodes"));
1727 /* No need to force the alignment, since we will have been
1728 coming from ARM mode, which is word-aligned. */
1729 record_alignment (now_seg
, 1);
1736 if ((cpu_variant
& ARM_ANY
) == ARM_EXT_THUMB
)
1737 as_bad (_("selected processor does not support ARM opcodes"));
1742 frag_align (2, 0, 0);
1744 record_alignment (now_seg
, 1);
1749 as_bad (_("invalid instruction size selected (%d)"), width
);
1755 int ignore ATTRIBUTE_UNUSED
;
1758 demand_empty_rest_of_line ();
1763 int ignore ATTRIBUTE_UNUSED
;
1766 demand_empty_rest_of_line ();
1771 int unused ATTRIBUTE_UNUSED
;
1775 temp
= get_absolute_expression ();
1780 opcode_select (temp
);
1784 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1792 skip_whitespace (str
);
1795 inst
.error
= _("Garbage following instruction");
1799 skip_past_comma (str
)
1802 char * p
= * str
, c
;
1805 while ((c
= *p
) == ' ' || c
== ',')
1808 if (c
== ',' && comma
++)
1816 return comma
? SUCCESS
: FAIL
;
1819 /* A standard register must be given at this point.
1820 SHIFT is the place to put it in inst.instruction.
1821 Restores input start point on error.
1822 Returns the reg#, or FAIL. */
1825 reg_required_here (str
, shift
)
1829 static char buff
[128]; /* XXX */
1831 char * start
= * str
;
1833 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1836 inst
.instruction
|= reg
<< shift
;
1840 /* Restore the start point, we may have got a reg of the wrong class. */
1843 /* In the few cases where we might be able to accept something else
1844 this error can be overridden. */
1845 sprintf (buff
, _("Register expected, not '%.100s'"), start
);
1851 static CONST
struct asm_psr
*
1853 register char ** ccp
;
1855 char * start
= * ccp
;
1858 CONST
struct asm_psr
* psr
;
1862 /* Skip to the end of the next word in the input stream. */
1867 while (ISALPHA (c
) || c
== '_');
1869 /* Terminate the word. */
1872 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1873 feature for ease of use and backwards compatibility. */
1874 if (!strncmp (start
, "cpsr", 4))
1875 strncpy (start
, "CPSR", 4);
1876 else if (!strncmp (start
, "spsr", 4))
1877 strncpy (start
, "SPSR", 4);
1879 /* Now locate the word in the psr hash table. */
1880 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
1882 /* Restore the input stream. */
1885 /* If we found a valid match, advance the
1886 stream pointer past the end of the word. */
1892 /* Parse the input looking for a PSR flag. */
1895 psr_required_here (str
)
1898 char * start
= * str
;
1899 CONST
struct asm_psr
* psr
;
1901 psr
= arm_psr_parse (str
);
1905 /* If this is the SPSR that is being modified, set the R bit. */
1907 inst
.instruction
|= SPSR_BIT
;
1909 /* Set the psr flags in the MSR instruction. */
1910 inst
.instruction
|= psr
->field
<< PSR_SHIFT
;
1915 /* In the few cases where we might be able to accept
1916 something else this error can be overridden. */
1917 inst
.error
= _("flag for {c}psr instruction expected");
1919 /* Restore the start point. */
1925 co_proc_number (str
)
1928 int processor
, pchar
;
1930 skip_whitespace (* str
);
1932 /* The data sheet seems to imply that just a number on its own is valid
1933 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1935 if (**str
== 'p' || **str
== 'P')
1939 if (pchar
>= '0' && pchar
<= '9')
1941 processor
= pchar
- '0';
1942 if (**str
>= '0' && **str
<= '9')
1944 processor
= processor
* 10 + *(*str
)++ - '0';
1947 inst
.error
= _("Illegal co-processor number");
1954 inst
.error
= _("Bad or missing co-processor number");
1958 inst
.instruction
|= processor
<< 8;
1963 cp_opc_expr (str
, where
, length
)
1970 skip_whitespace (* str
);
1972 memset (&expr
, '\0', sizeof (expr
));
1974 if (my_get_expression (&expr
, str
))
1976 if (expr
.X_op
!= O_constant
)
1978 inst
.error
= _("bad or missing expression");
1982 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1984 inst
.error
= _("immediate co-processor expression too large");
1988 inst
.instruction
|= expr
.X_add_number
<< where
;
1993 cp_reg_required_here (str
, where
)
1998 char * start
= *str
;
2000 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
2003 inst
.instruction
|= reg
<< where
;
2007 /* In the few cases where we might be able to accept something else
2008 this error can be overridden. */
2009 inst
.error
= _("Co-processor register expected");
2011 /* Restore the start point. */
2017 fp_reg_required_here (str
, where
)
2022 char * start
= * str
;
2024 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
2027 inst
.instruction
|= reg
<< where
;
2031 /* In the few cases where we might be able to accept something else
2032 this error can be overridden. */
2033 inst
.error
= _("Floating point register expected");
2035 /* Restore the start point. */
2041 cp_address_offset (str
)
2046 skip_whitespace (* str
);
2048 if (! is_immediate_prefix (**str
))
2050 inst
.error
= _("immediate expression expected");
2056 if (my_get_expression (& inst
.reloc
.exp
, str
))
2059 if (inst
.reloc
.exp
.X_op
== O_constant
)
2061 offset
= inst
.reloc
.exp
.X_add_number
;
2065 inst
.error
= _("co-processor address must be word aligned");
2069 if (offset
> 1023 || offset
< -1023)
2071 inst
.error
= _("offset too large");
2076 inst
.instruction
|= INDEX_UP
;
2080 inst
.instruction
|= offset
>> 2;
2083 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
2089 cp_address_required_here (str
)
2101 skip_whitespace (p
);
2103 if ((reg
= reg_required_here (& p
, 16)) == FAIL
)
2106 skip_whitespace (p
);
2112 if (skip_past_comma (& p
) == SUCCESS
)
2115 write_back
= WRITE_BACK
;
2119 inst
.error
= _("pc may not be used in post-increment");
2123 if (cp_address_offset (& p
) == FAIL
)
2127 pre_inc
= PRE_INDEX
| INDEX_UP
;
2131 /* '['Rn, #expr']'[!] */
2133 if (skip_past_comma (& p
) == FAIL
)
2135 inst
.error
= _("pre-indexed expression expected");
2139 pre_inc
= PRE_INDEX
;
2141 if (cp_address_offset (& p
) == FAIL
)
2144 skip_whitespace (p
);
2148 inst
.error
= _("missing ]");
2152 skip_whitespace (p
);
2158 inst
.error
= _("pc may not be used with write-back");
2163 write_back
= WRITE_BACK
;
2169 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2172 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
2173 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust. */
2174 inst
.reloc
.pc_rel
= 1;
2175 inst
.instruction
|= (REG_PC
<< 16);
2176 pre_inc
= PRE_INDEX
;
2179 inst
.instruction
|= write_back
| pre_inc
;
2187 unsigned long flags
;
2189 /* Do nothing really. */
2190 inst
.instruction
|= flags
; /* This is pointless. */
2198 unsigned long flags
;
2202 /* Only one syntax. */
2203 skip_whitespace (str
);
2205 if (reg_required_here (&str
, 12) == FAIL
)
2207 inst
.error
= BAD_ARGS
;
2211 if (skip_past_comma (&str
) == FAIL
)
2213 inst
.error
= _("comma expected after register name");
2217 skip_whitespace (str
);
2219 if ( strcmp (str
, "CPSR") == 0
2220 || strcmp (str
, "SPSR") == 0
2221 /* Lower case versions for backwards compatability. */
2222 || strcmp (str
, "cpsr") == 0
2223 || strcmp (str
, "spsr") == 0)
2226 /* This is for backwards compatability with older toolchains. */
2227 else if ( strcmp (str
, "cpsr_all") == 0
2228 || strcmp (str
, "spsr_all") == 0)
2232 inst
.error
= _("{C|S}PSR expected");
2236 if (* str
== 's' || * str
== 'S')
2237 inst
.instruction
|= SPSR_BIT
;
2240 inst
.instruction
|= flags
;
2244 /* Two possible forms:
2245 "{C|S}PSR_<field>, Rm",
2246 "{C|S}PSR_f, #expression". */
2251 unsigned long flags
;
2253 skip_whitespace (str
);
2255 if (psr_required_here (& str
) == FAIL
)
2258 if (skip_past_comma (& str
) == FAIL
)
2260 inst
.error
= _("comma missing after psr flags");
2264 skip_whitespace (str
);
2266 if (reg_required_here (& str
, 0) != FAIL
)
2269 inst
.instruction
|= flags
;
2274 if (! is_immediate_prefix (* str
))
2277 _("only a register or immediate value can follow a psr flag");
2284 if (my_get_expression (& inst
.reloc
.exp
, & str
))
2287 _("only a register or immediate value can follow a psr flag");
2291 #if 0 /* The first edition of the ARM architecture manual stated that
2292 writing anything other than the flags with an immediate operation
2293 had UNPREDICTABLE effects. This constraint was removed in the
2294 second edition of the specification. */
2295 if ((cpu_variant
& ARM_EXT_V5
) != ARM_EXT_V5
2296 && inst
.instruction
& ((PSR_c
| PSR_x
| PSR_s
) << PSR_SHIFT
))
2298 inst
.error
= _("immediate value cannot be used to set this field");
2303 flags
|= INST_IMMEDIATE
;
2305 if (inst
.reloc
.exp
.X_add_symbol
)
2307 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2308 inst
.reloc
.pc_rel
= 0;
2312 unsigned value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2314 if (value
== (unsigned) FAIL
)
2316 inst
.error
= _("Invalid constant");
2320 inst
.instruction
|= value
;
2324 inst
.instruction
|= flags
;
2328 /* Long Multiply Parser
2329 UMULL RdLo, RdHi, Rm, Rs
2330 SMULL RdLo, RdHi, Rm, Rs
2331 UMLAL RdLo, RdHi, Rm, Rs
2332 SMLAL RdLo, RdHi, Rm, Rs. */
2335 do_mull (str
, flags
)
2337 unsigned long flags
;
2339 int rdlo
, rdhi
, rm
, rs
;
2341 /* Only one format "rdlo, rdhi, rm, rs". */
2342 skip_whitespace (str
);
2344 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
2346 inst
.error
= BAD_ARGS
;
2350 if (skip_past_comma (&str
) == FAIL
2351 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
2353 inst
.error
= BAD_ARGS
;
2357 if (skip_past_comma (&str
) == FAIL
2358 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2360 inst
.error
= BAD_ARGS
;
2364 /* rdhi, rdlo and rm must all be different. */
2365 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
2366 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2368 if (skip_past_comma (&str
) == FAIL
2369 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
2371 inst
.error
= BAD_ARGS
;
2375 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
2377 inst
.error
= BAD_PC
;
2381 inst
.instruction
|= flags
;
2389 unsigned long flags
;
2393 /* Only one format "rd, rm, rs". */
2394 skip_whitespace (str
);
2396 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2398 inst
.error
= BAD_ARGS
;
2404 inst
.error
= BAD_PC
;
2408 if (skip_past_comma (&str
) == FAIL
2409 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2411 inst
.error
= BAD_ARGS
;
2417 inst
.error
= BAD_PC
;
2422 as_tsktsk (_("rd and rm should be different in mul"));
2424 if (skip_past_comma (&str
) == FAIL
2425 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
2427 inst
.error
= BAD_ARGS
;
2433 inst
.error
= BAD_PC
;
2437 inst
.instruction
|= flags
;
2445 unsigned long flags
;
2449 /* Only one format "rd, rm, rs, rn". */
2450 skip_whitespace (str
);
2452 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2454 inst
.error
= BAD_ARGS
;
2460 inst
.error
= BAD_PC
;
2464 if (skip_past_comma (&str
) == FAIL
2465 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2467 inst
.error
= BAD_ARGS
;
2473 inst
.error
= BAD_PC
;
2478 as_tsktsk (_("rd and rm should be different in mla"));
2480 if (skip_past_comma (&str
) == FAIL
2481 || (rd
= reg_required_here (&str
, 8)) == FAIL
2482 || skip_past_comma (&str
) == FAIL
2483 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
2485 inst
.error
= BAD_ARGS
;
2489 if (rd
== REG_PC
|| rm
== REG_PC
)
2491 inst
.error
= BAD_PC
;
2495 inst
.instruction
|= flags
;
2500 /* Expects *str -> the characters "acc0", possibly with leading blanks.
2501 Advances *str to the next non-alphanumeric.
2502 Returns 0, or else FAIL (in which case sets inst.error).
2504 (In a future XScale, there may be accumulators other than zero.
2505 At that time this routine and its callers can be upgraded to suit.) */
2508 accum0_required_here (str
)
2511 static char buff
[128]; /* Note the address is taken. Hence, static. */
2514 int result
= 0; /* The accum number. */
2516 skip_whitespace (p
);
2518 *str
= p
; /* Advance caller's string pointer too. */
2523 *--p
= 0; /* Aap nul into input buffer at non-alnum. */
2525 if (! ( streq (*str
, "acc0") || streq (*str
, "ACC0")))
2527 sprintf (buff
, _("acc0 expected, not '%.100s'"), *str
);
2532 *p
= c
; /* Unzap. */
2533 *str
= p
; /* Caller's string pointer to after match. */
2537 /* Expects **str -> after a comma. May be leading blanks.
2538 Advances *str, recognizing a load mode, and setting inst.instruction.
2539 Returns rn, or else FAIL (in which case may set inst.error
2540 and not advance str)
2542 Note: doesn't know Rd, so no err checks that require such knowledge. */
2545 ld_mode_required_here (string
)
2548 char * str
= * string
;
2552 skip_whitespace (str
);
2558 skip_whitespace (str
);
2560 if ((rn
= reg_required_here (& str
, 16)) == FAIL
)
2563 skip_whitespace (str
);
2569 if (skip_past_comma (& str
) == SUCCESS
)
2571 /* [Rn],... (post inc) */
2572 if (ldst_extend (& str
, 1) == FAIL
)
2577 skip_whitespace (str
);
2582 inst
.instruction
|= WRITE_BACK
;
2585 inst
.instruction
|= INDEX_UP
| HWOFFSET_IMM
;
2591 if (skip_past_comma (& str
) == FAIL
)
2593 inst
.error
= _("pre-indexed expression expected");
2599 if (ldst_extend (& str
, 1) == FAIL
)
2602 skip_whitespace (str
);
2604 if (* str
++ != ']')
2606 inst
.error
= _("missing ]");
2610 skip_whitespace (str
);
2615 inst
.instruction
|= WRITE_BACK
;
2619 else if (* str
== '=') /* ldr's "r,=label" syntax */
2620 /* We should never reach here, because <text> = <expression> is
2621 caught gas/read.c read_a_source_file() as a .set operation. */
2623 else /* PC +- 8 bit immediate offset. */
2625 if (my_get_expression (& inst
.reloc
.exp
, & str
))
2628 inst
.instruction
|= HWOFFSET_IMM
; /* The I bit. */
2629 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2630 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust. */
2631 inst
.reloc
.pc_rel
= 1;
2632 inst
.instruction
|= (REG_PC
<< 16);
2638 inst
.instruction
|= (pre_inc
? PRE_INDEX
: 0);
2644 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
2645 SMLAxy{cond} Rd,Rm,Rs,Rn
2646 SMLAWy{cond} Rd,Rm,Rs,Rn
2647 Error if any register is R15. */
2650 do_smla (str
, flags
)
2652 unsigned long flags
;
2656 skip_whitespace (str
);
2658 if ((rd
= reg_required_here (& str
, 16)) == FAIL
2659 || skip_past_comma (& str
) == FAIL
2660 || (rm
= reg_required_here (& str
, 0)) == FAIL
2661 || skip_past_comma (& str
) == FAIL
2662 || (rs
= reg_required_here (& str
, 8)) == FAIL
2663 || skip_past_comma (& str
) == FAIL
2664 || (rn
= reg_required_here (& str
, 12)) == FAIL
)
2665 inst
.error
= BAD_ARGS
;
2667 else if (rd
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
|| rn
== REG_PC
)
2668 inst
.error
= BAD_PC
;
2671 inst
.error
= BAD_FLAGS
;
2677 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
2678 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
2679 Error if any register is R15.
2680 Warning if Rdlo == Rdhi. */
2683 do_smlal (str
, flags
)
2685 unsigned long flags
;
2687 int rdlo
, rdhi
, rm
, rs
;
2689 skip_whitespace (str
);
2691 if ((rdlo
= reg_required_here (& str
, 12)) == FAIL
2692 || skip_past_comma (& str
) == FAIL
2693 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
2694 || skip_past_comma (& str
) == FAIL
2695 || (rm
= reg_required_here (& str
, 0)) == FAIL
2696 || skip_past_comma (& str
) == FAIL
2697 || (rs
= reg_required_here (& str
, 8)) == FAIL
)
2699 inst
.error
= BAD_ARGS
;
2703 if (rdlo
== REG_PC
|| rdhi
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
)
2705 inst
.error
= BAD_PC
;
2710 as_tsktsk (_("rdhi and rdlo must be different"));
2713 inst
.error
= BAD_FLAGS
;
2718 /* ARM V5E (El Segundo) signed-multiply (argument parse)
2719 SMULxy{cond} Rd,Rm,Rs
2720 Error if any register is R15. */
2723 do_smul (str
, flags
)
2725 unsigned long flags
;
2729 skip_whitespace (str
);
2731 if ((rd
= reg_required_here (& str
, 16)) == FAIL
2732 || skip_past_comma (& str
) == FAIL
2733 || (rm
= reg_required_here (& str
, 0)) == FAIL
2734 || skip_past_comma (& str
) == FAIL
2735 || (rs
= reg_required_here (& str
, 8)) == FAIL
)
2736 inst
.error
= BAD_ARGS
;
2738 else if (rd
== REG_PC
|| rm
== REG_PC
|| rs
== REG_PC
)
2739 inst
.error
= BAD_PC
;
2742 inst
.error
= BAD_FLAGS
;
2748 /* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
2749 Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
2750 Error if any register is R15. */
2753 do_qadd (str
, flags
)
2755 unsigned long flags
;
2759 skip_whitespace (str
);
2761 if ((rd
= reg_required_here (& str
, 12)) == FAIL
2762 || skip_past_comma (& str
) == FAIL
2763 || (rm
= reg_required_here (& str
, 0)) == FAIL
2764 || skip_past_comma (& str
) == FAIL
2765 || (rn
= reg_required_here (& str
, 16)) == FAIL
)
2766 inst
.error
= BAD_ARGS
;
2768 else if (rd
== REG_PC
|| rm
== REG_PC
|| rn
== REG_PC
)
2769 inst
.error
= BAD_PC
;
2772 inst
.error
= BAD_FLAGS
;
2778 /* ARM V5E (el Segundo)
2779 MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2780 MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2782 These are equivalent to the XScale instructions MAR and MRA,
2783 respectively, when coproc == 0, opcode == 0, and CRm == 0.
2785 Result unpredicatable if Rd or Rn is R15. */
2788 do_co_reg2c (str
, flags
)
2790 unsigned long flags
;
2794 skip_whitespace (str
);
2796 if (co_proc_number (& str
) == FAIL
)
2799 inst
.error
= BAD_ARGS
;
2803 if (skip_past_comma (& str
) == FAIL
2804 || cp_opc_expr (& str
, 4, 4) == FAIL
)
2807 inst
.error
= BAD_ARGS
;
2811 if (skip_past_comma (& str
) == FAIL
2812 || (rd
= reg_required_here (& str
, 12)) == FAIL
)
2815 inst
.error
= BAD_ARGS
;
2819 if (skip_past_comma (& str
) == FAIL
2820 || (rn
= reg_required_here (& str
, 16)) == FAIL
)
2823 inst
.error
= BAD_ARGS
;
2827 /* Unpredictable result if rd or rn is R15. */
2828 if (rd
== REG_PC
|| rn
== REG_PC
)
2830 (_("Warning: Instruction unpredictable when using r15"));
2832 if (skip_past_comma (& str
) == FAIL
2833 || cp_reg_required_here (& str
, 0) == FAIL
)
2836 inst
.error
= BAD_ARGS
;
2841 inst
.error
= BAD_COND
;
2846 /* ARM V5 count-leading-zeroes instruction (argument parse)
2847 CLZ{<cond>} <Rd>, <Rm>
2848 Condition defaults to COND_ALWAYS.
2849 Error if Rd or Rm are R15. */
2854 unsigned long flags
;
2864 skip_whitespace (str
);
2866 if (((rd
= reg_required_here (& str
, 12)) == FAIL
)
2867 || (skip_past_comma (& str
) == FAIL
)
2868 || ((rm
= reg_required_here (& str
, 0)) == FAIL
))
2869 inst
.error
= BAD_ARGS
;
2871 else if (rd
== REG_PC
|| rm
== REG_PC
)
2872 inst
.error
= BAD_PC
;
2878 /* ARM V5 (argument parse)
2879 LDC2{L} <coproc>, <CRd>, <addressing mode>
2880 STC2{L} <coproc>, <CRd>, <addressing mode>
2881 Instruction is not conditional, and has 0xf in the codition field.
2882 Otherwise, it's the same as LDC/STC. */
2885 do_lstc2 (str
, flags
)
2887 unsigned long flags
;
2890 inst
.error
= BAD_COND
;
2892 skip_whitespace (str
);
2894 if (co_proc_number (& str
) == FAIL
)
2897 inst
.error
= BAD_ARGS
;
2899 else if (skip_past_comma (& str
) == FAIL
2900 || cp_reg_required_here (& str
, 12) == FAIL
)
2903 inst
.error
= BAD_ARGS
;
2905 else if (skip_past_comma (& str
) == FAIL
2906 || cp_address_required_here (& str
) == FAIL
)
2909 inst
.error
= BAD_ARGS
;
2915 /* ARM V5 (argument parse)
2916 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
2917 Instruction is not conditional, and has 0xf in the condition field.
2918 Otherwise, it's the same as CDP. */
2921 do_cdp2 (str
, flags
)
2923 unsigned long flags
;
2925 skip_whitespace (str
);
2927 if (co_proc_number (& str
) == FAIL
)
2930 inst
.error
= BAD_ARGS
;
2934 if (skip_past_comma (& str
) == FAIL
2935 || cp_opc_expr (& str
, 20,4) == FAIL
)
2938 inst
.error
= BAD_ARGS
;
2942 if (skip_past_comma (& str
) == FAIL
2943 || cp_reg_required_here (& str
, 12) == FAIL
)
2946 inst
.error
= BAD_ARGS
;
2950 if (skip_past_comma (& str
) == FAIL
2951 || cp_reg_required_here (& str
, 16) == FAIL
)
2954 inst
.error
= BAD_ARGS
;
2958 if (skip_past_comma (& str
) == FAIL
2959 || cp_reg_required_here (& str
, 0) == FAIL
)
2962 inst
.error
= BAD_ARGS
;
2966 if (skip_past_comma (& str
) == SUCCESS
)
2968 if (cp_opc_expr (& str
, 5, 3) == FAIL
)
2971 inst
.error
= BAD_ARGS
;
2977 inst
.error
= BAD_FLAGS
;
2982 /* ARM V5 (argument parse)
2983 MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2984 MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2985 Instruction is not conditional, and has 0xf in the condition field.
2986 Otherwise, it's the same as MCR/MRC. */
2989 do_co_reg2 (str
, flags
)
2991 unsigned long flags
;
2993 skip_whitespace (str
);
2995 if (co_proc_number (& str
) == FAIL
)
2998 inst
.error
= BAD_ARGS
;
3002 if (skip_past_comma (& str
) == FAIL
3003 || cp_opc_expr (& str
, 21, 3) == FAIL
)
3006 inst
.error
= BAD_ARGS
;
3010 if (skip_past_comma (& str
) == FAIL
3011 || reg_required_here (& str
, 12) == FAIL
)
3014 inst
.error
= BAD_ARGS
;
3018 if (skip_past_comma (& str
) == FAIL
3019 || cp_reg_required_here (& str
, 16) == FAIL
)
3022 inst
.error
= BAD_ARGS
;
3026 if (skip_past_comma (& str
) == FAIL
3027 || cp_reg_required_here (& str
, 0) == FAIL
)
3030 inst
.error
= BAD_ARGS
;
3034 if (skip_past_comma (& str
) == SUCCESS
)
3036 if (cp_opc_expr (& str
, 5, 3) == FAIL
)
3039 inst
.error
= BAD_ARGS
;
3045 inst
.error
= BAD_COND
;
3050 /* THUMB V5 breakpoint instruction (argument parse)
3058 unsigned long number
;
3060 skip_whitespace (str
);
3062 /* Allow optional leading '#'. */
3063 if (is_immediate_prefix (*str
))
3066 memset (& expr
, '\0', sizeof (expr
));
3067 if (my_get_expression (& expr
, & str
) || (expr
.X_op
!= O_constant
))
3069 inst
.error
= _("bad or missing expression");
3073 number
= expr
.X_add_number
;
3075 /* Check it fits an 8 bit unsigned. */
3076 if (number
!= (number
& 0xff))
3078 inst
.error
= _("immediate value out of range");
3082 inst
.instruction
|= number
;
3087 /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
3088 Expects inst.instruction is set for BLX(1).
3089 Note: this is cloned from do_branch, and the reloc changed to be a
3090 new one that can cope with setting one extra bit (the H bit). */
3093 do_branch25 (str
, flags
)
3095 unsigned long flags ATTRIBUTE_UNUSED
;
3097 if (my_get_expression (& inst
.reloc
.exp
, & str
))
3104 /* ScottB: February 5, 1998 */
3105 /* Check to see of PLT32 reloc required for the instruction. */
3107 /* arm_parse_reloc() works on input_line_pointer.
3108 We actually want to parse the operands to the branch instruction
3109 passed in 'str'. Save the input pointer and restore it later. */
3110 save_in
= input_line_pointer
;
3111 input_line_pointer
= str
;
3113 if (inst
.reloc
.exp
.X_op
== O_symbol
3115 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
3117 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
3118 inst
.reloc
.pc_rel
= 0;
3119 /* Modify str to point to after parsed operands, otherwise
3120 end_of_line() will complain about the (PLT) left in str. */
3121 str
= input_line_pointer
;
3125 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BLX
;
3126 inst
.reloc
.pc_rel
= 1;
3129 input_line_pointer
= save_in
;
3132 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BLX
;
3133 inst
.reloc
.pc_rel
= 1;
3134 #endif /* OBJ_ELF */
3139 /* ARM V5 branch-link-exchange instruction (argument parse)
3140 BLX <target_addr> ie BLX(1)
3141 BLX{<condition>} <Rm> ie BLX(2)
3142 Unfortunately, there are two different opcodes for this mnemonic.
3143 So, the insns[].value is not used, and the code here zaps values
3144 into inst.instruction.
3145 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
3150 unsigned long flags
;
3161 skip_whitespace (mystr
);
3162 rm
= reg_required_here (& mystr
, 0);
3164 /* The above may set inst.error. Ignore his opinion. */
3169 /* Arg is a register.
3170 Use the condition code our caller put in inst.instruction.
3171 Pass ourselves off as a BX with a funny opcode. */
3172 inst
.instruction
|= 0x012fff30;
3177 /* This must be is BLX <target address>, no condition allowed. */
3178 if (inst
.instruction
!= COND_ALWAYS
)
3180 inst
.error
= BAD_COND
;
3184 inst
.instruction
= 0xfafffffe;
3186 /* Process like a B/BL, but with a different reloc.
3187 Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
3188 do_branch25 (str
, flags
);
3192 /* ARM V5 Thumb BLX (argument parse)
3193 BLX <target_addr> which is BLX(1)
3194 BLX <Rm> which is BLX(2)
3195 Unfortunately, there are two different opcodes for this mnemonic.
3196 So, the tinsns[].value is not used, and the code here zaps values
3197 into inst.instruction. */
3206 skip_whitespace (mystr
);
3207 inst
.instruction
= 0x4780;
3209 /* Note that this call is to the ARM register recognizer. BLX(2)
3210 uses the ARM register space, not the Thumb one, so a call to
3211 thumb_reg() would be wrong. */
3212 rm
= reg_required_here (& mystr
, 3);
3217 /* It's BLX(2). The .instruction was zapped with rm & is final. */
3222 /* No ARM register. This must be BLX(1). Change the .instruction. */
3223 inst
.instruction
= 0xf7ffeffe;
3226 if (my_get_expression (& inst
.reloc
.exp
, & mystr
))
3229 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
3230 inst
.reloc
.pc_rel
= 1;
3233 end_of_line (mystr
);
3236 /* ARM V5 breakpoint instruction (argument parse)
3237 BKPT <16 bit unsigned immediate>
3238 Instruction is not conditional.
3239 The bit pattern given in insns[] has the COND_ALWAYS condition,
3240 and it is an error if the caller tried to override that.
3241 Note "flags" is nonzero if a flag was supplied (which is an error). */
3244 do_bkpt (str
, flags
)
3246 unsigned long flags
;
3249 unsigned long number
;
3251 skip_whitespace (str
);
3253 /* Allow optional leading '#'. */
3254 if (is_immediate_prefix (* str
))
3257 memset (& expr
, '\0', sizeof (expr
));
3259 if (my_get_expression (& expr
, & str
) || (expr
.X_op
!= O_constant
))
3261 inst
.error
= _("bad or missing expression");
3265 number
= expr
.X_add_number
;
3267 /* Check it fits a 16 bit unsigned. */
3268 if (number
!= (number
& 0xffff))
3270 inst
.error
= _("immediate value out of range");
3274 /* Top 12 of 16 bits to bits 19:8. */
3275 inst
.instruction
|= (number
& 0xfff0) << 4;
3277 /* Bottom 4 of 16 bits to bits 3:0. */
3278 inst
.instruction
|= number
& 0xf;
3283 inst
.error
= BAD_FLAGS
;
3286 /* Xscale multiply-accumulate (argument parse)
3289 MIAxycc acc0,Rm,Rs. */
3294 unsigned long flags
;
3302 else if (accum0_required_here (& str
) == FAIL
)
3303 inst
.error
= ERR_NO_ACCUM
;
3305 else if (skip_past_comma (& str
) == FAIL
3306 || (rm
= reg_required_here (& str
, 0)) == FAIL
)
3307 inst
.error
= BAD_ARGS
;
3309 else if (skip_past_comma (& str
) == FAIL
3310 || (rs
= reg_required_here (& str
, 12)) == FAIL
)
3311 inst
.error
= BAD_ARGS
;
3313 /* inst.instruction has now been zapped with both rm and rs. */
3314 else if (rm
== REG_PC
|| rs
== REG_PC
)
3315 inst
.error
= BAD_PC
; /* Undefined result if rm or rs is R15. */
3321 /* Xscale move-accumulator-register (argument parse)
3323 MARcc acc0,RdLo,RdHi. */
3328 unsigned long flags
;
3335 else if (accum0_required_here (& str
) == FAIL
)
3336 inst
.error
= ERR_NO_ACCUM
;
3338 else if (skip_past_comma (& str
) == FAIL
3339 || (rdlo
= reg_required_here (& str
, 12)) == FAIL
)
3340 inst
.error
= BAD_ARGS
;
3342 else if (skip_past_comma (& str
) == FAIL
3343 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
)
3344 inst
.error
= BAD_ARGS
;
3346 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3347 else if (rdlo
== REG_PC
|| rdhi
== REG_PC
)
3348 inst
.error
= BAD_PC
; /* Undefined result if rdlo or rdhi is R15. */
3354 /* Xscale move-register-accumulator (argument parse)
3356 MRAcc RdLo,RdHi,acc0. */
3361 unsigned long flags
;
3372 skip_whitespace (str
);
3374 if ((rdlo
= reg_required_here (& str
, 12)) == FAIL
)
3375 inst
.error
= BAD_ARGS
;
3377 else if (skip_past_comma (& str
) == FAIL
3378 || (rdhi
= reg_required_here (& str
, 16)) == FAIL
)
3379 inst
.error
= BAD_ARGS
;
3381 else if (skip_past_comma (& str
) == FAIL
3382 || accum0_required_here (& str
) == FAIL
)
3383 inst
.error
= ERR_NO_ACCUM
;
3385 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3386 else if (rdlo
== rdhi
)
3387 inst
.error
= BAD_ARGS
; /* Undefined result if 2 writes to same reg. */
3389 else if (rdlo
== REG_PC
|| rdhi
== REG_PC
)
3390 inst
.error
= BAD_PC
; /* Undefined result if rdlo or rdhi is R15. */
3395 /* Xscale: Preload-Cache
3399 Syntactically, like LDR with B=1, W=0, L=1. */
3404 unsigned long flags
;
3414 skip_whitespace (str
);
3418 inst
.error
= _("'[' expected after PLD mnemonic");
3423 skip_whitespace (str
);
3425 if ((rd
= reg_required_here (& str
, 16)) == FAIL
)
3428 skip_whitespace (str
);
3434 skip_whitespace (str
);
3436 if (skip_past_comma (& str
) == SUCCESS
)
3438 if (ldst_extend (& str
, 0) == FAIL
)
3441 else if (* str
== '!') /* [Rn]! */
3443 inst
.error
= _("writeback used in preload instruction");
3447 inst
.instruction
|= INDEX_UP
| PRE_INDEX
;
3449 else /* [Rn, ...] */
3451 if (skip_past_comma (& str
) == FAIL
)
3453 inst
.error
= _("pre-indexed expression expected");
3457 if (ldst_extend (& str
, 0) == FAIL
)
3460 skip_whitespace (str
);
3464 inst
.error
= _("missing ]");
3469 skip_whitespace (str
);
3471 if (* str
== '!') /* [Rn]! */
3473 inst
.error
= _("writeback used in preload instruction");
3477 inst
.instruction
|= PRE_INDEX
;
3483 /* Xscale load-consecutive (argument parse)
3490 do_ldrd (str
, flags
)
3492 unsigned long flags
;
3497 if (flags
!= DOUBLE_LOAD_FLAG
)
3499 /* Change instruction pattern to normal ldr/str. */
3500 if (inst
.instruction
& 0x20)
3501 inst
.instruction
= (inst
.instruction
& COND_MASK
) | 0x04000000; /* str */
3503 inst
.instruction
= (inst
.instruction
& COND_MASK
) | 0x04100000; /* ldr */
3505 /* Perform a normal load/store instruction parse. */
3506 do_ldst (str
, flags
);
3511 if ((cpu_variant
& ARM_EXT_XSCALE
) != ARM_EXT_XSCALE
)
3513 static char buff
[128];
3516 while (ISSPACE (*str
))
3520 /* Deny all knowledge. */
3521 sprintf (buff
, _("bad instruction '%.100s'"), str
);
3526 skip_whitespace (str
);
3528 if ((rd
= reg_required_here (& str
, 12)) == FAIL
)
3530 inst
.error
= BAD_ARGS
;
3534 if (skip_past_comma (& str
) == FAIL
3535 || (rn
= ld_mode_required_here (& str
)) == FAIL
)
3538 inst
.error
= BAD_ARGS
;
3542 /* inst.instruction has now been zapped with Rd and the addressing mode. */
3543 if (rd
& 1) /* Unpredictable result if Rd is odd. */
3545 inst
.error
= _("Destination register must be even");
3549 if (rd
== REG_LR
|| rd
== 12)
3551 inst
.error
= _("r12 or r14 not allowed here");
3555 if (((rd
== rn
) || (rd
+ 1 == rn
))
3557 ((inst
.instruction
& WRITE_BACK
)
3558 || (!(inst
.instruction
& PRE_INDEX
))))
3559 as_warn (_("pre/post-indexing used when modified address register is destination"));
3564 /* Returns the index into fp_values of a floating point number,
3565 or -1 if not in the table. */
3568 my_get_float_expression (str
)
3571 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3577 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
3579 /* Look for a raw floating point number. */
3580 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
3581 && is_end_of_line
[(unsigned char) *save_in
])
3583 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3585 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3587 if (words
[j
] != fp_values
[i
][j
])
3591 if (j
== MAX_LITTLENUMS
)
3599 /* Try and parse a more complex expression, this will probably fail
3600 unless the code uses a floating point prefix (eg "0f"). */
3601 save_in
= input_line_pointer
;
3602 input_line_pointer
= *str
;
3603 if (expression (&exp
) == absolute_section
3604 && exp
.X_op
== O_big
3605 && exp
.X_add_number
< 0)
3607 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3609 if (gen_to_words (words
, 5, (long) 15) == 0)
3611 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3613 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3615 if (words
[j
] != fp_values
[i
][j
])
3619 if (j
== MAX_LITTLENUMS
)
3621 *str
= input_line_pointer
;
3622 input_line_pointer
= save_in
;
3629 *str
= input_line_pointer
;
3630 input_line_pointer
= save_in
;
3634 /* Return true if anything in the expression is a bignum. */
3637 walk_no_bignums (sp
)
3640 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
3643 if (symbol_get_value_expression (sp
)->X_add_symbol
)
3645 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
3646 || (symbol_get_value_expression (sp
)->X_op_symbol
3647 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
3654 my_get_expression (ep
, str
)
3661 save_in
= input_line_pointer
;
3662 input_line_pointer
= *str
;
3663 seg
= expression (ep
);
3666 if (seg
!= absolute_section
3667 && seg
!= text_section
3668 && seg
!= data_section
3669 && seg
!= bss_section
3670 && seg
!= undefined_section
)
3672 inst
.error
= _("bad_segment");
3673 *str
= input_line_pointer
;
3674 input_line_pointer
= save_in
;
3679 /* Get rid of any bignums now, so that we don't generate an error for which
3680 we can't establish a line number later on. Big numbers are never valid
3681 in instructions, which is where this routine is always called. */
3682 if (ep
->X_op
== O_big
3683 || (ep
->X_add_symbol
3684 && (walk_no_bignums (ep
->X_add_symbol
)
3686 && walk_no_bignums (ep
->X_op_symbol
)))))
3688 inst
.error
= _("Invalid constant");
3689 *str
= input_line_pointer
;
3690 input_line_pointer
= save_in
;
3694 *str
= input_line_pointer
;
3695 input_line_pointer
= save_in
;
3699 /* UNRESTRICT should be one if <shift> <register> is permitted for this
3703 decode_shift (str
, unrestrict
)
3707 const struct asm_shift_name
* shift
;
3711 skip_whitespace (* str
);
3713 for (p
= * str
; ISALPHA (* p
); p
++)
3718 inst
.error
= _("Shift expression expected");
3724 shift
= (const struct asm_shift_name
*) hash_find (arm_shift_hsh
, * str
);
3729 inst
.error
= _("Shift expression expected");
3733 assert (shift
->properties
->index
== shift_properties
[shift
->properties
->index
].index
);
3735 if (shift
->properties
->index
== SHIFT_RRX
)
3738 inst
.instruction
|= shift
->properties
->bit_field
;
3742 skip_whitespace (p
);
3744 if (unrestrict
&& reg_required_here (& p
, 8) != FAIL
)
3746 inst
.instruction
|= shift
->properties
->bit_field
| SHIFT_BY_REG
;
3750 else if (! is_immediate_prefix (* p
))
3752 inst
.error
= (unrestrict
3753 ? _("shift requires register or #expression")
3754 : _("shift requires #expression"));
3762 if (my_get_expression (& inst
.reloc
.exp
, & p
))
3765 /* Validate some simple #expressions. */
3766 if (inst
.reloc
.exp
.X_op
== O_constant
)
3768 unsigned num
= inst
.reloc
.exp
.X_add_number
;
3770 /* Reject operations greater than 32. */
3772 /* Reject a shift of 0 unless the mode allows it. */
3773 || (num
== 0 && shift
->properties
->allows_0
== 0)
3774 /* Reject a shift of 32 unless the mode allows it. */
3775 || (num
== 32 && shift
->properties
->allows_32
== 0)
3778 /* As a special case we allow a shift of zero for
3779 modes that do not support it to be recoded as an
3780 logical shift left of zero (ie nothing). We warn
3781 about this though. */
3784 as_warn (_("Shift of 0 ignored."));
3785 shift
= & shift_names
[0];
3786 assert (shift
->properties
->index
== SHIFT_LSL
);
3790 inst
.error
= _("Invalid immediate shift");
3795 /* Shifts of 32 are encoded as 0, for those shifts that
3800 inst
.instruction
|= (num
<< 7) | shift
->properties
->bit_field
;
3804 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
3805 inst
.reloc
.pc_rel
= 0;
3806 inst
.instruction
|= shift
->properties
->bit_field
;
3813 /* Do those data_ops which can take a negative immediate constant
3814 by altering the instuction. A bit of a hack really.
3818 by inverting the second operand, and
3821 by negating the second operand. */
3824 negate_data_op (instruction
, value
)
3825 unsigned long * instruction
;
3826 unsigned long value
;
3829 unsigned long negated
, inverted
;
3831 negated
= validate_immediate (-value
);
3832 inverted
= validate_immediate (~value
);
3834 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
3837 /* First negates. */
3838 case OPCODE_SUB
: /* ADD <-> SUB */
3839 new_inst
= OPCODE_ADD
;
3844 new_inst
= OPCODE_SUB
;
3848 case OPCODE_CMP
: /* CMP <-> CMN */
3849 new_inst
= OPCODE_CMN
;
3854 new_inst
= OPCODE_CMP
;
3858 /* Now Inverted ops. */
3859 case OPCODE_MOV
: /* MOV <-> MVN */
3860 new_inst
= OPCODE_MVN
;
3865 new_inst
= OPCODE_MOV
;
3869 case OPCODE_AND
: /* AND <-> BIC */
3870 new_inst
= OPCODE_BIC
;
3875 new_inst
= OPCODE_AND
;
3879 case OPCODE_ADC
: /* ADC <-> SBC */
3880 new_inst
= OPCODE_SBC
;
3885 new_inst
= OPCODE_ADC
;
3889 /* We cannot do anything. */
3894 if (value
== (unsigned) FAIL
)
3897 *instruction
&= OPCODE_MASK
;
3898 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
3909 skip_whitespace (* str
);
3911 if (reg_required_here (str
, 0) != FAIL
)
3913 if (skip_past_comma (str
) == SUCCESS
)
3914 /* Shift operation on register. */
3915 return decode_shift (str
, NO_SHIFT_RESTRICT
);
3921 /* Immediate expression. */
3922 if (is_immediate_prefix (**str
))
3927 if (my_get_expression (&inst
.reloc
.exp
, str
))
3930 if (inst
.reloc
.exp
.X_add_symbol
)
3932 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3933 inst
.reloc
.pc_rel
= 0;
3937 if (skip_past_comma (str
) == SUCCESS
)
3939 /* #x, y -- ie explicit rotation by Y. */
3940 if (my_get_expression (&expr
, str
))
3943 if (expr
.X_op
!= O_constant
)
3945 inst
.error
= _("Constant expression expected");
3949 /* Rotate must be a multiple of 2. */
3950 if (((unsigned) expr
.X_add_number
) > 30
3951 || (expr
.X_add_number
& 1) != 0
3952 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
3954 inst
.error
= _("Invalid constant");
3957 inst
.instruction
|= INST_IMMEDIATE
;
3958 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
3959 inst
.instruction
|= expr
.X_add_number
<< 7;
3963 /* Implicit rotation, select a suitable one. */
3964 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
3968 /* Can't be done. Perhaps the code reads something like
3969 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
3970 if ((value
= negate_data_op (&inst
.instruction
,
3971 inst
.reloc
.exp
.X_add_number
))
3974 inst
.error
= _("Invalid constant");
3979 inst
.instruction
|= value
;
3982 inst
.instruction
|= INST_IMMEDIATE
;
3987 inst
.error
= _("Register or shift expression expected");
3996 skip_whitespace (* str
);
3998 if (fp_reg_required_here (str
, 0) != FAIL
)
4002 /* Immediate expression. */
4003 if (*((*str
)++) == '#')
4009 skip_whitespace (* str
);
4011 /* First try and match exact strings, this is to guarantee
4012 that some formats will work even for cross assembly. */
4014 for (i
= 0; fp_const
[i
]; i
++)
4016 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4020 *str
+= strlen (fp_const
[i
]);
4021 if (is_end_of_line
[(unsigned char) **str
])
4023 inst
.instruction
|= i
+ 8;
4030 /* Just because we didn't get a match doesn't mean that the
4031 constant isn't valid, just that it is in a format that we
4032 don't automatically recognize. Try parsing it with
4033 the standard expression routines. */
4034 if ((i
= my_get_float_expression (str
)) >= 0)
4036 inst
.instruction
|= i
+ 8;
4040 inst
.error
= _("Invalid floating point immediate expression");
4044 _("Floating point register or immediate expression expected");
4050 do_arit (str
, flags
)
4052 unsigned long flags
;
4054 skip_whitespace (str
);
4056 if (reg_required_here (&str
, 12) == FAIL
4057 || skip_past_comma (&str
) == FAIL
4058 || reg_required_here (&str
, 16) == FAIL
4059 || skip_past_comma (&str
) == FAIL
4060 || data_op2 (&str
) == FAIL
)
4063 inst
.error
= BAD_ARGS
;
4067 inst
.instruction
|= flags
;
4075 unsigned long flags
;
4077 skip_whitespace (str
);
4079 if (reg_required_here (&str
, 12) == FAIL
4080 || skip_past_comma (&str
) == FAIL
4081 || my_get_expression (&inst
.reloc
.exp
, &str
))
4084 inst
.error
= BAD_ARGS
;
4088 if (flags
& 0x00400000)
4090 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4091 into a relative address of the form:
4092 add rd, pc, #low(label-.-8)"
4093 add rd, rd, #high(label-.-8)" */
4094 /* Frag hacking will turn this into a sub instruction if the offset turns
4095 out to be negative. */
4096 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4097 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
4098 inst
.reloc
.pc_rel
= 1;
4099 inst
.instruction
|= flags
& ~0x00400000;
4100 inst
.size
= INSN_SIZE
* 2;
4104 /* This is a pseudo-op of the form "adr rd, label" to be converted
4105 into a relative address of the form "add rd, pc, #label-.-8". */
4106 /* Frag hacking will turn this into a sub instruction if the offset turns
4107 out to be negative. */
4108 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4109 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust. */
4110 inst
.reloc
.pc_rel
= 1;
4111 inst
.instruction
|= flags
;
4120 unsigned long flags
;
4122 skip_whitespace (str
);
4124 if (reg_required_here (&str
, 16) == FAIL
)
4127 inst
.error
= BAD_ARGS
;
4131 if (skip_past_comma (&str
) == FAIL
4132 || data_op2 (&str
) == FAIL
)
4135 inst
.error
= BAD_ARGS
;
4139 inst
.instruction
|= flags
;
4140 if ((flags
& 0x0000f000) == 0)
4141 inst
.instruction
|= CONDS_BIT
;
4150 unsigned long flags
;
4152 skip_whitespace (str
);
4154 if (reg_required_here (&str
, 12) == FAIL
)
4157 inst
.error
= BAD_ARGS
;
4161 if (skip_past_comma (&str
) == FAIL
4162 || data_op2 (&str
) == FAIL
)
4165 inst
.error
= BAD_ARGS
;
4169 inst
.instruction
|= flags
;
4175 ldst_extend (str
, hwse
)
4186 if (my_get_expression (& inst
.reloc
.exp
, str
))
4189 if (inst
.reloc
.exp
.X_op
== O_constant
)
4191 int value
= inst
.reloc
.exp
.X_add_number
;
4193 if ((hwse
&& (value
< -255 || value
> 255))
4194 || (value
< -4095 || value
> 4095))
4196 inst
.error
= _("address offset too large");
4206 /* Halfword and signextension instructions have the
4207 immediate value split across bits 11..8 and bits 3..0. */
4209 inst
.instruction
|= (add
| HWOFFSET_IMM
4210 | ((value
>> 4) << 8) | (value
& 0xF));
4212 inst
.instruction
|= add
| value
;
4218 inst
.instruction
|= HWOFFSET_IMM
;
4219 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4222 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4223 inst
.reloc
.pc_rel
= 0;
4236 if (reg_required_here (str
, 0) == FAIL
)
4240 inst
.instruction
|= add
;
4243 inst
.instruction
|= add
| OFFSET_REG
;
4244 if (skip_past_comma (str
) == SUCCESS
)
4245 return decode_shift (str
, SHIFT_RESTRICT
);
4253 do_ldst (str
, flags
)
4255 unsigned long flags
;
4262 /* This is not ideal, but it is the simplest way of dealing with the
4263 ARM7T halfword instructions (since they use a different
4264 encoding, but the same mnemonic): */
4265 halfword
= (flags
& 0x80000000) != 0;
4268 /* This is actually a load/store of a halfword, or a
4269 signed-extension load. */
4270 if ((cpu_variant
& ARM_EXT_HALFWORD
) == 0)
4273 = _("Processor does not support halfwords or signed bytes");
4277 inst
.instruction
= ((inst
.instruction
& COND_MASK
)
4278 | (flags
& ~COND_MASK
));
4283 skip_whitespace (str
);
4285 if ((conflict_reg
= reg_required_here (& str
, 12)) == FAIL
)
4288 inst
.error
= BAD_ARGS
;
4292 if (skip_past_comma (& str
) == FAIL
)
4294 inst
.error
= _("Address expected");
4304 skip_whitespace (str
);
4306 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
4309 /* Conflicts can occur on stores as well as loads. */
4310 conflict_reg
= (conflict_reg
== reg
);
4312 skip_whitespace (str
);
4318 if (skip_past_comma (&str
) == SUCCESS
)
4320 /* [Rn],... (post inc) */
4321 if (ldst_extend (&str
, halfword
) == FAIL
)
4325 if (flags
& TRANS_BIT
)
4326 as_warn (_("Rn and Rd must be different in %s"),
4327 ((inst
.instruction
& LOAD_BIT
)
4328 ? "LDRT" : "STRT"));
4330 as_warn (_("%s register same as write-back base"),
4331 ((inst
.instruction
& LOAD_BIT
)
4332 ? _("destination") : _("source")));
4339 inst
.instruction
|= HWOFFSET_IMM
;
4341 skip_whitespace (str
);
4346 as_warn (_("%s register same as write-back base"),
4347 ((inst
.instruction
& LOAD_BIT
)
4348 ? _("destination") : _("source")));
4350 inst
.instruction
|= WRITE_BACK
;
4354 if (flags
& TRANS_BIT
)
4357 as_warn (_("Rn and Rd must be different in %s"),
4358 ((inst
.instruction
& LOAD_BIT
)
4359 ? "LDRT" : "STRT"));
4368 if (skip_past_comma (&str
) == FAIL
)
4370 inst
.error
= _("pre-indexed expression expected");
4375 if (ldst_extend (&str
, halfword
) == FAIL
)
4378 skip_whitespace (str
);
4382 inst
.error
= _("missing ]");
4386 skip_whitespace (str
);
4391 as_warn (_("%s register same as write-back base"),
4392 ((inst
.instruction
& LOAD_BIT
)
4393 ? _("destination") : _("source")));
4395 inst
.instruction
|= WRITE_BACK
;
4399 else if (*str
== '=')
4401 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4404 skip_whitespace (str
);
4406 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4409 if (inst
.reloc
.exp
.X_op
!= O_constant
4410 && inst
.reloc
.exp
.X_op
!= O_symbol
)
4412 inst
.error
= _("Constant expression expected");
4416 if (inst
.reloc
.exp
.X_op
== O_constant
)
4418 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
4422 /* This can be done with a mov instruction. */
4423 inst
.instruction
&= LITERAL_MASK
;
4424 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4425 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
4430 value
= validate_immediate (~ inst
.reloc
.exp
.X_add_number
);
4434 /* This can be done with a mvn instruction. */
4435 inst
.instruction
&= LITERAL_MASK
;
4436 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
4437 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
4443 /* Insert into literal pool. */
4444 if (add_to_lit_pool () == FAIL
)
4447 inst
.error
= _("literal pool insertion failed");
4451 /* Change the instruction exp to point to the pool. */
4454 inst
.instruction
|= HWOFFSET_IMM
;
4455 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
4458 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
4460 inst
.reloc
.pc_rel
= 1;
4461 inst
.instruction
|= (REG_PC
<< 16);
4466 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4471 inst
.instruction
|= HWOFFSET_IMM
;
4472 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4475 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4477 /* PC rel adjust. */
4478 inst
.reloc
.exp
.X_add_number
-= 8;
4480 inst
.reloc
.pc_rel
= 1;
4481 inst
.instruction
|= (REG_PC
<< 16);
4485 if (pre_inc
&& (flags
& TRANS_BIT
))
4486 inst
.error
= _("Pre-increment instruction with translate");
4488 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
4497 char * str
= * strp
;
4501 /* We come back here if we get ranges concatenated by '+' or '|'. */
4516 skip_whitespace (str
);
4518 if ((reg
= reg_required_here (& str
, -1)) == FAIL
)
4527 inst
.error
= _("Bad range in register list");
4531 for (i
= cur_reg
+ 1; i
< reg
; i
++)
4533 if (range
& (1 << i
))
4535 (_("Warning: Duplicated register (r%d) in register list"),
4543 if (range
& (1 << reg
))
4544 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
4546 else if (reg
<= cur_reg
)
4547 as_tsktsk (_("Warning: Register range not in ascending order"));
4552 while (skip_past_comma (&str
) != FAIL
4553 || (in_range
= 1, *str
++ == '-'));
4555 skip_whitespace (str
);
4559 inst
.error
= _("Missing `}'");
4567 if (my_get_expression (&expr
, &str
))
4570 if (expr
.X_op
== O_constant
)
4572 if (expr
.X_add_number
4573 != (expr
.X_add_number
& 0x0000ffff))
4575 inst
.error
= _("invalid register mask");
4579 if ((range
& expr
.X_add_number
) != 0)
4581 int regno
= range
& expr
.X_add_number
;
4584 regno
= (1 << regno
) - 1;
4586 (_("Warning: Duplicated register (r%d) in register list"),
4590 range
|= expr
.X_add_number
;
4594 if (inst
.reloc
.type
!= 0)
4596 inst
.error
= _("expression too complex");
4600 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
4601 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
4602 inst
.reloc
.pc_rel
= 0;
4606 skip_whitespace (str
);
4608 if (*str
== '|' || *str
== '+')
4614 while (another_range
);
4621 do_ldmstm (str
, flags
)
4623 unsigned long flags
;
4628 skip_whitespace (str
);
4630 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
4633 if (base_reg
== REG_PC
)
4635 inst
.error
= _("r15 not allowed as base register");
4639 skip_whitespace (str
);
4643 flags
|= WRITE_BACK
;
4647 if (skip_past_comma (&str
) == FAIL
4648 || (range
= reg_list (&str
)) == FAIL
)
4651 inst
.error
= BAD_ARGS
;
4658 flags
|= LDM_TYPE_2_OR_3
;
4661 inst
.instruction
|= flags
| range
;
4669 unsigned long flags
;
4671 skip_whitespace (str
);
4673 /* Allow optional leading '#'. */
4674 if (is_immediate_prefix (*str
))
4677 if (my_get_expression (& inst
.reloc
.exp
, & str
))
4680 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
4681 inst
.reloc
.pc_rel
= 0;
4682 inst
.instruction
|= flags
;
4690 do_swap (str
, flags
)
4692 unsigned long flags
;
4696 skip_whitespace (str
);
4698 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
4703 inst
.error
= _("r15 not allowed in swap");
4707 if (skip_past_comma (&str
) == FAIL
4708 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
4711 inst
.error
= BAD_ARGS
;
4717 inst
.error
= _("r15 not allowed in swap");
4721 if (skip_past_comma (&str
) == FAIL
4724 inst
.error
= BAD_ARGS
;
4728 skip_whitespace (str
);
4730 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
4735 inst
.error
= BAD_PC
;
4739 skip_whitespace (str
);
4743 inst
.error
= _("missing ]");
4747 inst
.instruction
|= flags
;
4753 do_branch (str
, flags
)
4755 unsigned long flags ATTRIBUTE_UNUSED
;
4757 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4764 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
4765 required for the instruction. */
4767 /* arm_parse_reloc () works on input_line_pointer.
4768 We actually want to parse the operands to the branch instruction
4769 passed in 'str'. Save the input pointer and restore it later. */
4770 save_in
= input_line_pointer
;
4771 input_line_pointer
= str
;
4772 if (inst
.reloc
.exp
.X_op
== O_symbol
4774 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
4776 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4777 inst
.reloc
.pc_rel
= 0;
4778 /* Modify str to point to after parsed operands, otherwise
4779 end_of_line() will complain about the (PLT) left in str. */
4780 str
= input_line_pointer
;
4784 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
4785 inst
.reloc
.pc_rel
= 1;
4787 input_line_pointer
= save_in
;
4790 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
4791 inst
.reloc
.pc_rel
= 1;
4792 #endif /* OBJ_ELF */
4801 unsigned long flags ATTRIBUTE_UNUSED
;
4805 skip_whitespace (str
);
4807 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
4809 inst
.error
= BAD_ARGS
;
4813 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
4815 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
4823 unsigned long flags ATTRIBUTE_UNUSED
;
4825 /* Co-processor data operation.
4826 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
4827 skip_whitespace (str
);
4829 if (co_proc_number (&str
) == FAIL
)
4832 inst
.error
= BAD_ARGS
;
4836 if (skip_past_comma (&str
) == FAIL
4837 || cp_opc_expr (&str
, 20,4) == FAIL
)
4840 inst
.error
= BAD_ARGS
;
4844 if (skip_past_comma (&str
) == FAIL
4845 || cp_reg_required_here (&str
, 12) == FAIL
)
4848 inst
.error
= BAD_ARGS
;
4852 if (skip_past_comma (&str
) == FAIL
4853 || cp_reg_required_here (&str
, 16) == FAIL
)
4856 inst
.error
= BAD_ARGS
;
4860 if (skip_past_comma (&str
) == FAIL
4861 || cp_reg_required_here (&str
, 0) == FAIL
)
4864 inst
.error
= BAD_ARGS
;
4868 if (skip_past_comma (&str
) == SUCCESS
)
4870 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
4873 inst
.error
= BAD_ARGS
;
4883 do_lstc (str
, flags
)
4885 unsigned long flags
;
4887 /* Co-processor register load/store.
4888 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
4890 skip_whitespace (str
);
4892 if (co_proc_number (&str
) == FAIL
)
4895 inst
.error
= BAD_ARGS
;
4899 if (skip_past_comma (&str
) == FAIL
4900 || cp_reg_required_here (&str
, 12) == FAIL
)
4903 inst
.error
= BAD_ARGS
;
4907 if (skip_past_comma (&str
) == FAIL
4908 || cp_address_required_here (&str
) == FAIL
)
4911 inst
.error
= BAD_ARGS
;
4915 inst
.instruction
|= flags
;
4921 do_co_reg (str
, flags
)
4923 unsigned long flags
;
4925 /* Co-processor register transfer.
4926 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
4928 skip_whitespace (str
);
4930 if (co_proc_number (&str
) == FAIL
)
4933 inst
.error
= BAD_ARGS
;
4937 if (skip_past_comma (&str
) == FAIL
4938 || cp_opc_expr (&str
, 21, 3) == FAIL
)
4941 inst
.error
= BAD_ARGS
;
4945 if (skip_past_comma (&str
) == FAIL
4946 || reg_required_here (&str
, 12) == FAIL
)
4949 inst
.error
= BAD_ARGS
;
4953 if (skip_past_comma (&str
) == FAIL
4954 || cp_reg_required_here (&str
, 16) == FAIL
)
4957 inst
.error
= BAD_ARGS
;
4961 if (skip_past_comma (&str
) == FAIL
4962 || cp_reg_required_here (&str
, 0) == FAIL
)
4965 inst
.error
= BAD_ARGS
;
4969 if (skip_past_comma (&str
) == SUCCESS
)
4971 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
4974 inst
.error
= BAD_ARGS
;
4980 inst
.error
= BAD_COND
;
4988 do_fp_ctrl (str
, flags
)
4990 unsigned long flags ATTRIBUTE_UNUSED
;
4992 /* FP control registers.
4993 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
4995 skip_whitespace (str
);
4997 if (reg_required_here (&str
, 12) == FAIL
)
5000 inst
.error
= BAD_ARGS
;
5009 do_fp_ldst (str
, flags
)
5011 unsigned long flags ATTRIBUTE_UNUSED
;
5013 skip_whitespace (str
);
5015 switch (inst
.suffix
)
5020 inst
.instruction
|= CP_T_X
;
5023 inst
.instruction
|= CP_T_Y
;
5026 inst
.instruction
|= CP_T_X
| CP_T_Y
;
5032 if (fp_reg_required_here (&str
, 12) == FAIL
)
5035 inst
.error
= BAD_ARGS
;
5039 if (skip_past_comma (&str
) == FAIL
5040 || cp_address_required_here (&str
) == FAIL
)
5043 inst
.error
= BAD_ARGS
;
5051 do_fp_ldmstm (str
, flags
)
5053 unsigned long flags
;
5057 skip_whitespace (str
);
5059 if (fp_reg_required_here (&str
, 12) == FAIL
)
5062 inst
.error
= BAD_ARGS
;
5066 /* Get Number of registers to transfer. */
5067 if (skip_past_comma (&str
) == FAIL
5068 || my_get_expression (&inst
.reloc
.exp
, &str
))
5071 inst
.error
= _("constant expression expected");
5075 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5077 inst
.error
= _("Constant value required for number of registers");
5081 num_regs
= inst
.reloc
.exp
.X_add_number
;
5083 if (num_regs
< 1 || num_regs
> 4)
5085 inst
.error
= _("number of registers must be in the range [1:4]");
5092 inst
.instruction
|= CP_T_X
;
5095 inst
.instruction
|= CP_T_Y
;
5098 inst
.instruction
|= CP_T_Y
| CP_T_X
;
5112 /* The instruction specified "ea" or "fd", so we can only accept
5113 [Rn]{!}. The instruction does not really support stacking or
5114 unstacking, so we have to emulate these by setting appropriate
5115 bits and offsets. */
5116 if (skip_past_comma (&str
) == FAIL
5120 inst
.error
= BAD_ARGS
;
5125 skip_whitespace (str
);
5127 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
5130 skip_whitespace (str
);
5134 inst
.error
= BAD_ARGS
;
5146 _("R15 not allowed as base register with write-back");
5153 if (flags
& CP_T_Pre
)
5155 /* Pre-decrement. */
5156 offset
= 3 * num_regs
;
5162 /* Post-increment. */
5166 offset
= 3 * num_regs
;
5170 /* No write-back, so convert this into a standard pre-increment
5171 instruction -- aesthetically more pleasing. */
5172 flags
= CP_T_Pre
| CP_T_UD
;
5177 inst
.instruction
|= flags
| offset
;
5179 else if (skip_past_comma (&str
) == FAIL
5180 || cp_address_required_here (&str
) == FAIL
)
5183 inst
.error
= BAD_ARGS
;
5191 do_fp_dyadic (str
, flags
)
5193 unsigned long flags
;
5195 skip_whitespace (str
);
5197 switch (inst
.suffix
)
5202 inst
.instruction
|= 0x00000080;
5205 inst
.instruction
|= 0x00080000;
5211 if (fp_reg_required_here (&str
, 12) == FAIL
)
5214 inst
.error
= BAD_ARGS
;
5218 if (skip_past_comma (&str
) == FAIL
5219 || fp_reg_required_here (&str
, 16) == FAIL
)
5222 inst
.error
= BAD_ARGS
;
5226 if (skip_past_comma (&str
) == FAIL
5227 || fp_op2 (&str
) == FAIL
)
5230 inst
.error
= BAD_ARGS
;
5234 inst
.instruction
|= flags
;
5240 do_fp_monadic (str
, flags
)
5242 unsigned long flags
;
5244 skip_whitespace (str
);
5246 switch (inst
.suffix
)
5251 inst
.instruction
|= 0x00000080;
5254 inst
.instruction
|= 0x00080000;
5260 if (fp_reg_required_here (&str
, 12) == FAIL
)
5263 inst
.error
= BAD_ARGS
;
5267 if (skip_past_comma (&str
) == FAIL
5268 || fp_op2 (&str
) == FAIL
)
5271 inst
.error
= BAD_ARGS
;
5275 inst
.instruction
|= flags
;
5281 do_fp_cmp (str
, flags
)
5283 unsigned long flags
;
5285 skip_whitespace (str
);
5287 if (fp_reg_required_here (&str
, 16) == FAIL
)
5290 inst
.error
= BAD_ARGS
;
5294 if (skip_past_comma (&str
) == FAIL
5295 || fp_op2 (&str
) == FAIL
)
5298 inst
.error
= BAD_ARGS
;
5302 inst
.instruction
|= flags
;
5308 do_fp_from_reg (str
, flags
)
5310 unsigned long flags
;
5312 skip_whitespace (str
);
5314 switch (inst
.suffix
)
5319 inst
.instruction
|= 0x00000080;
5322 inst
.instruction
|= 0x00080000;
5328 if (fp_reg_required_here (&str
, 16) == FAIL
)
5331 inst
.error
= BAD_ARGS
;
5335 if (skip_past_comma (&str
) == FAIL
5336 || reg_required_here (&str
, 12) == FAIL
)
5339 inst
.error
= BAD_ARGS
;
5343 inst
.instruction
|= flags
;
5349 do_fp_to_reg (str
, flags
)
5351 unsigned long flags
;
5353 skip_whitespace (str
);
5355 if (reg_required_here (&str
, 12) == FAIL
)
5358 if (skip_past_comma (&str
) == FAIL
5359 || fp_reg_required_here (&str
, 0) == FAIL
)
5362 inst
.error
= BAD_ARGS
;
5366 inst
.instruction
|= flags
;
5371 /* Thumb specific routines. */
5373 /* Parse and validate that a register is of the right form, this saves
5374 repeated checking of this information in many similar cases.
5375 Unlike the 32-bit case we do not insert the register into the opcode
5376 here, since the position is often unknown until the full instruction
5380 thumb_reg (strp
, hi_lo
)
5386 if ((reg
= reg_required_here (strp
, -1)) == FAIL
)
5394 inst
.error
= _("lo register required");
5402 inst
.error
= _("hi register required");
5414 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
5418 thumb_add_sub (str
, subtract
)
5422 int Rd
, Rs
, Rn
= FAIL
;
5424 skip_whitespace (str
);
5426 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
5427 || skip_past_comma (&str
) == FAIL
)
5430 inst
.error
= BAD_ARGS
;
5434 if (is_immediate_prefix (*str
))
5438 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5443 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5446 if (skip_past_comma (&str
) == FAIL
)
5448 /* Two operand format, shuffle the registers
5449 and pretend there are 3. */
5453 else if (is_immediate_prefix (*str
))
5456 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5459 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5463 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5464 for the latter case, EXPR contains the immediate that was found. */
5467 /* All register format. */
5468 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
5472 inst
.error
= _("dest and source1 must be the same register");
5476 /* Can't do this for SUB. */
5479 inst
.error
= _("subtract valid only on lo regs");
5483 inst
.instruction
= (T_OPCODE_ADD_HI
5484 | (Rd
> 7 ? THUMB_H1
: 0)
5485 | (Rn
> 7 ? THUMB_H2
: 0));
5486 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
5490 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
5491 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5496 /* Immediate expression, now things start to get nasty. */
5498 /* First deal with HI regs, only very restricted cases allowed:
5499 Adjusting SP, and using PC or SP to get an address. */
5500 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
5501 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
5503 inst
.error
= _("invalid Hi register with immediate");
5507 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5509 /* Value isn't known yet, all we can do is store all the fragments
5510 we know about in the instruction and let the reloc hacking
5512 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
5513 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5517 int offset
= inst
.reloc
.exp
.X_add_number
;
5527 /* Quick check, in case offset is MIN_INT. */
5530 inst
.error
= _("immediate value out of range");
5539 if (offset
& ~0x1fc)
5541 inst
.error
= _("invalid immediate value for stack adjust");
5544 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
5545 inst
.instruction
|= offset
>> 2;
5547 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
5550 || (offset
& ~0x3fc))
5552 inst
.error
= _("invalid immediate for address calculation");
5555 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
5557 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
5563 inst
.error
= _("immediate value out of range");
5566 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
5567 inst
.instruction
|= (Rd
<< 8) | offset
;
5573 inst
.error
= _("immediate value out of range");
5576 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
5577 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
5586 thumb_shift (str
, shift
)
5590 int Rd
, Rs
, Rn
= FAIL
;
5592 skip_whitespace (str
);
5594 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5595 || skip_past_comma (&str
) == FAIL
)
5598 inst
.error
= BAD_ARGS
;
5602 if (is_immediate_prefix (*str
))
5604 /* Two operand immediate format, set Rs to Rd. */
5607 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5612 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5615 if (skip_past_comma (&str
) == FAIL
)
5617 /* Two operand format, shuffle the registers
5618 and pretend there are 3. */
5622 else if (is_immediate_prefix (*str
))
5625 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5628 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5632 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5633 for the latter case, EXPR contains the immediate that was found. */
5639 inst
.error
= _("source1 and dest must be same register");
5645 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
5646 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
5647 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
5650 inst
.instruction
|= Rd
| (Rn
<< 3);
5656 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
5657 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
5658 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
5661 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5663 /* Value isn't known yet, create a dummy reloc and let reloc
5664 hacking fix it up. */
5665 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
5669 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
5671 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
5673 inst
.error
= _("Invalid immediate for shift");
5677 /* Shifts of zero are handled by converting to LSL. */
5678 if (shift_value
== 0)
5679 inst
.instruction
= T_OPCODE_LSL_I
;
5681 /* Shifts of 32 are encoded as a shift of zero. */
5682 if (shift_value
== 32)
5685 inst
.instruction
|= shift_value
<< 6;
5688 inst
.instruction
|= Rd
| (Rs
<< 3);
5695 thumb_mov_compare (str
, move
)
5701 skip_whitespace (str
);
5703 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
5704 || skip_past_comma (&str
) == FAIL
)
5707 inst
.error
= BAD_ARGS
;
5711 if (is_immediate_prefix (*str
))
5714 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5717 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5722 if (Rs
< 8 && Rd
< 8)
5724 if (move
== THUMB_MOVE
)
5725 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
5726 since a MOV instruction produces unpredictable results. */
5727 inst
.instruction
= T_OPCODE_ADD_I3
;
5729 inst
.instruction
= T_OPCODE_CMP_LR
;
5730 inst
.instruction
|= Rd
| (Rs
<< 3);
5734 if (move
== THUMB_MOVE
)
5735 inst
.instruction
= T_OPCODE_MOV_HR
;
5737 inst
.instruction
= T_OPCODE_CMP_HR
;
5740 inst
.instruction
|= THUMB_H1
;
5743 inst
.instruction
|= THUMB_H2
;
5745 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
5752 inst
.error
= _("only lo regs allowed with immediate");
5756 if (move
== THUMB_MOVE
)
5757 inst
.instruction
= T_OPCODE_MOV_I8
;
5759 inst
.instruction
= T_OPCODE_CMP_I8
;
5761 inst
.instruction
|= Rd
<< 8;
5763 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5764 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
5767 unsigned value
= inst
.reloc
.exp
.X_add_number
;
5771 inst
.error
= _("invalid immediate");
5775 inst
.instruction
|= value
;
5783 thumb_load_store (str
, load_store
, size
)
5788 int Rd
, Rb
, Ro
= FAIL
;
5790 skip_whitespace (str
);
5792 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5793 || skip_past_comma (&str
) == FAIL
)
5796 inst
.error
= BAD_ARGS
;
5803 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
5806 if (skip_past_comma (&str
) != FAIL
)
5808 if (is_immediate_prefix (*str
))
5811 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5814 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
5819 inst
.reloc
.exp
.X_op
= O_constant
;
5820 inst
.reloc
.exp
.X_add_number
= 0;
5825 inst
.error
= _("expected ']'");
5830 else if (*str
== '=')
5832 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
5835 skip_whitespace (str
);
5837 if (my_get_expression (& inst
.reloc
.exp
, & str
))
5842 if ( inst
.reloc
.exp
.X_op
!= O_constant
5843 && inst
.reloc
.exp
.X_op
!= O_symbol
)
5845 inst
.error
= "Constant expression expected";
5849 if (inst
.reloc
.exp
.X_op
== O_constant
5850 && ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0))
5852 /* This can be done with a mov instruction. */
5854 inst
.instruction
= T_OPCODE_MOV_I8
| (Rd
<< 8);
5855 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
5859 /* Insert into literal pool. */
5860 if (add_to_lit_pool () == FAIL
)
5863 inst
.error
= "literal pool insertion failed";
5867 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5868 inst
.reloc
.pc_rel
= 1;
5869 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
5870 /* Adjust ARM pipeline offset to Thumb. */
5871 inst
.reloc
.exp
.X_add_number
+= 4;
5877 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5880 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
5881 inst
.reloc
.pc_rel
= 1;
5882 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset. */
5883 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5888 if (Rb
== REG_PC
|| Rb
== REG_SP
)
5890 if (size
!= THUMB_WORD
)
5892 inst
.error
= _("byte or halfword not valid for base register");
5895 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
5897 inst
.error
= _("R15 based store not allowed");
5900 else if (Ro
!= FAIL
)
5902 inst
.error
= _("Invalid base register for register offset");
5907 inst
.instruction
= T_OPCODE_LDR_PC
;
5908 else if (load_store
== THUMB_LOAD
)
5909 inst
.instruction
= T_OPCODE_LDR_SP
;
5911 inst
.instruction
= T_OPCODE_STR_SP
;
5913 inst
.instruction
|= Rd
<< 8;
5914 if (inst
.reloc
.exp
.X_op
== O_constant
)
5916 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
5918 if (offset
& ~0x3fc)
5920 inst
.error
= _("invalid offset");
5924 inst
.instruction
|= offset
>> 2;
5927 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5931 inst
.error
= _("invalid base register in load/store");
5934 else if (Ro
== FAIL
)
5936 /* Immediate offset. */
5937 if (size
== THUMB_WORD
)
5938 inst
.instruction
= (load_store
== THUMB_LOAD
5939 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
5940 else if (size
== THUMB_HALFWORD
)
5941 inst
.instruction
= (load_store
== THUMB_LOAD
5942 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
5944 inst
.instruction
= (load_store
== THUMB_LOAD
5945 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
5947 inst
.instruction
|= Rd
| (Rb
<< 3);
5949 if (inst
.reloc
.exp
.X_op
== O_constant
)
5951 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
5953 if (offset
& ~(0x1f << size
))
5955 inst
.error
= _("Invalid offset");
5958 inst
.instruction
|= (offset
>> size
) << 6;
5961 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
5965 /* Register offset. */
5966 if (size
== THUMB_WORD
)
5967 inst
.instruction
= (load_store
== THUMB_LOAD
5968 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
5969 else if (size
== THUMB_HALFWORD
)
5970 inst
.instruction
= (load_store
== THUMB_LOAD
5971 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
5973 inst
.instruction
= (load_store
== THUMB_LOAD
5974 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
5976 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
5991 /* Handle the Format 4 instructions that do not have equivalents in other
5992 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
6001 skip_whitespace (str
);
6003 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6004 || skip_past_comma (&str
) == FAIL
6005 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6007 inst
.error
= BAD_ARGS
;
6011 if (skip_past_comma (&str
) != FAIL
)
6013 /* Three operand format not allowed for TST, CMN, NEG and MVN.
6014 (It isn't allowed for CMP either, but that isn't handled by this
6016 if (inst
.instruction
== T_OPCODE_TST
6017 || inst
.instruction
== T_OPCODE_CMN
6018 || inst
.instruction
== T_OPCODE_NEG
6019 || inst
.instruction
== T_OPCODE_MVN
)
6021 inst
.error
= BAD_ARGS
;
6025 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6030 inst
.error
= _("dest and source1 must be the same register");
6036 if (inst
.instruction
== T_OPCODE_MUL
6038 as_tsktsk (_("Rs and Rd must be different in MUL"));
6040 inst
.instruction
|= Rd
| (Rs
<< 3);
6048 thumb_add_sub (str
, 0);
6055 thumb_shift (str
, THUMB_ASR
);
6062 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6064 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6065 inst
.reloc
.pc_rel
= 1;
6073 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6075 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6076 inst
.reloc
.pc_rel
= 1;
6080 /* Find the real, Thumb encoded start of a Thumb function. */
6083 find_real_start (symbolP
)
6087 const char * name
= S_GET_NAME (symbolP
);
6088 symbolS
* new_target
;
6090 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
6091 #define STUB_NAME ".real_start_of"
6096 /* Names that start with '.' are local labels, not function entry points.
6097 The compiler may generate BL instructions to these labels because it
6098 needs to perform a branch to a far away location. */
6102 real_start
= malloc (strlen (name
) + strlen (STUB_NAME
) + 1);
6103 sprintf (real_start
, "%s%s", STUB_NAME
, name
);
6105 new_target
= symbol_find (real_start
);
6107 if (new_target
== NULL
)
6109 as_warn ("Failed to find real start of function: %s\n", name
);
6110 new_target
= symbolP
;
6122 if (my_get_expression (& inst
.reloc
.exp
, & str
))
6125 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6126 inst
.reloc
.pc_rel
= 1;
6129 /* If the destination of the branch is a defined symbol which does not have
6130 the THUMB_FUNC attribute, then we must be calling a function which has
6131 the (interfacearm) attribute. We look for the Thumb entry point to that
6132 function and change the branch to refer to that function instead. */
6133 if ( inst
.reloc
.exp
.X_op
== O_symbol
6134 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6135 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6136 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6137 inst
.reloc
.exp
.X_add_symbol
=
6138 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6147 skip_whitespace (str
);
6149 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
6152 /* This sets THUMB_H2 from the top bit of reg. */
6153 inst
.instruction
|= reg
<< 3;
6155 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6156 should cause the alignment to be checked once it is known. This is
6157 because BX PC only works if the instruction is word aligned. */
6166 thumb_mov_compare (str
, THUMB_COMPARE
);
6176 skip_whitespace (str
);
6178 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
6182 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
6186 if (skip_past_comma (&str
) == FAIL
6187 || (range
= reg_list (&str
)) == FAIL
)
6190 inst
.error
= BAD_ARGS
;
6194 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6196 /* This really doesn't seem worth it. */
6197 inst
.reloc
.type
= BFD_RELOC_NONE
;
6198 inst
.error
= _("Expression too complex");
6204 inst
.error
= _("only lo-regs valid in load/store multiple");
6208 inst
.instruction
|= (Rb
<< 8) | range
;
6216 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
6223 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
6230 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
6239 skip_whitespace (str
);
6241 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6242 || skip_past_comma (&str
) == FAIL
6244 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6245 || skip_past_comma (&str
) == FAIL
6246 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
6250 inst
.error
= _("Syntax: ldrs[b] Rd, [Rb, Ro]");
6254 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
6262 thumb_shift (str
, THUMB_LSL
);
6269 thumb_shift (str
, THUMB_LSR
);
6276 thumb_mov_compare (str
, THUMB_MOVE
);
6285 skip_whitespace (str
);
6287 if ((range
= reg_list (&str
)) == FAIL
)
6290 inst
.error
= BAD_ARGS
;
6294 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6296 /* This really doesn't seem worth it. */
6297 inst
.reloc
.type
= BFD_RELOC_NONE
;
6298 inst
.error
= _("Expression too complex");
6304 if ((inst
.instruction
== T_OPCODE_PUSH
6305 && (range
& ~0xff) == 1 << REG_LR
)
6306 || (inst
.instruction
== T_OPCODE_POP
6307 && (range
& ~0xff) == 1 << REG_PC
))
6309 inst
.instruction
|= THUMB_PP_PC_LR
;
6314 inst
.error
= _("invalid register list to push/pop instruction");
6319 inst
.instruction
|= range
;
6327 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
6334 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
6341 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
6348 thumb_add_sub (str
, 1);
6355 skip_whitespace (str
);
6357 if (my_get_expression (&inst
.reloc
.exp
, &str
))
6360 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
6371 /* This is a pseudo-op of the form "adr rd, label" to be converted
6372 into a relative address of the form "add rd, pc, #label-.-4". */
6373 skip_whitespace (str
);
6375 /* Store Rd in temporary location inside instruction. */
6376 if ((reg
= reg_required_here (&str
, 4)) == FAIL
6377 || (reg
> 7) /* For Thumb reg must be r0..r7. */
6378 || skip_past_comma (&str
) == FAIL
6379 || my_get_expression (&inst
.reloc
.exp
, &str
))
6382 inst
.error
= BAD_ARGS
;
6386 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6387 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
6388 inst
.reloc
.pc_rel
= 1;
6389 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction. */
6398 int len
= strlen (reg_table
[entry
].name
) + 2;
6399 char * buf
= (char *) xmalloc (len
);
6400 char * buf2
= (char *) xmalloc (len
);
6403 #ifdef REGISTER_PREFIX
6404 buf
[i
++] = REGISTER_PREFIX
;
6407 strcpy (buf
+ i
, reg_table
[entry
].name
);
6409 for (i
= 0; buf
[i
]; i
++)
6410 buf2
[i
] = TOUPPER (buf
[i
]);
6414 hash_insert (arm_reg_hsh
, buf
, (PTR
) & reg_table
[entry
]);
6415 hash_insert (arm_reg_hsh
, buf2
, (PTR
) & reg_table
[entry
]);
6419 insert_reg_alias (str
, regnum
)
6423 struct reg_entry
*new =
6424 (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
6425 char *name
= xmalloc (strlen (str
) + 1);
6429 new->number
= regnum
;
6431 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
6435 set_constant_flonums ()
6439 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
6440 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
6450 if ( (arm_ops_hsh
= hash_new ()) == NULL
6451 || (arm_tops_hsh
= hash_new ()) == NULL
6452 || (arm_cond_hsh
= hash_new ()) == NULL
6453 || (arm_shift_hsh
= hash_new ()) == NULL
6454 || (arm_reg_hsh
= hash_new ()) == NULL
6455 || (arm_psr_hsh
= hash_new ()) == NULL
)
6456 as_fatal (_("Virtual memory exhausted"));
6458 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
6459 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
6460 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
6461 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
6462 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
6463 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
6464 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
6465 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
6466 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
6467 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
6469 for (i
= 0; reg_table
[i
].name
; i
++)
6472 set_constant_flonums ();
6474 #if defined OBJ_COFF || defined OBJ_ELF
6476 unsigned int flags
= 0;
6478 /* Set the flags in the private structure. */
6479 if (uses_apcs_26
) flags
|= F_APCS26
;
6480 if (support_interwork
) flags
|= F_INTERWORK
;
6481 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
6482 if (pic_code
) flags
|= F_PIC
;
6483 if ((cpu_variant
& FPU_ALL
) == FPU_NONE
) flags
|= F_SOFT_FLOAT
;
6485 bfd_set_private_flags (stdoutput
, flags
);
6487 /* We have run out flags in the COFF header to encode the
6488 status of ATPCS support, so instead we create a dummy,
6489 empty, debug section called .arm.atpcs. */
6494 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
6498 bfd_set_section_flags
6499 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
6500 bfd_set_section_size (stdoutput
, sec
, 0);
6501 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
6507 /* Record the CPU type as well. */
6508 switch (cpu_variant
& ARM_CPU_MASK
)
6511 mach
= bfd_mach_arm_2
;
6514 case ARM_3
: /* Also ARM_250. */
6515 mach
= bfd_mach_arm_2a
;
6519 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined. */
6520 mach
= bfd_mach_arm_4
;
6523 case ARM_7
: /* Also ARM_6. */
6524 mach
= bfd_mach_arm_3
;
6528 /* Catch special cases. */
6529 if (cpu_variant
& ARM_EXT_XSCALE
)
6530 mach
= bfd_mach_arm_XScale
;
6531 else if (cpu_variant
& ARM_EXT_V5E
)
6532 mach
= bfd_mach_arm_5TE
;
6533 else if (cpu_variant
& ARM_EXT_V5
)
6535 if (cpu_variant
& ARM_EXT_THUMB
)
6536 mach
= bfd_mach_arm_5T
;
6538 mach
= bfd_mach_arm_5
;
6540 else if (cpu_variant
& ARM_EXT_HALFWORD
)
6542 if (cpu_variant
& ARM_EXT_THUMB
)
6543 mach
= bfd_mach_arm_4T
;
6545 mach
= bfd_mach_arm_4
;
6547 else if (cpu_variant
& ARM_EXT_LONGMUL
)
6548 mach
= bfd_mach_arm_3M
;
6550 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
6553 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6554 for use in the a.out file, and stores them in the array pointed to by buf.
6555 This knows about the endian-ness of the target machine and does
6556 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6557 2 (short) and 4 (long) Floating numbers are put out as a series of
6558 LITTLENUMS (shorts, here at least). */
6561 md_number_to_chars (buf
, val
, n
)
6566 if (target_big_endian
)
6567 number_to_chars_bigendian (buf
, val
, n
);
6569 number_to_chars_littleendian (buf
, val
, n
);
6573 md_chars_to_number (buf
, n
)
6578 unsigned char * where
= (unsigned char *) buf
;
6580 if (target_big_endian
)
6585 result
|= (*where
++ & 255);
6593 result
|= (where
[n
] & 255);
6600 /* Turn a string in input_line_pointer into a floating point constant
6601 of type TYPE, and store the appropriate bytes in *LITP. The number
6602 of LITTLENUMS emitted is stored in *SIZEP. An error message is
6603 returned, or NULL on OK.
6605 Note that fp constants aren't represent in the normal way on the ARM.
6606 In big endian mode, things are as expected. However, in little endian
6607 mode fp constants are big-endian word-wise, and little-endian byte-wise
6608 within the words. For example, (double) 1.1 in big endian mode is
6609 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
6610 the byte sequence 99 99 f1 3f 9a 99 99 99.
6612 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
6615 md_atof (type
, litP
, sizeP
)
6621 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
6653 return _("Bad call to MD_ATOF()");
6656 t
= atof_ieee (input_line_pointer
, type
, words
);
6658 input_line_pointer
= t
;
6661 if (target_big_endian
)
6663 for (i
= 0; i
< prec
; i
++)
6665 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6671 /* For a 4 byte float the order of elements in `words' is 1 0. For an
6672 8 byte float the order is 1 0 3 2. */
6673 for (i
= 0; i
< prec
; i
+= 2)
6675 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
6676 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
6684 /* The knowledge of the PC's pipeline offset is built into the insns
6688 md_pcrel_from (fixP
)
6692 && S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
6693 && fixP
->fx_subsy
== NULL
)
6696 if (fixP
->fx_pcrel
&& (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_ADD
))
6698 /* PC relative addressing on the Thumb is slightly odd
6699 as the bottom two bits of the PC are forced to zero
6700 for the calculation. */
6701 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
) & ~3;
6705 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
6706 so we un-adjust here to compensate for the accomodation. */
6707 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
+ 8;
6709 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6713 /* Round up a section size to the appropriate boundary. */
6716 md_section_align (segment
, size
)
6717 segT segment ATTRIBUTE_UNUSED
;
6723 /* Round all sects to multiple of 4. */
6724 return (size
+ 3) & ~3;
6728 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6729 Otherwise we have no need to default values of symbols. */
6732 md_undefined_symbol (name
)
6733 char * name ATTRIBUTE_UNUSED
;
6736 if (name
[0] == '_' && name
[1] == 'G'
6737 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6741 if (symbol_find (name
))
6742 as_bad ("GOT already in the symbol table");
6744 GOT_symbol
= symbol_new (name
, undefined_section
,
6745 (valueT
) 0, & zero_address_frag
);
6755 /* arm_reg_parse () := if it looks like a register, return its token and
6756 advance the pointer. */
6760 register char ** ccp
;
6762 char * start
= * ccp
;
6765 struct reg_entry
* reg
;
6767 #ifdef REGISTER_PREFIX
6768 if (*start
!= REGISTER_PREFIX
)
6773 #ifdef OPTIONAL_REGISTER_PREFIX
6774 if (*p
== OPTIONAL_REGISTER_PREFIX
)
6778 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
6782 while (ISALPHA (c
) || ISDIGIT (c
) || c
== '_')
6786 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
6799 md_apply_fix3 (fixP
, val
, seg
)
6804 offsetT value
= * val
;
6806 unsigned int newimm
;
6809 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6810 arm_fix_data
* arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
6812 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
6814 /* Note whether this will delete the relocation. */
6816 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
6817 doesn't work fully.) */
6818 if ((fixP
->fx_addsy
== 0 || symbol_constant_p (fixP
->fx_addsy
))
6821 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6825 /* If this symbol is in a different section then we need to leave it for
6826 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
6827 so we have to undo it's effects here. */
6830 if (fixP
->fx_addsy
!= NULL
6831 && S_IS_DEFINED (fixP
->fx_addsy
)
6832 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6835 && (fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
6836 || fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
6840 value
+= md_pcrel_from (fixP
);
6844 /* Remember value for emit_reloc. */
6845 fixP
->fx_addnumber
= value
;
6847 switch (fixP
->fx_r_type
)
6849 case BFD_RELOC_ARM_IMMEDIATE
:
6850 newimm
= validate_immediate (value
);
6851 temp
= md_chars_to_number (buf
, INSN_SIZE
);
6853 /* If the instruction will fail, see if we can fix things up by
6854 changing the opcode. */
6855 if (newimm
== (unsigned int) FAIL
6856 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
6858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6859 _("invalid constant (%lx) after fixup"),
6860 (unsigned long) value
);
6864 newimm
|= (temp
& 0xfffff000);
6865 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
6868 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
6870 unsigned int highpart
= 0;
6871 unsigned int newinsn
= 0xe1a00000; /* nop. */
6872 newimm
= validate_immediate (value
);
6873 temp
= md_chars_to_number (buf
, INSN_SIZE
);
6875 /* If the instruction will fail, see if we can fix things up by
6876 changing the opcode. */
6877 if (newimm
== (unsigned int) FAIL
6878 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
6880 /* No ? OK - try using two ADD instructions to generate
6882 newimm
= validate_immediate_twopart (value
, & highpart
);
6884 /* Yes - then make sure that the second instruction is
6886 if (newimm
!= (unsigned int) FAIL
)
6888 /* Still No ? Try using a negated value. */
6889 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
6890 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
6891 /* Otherwise - give up. */
6894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6895 _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
6900 /* Replace the first operand in the 2nd instruction (which
6901 is the PC) with the destination register. We have
6902 already added in the PC in the first instruction and we
6903 do not want to do it again. */
6904 newinsn
&= ~ 0xf0000;
6905 newinsn
|= ((newinsn
& 0x0f000) << 4);
6908 newimm
|= (temp
& 0xfffff000);
6909 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
6911 highpart
|= (newinsn
& 0xfffff000);
6912 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
6916 case BFD_RELOC_ARM_OFFSET_IMM
:
6922 if (validate_offset_imm (value
, 0) == FAIL
)
6924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6925 _("bad immediate value for offset (%ld)"),
6930 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6931 newval
&= 0xff7ff000;
6932 newval
|= value
| (sign
? INDEX_UP
: 0);
6933 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6936 case BFD_RELOC_ARM_OFFSET_IMM8
:
6937 case BFD_RELOC_ARM_HWLITERAL
:
6943 if (validate_offset_imm (value
, 1) == FAIL
)
6945 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
6946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6947 _("invalid literal constant: pool needs to be closer"));
6949 as_bad (_("bad immediate value for half-word offset (%ld)"),
6954 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6955 newval
&= 0xff7ff0f0;
6956 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
6957 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6960 case BFD_RELOC_ARM_LITERAL
:
6966 if (validate_offset_imm (value
, 0) == FAIL
)
6968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6969 _("invalid literal constant: pool needs to be closer"));
6973 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6974 newval
&= 0xff7ff000;
6975 newval
|= value
| (sign
? INDEX_UP
: 0);
6976 md_number_to_chars (buf
, newval
, INSN_SIZE
);
6979 case BFD_RELOC_ARM_SHIFT_IMM
:
6980 newval
= md_chars_to_number (buf
, INSN_SIZE
);
6981 if (((unsigned long) value
) > 32
6983 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
6985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6986 _("shift expression is too large"));
6991 /* Shifts of zero must be done as lsl. */
6993 else if (value
== 32)
6995 newval
&= 0xfffff07f;
6996 newval
|= (value
& 0x1f) << 7;
6997 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7000 case BFD_RELOC_ARM_SWI
:
7001 if (arm_data
->thumb_mode
)
7003 if (((unsigned long) value
) > 0xff)
7004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7005 _("Invalid swi expression"));
7006 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
7008 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7012 if (((unsigned long) value
) > 0x00ffffff)
7013 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7014 _("Invalid swi expression"));
7015 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
7017 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7021 case BFD_RELOC_ARM_MULTI
:
7022 if (((unsigned long) value
) > 0xffff)
7023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7024 _("Invalid expression in load/store multiple"));
7025 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
7026 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7029 case BFD_RELOC_ARM_PCREL_BRANCH
:
7030 newval
= md_chars_to_number (buf
, INSN_SIZE
);
7032 /* Sign-extend a 24-bit number. */
7033 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
7037 value
= fixP
->fx_offset
;
7040 /* We are going to store value (shifted right by two) in the
7041 instruction, in a 24 bit, signed field. Thus we need to check
7042 that none of the top 8 bits of the shifted value (top 7 bits of
7043 the unshifted, unsigned value) are set, or that they are all set. */
7044 if ((value
& ~ ((offsetT
) 0x1ffffff)) != 0
7045 && ((value
& ~ ((offsetT
) 0x1ffffff)) != ~ ((offsetT
) 0x1ffffff)))
7048 /* Normally we would be stuck at this point, since we cannot store
7049 the absolute address that is the destination of the branch in the
7050 24 bits of the branch instruction. If however, we happen to know
7051 that the destination of the branch is in the same section as the
7052 branch instruciton itself, then we can compute the relocation for
7053 ourselves and not have to bother the linker with it.
7055 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
7056 because I have not worked out how to do this for OBJ_COFF or
7059 && fixP
->fx_addsy
!= NULL
7060 && S_IS_DEFINED (fixP
->fx_addsy
)
7061 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
7063 /* Get pc relative value to go into the branch. */
7066 /* Permit a backward branch provided that enough bits
7067 are set. Allow a forwards branch, provided that
7068 enough bits are clear. */
7069 if ( (value
& ~ ((offsetT
) 0x1ffffff)) == ~ ((offsetT
) 0x1ffffff)
7070 || (value
& ~ ((offsetT
) 0x1ffffff)) == 0)
7074 if (! fixP
->fx_done
)
7076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7077 _("gas can't handle same-section branch dest >= 0x04000000"));
7081 value
+= SEXT24 (newval
);
7083 if ( (value
& ~ ((offsetT
) 0xffffff)) != 0
7084 && ((value
& ~ ((offsetT
) 0xffffff)) != ~ ((offsetT
) 0xffffff)))
7085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7086 _("out of range branch"));
7088 newval
= (value
& 0x00ffffff) | (newval
& 0xff000000);
7089 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7092 case BFD_RELOC_ARM_PCREL_BLX
:
7095 newval
= md_chars_to_number (buf
, INSN_SIZE
);
7099 value
= fixP
->fx_offset
;
7101 hbit
= (value
>> 1) & 1;
7102 value
= (value
>> 2) & 0x00ffffff;
7103 value
= (value
+ (newval
& 0x00ffffff)) & 0x00ffffff;
7104 newval
= value
| (newval
& 0xfe000000) | (hbit
<< 24);
7105 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7109 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
7110 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7112 addressT diff
= (newval
& 0xff) << 1;
7117 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
7118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7119 _("Branch out of range"));
7120 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
7122 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7125 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
7126 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7128 addressT diff
= (newval
& 0x7ff) << 1;
7133 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
7134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7135 _("Branch out of range"));
7136 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
7138 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7141 case BFD_RELOC_THUMB_PCREL_BLX
:
7142 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
7147 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7148 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
7149 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
7150 if (diff
& 0x400000)
7153 value
= fixP
->fx_offset
;
7156 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
7157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7158 _("Branch with link out of range"));
7160 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
7161 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
7162 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
7163 /* Remove bit zero of the adjusted offset. Bit zero can only be
7164 set if the upper insn is at a half-word boundary, since the
7165 destination address, an ARM instruction, must always be on a
7166 word boundary. The semantics of the BLX (1) instruction, however,
7167 are that bit zero in the offset must always be zero, and the
7168 corresponding bit one in the target address will be set from bit
7169 one of the source address. */
7171 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7172 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
7177 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7178 md_number_to_chars (buf
, value
, 1);
7180 else if (!target_oabi
)
7182 value
= fixP
->fx_offset
;
7183 md_number_to_chars (buf
, value
, 1);
7189 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7190 md_number_to_chars (buf
, value
, 2);
7192 else if (!target_oabi
)
7194 value
= fixP
->fx_offset
;
7195 md_number_to_chars (buf
, value
, 2);
7201 case BFD_RELOC_ARM_GOT32
:
7202 case BFD_RELOC_ARM_GOTOFF
:
7203 md_number_to_chars (buf
, 0, 4);
7209 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
7210 md_number_to_chars (buf
, value
, 4);
7212 else if (!target_oabi
)
7214 value
= fixP
->fx_offset
;
7215 md_number_to_chars (buf
, value
, 4);
7221 case BFD_RELOC_ARM_PLT32
:
7222 /* It appears the instruction is fully prepared at this point. */
7226 case BFD_RELOC_ARM_GOTPC
:
7227 md_number_to_chars (buf
, value
, 4);
7230 case BFD_RELOC_ARM_CP_OFF_IMM
:
7232 if (value
< -1023 || value
> 1023 || (value
& 3))
7233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7234 _("Illegal value for co-processor offset"));
7237 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
7238 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
7239 md_number_to_chars (buf
, newval
, INSN_SIZE
);
7242 case BFD_RELOC_ARM_THUMB_OFFSET
:
7243 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7244 /* Exactly what ranges, and where the offset is inserted depends
7245 on the type of instruction, we can establish this from the
7247 switch (newval
>> 12)
7249 case 4: /* PC load. */
7250 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
7251 forced to zero for these loads, so we will need to round
7252 up the offset if the instruction address is not word
7253 aligned (since the final address produced must be, and
7254 we can only describe word-aligned immediate offsets). */
7256 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
7257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7258 _("Invalid offset, target not word aligned (0x%08X)"),
7259 (unsigned int) (fixP
->fx_frag
->fr_address
7260 + fixP
->fx_where
+ value
));
7262 if ((value
+ 2) & ~0x3fe)
7263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7264 _("Invalid offset, value too big (0x%08lX)"), value
);
7266 /* Round up, since pc will be rounded down. */
7267 newval
|= (value
+ 2) >> 2;
7270 case 9: /* SP load/store. */
7272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7273 _("Invalid offset, value too big (0x%08lX)"), value
);
7274 newval
|= value
>> 2;
7277 case 6: /* Word load/store. */
7279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7280 _("Invalid offset, value too big (0x%08lX)"), value
);
7281 newval
|= value
<< 4; /* 6 - 2. */
7284 case 7: /* Byte load/store. */
7286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7287 _("Invalid offset, value too big (0x%08lX)"), value
);
7288 newval
|= value
<< 6;
7291 case 8: /* Halfword load/store. */
7293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7294 _("Invalid offset, value too big (0x%08lX)"), value
);
7295 newval
|= value
<< 5; /* 6 - 1. */
7299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7300 "Unable to process relocation for thumb opcode: %lx",
7301 (unsigned long) newval
);
7304 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7307 case BFD_RELOC_ARM_THUMB_ADD
:
7308 /* This is a complicated relocation, since we use it for all of
7309 the following immediate relocations:
7313 9bit ADD/SUB SP word-aligned
7314 10bit ADD PC/SP word-aligned
7316 The type of instruction being processed is encoded in the
7323 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7325 int rd
= (newval
>> 4) & 0xf;
7326 int rs
= newval
& 0xf;
7327 int subtract
= newval
& 0x8000;
7332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7333 _("Invalid immediate for stack address calculation"));
7334 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
7335 newval
|= value
>> 2;
7337 else if (rs
== REG_PC
|| rs
== REG_SP
)
7341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7342 _("Invalid immediate for address calculation (value = 0x%08lX)"),
7343 (unsigned long) value
);
7344 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
7346 newval
|= value
>> 2;
7351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7352 _("Invalid 8bit immediate"));
7353 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
7354 newval
|= (rd
<< 8) | value
;
7359 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7360 _("Invalid 3bit immediate"));
7361 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
7362 newval
|= rd
| (rs
<< 3) | (value
<< 6);
7365 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7368 case BFD_RELOC_ARM_THUMB_IMM
:
7369 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
7370 switch (newval
>> 11)
7372 case 0x04: /* 8bit immediate MOV. */
7373 case 0x05: /* 8bit immediate CMP. */
7374 if (value
< 0 || value
> 255)
7375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7376 _("Invalid immediate: %ld is too large"),
7384 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7387 case BFD_RELOC_ARM_THUMB_SHIFT
:
7388 /* 5bit shift value (0..31). */
7389 if (value
< 0 || value
> 31)
7390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7391 _("Illegal Thumb shift value: %ld"), (long) value
);
7392 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
7393 newval
|= value
<< 6;
7394 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
7397 case BFD_RELOC_VTABLE_INHERIT
:
7398 case BFD_RELOC_VTABLE_ENTRY
:
7402 case BFD_RELOC_NONE
:
7404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7405 _("Bad relocation fixup type (%d)"), fixP
->fx_r_type
);
7411 /* Translate internal representation of relocation info to BFD target
7415 tc_gen_reloc (section
, fixp
)
7416 asection
* section ATTRIBUTE_UNUSED
;
7420 bfd_reloc_code_real_type code
;
7422 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
7424 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7425 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7426 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7428 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
7430 if (fixp
->fx_pcrel
== 0)
7431 reloc
->addend
= fixp
->fx_offset
;
7433 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
7435 reloc
->addend
= fixp
->fx_offset
;
7438 switch (fixp
->fx_r_type
)
7443 code
= BFD_RELOC_8_PCREL
;
7450 code
= BFD_RELOC_16_PCREL
;
7457 code
= BFD_RELOC_32_PCREL
;
7461 case BFD_RELOC_ARM_PCREL_BRANCH
:
7462 case BFD_RELOC_ARM_PCREL_BLX
:
7464 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
7465 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
7466 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
7467 case BFD_RELOC_THUMB_PCREL_BLX
:
7468 case BFD_RELOC_VTABLE_ENTRY
:
7469 case BFD_RELOC_VTABLE_INHERIT
:
7470 code
= fixp
->fx_r_type
;
7473 case BFD_RELOC_ARM_LITERAL
:
7474 case BFD_RELOC_ARM_HWLITERAL
:
7475 /* If this is called then the a literal has been referenced across
7476 a section boundary - possibly due to an implicit dump. */
7477 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7478 _("Literal referenced across section boundary (Implicit dump?)"));
7482 case BFD_RELOC_ARM_GOT32
:
7483 case BFD_RELOC_ARM_GOTOFF
:
7484 case BFD_RELOC_ARM_PLT32
:
7485 code
= fixp
->fx_r_type
;
7489 case BFD_RELOC_ARM_IMMEDIATE
:
7490 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7491 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
7495 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
7496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7497 _("ADRL used for a symbol not defined in the same file"));
7500 case BFD_RELOC_ARM_OFFSET_IMM
:
7501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7502 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
7510 switch (fixp
->fx_r_type
)
7512 case BFD_RELOC_ARM_IMMEDIATE
: type
= "IMMEDIATE"; break;
7513 case BFD_RELOC_ARM_OFFSET_IMM
: type
= "OFFSET_IMM"; break;
7514 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
7515 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
7516 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
7517 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
7518 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
7519 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
7520 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
7521 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
7522 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
7523 default: type
= _("<unknown>"); break;
7525 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7526 _("Cannot represent %s relocation in this object file format"),
7533 if (code
== BFD_RELOC_32_PCREL
7535 && fixp
->fx_addsy
== GOT_symbol
)
7537 code
= BFD_RELOC_ARM_GOTPC
;
7538 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
7542 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7544 if (reloc
->howto
== NULL
)
7546 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7547 _("Can not represent %s relocation in this object file format"),
7548 bfd_get_reloc_code_name (code
));
7552 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
7553 vtable entry to be used in the relocation's section offset. */
7554 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7555 reloc
->address
= fixp
->fx_offset
;
7561 md_estimate_size_before_relax (fragP
, segtype
)
7562 fragS
* fragP ATTRIBUTE_UNUSED
;
7563 segT segtype ATTRIBUTE_UNUSED
;
7565 as_fatal (_("md_estimate_size_before_relax\n"));
7570 output_inst
PARAMS ((void))
7576 as_bad (inst
.error
);
7580 to
= frag_more (inst
.size
);
7582 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
7584 assert (inst
.size
== (2 * THUMB_SIZE
));
7585 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
7586 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
7588 else if (inst
.size
> INSN_SIZE
)
7590 assert (inst
.size
== (2 * INSN_SIZE
));
7591 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
7592 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
7595 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
7597 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
7598 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
7599 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
7603 dwarf2_emit_insn (inst
.size
);
7616 /* Align the instruction.
7617 This may not be the right thing to do but ... */
7621 listing_prev_line (); /* Defined in listing.h. */
7623 /* Align the previous label if needed. */
7624 if (last_label_seen
!= NULL
)
7626 symbol_set_frag (last_label_seen
, frag_now
);
7627 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7628 S_SET_SEGMENT (last_label_seen
, now_seg
);
7631 memset (&inst
, '\0', sizeof (inst
));
7632 inst
.reloc
.type
= BFD_RELOC_NONE
;
7634 skip_whitespace (str
);
7636 /* Scan up to the end of the op-code, which must end in white space or
7638 for (start
= p
= str
; *p
!= '\0'; p
++)
7644 as_bad (_("No operator -- statement `%s'\n"), str
);
7650 CONST
struct thumb_opcode
* opcode
;
7654 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
7659 /* Check that this instruction is supported for this CPU. */
7660 if (thumb_mode
== 1 && (opcode
->variants
& cpu_variant
) == 0)
7662 as_bad (_("selected processor does not support this opcode"));
7666 inst
.instruction
= opcode
->value
;
7667 inst
.size
= opcode
->size
;
7668 (*opcode
->parms
) (p
);
7675 CONST
struct asm_opcode
* opcode
;
7676 unsigned long cond_code
;
7678 inst
.size
= INSN_SIZE
;
7679 /* P now points to the end of the opcode, probably white space, but we
7680 have to break the opcode up in case it contains condionals and flags;
7681 keep trying with progressively smaller basic instructions until one
7682 matches, or we run out of opcode. */
7683 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
7685 for (; q
!= str
; q
--)
7690 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
7693 if (opcode
&& opcode
->template)
7695 unsigned long flag_bits
= 0;
7698 /* Check that this instruction is supported for this CPU. */
7699 if ((opcode
->variants
& cpu_variant
) == 0)
7702 inst
.instruction
= opcode
->value
;
7703 if (q
== p
) /* Just a simple opcode. */
7705 if (opcode
->comp_suffix
)
7707 if (*opcode
->comp_suffix
!= '\0')
7708 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
7709 str
, opcode
->comp_suffix
);
7711 /* Not a conditional instruction. */
7712 (*opcode
->parms
) (q
, 0);
7716 /* A conditional instruction with default condition. */
7717 inst
.instruction
|= COND_ALWAYS
;
7718 (*opcode
->parms
) (q
, 0);
7724 /* Not just a simple opcode. Check if extra is a
7729 CONST
struct asm_cond
*cond
;
7733 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
7737 if (cond
->value
== 0xf0000000)
7739 _("Warning: Use of the 'nv' conditional is deprecated\n"));
7741 cond_code
= cond
->value
;
7745 cond_code
= COND_ALWAYS
;
7748 cond_code
= COND_ALWAYS
;
7750 /* Apply the conditional, or complain it's not allowed. */
7751 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
== '\0')
7753 /* Instruction isn't conditional. */
7754 if (cond_code
!= COND_ALWAYS
)
7756 as_bad (_("Opcode `%s' is unconditional\n"), str
);
7761 /* Instruction is conditional: set the condition into it. */
7762 inst
.instruction
|= cond_code
;
7764 /* If there is a compulsory suffix, it should come here
7765 before any optional flags. */
7766 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
!= '\0')
7768 CONST
char *s
= opcode
->comp_suffix
;
7780 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
7781 str
, opcode
->comp_suffix
);
7788 /* The remainder, if any should now be flags for the instruction;
7789 Scan these checking each one found with the opcode. */
7793 CONST
struct asm_flg
*flag
= opcode
->flags
;
7802 for (flagno
= 0; flag
[flagno
].template; flagno
++)
7804 if (streq (r
, flag
[flagno
].template))
7806 flag_bits
|= flag
[flagno
].set_bits
;
7812 if (! flag
[flagno
].template)
7819 (*opcode
->parms
) (p
, flag_bits
);
7829 /* It wasn't an instruction, but it might be a register alias of the form
7832 skip_whitespace (q
);
7837 if (*q
&& !strncmp (q
, ".req ", 4))
7843 #ifdef IGNORE_OPCODE_CASE
7844 str
= original_case_string
;
7849 skip_whitespace (q
);
7851 for (r
= q
; *r
!= '\0'; r
++)
7861 regnum
= arm_reg_parse (& q
);
7864 reg
= arm_reg_parse (& str
);
7869 insert_reg_alias (str
, regnum
);
7871 as_warn (_("register '%s' does not exist\n"), q
);
7873 else if (regnum
!= FAIL
)
7876 as_warn (_("ignoring redefinition of register alias '%s'"),
7879 /* Do not warn about redefinitions to the same alias. */
7882 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
7886 as_warn (_("ignoring incomplete .req pseuso op"));
7893 as_bad (_("bad instruction `%s'"), start
);
7897 Invocation line includes a switch not recognized by the base assembler.
7898 See if it's a processor-specific option. These are:
7899 Cpu variants, the arm part is optional:
7900 -m[arm]1 Currently not supported.
7901 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
7902 -m[arm]3 Arm 3 processor
7903 -m[arm]6[xx], Arm 6 processors
7904 -m[arm]7[xx][t][[d]m] Arm 7 processors
7905 -m[arm]8[10] Arm 8 processors
7906 -m[arm]9[20][tdmi] Arm 9 processors
7907 -mstrongarm[110[0]] StrongARM processors
7908 -mxscale XScale processors
7909 -m[arm]v[2345[t[e]]] Arm architectures
7910 -mall All (except the ARM1)
7912 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
7913 -mfpe-old (No float load/store multiples)
7914 -mno-fpu Disable all floating point instructions
7915 Run-time endian selection:
7917 -EL little endian cpu
7918 ARM Procedure Calling Standard:
7919 -mapcs-32 32 bit APCS
7920 -mapcs-26 26 bit APCS
7921 -mapcs-float Pass floats in float regs
7922 -mapcs-reentrant Position independent code
7923 -mthumb-interwork Code supports Arm/Thumb interworking
7924 -matpcs ARM/Thumb Procedure Call Standard
7925 -moabi Old ELF ABI */
7927 CONST
char * md_shortopts
= "m:k";
7929 struct option md_longopts
[] =
7931 #ifdef ARM_BI_ENDIAN
7932 #define OPTION_EB (OPTION_MD_BASE + 0)
7933 {"EB", no_argument
, NULL
, OPTION_EB
},
7934 #define OPTION_EL (OPTION_MD_BASE + 1)
7935 {"EL", no_argument
, NULL
, OPTION_EL
},
7937 #define OPTION_OABI (OPTION_MD_BASE +2)
7938 {"oabi", no_argument
, NULL
, OPTION_OABI
},
7941 {NULL
, no_argument
, NULL
, 0}
7944 size_t md_longopts_size
= sizeof (md_longopts
);
7947 md_parse_option (c
, arg
)
7955 #ifdef ARM_BI_ENDIAN
7957 target_big_endian
= 1;
7960 target_big_endian
= 0;
7968 if (streq (str
, "fpa10"))
7969 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
7970 else if (streq (str
, "fpa11"))
7971 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
7972 else if (streq (str
, "fpe-old"))
7973 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
7979 if (streq (str
, "no-fpu"))
7980 cpu_variant
&= ~FPU_ALL
;
7985 if (streq (str
, "oabi"))
7991 /* Limit assembler to generating only Thumb instructions: */
7992 if (streq (str
, "thumb"))
7994 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_EXT_THUMB
;
7995 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
7998 else if (streq (str
, "thumb-interwork"))
8000 if ((cpu_variant
& ARM_EXT_THUMB
) == 0)
8001 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4T
;
8002 #if defined OBJ_COFF || defined OBJ_ELF
8003 support_interwork
= true;
8011 if (streq (str
, "all"))
8013 cpu_variant
= ARM_ALL
| FPU_ALL
;
8016 #if defined OBJ_COFF || defined OBJ_ELF
8017 if (! strncmp (str
, "apcs-", 5))
8019 /* GCC passes on all command line options starting "-mapcs-..."
8020 to us, so we must parse them here. */
8024 if (streq (str
, "32"))
8026 uses_apcs_26
= false;
8029 else if (streq (str
, "26"))
8031 uses_apcs_26
= true;
8034 else if (streq (str
, "frame"))
8036 /* Stack frames are being generated - does not affect
8040 else if (streq (str
, "stack-check"))
8042 /* Stack checking is being performed - does not affect
8043 linkage, but does require that the functions
8044 __rt_stkovf_split_small and __rt_stkovf_split_big be
8045 present in the final link. */
8049 else if (streq (str
, "float"))
8051 /* Floating point arguments are being passed in the floating
8052 point registers. This does affect linking, since this
8053 version of the APCS is incompatible with the version that
8054 passes floating points in the integer registers. */
8056 uses_apcs_float
= true;
8059 else if (streq (str
, "reentrant"))
8061 /* Reentrant code has been generated. This does affect
8062 linking, since there is no point in linking reentrant/
8063 position independent code with absolute position code. */
8068 as_bad (_("Unrecognised APCS switch -m%s"), arg
);
8072 if (! strcmp (str
, "atpcs"))
8078 /* Strip off optional "arm". */
8079 if (! strncmp (str
, "arm", 3))
8085 if (streq (str
, "1"))
8086 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
8092 if (streq (str
, "2"))
8093 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
8094 else if (streq (str
, "250"))
8095 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
8101 if (streq (str
, "3"))
8102 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
8108 switch (strtol (str
, NULL
, 10))
8115 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
8123 /* Eat the processor name. */
8124 switch (strtol (str
, & str
, 10))
8137 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
8143 cpu_variant
|= ARM_ARCH_V4T
;
8147 cpu_variant
|= ARM_EXT_LONGMUL
;
8150 case 'f': /* fe => fp enabled cpu. */
8156 case 'c': /* Left over from 710c processor name. */
8157 case 'd': /* Debug. */
8158 case 'i': /* Embedded ICE. */
8159 /* Included for completeness in ARM processor naming. */
8169 if (streq (str
, "8") || streq (str
, "810"))
8170 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8171 | ARM_8
| ARM_ARCH_V4
;
8177 if (streq (str
, "9"))
8178 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8179 | ARM_9
| ARM_ARCH_V4T
;
8180 else if (streq (str
, "920"))
8181 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8182 | ARM_9
| ARM_ARCH_V4
;
8183 else if (streq (str
, "920t"))
8184 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8185 | ARM_9
| ARM_ARCH_V4T
;
8186 else if (streq (str
, "9tdmi"))
8187 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8188 | ARM_9
| ARM_ARCH_V4T
;
8194 if (streq (str
, "strongarm")
8195 || streq (str
, "strongarm110")
8196 || streq (str
, "strongarm1100"))
8197 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
8198 | ARM_8
| ARM_ARCH_V4
;
8204 if (streq (str
, "xscale"))
8205 cpu_variant
= ARM_9
| ARM_ARCH_XSCALE
;
8211 /* Select variant based on architecture rather than
8219 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
8222 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
8225 as_bad (_("Invalid architecture variant -m%s"), arg
);
8231 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
8235 case 'm': cpu_variant
|= ARM_EXT_LONGMUL
; break;
8238 as_bad (_("Invalid architecture variant -m%s"), arg
);
8244 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
| ARM_ARCH_V4
;
8248 case 't': cpu_variant
|= ARM_EXT_THUMB
; break;
8251 as_bad (_("Invalid architecture variant -m%s"), arg
);
8257 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_9
| ARM_ARCH_V5
;
8260 case 't': cpu_variant
|= ARM_EXT_THUMB
; break;
8261 case 'e': cpu_variant
|= ARM_EXT_V5E
; break;
8264 as_bad (_("Invalid architecture variant -m%s"), arg
);
8270 as_bad (_("Invalid architecture variant -m%s"), arg
);
8277 as_bad (_("Invalid processor variant -m%s"), arg
);
8283 #if defined OBJ_ELF || defined OBJ_COFF
8301 ARM Specific Assembler Options:\n\
8302 -m[arm][<processor name>] select processor variant\n\
8303 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
8304 -mthumb only allow Thumb instructions\n\
8305 -mthumb-interwork mark the assembled code as supporting interworking\n\
8306 -mall allow any instruction\n\
8307 -mfpa10, -mfpa11 select floating point architecture\n\
8308 -mfpe-old don't allow floating-point multiple instructions\n\
8309 -mno-fpu don't allow any floating-point instructions.\n\
8310 -k generate PIC code.\n"));
8311 #if defined OBJ_COFF || defined OBJ_ELF
8313 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
8314 -matpcs use ARM/Thumb Procedure Calling Standard\n\
8315 -mapcs-float floating point args are passed in FP regs\n\
8316 -mapcs-reentrant the code is position independent/reentrant\n"));
8320 -moabi support the old ELF ABI\n"));
8322 #ifdef ARM_BI_ENDIAN
8324 -EB assemble code for a big endian cpu\n\
8325 -EL assemble code for a little endian cpu\n"));
8329 /* We need to be able to fix up arbitrary expressions in some statements.
8330 This is so that we can handle symbols that are an arbitrary distance from
8331 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8332 which returns part of an address in a form which will be valid for
8333 a data instruction. We do this by pushing the expression into a symbol
8334 in the expr_section, and creating a fix for that. */
8337 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
8346 arm_fix_data
* arm_data
;
8354 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
8358 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
8363 /* Mark whether the fix is to a THUMB instruction, or an ARM
8365 arm_data
= (arm_fix_data
*) obstack_alloc (& notes
, sizeof (arm_fix_data
));
8366 new_fix
->tc_fix_data
= (PTR
) arm_data
;
8367 arm_data
->thumb_mode
= thumb_mode
;
8372 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8375 cons_fix_new_arm (frag
, where
, size
, exp
)
8381 bfd_reloc_code_real_type type
;
8385 FIXME: @@ Should look at CPU word size. */
8392 type
= BFD_RELOC_16
;
8396 type
= BFD_RELOC_32
;
8399 type
= BFD_RELOC_64
;
8403 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8406 /* A good place to do this, although this was probably not intended
8407 for this kind of use. We need to dump the literal pool before
8408 references are made to a null symbol pointer. */
8413 if (current_poolP
== NULL
)
8416 /* Put it at the end of text section. */
8417 subseg_set (text_section
, 0);
8419 listing_prev_line ();
8423 arm_start_line_hook ()
8425 last_label_seen
= NULL
;
8429 arm_frob_label (sym
)
8432 last_label_seen
= sym
;
8434 ARM_SET_THUMB (sym
, thumb_mode
);
8436 #if defined OBJ_COFF || defined OBJ_ELF
8437 ARM_SET_INTERWORK (sym
, support_interwork
);
8440 /* Note - do not allow local symbols (.Lxxx) to be labeled
8441 as Thumb functions. This is because these labels, whilst
8442 they exist inside Thumb code, are not the entry points for
8443 possible ARM->Thumb calls. Also, these labels can be used
8444 as part of a computed goto or switch statement. eg gcc
8445 can generate code that looks like this:
8457 The first instruction loads the address of the jump table.
8458 The second instruction converts a table index into a byte offset.
8459 The third instruction gets the jump address out of the table.
8460 The fourth instruction performs the jump.
8462 If the address stored at .Laaa is that of a symbol which has the
8463 Thumb_Func bit set, then the linker will arrange for this address
8464 to have the bottom bit set, which in turn would mean that the
8465 address computation performed by the third instruction would end
8466 up with the bottom bit set. Since the ARM is capable of unaligned
8467 word loads, the instruction would then load the incorrect address
8468 out of the jump table, and chaos would ensue. */
8469 if (label_is_thumb_function_name
8470 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
8471 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
8473 /* When the address of a Thumb function is taken the bottom
8474 bit of that address should be set. This will allow
8475 interworking between Arm and Thumb functions to work
8478 THUMB_SET_FUNC (sym
, 1);
8480 label_is_thumb_function_name
= false;
8484 /* Adjust the symbol table. This marks Thumb symbols as distinct from
8488 arm_adjust_symtab ()
8493 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
8495 if (ARM_IS_THUMB (sym
))
8497 if (THUMB_IS_FUNC (sym
))
8499 /* Mark the symbol as a Thumb function. */
8500 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
8501 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
8502 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
8504 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
8505 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
8507 as_bad (_("%s: unexpected function type: %d"),
8508 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
8510 else switch (S_GET_STORAGE_CLASS (sym
))
8513 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
8516 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
8519 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
8527 if (ARM_IS_INTERWORK (sym
))
8528 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
8535 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
8537 if (ARM_IS_THUMB (sym
))
8539 elf_symbol_type
* elf_sym
;
8541 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
8542 bind
= ELF_ST_BIND (elf_sym
);
8544 /* If it's a .thumb_func, declare it as so,
8545 otherwise tag label as .code 16. */
8546 if (THUMB_IS_FUNC (sym
))
8547 elf_sym
->internal_elf_sym
.st_info
=
8548 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
8550 elf_sym
->internal_elf_sym
.st_info
=
8551 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
8560 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
8562 *input_line_pointer
= '/';
8563 input_line_pointer
+= 5;
8564 *input_line_pointer
= 0;
8572 arm_canonicalize_symbol_name (name
)
8577 if (thumb_mode
&& (len
= strlen (name
)) > 5
8578 && streq (name
+ len
- 5, "/data"))
8579 *(name
+ len
- 5) = 0;
8585 arm_validate_fix (fixP
)
8588 /* If the destination of the branch is a defined symbol which does not have
8589 the THUMB_FUNC attribute, then we must be calling a function which has
8590 the (interfacearm) attribute. We look for the Thumb entry point to that
8591 function and change the branch to refer to that function instead. */
8592 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
8593 && fixP
->fx_addsy
!= NULL
8594 && S_IS_DEFINED (fixP
->fx_addsy
)
8595 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
8597 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
8605 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
8606 local labels from being added to the output symbol table when they
8607 are used with the ADRL pseudo op. The ADRL relocation should always
8608 be resolved before the binbary is emitted, so it is safe to say that
8609 it is adjustable. */
8612 arm_fix_adjustable (fixP
)
8615 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
8621 /* Relocations against Thumb function names must be left unadjusted,
8622 so that the linker can use this information to correctly set the
8623 bottom bit of their addresses. The MIPS version of this function
8624 also prevents relocations that are mips-16 specific, but I do not
8625 know why it does this.
8628 There is one other problem that ought to be addressed here, but
8629 which currently is not: Taking the address of a label (rather
8630 than a function) and then later jumping to that address. Such
8631 addresses also ought to have their bottom bit set (assuming that
8632 they reside in Thumb code), but at the moment they will not. */
8635 arm_fix_adjustable (fixP
)
8638 if (fixP
->fx_addsy
== NULL
)
8641 /* Prevent all adjustments to global symbols. */
8642 if (S_IS_EXTERN (fixP
->fx_addsy
))
8645 if (S_IS_WEAK (fixP
->fx_addsy
))
8648 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
8649 && fixP
->fx_subsy
== NULL
)
8652 /* We need the symbol name for the VTABLE entries. */
8653 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
8654 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8661 elf32_arm_target_format ()
8663 if (target_big_endian
)
8666 return "elf32-bigarm-oabi";
8668 return "elf32-bigarm";
8673 return "elf32-littlearm-oabi";
8675 return "elf32-littlearm";
8680 armelf_frob_symbol (symp
, puntp
)
8684 elf_frob_symbol (symp
, puntp
);
8688 arm_force_relocation (fixp
)
8691 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
8692 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
8693 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
8694 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
8695 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
8696 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
)
8702 static bfd_reloc_code_real_type
8712 bfd_reloc_code_real_type reloc
;
8716 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
8717 MAP ("(got)", BFD_RELOC_ARM_GOT32
),
8718 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF
),
8719 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
8720 branch instructions generated by GCC for PLT relocs. */
8721 MAP ("(plt)", BFD_RELOC_ARM_PLT32
),
8722 { NULL
, 0, BFD_RELOC_UNUSED
}
8726 for (i
= 0, ip
= input_line_pointer
;
8727 i
< sizeof (id
) && (ISALNUM (*ip
) || ISPUNCT (*ip
));
8729 id
[i
] = TOLOWER (*ip
);
8731 for (i
= 0; reloc_map
[i
].str
; i
++)
8732 if (strncmp (id
, reloc_map
[i
].str
, reloc_map
[i
].len
) == 0)
8735 input_line_pointer
+= reloc_map
[i
].len
;
8737 return reloc_map
[i
].reloc
;
8741 s_arm_elf_cons (nbytes
)
8746 #ifdef md_flush_pending_output
8747 md_flush_pending_output ();
8750 if (is_it_end_of_statement ())
8752 demand_empty_rest_of_line ();
8756 #ifdef md_cons_align
8757 md_cons_align (nbytes
);
8762 bfd_reloc_code_real_type reloc
;
8766 if (exp
.X_op
== O_symbol
8767 && * input_line_pointer
== '('
8768 && (reloc
= arm_parse_reloc ()) != BFD_RELOC_UNUSED
)
8770 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
8771 int size
= bfd_get_reloc_size (howto
);
8774 as_bad ("%s relocations do not fit in %d bytes",
8775 howto
->name
, nbytes
);
8778 register char *p
= frag_more ((int) nbytes
);
8779 int offset
= nbytes
- size
;
8781 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
8786 emit_expr (&exp
, (unsigned int) nbytes
);
8788 while (*input_line_pointer
++ == ',');
8790 /* Put terminator back into stream. */
8791 input_line_pointer
--;
8792 demand_empty_rest_of_line ();
8795 #endif /* OBJ_ELF */
8797 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8798 of an rs_align_code fragment. */
8801 arm_handle_align (fragP
)
8804 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
8805 static char const thumb_noop
[2] = { 0xc0, 0x46 };
8806 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
8807 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
8809 int bytes
, fix
, noop_size
;
8813 if (fragP
->fr_type
!= rs_align_code
)
8816 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8817 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8820 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
8821 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
8823 if (fragP
->tc_frag_data
)
8825 if (target_big_endian
)
8826 noop
= thumb_bigend_noop
;
8829 noop_size
= sizeof (thumb_noop
);
8833 if (target_big_endian
)
8834 noop
= arm_bigend_noop
;
8837 noop_size
= sizeof (arm_noop
);
8840 if (bytes
& (noop_size
- 1))
8842 fix
= bytes
& (noop_size
- 1);
8848 while (bytes
>= noop_size
)
8850 memcpy (p
, noop
, noop_size
);
8856 fragP
->fr_fix
+= fix
;
8857 fragP
->fr_var
= noop_size
;
8860 /* Called from md_do_align. Used to create an alignment
8861 frag in a code section. */
8864 arm_frag_align_code (n
, max
)
8870 /* We assume that there will never be a requirment
8871 to support alignments greater than 32 bytes. */
8872 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
8873 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
8875 p
= frag_var (rs_align_code
,
8876 MAX_MEM_FOR_RS_ALIGN_CODE
,
8878 (relax_substateT
) max
,
8886 /* Perform target specific initialisation of a frag. */
8889 arm_init_frag (fragP
)
8892 /* Record whether this frag is in an ARM or a THUMB area. */
8893 fragP
->tc_frag_data
= thumb_mode
;