1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNSDQ
, /* Neon single, double or quad precision register */
6906 OP_RNSC
, /* Neon scalar D[X] */
6907 OP_RVC
, /* VFP control register */
6908 OP_RMF
, /* Maverick F register */
6909 OP_RMD
, /* Maverick D register */
6910 OP_RMFX
, /* Maverick FX register */
6911 OP_RMDX
, /* Maverick DX register */
6912 OP_RMAX
, /* Maverick AX register */
6913 OP_RMDS
, /* Maverick DSPSC register */
6914 OP_RIWR
, /* iWMMXt wR register */
6915 OP_RIWC
, /* iWMMXt wC register */
6916 OP_RIWG
, /* iWMMXt wCG register */
6917 OP_RXA
, /* XScale accumulator register */
6919 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6921 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6923 OP_RMQ
, /* MVE vector register. */
6924 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 /* New operands for Armv8.1-M Mainline. */
6927 OP_LR
, /* ARM LR register */
6928 OP_RRe
, /* ARM register, only even numbered. */
6929 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6930 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6932 OP_REGLST
, /* ARM register list */
6933 OP_CLRMLST
, /* CLRM register list */
6934 OP_VRSLST
, /* VFP single-precision register list */
6935 OP_VRDLST
, /* VFP double-precision register list */
6936 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6937 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6938 OP_NSTRLST
, /* Neon element/structure list */
6939 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6940 OP_MSTRLST2
, /* MVE vector list with two elements. */
6941 OP_MSTRLST4
, /* MVE vector list with four elements. */
6943 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6944 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6945 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6946 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6948 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6949 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6950 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6953 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6954 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6955 OP_VMOV
, /* Neon VMOV operands. */
6956 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6957 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6958 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6959 OP_VLDR
, /* VLDR operand. */
6961 OP_I0
, /* immediate zero */
6962 OP_I7
, /* immediate value 0 .. 7 */
6963 OP_I15
, /* 0 .. 15 */
6964 OP_I16
, /* 1 .. 16 */
6965 OP_I16z
, /* 0 .. 16 */
6966 OP_I31
, /* 0 .. 31 */
6967 OP_I31w
, /* 0 .. 31, optional trailing ! */
6968 OP_I32
, /* 1 .. 32 */
6969 OP_I32z
, /* 0 .. 32 */
6970 OP_I63
, /* 0 .. 63 */
6971 OP_I63s
, /* -64 .. 63 */
6972 OP_I64
, /* 1 .. 64 */
6973 OP_I64z
, /* 0 .. 64 */
6974 OP_I255
, /* 0 .. 255 */
6976 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6977 OP_I7b
, /* 0 .. 7 */
6978 OP_I15b
, /* 0 .. 15 */
6979 OP_I31b
, /* 0 .. 31 */
6981 OP_SH
, /* shifter operand */
6982 OP_SHG
, /* shifter operand with possible group relocation */
6983 OP_ADDR
, /* Memory address expression (any mode) */
6984 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6985 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6986 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6987 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6988 OP_EXP
, /* arbitrary expression */
6989 OP_EXPi
, /* same, with optional immediate prefix */
6990 OP_EXPr
, /* same, with optional relocation suffix */
6991 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6992 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6993 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6994 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6996 OP_CPSF
, /* CPS flags */
6997 OP_ENDI
, /* Endianness specifier */
6998 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6999 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7000 OP_COND
, /* conditional code */
7001 OP_TB
, /* Table branch. */
7003 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7005 OP_RRnpc_I0
, /* ARM register or literal 0 */
7006 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7007 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7008 OP_RF_IF
, /* FPA register or immediate */
7009 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7010 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7012 /* Optional operands. */
7013 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7014 OP_oI31b
, /* 0 .. 31 */
7015 OP_oI32b
, /* 1 .. 32 */
7016 OP_oI32z
, /* 0 .. 32 */
7017 OP_oIffffb
, /* 0 .. 65535 */
7018 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7020 OP_oRR
, /* ARM register */
7021 OP_oLR
, /* ARM LR register */
7022 OP_oRRnpc
, /* ARM register, not the PC */
7023 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7024 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7025 OP_oRND
, /* Optional Neon double precision register */
7026 OP_oRNQ
, /* Optional Neon quad precision register */
7027 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7028 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7029 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7030 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7032 OP_oSHll
, /* LSL immediate */
7033 OP_oSHar
, /* ASR immediate */
7034 OP_oSHllar
, /* LSL or ASR immediate */
7035 OP_oROR
, /* ROR 0/8/16/24 */
7036 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7038 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7040 /* Some pre-defined mixed (ARM/THUMB) operands. */
7041 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7042 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7043 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7045 OP_FIRST_OPTIONAL
= OP_oI7b
7048 /* Generic instruction operand parser. This does no encoding and no
7049 semantic validation; it merely squirrels values away in the inst
7050 structure. Returns SUCCESS or FAIL depending on whether the
7051 specified grammar matched. */
7053 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7055 unsigned const int *upat
= pattern
;
7056 char *backtrack_pos
= 0;
7057 const char *backtrack_error
= 0;
7058 int i
, val
= 0, backtrack_index
= 0;
7059 enum arm_reg_type rtype
;
7060 parse_operand_result result
;
7061 unsigned int op_parse_code
;
7062 bfd_boolean partial_match
;
7064 #define po_char_or_fail(chr) \
7067 if (skip_past_char (&str, chr) == FAIL) \
7072 #define po_reg_or_fail(regtype) \
7075 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7076 & inst.operands[i].vectype); \
7079 first_error (_(reg_expected_msgs[regtype])); \
7082 inst.operands[i].reg = val; \
7083 inst.operands[i].isreg = 1; \
7084 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7085 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7086 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7087 || rtype == REG_TYPE_VFD \
7088 || rtype == REG_TYPE_NQ); \
7089 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7093 #define po_reg_or_goto(regtype, label) \
7096 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7097 & inst.operands[i].vectype); \
7101 inst.operands[i].reg = val; \
7102 inst.operands[i].isreg = 1; \
7103 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7104 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7105 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7106 || rtype == REG_TYPE_VFD \
7107 || rtype == REG_TYPE_NQ); \
7108 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7112 #define po_imm_or_fail(min, max, popt) \
7115 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7117 inst.operands[i].imm = val; \
7121 #define po_scalar_or_goto(elsz, label, reg_type) \
7124 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7128 inst.operands[i].reg = val; \
7129 inst.operands[i].isscalar = 1; \
7133 #define po_misc_or_fail(expr) \
7141 #define po_misc_or_fail_no_backtrack(expr) \
7145 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7146 backtrack_pos = 0; \
7147 if (result != PARSE_OPERAND_SUCCESS) \
7152 #define po_barrier_or_imm(str) \
7155 val = parse_barrier (&str); \
7156 if (val == FAIL && ! ISALPHA (*str)) \
7159 /* ISB can only take SY as an option. */ \
7160 || ((inst.instruction & 0xf0) == 0x60 \
7163 inst.error = _("invalid barrier type"); \
7164 backtrack_pos = 0; \
7170 skip_whitespace (str
);
7172 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7174 op_parse_code
= upat
[i
];
7175 if (op_parse_code
>= 1<<16)
7176 op_parse_code
= thumb
? (op_parse_code
>> 16)
7177 : (op_parse_code
& ((1<<16)-1));
7179 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7181 /* Remember where we are in case we need to backtrack. */
7182 backtrack_pos
= str
;
7183 backtrack_error
= inst
.error
;
7184 backtrack_index
= i
;
7187 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7188 po_char_or_fail (',');
7190 switch (op_parse_code
)
7202 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7203 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7204 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7205 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7206 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7207 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7210 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7214 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7217 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7219 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7221 /* Also accept generic coprocessor regs for unknown registers. */
7223 po_reg_or_fail (REG_TYPE_CN
);
7225 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7226 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7227 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7228 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7229 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7230 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7231 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7232 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7233 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7234 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7237 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7240 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7241 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7244 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7248 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7250 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7253 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7255 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7258 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7260 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7265 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7268 po_reg_or_fail (REG_TYPE_NSDQ
);
7272 po_reg_or_fail (REG_TYPE_MQ
);
7274 /* Neon scalar. Using an element size of 8 means that some invalid
7275 scalars are accepted here, so deal with those in later code. */
7276 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7280 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7283 po_imm_or_fail (0, 0, TRUE
);
7288 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7292 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7297 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7300 if (parse_ifimm_zero (&str
))
7301 inst
.operands
[i
].imm
= 0;
7305 = _("only floating point zero is allowed as immediate value");
7313 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7316 po_reg_or_fail (REG_TYPE_RN
);
7320 case OP_RNSDQ_RNSC_MQ
:
7321 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7326 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7330 po_reg_or_fail (REG_TYPE_NSDQ
);
7337 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7340 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7343 po_reg_or_fail (REG_TYPE_NSD
);
7349 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7352 po_reg_or_fail (REG_TYPE_NDQ
);
7358 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7361 po_reg_or_fail (REG_TYPE_VFD
);
7366 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7367 not careful then bad things might happen. */
7368 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7373 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7376 /* There's a possibility of getting a 64-bit immediate here, so
7377 we need special handling. */
7378 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7381 inst
.error
= _("immediate value is out of range");
7389 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7392 po_imm_or_fail (0, 63, TRUE
);
7397 po_char_or_fail ('[');
7398 po_reg_or_fail (REG_TYPE_RN
);
7399 po_char_or_fail (']');
7405 po_reg_or_fail (REG_TYPE_RN
);
7406 if (skip_past_char (&str
, '!') == SUCCESS
)
7407 inst
.operands
[i
].writeback
= 1;
7411 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7412 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7413 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7414 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7415 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7416 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7417 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7418 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7419 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7420 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7421 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7422 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7424 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7426 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7427 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7429 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7430 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7431 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7432 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7434 /* Immediate variants */
7436 po_char_or_fail ('{');
7437 po_imm_or_fail (0, 255, TRUE
);
7438 po_char_or_fail ('}');
7442 /* The expression parser chokes on a trailing !, so we have
7443 to find it first and zap it. */
7446 while (*s
&& *s
!= ',')
7451 inst
.operands
[i
].writeback
= 1;
7453 po_imm_or_fail (0, 31, TRUE
);
7461 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7466 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7471 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7473 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7475 val
= parse_reloc (&str
);
7478 inst
.error
= _("unrecognized relocation suffix");
7481 else if (val
!= BFD_RELOC_UNUSED
)
7483 inst
.operands
[i
].imm
= val
;
7484 inst
.operands
[i
].hasreloc
= 1;
7490 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7492 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7494 inst
.operands
[i
].hasreloc
= 1;
7496 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7498 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7499 inst
.operands
[i
].hasreloc
= 0;
7503 /* Operand for MOVW or MOVT. */
7505 po_misc_or_fail (parse_half (&str
));
7508 /* Register or expression. */
7509 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7510 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7512 /* Register or immediate. */
7513 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7514 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7516 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7518 if (!is_immediate_prefix (*str
))
7521 val
= parse_fpa_immediate (&str
);
7524 /* FPA immediates are encoded as registers 8-15.
7525 parse_fpa_immediate has already applied the offset. */
7526 inst
.operands
[i
].reg
= val
;
7527 inst
.operands
[i
].isreg
= 1;
7530 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7531 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7533 /* Two kinds of register. */
7536 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7538 || (rege
->type
!= REG_TYPE_MMXWR
7539 && rege
->type
!= REG_TYPE_MMXWC
7540 && rege
->type
!= REG_TYPE_MMXWCG
))
7542 inst
.error
= _("iWMMXt data or control register expected");
7545 inst
.operands
[i
].reg
= rege
->number
;
7546 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7552 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7554 || (rege
->type
!= REG_TYPE_MMXWC
7555 && rege
->type
!= REG_TYPE_MMXWCG
))
7557 inst
.error
= _("iWMMXt control register expected");
7560 inst
.operands
[i
].reg
= rege
->number
;
7561 inst
.operands
[i
].isreg
= 1;
7566 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7567 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7568 case OP_oROR
: val
= parse_ror (&str
); break;
7570 case OP_COND
: val
= parse_cond (&str
); break;
7571 case OP_oBARRIER_I15
:
7572 po_barrier_or_imm (str
); break;
7574 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7580 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7581 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7583 inst
.error
= _("Banked registers are not available with this "
7589 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7593 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7596 val
= parse_sys_vldr_vstr (&str
);
7600 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7603 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7605 if (strncasecmp (str
, "APSR_", 5) == 0)
7612 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7613 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7614 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7615 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7616 default: found
= 16;
7620 inst
.operands
[i
].isvec
= 1;
7621 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7622 inst
.operands
[i
].reg
= REG_PC
;
7629 po_misc_or_fail (parse_tb (&str
));
7632 /* Register lists. */
7634 val
= parse_reg_list (&str
, REGLIST_RN
);
7637 inst
.operands
[i
].writeback
= 1;
7643 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7647 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7652 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7657 /* Allow Q registers too. */
7658 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7659 REGLIST_NEON_D
, &partial_match
);
7663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7664 REGLIST_VFP_S
, &partial_match
);
7665 inst
.operands
[i
].issingle
= 1;
7670 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7671 REGLIST_VFP_D_VPR
, &partial_match
);
7672 if (val
== FAIL
&& !partial_match
)
7675 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7676 REGLIST_VFP_S_VPR
, &partial_match
);
7677 inst
.operands
[i
].issingle
= 1;
7682 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7683 REGLIST_NEON_D
, &partial_match
);
7688 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7689 1, &inst
.operands
[i
].vectype
);
7690 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7694 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7695 0, &inst
.operands
[i
].vectype
);
7698 /* Addressing modes */
7700 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7704 po_misc_or_fail (parse_address (&str
, i
));
7708 po_misc_or_fail_no_backtrack (
7709 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7713 po_misc_or_fail_no_backtrack (
7714 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7718 po_misc_or_fail_no_backtrack (
7719 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7723 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7727 po_misc_or_fail_no_backtrack (
7728 parse_shifter_operand_group_reloc (&str
, i
));
7732 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7736 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7740 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7745 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7748 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7751 po_reg_or_fail (REG_TYPE_ZR
);
7755 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7758 /* Various value-based sanity checks and shared operations. We
7759 do not signal immediate failures for the register constraints;
7760 this allows a syntax error to take precedence. */
7761 switch (op_parse_code
)
7769 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7770 inst
.error
= BAD_PC
;
7775 if (inst
.operands
[i
].isreg
)
7777 if (inst
.operands
[i
].reg
== REG_PC
)
7778 inst
.error
= BAD_PC
;
7779 else if (inst
.operands
[i
].reg
== REG_SP
7780 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7781 relaxed since ARMv8-A. */
7782 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7785 inst
.error
= BAD_SP
;
7791 if (inst
.operands
[i
].isreg
7792 && inst
.operands
[i
].reg
== REG_PC
7793 && (inst
.operands
[i
].writeback
|| thumb
))
7794 inst
.error
= BAD_PC
;
7799 if (inst
.operands
[i
].isreg
)
7809 case OP_oBARRIER_I15
:
7822 inst
.operands
[i
].imm
= val
;
7827 if (inst
.operands
[i
].reg
!= REG_LR
)
7828 inst
.error
= _("operand must be LR register");
7833 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7834 inst
.error
= BAD_PC
;
7838 if (inst
.operands
[i
].isreg
7839 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7840 inst
.error
= BAD_ODD
;
7844 if (inst
.operands
[i
].isreg
)
7846 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7847 inst
.error
= BAD_EVEN
;
7848 else if (inst
.operands
[i
].reg
== REG_SP
)
7849 as_tsktsk (MVE_BAD_SP
);
7850 else if (inst
.operands
[i
].reg
== REG_PC
)
7851 inst
.error
= BAD_PC
;
7859 /* If we get here, this operand was successfully parsed. */
7860 inst
.operands
[i
].present
= 1;
7864 inst
.error
= BAD_ARGS
;
7869 /* The parse routine should already have set inst.error, but set a
7870 default here just in case. */
7872 inst
.error
= BAD_SYNTAX
;
7876 /* Do not backtrack over a trailing optional argument that
7877 absorbed some text. We will only fail again, with the
7878 'garbage following instruction' error message, which is
7879 probably less helpful than the current one. */
7880 if (backtrack_index
== i
&& backtrack_pos
!= str
7881 && upat
[i
+1] == OP_stop
)
7884 inst
.error
= BAD_SYNTAX
;
7888 /* Try again, skipping the optional argument at backtrack_pos. */
7889 str
= backtrack_pos
;
7890 inst
.error
= backtrack_error
;
7891 inst
.operands
[backtrack_index
].present
= 0;
7892 i
= backtrack_index
;
7896 /* Check that we have parsed all the arguments. */
7897 if (*str
!= '\0' && !inst
.error
)
7898 inst
.error
= _("garbage following instruction");
7900 return inst
.error
? FAIL
: SUCCESS
;
7903 #undef po_char_or_fail
7904 #undef po_reg_or_fail
7905 #undef po_reg_or_goto
7906 #undef po_imm_or_fail
7907 #undef po_scalar_or_fail
7908 #undef po_barrier_or_imm
7910 /* Shorthand macro for instruction encoding functions issuing errors. */
7911 #define constraint(expr, err) \
7922 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7923 instructions are unpredictable if these registers are used. This
7924 is the BadReg predicate in ARM's Thumb-2 documentation.
7926 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7927 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7928 #define reject_bad_reg(reg) \
7930 if (reg == REG_PC) \
7932 inst.error = BAD_PC; \
7935 else if (reg == REG_SP \
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7938 inst.error = BAD_SP; \
7943 /* If REG is R13 (the stack pointer), warn that its use is
7945 #define warn_deprecated_sp(reg) \
7947 if (warn_on_deprecated && reg == REG_SP) \
7948 as_tsktsk (_("use of r13 is deprecated")); \
7951 /* Functions for operand encoding. ARM, then Thumb. */
7953 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7955 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7957 The only binary encoding difference is the Coprocessor number. Coprocessor
7958 9 is used for half-precision calculations or conversions. The format of the
7959 instruction is the same as the equivalent Coprocessor 10 instruction that
7960 exists for Single-Precision operation. */
7963 do_scalar_fp16_v82_encode (void)
7965 if (inst
.cond
< COND_ALWAYS
)
7966 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7967 " the behaviour is UNPREDICTABLE"));
7968 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7971 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7972 mark_feature_used (&arm_ext_fp16
);
7975 /* If VAL can be encoded in the immediate field of an ARM instruction,
7976 return the encoded form. Otherwise, return FAIL. */
7979 encode_arm_immediate (unsigned int val
)
7986 for (i
= 2; i
< 32; i
+= 2)
7987 if ((a
= rotate_left (val
, i
)) <= 0xff)
7988 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7993 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7994 return the encoded form. Otherwise, return FAIL. */
7996 encode_thumb32_immediate (unsigned int val
)
8003 for (i
= 1; i
<= 24; i
++)
8006 if ((val
& ~(0xff << i
)) == 0)
8007 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8011 if (val
== ((a
<< 16) | a
))
8013 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8017 if (val
== ((a
<< 16) | a
))
8018 return 0x200 | (a
>> 8);
8022 /* Encode a VFP SP or DP register number into inst.instruction. */
8025 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8027 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8033 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8036 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8041 first_error (_("D register out of range for selected VFP version"));
8049 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8053 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8057 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8061 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8065 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8069 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8077 /* Encode a <shift> in an ARM-format instruction. The immediate,
8078 if any, is handled by md_apply_fix. */
8080 encode_arm_shift (int i
)
8082 /* register-shifted register. */
8083 if (inst
.operands
[i
].immisreg
)
8086 for (op_index
= 0; op_index
<= i
; ++op_index
)
8088 /* Check the operand only when it's presented. In pre-UAL syntax,
8089 if the destination register is the same as the first operand, two
8090 register form of the instruction can be used. */
8091 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8092 && inst
.operands
[op_index
].reg
== REG_PC
)
8093 as_warn (UNPRED_REG ("r15"));
8096 if (inst
.operands
[i
].imm
== REG_PC
)
8097 as_warn (UNPRED_REG ("r15"));
8100 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8101 inst
.instruction
|= SHIFT_ROR
<< 5;
8104 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8105 if (inst
.operands
[i
].immisreg
)
8107 inst
.instruction
|= SHIFT_BY_REG
;
8108 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8111 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8116 encode_arm_shifter_operand (int i
)
8118 if (inst
.operands
[i
].isreg
)
8120 inst
.instruction
|= inst
.operands
[i
].reg
;
8121 encode_arm_shift (i
);
8125 inst
.instruction
|= INST_IMMEDIATE
;
8126 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8127 inst
.instruction
|= inst
.operands
[i
].imm
;
8131 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8133 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8136 Generate an error if the operand is not a register. */
8137 constraint (!inst
.operands
[i
].isreg
,
8138 _("Instruction does not support =N addresses"));
8140 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8142 if (inst
.operands
[i
].preind
)
8146 inst
.error
= _("instruction does not accept preindexed addressing");
8149 inst
.instruction
|= PRE_INDEX
;
8150 if (inst
.operands
[i
].writeback
)
8151 inst
.instruction
|= WRITE_BACK
;
8154 else if (inst
.operands
[i
].postind
)
8156 gas_assert (inst
.operands
[i
].writeback
);
8158 inst
.instruction
|= WRITE_BACK
;
8160 else /* unindexed - only for coprocessor */
8162 inst
.error
= _("instruction does not accept unindexed addressing");
8166 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8167 && (((inst
.instruction
& 0x000f0000) >> 16)
8168 == ((inst
.instruction
& 0x0000f000) >> 12)))
8169 as_warn ((inst
.instruction
& LOAD_BIT
)
8170 ? _("destination register same as write-back base")
8171 : _("source register same as write-back base"));
8174 /* inst.operands[i] was set up by parse_address. Encode it into an
8175 ARM-format mode 2 load or store instruction. If is_t is true,
8176 reject forms that cannot be used with a T instruction (i.e. not
8179 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8181 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8183 encode_arm_addr_mode_common (i
, is_t
);
8185 if (inst
.operands
[i
].immisreg
)
8187 constraint ((inst
.operands
[i
].imm
== REG_PC
8188 || (is_pc
&& inst
.operands
[i
].writeback
)),
8190 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8191 inst
.instruction
|= inst
.operands
[i
].imm
;
8192 if (!inst
.operands
[i
].negative
)
8193 inst
.instruction
|= INDEX_UP
;
8194 if (inst
.operands
[i
].shifted
)
8196 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8197 inst
.instruction
|= SHIFT_ROR
<< 5;
8200 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8201 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8205 else /* immediate offset in inst.relocs[0] */
8207 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8209 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8211 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8212 cannot use PC in addressing.
8213 PC cannot be used in writeback addressing, either. */
8214 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8217 /* Use of PC in str is deprecated for ARMv7. */
8218 if (warn_on_deprecated
8220 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8221 as_tsktsk (_("use of PC in this instruction is deprecated"));
8224 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8226 /* Prefer + for zero encoded value. */
8227 if (!inst
.operands
[i
].negative
)
8228 inst
.instruction
|= INDEX_UP
;
8229 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8234 /* inst.operands[i] was set up by parse_address. Encode it into an
8235 ARM-format mode 3 load or store instruction. Reject forms that
8236 cannot be used with such instructions. If is_t is true, reject
8237 forms that cannot be used with a T instruction (i.e. not
8240 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8242 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8244 inst
.error
= _("instruction does not accept scaled register index");
8248 encode_arm_addr_mode_common (i
, is_t
);
8250 if (inst
.operands
[i
].immisreg
)
8252 constraint ((inst
.operands
[i
].imm
== REG_PC
8253 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8255 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8257 inst
.instruction
|= inst
.operands
[i
].imm
;
8258 if (!inst
.operands
[i
].negative
)
8259 inst
.instruction
|= INDEX_UP
;
8261 else /* immediate offset in inst.relocs[0] */
8263 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8264 && inst
.operands
[i
].writeback
),
8266 inst
.instruction
|= HWOFFSET_IMM
;
8267 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8269 /* Prefer + for zero encoded value. */
8270 if (!inst
.operands
[i
].negative
)
8271 inst
.instruction
|= INDEX_UP
;
8273 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8278 /* Write immediate bits [7:0] to the following locations:
8280 |28/24|23 19|18 16|15 4|3 0|
8281 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8283 This function is used by VMOV/VMVN/VORR/VBIC. */
8286 neon_write_immbits (unsigned immbits
)
8288 inst
.instruction
|= immbits
& 0xf;
8289 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8290 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8293 /* Invert low-order SIZE bits of XHI:XLO. */
8296 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8298 unsigned immlo
= xlo
? *xlo
: 0;
8299 unsigned immhi
= xhi
? *xhi
: 0;
8304 immlo
= (~immlo
) & 0xff;
8308 immlo
= (~immlo
) & 0xffff;
8312 immhi
= (~immhi
) & 0xffffffff;
8316 immlo
= (~immlo
) & 0xffffffff;
8330 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8334 neon_bits_same_in_bytes (unsigned imm
)
8336 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8337 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8338 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8339 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8342 /* For immediate of above form, return 0bABCD. */
8345 neon_squash_bits (unsigned imm
)
8347 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8348 | ((imm
& 0x01000000) >> 21);
8351 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8354 neon_qfloat_bits (unsigned imm
)
8356 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8359 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8360 the instruction. *OP is passed as the initial value of the op field, and
8361 may be set to a different value depending on the constant (i.e.
8362 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8363 MVN). If the immediate looks like a repeated pattern then also
8364 try smaller element sizes. */
8367 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8368 unsigned *immbits
, int *op
, int size
,
8369 enum neon_el_type type
)
8371 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8373 if (type
== NT_float
&& !float_p
)
8376 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8378 if (size
!= 32 || *op
== 1)
8380 *immbits
= neon_qfloat_bits (immlo
);
8386 if (neon_bits_same_in_bytes (immhi
)
8387 && neon_bits_same_in_bytes (immlo
))
8391 *immbits
= (neon_squash_bits (immhi
) << 4)
8392 | neon_squash_bits (immlo
);
8403 if (immlo
== (immlo
& 0x000000ff))
8408 else if (immlo
== (immlo
& 0x0000ff00))
8410 *immbits
= immlo
>> 8;
8413 else if (immlo
== (immlo
& 0x00ff0000))
8415 *immbits
= immlo
>> 16;
8418 else if (immlo
== (immlo
& 0xff000000))
8420 *immbits
= immlo
>> 24;
8423 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8425 *immbits
= (immlo
>> 8) & 0xff;
8428 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8430 *immbits
= (immlo
>> 16) & 0xff;
8434 if ((immlo
& 0xffff) != (immlo
>> 16))
8441 if (immlo
== (immlo
& 0x000000ff))
8446 else if (immlo
== (immlo
& 0x0000ff00))
8448 *immbits
= immlo
>> 8;
8452 if ((immlo
& 0xff) != (immlo
>> 8))
8457 if (immlo
== (immlo
& 0x000000ff))
8459 /* Don't allow MVN with 8-bit immediate. */
8469 #if defined BFD_HOST_64_BIT
8470 /* Returns TRUE if double precision value V may be cast
8471 to single precision without loss of accuracy. */
8474 is_double_a_single (bfd_int64_t v
)
8476 int exp
= (int)((v
>> 52) & 0x7FF);
8477 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8479 return (exp
== 0 || exp
== 0x7FF
8480 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8481 && (mantissa
& 0x1FFFFFFFl
) == 0;
8484 /* Returns a double precision value casted to single precision
8485 (ignoring the least significant bits in exponent and mantissa). */
8488 double_to_single (bfd_int64_t v
)
8490 int sign
= (int) ((v
>> 63) & 1l);
8491 int exp
= (int) ((v
>> 52) & 0x7FF);
8492 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8498 exp
= exp
- 1023 + 127;
8507 /* No denormalized numbers. */
8513 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8515 #endif /* BFD_HOST_64_BIT */
8524 static void do_vfp_nsyn_opcode (const char *);
8526 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8527 Determine whether it can be performed with a move instruction; if
8528 it can, convert inst.instruction to that move instruction and
8529 return TRUE; if it can't, convert inst.instruction to a literal-pool
8530 load and return FALSE. If this is not a valid thing to do in the
8531 current context, set inst.error and return TRUE.
8533 inst.operands[i] describes the destination register. */
8536 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8539 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8540 bfd_boolean arm_p
= (t
== CONST_ARM
);
8543 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8547 if ((inst
.instruction
& tbit
) == 0)
8549 inst
.error
= _("invalid pseudo operation");
8553 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8554 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8555 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8557 inst
.error
= _("constant expression expected");
8561 if (inst
.relocs
[0].exp
.X_op
== O_constant
8562 || inst
.relocs
[0].exp
.X_op
== O_big
)
8564 #if defined BFD_HOST_64_BIT
8569 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8571 LITTLENUM_TYPE w
[X_PRECISION
];
8574 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8576 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8578 /* FIXME: Should we check words w[2..5] ? */
8583 #if defined BFD_HOST_64_BIT
8585 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8586 << LITTLENUM_NUMBER_OF_BITS
)
8587 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8588 << LITTLENUM_NUMBER_OF_BITS
)
8589 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8590 << LITTLENUM_NUMBER_OF_BITS
)
8591 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8593 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8594 | (l
[0] & LITTLENUM_MASK
);
8598 v
= inst
.relocs
[0].exp
.X_add_number
;
8600 if (!inst
.operands
[i
].issingle
)
8604 /* LDR should not use lead in a flag-setting instruction being
8605 chosen so we do not check whether movs can be used. */
8607 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8608 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8609 && inst
.operands
[i
].reg
!= 13
8610 && inst
.operands
[i
].reg
!= 15)
8612 /* Check if on thumb2 it can be done with a mov.w, mvn or
8613 movw instruction. */
8614 unsigned int newimm
;
8615 bfd_boolean isNegated
;
8617 newimm
= encode_thumb32_immediate (v
);
8618 if (newimm
!= (unsigned int) FAIL
)
8622 newimm
= encode_thumb32_immediate (~v
);
8623 if (newimm
!= (unsigned int) FAIL
)
8627 /* The number can be loaded with a mov.w or mvn
8629 if (newimm
!= (unsigned int) FAIL
8630 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8632 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8633 | (inst
.operands
[i
].reg
<< 8));
8634 /* Change to MOVN. */
8635 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8636 inst
.instruction
|= (newimm
& 0x800) << 15;
8637 inst
.instruction
|= (newimm
& 0x700) << 4;
8638 inst
.instruction
|= (newimm
& 0x0ff);
8641 /* The number can be loaded with a movw instruction. */
8642 else if ((v
& ~0xFFFF) == 0
8643 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8645 int imm
= v
& 0xFFFF;
8647 inst
.instruction
= 0xf2400000; /* MOVW. */
8648 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8649 inst
.instruction
|= (imm
& 0xf000) << 4;
8650 inst
.instruction
|= (imm
& 0x0800) << 15;
8651 inst
.instruction
|= (imm
& 0x0700) << 4;
8652 inst
.instruction
|= (imm
& 0x00ff);
8659 int value
= encode_arm_immediate (v
);
8663 /* This can be done with a mov instruction. */
8664 inst
.instruction
&= LITERAL_MASK
;
8665 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8666 inst
.instruction
|= value
& 0xfff;
8670 value
= encode_arm_immediate (~ v
);
8673 /* This can be done with a mvn instruction. */
8674 inst
.instruction
&= LITERAL_MASK
;
8675 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8676 inst
.instruction
|= value
& 0xfff;
8680 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8683 unsigned immbits
= 0;
8684 unsigned immlo
= inst
.operands
[1].imm
;
8685 unsigned immhi
= inst
.operands
[1].regisimm
8686 ? inst
.operands
[1].reg
8687 : inst
.relocs
[0].exp
.X_unsigned
8689 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8690 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8691 &op
, 64, NT_invtype
);
8695 neon_invert_size (&immlo
, &immhi
, 64);
8697 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8698 &op
, 64, NT_invtype
);
8703 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8709 /* Fill other bits in vmov encoding for both thumb and arm. */
8711 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8713 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8714 neon_write_immbits (immbits
);
8722 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8723 if (inst
.operands
[i
].issingle
8724 && is_quarter_float (inst
.operands
[1].imm
)
8725 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8727 inst
.operands
[1].imm
=
8728 neon_qfloat_bits (v
);
8729 do_vfp_nsyn_opcode ("fconsts");
8733 /* If our host does not support a 64-bit type then we cannot perform
8734 the following optimization. This mean that there will be a
8735 discrepancy between the output produced by an assembler built for
8736 a 32-bit-only host and the output produced from a 64-bit host, but
8737 this cannot be helped. */
8738 #if defined BFD_HOST_64_BIT
8739 else if (!inst
.operands
[1].issingle
8740 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8742 if (is_double_a_single (v
)
8743 && is_quarter_float (double_to_single (v
)))
8745 inst
.operands
[1].imm
=
8746 neon_qfloat_bits (double_to_single (v
));
8747 do_vfp_nsyn_opcode ("fconstd");
8755 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8756 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8759 inst
.operands
[1].reg
= REG_PC
;
8760 inst
.operands
[1].isreg
= 1;
8761 inst
.operands
[1].preind
= 1;
8762 inst
.relocs
[0].pc_rel
= 1;
8763 inst
.relocs
[0].type
= (thumb_p
8764 ? BFD_RELOC_ARM_THUMB_OFFSET
8766 ? BFD_RELOC_ARM_HWLITERAL
8767 : BFD_RELOC_ARM_LITERAL
));
8771 /* inst.operands[i] was set up by parse_address. Encode it into an
8772 ARM-format instruction. Reject all forms which cannot be encoded
8773 into a coprocessor load/store instruction. If wb_ok is false,
8774 reject use of writeback; if unind_ok is false, reject use of
8775 unindexed addressing. If reloc_override is not 0, use it instead
8776 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8777 (in which case it is preserved). */
8780 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8782 if (!inst
.operands
[i
].isreg
)
8785 if (! inst
.operands
[0].isvec
)
8787 inst
.error
= _("invalid co-processor operand");
8790 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8794 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8796 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8798 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8800 gas_assert (!inst
.operands
[i
].writeback
);
8803 inst
.error
= _("instruction does not support unindexed addressing");
8806 inst
.instruction
|= inst
.operands
[i
].imm
;
8807 inst
.instruction
|= INDEX_UP
;
8811 if (inst
.operands
[i
].preind
)
8812 inst
.instruction
|= PRE_INDEX
;
8814 if (inst
.operands
[i
].writeback
)
8816 if (inst
.operands
[i
].reg
== REG_PC
)
8818 inst
.error
= _("pc may not be used with write-back");
8823 inst
.error
= _("instruction does not support writeback");
8826 inst
.instruction
|= WRITE_BACK
;
8830 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8831 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8832 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8833 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8836 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8838 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8841 /* Prefer + for zero encoded value. */
8842 if (!inst
.operands
[i
].negative
)
8843 inst
.instruction
|= INDEX_UP
;
8848 /* Functions for instruction encoding, sorted by sub-architecture.
8849 First some generics; their names are taken from the conventional
8850 bit positions for register arguments in ARM format instructions. */
8860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8866 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8873 inst
.instruction
|= inst
.operands
[1].reg
;
8879 inst
.instruction
|= inst
.operands
[0].reg
;
8880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8887 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8893 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8894 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8900 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8901 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8905 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8907 if (ARM_CPU_IS_ANY (cpu_variant
))
8909 as_tsktsk ("%s", msg
);
8912 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8924 unsigned Rn
= inst
.operands
[2].reg
;
8925 /* Enforce restrictions on SWP instruction. */
8926 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8928 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8929 _("Rn must not overlap other operands"));
8931 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8933 if (!check_obsolete (&arm_ext_v8
,
8934 _("swp{b} use is obsoleted for ARMv8 and later"))
8935 && warn_on_deprecated
8936 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8937 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8941 inst
.instruction
|= inst
.operands
[1].reg
;
8942 inst
.instruction
|= Rn
<< 16;
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8950 inst
.instruction
|= inst
.operands
[2].reg
;
8956 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8957 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8958 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8959 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8961 inst
.instruction
|= inst
.operands
[0].reg
;
8962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8963 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8969 inst
.instruction
|= inst
.operands
[0].imm
;
8975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8976 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8979 /* ARM instructions, in alphabetical order by function name (except
8980 that wrapper functions appear immediately after the function they
8983 /* This is a pseudo-op of the form "adr rd, label" to be converted
8984 into a relative address of the form "add rd, pc, #label-.-8". */
8989 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8991 /* Frag hacking will turn this into a sub instruction if the offset turns
8992 out to be negative. */
8993 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
8994 inst
.relocs
[0].pc_rel
= 1;
8995 inst
.relocs
[0].exp
.X_add_number
-= 8;
8997 if (support_interwork
8998 && inst
.relocs
[0].exp
.X_op
== O_symbol
8999 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9000 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9001 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9002 inst
.relocs
[0].exp
.X_add_number
|= 1;
9005 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9006 into a relative address of the form:
9007 add rd, pc, #low(label-.-8)"
9008 add rd, rd, #high(label-.-8)" */
9013 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9015 /* Frag hacking will turn this into a sub instruction if the offset turns
9016 out to be negative. */
9017 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9018 inst
.relocs
[0].pc_rel
= 1;
9019 inst
.size
= INSN_SIZE
* 2;
9020 inst
.relocs
[0].exp
.X_add_number
-= 8;
9022 if (support_interwork
9023 && inst
.relocs
[0].exp
.X_op
== O_symbol
9024 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9025 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9026 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9027 inst
.relocs
[0].exp
.X_add_number
|= 1;
9033 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9034 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9036 if (!inst
.operands
[1].present
)
9037 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9039 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9040 encode_arm_shifter_operand (2);
9046 if (inst
.operands
[0].present
)
9047 inst
.instruction
|= inst
.operands
[0].imm
;
9049 inst
.instruction
|= 0xf;
9055 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9056 constraint (msb
> 32, _("bit-field extends past end of register"));
9057 /* The instruction encoding stores the LSB and MSB,
9058 not the LSB and width. */
9059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9060 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9061 inst
.instruction
|= (msb
- 1) << 16;
9069 /* #0 in second position is alternative syntax for bfc, which is
9070 the same instruction but with REG_PC in the Rm field. */
9071 if (!inst
.operands
[1].isreg
)
9072 inst
.operands
[1].reg
= REG_PC
;
9074 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9075 constraint (msb
> 32, _("bit-field extends past end of register"));
9076 /* The instruction encoding stores the LSB and MSB,
9077 not the LSB and width. */
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 inst
.instruction
|= inst
.operands
[1].reg
;
9080 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9081 inst
.instruction
|= (msb
- 1) << 16;
9087 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9088 _("bit-field extends past end of register"));
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9090 inst
.instruction
|= inst
.operands
[1].reg
;
9091 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9092 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9095 /* ARM V5 breakpoint instruction (argument parse)
9096 BKPT <16 bit unsigned immediate>
9097 Instruction is not conditional.
9098 The bit pattern given in insns[] has the COND_ALWAYS condition,
9099 and it is an error if the caller tried to override that. */
9104 /* Top 12 of 16 bits to bits 19:8. */
9105 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9107 /* Bottom 4 of 16 bits to bits 3:0. */
9108 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9112 encode_branch (int default_reloc
)
9114 if (inst
.operands
[0].hasreloc
)
9116 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9117 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9118 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9119 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9120 ? BFD_RELOC_ARM_PLT32
9121 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9124 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9125 inst
.relocs
[0].pc_rel
= 1;
9132 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9133 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9136 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9143 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9145 if (inst
.cond
== COND_ALWAYS
)
9146 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9148 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9152 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9155 /* ARM V5 branch-link-exchange instruction (argument parse)
9156 BLX <target_addr> ie BLX(1)
9157 BLX{<condition>} <Rm> ie BLX(2)
9158 Unfortunately, there are two different opcodes for this mnemonic.
9159 So, the insns[].value is not used, and the code here zaps values
9160 into inst.instruction.
9161 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9166 if (inst
.operands
[0].isreg
)
9168 /* Arg is a register; the opcode provided by insns[] is correct.
9169 It is not illegal to do "blx pc", just useless. */
9170 if (inst
.operands
[0].reg
== REG_PC
)
9171 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9173 inst
.instruction
|= inst
.operands
[0].reg
;
9177 /* Arg is an address; this instruction cannot be executed
9178 conditionally, and the opcode must be adjusted.
9179 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9180 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9181 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9182 inst
.instruction
= 0xfa000000;
9183 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9190 bfd_boolean want_reloc
;
9192 if (inst
.operands
[0].reg
== REG_PC
)
9193 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9195 inst
.instruction
|= inst
.operands
[0].reg
;
9196 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9197 it is for ARMv4t or earlier. */
9198 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9199 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9200 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9204 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9209 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9213 /* ARM v5TEJ. Jump to Jazelle code. */
9218 if (inst
.operands
[0].reg
== REG_PC
)
9219 as_tsktsk (_("use of r15 in bxj is not really useful"));
9221 inst
.instruction
|= inst
.operands
[0].reg
;
9224 /* Co-processor data operation:
9225 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9226 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9230 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9231 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9232 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9233 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9234 inst
.instruction
|= inst
.operands
[4].reg
;
9235 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9242 encode_arm_shifter_operand (1);
9245 /* Transfer between coprocessor and ARM registers.
9246 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9251 No special properties. */
9253 struct deprecated_coproc_regs_s
9260 arm_feature_set deprecated
;
9261 arm_feature_set obsoleted
;
9262 const char *dep_msg
;
9263 const char *obs_msg
;
9266 #define DEPR_ACCESS_V8 \
9267 N_("This coprocessor register access is deprecated in ARMv8")
9269 /* Table of all deprecated coprocessor registers. */
9270 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9272 {15, 0, 7, 10, 5, /* CP15DMB. */
9273 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9274 DEPR_ACCESS_V8
, NULL
},
9275 {15, 0, 7, 10, 4, /* CP15DSB. */
9276 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9277 DEPR_ACCESS_V8
, NULL
},
9278 {15, 0, 7, 5, 4, /* CP15ISB. */
9279 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9280 DEPR_ACCESS_V8
, NULL
},
9281 {14, 6, 1, 0, 0, /* TEEHBR. */
9282 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9283 DEPR_ACCESS_V8
, NULL
},
9284 {14, 6, 0, 0, 0, /* TEECR. */
9285 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9286 DEPR_ACCESS_V8
, NULL
},
9289 #undef DEPR_ACCESS_V8
9291 static const size_t deprecated_coproc_reg_count
=
9292 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9300 Rd
= inst
.operands
[2].reg
;
9303 if (inst
.instruction
== 0xee000010
9304 || inst
.instruction
== 0xfe000010)
9306 reject_bad_reg (Rd
);
9307 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9309 constraint (Rd
== REG_SP
, BAD_SP
);
9314 if (inst
.instruction
== 0xe000010)
9315 constraint (Rd
== REG_PC
, BAD_PC
);
9318 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9320 const struct deprecated_coproc_regs_s
*r
=
9321 deprecated_coproc_regs
+ i
;
9323 if (inst
.operands
[0].reg
== r
->cp
9324 && inst
.operands
[1].imm
== r
->opc1
9325 && inst
.operands
[3].reg
== r
->crn
9326 && inst
.operands
[4].reg
== r
->crm
9327 && inst
.operands
[5].imm
== r
->opc2
)
9329 if (! ARM_CPU_IS_ANY (cpu_variant
)
9330 && warn_on_deprecated
9331 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9332 as_tsktsk ("%s", r
->dep_msg
);
9336 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9337 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9338 inst
.instruction
|= Rd
<< 12;
9339 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9340 inst
.instruction
|= inst
.operands
[4].reg
;
9341 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9344 /* Transfer between coprocessor register and pair of ARM registers.
9345 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9350 Two XScale instructions are special cases of these:
9352 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9353 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9355 Result unpredictable if Rd or Rn is R15. */
9362 Rd
= inst
.operands
[2].reg
;
9363 Rn
= inst
.operands
[3].reg
;
9367 reject_bad_reg (Rd
);
9368 reject_bad_reg (Rn
);
9372 constraint (Rd
== REG_PC
, BAD_PC
);
9373 constraint (Rn
== REG_PC
, BAD_PC
);
9376 /* Only check the MRRC{2} variants. */
9377 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9379 /* If Rd == Rn, error that the operation is
9380 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9381 constraint (Rd
== Rn
, BAD_OVERLAP
);
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9385 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9386 inst
.instruction
|= Rd
<< 12;
9387 inst
.instruction
|= Rn
<< 16;
9388 inst
.instruction
|= inst
.operands
[4].reg
;
9394 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9395 if (inst
.operands
[1].present
)
9397 inst
.instruction
|= CPSI_MMOD
;
9398 inst
.instruction
|= inst
.operands
[1].imm
;
9405 inst
.instruction
|= inst
.operands
[0].imm
;
9411 unsigned Rd
, Rn
, Rm
;
9413 Rd
= inst
.operands
[0].reg
;
9414 Rn
= (inst
.operands
[1].present
9415 ? inst
.operands
[1].reg
: Rd
);
9416 Rm
= inst
.operands
[2].reg
;
9418 constraint ((Rd
== REG_PC
), BAD_PC
);
9419 constraint ((Rn
== REG_PC
), BAD_PC
);
9420 constraint ((Rm
== REG_PC
), BAD_PC
);
9422 inst
.instruction
|= Rd
<< 16;
9423 inst
.instruction
|= Rn
<< 0;
9424 inst
.instruction
|= Rm
<< 8;
9430 /* There is no IT instruction in ARM mode. We
9431 process it to do the validation as if in
9432 thumb mode, just in case the code gets
9433 assembled for thumb using the unified syntax. */
9438 set_pred_insn_type (IT_INSN
);
9439 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9440 now_pred
.cc
= inst
.operands
[0].imm
;
9444 /* If there is only one register in the register list,
9445 then return its register number. Otherwise return -1. */
9447 only_one_reg_in_list (int range
)
9449 int i
= ffs (range
) - 1;
9450 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9454 encode_ldmstm(int from_push_pop_mnem
)
9456 int base_reg
= inst
.operands
[0].reg
;
9457 int range
= inst
.operands
[1].imm
;
9460 inst
.instruction
|= base_reg
<< 16;
9461 inst
.instruction
|= range
;
9463 if (inst
.operands
[1].writeback
)
9464 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9466 if (inst
.operands
[0].writeback
)
9468 inst
.instruction
|= WRITE_BACK
;
9469 /* Check for unpredictable uses of writeback. */
9470 if (inst
.instruction
& LOAD_BIT
)
9472 /* Not allowed in LDM type 2. */
9473 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9474 && ((range
& (1 << REG_PC
)) == 0))
9475 as_warn (_("writeback of base register is UNPREDICTABLE"));
9476 /* Only allowed if base reg not in list for other types. */
9477 else if (range
& (1 << base_reg
))
9478 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9482 /* Not allowed for type 2. */
9483 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9484 as_warn (_("writeback of base register is UNPREDICTABLE"));
9485 /* Only allowed if base reg not in list, or first in list. */
9486 else if ((range
& (1 << base_reg
))
9487 && (range
& ((1 << base_reg
) - 1)))
9488 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9492 /* If PUSH/POP has only one register, then use the A2 encoding. */
9493 one_reg
= only_one_reg_in_list (range
);
9494 if (from_push_pop_mnem
&& one_reg
>= 0)
9496 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9498 if (is_push
&& one_reg
== 13 /* SP */)
9499 /* PR 22483: The A2 encoding cannot be used when
9500 pushing the stack pointer as this is UNPREDICTABLE. */
9503 inst
.instruction
&= A_COND_MASK
;
9504 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9505 inst
.instruction
|= one_reg
<< 12;
9512 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9515 /* ARMv5TE load-consecutive (argument parse)
9524 constraint (inst
.operands
[0].reg
% 2 != 0,
9525 _("first transfer register must be even"));
9526 constraint (inst
.operands
[1].present
9527 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9528 _("can only transfer two consecutive registers"));
9529 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9530 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9532 if (!inst
.operands
[1].present
)
9533 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9535 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9536 register and the first register written; we have to diagnose
9537 overlap between the base and the second register written here. */
9539 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9540 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9541 as_warn (_("base register written back, and overlaps "
9542 "second transfer register"));
9544 if (!(inst
.instruction
& V4_STR_BIT
))
9546 /* For an index-register load, the index register must not overlap the
9547 destination (even if not write-back). */
9548 if (inst
.operands
[2].immisreg
9549 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9550 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9551 as_warn (_("index register overlaps transfer register"));
9553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9554 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9560 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9561 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9562 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9563 || inst
.operands
[1].negative
9564 /* This can arise if the programmer has written
9566 or if they have mistakenly used a register name as the last
9569 It is very difficult to distinguish between these two cases
9570 because "rX" might actually be a label. ie the register
9571 name has been occluded by a symbol of the same name. So we
9572 just generate a general 'bad addressing mode' type error
9573 message and leave it up to the programmer to discover the
9574 true cause and fix their mistake. */
9575 || (inst
.operands
[1].reg
== REG_PC
),
9578 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9579 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9580 _("offset must be zero in ARM encoding"));
9582 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9585 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9586 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9592 constraint (inst
.operands
[0].reg
% 2 != 0,
9593 _("even register required"));
9594 constraint (inst
.operands
[1].present
9595 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9596 _("can only load two consecutive registers"));
9597 /* If op 1 were present and equal to PC, this function wouldn't
9598 have been called in the first place. */
9599 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9602 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9605 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9606 which is not a multiple of four is UNPREDICTABLE. */
9608 check_ldr_r15_aligned (void)
9610 constraint (!(inst
.operands
[1].immisreg
)
9611 && (inst
.operands
[0].reg
== REG_PC
9612 && inst
.operands
[1].reg
== REG_PC
9613 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9614 _("ldr to register 15 must be 4-byte aligned"));
9620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9621 if (!inst
.operands
[1].isreg
)
9622 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9624 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9625 check_ldr_r15_aligned ();
9631 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9633 if (inst
.operands
[1].preind
)
9635 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9636 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9637 _("this instruction requires a post-indexed address"));
9639 inst
.operands
[1].preind
= 0;
9640 inst
.operands
[1].postind
= 1;
9641 inst
.operands
[1].writeback
= 1;
9643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9644 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9647 /* Halfword and signed-byte load/store operations. */
9652 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9654 if (!inst
.operands
[1].isreg
)
9655 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9657 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9663 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9665 if (inst
.operands
[1].preind
)
9667 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9668 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9669 _("this instruction requires a post-indexed address"));
9671 inst
.operands
[1].preind
= 0;
9672 inst
.operands
[1].postind
= 1;
9673 inst
.operands
[1].writeback
= 1;
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9679 /* Co-processor register load/store.
9680 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9684 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9685 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9686 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9692 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9693 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9694 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9695 && !(inst
.instruction
& 0x00400000))
9696 as_tsktsk (_("Rd and Rm should be different in mla"));
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9699 inst
.instruction
|= inst
.operands
[1].reg
;
9700 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9701 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9707 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9708 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9711 encode_arm_shifter_operand (1);
9714 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9721 top
= (inst
.instruction
& 0x00400000) != 0;
9722 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9723 _(":lower16: not allowed in this instruction"));
9724 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9725 _(":upper16: not allowed in this instruction"));
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9727 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9729 imm
= inst
.relocs
[0].exp
.X_add_number
;
9730 /* The value is in two pieces: 0:11, 16:19. */
9731 inst
.instruction
|= (imm
& 0x00000fff);
9732 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9737 do_vfp_nsyn_mrs (void)
9739 if (inst
.operands
[0].isvec
)
9741 if (inst
.operands
[1].reg
!= 1)
9742 first_error (_("operand 1 must be FPSCR"));
9743 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9744 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9745 do_vfp_nsyn_opcode ("fmstat");
9747 else if (inst
.operands
[1].isvec
)
9748 do_vfp_nsyn_opcode ("fmrx");
9756 do_vfp_nsyn_msr (void)
9758 if (inst
.operands
[0].isvec
)
9759 do_vfp_nsyn_opcode ("fmxr");
9769 unsigned Rt
= inst
.operands
[0].reg
;
9771 if (thumb_mode
&& Rt
== REG_SP
)
9773 inst
.error
= BAD_SP
;
9777 /* MVFR2 is only valid at ARMv8-A. */
9778 if (inst
.operands
[1].reg
== 5)
9779 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9782 /* APSR_ sets isvec. All other refs to PC are illegal. */
9783 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9785 inst
.error
= BAD_PC
;
9789 /* If we get through parsing the register name, we just insert the number
9790 generated into the instruction without further validation. */
9791 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9792 inst
.instruction
|= (Rt
<< 12);
9798 unsigned Rt
= inst
.operands
[1].reg
;
9801 reject_bad_reg (Rt
);
9802 else if (Rt
== REG_PC
)
9804 inst
.error
= BAD_PC
;
9808 /* MVFR2 is only valid for ARMv8-A. */
9809 if (inst
.operands
[0].reg
== 5)
9810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9813 /* If we get through parsing the register name, we just insert the number
9814 generated into the instruction without further validation. */
9815 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9816 inst
.instruction
|= (Rt
<< 12);
9824 if (do_vfp_nsyn_mrs () == SUCCESS
)
9827 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9830 if (inst
.operands
[1].isreg
)
9832 br
= inst
.operands
[1].reg
;
9833 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9834 as_bad (_("bad register for mrs"));
9838 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9839 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9841 _("'APSR', 'CPSR' or 'SPSR' expected"));
9842 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9845 inst
.instruction
|= br
;
9848 /* Two possible forms:
9849 "{C|S}PSR_<field>, Rm",
9850 "{C|S}PSR_f, #expression". */
9855 if (do_vfp_nsyn_msr () == SUCCESS
)
9858 inst
.instruction
|= inst
.operands
[0].imm
;
9859 if (inst
.operands
[1].isreg
)
9860 inst
.instruction
|= inst
.operands
[1].reg
;
9863 inst
.instruction
|= INST_IMMEDIATE
;
9864 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9865 inst
.relocs
[0].pc_rel
= 0;
9872 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9874 if (!inst
.operands
[2].present
)
9875 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9876 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9877 inst
.instruction
|= inst
.operands
[1].reg
;
9878 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9880 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9881 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9882 as_tsktsk (_("Rd and Rm should be different in mul"));
9885 /* Long Multiply Parser
9886 UMULL RdLo, RdHi, Rm, Rs
9887 SMULL RdLo, RdHi, Rm, Rs
9888 UMLAL RdLo, RdHi, Rm, Rs
9889 SMLAL RdLo, RdHi, Rm, Rs. */
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9896 inst
.instruction
|= inst
.operands
[2].reg
;
9897 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9899 /* rdhi and rdlo must be different. */
9900 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9901 as_tsktsk (_("rdhi and rdlo must be different"));
9903 /* rdhi, rdlo and rm must all be different before armv6. */
9904 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9905 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9906 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9907 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9913 if (inst
.operands
[0].present
9914 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9916 /* Architectural NOP hints are CPSR sets with no bits selected. */
9917 inst
.instruction
&= 0xf0000000;
9918 inst
.instruction
|= 0x0320f000;
9919 if (inst
.operands
[0].present
)
9920 inst
.instruction
|= inst
.operands
[0].imm
;
9924 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9925 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9926 Condition defaults to COND_ALWAYS.
9927 Error if Rd, Rn or Rm are R15. */
9932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9933 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9934 inst
.instruction
|= inst
.operands
[2].reg
;
9935 if (inst
.operands
[3].present
)
9936 encode_arm_shift (3);
9939 /* ARM V6 PKHTB (Argument Parse). */
9944 if (!inst
.operands
[3].present
)
9946 /* If the shift specifier is omitted, turn the instruction
9947 into pkhbt rd, rm, rn. */
9948 inst
.instruction
&= 0xfff00010;
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 inst
.instruction
|= inst
.operands
[1].reg
;
9951 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9958 encode_arm_shift (3);
9962 /* ARMv5TE: Preload-Cache
9963 MP Extensions: Preload for write
9967 Syntactically, like LDR with B=1, W=0, L=1. */
9972 constraint (!inst
.operands
[0].isreg
,
9973 _("'[' expected after PLD mnemonic"));
9974 constraint (inst
.operands
[0].postind
,
9975 _("post-indexed expression used in preload instruction"));
9976 constraint (inst
.operands
[0].writeback
,
9977 _("writeback used in preload instruction"));
9978 constraint (!inst
.operands
[0].preind
,
9979 _("unindexed addressing used in preload instruction"));
9980 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9983 /* ARMv7: PLI <addr_mode> */
9987 constraint (!inst
.operands
[0].isreg
,
9988 _("'[' expected after PLI mnemonic"));
9989 constraint (inst
.operands
[0].postind
,
9990 _("post-indexed expression used in preload instruction"));
9991 constraint (inst
.operands
[0].writeback
,
9992 _("writeback used in preload instruction"));
9993 constraint (!inst
.operands
[0].preind
,
9994 _("unindexed addressing used in preload instruction"));
9995 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9996 inst
.instruction
&= ~PRE_INDEX
;
10002 constraint (inst
.operands
[0].writeback
,
10003 _("push/pop do not support {reglist}^"));
10004 inst
.operands
[1] = inst
.operands
[0];
10005 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10006 inst
.operands
[0].isreg
= 1;
10007 inst
.operands
[0].writeback
= 1;
10008 inst
.operands
[0].reg
= REG_SP
;
10009 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10012 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10013 word at the specified address and the following word
10015 Unconditionally executed.
10016 Error if Rn is R15. */
10021 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10022 if (inst
.operands
[0].writeback
)
10023 inst
.instruction
|= WRITE_BACK
;
10026 /* ARM V6 ssat (argument parse). */
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10032 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10033 inst
.instruction
|= inst
.operands
[2].reg
;
10035 if (inst
.operands
[3].present
)
10036 encode_arm_shift (3);
10039 /* ARM V6 usat (argument parse). */
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10045 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10046 inst
.instruction
|= inst
.operands
[2].reg
;
10048 if (inst
.operands
[3].present
)
10049 encode_arm_shift (3);
10052 /* ARM V6 ssat16 (argument parse). */
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10058 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10059 inst
.instruction
|= inst
.operands
[2].reg
;
10065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10066 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10067 inst
.instruction
|= inst
.operands
[2].reg
;
10070 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10071 preserving the other bits.
10073 setend <endian_specifier>, where <endian_specifier> is either
10079 if (warn_on_deprecated
10080 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10081 as_tsktsk (_("setend use is deprecated for ARMv8"));
10083 if (inst
.operands
[0].imm
)
10084 inst
.instruction
|= 0x200;
10090 unsigned int Rm
= (inst
.operands
[1].present
10091 ? inst
.operands
[1].reg
10092 : inst
.operands
[0].reg
);
10094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10095 inst
.instruction
|= Rm
;
10096 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10098 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10099 inst
.instruction
|= SHIFT_BY_REG
;
10100 /* PR 12854: Error on extraneous shifts. */
10101 constraint (inst
.operands
[2].shifted
,
10102 _("extraneous shift as part of operand to shift insn"));
10105 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10111 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10112 inst
.relocs
[0].pc_rel
= 0;
10118 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10119 inst
.relocs
[0].pc_rel
= 0;
10125 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10126 inst
.relocs
[0].pc_rel
= 0;
10132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10133 _("selected processor does not support SETPAN instruction"));
10135 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10141 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10142 _("selected processor does not support SETPAN instruction"));
10144 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10147 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10148 SMLAxy{cond} Rd,Rm,Rs,Rn
10149 SMLAWy{cond} Rd,Rm,Rs,Rn
10150 Error if any register is R15. */
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10156 inst
.instruction
|= inst
.operands
[1].reg
;
10157 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10158 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10161 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10162 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10163 Error if any register is R15.
10164 Warning if Rdlo == Rdhi. */
10169 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10170 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10171 inst
.instruction
|= inst
.operands
[2].reg
;
10172 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10174 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10175 as_tsktsk (_("rdhi and rdlo must be different"));
10178 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10179 SMULxy{cond} Rd,Rm,Rs
10180 Error if any register is R15. */
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10186 inst
.instruction
|= inst
.operands
[1].reg
;
10187 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10190 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10191 the same for both ARM and Thumb-2. */
10198 if (inst
.operands
[0].present
)
10200 reg
= inst
.operands
[0].reg
;
10201 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10206 inst
.instruction
|= reg
<< 16;
10207 inst
.instruction
|= inst
.operands
[1].imm
;
10208 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10209 inst
.instruction
|= WRITE_BACK
;
10212 /* ARM V6 strex (argument parse). */
10217 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10218 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10219 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10220 || inst
.operands
[2].negative
10221 /* See comment in do_ldrex(). */
10222 || (inst
.operands
[2].reg
== REG_PC
),
10225 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10226 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10228 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10229 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10230 _("offset must be zero in ARM encoding"));
10232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10233 inst
.instruction
|= inst
.operands
[1].reg
;
10234 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10235 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10239 do_t_strexbh (void)
10241 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10242 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10243 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10244 || inst
.operands
[2].negative
,
10247 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10248 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10256 constraint (inst
.operands
[1].reg
% 2 != 0,
10257 _("even register required"));
10258 constraint (inst
.operands
[2].present
10259 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10260 _("can only store two consecutive registers"));
10261 /* If op 2 were present and equal to PC, this function wouldn't
10262 have been called in the first place. */
10263 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10265 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10266 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10267 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10271 inst
.instruction
|= inst
.operands
[1].reg
;
10272 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10279 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10280 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10288 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10289 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10294 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10295 extends it to 32-bits, and adds the result to a value in another
10296 register. You can specify a rotation by 0, 8, 16, or 24 bits
10297 before extracting the 16-bit value.
10298 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10299 Condition defaults to COND_ALWAYS.
10300 Error if any register uses R15. */
10305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10307 inst
.instruction
|= inst
.operands
[2].reg
;
10308 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10313 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10314 Condition defaults to COND_ALWAYS.
10315 Error if any register uses R15. */
10320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10321 inst
.instruction
|= inst
.operands
[1].reg
;
10322 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10325 /* VFP instructions. In a logical order: SP variant first, monad
10326 before dyad, arithmetic then move then load/store. */
10329 do_vfp_sp_monadic (void)
10331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10332 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10335 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10336 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10340 do_vfp_sp_dyadic (void)
10342 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10344 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10348 do_vfp_sp_compare_z (void)
10350 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10354 do_vfp_dp_sp_cvt (void)
10356 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10357 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10361 do_vfp_sp_dp_cvt (void)
10363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10364 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10368 do_vfp_reg_from_sp (void)
10370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10371 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10375 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10379 do_vfp_reg2_from_sp2 (void)
10381 constraint (inst
.operands
[2].imm
!= 2,
10382 _("only two consecutive VFP SP registers allowed here"));
10383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10384 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10385 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10389 do_vfp_sp_from_reg (void)
10391 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10392 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10395 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10396 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10400 do_vfp_sp2_from_reg2 (void)
10402 constraint (inst
.operands
[0].imm
!= 2,
10403 _("only two consecutive VFP SP registers allowed here"));
10404 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10405 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10406 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10410 do_vfp_sp_ldst (void)
10412 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10413 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10417 do_vfp_dp_ldst (void)
10419 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10420 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10425 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10427 if (inst
.operands
[0].writeback
)
10428 inst
.instruction
|= WRITE_BACK
;
10430 constraint (ldstm_type
!= VFP_LDSTMIA
,
10431 _("this addressing mode requires base-register writeback"));
10432 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10433 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10434 inst
.instruction
|= inst
.operands
[1].imm
;
10438 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10442 if (inst
.operands
[0].writeback
)
10443 inst
.instruction
|= WRITE_BACK
;
10445 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10446 _("this addressing mode requires base-register writeback"));
10448 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10449 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10451 count
= inst
.operands
[1].imm
<< 1;
10452 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10455 inst
.instruction
|= count
;
10459 do_vfp_sp_ldstmia (void)
10461 vfp_sp_ldstm (VFP_LDSTMIA
);
10465 do_vfp_sp_ldstmdb (void)
10467 vfp_sp_ldstm (VFP_LDSTMDB
);
10471 do_vfp_dp_ldstmia (void)
10473 vfp_dp_ldstm (VFP_LDSTMIA
);
10477 do_vfp_dp_ldstmdb (void)
10479 vfp_dp_ldstm (VFP_LDSTMDB
);
10483 do_vfp_xp_ldstmia (void)
10485 vfp_dp_ldstm (VFP_LDSTMIAX
);
10489 do_vfp_xp_ldstmdb (void)
10491 vfp_dp_ldstm (VFP_LDSTMDBX
);
10495 do_vfp_dp_rd_rm (void)
10497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10498 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10501 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10502 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10506 do_vfp_dp_rn_rd (void)
10508 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10509 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10513 do_vfp_dp_rd_rn (void)
10515 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10516 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10520 do_vfp_dp_rd_rn_rm (void)
10522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10523 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10526 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10527 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10528 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10532 do_vfp_dp_rd (void)
10534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10538 do_vfp_dp_rm_rd_rn (void)
10540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10541 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10544 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10546 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10549 /* VFPv3 instructions. */
10551 do_vfp_sp_const (void)
10553 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10554 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10555 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10559 do_vfp_dp_const (void)
10561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10562 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10563 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10567 vfp_conv (int srcsize
)
10569 int immbits
= srcsize
- inst
.operands
[1].imm
;
10571 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10573 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10574 i.e. immbits must be in range 0 - 16. */
10575 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10578 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10580 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10581 i.e. immbits must be in range 0 - 31. */
10582 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10586 inst
.instruction
|= (immbits
& 1) << 5;
10587 inst
.instruction
|= (immbits
>> 1);
10591 do_vfp_sp_conv_16 (void)
10593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10598 do_vfp_dp_conv_16 (void)
10600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10605 do_vfp_sp_conv_32 (void)
10607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10612 do_vfp_dp_conv_32 (void)
10614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10618 /* FPA instructions. Also in a logical order. */
10623 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10624 inst
.instruction
|= inst
.operands
[1].reg
;
10628 do_fpa_ldmstm (void)
10630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10631 switch (inst
.operands
[1].imm
)
10633 case 1: inst
.instruction
|= CP_T_X
; break;
10634 case 2: inst
.instruction
|= CP_T_Y
; break;
10635 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10640 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10642 /* The instruction specified "ea" or "fd", so we can only accept
10643 [Rn]{!}. The instruction does not really support stacking or
10644 unstacking, so we have to emulate these by setting appropriate
10645 bits and offsets. */
10646 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10647 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10648 _("this instruction does not support indexing"));
10650 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10651 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10653 if (!(inst
.instruction
& INDEX_UP
))
10654 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10656 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10658 inst
.operands
[2].preind
= 0;
10659 inst
.operands
[2].postind
= 1;
10663 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10666 /* iWMMXt instructions: strictly in alphabetical order. */
10669 do_iwmmxt_tandorc (void)
10671 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10675 do_iwmmxt_textrc (void)
10677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10678 inst
.instruction
|= inst
.operands
[1].imm
;
10682 do_iwmmxt_textrm (void)
10684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10685 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10686 inst
.instruction
|= inst
.operands
[2].imm
;
10690 do_iwmmxt_tinsr (void)
10692 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10693 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10694 inst
.instruction
|= inst
.operands
[2].imm
;
10698 do_iwmmxt_tmia (void)
10700 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10701 inst
.instruction
|= inst
.operands
[1].reg
;
10702 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10706 do_iwmmxt_waligni (void)
10708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10709 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10710 inst
.instruction
|= inst
.operands
[2].reg
;
10711 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10715 do_iwmmxt_wmerge (void)
10717 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10718 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10719 inst
.instruction
|= inst
.operands
[2].reg
;
10720 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10724 do_iwmmxt_wmov (void)
10726 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10728 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10729 inst
.instruction
|= inst
.operands
[1].reg
;
10733 do_iwmmxt_wldstbh (void)
10736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10738 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10740 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10741 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10745 do_iwmmxt_wldstw (void)
10747 /* RIWR_RIWC clears .isreg for a control register. */
10748 if (!inst
.operands
[0].isreg
)
10750 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10751 inst
.instruction
|= 0xf0000000;
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10755 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10759 do_iwmmxt_wldstd (void)
10761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10762 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10763 && inst
.operands
[1].immisreg
)
10765 inst
.instruction
&= ~0x1a000ff;
10766 inst
.instruction
|= (0xfU
<< 28);
10767 if (inst
.operands
[1].preind
)
10768 inst
.instruction
|= PRE_INDEX
;
10769 if (!inst
.operands
[1].negative
)
10770 inst
.instruction
|= INDEX_UP
;
10771 if (inst
.operands
[1].writeback
)
10772 inst
.instruction
|= WRITE_BACK
;
10773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10774 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10775 inst
.instruction
|= inst
.operands
[1].imm
;
10778 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10782 do_iwmmxt_wshufh (void)
10784 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10785 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10786 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10787 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10791 do_iwmmxt_wzero (void)
10793 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10794 inst
.instruction
|= inst
.operands
[0].reg
;
10795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10796 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10800 do_iwmmxt_wrwrwr_or_imm5 (void)
10802 if (inst
.operands
[2].isreg
)
10805 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10806 _("immediate operand requires iWMMXt2"));
10808 if (inst
.operands
[2].imm
== 0)
10810 switch ((inst
.instruction
>> 20) & 0xf)
10816 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10817 inst
.operands
[2].imm
= 16;
10818 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10824 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10825 inst
.operands
[2].imm
= 32;
10826 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10833 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10835 wrn
= (inst
.instruction
>> 16) & 0xf;
10836 inst
.instruction
&= 0xff0fff0f;
10837 inst
.instruction
|= wrn
;
10838 /* Bail out here; the instruction is now assembled. */
10843 /* Map 32 -> 0, etc. */
10844 inst
.operands
[2].imm
&= 0x1f;
10845 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10849 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10850 operations first, then control, shift, and load/store. */
10852 /* Insns like "foo X,Y,Z". */
10855 do_mav_triple (void)
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10858 inst
.instruction
|= inst
.operands
[1].reg
;
10859 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10862 /* Insns like "foo W,X,Y,Z".
10863 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10868 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10869 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10870 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10871 inst
.instruction
|= inst
.operands
[3].reg
;
10874 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10876 do_mav_dspsc (void)
10878 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10881 /* Maverick shift immediate instructions.
10882 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10883 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10886 do_mav_shift (void)
10888 int imm
= inst
.operands
[2].imm
;
10890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10893 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10894 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10895 Bit 4 should be 0. */
10896 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10898 inst
.instruction
|= imm
;
10901 /* XScale instructions. Also sorted arithmetic before move. */
10903 /* Xscale multiply-accumulate (argument parse)
10906 MIAxycc acc0,Rm,Rs. */
10911 inst
.instruction
|= inst
.operands
[1].reg
;
10912 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10915 /* Xscale move-accumulator-register (argument parse)
10917 MARcc acc0,RdLo,RdHi. */
10922 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10923 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10926 /* Xscale move-register-accumulator (argument parse)
10928 MRAcc RdLo,RdHi,acc0. */
10933 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10935 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10938 /* Encoding functions relevant only to Thumb. */
10940 /* inst.operands[i] is a shifted-register operand; encode
10941 it into inst.instruction in the format used by Thumb32. */
10944 encode_thumb32_shifted_operand (int i
)
10946 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10947 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10949 constraint (inst
.operands
[i
].immisreg
,
10950 _("shift by register not allowed in thumb mode"));
10951 inst
.instruction
|= inst
.operands
[i
].reg
;
10952 if (shift
== SHIFT_RRX
)
10953 inst
.instruction
|= SHIFT_ROR
<< 4;
10956 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10957 _("expression too complex"));
10959 constraint (value
> 32
10960 || (value
== 32 && (shift
== SHIFT_LSL
10961 || shift
== SHIFT_ROR
)),
10962 _("shift expression is too large"));
10966 else if (value
== 32)
10969 inst
.instruction
|= shift
<< 4;
10970 inst
.instruction
|= (value
& 0x1c) << 10;
10971 inst
.instruction
|= (value
& 0x03) << 6;
10976 /* inst.operands[i] was set up by parse_address. Encode it into a
10977 Thumb32 format load or store instruction. Reject forms that cannot
10978 be used with such instructions. If is_t is true, reject forms that
10979 cannot be used with a T instruction; if is_d is true, reject forms
10980 that cannot be used with a D instruction. If it is a store insn,
10981 reject PC in Rn. */
10984 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10986 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10988 constraint (!inst
.operands
[i
].isreg
,
10989 _("Instruction does not support =N addresses"));
10991 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10992 if (inst
.operands
[i
].immisreg
)
10994 constraint (is_pc
, BAD_PC_ADDRESSING
);
10995 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10996 constraint (inst
.operands
[i
].negative
,
10997 _("Thumb does not support negative register indexing"));
10998 constraint (inst
.operands
[i
].postind
,
10999 _("Thumb does not support register post-indexing"));
11000 constraint (inst
.operands
[i
].writeback
,
11001 _("Thumb does not support register indexing with writeback"));
11002 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11003 _("Thumb supports only LSL in shifted register indexing"));
11005 inst
.instruction
|= inst
.operands
[i
].imm
;
11006 if (inst
.operands
[i
].shifted
)
11008 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11009 _("expression too complex"));
11010 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11011 || inst
.relocs
[0].exp
.X_add_number
> 3,
11012 _("shift out of range"));
11013 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11015 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11017 else if (inst
.operands
[i
].preind
)
11019 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11020 constraint (is_t
&& inst
.operands
[i
].writeback
,
11021 _("cannot use writeback with this instruction"));
11022 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11023 BAD_PC_ADDRESSING
);
11027 inst
.instruction
|= 0x01000000;
11028 if (inst
.operands
[i
].writeback
)
11029 inst
.instruction
|= 0x00200000;
11033 inst
.instruction
|= 0x00000c00;
11034 if (inst
.operands
[i
].writeback
)
11035 inst
.instruction
|= 0x00000100;
11037 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11039 else if (inst
.operands
[i
].postind
)
11041 gas_assert (inst
.operands
[i
].writeback
);
11042 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11043 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11046 inst
.instruction
|= 0x00200000;
11048 inst
.instruction
|= 0x00000900;
11049 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11051 else /* unindexed - only for coprocessor */
11052 inst
.error
= _("instruction does not accept unindexed addressing");
11055 /* Table of Thumb instructions which exist in both 16- and 32-bit
11056 encodings (the latter only in post-V6T2 cores). The index is the
11057 value used in the insns table below. When there is more than one
11058 possible 16-bit encoding for the instruction, this table always
11060 Also contains several pseudo-instructions used during relaxation. */
11061 #define T16_32_TAB \
11062 X(_adc, 4140, eb400000), \
11063 X(_adcs, 4140, eb500000), \
11064 X(_add, 1c00, eb000000), \
11065 X(_adds, 1c00, eb100000), \
11066 X(_addi, 0000, f1000000), \
11067 X(_addis, 0000, f1100000), \
11068 X(_add_pc,000f, f20f0000), \
11069 X(_add_sp,000d, f10d0000), \
11070 X(_adr, 000f, f20f0000), \
11071 X(_and, 4000, ea000000), \
11072 X(_ands, 4000, ea100000), \
11073 X(_asr, 1000, fa40f000), \
11074 X(_asrs, 1000, fa50f000), \
11075 X(_b, e000, f000b000), \
11076 X(_bcond, d000, f0008000), \
11077 X(_bf, 0000, f040e001), \
11078 X(_bfcsel,0000, f000e001), \
11079 X(_bfx, 0000, f060e001), \
11080 X(_bfl, 0000, f000c001), \
11081 X(_bflx, 0000, f070e001), \
11082 X(_bic, 4380, ea200000), \
11083 X(_bics, 4380, ea300000), \
11084 X(_cmn, 42c0, eb100f00), \
11085 X(_cmp, 2800, ebb00f00), \
11086 X(_cpsie, b660, f3af8400), \
11087 X(_cpsid, b670, f3af8600), \
11088 X(_cpy, 4600, ea4f0000), \
11089 X(_dec_sp,80dd, f1ad0d00), \
11090 X(_dls, 0000, f040e001), \
11091 X(_eor, 4040, ea800000), \
11092 X(_eors, 4040, ea900000), \
11093 X(_inc_sp,00dd, f10d0d00), \
11094 X(_ldmia, c800, e8900000), \
11095 X(_ldr, 6800, f8500000), \
11096 X(_ldrb, 7800, f8100000), \
11097 X(_ldrh, 8800, f8300000), \
11098 X(_ldrsb, 5600, f9100000), \
11099 X(_ldrsh, 5e00, f9300000), \
11100 X(_ldr_pc,4800, f85f0000), \
11101 X(_ldr_pc2,4800, f85f0000), \
11102 X(_ldr_sp,9800, f85d0000), \
11103 X(_le, 0000, f00fc001), \
11104 X(_lsl, 0000, fa00f000), \
11105 X(_lsls, 0000, fa10f000), \
11106 X(_lsr, 0800, fa20f000), \
11107 X(_lsrs, 0800, fa30f000), \
11108 X(_mov, 2000, ea4f0000), \
11109 X(_movs, 2000, ea5f0000), \
11110 X(_mul, 4340, fb00f000), \
11111 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11112 X(_mvn, 43c0, ea6f0000), \
11113 X(_mvns, 43c0, ea7f0000), \
11114 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11115 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11116 X(_orr, 4300, ea400000), \
11117 X(_orrs, 4300, ea500000), \
11118 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11119 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11120 X(_rev, ba00, fa90f080), \
11121 X(_rev16, ba40, fa90f090), \
11122 X(_revsh, bac0, fa90f0b0), \
11123 X(_ror, 41c0, fa60f000), \
11124 X(_rors, 41c0, fa70f000), \
11125 X(_sbc, 4180, eb600000), \
11126 X(_sbcs, 4180, eb700000), \
11127 X(_stmia, c000, e8800000), \
11128 X(_str, 6000, f8400000), \
11129 X(_strb, 7000, f8000000), \
11130 X(_strh, 8000, f8200000), \
11131 X(_str_sp,9000, f84d0000), \
11132 X(_sub, 1e00, eba00000), \
11133 X(_subs, 1e00, ebb00000), \
11134 X(_subi, 8000, f1a00000), \
11135 X(_subis, 8000, f1b00000), \
11136 X(_sxtb, b240, fa4ff080), \
11137 X(_sxth, b200, fa0ff080), \
11138 X(_tst, 4200, ea100f00), \
11139 X(_uxtb, b2c0, fa5ff080), \
11140 X(_uxth, b280, fa1ff080), \
11141 X(_nop, bf00, f3af8000), \
11142 X(_yield, bf10, f3af8001), \
11143 X(_wfe, bf20, f3af8002), \
11144 X(_wfi, bf30, f3af8003), \
11145 X(_wls, 0000, f040c001), \
11146 X(_sev, bf40, f3af8004), \
11147 X(_sevl, bf50, f3af8005), \
11148 X(_udf, de00, f7f0a000)
11150 /* To catch errors in encoding functions, the codes are all offset by
11151 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11152 as 16-bit instructions. */
11153 #define X(a,b,c) T_MNEM##a
11154 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11157 #define X(a,b,c) 0x##b
11158 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11159 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11162 #define X(a,b,c) 0x##c
11163 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11164 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11165 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11169 /* Thumb instruction encoders, in alphabetical order. */
11171 /* ADDW or SUBW. */
11174 do_t_add_sub_w (void)
11178 Rd
= inst
.operands
[0].reg
;
11179 Rn
= inst
.operands
[1].reg
;
11181 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11182 is the SP-{plus,minus}-immediate form of the instruction. */
11184 constraint (Rd
== REG_PC
, BAD_PC
);
11186 reject_bad_reg (Rd
);
11188 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11189 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11192 /* Parse an add or subtract instruction. We get here with inst.instruction
11193 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11196 do_t_add_sub (void)
11200 Rd
= inst
.operands
[0].reg
;
11201 Rs
= (inst
.operands
[1].present
11202 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11203 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11206 set_pred_insn_type_last ();
11208 if (unified_syntax
)
11211 bfd_boolean narrow
;
11214 flags
= (inst
.instruction
== T_MNEM_adds
11215 || inst
.instruction
== T_MNEM_subs
);
11217 narrow
= !in_pred_block ();
11219 narrow
= in_pred_block ();
11220 if (!inst
.operands
[2].isreg
)
11224 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11225 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11227 add
= (inst
.instruction
== T_MNEM_add
11228 || inst
.instruction
== T_MNEM_adds
);
11230 if (inst
.size_req
!= 4)
11232 /* Attempt to use a narrow opcode, with relaxation if
11234 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11235 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11236 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11237 opcode
= T_MNEM_add_sp
;
11238 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11239 opcode
= T_MNEM_add_pc
;
11240 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11243 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11245 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11249 inst
.instruction
= THUMB_OP16(opcode
);
11250 inst
.instruction
|= (Rd
<< 4) | Rs
;
11251 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11252 || (inst
.relocs
[0].type
11253 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11255 if (inst
.size_req
== 2)
11256 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11258 inst
.relax
= opcode
;
11262 constraint (inst
.size_req
== 2, BAD_HIREG
);
11264 if (inst
.size_req
== 4
11265 || (inst
.size_req
!= 2 && !opcode
))
11267 constraint ((inst
.relocs
[0].type
11268 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11269 && (inst
.relocs
[0].type
11270 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11271 THUMB1_RELOC_ONLY
);
11274 constraint (add
, BAD_PC
);
11275 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11276 _("only SUBS PC, LR, #const allowed"));
11277 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11278 _("expression too complex"));
11279 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11280 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11281 _("immediate value out of range"));
11282 inst
.instruction
= T2_SUBS_PC_LR
11283 | inst
.relocs
[0].exp
.X_add_number
;
11284 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11287 else if (Rs
== REG_PC
)
11289 /* Always use addw/subw. */
11290 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11291 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11295 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11296 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11299 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11301 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11303 inst
.instruction
|= Rd
<< 8;
11304 inst
.instruction
|= Rs
<< 16;
11309 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11310 unsigned int shift
= inst
.operands
[2].shift_kind
;
11312 Rn
= inst
.operands
[2].reg
;
11313 /* See if we can do this with a 16-bit instruction. */
11314 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11316 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11321 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11322 || inst
.instruction
== T_MNEM_add
)
11324 : T_OPCODE_SUB_R3
);
11325 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11329 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11331 /* Thumb-1 cores (except v6-M) require at least one high
11332 register in a narrow non flag setting add. */
11333 if (Rd
> 7 || Rn
> 7
11334 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11335 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11342 inst
.instruction
= T_OPCODE_ADD_HI
;
11343 inst
.instruction
|= (Rd
& 8) << 4;
11344 inst
.instruction
|= (Rd
& 7);
11345 inst
.instruction
|= Rn
<< 3;
11351 constraint (Rd
== REG_PC
, BAD_PC
);
11352 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11353 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11354 constraint (Rs
== REG_PC
, BAD_PC
);
11355 reject_bad_reg (Rn
);
11357 /* If we get here, it can't be done in 16 bits. */
11358 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11359 _("shift must be constant"));
11360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11361 inst
.instruction
|= Rd
<< 8;
11362 inst
.instruction
|= Rs
<< 16;
11363 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11364 _("shift value over 3 not allowed in thumb mode"));
11365 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11366 _("only LSL shift allowed in thumb mode"));
11367 encode_thumb32_shifted_operand (2);
11372 constraint (inst
.instruction
== T_MNEM_adds
11373 || inst
.instruction
== T_MNEM_subs
,
11376 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11378 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11379 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11382 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11383 ? 0x0000 : 0x8000);
11384 inst
.instruction
|= (Rd
<< 4) | Rs
;
11385 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11389 Rn
= inst
.operands
[2].reg
;
11390 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11392 /* We now have Rd, Rs, and Rn set to registers. */
11393 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11395 /* Can't do this for SUB. */
11396 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11397 inst
.instruction
= T_OPCODE_ADD_HI
;
11398 inst
.instruction
|= (Rd
& 8) << 4;
11399 inst
.instruction
|= (Rd
& 7);
11401 inst
.instruction
|= Rn
<< 3;
11403 inst
.instruction
|= Rs
<< 3;
11405 constraint (1, _("dest must overlap one source register"));
11409 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11410 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11411 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11421 Rd
= inst
.operands
[0].reg
;
11422 reject_bad_reg (Rd
);
11424 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11426 /* Defer to section relaxation. */
11427 inst
.relax
= inst
.instruction
;
11428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11429 inst
.instruction
|= Rd
<< 4;
11431 else if (unified_syntax
&& inst
.size_req
!= 2)
11433 /* Generate a 32-bit opcode. */
11434 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11435 inst
.instruction
|= Rd
<< 8;
11436 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11437 inst
.relocs
[0].pc_rel
= 1;
11441 /* Generate a 16-bit opcode. */
11442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11443 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11444 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11445 inst
.relocs
[0].pc_rel
= 1;
11446 inst
.instruction
|= Rd
<< 4;
11449 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11450 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11451 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11452 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11453 inst
.relocs
[0].exp
.X_add_number
+= 1;
11456 /* Arithmetic instructions for which there is just one 16-bit
11457 instruction encoding, and it allows only two low registers.
11458 For maximal compatibility with ARM syntax, we allow three register
11459 operands even when Thumb-32 instructions are not available, as long
11460 as the first two are identical. For instance, both "sbc r0,r1" and
11461 "sbc r0,r0,r1" are allowed. */
11467 Rd
= inst
.operands
[0].reg
;
11468 Rs
= (inst
.operands
[1].present
11469 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11470 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11471 Rn
= inst
.operands
[2].reg
;
11473 reject_bad_reg (Rd
);
11474 reject_bad_reg (Rs
);
11475 if (inst
.operands
[2].isreg
)
11476 reject_bad_reg (Rn
);
11478 if (unified_syntax
)
11480 if (!inst
.operands
[2].isreg
)
11482 /* For an immediate, we always generate a 32-bit opcode;
11483 section relaxation will shrink it later if possible. */
11484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11485 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11486 inst
.instruction
|= Rd
<< 8;
11487 inst
.instruction
|= Rs
<< 16;
11488 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11492 bfd_boolean narrow
;
11494 /* See if we can do this with a 16-bit instruction. */
11495 if (THUMB_SETS_FLAGS (inst
.instruction
))
11496 narrow
= !in_pred_block ();
11498 narrow
= in_pred_block ();
11500 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11502 if (inst
.operands
[2].shifted
)
11504 if (inst
.size_req
== 4)
11510 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11511 inst
.instruction
|= Rd
;
11512 inst
.instruction
|= Rn
<< 3;
11516 /* If we get here, it can't be done in 16 bits. */
11517 constraint (inst
.operands
[2].shifted
11518 && inst
.operands
[2].immisreg
,
11519 _("shift must be constant"));
11520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11521 inst
.instruction
|= Rd
<< 8;
11522 inst
.instruction
|= Rs
<< 16;
11523 encode_thumb32_shifted_operand (2);
11528 /* On its face this is a lie - the instruction does set the
11529 flags. However, the only supported mnemonic in this mode
11530 says it doesn't. */
11531 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11533 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11534 _("unshifted register required"));
11535 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11536 constraint (Rd
!= Rs
,
11537 _("dest and source1 must be the same register"));
11539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11540 inst
.instruction
|= Rd
;
11541 inst
.instruction
|= Rn
<< 3;
11545 /* Similarly, but for instructions where the arithmetic operation is
11546 commutative, so we can allow either of them to be different from
11547 the destination operand in a 16-bit instruction. For instance, all
11548 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11555 Rd
= inst
.operands
[0].reg
;
11556 Rs
= (inst
.operands
[1].present
11557 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11558 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11559 Rn
= inst
.operands
[2].reg
;
11561 reject_bad_reg (Rd
);
11562 reject_bad_reg (Rs
);
11563 if (inst
.operands
[2].isreg
)
11564 reject_bad_reg (Rn
);
11566 if (unified_syntax
)
11568 if (!inst
.operands
[2].isreg
)
11570 /* For an immediate, we always generate a 32-bit opcode;
11571 section relaxation will shrink it later if possible. */
11572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11573 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11574 inst
.instruction
|= Rd
<< 8;
11575 inst
.instruction
|= Rs
<< 16;
11576 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11580 bfd_boolean narrow
;
11582 /* See if we can do this with a 16-bit instruction. */
11583 if (THUMB_SETS_FLAGS (inst
.instruction
))
11584 narrow
= !in_pred_block ();
11586 narrow
= in_pred_block ();
11588 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11590 if (inst
.operands
[2].shifted
)
11592 if (inst
.size_req
== 4)
11599 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11600 inst
.instruction
|= Rd
;
11601 inst
.instruction
|= Rn
<< 3;
11606 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11607 inst
.instruction
|= Rd
;
11608 inst
.instruction
|= Rs
<< 3;
11613 /* If we get here, it can't be done in 16 bits. */
11614 constraint (inst
.operands
[2].shifted
11615 && inst
.operands
[2].immisreg
,
11616 _("shift must be constant"));
11617 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11618 inst
.instruction
|= Rd
<< 8;
11619 inst
.instruction
|= Rs
<< 16;
11620 encode_thumb32_shifted_operand (2);
11625 /* On its face this is a lie - the instruction does set the
11626 flags. However, the only supported mnemonic in this mode
11627 says it doesn't. */
11628 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11630 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11631 _("unshifted register required"));
11632 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11635 inst
.instruction
|= Rd
;
11638 inst
.instruction
|= Rn
<< 3;
11640 inst
.instruction
|= Rs
<< 3;
11642 constraint (1, _("dest must overlap one source register"));
11650 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11651 constraint (msb
> 32, _("bit-field extends past end of register"));
11652 /* The instruction encoding stores the LSB and MSB,
11653 not the LSB and width. */
11654 Rd
= inst
.operands
[0].reg
;
11655 reject_bad_reg (Rd
);
11656 inst
.instruction
|= Rd
<< 8;
11657 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11658 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11659 inst
.instruction
|= msb
- 1;
11668 Rd
= inst
.operands
[0].reg
;
11669 reject_bad_reg (Rd
);
11671 /* #0 in second position is alternative syntax for bfc, which is
11672 the same instruction but with REG_PC in the Rm field. */
11673 if (!inst
.operands
[1].isreg
)
11677 Rn
= inst
.operands
[1].reg
;
11678 reject_bad_reg (Rn
);
11681 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11682 constraint (msb
> 32, _("bit-field extends past end of register"));
11683 /* The instruction encoding stores the LSB and MSB,
11684 not the LSB and width. */
11685 inst
.instruction
|= Rd
<< 8;
11686 inst
.instruction
|= Rn
<< 16;
11687 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11688 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11689 inst
.instruction
|= msb
- 1;
11697 Rd
= inst
.operands
[0].reg
;
11698 Rn
= inst
.operands
[1].reg
;
11700 reject_bad_reg (Rd
);
11701 reject_bad_reg (Rn
);
11703 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11704 _("bit-field extends past end of register"));
11705 inst
.instruction
|= Rd
<< 8;
11706 inst
.instruction
|= Rn
<< 16;
11707 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11708 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11709 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11712 /* ARM V5 Thumb BLX (argument parse)
11713 BLX <target_addr> which is BLX(1)
11714 BLX <Rm> which is BLX(2)
11715 Unfortunately, there are two different opcodes for this mnemonic.
11716 So, the insns[].value is not used, and the code here zaps values
11717 into inst.instruction.
11719 ??? How to take advantage of the additional two bits of displacement
11720 available in Thumb32 mode? Need new relocation? */
11725 set_pred_insn_type_last ();
11727 if (inst
.operands
[0].isreg
)
11729 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11730 /* We have a register, so this is BLX(2). */
11731 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11735 /* No register. This must be BLX(1). */
11736 inst
.instruction
= 0xf000e800;
11737 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11746 bfd_reloc_code_real_type reloc
;
11749 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11751 if (in_pred_block ())
11753 /* Conditional branches inside IT blocks are encoded as unconditional
11755 cond
= COND_ALWAYS
;
11760 if (cond
!= COND_ALWAYS
)
11761 opcode
= T_MNEM_bcond
;
11763 opcode
= inst
.instruction
;
11766 && (inst
.size_req
== 4
11767 || (inst
.size_req
!= 2
11768 && (inst
.operands
[0].hasreloc
11769 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11771 inst
.instruction
= THUMB_OP32(opcode
);
11772 if (cond
== COND_ALWAYS
)
11773 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11777 _("selected architecture does not support "
11778 "wide conditional branch instruction"));
11780 gas_assert (cond
!= 0xF);
11781 inst
.instruction
|= cond
<< 22;
11782 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11787 inst
.instruction
= THUMB_OP16(opcode
);
11788 if (cond
== COND_ALWAYS
)
11789 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11792 inst
.instruction
|= cond
<< 8;
11793 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11795 /* Allow section relaxation. */
11796 if (unified_syntax
&& inst
.size_req
!= 2)
11797 inst
.relax
= opcode
;
11799 inst
.relocs
[0].type
= reloc
;
11800 inst
.relocs
[0].pc_rel
= 1;
11803 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11804 between the two is the maximum immediate allowed - which is passed in
11807 do_t_bkpt_hlt1 (int range
)
11809 constraint (inst
.cond
!= COND_ALWAYS
,
11810 _("instruction is always unconditional"));
11811 if (inst
.operands
[0].present
)
11813 constraint (inst
.operands
[0].imm
> range
,
11814 _("immediate value out of range"));
11815 inst
.instruction
|= inst
.operands
[0].imm
;
11818 set_pred_insn_type (NEUTRAL_IT_INSN
);
11824 do_t_bkpt_hlt1 (63);
11830 do_t_bkpt_hlt1 (255);
11834 do_t_branch23 (void)
11836 set_pred_insn_type_last ();
11837 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11839 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11840 this file. We used to simply ignore the PLT reloc type here --
11841 the branch encoding is now needed to deal with TLSCALL relocs.
11842 So if we see a PLT reloc now, put it back to how it used to be to
11843 keep the preexisting behaviour. */
11844 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11845 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11847 #if defined(OBJ_COFF)
11848 /* If the destination of the branch is a defined symbol which does not have
11849 the THUMB_FUNC attribute, then we must be calling a function which has
11850 the (interfacearm) attribute. We look for the Thumb entry point to that
11851 function and change the branch to refer to that function instead. */
11852 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11853 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11854 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11855 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11856 inst
.relocs
[0].exp
.X_add_symbol
11857 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11864 set_pred_insn_type_last ();
11865 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11866 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11867 should cause the alignment to be checked once it is known. This is
11868 because BX PC only works if the instruction is word aligned. */
11876 set_pred_insn_type_last ();
11877 Rm
= inst
.operands
[0].reg
;
11878 reject_bad_reg (Rm
);
11879 inst
.instruction
|= Rm
<< 16;
11888 Rd
= inst
.operands
[0].reg
;
11889 Rm
= inst
.operands
[1].reg
;
11891 reject_bad_reg (Rd
);
11892 reject_bad_reg (Rm
);
11894 inst
.instruction
|= Rd
<< 8;
11895 inst
.instruction
|= Rm
<< 16;
11896 inst
.instruction
|= Rm
;
11902 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11908 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11909 inst
.instruction
|= inst
.operands
[0].imm
;
11915 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11917 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11918 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11920 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11921 inst
.instruction
= 0xf3af8000;
11922 inst
.instruction
|= imod
<< 9;
11923 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11924 if (inst
.operands
[1].present
)
11925 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11930 && (inst
.operands
[0].imm
& 4),
11931 _("selected processor does not support 'A' form "
11932 "of this instruction"));
11933 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11934 _("Thumb does not support the 2-argument "
11935 "form of this instruction"));
11936 inst
.instruction
|= inst
.operands
[0].imm
;
11940 /* THUMB CPY instruction (argument parse). */
11945 if (inst
.size_req
== 4)
11947 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11948 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11949 inst
.instruction
|= inst
.operands
[1].reg
;
11953 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11954 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11955 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11962 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11963 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11964 inst
.instruction
|= inst
.operands
[0].reg
;
11965 inst
.relocs
[0].pc_rel
= 1;
11966 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11972 inst
.instruction
|= inst
.operands
[0].imm
;
11978 unsigned Rd
, Rn
, Rm
;
11980 Rd
= inst
.operands
[0].reg
;
11981 Rn
= (inst
.operands
[1].present
11982 ? inst
.operands
[1].reg
: Rd
);
11983 Rm
= inst
.operands
[2].reg
;
11985 reject_bad_reg (Rd
);
11986 reject_bad_reg (Rn
);
11987 reject_bad_reg (Rm
);
11989 inst
.instruction
|= Rd
<< 8;
11990 inst
.instruction
|= Rn
<< 16;
11991 inst
.instruction
|= Rm
;
11997 if (unified_syntax
&& inst
.size_req
== 4)
11998 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12006 unsigned int cond
= inst
.operands
[0].imm
;
12008 set_pred_insn_type (IT_INSN
);
12009 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12010 now_pred
.cc
= cond
;
12011 now_pred
.warn_deprecated
= FALSE
;
12012 now_pred
.type
= SCALAR_PRED
;
12014 /* If the condition is a negative condition, invert the mask. */
12015 if ((cond
& 0x1) == 0x0)
12017 unsigned int mask
= inst
.instruction
& 0x000f;
12019 if ((mask
& 0x7) == 0)
12021 /* No conversion needed. */
12022 now_pred
.block_length
= 1;
12024 else if ((mask
& 0x3) == 0)
12027 now_pred
.block_length
= 2;
12029 else if ((mask
& 0x1) == 0)
12032 now_pred
.block_length
= 3;
12037 now_pred
.block_length
= 4;
12040 inst
.instruction
&= 0xfff0;
12041 inst
.instruction
|= mask
;
12044 inst
.instruction
|= cond
<< 4;
12047 /* Helper function used for both push/pop and ldm/stm. */
12049 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12050 bfd_boolean writeback
)
12052 bfd_boolean load
, store
;
12054 gas_assert (base
!= -1 || !do_io
);
12055 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12056 store
= do_io
&& !load
;
12058 if (mask
& (1 << 13))
12059 inst
.error
= _("SP not allowed in register list");
12061 if (do_io
&& (mask
& (1 << base
)) != 0
12063 inst
.error
= _("having the base register in the register list when "
12064 "using write back is UNPREDICTABLE");
12068 if (mask
& (1 << 15))
12070 if (mask
& (1 << 14))
12071 inst
.error
= _("LR and PC should not both be in register list");
12073 set_pred_insn_type_last ();
12078 if (mask
& (1 << 15))
12079 inst
.error
= _("PC not allowed in register list");
12082 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12084 /* Single register transfers implemented as str/ldr. */
12087 if (inst
.instruction
& (1 << 23))
12088 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12090 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12094 if (inst
.instruction
& (1 << 23))
12095 inst
.instruction
= 0x00800000; /* ia -> [base] */
12097 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12100 inst
.instruction
|= 0xf8400000;
12102 inst
.instruction
|= 0x00100000;
12104 mask
= ffs (mask
) - 1;
12107 else if (writeback
)
12108 inst
.instruction
|= WRITE_BACK
;
12110 inst
.instruction
|= mask
;
12112 inst
.instruction
|= base
<< 16;
12118 /* This really doesn't seem worth it. */
12119 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12120 _("expression too complex"));
12121 constraint (inst
.operands
[1].writeback
,
12122 _("Thumb load/store multiple does not support {reglist}^"));
12124 if (unified_syntax
)
12126 bfd_boolean narrow
;
12130 /* See if we can use a 16-bit instruction. */
12131 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12132 && inst
.size_req
!= 4
12133 && !(inst
.operands
[1].imm
& ~0xff))
12135 mask
= 1 << inst
.operands
[0].reg
;
12137 if (inst
.operands
[0].reg
<= 7)
12139 if (inst
.instruction
== T_MNEM_stmia
12140 ? inst
.operands
[0].writeback
12141 : (inst
.operands
[0].writeback
12142 == !(inst
.operands
[1].imm
& mask
)))
12144 if (inst
.instruction
== T_MNEM_stmia
12145 && (inst
.operands
[1].imm
& mask
)
12146 && (inst
.operands
[1].imm
& (mask
- 1)))
12147 as_warn (_("value stored for r%d is UNKNOWN"),
12148 inst
.operands
[0].reg
);
12150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12151 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12152 inst
.instruction
|= inst
.operands
[1].imm
;
12155 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12157 /* This means 1 register in reg list one of 3 situations:
12158 1. Instruction is stmia, but without writeback.
12159 2. lmdia without writeback, but with Rn not in
12161 3. ldmia with writeback, but with Rn in reglist.
12162 Case 3 is UNPREDICTABLE behaviour, so we handle
12163 case 1 and 2 which can be converted into a 16-bit
12164 str or ldr. The SP cases are handled below. */
12165 unsigned long opcode
;
12166 /* First, record an error for Case 3. */
12167 if (inst
.operands
[1].imm
& mask
12168 && inst
.operands
[0].writeback
)
12170 _("having the base register in the register list when "
12171 "using write back is UNPREDICTABLE");
12173 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12175 inst
.instruction
= THUMB_OP16 (opcode
);
12176 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12177 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12181 else if (inst
.operands
[0] .reg
== REG_SP
)
12183 if (inst
.operands
[0].writeback
)
12186 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12187 ? T_MNEM_push
: T_MNEM_pop
);
12188 inst
.instruction
|= inst
.operands
[1].imm
;
12191 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12194 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12195 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12196 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12204 if (inst
.instruction
< 0xffff)
12205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12207 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12208 inst
.operands
[1].imm
,
12209 inst
.operands
[0].writeback
);
12214 constraint (inst
.operands
[0].reg
> 7
12215 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12216 constraint (inst
.instruction
!= T_MNEM_ldmia
12217 && inst
.instruction
!= T_MNEM_stmia
,
12218 _("Thumb-2 instruction only valid in unified syntax"));
12219 if (inst
.instruction
== T_MNEM_stmia
)
12221 if (!inst
.operands
[0].writeback
)
12222 as_warn (_("this instruction will write back the base register"));
12223 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12224 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12225 as_warn (_("value stored for r%d is UNKNOWN"),
12226 inst
.operands
[0].reg
);
12230 if (!inst
.operands
[0].writeback
12231 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12232 as_warn (_("this instruction will write back the base register"));
12233 else if (inst
.operands
[0].writeback
12234 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12235 as_warn (_("this instruction will not write back the base register"));
12238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12239 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12240 inst
.instruction
|= inst
.operands
[1].imm
;
12247 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12248 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12249 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12250 || inst
.operands
[1].negative
,
12253 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12256 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12257 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12263 if (!inst
.operands
[1].present
)
12265 constraint (inst
.operands
[0].reg
== REG_LR
,
12266 _("r14 not allowed as first register "
12267 "when second register is omitted"));
12268 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12270 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12274 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12275 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12281 unsigned long opcode
;
12284 if (inst
.operands
[0].isreg
12285 && !inst
.operands
[0].preind
12286 && inst
.operands
[0].reg
== REG_PC
)
12287 set_pred_insn_type_last ();
12289 opcode
= inst
.instruction
;
12290 if (unified_syntax
)
12292 if (!inst
.operands
[1].isreg
)
12294 if (opcode
<= 0xffff)
12295 inst
.instruction
= THUMB_OP32 (opcode
);
12296 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12299 if (inst
.operands
[1].isreg
12300 && !inst
.operands
[1].writeback
12301 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12302 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12303 && opcode
<= 0xffff
12304 && inst
.size_req
!= 4)
12306 /* Insn may have a 16-bit form. */
12307 Rn
= inst
.operands
[1].reg
;
12308 if (inst
.operands
[1].immisreg
)
12310 inst
.instruction
= THUMB_OP16 (opcode
);
12312 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12314 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12315 reject_bad_reg (inst
.operands
[1].imm
);
12317 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12318 && opcode
!= T_MNEM_ldrsb
)
12319 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12320 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12327 if (inst
.relocs
[0].pc_rel
)
12328 opcode
= T_MNEM_ldr_pc2
;
12330 opcode
= T_MNEM_ldr_pc
;
12334 if (opcode
== T_MNEM_ldr
)
12335 opcode
= T_MNEM_ldr_sp
;
12337 opcode
= T_MNEM_str_sp
;
12339 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12343 inst
.instruction
= inst
.operands
[0].reg
;
12344 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12346 inst
.instruction
|= THUMB_OP16 (opcode
);
12347 if (inst
.size_req
== 2)
12348 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12350 inst
.relax
= opcode
;
12354 /* Definitely a 32-bit variant. */
12356 /* Warning for Erratum 752419. */
12357 if (opcode
== T_MNEM_ldr
12358 && inst
.operands
[0].reg
== REG_SP
12359 && inst
.operands
[1].writeback
== 1
12360 && !inst
.operands
[1].immisreg
)
12362 if (no_cpu_selected ()
12363 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12364 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12365 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12366 as_warn (_("This instruction may be unpredictable "
12367 "if executed on M-profile cores "
12368 "with interrupts enabled."));
12371 /* Do some validations regarding addressing modes. */
12372 if (inst
.operands
[1].immisreg
)
12373 reject_bad_reg (inst
.operands
[1].imm
);
12375 constraint (inst
.operands
[1].writeback
== 1
12376 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12379 inst
.instruction
= THUMB_OP32 (opcode
);
12380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12381 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12382 check_ldr_r15_aligned ();
12386 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12388 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12390 /* Only [Rn,Rm] is acceptable. */
12391 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12392 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12393 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12394 || inst
.operands
[1].negative
,
12395 _("Thumb does not support this addressing mode"));
12396 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12400 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12401 if (!inst
.operands
[1].isreg
)
12402 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12405 constraint (!inst
.operands
[1].preind
12406 || inst
.operands
[1].shifted
12407 || inst
.operands
[1].writeback
,
12408 _("Thumb does not support this addressing mode"));
12409 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12411 constraint (inst
.instruction
& 0x0600,
12412 _("byte or halfword not valid for base register"));
12413 constraint (inst
.operands
[1].reg
== REG_PC
12414 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12415 _("r15 based store not allowed"));
12416 constraint (inst
.operands
[1].immisreg
,
12417 _("invalid base register for register offset"));
12419 if (inst
.operands
[1].reg
== REG_PC
)
12420 inst
.instruction
= T_OPCODE_LDR_PC
;
12421 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12422 inst
.instruction
= T_OPCODE_LDR_SP
;
12424 inst
.instruction
= T_OPCODE_STR_SP
;
12426 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12427 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12431 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12432 if (!inst
.operands
[1].immisreg
)
12434 /* Immediate offset. */
12435 inst
.instruction
|= inst
.operands
[0].reg
;
12436 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12437 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12441 /* Register offset. */
12442 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12443 constraint (inst
.operands
[1].negative
,
12444 _("Thumb does not support this addressing mode"));
12447 switch (inst
.instruction
)
12449 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12450 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12451 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12452 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12453 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12454 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12455 case 0x5600 /* ldrsb */:
12456 case 0x5e00 /* ldrsh */: break;
12460 inst
.instruction
|= inst
.operands
[0].reg
;
12461 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12462 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12468 if (!inst
.operands
[1].present
)
12470 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12471 constraint (inst
.operands
[0].reg
== REG_LR
,
12472 _("r14 not allowed here"));
12473 constraint (inst
.operands
[0].reg
== REG_R12
,
12474 _("r12 not allowed here"));
12477 if (inst
.operands
[2].writeback
12478 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12479 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12480 as_warn (_("base register written back, and overlaps "
12481 "one of transfer registers"));
12483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12484 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12485 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12491 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12492 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12498 unsigned Rd
, Rn
, Rm
, Ra
;
12500 Rd
= inst
.operands
[0].reg
;
12501 Rn
= inst
.operands
[1].reg
;
12502 Rm
= inst
.operands
[2].reg
;
12503 Ra
= inst
.operands
[3].reg
;
12505 reject_bad_reg (Rd
);
12506 reject_bad_reg (Rn
);
12507 reject_bad_reg (Rm
);
12508 reject_bad_reg (Ra
);
12510 inst
.instruction
|= Rd
<< 8;
12511 inst
.instruction
|= Rn
<< 16;
12512 inst
.instruction
|= Rm
;
12513 inst
.instruction
|= Ra
<< 12;
12519 unsigned RdLo
, RdHi
, Rn
, Rm
;
12521 RdLo
= inst
.operands
[0].reg
;
12522 RdHi
= inst
.operands
[1].reg
;
12523 Rn
= inst
.operands
[2].reg
;
12524 Rm
= inst
.operands
[3].reg
;
12526 reject_bad_reg (RdLo
);
12527 reject_bad_reg (RdHi
);
12528 reject_bad_reg (Rn
);
12529 reject_bad_reg (Rm
);
12531 inst
.instruction
|= RdLo
<< 12;
12532 inst
.instruction
|= RdHi
<< 8;
12533 inst
.instruction
|= Rn
<< 16;
12534 inst
.instruction
|= Rm
;
12538 do_t_mov_cmp (void)
12542 Rn
= inst
.operands
[0].reg
;
12543 Rm
= inst
.operands
[1].reg
;
12546 set_pred_insn_type_last ();
12548 if (unified_syntax
)
12550 int r0off
= (inst
.instruction
== T_MNEM_mov
12551 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12552 unsigned long opcode
;
12553 bfd_boolean narrow
;
12554 bfd_boolean low_regs
;
12556 low_regs
= (Rn
<= 7 && Rm
<= 7);
12557 opcode
= inst
.instruction
;
12558 if (in_pred_block ())
12559 narrow
= opcode
!= T_MNEM_movs
;
12561 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12562 if (inst
.size_req
== 4
12563 || inst
.operands
[1].shifted
)
12566 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12567 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12568 && !inst
.operands
[1].shifted
12572 inst
.instruction
= T2_SUBS_PC_LR
;
12576 if (opcode
== T_MNEM_cmp
)
12578 constraint (Rn
== REG_PC
, BAD_PC
);
12581 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12583 warn_deprecated_sp (Rm
);
12584 /* R15 was documented as a valid choice for Rm in ARMv6,
12585 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12586 tools reject R15, so we do too. */
12587 constraint (Rm
== REG_PC
, BAD_PC
);
12590 reject_bad_reg (Rm
);
12592 else if (opcode
== T_MNEM_mov
12593 || opcode
== T_MNEM_movs
)
12595 if (inst
.operands
[1].isreg
)
12597 if (opcode
== T_MNEM_movs
)
12599 reject_bad_reg (Rn
);
12600 reject_bad_reg (Rm
);
12604 /* This is mov.n. */
12605 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12606 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12608 as_tsktsk (_("Use of r%u as a source register is "
12609 "deprecated when r%u is the destination "
12610 "register."), Rm
, Rn
);
12615 /* This is mov.w. */
12616 constraint (Rn
== REG_PC
, BAD_PC
);
12617 constraint (Rm
== REG_PC
, BAD_PC
);
12618 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12619 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12623 reject_bad_reg (Rn
);
12626 if (!inst
.operands
[1].isreg
)
12628 /* Immediate operand. */
12629 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12631 if (low_regs
&& narrow
)
12633 inst
.instruction
= THUMB_OP16 (opcode
);
12634 inst
.instruction
|= Rn
<< 8;
12635 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12636 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12638 if (inst
.size_req
== 2)
12639 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12641 inst
.relax
= opcode
;
12646 constraint ((inst
.relocs
[0].type
12647 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12648 && (inst
.relocs
[0].type
12649 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12650 THUMB1_RELOC_ONLY
);
12652 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12653 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12654 inst
.instruction
|= Rn
<< r0off
;
12655 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12658 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12659 && (inst
.instruction
== T_MNEM_mov
12660 || inst
.instruction
== T_MNEM_movs
))
12662 /* Register shifts are encoded as separate shift instructions. */
12663 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12665 if (in_pred_block ())
12670 if (inst
.size_req
== 4)
12673 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12679 switch (inst
.operands
[1].shift_kind
)
12682 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12685 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12688 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12691 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12697 inst
.instruction
= opcode
;
12700 inst
.instruction
|= Rn
;
12701 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12706 inst
.instruction
|= CONDS_BIT
;
12708 inst
.instruction
|= Rn
<< 8;
12709 inst
.instruction
|= Rm
<< 16;
12710 inst
.instruction
|= inst
.operands
[1].imm
;
12715 /* Some mov with immediate shift have narrow variants.
12716 Register shifts are handled above. */
12717 if (low_regs
&& inst
.operands
[1].shifted
12718 && (inst
.instruction
== T_MNEM_mov
12719 || inst
.instruction
== T_MNEM_movs
))
12721 if (in_pred_block ())
12722 narrow
= (inst
.instruction
== T_MNEM_mov
);
12724 narrow
= (inst
.instruction
== T_MNEM_movs
);
12729 switch (inst
.operands
[1].shift_kind
)
12731 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12732 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12733 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12734 default: narrow
= FALSE
; break;
12740 inst
.instruction
|= Rn
;
12741 inst
.instruction
|= Rm
<< 3;
12742 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12747 inst
.instruction
|= Rn
<< r0off
;
12748 encode_thumb32_shifted_operand (1);
12752 switch (inst
.instruction
)
12755 /* In v4t or v5t a move of two lowregs produces unpredictable
12756 results. Don't allow this. */
12759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12760 "MOV Rd, Rs with two low registers is not "
12761 "permitted on this architecture");
12762 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12766 inst
.instruction
= T_OPCODE_MOV_HR
;
12767 inst
.instruction
|= (Rn
& 0x8) << 4;
12768 inst
.instruction
|= (Rn
& 0x7);
12769 inst
.instruction
|= Rm
<< 3;
12773 /* We know we have low registers at this point.
12774 Generate LSLS Rd, Rs, #0. */
12775 inst
.instruction
= T_OPCODE_LSL_I
;
12776 inst
.instruction
|= Rn
;
12777 inst
.instruction
|= Rm
<< 3;
12783 inst
.instruction
= T_OPCODE_CMP_LR
;
12784 inst
.instruction
|= Rn
;
12785 inst
.instruction
|= Rm
<< 3;
12789 inst
.instruction
= T_OPCODE_CMP_HR
;
12790 inst
.instruction
|= (Rn
& 0x8) << 4;
12791 inst
.instruction
|= (Rn
& 0x7);
12792 inst
.instruction
|= Rm
<< 3;
12799 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12801 /* PR 10443: Do not silently ignore shifted operands. */
12802 constraint (inst
.operands
[1].shifted
,
12803 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12805 if (inst
.operands
[1].isreg
)
12807 if (Rn
< 8 && Rm
< 8)
12809 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12810 since a MOV instruction produces unpredictable results. */
12811 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12812 inst
.instruction
= T_OPCODE_ADD_I3
;
12814 inst
.instruction
= T_OPCODE_CMP_LR
;
12816 inst
.instruction
|= Rn
;
12817 inst
.instruction
|= Rm
<< 3;
12821 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12822 inst
.instruction
= T_OPCODE_MOV_HR
;
12824 inst
.instruction
= T_OPCODE_CMP_HR
;
12830 constraint (Rn
> 7,
12831 _("only lo regs allowed with immediate"));
12832 inst
.instruction
|= Rn
<< 8;
12833 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12844 top
= (inst
.instruction
& 0x00800000) != 0;
12845 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12847 constraint (top
, _(":lower16: not allowed in this instruction"));
12848 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12850 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12852 constraint (!top
, _(":upper16: not allowed in this instruction"));
12853 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12856 Rd
= inst
.operands
[0].reg
;
12857 reject_bad_reg (Rd
);
12859 inst
.instruction
|= Rd
<< 8;
12860 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12862 imm
= inst
.relocs
[0].exp
.X_add_number
;
12863 inst
.instruction
|= (imm
& 0xf000) << 4;
12864 inst
.instruction
|= (imm
& 0x0800) << 15;
12865 inst
.instruction
|= (imm
& 0x0700) << 4;
12866 inst
.instruction
|= (imm
& 0x00ff);
12871 do_t_mvn_tst (void)
12875 Rn
= inst
.operands
[0].reg
;
12876 Rm
= inst
.operands
[1].reg
;
12878 if (inst
.instruction
== T_MNEM_cmp
12879 || inst
.instruction
== T_MNEM_cmn
)
12880 constraint (Rn
== REG_PC
, BAD_PC
);
12882 reject_bad_reg (Rn
);
12883 reject_bad_reg (Rm
);
12885 if (unified_syntax
)
12887 int r0off
= (inst
.instruction
== T_MNEM_mvn
12888 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12889 bfd_boolean narrow
;
12891 if (inst
.size_req
== 4
12892 || inst
.instruction
> 0xffff
12893 || inst
.operands
[1].shifted
12894 || Rn
> 7 || Rm
> 7)
12896 else if (inst
.instruction
== T_MNEM_cmn
12897 || inst
.instruction
== T_MNEM_tst
)
12899 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12900 narrow
= !in_pred_block ();
12902 narrow
= in_pred_block ();
12904 if (!inst
.operands
[1].isreg
)
12906 /* For an immediate, we always generate a 32-bit opcode;
12907 section relaxation will shrink it later if possible. */
12908 if (inst
.instruction
< 0xffff)
12909 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12910 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12911 inst
.instruction
|= Rn
<< r0off
;
12912 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12916 /* See if we can do this with a 16-bit instruction. */
12919 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12920 inst
.instruction
|= Rn
;
12921 inst
.instruction
|= Rm
<< 3;
12925 constraint (inst
.operands
[1].shifted
12926 && inst
.operands
[1].immisreg
,
12927 _("shift must be constant"));
12928 if (inst
.instruction
< 0xffff)
12929 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12930 inst
.instruction
|= Rn
<< r0off
;
12931 encode_thumb32_shifted_operand (1);
12937 constraint (inst
.instruction
> 0xffff
12938 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12939 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12940 _("unshifted register required"));
12941 constraint (Rn
> 7 || Rm
> 7,
12944 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12945 inst
.instruction
|= Rn
;
12946 inst
.instruction
|= Rm
<< 3;
12955 if (do_vfp_nsyn_mrs () == SUCCESS
)
12958 Rd
= inst
.operands
[0].reg
;
12959 reject_bad_reg (Rd
);
12960 inst
.instruction
|= Rd
<< 8;
12962 if (inst
.operands
[1].isreg
)
12964 unsigned br
= inst
.operands
[1].reg
;
12965 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12966 as_bad (_("bad register for mrs"));
12968 inst
.instruction
|= br
& (0xf << 16);
12969 inst
.instruction
|= (br
& 0x300) >> 4;
12970 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12974 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12976 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12978 /* PR gas/12698: The constraint is only applied for m_profile.
12979 If the user has specified -march=all, we want to ignore it as
12980 we are building for any CPU type, including non-m variants. */
12981 bfd_boolean m_profile
=
12982 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12983 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12984 "not support requested special purpose register"));
12987 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12989 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12990 _("'APSR', 'CPSR' or 'SPSR' expected"));
12992 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12993 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12994 inst
.instruction
|= 0xf0000;
13004 if (do_vfp_nsyn_msr () == SUCCESS
)
13007 constraint (!inst
.operands
[1].isreg
,
13008 _("Thumb encoding does not support an immediate here"));
13010 if (inst
.operands
[0].isreg
)
13011 flags
= (int)(inst
.operands
[0].reg
);
13013 flags
= inst
.operands
[0].imm
;
13015 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13017 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13019 /* PR gas/12698: The constraint is only applied for m_profile.
13020 If the user has specified -march=all, we want to ignore it as
13021 we are building for any CPU type, including non-m variants. */
13022 bfd_boolean m_profile
=
13023 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13024 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13025 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13026 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13027 && bits
!= PSR_f
)) && m_profile
,
13028 _("selected processor does not support requested special "
13029 "purpose register"));
13032 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13033 "requested special purpose register"));
13035 Rn
= inst
.operands
[1].reg
;
13036 reject_bad_reg (Rn
);
13038 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13039 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13040 inst
.instruction
|= (flags
& 0x300) >> 4;
13041 inst
.instruction
|= (flags
& 0xff);
13042 inst
.instruction
|= Rn
<< 16;
13048 bfd_boolean narrow
;
13049 unsigned Rd
, Rn
, Rm
;
13051 if (!inst
.operands
[2].present
)
13052 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13054 Rd
= inst
.operands
[0].reg
;
13055 Rn
= inst
.operands
[1].reg
;
13056 Rm
= inst
.operands
[2].reg
;
13058 if (unified_syntax
)
13060 if (inst
.size_req
== 4
13066 else if (inst
.instruction
== T_MNEM_muls
)
13067 narrow
= !in_pred_block ();
13069 narrow
= in_pred_block ();
13073 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13074 constraint (Rn
> 7 || Rm
> 7,
13081 /* 16-bit MULS/Conditional MUL. */
13082 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13083 inst
.instruction
|= Rd
;
13086 inst
.instruction
|= Rm
<< 3;
13088 inst
.instruction
|= Rn
<< 3;
13090 constraint (1, _("dest must overlap one source register"));
13094 constraint (inst
.instruction
!= T_MNEM_mul
,
13095 _("Thumb-2 MUL must not set flags"));
13097 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13098 inst
.instruction
|= Rd
<< 8;
13099 inst
.instruction
|= Rn
<< 16;
13100 inst
.instruction
|= Rm
<< 0;
13102 reject_bad_reg (Rd
);
13103 reject_bad_reg (Rn
);
13104 reject_bad_reg (Rm
);
13111 unsigned RdLo
, RdHi
, Rn
, Rm
;
13113 RdLo
= inst
.operands
[0].reg
;
13114 RdHi
= inst
.operands
[1].reg
;
13115 Rn
= inst
.operands
[2].reg
;
13116 Rm
= inst
.operands
[3].reg
;
13118 reject_bad_reg (RdLo
);
13119 reject_bad_reg (RdHi
);
13120 reject_bad_reg (Rn
);
13121 reject_bad_reg (Rm
);
13123 inst
.instruction
|= RdLo
<< 12;
13124 inst
.instruction
|= RdHi
<< 8;
13125 inst
.instruction
|= Rn
<< 16;
13126 inst
.instruction
|= Rm
;
13129 as_tsktsk (_("rdhi and rdlo must be different"));
13135 set_pred_insn_type (NEUTRAL_IT_INSN
);
13137 if (unified_syntax
)
13139 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13141 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13142 inst
.instruction
|= inst
.operands
[0].imm
;
13146 /* PR9722: Check for Thumb2 availability before
13147 generating a thumb2 nop instruction. */
13148 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13150 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13151 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13154 inst
.instruction
= 0x46c0;
13159 constraint (inst
.operands
[0].present
,
13160 _("Thumb does not support NOP with hints"));
13161 inst
.instruction
= 0x46c0;
13168 if (unified_syntax
)
13170 bfd_boolean narrow
;
13172 if (THUMB_SETS_FLAGS (inst
.instruction
))
13173 narrow
= !in_pred_block ();
13175 narrow
= in_pred_block ();
13176 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13178 if (inst
.size_req
== 4)
13183 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13189 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13190 inst
.instruction
|= inst
.operands
[0].reg
;
13191 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13196 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13198 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13201 inst
.instruction
|= inst
.operands
[0].reg
;
13202 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13211 Rd
= inst
.operands
[0].reg
;
13212 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13214 reject_bad_reg (Rd
);
13215 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13216 reject_bad_reg (Rn
);
13218 inst
.instruction
|= Rd
<< 8;
13219 inst
.instruction
|= Rn
<< 16;
13221 if (!inst
.operands
[2].isreg
)
13223 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13224 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13230 Rm
= inst
.operands
[2].reg
;
13231 reject_bad_reg (Rm
);
13233 constraint (inst
.operands
[2].shifted
13234 && inst
.operands
[2].immisreg
,
13235 _("shift must be constant"));
13236 encode_thumb32_shifted_operand (2);
13243 unsigned Rd
, Rn
, Rm
;
13245 Rd
= inst
.operands
[0].reg
;
13246 Rn
= inst
.operands
[1].reg
;
13247 Rm
= inst
.operands
[2].reg
;
13249 reject_bad_reg (Rd
);
13250 reject_bad_reg (Rn
);
13251 reject_bad_reg (Rm
);
13253 inst
.instruction
|= Rd
<< 8;
13254 inst
.instruction
|= Rn
<< 16;
13255 inst
.instruction
|= Rm
;
13256 if (inst
.operands
[3].present
)
13258 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13259 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13260 _("expression too complex"));
13261 inst
.instruction
|= (val
& 0x1c) << 10;
13262 inst
.instruction
|= (val
& 0x03) << 6;
13269 if (!inst
.operands
[3].present
)
13273 inst
.instruction
&= ~0x00000020;
13275 /* PR 10168. Swap the Rm and Rn registers. */
13276 Rtmp
= inst
.operands
[1].reg
;
13277 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13278 inst
.operands
[2].reg
= Rtmp
;
13286 if (inst
.operands
[0].immisreg
)
13287 reject_bad_reg (inst
.operands
[0].imm
);
13289 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13293 do_t_push_pop (void)
13297 constraint (inst
.operands
[0].writeback
,
13298 _("push/pop do not support {reglist}^"));
13299 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13300 _("expression too complex"));
13302 mask
= inst
.operands
[0].imm
;
13303 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13304 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13305 else if (inst
.size_req
!= 4
13306 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13307 ? REG_LR
: REG_PC
)))
13309 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13310 inst
.instruction
|= THUMB_PP_PC_LR
;
13311 inst
.instruction
|= mask
& 0xff;
13313 else if (unified_syntax
)
13315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13316 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13320 inst
.error
= _("invalid register list to push/pop instruction");
13328 if (unified_syntax
)
13329 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13332 inst
.error
= _("invalid register list to push/pop instruction");
13338 do_t_vscclrm (void)
13340 if (inst
.operands
[0].issingle
)
13342 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13343 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13344 inst
.instruction
|= inst
.operands
[0].imm
;
13348 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13349 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13350 inst
.instruction
|= 1 << 8;
13351 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13360 Rd
= inst
.operands
[0].reg
;
13361 Rm
= inst
.operands
[1].reg
;
13363 reject_bad_reg (Rd
);
13364 reject_bad_reg (Rm
);
13366 inst
.instruction
|= Rd
<< 8;
13367 inst
.instruction
|= Rm
<< 16;
13368 inst
.instruction
|= Rm
;
13376 Rd
= inst
.operands
[0].reg
;
13377 Rm
= inst
.operands
[1].reg
;
13379 reject_bad_reg (Rd
);
13380 reject_bad_reg (Rm
);
13382 if (Rd
<= 7 && Rm
<= 7
13383 && inst
.size_req
!= 4)
13385 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13386 inst
.instruction
|= Rd
;
13387 inst
.instruction
|= Rm
<< 3;
13389 else if (unified_syntax
)
13391 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13392 inst
.instruction
|= Rd
<< 8;
13393 inst
.instruction
|= Rm
<< 16;
13394 inst
.instruction
|= Rm
;
13397 inst
.error
= BAD_HIREG
;
13405 Rd
= inst
.operands
[0].reg
;
13406 Rm
= inst
.operands
[1].reg
;
13408 reject_bad_reg (Rd
);
13409 reject_bad_reg (Rm
);
13411 inst
.instruction
|= Rd
<< 8;
13412 inst
.instruction
|= Rm
;
13420 Rd
= inst
.operands
[0].reg
;
13421 Rs
= (inst
.operands
[1].present
13422 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13423 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13425 reject_bad_reg (Rd
);
13426 reject_bad_reg (Rs
);
13427 if (inst
.operands
[2].isreg
)
13428 reject_bad_reg (inst
.operands
[2].reg
);
13430 inst
.instruction
|= Rd
<< 8;
13431 inst
.instruction
|= Rs
<< 16;
13432 if (!inst
.operands
[2].isreg
)
13434 bfd_boolean narrow
;
13436 if ((inst
.instruction
& 0x00100000) != 0)
13437 narrow
= !in_pred_block ();
13439 narrow
= in_pred_block ();
13441 if (Rd
> 7 || Rs
> 7)
13444 if (inst
.size_req
== 4 || !unified_syntax
)
13447 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13448 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13451 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13452 relaxation, but it doesn't seem worth the hassle. */
13455 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13456 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13457 inst
.instruction
|= Rs
<< 3;
13458 inst
.instruction
|= Rd
;
13462 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13463 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13467 encode_thumb32_shifted_operand (2);
13473 if (warn_on_deprecated
13474 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13475 as_tsktsk (_("setend use is deprecated for ARMv8"));
13477 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13478 if (inst
.operands
[0].imm
)
13479 inst
.instruction
|= 0x8;
13485 if (!inst
.operands
[1].present
)
13486 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13488 if (unified_syntax
)
13490 bfd_boolean narrow
;
13493 switch (inst
.instruction
)
13496 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13498 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13500 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13502 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13506 if (THUMB_SETS_FLAGS (inst
.instruction
))
13507 narrow
= !in_pred_block ();
13509 narrow
= in_pred_block ();
13510 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13512 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13514 if (inst
.operands
[2].isreg
13515 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13516 || inst
.operands
[2].reg
> 7))
13518 if (inst
.size_req
== 4)
13521 reject_bad_reg (inst
.operands
[0].reg
);
13522 reject_bad_reg (inst
.operands
[1].reg
);
13526 if (inst
.operands
[2].isreg
)
13528 reject_bad_reg (inst
.operands
[2].reg
);
13529 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13530 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13532 inst
.instruction
|= inst
.operands
[2].reg
;
13534 /* PR 12854: Error on extraneous shifts. */
13535 constraint (inst
.operands
[2].shifted
,
13536 _("extraneous shift as part of operand to shift insn"));
13540 inst
.operands
[1].shifted
= 1;
13541 inst
.operands
[1].shift_kind
= shift_kind
;
13542 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13543 ? T_MNEM_movs
: T_MNEM_mov
);
13544 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13545 encode_thumb32_shifted_operand (1);
13546 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13547 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13552 if (inst
.operands
[2].isreg
)
13554 switch (shift_kind
)
13556 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13557 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13558 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13559 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13563 inst
.instruction
|= inst
.operands
[0].reg
;
13564 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13566 /* PR 12854: Error on extraneous shifts. */
13567 constraint (inst
.operands
[2].shifted
,
13568 _("extraneous shift as part of operand to shift insn"));
13572 switch (shift_kind
)
13574 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13575 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13576 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13579 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13580 inst
.instruction
|= inst
.operands
[0].reg
;
13581 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13587 constraint (inst
.operands
[0].reg
> 7
13588 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13589 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13591 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13593 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13594 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13595 _("source1 and dest must be same register"));
13597 switch (inst
.instruction
)
13599 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13600 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13601 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13602 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13606 inst
.instruction
|= inst
.operands
[0].reg
;
13607 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13609 /* PR 12854: Error on extraneous shifts. */
13610 constraint (inst
.operands
[2].shifted
,
13611 _("extraneous shift as part of operand to shift insn"));
13615 switch (inst
.instruction
)
13617 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13618 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13619 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13620 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13623 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13624 inst
.instruction
|= inst
.operands
[0].reg
;
13625 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13633 unsigned Rd
, Rn
, Rm
;
13635 Rd
= inst
.operands
[0].reg
;
13636 Rn
= inst
.operands
[1].reg
;
13637 Rm
= inst
.operands
[2].reg
;
13639 reject_bad_reg (Rd
);
13640 reject_bad_reg (Rn
);
13641 reject_bad_reg (Rm
);
13643 inst
.instruction
|= Rd
<< 8;
13644 inst
.instruction
|= Rn
<< 16;
13645 inst
.instruction
|= Rm
;
13651 unsigned Rd
, Rn
, Rm
;
13653 Rd
= inst
.operands
[0].reg
;
13654 Rm
= inst
.operands
[1].reg
;
13655 Rn
= inst
.operands
[2].reg
;
13657 reject_bad_reg (Rd
);
13658 reject_bad_reg (Rn
);
13659 reject_bad_reg (Rm
);
13661 inst
.instruction
|= Rd
<< 8;
13662 inst
.instruction
|= Rn
<< 16;
13663 inst
.instruction
|= Rm
;
13669 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13671 _("SMC is not permitted on this architecture"));
13672 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13673 _("expression too complex"));
13674 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13675 inst
.instruction
|= (value
& 0xf000) >> 12;
13676 inst
.instruction
|= (value
& 0x0ff0);
13677 inst
.instruction
|= (value
& 0x000f) << 16;
13678 /* PR gas/15623: SMC instructions must be last in an IT block. */
13679 set_pred_insn_type_last ();
13685 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13687 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13688 inst
.instruction
|= (value
& 0x0fff);
13689 inst
.instruction
|= (value
& 0xf000) << 4;
13693 do_t_ssat_usat (int bias
)
13697 Rd
= inst
.operands
[0].reg
;
13698 Rn
= inst
.operands
[2].reg
;
13700 reject_bad_reg (Rd
);
13701 reject_bad_reg (Rn
);
13703 inst
.instruction
|= Rd
<< 8;
13704 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13705 inst
.instruction
|= Rn
<< 16;
13707 if (inst
.operands
[3].present
)
13709 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13711 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13713 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13714 _("expression too complex"));
13716 if (shift_amount
!= 0)
13718 constraint (shift_amount
> 31,
13719 _("shift expression is too large"));
13721 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13722 inst
.instruction
|= 0x00200000; /* sh bit. */
13724 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13725 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13733 do_t_ssat_usat (1);
13741 Rd
= inst
.operands
[0].reg
;
13742 Rn
= inst
.operands
[2].reg
;
13744 reject_bad_reg (Rd
);
13745 reject_bad_reg (Rn
);
13747 inst
.instruction
|= Rd
<< 8;
13748 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13749 inst
.instruction
|= Rn
<< 16;
13755 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13756 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13757 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13758 || inst
.operands
[2].negative
,
13761 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13763 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13764 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13765 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13766 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13772 if (!inst
.operands
[2].present
)
13773 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13775 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13776 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13777 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13780 inst
.instruction
|= inst
.operands
[0].reg
;
13781 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13782 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13783 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13789 unsigned Rd
, Rn
, Rm
;
13791 Rd
= inst
.operands
[0].reg
;
13792 Rn
= inst
.operands
[1].reg
;
13793 Rm
= inst
.operands
[2].reg
;
13795 reject_bad_reg (Rd
);
13796 reject_bad_reg (Rn
);
13797 reject_bad_reg (Rm
);
13799 inst
.instruction
|= Rd
<< 8;
13800 inst
.instruction
|= Rn
<< 16;
13801 inst
.instruction
|= Rm
;
13802 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13810 Rd
= inst
.operands
[0].reg
;
13811 Rm
= inst
.operands
[1].reg
;
13813 reject_bad_reg (Rd
);
13814 reject_bad_reg (Rm
);
13816 if (inst
.instruction
<= 0xffff
13817 && inst
.size_req
!= 4
13818 && Rd
<= 7 && Rm
<= 7
13819 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13822 inst
.instruction
|= Rd
;
13823 inst
.instruction
|= Rm
<< 3;
13825 else if (unified_syntax
)
13827 if (inst
.instruction
<= 0xffff)
13828 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13829 inst
.instruction
|= Rd
<< 8;
13830 inst
.instruction
|= Rm
;
13831 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13835 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13836 _("Thumb encoding does not support rotation"));
13837 constraint (1, BAD_HIREG
);
13844 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13853 half
= (inst
.instruction
& 0x10) != 0;
13854 set_pred_insn_type_last ();
13855 constraint (inst
.operands
[0].immisreg
,
13856 _("instruction requires register index"));
13858 Rn
= inst
.operands
[0].reg
;
13859 Rm
= inst
.operands
[0].imm
;
13861 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13862 constraint (Rn
== REG_SP
, BAD_SP
);
13863 reject_bad_reg (Rm
);
13865 constraint (!half
&& inst
.operands
[0].shifted
,
13866 _("instruction does not allow shifted index"));
13867 inst
.instruction
|= (Rn
<< 16) | Rm
;
13873 if (!inst
.operands
[0].present
)
13874 inst
.operands
[0].imm
= 0;
13876 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13878 constraint (inst
.size_req
== 2,
13879 _("immediate value out of range"));
13880 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13881 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13882 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13887 inst
.instruction
|= inst
.operands
[0].imm
;
13890 set_pred_insn_type (NEUTRAL_IT_INSN
);
13897 do_t_ssat_usat (0);
13905 Rd
= inst
.operands
[0].reg
;
13906 Rn
= inst
.operands
[2].reg
;
13908 reject_bad_reg (Rd
);
13909 reject_bad_reg (Rn
);
13911 inst
.instruction
|= Rd
<< 8;
13912 inst
.instruction
|= inst
.operands
[1].imm
;
13913 inst
.instruction
|= Rn
<< 16;
13916 /* Checking the range of the branch offset (VAL) with NBITS bits
13917 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13919 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13921 gas_assert (nbits
> 0 && nbits
<= 32);
13924 int cmp
= (1 << (nbits
- 1));
13925 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13930 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13936 /* For branches in Armv8.1-M Mainline. */
13938 do_t_branch_future (void)
13940 unsigned long insn
= inst
.instruction
;
13942 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13943 if (inst
.operands
[0].hasreloc
== 0)
13945 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13946 as_bad (BAD_BRANCH_OFF
);
13948 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13952 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13953 inst
.relocs
[0].pc_rel
= 1;
13959 if (inst
.operands
[1].hasreloc
== 0)
13961 int val
= inst
.operands
[1].imm
;
13962 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13963 as_bad (BAD_BRANCH_OFF
);
13965 int immA
= (val
& 0x0001f000) >> 12;
13966 int immB
= (val
& 0x00000ffc) >> 2;
13967 int immC
= (val
& 0x00000002) >> 1;
13968 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13972 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13973 inst
.relocs
[1].pc_rel
= 1;
13978 if (inst
.operands
[1].hasreloc
== 0)
13980 int val
= inst
.operands
[1].imm
;
13981 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13982 as_bad (BAD_BRANCH_OFF
);
13984 int immA
= (val
& 0x0007f000) >> 12;
13985 int immB
= (val
& 0x00000ffc) >> 2;
13986 int immC
= (val
& 0x00000002) >> 1;
13987 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13991 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
13992 inst
.relocs
[1].pc_rel
= 1;
13996 case T_MNEM_bfcsel
:
13998 if (inst
.operands
[1].hasreloc
== 0)
14000 int val
= inst
.operands
[1].imm
;
14001 int immA
= (val
& 0x00001000) >> 12;
14002 int immB
= (val
& 0x00000ffc) >> 2;
14003 int immC
= (val
& 0x00000002) >> 1;
14004 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14008 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14009 inst
.relocs
[1].pc_rel
= 1;
14013 if (inst
.operands
[2].hasreloc
== 0)
14015 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14016 int val2
= inst
.operands
[2].imm
;
14017 int val0
= inst
.operands
[0].imm
& 0x1f;
14018 int diff
= val2
- val0
;
14020 inst
.instruction
|= 1 << 17; /* T bit. */
14021 else if (diff
!= 2)
14022 as_bad (_("out of range label-relative fixup value"));
14026 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14027 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14028 inst
.relocs
[2].pc_rel
= 1;
14032 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14033 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14038 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14045 /* Helper function for do_t_loloop to handle relocations. */
14047 v8_1_loop_reloc (int is_le
)
14049 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14051 int value
= inst
.relocs
[0].exp
.X_add_number
;
14052 value
= (is_le
) ? -value
: value
;
14054 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14055 as_bad (BAD_BRANCH_OFF
);
14059 immh
= (value
& 0x00000ffc) >> 2;
14060 imml
= (value
& 0x00000002) >> 1;
14062 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14066 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14067 inst
.relocs
[0].pc_rel
= 1;
14071 /* To handle the Scalar Low Overhead Loop instructions
14072 in Armv8.1-M Mainline. */
14076 unsigned long insn
= inst
.instruction
;
14078 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14079 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14085 if (!inst
.operands
[0].present
)
14086 inst
.instruction
|= 1 << 21;
14088 v8_1_loop_reloc (TRUE
);
14092 v8_1_loop_reloc (FALSE
);
14093 /* Fall through. */
14095 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14096 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14103 /* MVE instruction encoder helpers. */
14104 #define M_MNEM_vabav 0xee800f01
14105 #define M_MNEM_vmladav 0xeef00e00
14106 #define M_MNEM_vmladava 0xeef00e20
14107 #define M_MNEM_vmladavx 0xeef01e00
14108 #define M_MNEM_vmladavax 0xeef01e20
14109 #define M_MNEM_vmlsdav 0xeef00e01
14110 #define M_MNEM_vmlsdava 0xeef00e21
14111 #define M_MNEM_vmlsdavx 0xeef01e01
14112 #define M_MNEM_vmlsdavax 0xeef01e21
14113 #define M_MNEM_vmullt 0xee011e00
14114 #define M_MNEM_vmullb 0xee010e00
14115 #define M_MNEM_vst20 0xfc801e00
14116 #define M_MNEM_vst21 0xfc801e20
14117 #define M_MNEM_vst40 0xfc801e01
14118 #define M_MNEM_vst41 0xfc801e21
14119 #define M_MNEM_vst42 0xfc801e41
14120 #define M_MNEM_vst43 0xfc801e61
14121 #define M_MNEM_vld20 0xfc901e00
14122 #define M_MNEM_vld21 0xfc901e20
14123 #define M_MNEM_vld40 0xfc901e01
14124 #define M_MNEM_vld41 0xfc901e21
14125 #define M_MNEM_vld42 0xfc901e41
14126 #define M_MNEM_vld43 0xfc901e61
14127 #define M_MNEM_vstrb 0xec000e00
14128 #define M_MNEM_vstrh 0xec000e10
14129 #define M_MNEM_vstrw 0xec000e40
14130 #define M_MNEM_vstrd 0xec000e50
14131 #define M_MNEM_vldrb 0xec100e00
14132 #define M_MNEM_vldrh 0xec100e10
14133 #define M_MNEM_vldrw 0xec100e40
14134 #define M_MNEM_vldrd 0xec100e50
14135 #define M_MNEM_vmovlt 0xeea01f40
14136 #define M_MNEM_vmovlb 0xeea00f40
14137 #define M_MNEM_vmovnt 0xfe311e81
14138 #define M_MNEM_vmovnb 0xfe310e81
14140 /* Neon instruction encoder helpers. */
14142 /* Encodings for the different types for various Neon opcodes. */
14144 /* An "invalid" code for the following tables. */
14147 struct neon_tab_entry
14150 unsigned float_or_poly
;
14151 unsigned scalar_or_imm
;
14154 /* Map overloaded Neon opcodes to their respective encodings. */
14155 #define NEON_ENC_TAB \
14156 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14157 X(vabdl, 0x0800700, N_INV, N_INV), \
14158 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14159 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14160 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14161 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14162 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14163 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14164 X(vaddl, 0x0800000, N_INV, N_INV), \
14165 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14166 X(vsubl, 0x0800200, N_INV, N_INV), \
14167 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14168 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14169 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14170 /* Register variants of the following two instructions are encoded as
14171 vcge / vcgt with the operands reversed. */ \
14172 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14173 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14174 X(vfma, N_INV, 0x0000c10, N_INV), \
14175 X(vfms, N_INV, 0x0200c10, N_INV), \
14176 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14177 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14178 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14179 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14180 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14181 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14182 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14183 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14184 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14185 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14186 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14187 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14188 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14189 X(vshl, 0x0000400, N_INV, 0x0800510), \
14190 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14191 X(vand, 0x0000110, N_INV, 0x0800030), \
14192 X(vbic, 0x0100110, N_INV, 0x0800030), \
14193 X(veor, 0x1000110, N_INV, N_INV), \
14194 X(vorn, 0x0300110, N_INV, 0x0800010), \
14195 X(vorr, 0x0200110, N_INV, 0x0800010), \
14196 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14197 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14198 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14199 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14200 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14201 X(vst1, 0x0000000, 0x0800000, N_INV), \
14202 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14203 X(vst2, 0x0000100, 0x0800100, N_INV), \
14204 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14205 X(vst3, 0x0000200, 0x0800200, N_INV), \
14206 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14207 X(vst4, 0x0000300, 0x0800300, N_INV), \
14208 X(vmovn, 0x1b20200, N_INV, N_INV), \
14209 X(vtrn, 0x1b20080, N_INV, N_INV), \
14210 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14211 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14212 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14213 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14214 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14215 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14216 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14217 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14218 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14219 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14220 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14221 X(vseleq, 0xe000a00, N_INV, N_INV), \
14222 X(vselvs, 0xe100a00, N_INV, N_INV), \
14223 X(vselge, 0xe200a00, N_INV, N_INV), \
14224 X(vselgt, 0xe300a00, N_INV, N_INV), \
14225 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14226 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14227 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14228 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14229 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14230 X(aes, 0x3b00300, N_INV, N_INV), \
14231 X(sha3op, 0x2000c00, N_INV, N_INV), \
14232 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14233 X(sha2op, 0x3ba0380, N_INV, N_INV)
14237 #define X(OPC,I,F,S) N_MNEM_##OPC
14242 static const struct neon_tab_entry neon_enc_tab
[] =
14244 #define X(OPC,I,F,S) { (I), (F), (S) }
14249 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14250 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14251 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14252 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14253 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14254 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14255 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14256 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14257 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14258 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14259 #define NEON_ENC_SINGLE_(X) \
14260 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14261 #define NEON_ENC_DOUBLE_(X) \
14262 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14263 #define NEON_ENC_FPV8_(X) \
14264 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14266 #define NEON_ENCODE(type, inst) \
14269 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14270 inst.is_neon = 1; \
14274 #define check_neon_suffixes \
14277 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14279 as_bad (_("invalid neon suffix for non neon instruction")); \
14285 /* Define shapes for instruction operands. The following mnemonic characters
14286 are used in this table:
14288 F - VFP S<n> register
14289 D - Neon D<n> register
14290 Q - Neon Q<n> register
14294 L - D<n> register list
14296 This table is used to generate various data:
14297 - enumerations of the form NS_DDR to be used as arguments to
14299 - a table classifying shapes into single, double, quad, mixed.
14300 - a table used to drive neon_select_shape. */
14302 #define NEON_SHAPE_DEF \
14303 X(4, (R, R, S, S), QUAD), \
14304 X(4, (S, S, R, R), QUAD), \
14305 X(3, (I, Q, Q), QUAD), \
14306 X(3, (I, Q, R), QUAD), \
14307 X(3, (R, Q, Q), QUAD), \
14308 X(3, (D, D, D), DOUBLE), \
14309 X(3, (Q, Q, Q), QUAD), \
14310 X(3, (D, D, I), DOUBLE), \
14311 X(3, (Q, Q, I), QUAD), \
14312 X(3, (D, D, S), DOUBLE), \
14313 X(3, (Q, Q, S), QUAD), \
14314 X(3, (Q, Q, R), QUAD), \
14315 X(2, (D, D), DOUBLE), \
14316 X(2, (Q, Q), QUAD), \
14317 X(2, (D, S), DOUBLE), \
14318 X(2, (Q, S), QUAD), \
14319 X(2, (D, R), DOUBLE), \
14320 X(2, (Q, R), QUAD), \
14321 X(2, (D, I), DOUBLE), \
14322 X(2, (Q, I), QUAD), \
14323 X(3, (D, L, D), DOUBLE), \
14324 X(2, (D, Q), MIXED), \
14325 X(2, (Q, D), MIXED), \
14326 X(3, (D, Q, I), MIXED), \
14327 X(3, (Q, D, I), MIXED), \
14328 X(3, (Q, D, D), MIXED), \
14329 X(3, (D, Q, Q), MIXED), \
14330 X(3, (Q, Q, D), MIXED), \
14331 X(3, (Q, D, S), MIXED), \
14332 X(3, (D, Q, S), MIXED), \
14333 X(4, (D, D, D, I), DOUBLE), \
14334 X(4, (Q, Q, Q, I), QUAD), \
14335 X(4, (D, D, S, I), DOUBLE), \
14336 X(4, (Q, Q, S, I), QUAD), \
14337 X(2, (F, F), SINGLE), \
14338 X(3, (F, F, F), SINGLE), \
14339 X(2, (F, I), SINGLE), \
14340 X(2, (F, D), MIXED), \
14341 X(2, (D, F), MIXED), \
14342 X(3, (F, F, I), MIXED), \
14343 X(4, (R, R, F, F), SINGLE), \
14344 X(4, (F, F, R, R), SINGLE), \
14345 X(3, (D, R, R), DOUBLE), \
14346 X(3, (R, R, D), DOUBLE), \
14347 X(2, (S, R), SINGLE), \
14348 X(2, (R, S), SINGLE), \
14349 X(2, (F, R), SINGLE), \
14350 X(2, (R, F), SINGLE), \
14351 /* Half float shape supported so far. */\
14352 X (2, (H, D), MIXED), \
14353 X (2, (D, H), MIXED), \
14354 X (2, (H, F), MIXED), \
14355 X (2, (F, H), MIXED), \
14356 X (2, (H, H), HALF), \
14357 X (2, (H, R), HALF), \
14358 X (2, (R, H), HALF), \
14359 X (2, (H, I), HALF), \
14360 X (3, (H, H, H), HALF), \
14361 X (3, (H, F, I), MIXED), \
14362 X (3, (F, H, I), MIXED), \
14363 X (3, (D, H, H), MIXED), \
14364 X (3, (D, H, S), MIXED)
14366 #define S2(A,B) NS_##A##B
14367 #define S3(A,B,C) NS_##A##B##C
14368 #define S4(A,B,C,D) NS_##A##B##C##D
14370 #define X(N, L, C) S##N L
14383 enum neon_shape_class
14392 #define X(N, L, C) SC_##C
14394 static enum neon_shape_class neon_shape_class
[] =
14413 /* Register widths of above. */
14414 static unsigned neon_shape_el_size
[] =
14426 struct neon_shape_info
14429 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14432 #define S2(A,B) { SE_##A, SE_##B }
14433 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14434 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14436 #define X(N, L, C) { N, S##N L }
14438 static struct neon_shape_info neon_shape_tab
[] =
14448 /* Bit masks used in type checking given instructions.
14449 'N_EQK' means the type must be the same as (or based on in some way) the key
14450 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14451 set, various other bits can be set as well in order to modify the meaning of
14452 the type constraint. */
14454 enum neon_type_mask
14478 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14479 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14480 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14481 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14482 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14483 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14484 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14485 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14486 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14487 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14488 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14490 N_MAX_NONSPECIAL
= N_P64
14493 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14495 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14496 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14497 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14498 #define N_S_32 (N_S8 | N_S16 | N_S32)
14499 #define N_F_16_32 (N_F16 | N_F32)
14500 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14501 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14502 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14503 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14504 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14505 #define N_F_MVE (N_F16 | N_F32)
14506 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14508 /* Pass this as the first type argument to neon_check_type to ignore types
14510 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14512 /* Select a "shape" for the current instruction (describing register types or
14513 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14514 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14515 function of operand parsing, so this function doesn't need to be called.
14516 Shapes should be listed in order of decreasing length. */
14518 static enum neon_shape
14519 neon_select_shape (enum neon_shape shape
, ...)
14522 enum neon_shape first_shape
= shape
;
14524 /* Fix missing optional operands. FIXME: we don't know at this point how
14525 many arguments we should have, so this makes the assumption that we have
14526 > 1. This is true of all current Neon opcodes, I think, but may not be
14527 true in the future. */
14528 if (!inst
.operands
[1].present
)
14529 inst
.operands
[1] = inst
.operands
[0];
14531 va_start (ap
, shape
);
14533 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14538 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14540 if (!inst
.operands
[j
].present
)
14546 switch (neon_shape_tab
[shape
].el
[j
])
14548 /* If a .f16, .16, .u16, .s16 type specifier is given over
14549 a VFP single precision register operand, it's essentially
14550 means only half of the register is used.
14552 If the type specifier is given after the mnemonics, the
14553 information is stored in inst.vectype. If the type specifier
14554 is given after register operand, the information is stored
14555 in inst.operands[].vectype.
14557 When there is only one type specifier, and all the register
14558 operands are the same type of hardware register, the type
14559 specifier applies to all register operands.
14561 If no type specifier is given, the shape is inferred from
14562 operand information.
14565 vadd.f16 s0, s1, s2: NS_HHH
14566 vabs.f16 s0, s1: NS_HH
14567 vmov.f16 s0, r1: NS_HR
14568 vmov.f16 r0, s1: NS_RH
14569 vcvt.f16 r0, s1: NS_RH
14570 vcvt.f16.s32 s2, s2, #29: NS_HFI
14571 vcvt.f16.s32 s2, s2: NS_HF
14574 if (!(inst
.operands
[j
].isreg
14575 && inst
.operands
[j
].isvec
14576 && inst
.operands
[j
].issingle
14577 && !inst
.operands
[j
].isquad
14578 && ((inst
.vectype
.elems
== 1
14579 && inst
.vectype
.el
[0].size
== 16)
14580 || (inst
.vectype
.elems
> 1
14581 && inst
.vectype
.el
[j
].size
== 16)
14582 || (inst
.vectype
.elems
== 0
14583 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14584 && inst
.operands
[j
].vectype
.size
== 16))))
14589 if (!(inst
.operands
[j
].isreg
14590 && inst
.operands
[j
].isvec
14591 && inst
.operands
[j
].issingle
14592 && !inst
.operands
[j
].isquad
14593 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14594 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14595 || (inst
.vectype
.elems
== 0
14596 && (inst
.operands
[j
].vectype
.size
== 32
14597 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14602 if (!(inst
.operands
[j
].isreg
14603 && inst
.operands
[j
].isvec
14604 && !inst
.operands
[j
].isquad
14605 && !inst
.operands
[j
].issingle
))
14610 if (!(inst
.operands
[j
].isreg
14611 && !inst
.operands
[j
].isvec
))
14616 if (!(inst
.operands
[j
].isreg
14617 && inst
.operands
[j
].isvec
14618 && inst
.operands
[j
].isquad
14619 && !inst
.operands
[j
].issingle
))
14624 if (!(!inst
.operands
[j
].isreg
14625 && !inst
.operands
[j
].isscalar
))
14630 if (!(!inst
.operands
[j
].isreg
14631 && inst
.operands
[j
].isscalar
))
14641 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14642 /* We've matched all the entries in the shape table, and we don't
14643 have any left over operands which have not been matched. */
14649 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14650 first_error (_("invalid instruction shape"));
14655 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14656 means the Q bit should be set). */
14659 neon_quad (enum neon_shape shape
)
14661 return neon_shape_class
[shape
] == SC_QUAD
;
14665 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14668 /* Allow modification to be made to types which are constrained to be
14669 based on the key element, based on bits set alongside N_EQK. */
14670 if ((typebits
& N_EQK
) != 0)
14672 if ((typebits
& N_HLF
) != 0)
14674 else if ((typebits
& N_DBL
) != 0)
14676 if ((typebits
& N_SGN
) != 0)
14677 *g_type
= NT_signed
;
14678 else if ((typebits
& N_UNS
) != 0)
14679 *g_type
= NT_unsigned
;
14680 else if ((typebits
& N_INT
) != 0)
14681 *g_type
= NT_integer
;
14682 else if ((typebits
& N_FLT
) != 0)
14683 *g_type
= NT_float
;
14684 else if ((typebits
& N_SIZ
) != 0)
14685 *g_type
= NT_untyped
;
14689 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14690 operand type, i.e. the single type specified in a Neon instruction when it
14691 is the only one given. */
14693 static struct neon_type_el
14694 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14696 struct neon_type_el dest
= *key
;
14698 gas_assert ((thisarg
& N_EQK
) != 0);
14700 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14705 /* Convert Neon type and size into compact bitmask representation. */
14707 static enum neon_type_mask
14708 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14715 case 8: return N_8
;
14716 case 16: return N_16
;
14717 case 32: return N_32
;
14718 case 64: return N_64
;
14726 case 8: return N_I8
;
14727 case 16: return N_I16
;
14728 case 32: return N_I32
;
14729 case 64: return N_I64
;
14737 case 16: return N_F16
;
14738 case 32: return N_F32
;
14739 case 64: return N_F64
;
14747 case 8: return N_P8
;
14748 case 16: return N_P16
;
14749 case 64: return N_P64
;
14757 case 8: return N_S8
;
14758 case 16: return N_S16
;
14759 case 32: return N_S32
;
14760 case 64: return N_S64
;
14768 case 8: return N_U8
;
14769 case 16: return N_U16
;
14770 case 32: return N_U32
;
14771 case 64: return N_U64
;
14782 /* Convert compact Neon bitmask type representation to a type and size. Only
14783 handles the case where a single bit is set in the mask. */
14786 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14787 enum neon_type_mask mask
)
14789 if ((mask
& N_EQK
) != 0)
14792 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14794 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14796 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14798 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14803 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14805 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14806 *type
= NT_unsigned
;
14807 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14808 *type
= NT_integer
;
14809 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14810 *type
= NT_untyped
;
14811 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14813 else if ((mask
& (N_F_ALL
)) != 0)
14821 /* Modify a bitmask of allowed types. This is only needed for type
14825 modify_types_allowed (unsigned allowed
, unsigned mods
)
14828 enum neon_el_type type
;
14834 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14836 if (el_type_of_type_chk (&type
, &size
,
14837 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14839 neon_modify_type_size (mods
, &type
, &size
);
14840 destmask
|= type_chk_of_el_type (type
, size
);
14847 /* Check type and return type classification.
14848 The manual states (paraphrase): If one datatype is given, it indicates the
14850 - the second operand, if there is one
14851 - the operand, if there is no second operand
14852 - the result, if there are no operands.
14853 This isn't quite good enough though, so we use a concept of a "key" datatype
14854 which is set on a per-instruction basis, which is the one which matters when
14855 only one data type is written.
14856 Note: this function has side-effects (e.g. filling in missing operands). All
14857 Neon instructions should call it before performing bit encoding. */
14859 static struct neon_type_el
14860 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14863 unsigned i
, pass
, key_el
= 0;
14864 unsigned types
[NEON_MAX_TYPE_ELS
];
14865 enum neon_el_type k_type
= NT_invtype
;
14866 unsigned k_size
= -1u;
14867 struct neon_type_el badtype
= {NT_invtype
, -1};
14868 unsigned key_allowed
= 0;
14870 /* Optional registers in Neon instructions are always (not) in operand 1.
14871 Fill in the missing operand here, if it was omitted. */
14872 if (els
> 1 && !inst
.operands
[1].present
)
14873 inst
.operands
[1] = inst
.operands
[0];
14875 /* Suck up all the varargs. */
14877 for (i
= 0; i
< els
; i
++)
14879 unsigned thisarg
= va_arg (ap
, unsigned);
14880 if (thisarg
== N_IGNORE_TYPE
)
14885 types
[i
] = thisarg
;
14886 if ((thisarg
& N_KEY
) != 0)
14891 if (inst
.vectype
.elems
> 0)
14892 for (i
= 0; i
< els
; i
++)
14893 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14895 first_error (_("types specified in both the mnemonic and operands"));
14899 /* Duplicate inst.vectype elements here as necessary.
14900 FIXME: No idea if this is exactly the same as the ARM assembler,
14901 particularly when an insn takes one register and one non-register
14903 if (inst
.vectype
.elems
== 1 && els
> 1)
14906 inst
.vectype
.elems
= els
;
14907 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14908 for (j
= 0; j
< els
; j
++)
14910 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14913 else if (inst
.vectype
.elems
== 0 && els
> 0)
14916 /* No types were given after the mnemonic, so look for types specified
14917 after each operand. We allow some flexibility here; as long as the
14918 "key" operand has a type, we can infer the others. */
14919 for (j
= 0; j
< els
; j
++)
14920 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14921 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14923 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14925 for (j
= 0; j
< els
; j
++)
14926 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14927 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14932 first_error (_("operand types can't be inferred"));
14936 else if (inst
.vectype
.elems
!= els
)
14938 first_error (_("type specifier has the wrong number of parts"));
14942 for (pass
= 0; pass
< 2; pass
++)
14944 for (i
= 0; i
< els
; i
++)
14946 unsigned thisarg
= types
[i
];
14947 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14948 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14949 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14950 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14952 /* Decay more-specific signed & unsigned types to sign-insensitive
14953 integer types if sign-specific variants are unavailable. */
14954 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14955 && (types_allowed
& N_SU_ALL
) == 0)
14956 g_type
= NT_integer
;
14958 /* If only untyped args are allowed, decay any more specific types to
14959 them. Some instructions only care about signs for some element
14960 sizes, so handle that properly. */
14961 if (((types_allowed
& N_UNT
) == 0)
14962 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14963 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14964 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14965 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14966 g_type
= NT_untyped
;
14970 if ((thisarg
& N_KEY
) != 0)
14974 key_allowed
= thisarg
& ~N_KEY
;
14976 /* Check architecture constraint on FP16 extension. */
14978 && k_type
== NT_float
14979 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14981 inst
.error
= _(BAD_FP16
);
14988 if ((thisarg
& N_VFP
) != 0)
14990 enum neon_shape_el regshape
;
14991 unsigned regwidth
, match
;
14993 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14996 first_error (_("invalid instruction shape"));
14999 regshape
= neon_shape_tab
[ns
].el
[i
];
15000 regwidth
= neon_shape_el_size
[regshape
];
15002 /* In VFP mode, operands must match register widths. If we
15003 have a key operand, use its width, else use the width of
15004 the current operand. */
15010 /* FP16 will use a single precision register. */
15011 if (regwidth
== 32 && match
== 16)
15013 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15017 inst
.error
= _(BAD_FP16
);
15022 if (regwidth
!= match
)
15024 first_error (_("operand size must match register width"));
15029 if ((thisarg
& N_EQK
) == 0)
15031 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15033 if ((given_type
& types_allowed
) == 0)
15035 first_error (BAD_SIMD_TYPE
);
15041 enum neon_el_type mod_k_type
= k_type
;
15042 unsigned mod_k_size
= k_size
;
15043 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15044 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15046 first_error (_("inconsistent types in Neon instruction"));
15054 return inst
.vectype
.el
[key_el
];
15057 /* Neon-style VFP instruction forwarding. */
15059 /* Thumb VFP instructions have 0xE in the condition field. */
15062 do_vfp_cond_or_thumb (void)
15067 inst
.instruction
|= 0xe0000000;
15069 inst
.instruction
|= inst
.cond
<< 28;
15072 /* Look up and encode a simple mnemonic, for use as a helper function for the
15073 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15074 etc. It is assumed that operand parsing has already been done, and that the
15075 operands are in the form expected by the given opcode (this isn't necessarily
15076 the same as the form in which they were parsed, hence some massaging must
15077 take place before this function is called).
15078 Checks current arch version against that in the looked-up opcode. */
15081 do_vfp_nsyn_opcode (const char *opname
)
15083 const struct asm_opcode
*opcode
;
15085 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15090 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15091 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15098 inst
.instruction
= opcode
->tvalue
;
15099 opcode
->tencode ();
15103 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15104 opcode
->aencode ();
15109 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15111 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15113 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15116 do_vfp_nsyn_opcode ("fadds");
15118 do_vfp_nsyn_opcode ("fsubs");
15120 /* ARMv8.2 fp16 instruction. */
15122 do_scalar_fp16_v82_encode ();
15127 do_vfp_nsyn_opcode ("faddd");
15129 do_vfp_nsyn_opcode ("fsubd");
15133 /* Check operand types to see if this is a VFP instruction, and if so call
15137 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15139 enum neon_shape rs
;
15140 struct neon_type_el et
;
15145 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15146 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15150 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15151 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15152 N_F_ALL
| N_KEY
| N_VFP
);
15159 if (et
.type
!= NT_invtype
)
15170 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15172 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15174 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15177 do_vfp_nsyn_opcode ("fmacs");
15179 do_vfp_nsyn_opcode ("fnmacs");
15181 /* ARMv8.2 fp16 instruction. */
15183 do_scalar_fp16_v82_encode ();
15188 do_vfp_nsyn_opcode ("fmacd");
15190 do_vfp_nsyn_opcode ("fnmacd");
15195 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15197 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15199 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15202 do_vfp_nsyn_opcode ("ffmas");
15204 do_vfp_nsyn_opcode ("ffnmas");
15206 /* ARMv8.2 fp16 instruction. */
15208 do_scalar_fp16_v82_encode ();
15213 do_vfp_nsyn_opcode ("ffmad");
15215 do_vfp_nsyn_opcode ("ffnmad");
15220 do_vfp_nsyn_mul (enum neon_shape rs
)
15222 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15224 do_vfp_nsyn_opcode ("fmuls");
15226 /* ARMv8.2 fp16 instruction. */
15228 do_scalar_fp16_v82_encode ();
15231 do_vfp_nsyn_opcode ("fmuld");
15235 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15237 int is_neg
= (inst
.instruction
& 0x80) != 0;
15238 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15240 if (rs
== NS_FF
|| rs
== NS_HH
)
15243 do_vfp_nsyn_opcode ("fnegs");
15245 do_vfp_nsyn_opcode ("fabss");
15247 /* ARMv8.2 fp16 instruction. */
15249 do_scalar_fp16_v82_encode ();
15254 do_vfp_nsyn_opcode ("fnegd");
15256 do_vfp_nsyn_opcode ("fabsd");
15260 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15261 insns belong to Neon, and are handled elsewhere. */
15264 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15266 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15270 do_vfp_nsyn_opcode ("fldmdbs");
15272 do_vfp_nsyn_opcode ("fldmias");
15277 do_vfp_nsyn_opcode ("fstmdbs");
15279 do_vfp_nsyn_opcode ("fstmias");
15284 do_vfp_nsyn_sqrt (void)
15286 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15287 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15289 if (rs
== NS_FF
|| rs
== NS_HH
)
15291 do_vfp_nsyn_opcode ("fsqrts");
15293 /* ARMv8.2 fp16 instruction. */
15295 do_scalar_fp16_v82_encode ();
15298 do_vfp_nsyn_opcode ("fsqrtd");
15302 do_vfp_nsyn_div (void)
15304 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15305 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15306 N_F_ALL
| N_KEY
| N_VFP
);
15308 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15310 do_vfp_nsyn_opcode ("fdivs");
15312 /* ARMv8.2 fp16 instruction. */
15314 do_scalar_fp16_v82_encode ();
15317 do_vfp_nsyn_opcode ("fdivd");
15321 do_vfp_nsyn_nmul (void)
15323 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15324 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15325 N_F_ALL
| N_KEY
| N_VFP
);
15327 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15329 NEON_ENCODE (SINGLE
, inst
);
15330 do_vfp_sp_dyadic ();
15332 /* ARMv8.2 fp16 instruction. */
15334 do_scalar_fp16_v82_encode ();
15338 NEON_ENCODE (DOUBLE
, inst
);
15339 do_vfp_dp_rd_rn_rm ();
15341 do_vfp_cond_or_thumb ();
15345 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15349 neon_logbits (unsigned x
)
15351 return ffs (x
) - 4;
15354 #define LOW4(R) ((R) & 0xf)
15355 #define HI1(R) (((R) >> 4) & 1)
15358 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15363 first_error (BAD_EL_TYPE
);
15366 switch (inst
.operands
[0].imm
)
15369 first_error (_("invalid condition"));
15391 /* only accept eq and ne. */
15392 if (inst
.operands
[0].imm
> 1)
15394 first_error (_("invalid condition"));
15397 return inst
.operands
[0].imm
;
15399 if (inst
.operands
[0].imm
== 0x2)
15401 else if (inst
.operands
[0].imm
== 0x8)
15405 first_error (_("invalid condition"));
15409 switch (inst
.operands
[0].imm
)
15412 first_error (_("invalid condition"));
15428 /* Should be unreachable. */
15435 /* We are dealing with a vector predicated block. */
15436 if (inst
.operands
[0].present
)
15438 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15439 struct neon_type_el et
15440 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15443 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15445 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15447 if (et
.type
== NT_invtype
)
15450 if (et
.type
== NT_float
)
15452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15454 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15455 inst
.instruction
|= (et
.size
== 16) << 28;
15456 inst
.instruction
|= 0x3 << 20;
15460 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15462 inst
.instruction
|= 1 << 28;
15463 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15466 if (inst
.operands
[2].isquad
)
15468 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15469 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15470 inst
.instruction
|= (fcond
& 0x2) >> 1;
15474 if (inst
.operands
[2].reg
== REG_SP
)
15475 as_tsktsk (MVE_BAD_SP
);
15476 inst
.instruction
|= 1 << 6;
15477 inst
.instruction
|= (fcond
& 0x2) << 4;
15478 inst
.instruction
|= inst
.operands
[2].reg
;
15480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15481 inst
.instruction
|= (fcond
& 0x4) << 10;
15482 inst
.instruction
|= (fcond
& 0x1) << 7;
15485 set_pred_insn_type (VPT_INSN
);
15487 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15488 | ((inst
.instruction
& 0xe000) >> 13);
15489 now_pred
.warn_deprecated
= FALSE
;
15490 now_pred
.type
= VECTOR_PRED
;
15497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15498 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15499 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15500 if (!inst
.operands
[2].present
)
15501 first_error (_("MVE vector or ARM register expected"));
15502 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15504 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15505 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15506 && inst
.operands
[1].isquad
)
15508 inst
.instruction
= N_MNEM_vcmp
;
15512 if (inst
.cond
> COND_ALWAYS
)
15513 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15515 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15517 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15518 struct neon_type_el et
15519 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15522 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15523 && !inst
.operands
[2].iszr
, BAD_PC
);
15525 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15527 inst
.instruction
= 0xee010f00;
15528 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15529 inst
.instruction
|= (fcond
& 0x4) << 10;
15530 inst
.instruction
|= (fcond
& 0x1) << 7;
15531 if (et
.type
== NT_float
)
15533 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15535 inst
.instruction
|= (et
.size
== 16) << 28;
15536 inst
.instruction
|= 0x3 << 20;
15540 inst
.instruction
|= 1 << 28;
15541 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15543 if (inst
.operands
[2].isquad
)
15545 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15546 inst
.instruction
|= (fcond
& 0x2) >> 1;
15547 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15551 if (inst
.operands
[2].reg
== REG_SP
)
15552 as_tsktsk (MVE_BAD_SP
);
15553 inst
.instruction
|= 1 << 6;
15554 inst
.instruction
|= (fcond
& 0x2) << 4;
15555 inst
.instruction
|= inst
.operands
[2].reg
;
15563 do_vfp_nsyn_cmp (void)
15565 enum neon_shape rs
;
15566 if (!inst
.operands
[0].isreg
)
15573 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15578 if (inst
.operands
[1].isreg
)
15580 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15581 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15583 if (rs
== NS_FF
|| rs
== NS_HH
)
15585 NEON_ENCODE (SINGLE
, inst
);
15586 do_vfp_sp_monadic ();
15590 NEON_ENCODE (DOUBLE
, inst
);
15591 do_vfp_dp_rd_rm ();
15596 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15597 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15599 switch (inst
.instruction
& 0x0fffffff)
15602 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15605 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15611 if (rs
== NS_FI
|| rs
== NS_HI
)
15613 NEON_ENCODE (SINGLE
, inst
);
15614 do_vfp_sp_compare_z ();
15618 NEON_ENCODE (DOUBLE
, inst
);
15622 do_vfp_cond_or_thumb ();
15624 /* ARMv8.2 fp16 instruction. */
15625 if (rs
== NS_HI
|| rs
== NS_HH
)
15626 do_scalar_fp16_v82_encode ();
15630 nsyn_insert_sp (void)
15632 inst
.operands
[1] = inst
.operands
[0];
15633 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15634 inst
.operands
[0].reg
= REG_SP
;
15635 inst
.operands
[0].isreg
= 1;
15636 inst
.operands
[0].writeback
= 1;
15637 inst
.operands
[0].present
= 1;
15641 do_vfp_nsyn_push (void)
15645 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15646 _("register list must contain at least 1 and at most 16 "
15649 if (inst
.operands
[1].issingle
)
15650 do_vfp_nsyn_opcode ("fstmdbs");
15652 do_vfp_nsyn_opcode ("fstmdbd");
15656 do_vfp_nsyn_pop (void)
15660 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15661 _("register list must contain at least 1 and at most 16 "
15664 if (inst
.operands
[1].issingle
)
15665 do_vfp_nsyn_opcode ("fldmias");
15667 do_vfp_nsyn_opcode ("fldmiad");
15670 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15671 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15674 neon_dp_fixup (struct arm_it
* insn
)
15676 unsigned int i
= insn
->instruction
;
15681 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15692 insn
->instruction
= i
;
15696 mve_encode_qqr (int size
, int fp
)
15698 if (inst
.operands
[2].reg
== REG_SP
)
15699 as_tsktsk (MVE_BAD_SP
);
15700 else if (inst
.operands
[2].reg
== REG_PC
)
15701 as_tsktsk (MVE_BAD_PC
);
15706 if (((unsigned)inst
.instruction
) == 0xd00)
15707 inst
.instruction
= 0xee300f40;
15709 else if (((unsigned)inst
.instruction
) == 0x200d00)
15710 inst
.instruction
= 0xee301f40;
15712 /* Setting size which is 1 for F16 and 0 for F32. */
15713 inst
.instruction
|= (size
== 16) << 28;
15718 if (((unsigned)inst
.instruction
) == 0x800)
15719 inst
.instruction
= 0xee010f40;
15721 else if (((unsigned)inst
.instruction
) == 0x1000800)
15722 inst
.instruction
= 0xee011f40;
15723 /* Setting bits for size. */
15724 inst
.instruction
|= neon_logbits (size
) << 20;
15726 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15727 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15729 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15730 inst
.instruction
|= inst
.operands
[2].reg
;
15735 mve_encode_rqq (unsigned bit28
, unsigned size
)
15737 inst
.instruction
|= bit28
<< 28;
15738 inst
.instruction
|= neon_logbits (size
) << 20;
15739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15740 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15742 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15743 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15748 mve_encode_qqq (int ubit
, int size
)
15751 inst
.instruction
|= (ubit
!= 0) << 28;
15752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15753 inst
.instruction
|= neon_logbits (size
) << 20;
15754 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15756 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15757 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15758 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15764 /* Encode insns with bit pattern:
15766 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15767 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15769 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15770 different meaning for some instruction. */
15773 neon_three_same (int isquad
, int ubit
, int size
)
15775 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15776 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15777 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15778 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15779 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15780 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15781 inst
.instruction
|= (isquad
!= 0) << 6;
15782 inst
.instruction
|= (ubit
!= 0) << 24;
15784 inst
.instruction
|= neon_logbits (size
) << 20;
15786 neon_dp_fixup (&inst
);
15789 /* Encode instructions of the form:
15791 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15792 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15794 Don't write size if SIZE == -1. */
15797 neon_two_same (int qbit
, int ubit
, int size
)
15799 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15800 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15801 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15802 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15803 inst
.instruction
|= (qbit
!= 0) << 6;
15804 inst
.instruction
|= (ubit
!= 0) << 24;
15807 inst
.instruction
|= neon_logbits (size
) << 18;
15809 neon_dp_fixup (&inst
);
15812 /* Neon instruction encoders, in approximate order of appearance. */
15815 do_neon_dyadic_i_su (void)
15817 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15818 struct neon_type_el et
= neon_check_type (3, rs
,
15819 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15820 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15824 do_neon_dyadic_i64_su (void)
15826 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15827 struct neon_type_el et
= neon_check_type (3, rs
,
15828 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15829 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15833 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15836 unsigned size
= et
.size
>> 3;
15837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15841 inst
.instruction
|= (isquad
!= 0) << 6;
15842 inst
.instruction
|= immbits
<< 16;
15843 inst
.instruction
|= (size
>> 3) << 7;
15844 inst
.instruction
|= (size
& 0x7) << 19;
15846 inst
.instruction
|= (uval
!= 0) << 24;
15848 neon_dp_fixup (&inst
);
15852 do_neon_shl_imm (void)
15854 if (!inst
.operands
[2].isreg
)
15856 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15857 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15858 int imm
= inst
.operands
[2].imm
;
15860 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15861 _("immediate out of range for shift"));
15862 NEON_ENCODE (IMMED
, inst
);
15863 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15867 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15868 struct neon_type_el et
= neon_check_type (3, rs
,
15869 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15872 /* VSHL/VQSHL 3-register variants have syntax such as:
15874 whereas other 3-register operations encoded by neon_three_same have
15877 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15879 tmp
= inst
.operands
[2].reg
;
15880 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15881 inst
.operands
[1].reg
= tmp
;
15882 NEON_ENCODE (INTEGER
, inst
);
15883 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15888 do_neon_qshl_imm (void)
15890 if (!inst
.operands
[2].isreg
)
15892 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15893 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15894 int imm
= inst
.operands
[2].imm
;
15896 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15897 _("immediate out of range for shift"));
15898 NEON_ENCODE (IMMED
, inst
);
15899 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15903 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15904 struct neon_type_el et
= neon_check_type (3, rs
,
15905 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15908 /* See note in do_neon_shl_imm. */
15909 tmp
= inst
.operands
[2].reg
;
15910 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15911 inst
.operands
[1].reg
= tmp
;
15912 NEON_ENCODE (INTEGER
, inst
);
15913 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15918 do_neon_rshl (void)
15920 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15921 struct neon_type_el et
= neon_check_type (3, rs
,
15922 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15925 tmp
= inst
.operands
[2].reg
;
15926 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15927 inst
.operands
[1].reg
= tmp
;
15928 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15932 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15934 /* Handle .I8 pseudo-instructions. */
15937 /* Unfortunately, this will make everything apart from zero out-of-range.
15938 FIXME is this the intended semantics? There doesn't seem much point in
15939 accepting .I8 if so. */
15940 immediate
|= immediate
<< 8;
15946 if (immediate
== (immediate
& 0x000000ff))
15948 *immbits
= immediate
;
15951 else if (immediate
== (immediate
& 0x0000ff00))
15953 *immbits
= immediate
>> 8;
15956 else if (immediate
== (immediate
& 0x00ff0000))
15958 *immbits
= immediate
>> 16;
15961 else if (immediate
== (immediate
& 0xff000000))
15963 *immbits
= immediate
>> 24;
15966 if ((immediate
& 0xffff) != (immediate
>> 16))
15967 goto bad_immediate
;
15968 immediate
&= 0xffff;
15971 if (immediate
== (immediate
& 0x000000ff))
15973 *immbits
= immediate
;
15976 else if (immediate
== (immediate
& 0x0000ff00))
15978 *immbits
= immediate
>> 8;
15983 first_error (_("immediate value out of range"));
15988 do_neon_logic (void)
15990 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
15992 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15993 neon_check_type (3, rs
, N_IGNORE_TYPE
);
15994 /* U bit and size field were set as part of the bitmask. */
15995 NEON_ENCODE (INTEGER
, inst
);
15996 neon_three_same (neon_quad (rs
), 0, -1);
16000 const int three_ops_form
= (inst
.operands
[2].present
16001 && !inst
.operands
[2].isreg
);
16002 const int immoperand
= (three_ops_form
? 2 : 1);
16003 enum neon_shape rs
= (three_ops_form
16004 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16005 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16006 struct neon_type_el et
= neon_check_type (2, rs
,
16007 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16008 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16012 if (et
.type
== NT_invtype
)
16015 if (three_ops_form
)
16016 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16017 _("first and second operands shall be the same register"));
16019 NEON_ENCODE (IMMED
, inst
);
16021 immbits
= inst
.operands
[immoperand
].imm
;
16024 /* .i64 is a pseudo-op, so the immediate must be a repeating
16026 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16027 inst
.operands
[immoperand
].reg
: 0))
16029 /* Set immbits to an invalid constant. */
16030 immbits
= 0xdeadbeef;
16037 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16041 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16045 /* Pseudo-instruction for VBIC. */
16046 neon_invert_size (&immbits
, 0, et
.size
);
16047 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16051 /* Pseudo-instruction for VORR. */
16052 neon_invert_size (&immbits
, 0, et
.size
);
16053 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16063 inst
.instruction
|= neon_quad (rs
) << 6;
16064 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16065 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16066 inst
.instruction
|= cmode
<< 8;
16067 neon_write_immbits (immbits
);
16069 neon_dp_fixup (&inst
);
16074 do_neon_bitfield (void)
16076 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16077 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16078 neon_three_same (neon_quad (rs
), 0, -1);
16082 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16085 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16086 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16088 if (et
.type
== NT_float
)
16090 NEON_ENCODE (FLOAT
, inst
);
16092 mve_encode_qqr (et
.size
, 1);
16094 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16098 NEON_ENCODE (INTEGER
, inst
);
16100 mve_encode_qqr (et
.size
, 0);
16102 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16108 do_neon_dyadic_if_su_d (void)
16110 /* This version only allow D registers, but that constraint is enforced during
16111 operand parsing so we don't need to do anything extra here. */
16112 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16116 do_neon_dyadic_if_i_d (void)
16118 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16119 affected if we specify unsigned args. */
16120 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16123 enum vfp_or_neon_is_neon_bits
16126 NEON_CHECK_ARCH
= 2,
16127 NEON_CHECK_ARCH8
= 4
16130 /* Call this function if an instruction which may have belonged to the VFP or
16131 Neon instruction sets, but turned out to be a Neon instruction (due to the
16132 operand types involved, etc.). We have to check and/or fix-up a couple of
16135 - Make sure the user hasn't attempted to make a Neon instruction
16137 - Alter the value in the condition code field if necessary.
16138 - Make sure that the arch supports Neon instructions.
16140 Which of these operations take place depends on bits from enum
16141 vfp_or_neon_is_neon_bits.
16143 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16144 current instruction's condition is COND_ALWAYS, the condition field is
16145 changed to inst.uncond_value. This is necessary because instructions shared
16146 between VFP and Neon may be conditional for the VFP variants only, and the
16147 unconditional Neon version must have, e.g., 0xF in the condition field. */
16150 vfp_or_neon_is_neon (unsigned check
)
16152 /* Conditions are always legal in Thumb mode (IT blocks). */
16153 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16155 if (inst
.cond
!= COND_ALWAYS
)
16157 first_error (_(BAD_COND
));
16160 if (inst
.uncond_value
!= -1)
16161 inst
.instruction
|= inst
.uncond_value
<< 28;
16165 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16166 || ((check
& NEON_CHECK_ARCH8
)
16167 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16169 first_error (_(BAD_FPU
));
16177 check_simd_pred_availability (int fp
, unsigned check
)
16179 if (inst
.cond
> COND_ALWAYS
)
16181 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16183 inst
.error
= BAD_FPU
;
16186 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16188 else if (inst
.cond
< COND_ALWAYS
)
16190 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16191 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16192 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16197 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16198 && vfp_or_neon_is_neon (check
) == FAIL
)
16201 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16202 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16208 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16210 constraint (size
< 32, BAD_ADDR_MODE
);
16211 constraint (size
!= elsize
, BAD_EL_TYPE
);
16212 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16213 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16214 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16215 _("destination register and offset register may not be the"
16218 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16225 constraint ((imm
% (size
/ 8) != 0)
16226 || imm
> (0x7f << neon_logbits (size
)),
16227 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16228 " range of +/-[0,508]")
16229 : _("immediate must be a multiple of 8 in the"
16230 " range of +/-[0,1016]"));
16231 inst
.instruction
|= 0x11 << 24;
16232 inst
.instruction
|= add
<< 23;
16233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16234 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16236 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16237 inst
.instruction
|= 1 << 12;
16238 inst
.instruction
|= (size
== 64) << 8;
16239 inst
.instruction
&= 0xffffff00;
16240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16241 inst
.instruction
|= imm
>> neon_logbits (size
);
16245 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16247 unsigned os
= inst
.operands
[1].imm
>> 5;
16248 constraint (os
!= 0 && size
== 8,
16249 _("can not shift offsets when accessing less than half-word"));
16250 constraint (os
&& os
!= neon_logbits (size
),
16251 _("shift immediate must be 1, 2 or 3 for half-word, word"
16252 " or double-word accesses respectively"));
16253 if (inst
.operands
[1].reg
== REG_PC
)
16254 as_tsktsk (MVE_BAD_PC
);
16259 constraint (elsize
>= 64, BAD_EL_TYPE
);
16262 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16266 constraint (elsize
!= size
, BAD_EL_TYPE
);
16271 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16275 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16276 _("destination register and offset register may not be"
16278 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16280 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16281 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16282 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16286 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16289 inst
.instruction
|= 1 << 23;
16290 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16292 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16293 inst
.instruction
|= neon_logbits (elsize
) << 7;
16294 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16295 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16296 inst
.instruction
|= !!os
;
16300 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16302 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16304 constraint (size
>= 64, BAD_ADDR_MODE
);
16308 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16311 constraint (elsize
!= size
, BAD_EL_TYPE
);
16318 constraint (elsize
!= size
&& type
!= NT_unsigned
16319 && type
!= NT_signed
, BAD_EL_TYPE
);
16323 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16326 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16334 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16339 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16342 constraint (1, _("immediate must be a multiple of 2 in the"
16343 " range of +/-[0,254]"));
16346 constraint (1, _("immediate must be a multiple of 4 in the"
16347 " range of +/-[0,508]"));
16352 if (size
!= elsize
)
16354 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16355 constraint (inst
.operands
[0].reg
> 14,
16356 _("MVE vector register in the range [Q0..Q7] expected"));
16357 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16358 inst
.instruction
|= (size
== 16) << 19;
16359 inst
.instruction
|= neon_logbits (elsize
) << 7;
16363 if (inst
.operands
[1].reg
== REG_PC
)
16364 as_tsktsk (MVE_BAD_PC
);
16365 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16366 as_tsktsk (MVE_BAD_SP
);
16367 inst
.instruction
|= 1 << 12;
16368 inst
.instruction
|= neon_logbits (size
) << 7;
16370 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16371 inst
.instruction
|= add
<< 23;
16372 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16373 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16374 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16375 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16376 inst
.instruction
&= 0xffffff80;
16377 inst
.instruction
|= imm
>> neon_logbits (size
);
16382 do_mve_vstr_vldr (void)
16387 if (inst
.cond
> COND_ALWAYS
)
16388 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16390 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16392 switch (inst
.instruction
)
16399 /* fall through. */
16405 /* fall through. */
16411 /* fall through. */
16417 /* fall through. */
16422 unsigned elsize
= inst
.vectype
.el
[0].size
;
16424 if (inst
.operands
[1].isquad
)
16426 /* We are dealing with [Q, imm]{!} cases. */
16427 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16431 if (inst
.operands
[1].immisreg
== 2)
16433 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16434 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16436 else if (!inst
.operands
[1].immisreg
)
16438 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16439 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16442 constraint (1, BAD_ADDR_MODE
);
16449 do_mve_vst_vld (void)
16451 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16454 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16455 || inst
.relocs
[0].exp
.X_add_number
!= 0
16456 || inst
.operands
[1].immisreg
!= 0,
16458 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16459 if (inst
.operands
[1].reg
== REG_PC
)
16460 as_tsktsk (MVE_BAD_PC
);
16461 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16462 as_tsktsk (MVE_BAD_SP
);
16465 /* These instructions are one of the "exceptions" mentioned in
16466 handle_pred_state. They are MVE instructions that are not VPT compatible
16467 and do not accept a VPT code, thus appending such a code is a syntax
16469 if (inst
.cond
> COND_ALWAYS
)
16470 first_error (BAD_SYNTAX
);
16471 /* If we append a scalar condition code we can set this to
16472 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16473 else if (inst
.cond
< COND_ALWAYS
)
16474 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16476 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16478 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16479 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16480 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16482 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16487 do_neon_dyadic_if_su (void)
16489 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16490 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16493 if (check_simd_pred_availability (et
.type
== NT_float
,
16494 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16497 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16501 do_neon_addsub_if_i (void)
16503 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16504 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16507 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16508 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16509 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16511 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16512 /* If we are parsing Q registers and the element types match MVE, which NEON
16513 also supports, then we must check whether this is an instruction that can
16514 be used by both MVE/NEON. This distinction can be made based on whether
16515 they are predicated or not. */
16516 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16518 if (check_simd_pred_availability (et
.type
== NT_float
,
16519 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16524 /* If they are either in a D register or are using an unsupported. */
16526 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16530 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16531 affected if we specify unsigned args. */
16532 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16535 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16537 V<op> A,B (A is operand 0, B is operand 2)
16542 so handle that case specially. */
16545 neon_exchange_operands (void)
16547 if (inst
.operands
[1].present
)
16549 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16551 /* Swap operands[1] and operands[2]. */
16552 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16553 inst
.operands
[1] = inst
.operands
[2];
16554 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16559 inst
.operands
[1] = inst
.operands
[2];
16560 inst
.operands
[2] = inst
.operands
[0];
16565 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16567 if (inst
.operands
[2].isreg
)
16570 neon_exchange_operands ();
16571 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16575 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16576 struct neon_type_el et
= neon_check_type (2, rs
,
16577 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16579 NEON_ENCODE (IMMED
, inst
);
16580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16584 inst
.instruction
|= neon_quad (rs
) << 6;
16585 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16586 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16588 neon_dp_fixup (&inst
);
16595 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16599 do_neon_cmp_inv (void)
16601 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16607 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16610 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16611 scalars, which are encoded in 5 bits, M : Rm.
16612 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16613 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16616 Dot Product instructions are similar to multiply instructions except elsize
16617 should always be 32.
16619 This function translates SCALAR, which is GAS's internal encoding of indexed
16620 scalar register, to raw encoding. There is also register and index range
16621 check based on ELSIZE. */
16624 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16626 unsigned regno
= NEON_SCALAR_REG (scalar
);
16627 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16632 if (regno
> 7 || elno
> 3)
16634 return regno
| (elno
<< 3);
16637 if (regno
> 15 || elno
> 1)
16639 return regno
| (elno
<< 4);
16643 first_error (_("scalar out of range for multiply instruction"));
16649 /* Encode multiply / multiply-accumulate scalar instructions. */
16652 neon_mul_mac (struct neon_type_el et
, int ubit
)
16656 /* Give a more helpful error message if we have an invalid type. */
16657 if (et
.type
== NT_invtype
)
16660 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
16661 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16662 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16663 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16664 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16665 inst
.instruction
|= LOW4 (scalar
);
16666 inst
.instruction
|= HI1 (scalar
) << 5;
16667 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16668 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16669 inst
.instruction
|= (ubit
!= 0) << 24;
16671 neon_dp_fixup (&inst
);
16675 do_neon_mac_maybe_scalar (void)
16677 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
16680 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16683 if (inst
.operands
[2].isscalar
)
16685 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16686 struct neon_type_el et
= neon_check_type (3, rs
,
16687 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
16688 NEON_ENCODE (SCALAR
, inst
);
16689 neon_mul_mac (et
, neon_quad (rs
));
16693 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16694 affected if we specify unsigned args. */
16695 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16700 do_neon_fmac (void)
16702 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
16705 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16708 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16714 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16715 struct neon_type_el et
= neon_check_type (3, rs
,
16716 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16717 neon_three_same (neon_quad (rs
), 0, et
.size
);
16720 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
16721 same types as the MAC equivalents. The polynomial type for this instruction
16722 is encoded the same as the integer type. */
16727 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
16730 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16733 if (inst
.operands
[2].isscalar
)
16734 do_neon_mac_maybe_scalar ();
16736 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
16740 do_neon_qdmulh (void)
16742 if (inst
.operands
[2].isscalar
)
16744 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16745 struct neon_type_el et
= neon_check_type (3, rs
,
16746 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16747 NEON_ENCODE (SCALAR
, inst
);
16748 neon_mul_mac (et
, neon_quad (rs
));
16752 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16753 struct neon_type_el et
= neon_check_type (3, rs
,
16754 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16755 NEON_ENCODE (INTEGER
, inst
);
16756 /* The U bit (rounding) comes from bit mask. */
16757 neon_three_same (neon_quad (rs
), 0, et
.size
);
16762 do_mve_vmull (void)
16765 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
16766 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
16767 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
16768 && inst
.cond
== COND_ALWAYS
16769 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
16774 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16775 N_SUF_32
| N_F64
| N_P8
16776 | N_P16
| N_I_MVE
| N_KEY
);
16777 if (((et
.type
== NT_poly
) && et
.size
== 8
16778 && ARM_CPU_IS_ANY (cpu_variant
))
16779 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
16786 constraint (rs
!= NS_QQQ
, BAD_FPU
);
16787 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16788 N_SU_32
| N_P8
| N_P16
| N_KEY
);
16790 /* We are dealing with MVE's vmullt. */
16792 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16793 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16794 as_tsktsk (BAD_MVE_SRCDEST
);
16796 if (inst
.cond
> COND_ALWAYS
)
16797 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16799 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16801 if (et
.type
== NT_poly
)
16802 mve_encode_qqq (neon_logbits (et
.size
), 64);
16804 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
16809 inst
.instruction
= N_MNEM_vmul
;
16812 inst
.pred_insn_type
= INSIDE_IT_INSN
;
16817 do_mve_vabav (void)
16819 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16824 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16827 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
16828 | N_S16
| N_S32
| N_U8
| N_U16
16831 if (inst
.cond
> COND_ALWAYS
)
16832 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16834 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16836 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
16840 do_mve_vmladav (void)
16842 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16843 struct neon_type_el et
= neon_check_type (3, rs
,
16844 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16846 if (et
.type
== NT_unsigned
16847 && (inst
.instruction
== M_MNEM_vmladavx
16848 || inst
.instruction
== M_MNEM_vmladavax
16849 || inst
.instruction
== M_MNEM_vmlsdav
16850 || inst
.instruction
== M_MNEM_vmlsdava
16851 || inst
.instruction
== M_MNEM_vmlsdavx
16852 || inst
.instruction
== M_MNEM_vmlsdavax
))
16853 first_error (BAD_SIMD_TYPE
);
16855 constraint (inst
.operands
[2].reg
> 14,
16856 _("MVE vector register in the range [Q0..Q7] expected"));
16858 if (inst
.cond
> COND_ALWAYS
)
16859 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16861 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16863 if (inst
.instruction
== M_MNEM_vmlsdav
16864 || inst
.instruction
== M_MNEM_vmlsdava
16865 || inst
.instruction
== M_MNEM_vmlsdavx
16866 || inst
.instruction
== M_MNEM_vmlsdavax
)
16867 inst
.instruction
|= (et
.size
== 8) << 28;
16869 inst
.instruction
|= (et
.size
== 8) << 8;
16871 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
16872 inst
.instruction
|= (et
.size
== 32) << 16;
16876 do_neon_qrdmlah (void)
16878 /* Check we're on the correct architecture. */
16879 if (!mark_feature_used (&fpu_neon_ext_armv8
))
16881 _("instruction form not available on this architecture.");
16882 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
16884 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
16885 record_feature_use (&fpu_neon_ext_v8_1
);
16888 if (inst
.operands
[2].isscalar
)
16890 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16891 struct neon_type_el et
= neon_check_type (3, rs
,
16892 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16893 NEON_ENCODE (SCALAR
, inst
);
16894 neon_mul_mac (et
, neon_quad (rs
));
16898 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16899 struct neon_type_el et
= neon_check_type (3, rs
,
16900 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16901 NEON_ENCODE (INTEGER
, inst
);
16902 /* The U bit (rounding) comes from bit mask. */
16903 neon_three_same (neon_quad (rs
), 0, et
.size
);
16908 do_neon_fcmp_absolute (void)
16910 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16911 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16912 N_F_16_32
| N_KEY
);
16913 /* Size field comes from bit mask. */
16914 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
16918 do_neon_fcmp_absolute_inv (void)
16920 neon_exchange_operands ();
16921 do_neon_fcmp_absolute ();
16925 do_neon_step (void)
16927 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16928 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16929 N_F_16_32
| N_KEY
);
16930 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16934 do_neon_abs_neg (void)
16936 enum neon_shape rs
;
16937 struct neon_type_el et
;
16939 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
16942 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16943 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
16945 if (check_simd_pred_availability (et
.type
== NT_float
,
16946 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16951 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16952 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16953 inst
.instruction
|= neon_quad (rs
) << 6;
16954 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16955 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16957 neon_dp_fixup (&inst
);
16963 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16964 struct neon_type_el et
= neon_check_type (2, rs
,
16965 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16966 int imm
= inst
.operands
[2].imm
;
16967 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16968 _("immediate out of range for insert"));
16969 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16975 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16976 struct neon_type_el et
= neon_check_type (2, rs
,
16977 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16978 int imm
= inst
.operands
[2].imm
;
16979 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16980 _("immediate out of range for insert"));
16981 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
16985 do_neon_qshlu_imm (void)
16987 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16988 struct neon_type_el et
= neon_check_type (2, rs
,
16989 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
16990 int imm
= inst
.operands
[2].imm
;
16991 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16992 _("immediate out of range for shift"));
16993 /* Only encodes the 'U present' variant of the instruction.
16994 In this case, signed types have OP (bit 8) set to 0.
16995 Unsigned types have OP set to 1. */
16996 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
16997 /* The rest of the bits are the same as other immediate shifts. */
16998 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17002 do_neon_qmovn (void)
17004 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17005 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17006 /* Saturating move where operands can be signed or unsigned, and the
17007 destination has the same signedness. */
17008 NEON_ENCODE (INTEGER
, inst
);
17009 if (et
.type
== NT_unsigned
)
17010 inst
.instruction
|= 0xc0;
17012 inst
.instruction
|= 0x80;
17013 neon_two_same (0, 1, et
.size
/ 2);
17017 do_neon_qmovun (void)
17019 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17020 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17021 /* Saturating move with unsigned results. Operands must be signed. */
17022 NEON_ENCODE (INTEGER
, inst
);
17023 neon_two_same (0, 1, et
.size
/ 2);
17027 do_neon_rshift_sat_narrow (void)
17029 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17030 or unsigned. If operands are unsigned, results must also be unsigned. */
17031 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17032 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17033 int imm
= inst
.operands
[2].imm
;
17034 /* This gets the bounds check, size encoding and immediate bits calculation
17038 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17039 VQMOVN.I<size> <Dd>, <Qm>. */
17042 inst
.operands
[2].present
= 0;
17043 inst
.instruction
= N_MNEM_vqmovn
;
17048 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17049 _("immediate out of range"));
17050 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17054 do_neon_rshift_sat_narrow_u (void)
17056 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17057 or unsigned. If operands are unsigned, results must also be unsigned. */
17058 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17059 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17060 int imm
= inst
.operands
[2].imm
;
17061 /* This gets the bounds check, size encoding and immediate bits calculation
17065 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17066 VQMOVUN.I<size> <Dd>, <Qm>. */
17069 inst
.operands
[2].present
= 0;
17070 inst
.instruction
= N_MNEM_vqmovun
;
17075 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17076 _("immediate out of range"));
17077 /* FIXME: The manual is kind of unclear about what value U should have in
17078 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17080 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
17084 do_neon_movn (void)
17086 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17087 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17088 NEON_ENCODE (INTEGER
, inst
);
17089 neon_two_same (0, 1, et
.size
/ 2);
17093 do_neon_rshift_narrow (void)
17095 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17096 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17097 int imm
= inst
.operands
[2].imm
;
17098 /* This gets the bounds check, size encoding and immediate bits calculation
17102 /* If immediate is zero then we are a pseudo-instruction for
17103 VMOVN.I<size> <Dd>, <Qm> */
17106 inst
.operands
[2].present
= 0;
17107 inst
.instruction
= N_MNEM_vmovn
;
17112 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17113 _("immediate out of range for narrowing operation"));
17114 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
17118 do_neon_shll (void)
17120 /* FIXME: Type checking when lengthening. */
17121 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
17122 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
17123 unsigned imm
= inst
.operands
[2].imm
;
17125 if (imm
== et
.size
)
17127 /* Maximum shift variant. */
17128 NEON_ENCODE (INTEGER
, inst
);
17129 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17130 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17131 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17132 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17133 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17135 neon_dp_fixup (&inst
);
17139 /* A more-specific type check for non-max versions. */
17140 et
= neon_check_type (2, NS_QDI
,
17141 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17142 NEON_ENCODE (IMMED
, inst
);
17143 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
17147 /* Check the various types for the VCVT instruction, and return which version
17148 the current instruction is. */
17150 #define CVT_FLAVOUR_VAR \
17151 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17152 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17153 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17154 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17155 /* Half-precision conversions. */ \
17156 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17157 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17158 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17159 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17160 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17161 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17162 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17163 Compared with single/double precision variants, only the co-processor \
17164 field is different, so the encoding flow is reused here. */ \
17165 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17166 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17167 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17168 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17169 /* VFP instructions. */ \
17170 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17171 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17172 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17173 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17174 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17175 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17176 /* VFP instructions with bitshift. */ \
17177 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17178 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17179 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17180 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17181 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17182 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17183 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17184 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17186 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17187 neon_cvt_flavour_##C,
17189 /* The different types of conversions we can do. */
17190 enum neon_cvt_flavour
17193 neon_cvt_flavour_invalid
,
17194 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
17199 static enum neon_cvt_flavour
17200 get_neon_cvt_flavour (enum neon_shape rs
)
17202 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17203 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17204 if (et.type != NT_invtype) \
17206 inst.error = NULL; \
17207 return (neon_cvt_flavour_##C); \
17210 struct neon_type_el et
;
17211 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
17212 || rs
== NS_FF
) ? N_VFP
: 0;
17213 /* The instruction versions which take an immediate take one register
17214 argument, which is extended to the width of the full register. Thus the
17215 "source" and "destination" registers must have the same width. Hack that
17216 here by making the size equal to the key (wider, in this case) operand. */
17217 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
17221 return neon_cvt_flavour_invalid
;
17236 /* Neon-syntax VFP conversions. */
17239 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
17241 const char *opname
= 0;
17243 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
17244 || rs
== NS_FHI
|| rs
== NS_HFI
)
17246 /* Conversions with immediate bitshift. */
17247 const char *enc
[] =
17249 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17255 if (flavour
< (int) ARRAY_SIZE (enc
))
17257 opname
= enc
[flavour
];
17258 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17259 _("operands 0 and 1 must be the same register"));
17260 inst
.operands
[1] = inst
.operands
[2];
17261 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17266 /* Conversions without bitshift. */
17267 const char *enc
[] =
17269 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17275 if (flavour
< (int) ARRAY_SIZE (enc
))
17276 opname
= enc
[flavour
];
17280 do_vfp_nsyn_opcode (opname
);
17282 /* ARMv8.2 fp16 VCVT instruction. */
17283 if (flavour
== neon_cvt_flavour_s32_f16
17284 || flavour
== neon_cvt_flavour_u32_f16
17285 || flavour
== neon_cvt_flavour_f16_u32
17286 || flavour
== neon_cvt_flavour_f16_s32
)
17287 do_scalar_fp16_v82_encode ();
17291 do_vfp_nsyn_cvtz (void)
17293 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17294 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17295 const char *enc
[] =
17297 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17303 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17304 do_vfp_nsyn_opcode (enc
[flavour
]);
17308 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17309 enum neon_cvt_mode mode
)
17314 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17315 D register operands. */
17316 if (flavour
== neon_cvt_flavour_s32_f64
17317 || flavour
== neon_cvt_flavour_u32_f64
)
17318 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17321 if (flavour
== neon_cvt_flavour_s32_f16
17322 || flavour
== neon_cvt_flavour_u32_f16
)
17323 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17326 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17330 case neon_cvt_flavour_s32_f64
:
17334 case neon_cvt_flavour_s32_f32
:
17338 case neon_cvt_flavour_s32_f16
:
17342 case neon_cvt_flavour_u32_f64
:
17346 case neon_cvt_flavour_u32_f32
:
17350 case neon_cvt_flavour_u32_f16
:
17355 first_error (_("invalid instruction shape"));
17361 case neon_cvt_mode_a
: rm
= 0; break;
17362 case neon_cvt_mode_n
: rm
= 1; break;
17363 case neon_cvt_mode_p
: rm
= 2; break;
17364 case neon_cvt_mode_m
: rm
= 3; break;
17365 default: first_error (_("invalid rounding mode")); return;
17368 NEON_ENCODE (FPV8
, inst
);
17369 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
17370 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
17371 inst
.instruction
|= sz
<< 8;
17373 /* ARMv8.2 fp16 VCVT instruction. */
17374 if (flavour
== neon_cvt_flavour_s32_f16
17375 ||flavour
== neon_cvt_flavour_u32_f16
)
17376 do_scalar_fp16_v82_encode ();
17377 inst
.instruction
|= op
<< 7;
17378 inst
.instruction
|= rm
<< 16;
17379 inst
.instruction
|= 0xf0000000;
17380 inst
.is_neon
= TRUE
;
17384 do_neon_cvt_1 (enum neon_cvt_mode mode
)
17386 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
17387 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
17388 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
17390 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17392 if (flavour
== neon_cvt_flavour_invalid
)
17395 /* PR11109: Handle round-to-zero for VCVT conversions. */
17396 if (mode
== neon_cvt_mode_z
17397 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
17398 && (flavour
== neon_cvt_flavour_s16_f16
17399 || flavour
== neon_cvt_flavour_u16_f16
17400 || flavour
== neon_cvt_flavour_s32_f32
17401 || flavour
== neon_cvt_flavour_u32_f32
17402 || flavour
== neon_cvt_flavour_s32_f64
17403 || flavour
== neon_cvt_flavour_u32_f64
)
17404 && (rs
== NS_FD
|| rs
== NS_FF
))
17406 do_vfp_nsyn_cvtz ();
17410 /* ARMv8.2 fp16 VCVT conversions. */
17411 if (mode
== neon_cvt_mode_z
17412 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
17413 && (flavour
== neon_cvt_flavour_s32_f16
17414 || flavour
== neon_cvt_flavour_u32_f16
)
17417 do_vfp_nsyn_cvtz ();
17418 do_scalar_fp16_v82_encode ();
17422 /* VFP rather than Neon conversions. */
17423 if (flavour
>= neon_cvt_flavour_first_fp
)
17425 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17426 do_vfp_nsyn_cvt (rs
, flavour
);
17428 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17436 if (mode
== neon_cvt_mode_z
17437 && (flavour
== neon_cvt_flavour_f16_s16
17438 || flavour
== neon_cvt_flavour_f16_u16
17439 || flavour
== neon_cvt_flavour_s16_f16
17440 || flavour
== neon_cvt_flavour_u16_f16
17441 || flavour
== neon_cvt_flavour_f32_u32
17442 || flavour
== neon_cvt_flavour_f32_s32
17443 || flavour
== neon_cvt_flavour_s32_f32
17444 || flavour
== neon_cvt_flavour_u32_f32
))
17446 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17449 else if (mode
== neon_cvt_mode_n
)
17451 /* We are dealing with vcvt with the 'ne' condition. */
17453 inst
.instruction
= N_MNEM_vcvt
;
17454 do_neon_cvt_1 (neon_cvt_mode_z
);
17457 /* fall through. */
17461 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17462 0x0000100, 0x1000100, 0x0, 0x1000000};
17464 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17465 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17468 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17470 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
17471 _("immediate value out of range"));
17474 case neon_cvt_flavour_f16_s16
:
17475 case neon_cvt_flavour_f16_u16
:
17476 case neon_cvt_flavour_s16_f16
:
17477 case neon_cvt_flavour_u16_f16
:
17478 constraint (inst
.operands
[2].imm
> 16,
17479 _("immediate value out of range"));
17481 case neon_cvt_flavour_f32_u32
:
17482 case neon_cvt_flavour_f32_s32
:
17483 case neon_cvt_flavour_s32_f32
:
17484 case neon_cvt_flavour_u32_f32
:
17485 constraint (inst
.operands
[2].imm
> 32,
17486 _("immediate value out of range"));
17489 inst
.error
= BAD_FPU
;
17494 /* Fixed-point conversion with #0 immediate is encoded as an
17495 integer conversion. */
17496 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
17498 NEON_ENCODE (IMMED
, inst
);
17499 if (flavour
!= neon_cvt_flavour_invalid
)
17500 inst
.instruction
|= enctab
[flavour
];
17501 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17502 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17503 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17504 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17505 inst
.instruction
|= neon_quad (rs
) << 6;
17506 inst
.instruction
|= 1 << 21;
17507 if (flavour
< neon_cvt_flavour_s16_f16
)
17509 inst
.instruction
|= 1 << 21;
17510 immbits
= 32 - inst
.operands
[2].imm
;
17511 inst
.instruction
|= immbits
<< 16;
17515 inst
.instruction
|= 3 << 20;
17516 immbits
= 16 - inst
.operands
[2].imm
;
17517 inst
.instruction
|= immbits
<< 16;
17518 inst
.instruction
&= ~(1 << 9);
17521 neon_dp_fixup (&inst
);
17526 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17527 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
17528 && (flavour
== neon_cvt_flavour_s16_f16
17529 || flavour
== neon_cvt_flavour_u16_f16
17530 || flavour
== neon_cvt_flavour_s32_f32
17531 || flavour
== neon_cvt_flavour_u32_f32
))
17533 if (check_simd_pred_availability (1,
17534 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17537 else if (mode
== neon_cvt_mode_z
17538 && (flavour
== neon_cvt_flavour_f16_s16
17539 || flavour
== neon_cvt_flavour_f16_u16
17540 || flavour
== neon_cvt_flavour_s16_f16
17541 || flavour
== neon_cvt_flavour_u16_f16
17542 || flavour
== neon_cvt_flavour_f32_u32
17543 || flavour
== neon_cvt_flavour_f32_s32
17544 || flavour
== neon_cvt_flavour_s32_f32
17545 || flavour
== neon_cvt_flavour_u32_f32
))
17547 if (check_simd_pred_availability (1,
17548 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17551 /* fall through. */
17553 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
17556 NEON_ENCODE (FLOAT
, inst
);
17557 if (check_simd_pred_availability (1,
17558 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17564 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17565 inst
.instruction
|= neon_quad (rs
) << 6;
17566 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
17567 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
17568 inst
.instruction
|= mode
<< 8;
17569 if (flavour
== neon_cvt_flavour_u16_f16
17570 || flavour
== neon_cvt_flavour_s16_f16
)
17571 /* Mask off the original size bits and reencode them. */
17572 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
17575 inst
.instruction
|= 0xfc000000;
17577 inst
.instruction
|= 0xf0000000;
17583 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
17584 0x100, 0x180, 0x0, 0x080};
17586 NEON_ENCODE (INTEGER
, inst
);
17588 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17590 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17594 if (flavour
!= neon_cvt_flavour_invalid
)
17595 inst
.instruction
|= enctab
[flavour
];
17597 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17598 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17599 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17600 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17601 inst
.instruction
|= neon_quad (rs
) << 6;
17602 if (flavour
>= neon_cvt_flavour_s16_f16
17603 && flavour
<= neon_cvt_flavour_f16_u16
)
17604 /* Half precision. */
17605 inst
.instruction
|= 1 << 18;
17607 inst
.instruction
|= 2 << 18;
17609 neon_dp_fixup (&inst
);
17614 /* Half-precision conversions for Advanced SIMD -- neon. */
17617 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17621 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
17623 as_bad (_("operand size must match register width"));
17628 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
17630 as_bad (_("operand size must match register width"));
17635 inst
.instruction
= 0x3b60600;
17637 inst
.instruction
= 0x3b60700;
17639 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17640 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17641 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17642 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17643 neon_dp_fixup (&inst
);
17647 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
17648 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17649 do_vfp_nsyn_cvt (rs
, flavour
);
17651 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17656 do_neon_cvtr (void)
17658 do_neon_cvt_1 (neon_cvt_mode_x
);
17664 do_neon_cvt_1 (neon_cvt_mode_z
);
17668 do_neon_cvta (void)
17670 do_neon_cvt_1 (neon_cvt_mode_a
);
17674 do_neon_cvtn (void)
17676 do_neon_cvt_1 (neon_cvt_mode_n
);
17680 do_neon_cvtp (void)
17682 do_neon_cvt_1 (neon_cvt_mode_p
);
17686 do_neon_cvtm (void)
17688 do_neon_cvt_1 (neon_cvt_mode_m
);
17692 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
17695 mark_feature_used (&fpu_vfp_ext_armv8
);
17697 encode_arm_vfp_reg (inst
.operands
[0].reg
,
17698 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
17699 encode_arm_vfp_reg (inst
.operands
[1].reg
,
17700 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
17701 inst
.instruction
|= to
? 0x10000 : 0;
17702 inst
.instruction
|= t
? 0x80 : 0;
17703 inst
.instruction
|= is_double
? 0x100 : 0;
17704 do_vfp_cond_or_thumb ();
17708 do_neon_cvttb_1 (bfd_boolean t
)
17710 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
17711 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
17715 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
17717 int single_to_half
= 0;
17718 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
17721 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17723 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17724 && (flavour
== neon_cvt_flavour_u16_f16
17725 || flavour
== neon_cvt_flavour_s16_f16
17726 || flavour
== neon_cvt_flavour_f16_s16
17727 || flavour
== neon_cvt_flavour_f16_u16
17728 || flavour
== neon_cvt_flavour_u32_f32
17729 || flavour
== neon_cvt_flavour_s32_f32
17730 || flavour
== neon_cvt_flavour_f32_s32
17731 || flavour
== neon_cvt_flavour_f32_u32
))
17734 inst
.instruction
= N_MNEM_vcvt
;
17735 set_pred_insn_type (INSIDE_VPT_INSN
);
17736 do_neon_cvt_1 (neon_cvt_mode_z
);
17739 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
17740 single_to_half
= 1;
17741 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
17743 first_error (BAD_FPU
);
17747 inst
.instruction
= 0xee3f0e01;
17748 inst
.instruction
|= single_to_half
<< 28;
17749 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17750 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
17751 inst
.instruction
|= t
<< 12;
17752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
17756 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
17759 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
17761 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
17764 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
17766 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
17768 /* The VCVTB and VCVTT instructions with D-register operands
17769 don't work for SP only targets. */
17770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17774 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
17776 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
17778 /* The VCVTB and VCVTT instructions with D-register operands
17779 don't work for SP only targets. */
17780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17784 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
17791 do_neon_cvtb (void)
17793 do_neon_cvttb_1 (FALSE
);
17798 do_neon_cvtt (void)
17800 do_neon_cvttb_1 (TRUE
);
17804 neon_move_immediate (void)
17806 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
17807 struct neon_type_el et
= neon_check_type (2, rs
,
17808 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
17809 unsigned immlo
, immhi
= 0, immbits
;
17810 int op
, cmode
, float_p
;
17812 constraint (et
.type
== NT_invtype
,
17813 _("operand size must be specified for immediate VMOV"));
17815 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
17816 op
= (inst
.instruction
& (1 << 5)) != 0;
17818 immlo
= inst
.operands
[1].imm
;
17819 if (inst
.operands
[1].regisimm
)
17820 immhi
= inst
.operands
[1].reg
;
17822 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
17823 _("immediate has bits set outside the operand size"));
17825 float_p
= inst
.operands
[1].immisfloat
;
17827 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
17828 et
.size
, et
.type
)) == FAIL
)
17830 /* Invert relevant bits only. */
17831 neon_invert_size (&immlo
, &immhi
, et
.size
);
17832 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
17833 with one or the other; those cases are caught by
17834 neon_cmode_for_move_imm. */
17836 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
17837 &op
, et
.size
, et
.type
)) == FAIL
)
17839 first_error (_("immediate out of range"));
17844 inst
.instruction
&= ~(1 << 5);
17845 inst
.instruction
|= op
<< 5;
17847 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17848 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17849 inst
.instruction
|= neon_quad (rs
) << 6;
17850 inst
.instruction
|= cmode
<< 8;
17852 neon_write_immbits (immbits
);
17858 if (inst
.operands
[1].isreg
)
17860 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17862 NEON_ENCODE (INTEGER
, inst
);
17863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17865 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17866 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17867 inst
.instruction
|= neon_quad (rs
) << 6;
17871 NEON_ENCODE (IMMED
, inst
);
17872 neon_move_immediate ();
17875 neon_dp_fixup (&inst
);
17878 /* Encode instructions of form:
17880 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
17881 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
17884 neon_mixed_length (struct neon_type_el et
, unsigned size
)
17886 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17887 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17888 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17889 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17890 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
17891 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
17892 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
17893 inst
.instruction
|= neon_logbits (size
) << 20;
17895 neon_dp_fixup (&inst
);
17899 do_neon_dyadic_long (void)
17901 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17904 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
17907 NEON_ENCODE (INTEGER
, inst
);
17908 /* FIXME: Type checking for lengthening op. */
17909 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17910 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
17911 neon_mixed_length (et
, et
.size
);
17913 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17914 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
17916 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
17917 in an IT block with le/lt conditions. */
17919 if (inst
.cond
== 0xf)
17921 else if (inst
.cond
== 0x10)
17924 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17926 if (inst
.instruction
== N_MNEM_vaddl
)
17928 inst
.instruction
= N_MNEM_vadd
;
17929 do_neon_addsub_if_i ();
17931 else if (inst
.instruction
== N_MNEM_vsubl
)
17933 inst
.instruction
= N_MNEM_vsub
;
17934 do_neon_addsub_if_i ();
17936 else if (inst
.instruction
== N_MNEM_vabdl
)
17938 inst
.instruction
= N_MNEM_vabd
;
17939 do_neon_dyadic_if_su ();
17943 first_error (BAD_FPU
);
17947 do_neon_abal (void)
17949 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17950 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
17951 neon_mixed_length (et
, et
.size
);
17955 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
17957 if (inst
.operands
[2].isscalar
)
17959 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
17960 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
17961 NEON_ENCODE (SCALAR
, inst
);
17962 neon_mul_mac (et
, et
.type
== NT_unsigned
);
17966 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
17967 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
17968 NEON_ENCODE (INTEGER
, inst
);
17969 neon_mixed_length (et
, et
.size
);
17974 do_neon_mac_maybe_scalar_long (void)
17976 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
17979 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
17980 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
17983 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
17985 unsigned regno
= NEON_SCALAR_REG (scalar
);
17986 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17990 if (regno
> 7 || elno
> 3)
17993 return ((regno
& 0x7)
17994 | ((elno
& 0x1) << 3)
17995 | (((elno
>> 1) & 0x1) << 5));
17999 if (regno
> 15 || elno
> 1)
18002 return (((regno
& 0x1) << 5)
18003 | ((regno
>> 1) & 0x7)
18004 | ((elno
& 0x1) << 3));
18008 first_error (_("scalar out of range for multiply instruction"));
18013 do_neon_fmac_maybe_scalar_long (int subtype
)
18015 enum neon_shape rs
;
18017 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18018 field (bits[21:20]) has different meaning. For scalar index variant, it's
18019 used to differentiate add and subtract, otherwise it's with fixed value
18023 if (inst
.cond
!= COND_ALWAYS
)
18024 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18025 "behaviour is UNPREDICTABLE"));
18027 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18030 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18033 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18034 be a scalar index register. */
18035 if (inst
.operands
[2].isscalar
)
18037 high8
= 0xfe000000;
18040 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18044 high8
= 0xfc000000;
18047 inst
.instruction
|= (0x1 << 23);
18048 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
18051 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
18053 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18054 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18055 so we simply pass -1 as size. */
18056 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
18057 neon_three_same (quad_p
, 0, size
);
18059 /* Undo neon_dp_fixup. Redo the high eight bits. */
18060 inst
.instruction
&= 0x00ffffff;
18061 inst
.instruction
|= high8
;
18063 #define LOW1(R) ((R) & 0x1)
18064 #define HI4(R) (((R) >> 1) & 0xf)
18065 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18066 whether the instruction is in Q form and whether Vm is a scalar indexed
18068 if (inst
.operands
[2].isscalar
)
18071 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
18072 inst
.instruction
&= 0xffffffd0;
18073 inst
.instruction
|= rm
;
18077 /* Redo Rn as well. */
18078 inst
.instruction
&= 0xfff0ff7f;
18079 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18080 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18085 /* Redo Rn and Rm. */
18086 inst
.instruction
&= 0xfff0ff50;
18087 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18088 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18089 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
18090 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
18095 do_neon_vfmal (void)
18097 return do_neon_fmac_maybe_scalar_long (0);
18101 do_neon_vfmsl (void)
18103 return do_neon_fmac_maybe_scalar_long (1);
18107 do_neon_dyadic_wide (void)
18109 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
18110 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18111 neon_mixed_length (et
, et
.size
);
18115 do_neon_dyadic_narrow (void)
18117 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18118 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
18119 /* Operand sign is unimportant, and the U bit is part of the opcode,
18120 so force the operand type to integer. */
18121 et
.type
= NT_integer
;
18122 neon_mixed_length (et
, et
.size
/ 2);
18126 do_neon_mul_sat_scalar_long (void)
18128 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
18132 do_neon_vmull (void)
18134 if (inst
.operands
[2].isscalar
)
18135 do_neon_mac_maybe_scalar_long ();
18138 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18139 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
18141 if (et
.type
== NT_poly
)
18142 NEON_ENCODE (POLY
, inst
);
18144 NEON_ENCODE (INTEGER
, inst
);
18146 /* For polynomial encoding the U bit must be zero, and the size must
18147 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18148 obviously, as 0b10). */
18151 /* Check we're on the correct architecture. */
18152 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
18154 _("Instruction form not available on this architecture.");
18159 neon_mixed_length (et
, et
.size
);
18166 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18167 struct neon_type_el et
= neon_check_type (3, rs
,
18168 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18169 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
18171 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
18172 _("shift out of range"));
18173 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18174 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18177 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18178 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18179 inst
.instruction
|= neon_quad (rs
) << 6;
18180 inst
.instruction
|= imm
<< 8;
18182 neon_dp_fixup (&inst
);
18188 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18189 struct neon_type_el et
= neon_check_type (2, rs
,
18190 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18191 unsigned op
= (inst
.instruction
>> 7) & 3;
18192 /* N (width of reversed regions) is encoded as part of the bitmask. We
18193 extract it here to check the elements to be reversed are smaller.
18194 Otherwise we'd get a reserved instruction. */
18195 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
18196 gas_assert (elsize
!= 0);
18197 constraint (et
.size
>= elsize
,
18198 _("elements must be smaller than reversal region"));
18199 neon_two_same (neon_quad (rs
), 1, et
.size
);
18205 if (inst
.operands
[1].isscalar
)
18207 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
18208 struct neon_type_el et
= neon_check_type (2, rs
,
18209 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18210 unsigned sizebits
= et
.size
>> 3;
18211 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18212 int logsize
= neon_logbits (et
.size
);
18213 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
18215 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
18218 NEON_ENCODE (SCALAR
, inst
);
18219 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18220 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18221 inst
.instruction
|= LOW4 (dm
);
18222 inst
.instruction
|= HI1 (dm
) << 5;
18223 inst
.instruction
|= neon_quad (rs
) << 6;
18224 inst
.instruction
|= x
<< 17;
18225 inst
.instruction
|= sizebits
<< 16;
18227 neon_dp_fixup (&inst
);
18231 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
18232 struct neon_type_el et
= neon_check_type (2, rs
,
18233 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18234 /* Duplicate ARM register to lanes of vector. */
18235 NEON_ENCODE (ARMREG
, inst
);
18238 case 8: inst
.instruction
|= 0x400000; break;
18239 case 16: inst
.instruction
|= 0x000020; break;
18240 case 32: inst
.instruction
|= 0x000000; break;
18243 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18246 inst
.instruction
|= neon_quad (rs
) << 21;
18247 /* The encoding for this instruction is identical for the ARM and Thumb
18248 variants, except for the condition field. */
18249 do_vfp_cond_or_thumb ();
18254 do_mve_mov (int toQ
)
18256 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18258 if (inst
.cond
> COND_ALWAYS
)
18259 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18261 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18270 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18271 _("Index one must be [2,3] and index two must be two less than"
18273 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18274 _("General purpose registers may not be the same"));
18275 constraint (inst
.operands
[Rt
].reg
== REG_SP
18276 || inst
.operands
[Rt2
].reg
== REG_SP
,
18278 constraint (inst
.operands
[Rt
].reg
== REG_PC
18279 || inst
.operands
[Rt2
].reg
== REG_PC
,
18282 inst
.instruction
= 0xec000f00;
18283 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18284 inst
.instruction
|= !!toQ
<< 20;
18285 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18286 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18287 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18288 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18294 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18297 if (inst
.cond
> COND_ALWAYS
)
18298 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18300 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18302 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18305 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18306 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18307 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18309 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18314 /* VMOV has particularly many variations. It can be one of:
18315 0. VMOV<c><q> <Qd>, <Qm>
18316 1. VMOV<c><q> <Dd>, <Dm>
18317 (Register operations, which are VORR with Rm = Rn.)
18318 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18319 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18321 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18322 (ARM register to scalar.)
18323 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18324 (Two ARM registers to vector.)
18325 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18326 (Scalar to ARM register.)
18327 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18328 (Vector to two ARM registers.)
18329 8. VMOV.F32 <Sd>, <Sm>
18330 9. VMOV.F64 <Dd>, <Dm>
18331 (VFP register moves.)
18332 10. VMOV.F32 <Sd>, #imm
18333 11. VMOV.F64 <Dd>, #imm
18334 (VFP float immediate load.)
18335 12. VMOV <Rd>, <Sm>
18336 (VFP single to ARM reg.)
18337 13. VMOV <Sd>, <Rm>
18338 (ARM reg to VFP single.)
18339 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18340 (Two ARM regs to two VFP singles.)
18341 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18342 (Two VFP singles to two ARM regs.)
18343 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18344 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18345 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18346 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18348 These cases can be disambiguated using neon_select_shape, except cases 1/9
18349 and 3/11 which depend on the operand type too.
18351 All the encoded bits are hardcoded by this function.
18353 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18354 Cases 5, 7 may be used with VFPv2 and above.
18356 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18357 can specify a type where it doesn't make sense to, and is ignored). */
18362 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
18363 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
18364 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
18365 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
18367 struct neon_type_el et
;
18368 const char *ldconst
= 0;
18372 case NS_DD
: /* case 1/9. */
18373 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18374 /* It is not an error here if no type is given. */
18376 if (et
.type
== NT_float
&& et
.size
== 64)
18378 do_vfp_nsyn_opcode ("fcpyd");
18381 /* fall through. */
18383 case NS_QQ
: /* case 0/1. */
18385 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18387 /* The architecture manual I have doesn't explicitly state which
18388 value the U bit should have for register->register moves, but
18389 the equivalent VORR instruction has U = 0, so do that. */
18390 inst
.instruction
= 0x0200110;
18391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18393 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18394 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18395 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18396 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18397 inst
.instruction
|= neon_quad (rs
) << 6;
18399 neon_dp_fixup (&inst
);
18403 case NS_DI
: /* case 3/11. */
18404 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18406 if (et
.type
== NT_float
&& et
.size
== 64)
18408 /* case 11 (fconstd). */
18409 ldconst
= "fconstd";
18410 goto encode_fconstd
;
18412 /* fall through. */
18414 case NS_QI
: /* case 2/3. */
18415 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18417 inst
.instruction
= 0x0800010;
18418 neon_move_immediate ();
18419 neon_dp_fixup (&inst
);
18422 case NS_SR
: /* case 4. */
18424 unsigned bcdebits
= 0;
18426 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
18427 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
18429 /* .<size> is optional here, defaulting to .32. */
18430 if (inst
.vectype
.elems
== 0
18431 && inst
.operands
[0].vectype
.type
== NT_invtype
18432 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18434 inst
.vectype
.el
[0].type
= NT_untyped
;
18435 inst
.vectype
.el
[0].size
= 32;
18436 inst
.vectype
.elems
= 1;
18439 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18440 logsize
= neon_logbits (et
.size
);
18444 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18445 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
18450 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18451 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18455 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18457 if (inst
.operands
[1].reg
== REG_SP
)
18458 as_tsktsk (MVE_BAD_SP
);
18459 else if (inst
.operands
[1].reg
== REG_PC
)
18460 as_tsktsk (MVE_BAD_PC
);
18462 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
18464 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18465 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18470 case 8: bcdebits
= 0x8; break;
18471 case 16: bcdebits
= 0x1; break;
18472 case 32: bcdebits
= 0x0; break;
18476 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18478 inst
.instruction
= 0xe000b10;
18479 do_vfp_cond_or_thumb ();
18480 inst
.instruction
|= LOW4 (dn
) << 16;
18481 inst
.instruction
|= HI1 (dn
) << 7;
18482 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18483 inst
.instruction
|= (bcdebits
& 3) << 5;
18484 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
18485 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18489 case NS_DRR
: /* case 5 (fmdrr). */
18490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18491 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18494 inst
.instruction
= 0xc400b10;
18495 do_vfp_cond_or_thumb ();
18496 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
18497 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
18498 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18499 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
18502 case NS_RS
: /* case 6. */
18505 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18506 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
18507 unsigned abcdebits
= 0;
18509 /* .<dt> is optional here, defaulting to .32. */
18510 if (inst
.vectype
.elems
== 0
18511 && inst
.operands
[0].vectype
.type
== NT_invtype
18512 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18514 inst
.vectype
.el
[0].type
= NT_untyped
;
18515 inst
.vectype
.el
[0].size
= 32;
18516 inst
.vectype
.elems
= 1;
18519 et
= neon_check_type (2, NS_NULL
,
18520 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
18521 logsize
= neon_logbits (et
.size
);
18525 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18526 && vfp_or_neon_is_neon (NEON_CHECK_CC
18527 | NEON_CHECK_ARCH
) == FAIL
)
18532 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18533 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18537 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18539 if (inst
.operands
[0].reg
== REG_SP
)
18540 as_tsktsk (MVE_BAD_SP
);
18541 else if (inst
.operands
[0].reg
== REG_PC
)
18542 as_tsktsk (MVE_BAD_PC
);
18545 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
18547 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18548 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18552 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
18553 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
18554 case 32: abcdebits
= 0x00; break;
18558 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18559 inst
.instruction
= 0xe100b10;
18560 do_vfp_cond_or_thumb ();
18561 inst
.instruction
|= LOW4 (dn
) << 16;
18562 inst
.instruction
|= HI1 (dn
) << 7;
18563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18564 inst
.instruction
|= (abcdebits
& 3) << 5;
18565 inst
.instruction
|= (abcdebits
>> 2) << 21;
18566 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18570 case NS_RRD
: /* case 7 (fmrrd). */
18571 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18572 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18575 inst
.instruction
= 0xc500b10;
18576 do_vfp_cond_or_thumb ();
18577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18578 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
18579 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18580 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18583 case NS_FF
: /* case 8 (fcpys). */
18584 do_vfp_nsyn_opcode ("fcpys");
18588 case NS_FI
: /* case 10 (fconsts). */
18589 ldconst
= "fconsts";
18591 if (!inst
.operands
[1].immisfloat
)
18594 /* Immediate has to fit in 8 bits so float is enough. */
18595 float imm
= (float) inst
.operands
[1].imm
;
18596 memcpy (&new_imm
, &imm
, sizeof (float));
18597 /* But the assembly may have been written to provide an integer
18598 bit pattern that equates to a float, so check that the
18599 conversion has worked. */
18600 if (is_quarter_float (new_imm
))
18602 if (is_quarter_float (inst
.operands
[1].imm
))
18603 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
18605 inst
.operands
[1].imm
= new_imm
;
18606 inst
.operands
[1].immisfloat
= 1;
18610 if (is_quarter_float (inst
.operands
[1].imm
))
18612 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
18613 do_vfp_nsyn_opcode (ldconst
);
18615 /* ARMv8.2 fp16 vmov.f16 instruction. */
18617 do_scalar_fp16_v82_encode ();
18620 first_error (_("immediate out of range"));
18624 case NS_RF
: /* case 12 (fmrs). */
18625 do_vfp_nsyn_opcode ("fmrs");
18626 /* ARMv8.2 fp16 vmov.f16 instruction. */
18628 do_scalar_fp16_v82_encode ();
18632 case NS_FR
: /* case 13 (fmsr). */
18633 do_vfp_nsyn_opcode ("fmsr");
18634 /* ARMv8.2 fp16 vmov.f16 instruction. */
18636 do_scalar_fp16_v82_encode ();
18646 /* The encoders for the fmrrs and fmsrr instructions expect three operands
18647 (one of which is a list), but we have parsed four. Do some fiddling to
18648 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
18650 case NS_RRFF
: /* case 14 (fmrrs). */
18651 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18652 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18654 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
18655 _("VFP registers must be adjacent"));
18656 inst
.operands
[2].imm
= 2;
18657 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18658 do_vfp_nsyn_opcode ("fmrrs");
18661 case NS_FFRR
: /* case 15 (fmsrr). */
18662 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18663 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18665 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
18666 _("VFP registers must be adjacent"));
18667 inst
.operands
[1] = inst
.operands
[2];
18668 inst
.operands
[2] = inst
.operands
[3];
18669 inst
.operands
[0].imm
= 2;
18670 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18671 do_vfp_nsyn_opcode ("fmsrr");
18675 /* neon_select_shape has determined that the instruction
18676 shape is wrong and has already set the error message. */
18687 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
18688 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
18689 && !inst
.operands
[2].present
))
18691 inst
.instruction
= 0;
18694 set_pred_insn_type (INSIDE_IT_INSN
);
18699 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18702 if (inst
.cond
!= COND_ALWAYS
)
18703 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18705 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
18706 | N_S16
| N_U16
| N_KEY
);
18708 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
18709 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18710 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
18711 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18712 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18713 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18718 do_neon_rshift_round_imm (void)
18720 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18721 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
18722 int imm
= inst
.operands
[2].imm
;
18724 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
18727 inst
.operands
[2].present
= 0;
18732 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18733 _("immediate out of range for shift"));
18734 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
18739 do_neon_movhf (void)
18741 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
18742 constraint (rs
!= NS_HH
, _("invalid suffix"));
18744 if (inst
.cond
!= COND_ALWAYS
)
18748 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
18749 " the behaviour is UNPREDICTABLE"));
18753 inst
.error
= BAD_COND
;
18758 do_vfp_sp_monadic ();
18761 inst
.instruction
|= 0xf0000000;
18765 do_neon_movl (void)
18767 struct neon_type_el et
= neon_check_type (2, NS_QD
,
18768 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18769 unsigned sizebits
= et
.size
>> 3;
18770 inst
.instruction
|= sizebits
<< 19;
18771 neon_two_same (0, et
.type
== NT_unsigned
, -1);
18777 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18778 struct neon_type_el et
= neon_check_type (2, rs
,
18779 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18780 NEON_ENCODE (INTEGER
, inst
);
18781 neon_two_same (neon_quad (rs
), 1, et
.size
);
18785 do_neon_zip_uzp (void)
18787 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18788 struct neon_type_el et
= neon_check_type (2, rs
,
18789 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18790 if (rs
== NS_DD
&& et
.size
== 32)
18792 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
18793 inst
.instruction
= N_MNEM_vtrn
;
18797 neon_two_same (neon_quad (rs
), 1, et
.size
);
18801 do_neon_sat_abs_neg (void)
18803 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18804 struct neon_type_el et
= neon_check_type (2, rs
,
18805 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18806 neon_two_same (neon_quad (rs
), 1, et
.size
);
18810 do_neon_pair_long (void)
18812 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18813 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18814 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
18815 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
18816 neon_two_same (neon_quad (rs
), 1, et
.size
);
18820 do_neon_recip_est (void)
18822 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18823 struct neon_type_el et
= neon_check_type (2, rs
,
18824 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
18825 inst
.instruction
|= (et
.type
== NT_float
) << 8;
18826 neon_two_same (neon_quad (rs
), 1, et
.size
);
18832 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18833 struct neon_type_el et
= neon_check_type (2, rs
,
18834 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18835 neon_two_same (neon_quad (rs
), 1, et
.size
);
18841 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18842 struct neon_type_el et
= neon_check_type (2, rs
,
18843 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
18844 neon_two_same (neon_quad (rs
), 1, et
.size
);
18850 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18851 struct neon_type_el et
= neon_check_type (2, rs
,
18852 N_EQK
| N_INT
, N_8
| N_KEY
);
18853 neon_two_same (neon_quad (rs
), 1, et
.size
);
18859 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18860 neon_two_same (neon_quad (rs
), 1, -1);
18864 do_neon_tbl_tbx (void)
18866 unsigned listlenbits
;
18867 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
18869 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
18871 first_error (_("bad list length for table lookup"));
18875 listlenbits
= inst
.operands
[1].imm
- 1;
18876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18878 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18879 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18880 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18881 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18882 inst
.instruction
|= listlenbits
<< 8;
18884 neon_dp_fixup (&inst
);
18888 do_neon_ldm_stm (void)
18890 /* P, U and L bits are part of bitmask. */
18891 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
18892 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
18894 if (inst
.operands
[1].issingle
)
18896 do_vfp_nsyn_ldm_stm (is_dbmode
);
18900 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
18901 _("writeback (!) must be used for VLDMDB and VSTMDB"));
18903 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
18904 _("register list must contain at least 1 and at most 16 "
18907 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
18908 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
18909 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18910 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
18912 inst
.instruction
|= offsetbits
;
18914 do_vfp_cond_or_thumb ();
18918 do_neon_ldr_str (void)
18920 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
18922 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
18923 And is UNPREDICTABLE in thumb mode. */
18925 && inst
.operands
[1].reg
== REG_PC
18926 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
18929 inst
.error
= _("Use of PC here is UNPREDICTABLE");
18930 else if (warn_on_deprecated
)
18931 as_tsktsk (_("Use of PC here is deprecated"));
18934 if (inst
.operands
[0].issingle
)
18937 do_vfp_nsyn_opcode ("flds");
18939 do_vfp_nsyn_opcode ("fsts");
18941 /* ARMv8.2 vldr.16/vstr.16 instruction. */
18942 if (inst
.vectype
.el
[0].size
== 16)
18943 do_scalar_fp16_v82_encode ();
18948 do_vfp_nsyn_opcode ("fldd");
18950 do_vfp_nsyn_opcode ("fstd");
18955 do_t_vldr_vstr_sysreg (void)
18957 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
18958 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
18960 /* Use of PC is UNPREDICTABLE. */
18961 if (inst
.operands
[1].reg
== REG_PC
)
18962 inst
.error
= _("Use of PC here is UNPREDICTABLE");
18964 if (inst
.operands
[1].immisreg
)
18965 inst
.error
= _("instruction does not accept register index");
18967 if (!inst
.operands
[1].isreg
)
18968 inst
.error
= _("instruction does not accept PC-relative addressing");
18970 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
18971 inst
.error
= _("immediate value out of range");
18973 inst
.instruction
= 0xec000f80;
18975 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
18976 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
18977 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
18978 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
18982 do_vldr_vstr (void)
18984 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
18986 /* VLDR/VSTR (System Register). */
18989 if (!mark_feature_used (&arm_ext_v8_1m_main
))
18990 as_bad (_("Instruction not permitted on this architecture"));
18992 do_t_vldr_vstr_sysreg ();
18997 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
18998 as_bad (_("Instruction not permitted on this architecture"));
18999 do_neon_ldr_str ();
19003 /* "interleave" version also handles non-interleaving register VLD1/VST1
19007 do_neon_ld_st_interleave (void)
19009 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
19010 N_8
| N_16
| N_32
| N_64
);
19011 unsigned alignbits
= 0;
19013 /* The bits in this table go:
19014 0: register stride of one (0) or two (1)
19015 1,2: register list length, minus one (1, 2, 3, 4).
19016 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19017 We use -1 for invalid entries. */
19018 const int typetable
[] =
19020 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19021 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19022 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19023 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19027 if (et
.type
== NT_invtype
)
19030 if (inst
.operands
[1].immisalign
)
19031 switch (inst
.operands
[1].imm
>> 8)
19033 case 64: alignbits
= 1; break;
19035 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
19036 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19037 goto bad_alignment
;
19041 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19042 goto bad_alignment
;
19047 first_error (_("bad alignment"));
19051 inst
.instruction
|= alignbits
<< 4;
19052 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19054 /* Bits [4:6] of the immediate in a list specifier encode register stride
19055 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19056 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19057 up the right value for "type" in a table based on this value and the given
19058 list style, then stick it back. */
19059 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
19060 | (((inst
.instruction
>> 8) & 3) << 3);
19062 typebits
= typetable
[idx
];
19064 constraint (typebits
== -1, _("bad list type for instruction"));
19065 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
19068 inst
.instruction
&= ~0xf00;
19069 inst
.instruction
|= typebits
<< 8;
19072 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19073 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19074 otherwise. The variable arguments are a list of pairs of legal (size, align)
19075 values, terminated with -1. */
19078 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
19081 int result
= FAIL
, thissize
, thisalign
;
19083 if (!inst
.operands
[1].immisalign
)
19089 va_start (ap
, do_alignment
);
19093 thissize
= va_arg (ap
, int);
19094 if (thissize
== -1)
19096 thisalign
= va_arg (ap
, int);
19098 if (size
== thissize
&& align
== thisalign
)
19101 while (result
!= SUCCESS
);
19105 if (result
== SUCCESS
)
19108 first_error (_("unsupported alignment for instruction"));
19114 do_neon_ld_st_lane (void)
19116 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19117 int align_good
, do_alignment
= 0;
19118 int logsize
= neon_logbits (et
.size
);
19119 int align
= inst
.operands
[1].imm
>> 8;
19120 int n
= (inst
.instruction
>> 8) & 3;
19121 int max_el
= 64 / et
.size
;
19123 if (et
.type
== NT_invtype
)
19126 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
19127 _("bad list length"));
19128 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
19129 _("scalar index out of range"));
19130 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
19132 _("stride of 2 unavailable when element size is 8"));
19136 case 0: /* VLD1 / VST1. */
19137 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
19139 if (align_good
== FAIL
)
19143 unsigned alignbits
= 0;
19146 case 16: alignbits
= 0x1; break;
19147 case 32: alignbits
= 0x3; break;
19150 inst
.instruction
|= alignbits
<< 4;
19154 case 1: /* VLD2 / VST2. */
19155 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
19156 16, 32, 32, 64, -1);
19157 if (align_good
== FAIL
)
19160 inst
.instruction
|= 1 << 4;
19163 case 2: /* VLD3 / VST3. */
19164 constraint (inst
.operands
[1].immisalign
,
19165 _("can't use alignment with this instruction"));
19168 case 3: /* VLD4 / VST4. */
19169 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19170 16, 64, 32, 64, 32, 128, -1);
19171 if (align_good
== FAIL
)
19175 unsigned alignbits
= 0;
19178 case 8: alignbits
= 0x1; break;
19179 case 16: alignbits
= 0x1; break;
19180 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
19183 inst
.instruction
|= alignbits
<< 4;
19190 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19191 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19192 inst
.instruction
|= 1 << (4 + logsize
);
19194 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
19195 inst
.instruction
|= logsize
<< 10;
19198 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19201 do_neon_ld_dup (void)
19203 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19204 int align_good
, do_alignment
= 0;
19206 if (et
.type
== NT_invtype
)
19209 switch ((inst
.instruction
>> 8) & 3)
19211 case 0: /* VLD1. */
19212 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
19213 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19214 &do_alignment
, 16, 16, 32, 32, -1);
19215 if (align_good
== FAIL
)
19217 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
19220 case 2: inst
.instruction
|= 1 << 5; break;
19221 default: first_error (_("bad list length")); return;
19223 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19226 case 1: /* VLD2. */
19227 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19228 &do_alignment
, 8, 16, 16, 32, 32, 64,
19230 if (align_good
== FAIL
)
19232 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
19233 _("bad list length"));
19234 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19235 inst
.instruction
|= 1 << 5;
19236 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19239 case 2: /* VLD3. */
19240 constraint (inst
.operands
[1].immisalign
,
19241 _("can't use alignment with this instruction"));
19242 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
19243 _("bad list length"));
19244 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19245 inst
.instruction
|= 1 << 5;
19246 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19249 case 3: /* VLD4. */
19251 int align
= inst
.operands
[1].imm
>> 8;
19252 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19253 16, 64, 32, 64, 32, 128, -1);
19254 if (align_good
== FAIL
)
19256 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19257 _("bad list length"));
19258 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19259 inst
.instruction
|= 1 << 5;
19260 if (et
.size
== 32 && align
== 128)
19261 inst
.instruction
|= 0x3 << 6;
19263 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19270 inst
.instruction
|= do_alignment
<< 4;
19273 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19274 apart from bits [11:4]. */
19277 do_neon_ldx_stx (void)
19279 if (inst
.operands
[1].isreg
)
19280 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19282 switch (NEON_LANE (inst
.operands
[0].imm
))
19284 case NEON_INTERLEAVE_LANES
:
19285 NEON_ENCODE (INTERLV
, inst
);
19286 do_neon_ld_st_interleave ();
19289 case NEON_ALL_LANES
:
19290 NEON_ENCODE (DUP
, inst
);
19291 if (inst
.instruction
== N_INV
)
19293 first_error ("only loads support such operands");
19300 NEON_ENCODE (LANE
, inst
);
19301 do_neon_ld_st_lane ();
19304 /* L bit comes from bit mask. */
19305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19309 if (inst
.operands
[1].postind
)
19311 int postreg
= inst
.operands
[1].imm
& 0xf;
19312 constraint (!inst
.operands
[1].immisreg
,
19313 _("post-index must be a register"));
19314 constraint (postreg
== 0xd || postreg
== 0xf,
19315 _("bad register for post-index"));
19316 inst
.instruction
|= postreg
;
19320 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
19321 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
19322 || inst
.relocs
[0].exp
.X_add_number
!= 0,
19325 if (inst
.operands
[1].writeback
)
19327 inst
.instruction
|= 0xd;
19330 inst
.instruction
|= 0xf;
19334 inst
.instruction
|= 0xf9000000;
19336 inst
.instruction
|= 0xf4000000;
19341 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
19343 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19344 D register operands. */
19345 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19346 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19349 NEON_ENCODE (FPV8
, inst
);
19351 if (rs
== NS_FFF
|| rs
== NS_HHH
)
19353 do_vfp_sp_dyadic ();
19355 /* ARMv8.2 fp16 instruction. */
19357 do_scalar_fp16_v82_encode ();
19360 do_vfp_dp_rd_rn_rm ();
19363 inst
.instruction
|= 0x100;
19365 inst
.instruction
|= 0xf0000000;
19371 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19373 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
19374 first_error (_("invalid instruction shape"));
19380 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19382 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
19385 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19388 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
19392 do_vrint_1 (enum neon_cvt_mode mode
)
19394 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
19395 struct neon_type_el et
;
19400 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19401 D register operands. */
19402 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19406 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
19408 if (et
.type
!= NT_invtype
)
19410 /* VFP encodings. */
19411 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19412 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
19413 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19415 NEON_ENCODE (FPV8
, inst
);
19416 if (rs
== NS_FF
|| rs
== NS_HH
)
19417 do_vfp_sp_monadic ();
19419 do_vfp_dp_rd_rm ();
19423 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
19424 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
19425 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
19426 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
19427 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
19428 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
19429 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
19433 inst
.instruction
|= (rs
== NS_DD
) << 8;
19434 do_vfp_cond_or_thumb ();
19436 /* ARMv8.2 fp16 vrint instruction. */
19438 do_scalar_fp16_v82_encode ();
19442 /* Neon encodings (or something broken...). */
19444 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
19446 if (et
.type
== NT_invtype
)
19449 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19450 NEON_ENCODE (FLOAT
, inst
);
19452 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19459 inst
.instruction
|= neon_quad (rs
) << 6;
19460 /* Mask off the original size bits and reencode them. */
19461 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
19462 | neon_logbits (et
.size
) << 18);
19466 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
19467 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
19468 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
19469 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
19470 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
19471 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
19472 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
19477 inst
.instruction
|= 0xfc000000;
19479 inst
.instruction
|= 0xf0000000;
19486 do_vrint_1 (neon_cvt_mode_x
);
19492 do_vrint_1 (neon_cvt_mode_z
);
19498 do_vrint_1 (neon_cvt_mode_r
);
19504 do_vrint_1 (neon_cvt_mode_a
);
19510 do_vrint_1 (neon_cvt_mode_n
);
19516 do_vrint_1 (neon_cvt_mode_p
);
19522 do_vrint_1 (neon_cvt_mode_m
);
19526 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
19528 unsigned regno
= NEON_SCALAR_REG (opnd
);
19529 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
19531 if (elsize
== 16 && elno
< 2 && regno
< 16)
19532 return regno
| (elno
<< 4);
19533 else if (elsize
== 32 && elno
== 0)
19536 first_error (_("scalar out of range"));
19543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19545 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19546 _("expression too complex"));
19547 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19548 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
19549 _("immediate out of range"));
19551 if (inst
.operands
[2].isscalar
)
19553 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
19554 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19555 N_KEY
| N_F16
| N_F32
).size
;
19556 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
19558 inst
.instruction
= 0xfe000800;
19559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19560 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19561 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19562 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19563 inst
.instruction
|= LOW4 (m
);
19564 inst
.instruction
|= HI1 (m
) << 5;
19565 inst
.instruction
|= neon_quad (rs
) << 6;
19566 inst
.instruction
|= rot
<< 20;
19567 inst
.instruction
|= (size
== 32) << 23;
19571 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19572 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19573 N_KEY
| N_F16
| N_F32
).size
;
19574 neon_three_same (neon_quad (rs
), 0, -1);
19575 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19576 inst
.instruction
|= 0xfc200800;
19577 inst
.instruction
|= rot
<< 23;
19578 inst
.instruction
|= (size
== 32) << 20;
19585 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19587 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19588 _("expression too complex"));
19589 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19590 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
19591 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19592 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19593 N_KEY
| N_F16
| N_F32
).size
;
19594 neon_three_same (neon_quad (rs
), 0, -1);
19595 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19596 inst
.instruction
|= 0xfc800800;
19597 inst
.instruction
|= (rot
== 270) << 24;
19598 inst
.instruction
|= (size
== 32) << 20;
19601 /* Dot Product instructions encoding support. */
19604 do_neon_dotproduct (int unsigned_p
)
19606 enum neon_shape rs
;
19607 unsigned scalar_oprd2
= 0;
19610 if (inst
.cond
!= COND_ALWAYS
)
19611 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
19612 "is UNPREDICTABLE"));
19614 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19617 /* Dot Product instructions are in three-same D/Q register format or the third
19618 operand can be a scalar index register. */
19619 if (inst
.operands
[2].isscalar
)
19621 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
19622 high8
= 0xfe000000;
19623 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
19627 high8
= 0xfc000000;
19628 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
19632 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
19634 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
19636 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
19637 Product instruction, so we pass 0 as the "ubit" parameter. And the
19638 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
19639 neon_three_same (neon_quad (rs
), 0, 32);
19641 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
19642 different NEON three-same encoding. */
19643 inst
.instruction
&= 0x00ffffff;
19644 inst
.instruction
|= high8
;
19645 /* Encode 'U' bit which indicates signedness. */
19646 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
19647 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
19648 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
19649 the instruction encoding. */
19650 if (inst
.operands
[2].isscalar
)
19652 inst
.instruction
&= 0xffffffd0;
19653 inst
.instruction
|= LOW4 (scalar_oprd2
);
19654 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
19658 /* Dot Product instructions for signed integer. */
19661 do_neon_dotproduct_s (void)
19663 return do_neon_dotproduct (0);
19666 /* Dot Product instructions for unsigned integer. */
19669 do_neon_dotproduct_u (void)
19671 return do_neon_dotproduct (1);
19674 /* Crypto v1 instructions. */
19676 do_crypto_2op_1 (unsigned elttype
, int op
)
19678 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19680 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
19686 NEON_ENCODE (INTEGER
, inst
);
19687 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19688 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19689 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19690 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19692 inst
.instruction
|= op
<< 6;
19695 inst
.instruction
|= 0xfc000000;
19697 inst
.instruction
|= 0xf0000000;
19701 do_crypto_3op_1 (int u
, int op
)
19703 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19705 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
19706 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
19711 NEON_ENCODE (INTEGER
, inst
);
19712 neon_three_same (1, u
, 8 << op
);
19718 do_crypto_2op_1 (N_8
, 0);
19724 do_crypto_2op_1 (N_8
, 1);
19730 do_crypto_2op_1 (N_8
, 2);
19736 do_crypto_2op_1 (N_8
, 3);
19742 do_crypto_3op_1 (0, 0);
19748 do_crypto_3op_1 (0, 1);
19754 do_crypto_3op_1 (0, 2);
19760 do_crypto_3op_1 (0, 3);
19766 do_crypto_3op_1 (1, 0);
19772 do_crypto_3op_1 (1, 1);
19776 do_sha256su1 (void)
19778 do_crypto_3op_1 (1, 2);
19784 do_crypto_2op_1 (N_32
, -1);
19790 do_crypto_2op_1 (N_32
, 0);
19794 do_sha256su0 (void)
19796 do_crypto_2op_1 (N_32
, 1);
19800 do_crc32_1 (unsigned int poly
, unsigned int sz
)
19802 unsigned int Rd
= inst
.operands
[0].reg
;
19803 unsigned int Rn
= inst
.operands
[1].reg
;
19804 unsigned int Rm
= inst
.operands
[2].reg
;
19806 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19807 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
19808 inst
.instruction
|= LOW4 (Rn
) << 16;
19809 inst
.instruction
|= LOW4 (Rm
);
19810 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
19811 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
19813 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
19814 as_warn (UNPRED_REG ("r15"));
19856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19858 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
19859 do_vfp_sp_dp_cvt ();
19860 do_vfp_cond_or_thumb ();
19864 /* Overall per-instruction processing. */
19866 /* We need to be able to fix up arbitrary expressions in some statements.
19867 This is so that we can handle symbols that are an arbitrary distance from
19868 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
19869 which returns part of an address in a form which will be valid for
19870 a data instruction. We do this by pushing the expression into a symbol
19871 in the expr_section, and creating a fix for that. */
19874 fix_new_arm (fragS
* frag
,
19888 /* Create an absolute valued symbol, so we have something to
19889 refer to in the object file. Unfortunately for us, gas's
19890 generic expression parsing will already have folded out
19891 any use of .set foo/.type foo %function that may have
19892 been used to set type information of the target location,
19893 that's being specified symbolically. We have to presume
19894 the user knows what they are doing. */
19898 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
19900 symbol
= symbol_find_or_make (name
);
19901 S_SET_SEGMENT (symbol
, absolute_section
);
19902 symbol_set_frag (symbol
, &zero_address_frag
);
19903 S_SET_VALUE (symbol
, exp
->X_add_number
);
19904 exp
->X_op
= O_symbol
;
19905 exp
->X_add_symbol
= symbol
;
19906 exp
->X_add_number
= 0;
19912 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
19913 (enum bfd_reloc_code_real
) reloc
);
19917 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
19918 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
19922 /* Mark whether the fix is to a THUMB instruction, or an ARM
19924 new_fix
->tc_fix_data
= thumb_mode
;
19927 /* Create a frg for an instruction requiring relaxation. */
19929 output_relax_insn (void)
19935 /* The size of the instruction is unknown, so tie the debug info to the
19936 start of the instruction. */
19937 dwarf2_emit_insn (0);
19939 switch (inst
.relocs
[0].exp
.X_op
)
19942 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
19943 offset
= inst
.relocs
[0].exp
.X_add_number
;
19947 offset
= inst
.relocs
[0].exp
.X_add_number
;
19950 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
19954 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
19955 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
19956 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
19959 /* Write a 32-bit thumb instruction to buf. */
19961 put_thumb32_insn (char * buf
, unsigned long insn
)
19963 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
19964 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
19968 output_inst (const char * str
)
19974 as_bad ("%s -- `%s'", inst
.error
, str
);
19979 output_relax_insn ();
19982 if (inst
.size
== 0)
19985 to
= frag_more (inst
.size
);
19986 /* PR 9814: Record the thumb mode into the current frag so that we know
19987 what type of NOP padding to use, if necessary. We override any previous
19988 setting so that if the mode has changed then the NOPS that we use will
19989 match the encoding of the last instruction in the frag. */
19990 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19992 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
19994 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
19995 put_thumb32_insn (to
, inst
.instruction
);
19997 else if (inst
.size
> INSN_SIZE
)
19999 gas_assert (inst
.size
== (2 * INSN_SIZE
));
20000 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
20001 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
20004 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
20007 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20009 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
20010 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
20011 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
20012 inst
.relocs
[r
].type
);
20015 dwarf2_emit_insn (inst
.size
);
20019 output_it_inst (int cond
, int mask
, char * to
)
20021 unsigned long instruction
= 0xbf00;
20024 instruction
|= mask
;
20025 instruction
|= cond
<< 4;
20029 to
= frag_more (2);
20031 dwarf2_emit_insn (2);
20035 md_number_to_chars (to
, instruction
, 2);
20040 /* Tag values used in struct asm_opcode's tag field. */
20043 OT_unconditional
, /* Instruction cannot be conditionalized.
20044 The ARM condition field is still 0xE. */
20045 OT_unconditionalF
, /* Instruction cannot be conditionalized
20046 and carries 0xF in its ARM condition field. */
20047 OT_csuffix
, /* Instruction takes a conditional suffix. */
20048 OT_csuffixF
, /* Some forms of the instruction take a scalar
20049 conditional suffix, others place 0xF where the
20050 condition field would be, others take a vector
20051 conditional suffix. */
20052 OT_cinfix3
, /* Instruction takes a conditional infix,
20053 beginning at character index 3. (In
20054 unified mode, it becomes a suffix.) */
20055 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
20056 tsts, cmps, cmns, and teqs. */
20057 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
20058 character index 3, even in unified mode. Used for
20059 legacy instructions where suffix and infix forms
20060 may be ambiguous. */
20061 OT_csuf_or_in3
, /* Instruction takes either a conditional
20062 suffix or an infix at character index 3. */
20063 OT_odd_infix_unc
, /* This is the unconditional variant of an
20064 instruction that takes a conditional infix
20065 at an unusual position. In unified mode,
20066 this variant will accept a suffix. */
20067 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
20068 are the conditional variants of instructions that
20069 take conditional infixes in unusual positions.
20070 The infix appears at character index
20071 (tag - OT_odd_infix_0). These are not accepted
20072 in unified mode. */
20075 /* Subroutine of md_assemble, responsible for looking up the primary
20076 opcode from the mnemonic the user wrote. STR points to the
20077 beginning of the mnemonic.
20079 This is not simply a hash table lookup, because of conditional
20080 variants. Most instructions have conditional variants, which are
20081 expressed with a _conditional affix_ to the mnemonic. If we were
20082 to encode each conditional variant as a literal string in the opcode
20083 table, it would have approximately 20,000 entries.
20085 Most mnemonics take this affix as a suffix, and in unified syntax,
20086 'most' is upgraded to 'all'. However, in the divided syntax, some
20087 instructions take the affix as an infix, notably the s-variants of
20088 the arithmetic instructions. Of those instructions, all but six
20089 have the infix appear after the third character of the mnemonic.
20091 Accordingly, the algorithm for looking up primary opcodes given
20094 1. Look up the identifier in the opcode table.
20095 If we find a match, go to step U.
20097 2. Look up the last two characters of the identifier in the
20098 conditions table. If we find a match, look up the first N-2
20099 characters of the identifier in the opcode table. If we
20100 find a match, go to step CE.
20102 3. Look up the fourth and fifth characters of the identifier in
20103 the conditions table. If we find a match, extract those
20104 characters from the identifier, and look up the remaining
20105 characters in the opcode table. If we find a match, go
20110 U. Examine the tag field of the opcode structure, in case this is
20111 one of the six instructions with its conditional infix in an
20112 unusual place. If it is, the tag tells us where to find the
20113 infix; look it up in the conditions table and set inst.cond
20114 accordingly. Otherwise, this is an unconditional instruction.
20115 Again set inst.cond accordingly. Return the opcode structure.
20117 CE. Examine the tag field to make sure this is an instruction that
20118 should receive a conditional suffix. If it is not, fail.
20119 Otherwise, set inst.cond from the suffix we already looked up,
20120 and return the opcode structure.
20122 CM. Examine the tag field to make sure this is an instruction that
20123 should receive a conditional infix after the third character.
20124 If it is not, fail. Otherwise, undo the edits to the current
20125 line of input and proceed as for case CE. */
20127 static const struct asm_opcode
*
20128 opcode_lookup (char **str
)
20132 const struct asm_opcode
*opcode
;
20133 const struct asm_cond
*cond
;
20136 /* Scan up to the end of the mnemonic, which must end in white space,
20137 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20138 for (base
= end
= *str
; *end
!= '\0'; end
++)
20139 if (*end
== ' ' || *end
== '.')
20145 /* Handle a possible width suffix and/or Neon type suffix. */
20150 /* The .w and .n suffixes are only valid if the unified syntax is in
20152 if (unified_syntax
&& end
[1] == 'w')
20154 else if (unified_syntax
&& end
[1] == 'n')
20159 inst
.vectype
.elems
= 0;
20161 *str
= end
+ offset
;
20163 if (end
[offset
] == '.')
20165 /* See if we have a Neon type suffix (possible in either unified or
20166 non-unified ARM syntax mode). */
20167 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
20170 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
20176 /* Look for unaffixed or special-case affixed mnemonic. */
20177 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20182 if (opcode
->tag
< OT_odd_infix_0
)
20184 inst
.cond
= COND_ALWAYS
;
20188 if (warn_on_deprecated
&& unified_syntax
)
20189 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20190 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
20191 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20194 inst
.cond
= cond
->value
;
20197 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20199 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20201 if (end
- base
< 2)
20204 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
20205 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20207 /* If this opcode can not be vector predicated then don't accept it with a
20208 vector predication code. */
20209 if (opcode
&& !opcode
->mayBeVecPred
)
20212 if (!opcode
|| !cond
)
20214 /* Cannot have a conditional suffix on a mnemonic of less than two
20216 if (end
- base
< 3)
20219 /* Look for suffixed mnemonic. */
20221 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20222 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20226 if (opcode
&& cond
)
20229 switch (opcode
->tag
)
20231 case OT_cinfix3_legacy
:
20232 /* Ignore conditional suffixes matched on infix only mnemonics. */
20236 case OT_cinfix3_deprecated
:
20237 case OT_odd_infix_unc
:
20238 if (!unified_syntax
)
20240 /* Fall through. */
20244 case OT_csuf_or_in3
:
20245 inst
.cond
= cond
->value
;
20248 case OT_unconditional
:
20249 case OT_unconditionalF
:
20251 inst
.cond
= cond
->value
;
20254 /* Delayed diagnostic. */
20255 inst
.error
= BAD_COND
;
20256 inst
.cond
= COND_ALWAYS
;
20265 /* Cannot have a usual-position infix on a mnemonic of less than
20266 six characters (five would be a suffix). */
20267 if (end
- base
< 6)
20270 /* Look for infixed mnemonic in the usual position. */
20272 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20276 memcpy (save
, affix
, 2);
20277 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
20278 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20280 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
20281 memcpy (affix
, save
, 2);
20284 && (opcode
->tag
== OT_cinfix3
20285 || opcode
->tag
== OT_cinfix3_deprecated
20286 || opcode
->tag
== OT_csuf_or_in3
20287 || opcode
->tag
== OT_cinfix3_legacy
))
20290 if (warn_on_deprecated
&& unified_syntax
20291 && (opcode
->tag
== OT_cinfix3
20292 || opcode
->tag
== OT_cinfix3_deprecated
))
20293 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20295 inst
.cond
= cond
->value
;
20302 /* This function generates an initial IT instruction, leaving its block
20303 virtually open for the new instructions. Eventually,
20304 the mask will be updated by now_pred_add_mask () each time
20305 a new instruction needs to be included in the IT block.
20306 Finally, the block is closed with close_automatic_it_block ().
20307 The block closure can be requested either from md_assemble (),
20308 a tencode (), or due to a label hook. */
20311 new_automatic_it_block (int cond
)
20313 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
20314 now_pred
.mask
= 0x18;
20315 now_pred
.cc
= cond
;
20316 now_pred
.block_length
= 1;
20317 mapping_state (MAP_THUMB
);
20318 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
20319 now_pred
.warn_deprecated
= FALSE
;
20320 now_pred
.insn_cond
= TRUE
;
20323 /* Close an automatic IT block.
20324 See comments in new_automatic_it_block (). */
20327 close_automatic_it_block (void)
20329 now_pred
.mask
= 0x10;
20330 now_pred
.block_length
= 0;
20333 /* Update the mask of the current automatically-generated IT
20334 instruction. See comments in new_automatic_it_block (). */
20337 now_pred_add_mask (int cond
)
20339 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20340 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20341 | ((bitvalue) << (nbit)))
20342 const int resulting_bit
= (cond
& 1);
20344 now_pred
.mask
&= 0xf;
20345 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20347 (5 - now_pred
.block_length
));
20348 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20350 ((5 - now_pred
.block_length
) - 1));
20351 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
20354 #undef SET_BIT_VALUE
20357 /* The IT blocks handling machinery is accessed through the these functions:
20358 it_fsm_pre_encode () from md_assemble ()
20359 set_pred_insn_type () optional, from the tencode functions
20360 set_pred_insn_type_last () ditto
20361 in_pred_block () ditto
20362 it_fsm_post_encode () from md_assemble ()
20363 force_automatic_it_block_close () from label handling functions
20366 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20367 initializing the IT insn type with a generic initial value depending
20368 on the inst.condition.
20369 2) During the tencode function, two things may happen:
20370 a) The tencode function overrides the IT insn type by
20371 calling either set_pred_insn_type (type) or
20372 set_pred_insn_type_last ().
20373 b) The tencode function queries the IT block state by
20374 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20376 Both set_pred_insn_type and in_pred_block run the internal FSM state
20377 handling function (handle_pred_state), because: a) setting the IT insn
20378 type may incur in an invalid state (exiting the function),
20379 and b) querying the state requires the FSM to be updated.
20380 Specifically we want to avoid creating an IT block for conditional
20381 branches, so it_fsm_pre_encode is actually a guess and we can't
20382 determine whether an IT block is required until the tencode () routine
20383 has decided what type of instruction this actually it.
20384 Because of this, if set_pred_insn_type and in_pred_block have to be
20385 used, set_pred_insn_type has to be called first.
20387 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
20388 that determines the insn IT type depending on the inst.cond code.
20389 When a tencode () routine encodes an instruction that can be
20390 either outside an IT block, or, in the case of being inside, has to be
20391 the last one, set_pred_insn_type_last () will determine the proper
20392 IT instruction type based on the inst.cond code. Otherwise,
20393 set_pred_insn_type can be called for overriding that logic or
20394 for covering other cases.
20396 Calling handle_pred_state () may not transition the IT block state to
20397 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
20398 still queried. Instead, if the FSM determines that the state should
20399 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
20400 after the tencode () function: that's what it_fsm_post_encode () does.
20402 Since in_pred_block () calls the state handling function to get an
20403 updated state, an error may occur (due to invalid insns combination).
20404 In that case, inst.error is set.
20405 Therefore, inst.error has to be checked after the execution of
20406 the tencode () routine.
20408 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
20409 any pending state change (if any) that didn't take place in
20410 handle_pred_state () as explained above. */
20413 it_fsm_pre_encode (void)
20415 if (inst
.cond
!= COND_ALWAYS
)
20416 inst
.pred_insn_type
= INSIDE_IT_INSN
;
20418 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
20420 now_pred
.state_handled
= 0;
20423 /* IT state FSM handling function. */
20424 /* MVE instructions and non-MVE instructions are handled differently because of
20425 the introduction of VPT blocks.
20426 Specifications say that any non-MVE instruction inside a VPT block is
20427 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
20428 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
20429 few exceptions we have MVE_UNPREDICABLE_INSN.
20430 The error messages provided depending on the different combinations possible
20431 are described in the cases below:
20432 For 'most' MVE instructions:
20433 1) In an IT block, with an IT code: syntax error
20434 2) In an IT block, with a VPT code: error: must be in a VPT block
20435 3) In an IT block, with no code: warning: UNPREDICTABLE
20436 4) In a VPT block, with an IT code: syntax error
20437 5) In a VPT block, with a VPT code: OK!
20438 6) In a VPT block, with no code: error: missing code
20439 7) Outside a pred block, with an IT code: error: syntax error
20440 8) Outside a pred block, with a VPT code: error: should be in a VPT block
20441 9) Outside a pred block, with no code: OK!
20442 For non-MVE instructions:
20443 10) In an IT block, with an IT code: OK!
20444 11) In an IT block, with a VPT code: syntax error
20445 12) In an IT block, with no code: error: missing code
20446 13) In a VPT block, with an IT code: error: should be in an IT block
20447 14) In a VPT block, with a VPT code: syntax error
20448 15) In a VPT block, with no code: UNPREDICTABLE
20449 16) Outside a pred block, with an IT code: error: should be in an IT block
20450 17) Outside a pred block, with a VPT code: syntax error
20451 18) Outside a pred block, with no code: OK!
20456 handle_pred_state (void)
20458 now_pred
.state_handled
= 1;
20459 now_pred
.insn_cond
= FALSE
;
20461 switch (now_pred
.state
)
20463 case OUTSIDE_PRED_BLOCK
:
20464 switch (inst
.pred_insn_type
)
20466 case MVE_UNPREDICABLE_INSN
:
20467 case MVE_OUTSIDE_PRED_INSN
:
20468 if (inst
.cond
< COND_ALWAYS
)
20470 /* Case 7: Outside a pred block, with an IT code: error: syntax
20472 inst
.error
= BAD_SYNTAX
;
20475 /* Case 9: Outside a pred block, with no code: OK! */
20477 case OUTSIDE_PRED_INSN
:
20478 if (inst
.cond
> COND_ALWAYS
)
20480 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20482 inst
.error
= BAD_SYNTAX
;
20485 /* Case 18: Outside a pred block, with no code: OK! */
20488 case INSIDE_VPT_INSN
:
20489 /* Case 8: Outside a pred block, with a VPT code: error: should be in
20491 inst
.error
= BAD_OUT_VPT
;
20494 case INSIDE_IT_INSN
:
20495 case INSIDE_IT_LAST_INSN
:
20496 if (inst
.cond
< COND_ALWAYS
)
20498 /* Case 16: Outside a pred block, with an IT code: error: should
20499 be in an IT block. */
20500 if (thumb_mode
== 0)
20503 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
20504 as_tsktsk (_("Warning: conditional outside an IT block"\
20509 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
20510 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
20512 /* Automatically generate the IT instruction. */
20513 new_automatic_it_block (inst
.cond
);
20514 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
20515 close_automatic_it_block ();
20519 inst
.error
= BAD_OUT_IT
;
20525 else if (inst
.cond
> COND_ALWAYS
)
20527 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20529 inst
.error
= BAD_SYNTAX
;
20534 case IF_INSIDE_IT_LAST_INSN
:
20535 case NEUTRAL_IT_INSN
:
20539 if (inst
.cond
!= COND_ALWAYS
)
20540 first_error (BAD_SYNTAX
);
20541 now_pred
.state
= MANUAL_PRED_BLOCK
;
20542 now_pred
.block_length
= 0;
20543 now_pred
.type
= VECTOR_PRED
;
20547 now_pred
.state
= MANUAL_PRED_BLOCK
;
20548 now_pred
.block_length
= 0;
20549 now_pred
.type
= SCALAR_PRED
;
20554 case AUTOMATIC_PRED_BLOCK
:
20555 /* Three things may happen now:
20556 a) We should increment current it block size;
20557 b) We should close current it block (closing insn or 4 insns);
20558 c) We should close current it block and start a new one (due
20559 to incompatible conditions or
20560 4 insns-length block reached). */
20562 switch (inst
.pred_insn_type
)
20564 case INSIDE_VPT_INSN
:
20566 case MVE_UNPREDICABLE_INSN
:
20567 case MVE_OUTSIDE_PRED_INSN
:
20569 case OUTSIDE_PRED_INSN
:
20570 /* The closure of the block shall happen immediately,
20571 so any in_pred_block () call reports the block as closed. */
20572 force_automatic_it_block_close ();
20575 case INSIDE_IT_INSN
:
20576 case INSIDE_IT_LAST_INSN
:
20577 case IF_INSIDE_IT_LAST_INSN
:
20578 now_pred
.block_length
++;
20580 if (now_pred
.block_length
> 4
20581 || !now_pred_compatible (inst
.cond
))
20583 force_automatic_it_block_close ();
20584 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
20585 new_automatic_it_block (inst
.cond
);
20589 now_pred
.insn_cond
= TRUE
;
20590 now_pred_add_mask (inst
.cond
);
20593 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
20594 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
20595 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
20596 close_automatic_it_block ();
20599 case NEUTRAL_IT_INSN
:
20600 now_pred
.block_length
++;
20601 now_pred
.insn_cond
= TRUE
;
20603 if (now_pred
.block_length
> 4)
20604 force_automatic_it_block_close ();
20606 now_pred_add_mask (now_pred
.cc
& 1);
20610 close_automatic_it_block ();
20611 now_pred
.state
= MANUAL_PRED_BLOCK
;
20616 case MANUAL_PRED_BLOCK
:
20619 if (now_pred
.type
== SCALAR_PRED
)
20621 /* Check conditional suffixes. */
20622 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
20623 now_pred
.mask
<<= 1;
20624 now_pred
.mask
&= 0x1f;
20625 is_last
= (now_pred
.mask
== 0x10);
20629 now_pred
.cc
^= (now_pred
.mask
>> 4);
20630 cond
= now_pred
.cc
+ 0xf;
20631 now_pred
.mask
<<= 1;
20632 now_pred
.mask
&= 0x1f;
20633 is_last
= now_pred
.mask
== 0x10;
20635 now_pred
.insn_cond
= TRUE
;
20637 switch (inst
.pred_insn_type
)
20639 case OUTSIDE_PRED_INSN
:
20640 if (now_pred
.type
== SCALAR_PRED
)
20642 if (inst
.cond
== COND_ALWAYS
)
20644 /* Case 12: In an IT block, with no code: error: missing
20646 inst
.error
= BAD_NOT_IT
;
20649 else if (inst
.cond
> COND_ALWAYS
)
20651 /* Case 11: In an IT block, with a VPT code: syntax error.
20653 inst
.error
= BAD_SYNTAX
;
20656 else if (thumb_mode
)
20658 /* This is for some special cases where a non-MVE
20659 instruction is not allowed in an IT block, such as cbz,
20660 but are put into one with a condition code.
20661 You could argue this should be a syntax error, but we
20662 gave the 'not allowed in IT block' diagnostic in the
20663 past so we will keep doing so. */
20664 inst
.error
= BAD_NOT_IT
;
20671 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
20672 as_tsktsk (MVE_NOT_VPT
);
20675 case MVE_OUTSIDE_PRED_INSN
:
20676 if (now_pred
.type
== SCALAR_PRED
)
20678 if (inst
.cond
== COND_ALWAYS
)
20680 /* Case 3: In an IT block, with no code: warning:
20682 as_tsktsk (MVE_NOT_IT
);
20685 else if (inst
.cond
< COND_ALWAYS
)
20687 /* Case 1: In an IT block, with an IT code: syntax error.
20689 inst
.error
= BAD_SYNTAX
;
20697 if (inst
.cond
< COND_ALWAYS
)
20699 /* Case 4: In a VPT block, with an IT code: syntax error.
20701 inst
.error
= BAD_SYNTAX
;
20704 else if (inst
.cond
== COND_ALWAYS
)
20706 /* Case 6: In a VPT block, with no code: error: missing
20708 inst
.error
= BAD_NOT_VPT
;
20716 case MVE_UNPREDICABLE_INSN
:
20717 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
20719 case INSIDE_IT_INSN
:
20720 if (inst
.cond
> COND_ALWAYS
)
20722 /* Case 11: In an IT block, with a VPT code: syntax error. */
20723 /* Case 14: In a VPT block, with a VPT code: syntax error. */
20724 inst
.error
= BAD_SYNTAX
;
20727 else if (now_pred
.type
== SCALAR_PRED
)
20729 /* Case 10: In an IT block, with an IT code: OK! */
20730 if (cond
!= inst
.cond
)
20732 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
20739 /* Case 13: In a VPT block, with an IT code: error: should be
20741 inst
.error
= BAD_OUT_IT
;
20746 case INSIDE_VPT_INSN
:
20747 if (now_pred
.type
== SCALAR_PRED
)
20749 /* Case 2: In an IT block, with a VPT code: error: must be in a
20751 inst
.error
= BAD_OUT_VPT
;
20754 /* Case 5: In a VPT block, with a VPT code: OK! */
20755 else if (cond
!= inst
.cond
)
20757 inst
.error
= BAD_VPT_COND
;
20761 case INSIDE_IT_LAST_INSN
:
20762 case IF_INSIDE_IT_LAST_INSN
:
20763 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
20765 /* Case 4: In a VPT block, with an IT code: syntax error. */
20766 /* Case 11: In an IT block, with a VPT code: syntax error. */
20767 inst
.error
= BAD_SYNTAX
;
20770 else if (cond
!= inst
.cond
)
20772 inst
.error
= BAD_IT_COND
;
20777 inst
.error
= BAD_BRANCH
;
20782 case NEUTRAL_IT_INSN
:
20783 /* The BKPT instruction is unconditional even in a IT or VPT
20788 if (now_pred
.type
== SCALAR_PRED
)
20790 inst
.error
= BAD_IT_IT
;
20793 /* fall through. */
20795 if (inst
.cond
== COND_ALWAYS
)
20797 /* Executing a VPT/VPST instruction inside an IT block or a
20798 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
20800 if (now_pred
.type
== SCALAR_PRED
)
20801 as_tsktsk (MVE_NOT_IT
);
20803 as_tsktsk (MVE_NOT_VPT
);
20808 /* VPT/VPST do not accept condition codes. */
20809 inst
.error
= BAD_SYNTAX
;
20820 struct depr_insn_mask
20822 unsigned long pattern
;
20823 unsigned long mask
;
20824 const char* description
;
20827 /* List of 16-bit instruction patterns deprecated in an IT block in
20829 static const struct depr_insn_mask depr_it_insns
[] = {
20830 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
20831 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
20832 { 0xa000, 0xb800, N_("ADR") },
20833 { 0x4800, 0xf800, N_("Literal loads") },
20834 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
20835 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
20836 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
20837 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
20838 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
20843 it_fsm_post_encode (void)
20847 if (!now_pred
.state_handled
)
20848 handle_pred_state ();
20850 if (now_pred
.insn_cond
20851 && !now_pred
.warn_deprecated
20852 && warn_on_deprecated
20853 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
20854 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
20856 if (inst
.instruction
>= 0x10000)
20858 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
20859 "performance deprecated in ARMv8-A and ARMv8-R"));
20860 now_pred
.warn_deprecated
= TRUE
;
20864 const struct depr_insn_mask
*p
= depr_it_insns
;
20866 while (p
->mask
!= 0)
20868 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
20870 as_tsktsk (_("IT blocks containing 16-bit Thumb "
20871 "instructions of the following class are "
20872 "performance deprecated in ARMv8-A and "
20873 "ARMv8-R: %s"), p
->description
);
20874 now_pred
.warn_deprecated
= TRUE
;
20882 if (now_pred
.block_length
> 1)
20884 as_tsktsk (_("IT blocks containing more than one conditional "
20885 "instruction are performance deprecated in ARMv8-A and "
20887 now_pred
.warn_deprecated
= TRUE
;
20891 is_last
= (now_pred
.mask
== 0x10);
20894 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
20900 force_automatic_it_block_close (void)
20902 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
20904 close_automatic_it_block ();
20905 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
20911 in_pred_block (void)
20913 if (!now_pred
.state_handled
)
20914 handle_pred_state ();
20916 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
20919 /* Whether OPCODE only has T32 encoding. Since this function is only used by
20920 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
20921 here, hence the "known" in the function name. */
20924 known_t32_only_insn (const struct asm_opcode
*opcode
)
20926 /* Original Thumb-1 wide instruction. */
20927 if (opcode
->tencode
== do_t_blx
20928 || opcode
->tencode
== do_t_branch23
20929 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
20930 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
20933 /* Wide-only instruction added to ARMv8-M Baseline. */
20934 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
20935 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
20936 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
20937 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
20943 /* Whether wide instruction variant can be used if available for a valid OPCODE
20947 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
20949 if (known_t32_only_insn (opcode
))
20952 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
20953 of variant T3 of B.W is checked in do_t_branch. */
20954 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
20955 && opcode
->tencode
== do_t_branch
)
20958 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
20959 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
20960 && opcode
->tencode
== do_t_mov_cmp
20961 /* Make sure CMP instruction is not affected. */
20962 && opcode
->aencode
== do_mov
)
20965 /* Wide instruction variants of all instructions with narrow *and* wide
20966 variants become available with ARMv6t2. Other opcodes are either
20967 narrow-only or wide-only and are thus available if OPCODE is valid. */
20968 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
20971 /* OPCODE with narrow only instruction variant or wide variant not
20977 md_assemble (char *str
)
20980 const struct asm_opcode
* opcode
;
20982 /* Align the previous label if needed. */
20983 if (last_label_seen
!= NULL
)
20985 symbol_set_frag (last_label_seen
, frag_now
);
20986 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
20987 S_SET_SEGMENT (last_label_seen
, now_seg
);
20990 memset (&inst
, '\0', sizeof (inst
));
20992 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20993 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
20995 opcode
= opcode_lookup (&p
);
20998 /* It wasn't an instruction, but it might be a register alias of
20999 the form alias .req reg, or a Neon .dn/.qn directive. */
21000 if (! create_register_alias (str
, p
)
21001 && ! create_neon_reg_alias (str
, p
))
21002 as_bad (_("bad instruction `%s'"), str
);
21007 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
21008 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21010 /* The value which unconditional instructions should have in place of the
21011 condition field. */
21012 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
21016 arm_feature_set variant
;
21018 variant
= cpu_variant
;
21019 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21020 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
21021 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
21022 /* Check that this instruction is supported for this CPU. */
21023 if (!opcode
->tvariant
21024 || (thumb_mode
== 1
21025 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
21027 if (opcode
->tencode
== do_t_swi
)
21028 as_bad (_("SVC is not permitted on this architecture"));
21030 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
21033 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
21034 && opcode
->tencode
!= do_t_branch
)
21036 as_bad (_("Thumb does not support conditional execution"));
21040 /* Two things are addressed here:
21041 1) Implicit require narrow instructions on Thumb-1.
21042 This avoids relaxation accidentally introducing Thumb-2
21044 2) Reject wide instructions in non Thumb-2 cores.
21046 Only instructions with narrow and wide variants need to be handled
21047 but selecting all non wide-only instructions is easier. */
21048 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
21049 && !t32_insn_ok (variant
, opcode
))
21051 if (inst
.size_req
== 0)
21053 else if (inst
.size_req
== 4)
21055 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
21056 as_bad (_("selected processor does not support 32bit wide "
21057 "variant of instruction `%s'"), str
);
21059 as_bad (_("selected processor does not support `%s' in "
21060 "Thumb-2 mode"), str
);
21065 inst
.instruction
= opcode
->tvalue
;
21067 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
21069 /* Prepare the pred_insn_type for those encodings that don't set
21071 it_fsm_pre_encode ();
21073 opcode
->tencode ();
21075 it_fsm_post_encode ();
21078 if (!(inst
.error
|| inst
.relax
))
21080 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
21081 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
21082 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
21084 as_bad (_("cannot honor width suffix -- `%s'"), str
);
21089 /* Something has gone badly wrong if we try to relax a fixed size
21091 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
21093 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21094 *opcode
->tvariant
);
21095 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21096 set those bits when Thumb-2 32-bit instructions are seen. The impact
21097 of relaxable instructions will be considered later after we finish all
21099 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
21100 variant
= arm_arch_none
;
21102 variant
= cpu_variant
;
21103 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
21104 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21107 check_neon_suffixes
;
21111 mapping_state (MAP_THUMB
);
21114 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21118 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21119 is_bx
= (opcode
->aencode
== do_bx
);
21121 /* Check that this instruction is supported for this CPU. */
21122 if (!(is_bx
&& fix_v4bx
)
21123 && !(opcode
->avariant
&&
21124 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
21126 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
21131 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
21135 inst
.instruction
= opcode
->avalue
;
21136 if (opcode
->tag
== OT_unconditionalF
)
21137 inst
.instruction
|= 0xFU
<< 28;
21139 inst
.instruction
|= inst
.cond
<< 28;
21140 inst
.size
= INSN_SIZE
;
21141 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
21143 it_fsm_pre_encode ();
21144 opcode
->aencode ();
21145 it_fsm_post_encode ();
21147 /* Arm mode bx is marked as both v4T and v5 because it's still required
21148 on a hypothetical non-thumb v5 core. */
21150 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
21152 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
21153 *opcode
->avariant
);
21155 check_neon_suffixes
;
21159 mapping_state (MAP_ARM
);
21164 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21172 check_pred_blocks_finished (void)
21177 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
21178 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
21179 == MANUAL_PRED_BLOCK
)
21181 if (now_pred
.type
== SCALAR_PRED
)
21182 as_warn (_("section '%s' finished with an open IT block."),
21185 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21189 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
21191 if (now_pred
.type
== SCALAR_PRED
)
21192 as_warn (_("file finished with an open IT block."));
21194 as_warn (_("file finished with an open VPT/VPST block."));
21199 /* Various frobbings of labels and their addresses. */
21202 arm_start_line_hook (void)
21204 last_label_seen
= NULL
;
21208 arm_frob_label (symbolS
* sym
)
21210 last_label_seen
= sym
;
21212 ARM_SET_THUMB (sym
, thumb_mode
);
21214 #if defined OBJ_COFF || defined OBJ_ELF
21215 ARM_SET_INTERWORK (sym
, support_interwork
);
21218 force_automatic_it_block_close ();
21220 /* Note - do not allow local symbols (.Lxxx) to be labelled
21221 as Thumb functions. This is because these labels, whilst
21222 they exist inside Thumb code, are not the entry points for
21223 possible ARM->Thumb calls. Also, these labels can be used
21224 as part of a computed goto or switch statement. eg gcc
21225 can generate code that looks like this:
21227 ldr r2, [pc, .Laaa]
21237 The first instruction loads the address of the jump table.
21238 The second instruction converts a table index into a byte offset.
21239 The third instruction gets the jump address out of the table.
21240 The fourth instruction performs the jump.
21242 If the address stored at .Laaa is that of a symbol which has the
21243 Thumb_Func bit set, then the linker will arrange for this address
21244 to have the bottom bit set, which in turn would mean that the
21245 address computation performed by the third instruction would end
21246 up with the bottom bit set. Since the ARM is capable of unaligned
21247 word loads, the instruction would then load the incorrect address
21248 out of the jump table, and chaos would ensue. */
21249 if (label_is_thumb_function_name
21250 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21251 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21253 /* When the address of a Thumb function is taken the bottom
21254 bit of that address should be set. This will allow
21255 interworking between Arm and Thumb functions to work
21258 THUMB_SET_FUNC (sym
, 1);
21260 label_is_thumb_function_name
= FALSE
;
21263 dwarf2_emit_label (sym
);
21267 arm_data_in_code (void)
21269 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
21271 *input_line_pointer
= '/';
21272 input_line_pointer
+= 5;
21273 *input_line_pointer
= 0;
21281 arm_canonicalize_symbol_name (char * name
)
21285 if (thumb_mode
&& (len
= strlen (name
)) > 5
21286 && streq (name
+ len
- 5, "/data"))
21287 *(name
+ len
- 5) = 0;
21292 /* Table of all register names defined by default. The user can
21293 define additional names with .req. Note that all register names
21294 should appear in both upper and lowercase variants. Some registers
21295 also have mixed-case names. */
21297 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21298 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21299 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21300 #define REGSET(p,t) \
21301 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21302 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21303 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21304 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21305 #define REGSETH(p,t) \
21306 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21307 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21308 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21309 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21310 #define REGSET2(p,t) \
21311 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21312 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21313 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21314 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21315 #define SPLRBANK(base,bank,t) \
21316 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21317 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21318 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21319 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21320 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21321 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21323 static const struct reg_entry reg_names
[] =
21325 /* ARM integer registers. */
21326 REGSET(r
, RN
), REGSET(R
, RN
),
21328 /* ATPCS synonyms. */
21329 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
21330 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
21331 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
21333 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
21334 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
21335 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
21337 /* Well-known aliases. */
21338 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
21339 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
21341 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
21342 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
21344 /* Defining the new Zero register from ARMv8.1-M. */
21348 /* Coprocessor numbers. */
21349 REGSET(p
, CP
), REGSET(P
, CP
),
21351 /* Coprocessor register numbers. The "cr" variants are for backward
21353 REGSET(c
, CN
), REGSET(C
, CN
),
21354 REGSET(cr
, CN
), REGSET(CR
, CN
),
21356 /* ARM banked registers. */
21357 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
21358 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
21359 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
21360 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
21361 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
21362 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
21363 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
21365 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
21366 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
21367 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
21368 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
21369 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
21370 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
21371 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
21372 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
21374 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
21375 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
21376 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
21377 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
21378 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
21379 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
21380 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
21381 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21382 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21384 /* FPA registers. */
21385 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
21386 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
21388 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
21389 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
21391 /* VFP SP registers. */
21392 REGSET(s
,VFS
), REGSET(S
,VFS
),
21393 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
21395 /* VFP DP Registers. */
21396 REGSET(d
,VFD
), REGSET(D
,VFD
),
21397 /* Extra Neon DP registers. */
21398 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
21400 /* Neon QP registers. */
21401 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
21403 /* VFP control registers. */
21404 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
21405 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
21406 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
21407 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
21408 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
21409 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
21410 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
21412 /* Maverick DSP coprocessor registers. */
21413 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
21414 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
21416 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
21417 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
21418 REGDEF(dspsc
,0,DSPSC
),
21420 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
21421 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
21422 REGDEF(DSPSC
,0,DSPSC
),
21424 /* iWMMXt data registers - p0, c0-15. */
21425 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
21427 /* iWMMXt control registers - p1, c0-3. */
21428 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
21429 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
21430 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
21431 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
21433 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
21434 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
21435 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
21436 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
21437 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
21439 /* XScale accumulator registers. */
21440 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
21446 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
21447 within psr_required_here. */
21448 static const struct asm_psr psrs
[] =
21450 /* Backward compatibility notation. Note that "all" is no longer
21451 truly all possible PSR bits. */
21452 {"all", PSR_c
| PSR_f
},
21456 /* Individual flags. */
21462 /* Combinations of flags. */
21463 {"fs", PSR_f
| PSR_s
},
21464 {"fx", PSR_f
| PSR_x
},
21465 {"fc", PSR_f
| PSR_c
},
21466 {"sf", PSR_s
| PSR_f
},
21467 {"sx", PSR_s
| PSR_x
},
21468 {"sc", PSR_s
| PSR_c
},
21469 {"xf", PSR_x
| PSR_f
},
21470 {"xs", PSR_x
| PSR_s
},
21471 {"xc", PSR_x
| PSR_c
},
21472 {"cf", PSR_c
| PSR_f
},
21473 {"cs", PSR_c
| PSR_s
},
21474 {"cx", PSR_c
| PSR_x
},
21475 {"fsx", PSR_f
| PSR_s
| PSR_x
},
21476 {"fsc", PSR_f
| PSR_s
| PSR_c
},
21477 {"fxs", PSR_f
| PSR_x
| PSR_s
},
21478 {"fxc", PSR_f
| PSR_x
| PSR_c
},
21479 {"fcs", PSR_f
| PSR_c
| PSR_s
},
21480 {"fcx", PSR_f
| PSR_c
| PSR_x
},
21481 {"sfx", PSR_s
| PSR_f
| PSR_x
},
21482 {"sfc", PSR_s
| PSR_f
| PSR_c
},
21483 {"sxf", PSR_s
| PSR_x
| PSR_f
},
21484 {"sxc", PSR_s
| PSR_x
| PSR_c
},
21485 {"scf", PSR_s
| PSR_c
| PSR_f
},
21486 {"scx", PSR_s
| PSR_c
| PSR_x
},
21487 {"xfs", PSR_x
| PSR_f
| PSR_s
},
21488 {"xfc", PSR_x
| PSR_f
| PSR_c
},
21489 {"xsf", PSR_x
| PSR_s
| PSR_f
},
21490 {"xsc", PSR_x
| PSR_s
| PSR_c
},
21491 {"xcf", PSR_x
| PSR_c
| PSR_f
},
21492 {"xcs", PSR_x
| PSR_c
| PSR_s
},
21493 {"cfs", PSR_c
| PSR_f
| PSR_s
},
21494 {"cfx", PSR_c
| PSR_f
| PSR_x
},
21495 {"csf", PSR_c
| PSR_s
| PSR_f
},
21496 {"csx", PSR_c
| PSR_s
| PSR_x
},
21497 {"cxf", PSR_c
| PSR_x
| PSR_f
},
21498 {"cxs", PSR_c
| PSR_x
| PSR_s
},
21499 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
21500 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
21501 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
21502 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
21503 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
21504 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
21505 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
21506 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
21507 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
21508 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
21509 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
21510 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
21511 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
21512 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
21513 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
21514 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
21515 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
21516 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
21517 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
21518 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
21519 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
21520 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
21521 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
21522 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
21525 /* Table of V7M psr names. */
21526 static const struct asm_psr v7m_psrs
[] =
21528 {"apsr", 0x0 }, {"APSR", 0x0 },
21529 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
21530 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
21531 {"psr", 0x3 }, {"PSR", 0x3 },
21532 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
21533 {"ipsr", 0x5 }, {"IPSR", 0x5 },
21534 {"epsr", 0x6 }, {"EPSR", 0x6 },
21535 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
21536 {"msp", 0x8 }, {"MSP", 0x8 },
21537 {"psp", 0x9 }, {"PSP", 0x9 },
21538 {"msplim", 0xa }, {"MSPLIM", 0xa },
21539 {"psplim", 0xb }, {"PSPLIM", 0xb },
21540 {"primask", 0x10}, {"PRIMASK", 0x10},
21541 {"basepri", 0x11}, {"BASEPRI", 0x11},
21542 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
21543 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
21544 {"control", 0x14}, {"CONTROL", 0x14},
21545 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
21546 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
21547 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
21548 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
21549 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
21550 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
21551 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
21552 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
21553 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
21556 /* Table of all shift-in-operand names. */
21557 static const struct asm_shift_name shift_names
[] =
21559 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
21560 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
21561 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
21562 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
21563 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
21564 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
21565 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
21568 /* Table of all explicit relocation names. */
21570 static struct reloc_entry reloc_names
[] =
21572 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
21573 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
21574 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
21575 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
21576 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
21577 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
21578 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
21579 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
21580 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
21581 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
21582 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
21583 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
21584 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
21585 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
21586 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
21587 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
21588 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
21589 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
21590 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
21591 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
21592 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21593 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21594 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
21595 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
21596 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
21597 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
21598 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
21602 /* Table of all conditional affixes. */
21603 static const struct asm_cond conds
[] =
21607 {"cs", 0x2}, {"hs", 0x2},
21608 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
21621 static const struct asm_cond vconds
[] =
21627 #define UL_BARRIER(L,U,CODE,FEAT) \
21628 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
21629 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
21631 static struct asm_barrier_opt barrier_opt_names
[] =
21633 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
21634 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
21635 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
21636 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
21637 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
21638 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
21639 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
21640 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
21641 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
21642 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
21643 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
21644 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
21645 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
21646 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
21647 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
21648 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
21653 /* Table of ARM-format instructions. */
21655 /* Macros for gluing together operand strings. N.B. In all cases
21656 other than OPS0, the trailing OP_stop comes from default
21657 zero-initialization of the unspecified elements of the array. */
21658 #define OPS0() { OP_stop, }
21659 #define OPS1(a) { OP_##a, }
21660 #define OPS2(a,b) { OP_##a,OP_##b, }
21661 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
21662 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
21663 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
21664 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
21666 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
21667 This is useful when mixing operands for ARM and THUMB, i.e. using the
21668 MIX_ARM_THUMB_OPERANDS macro.
21669 In order to use these macros, prefix the number of operands with _
21671 #define OPS_1(a) { a, }
21672 #define OPS_2(a,b) { a,b, }
21673 #define OPS_3(a,b,c) { a,b,c, }
21674 #define OPS_4(a,b,c,d) { a,b,c,d, }
21675 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
21676 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
21678 /* These macros abstract out the exact format of the mnemonic table and
21679 save some repeated characters. */
21681 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
21682 #define TxCE(mnem, op, top, nops, ops, ae, te) \
21683 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
21684 THUMB_VARIANT, do_##ae, do_##te, 0 }
21686 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
21687 a T_MNEM_xyz enumerator. */
21688 #define TCE(mnem, aop, top, nops, ops, ae, te) \
21689 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
21690 #define tCE(mnem, aop, top, nops, ops, ae, te) \
21691 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21693 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
21694 infix after the third character. */
21695 #define TxC3(mnem, op, top, nops, ops, ae, te) \
21696 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
21697 THUMB_VARIANT, do_##ae, do_##te, 0 }
21698 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
21699 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
21700 THUMB_VARIANT, do_##ae, do_##te, 0 }
21701 #define TC3(mnem, aop, top, nops, ops, ae, te) \
21702 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
21703 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
21704 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
21705 #define tC3(mnem, aop, top, nops, ops, ae, te) \
21706 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21707 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
21708 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21710 /* Mnemonic that cannot be conditionalized. The ARM condition-code
21711 field is still 0xE. Many of the Thumb variants can be executed
21712 conditionally, so this is checked separately. */
21713 #define TUE(mnem, op, top, nops, ops, ae, te) \
21714 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21715 THUMB_VARIANT, do_##ae, do_##te, 0 }
21717 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
21718 Used by mnemonics that have very minimal differences in the encoding for
21719 ARM and Thumb variants and can be handled in a common function. */
21720 #define TUEc(mnem, op, top, nops, ops, en) \
21721 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21722 THUMB_VARIANT, do_##en, do_##en, 0 }
21724 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
21725 condition code field. */
21726 #define TUF(mnem, op, top, nops, ops, ae, te) \
21727 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
21728 THUMB_VARIANT, do_##ae, do_##te, 0 }
21730 /* ARM-only variants of all the above. */
21731 #define CE(mnem, op, nops, ops, ae) \
21732 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21734 #define C3(mnem, op, nops, ops, ae) \
21735 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21737 /* Thumb-only variants of TCE and TUE. */
21738 #define ToC(mnem, top, nops, ops, te) \
21739 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21742 #define ToU(mnem, top, nops, ops, te) \
21743 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
21746 /* T_MNEM_xyz enumerator variants of ToC. */
21747 #define toC(mnem, top, nops, ops, te) \
21748 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
21751 /* T_MNEM_xyz enumerator variants of ToU. */
21752 #define toU(mnem, top, nops, ops, te) \
21753 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
21756 /* Legacy mnemonics that always have conditional infix after the third
21758 #define CL(mnem, op, nops, ops, ae) \
21759 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21760 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21762 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
21763 #define cCE(mnem, op, nops, ops, ae) \
21764 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21766 /* mov instructions that are shared between coprocessor and MVE. */
21767 #define mcCE(mnem, op, nops, ops, ae) \
21768 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
21770 /* Legacy coprocessor instructions where conditional infix and conditional
21771 suffix are ambiguous. For consistency this includes all FPA instructions,
21772 not just the potentially ambiguous ones. */
21773 #define cCL(mnem, op, nops, ops, ae) \
21774 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21775 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21777 /* Coprocessor, takes either a suffix or a position-3 infix
21778 (for an FPA corner case). */
21779 #define C3E(mnem, op, nops, ops, ae) \
21780 { mnem, OPS##nops ops, OT_csuf_or_in3, \
21781 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21783 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
21784 { m1 #m2 m3, OPS##nops ops, \
21785 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
21786 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21788 #define CM(m1, m2, op, nops, ops, ae) \
21789 xCM_ (m1, , m2, op, nops, ops, ae), \
21790 xCM_ (m1, eq, m2, op, nops, ops, ae), \
21791 xCM_ (m1, ne, m2, op, nops, ops, ae), \
21792 xCM_ (m1, cs, m2, op, nops, ops, ae), \
21793 xCM_ (m1, hs, m2, op, nops, ops, ae), \
21794 xCM_ (m1, cc, m2, op, nops, ops, ae), \
21795 xCM_ (m1, ul, m2, op, nops, ops, ae), \
21796 xCM_ (m1, lo, m2, op, nops, ops, ae), \
21797 xCM_ (m1, mi, m2, op, nops, ops, ae), \
21798 xCM_ (m1, pl, m2, op, nops, ops, ae), \
21799 xCM_ (m1, vs, m2, op, nops, ops, ae), \
21800 xCM_ (m1, vc, m2, op, nops, ops, ae), \
21801 xCM_ (m1, hi, m2, op, nops, ops, ae), \
21802 xCM_ (m1, ls, m2, op, nops, ops, ae), \
21803 xCM_ (m1, ge, m2, op, nops, ops, ae), \
21804 xCM_ (m1, lt, m2, op, nops, ops, ae), \
21805 xCM_ (m1, gt, m2, op, nops, ops, ae), \
21806 xCM_ (m1, le, m2, op, nops, ops, ae), \
21807 xCM_ (m1, al, m2, op, nops, ops, ae)
21809 #define UE(mnem, op, nops, ops, ae) \
21810 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21812 #define UF(mnem, op, nops, ops, ae) \
21813 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21815 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
21816 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
21817 use the same encoding function for each. */
21818 #define NUF(mnem, op, nops, ops, enc) \
21819 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21820 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21822 /* Neon data processing, version which indirects through neon_enc_tab for
21823 the various overloaded versions of opcodes. */
21824 #define nUF(mnem, op, nops, ops, enc) \
21825 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21826 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
21828 /* Neon insn with conditional suffix for the ARM version, non-overloaded
21830 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21831 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
21832 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21834 #define NCE(mnem, op, nops, ops, enc) \
21835 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21837 #define NCEF(mnem, op, nops, ops, enc) \
21838 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21840 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
21841 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21842 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
21843 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
21845 #define nCE(mnem, op, nops, ops, enc) \
21846 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
21848 #define nCEF(mnem, op, nops, ops, enc) \
21849 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
21852 #define mCEF(mnem, op, nops, ops, enc) \
21853 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
21854 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21857 /* nCEF but for MVE predicated instructions. */
21858 #define mnCEF(mnem, op, nops, ops, enc) \
21859 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21861 /* nCE but for MVE predicated instructions. */
21862 #define mnCE(mnem, op, nops, ops, enc) \
21863 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21865 /* NUF but for potentially MVE predicated instructions. */
21866 #define MNUF(mnem, op, nops, ops, enc) \
21867 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
21868 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21870 /* nUF but for potentially MVE predicated instructions. */
21871 #define mnUF(mnem, op, nops, ops, enc) \
21872 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
21873 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
21875 /* ToC but for potentially MVE predicated instructions. */
21876 #define mToC(mnem, top, nops, ops, te) \
21877 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21880 /* NCE but for MVE predicated instructions. */
21881 #define MNCE(mnem, op, nops, ops, enc) \
21882 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
21884 /* NCEF but for MVE predicated instructions. */
21885 #define MNCEF(mnem, op, nops, ops, enc) \
21886 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
21889 static const struct asm_opcode insns
[] =
21891 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
21892 #define THUMB_VARIANT & arm_ext_v4t
21893 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21894 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21895 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21896 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21897 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
21898 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
21899 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
21900 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
21901 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21902 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21903 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21904 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21905 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21906 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
21907 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21908 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
21910 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
21911 for setting PSR flag bits. They are obsolete in V6 and do not
21912 have Thumb equivalents. */
21913 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21914 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21915 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
21916 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
21917 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
21918 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
21919 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21920 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21921 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
21923 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
21924 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
21925 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
21926 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
21928 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
21929 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
21930 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
21932 OP_ADDRGLDR
),ldst
, t_ldst
),
21933 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
21935 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21936 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21937 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21938 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21939 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21940 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21942 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
21943 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
21946 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
21947 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
21948 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
21949 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
21951 /* Thumb-compatibility pseudo ops. */
21952 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21953 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21954 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21955 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21956 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21957 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21958 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21959 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
21960 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
21961 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
21962 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
21963 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
21965 /* These may simplify to neg. */
21966 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
21967 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
21969 #undef THUMB_VARIANT
21970 #define THUMB_VARIANT & arm_ext_os
21972 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
21973 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
21975 #undef THUMB_VARIANT
21976 #define THUMB_VARIANT & arm_ext_v6
21978 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
21980 /* V1 instructions with no Thumb analogue prior to V6T2. */
21981 #undef THUMB_VARIANT
21982 #define THUMB_VARIANT & arm_ext_v6t2
21984 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21985 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
21986 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
21988 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21989 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21990 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
21991 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
21993 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21994 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21996 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21997 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
21999 /* V1 instructions with no Thumb analogue at all. */
22000 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
22001 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
22003 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22004 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22005 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22006 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22007 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22008 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22009 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22010 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22013 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22014 #undef THUMB_VARIANT
22015 #define THUMB_VARIANT & arm_ext_v4t
22017 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22018 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22020 #undef THUMB_VARIANT
22021 #define THUMB_VARIANT & arm_ext_v6t2
22023 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22024 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
22026 /* Generic coprocessor instructions. */
22027 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22028 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22029 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22030 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22031 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22032 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22033 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22036 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22038 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22039 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22042 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22043 #undef THUMB_VARIANT
22044 #define THUMB_VARIANT & arm_ext_msr
22046 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
22047 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
22050 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22051 #undef THUMB_VARIANT
22052 #define THUMB_VARIANT & arm_ext_v6t2
22054 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22055 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22056 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22057 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22058 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22059 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22060 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22061 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22064 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22065 #undef THUMB_VARIANT
22066 #define THUMB_VARIANT & arm_ext_v4t
22068 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22069 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22070 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22071 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22072 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22073 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22076 #define ARM_VARIANT & arm_ext_v4t_5
22078 /* ARM Architecture 4T. */
22079 /* Note: bx (and blx) are required on V5, even if the processor does
22080 not support Thumb. */
22081 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
22084 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22085 #undef THUMB_VARIANT
22086 #define THUMB_VARIANT & arm_ext_v5t
22088 /* Note: blx has 2 variants; the .value coded here is for
22089 BLX(2). Only this variant has conditional execution. */
22090 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
22091 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
22093 #undef THUMB_VARIANT
22094 #define THUMB_VARIANT & arm_ext_v6t2
22096 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
22097 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22098 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22099 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22100 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22101 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22102 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22103 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22106 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22107 #undef THUMB_VARIANT
22108 #define THUMB_VARIANT & arm_ext_v5exp
22110 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22111 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22112 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22113 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22115 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22116 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22118 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22119 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22120 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22121 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22123 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22124 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22125 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22126 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22128 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22129 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22131 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22132 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22133 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22134 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22137 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22138 #undef THUMB_VARIANT
22139 #define THUMB_VARIANT & arm_ext_v6t2
22141 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
22142 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
22144 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
22145 ADDRGLDRS
), ldrd
, t_ldstd
),
22147 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22148 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22151 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22153 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
22156 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22157 #undef THUMB_VARIANT
22158 #define THUMB_VARIANT & arm_ext_v6
22160 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22161 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22162 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22163 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22164 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22165 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22166 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22167 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22168 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22169 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
22171 #undef THUMB_VARIANT
22172 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22174 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
22175 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22177 #undef THUMB_VARIANT
22178 #define THUMB_VARIANT & arm_ext_v6t2
22180 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22181 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22183 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
22184 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
22186 /* ARM V6 not included in V7M. */
22187 #undef THUMB_VARIANT
22188 #define THUMB_VARIANT & arm_ext_v6_notm
22189 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22190 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22191 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
22192 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
22193 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22194 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22195 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
22196 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22197 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
22198 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22199 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22200 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22201 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22202 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22203 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
22204 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
22205 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22206 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22207 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
22209 /* ARM V6 not included in V7M (eg. integer SIMD). */
22210 #undef THUMB_VARIANT
22211 #define THUMB_VARIANT & arm_ext_v6_dsp
22212 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
22213 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
22214 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22215 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22216 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22217 /* Old name for QASX. */
22218 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22219 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22220 /* Old name for QSAX. */
22221 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22222 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22223 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22224 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22225 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22226 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22227 /* Old name for SASX. */
22228 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22229 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22230 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22231 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22232 /* Old name for SHASX. */
22233 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22234 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22235 /* Old name for SHSAX. */
22236 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22237 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22238 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22239 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22240 /* Old name for SSAX. */
22241 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22242 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22243 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22244 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22245 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22246 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22247 /* Old name for UASX. */
22248 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22249 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22250 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22251 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22252 /* Old name for UHASX. */
22253 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22254 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22255 /* Old name for UHSAX. */
22256 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22257 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22258 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22259 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22260 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22261 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22262 /* Old name for UQASX. */
22263 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22264 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22265 /* Old name for UQSAX. */
22266 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22267 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22268 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22269 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22270 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22271 /* Old name for USAX. */
22272 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22273 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22274 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22275 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22276 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22277 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22278 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22279 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22280 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22281 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22282 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22283 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22284 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22285 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22286 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22287 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22288 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22289 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22290 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22291 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22292 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22293 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22294 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22295 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22296 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22297 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22298 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22299 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22300 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22301 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
22302 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
22303 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22304 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22305 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
22308 #define ARM_VARIANT & arm_ext_v6k_v6t2
22309 #undef THUMB_VARIANT
22310 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22312 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
22313 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
22314 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
22315 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
22317 #undef THUMB_VARIANT
22318 #define THUMB_VARIANT & arm_ext_v6_notm
22319 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
22321 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
22322 RRnpcb
), strexd
, t_strexd
),
22324 #undef THUMB_VARIANT
22325 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22326 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
22328 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
22330 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22332 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22334 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
22337 #define ARM_VARIANT & arm_ext_sec
22338 #undef THUMB_VARIANT
22339 #define THUMB_VARIANT & arm_ext_sec
22341 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
22344 #define ARM_VARIANT & arm_ext_virt
22345 #undef THUMB_VARIANT
22346 #define THUMB_VARIANT & arm_ext_virt
22348 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
22349 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
22352 #define ARM_VARIANT & arm_ext_pan
22353 #undef THUMB_VARIANT
22354 #define THUMB_VARIANT & arm_ext_pan
22356 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
22359 #define ARM_VARIANT & arm_ext_v6t2
22360 #undef THUMB_VARIANT
22361 #define THUMB_VARIANT & arm_ext_v6t2
22363 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
22364 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
22365 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22366 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22368 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22369 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
22371 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22372 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22373 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22374 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22377 #define ARM_VARIANT & arm_ext_v3
22378 #undef THUMB_VARIANT
22379 #define THUMB_VARIANT & arm_ext_v6t2
22381 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
22382 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
22383 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
22386 #define ARM_VARIANT & arm_ext_v6t2
22387 #undef THUMB_VARIANT
22388 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22389 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22390 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22392 /* Thumb-only instructions. */
22394 #define ARM_VARIANT NULL
22395 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
22396 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
22398 /* ARM does not really have an IT instruction, so always allow it.
22399 The opcode is copied from Thumb in order to allow warnings in
22400 -mimplicit-it=[never | arm] modes. */
22402 #define ARM_VARIANT & arm_ext_v1
22403 #undef THUMB_VARIANT
22404 #define THUMB_VARIANT & arm_ext_v6t2
22406 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
22407 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
22408 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
22409 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
22410 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
22411 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
22412 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
22413 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
22414 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
22415 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
22416 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
22417 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
22418 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
22419 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
22420 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
22421 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
22422 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22423 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22425 /* Thumb2 only instructions. */
22427 #define ARM_VARIANT NULL
22429 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22430 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22431 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22432 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22433 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
22434 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
22436 /* Hardware division instructions. */
22438 #define ARM_VARIANT & arm_ext_adiv
22439 #undef THUMB_VARIANT
22440 #define THUMB_VARIANT & arm_ext_div
22442 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22443 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22445 /* ARM V6M/V7 instructions. */
22447 #define ARM_VARIANT & arm_ext_barrier
22448 #undef THUMB_VARIANT
22449 #define THUMB_VARIANT & arm_ext_barrier
22451 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
22452 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
22453 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
22455 /* ARM V7 instructions. */
22457 #define ARM_VARIANT & arm_ext_v7
22458 #undef THUMB_VARIANT
22459 #define THUMB_VARIANT & arm_ext_v7
22461 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
22462 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
22465 #define ARM_VARIANT & arm_ext_mp
22466 #undef THUMB_VARIANT
22467 #define THUMB_VARIANT & arm_ext_mp
22469 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
22471 /* AArchv8 instructions. */
22473 #define ARM_VARIANT & arm_ext_v8
22475 /* Instructions shared between armv8-a and armv8-m. */
22476 #undef THUMB_VARIANT
22477 #define THUMB_VARIANT & arm_ext_atomics
22479 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22480 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22481 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22482 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22483 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22484 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22485 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22486 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
22487 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22488 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22490 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22492 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22494 #undef THUMB_VARIANT
22495 #define THUMB_VARIANT & arm_ext_v8
22497 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
22498 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
22500 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
22503 /* Defined in V8 but is in undefined encoding space for earlier
22504 architectures. However earlier architectures are required to treat
22505 this instuction as a semihosting trap as well. Hence while not explicitly
22506 defined as such, it is in fact correct to define the instruction for all
22508 #undef THUMB_VARIANT
22509 #define THUMB_VARIANT & arm_ext_v1
22511 #define ARM_VARIANT & arm_ext_v1
22512 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
22514 /* ARMv8 T32 only. */
22516 #define ARM_VARIANT NULL
22517 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
22518 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
22519 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
22521 /* FP for ARMv8. */
22523 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
22524 #undef THUMB_VARIANT
22525 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
22527 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22528 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22529 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22530 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22531 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22532 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22533 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
22534 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
22535 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
22536 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
22537 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
22538 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
22539 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
22541 /* Crypto v1 extensions. */
22543 #define ARM_VARIANT & fpu_crypto_ext_armv8
22544 #undef THUMB_VARIANT
22545 #define THUMB_VARIANT & fpu_crypto_ext_armv8
22547 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
22548 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
22549 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
22550 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
22551 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
22552 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
22553 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
22554 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
22555 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
22556 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
22557 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
22558 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
22559 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
22560 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
22563 #define ARM_VARIANT & crc_ext_armv8
22564 #undef THUMB_VARIANT
22565 #define THUMB_VARIANT & crc_ext_armv8
22566 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
22567 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
22568 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
22569 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
22570 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
22571 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
22573 /* ARMv8.2 RAS extension. */
22575 #define ARM_VARIANT & arm_ext_ras
22576 #undef THUMB_VARIANT
22577 #define THUMB_VARIANT & arm_ext_ras
22578 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
22581 #define ARM_VARIANT & arm_ext_v8_3
22582 #undef THUMB_VARIANT
22583 #define THUMB_VARIANT & arm_ext_v8_3
22584 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
22585 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
22586 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
22589 #define ARM_VARIANT & fpu_neon_ext_dotprod
22590 #undef THUMB_VARIANT
22591 #define THUMB_VARIANT & fpu_neon_ext_dotprod
22592 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
22593 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
22596 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
22597 #undef THUMB_VARIANT
22598 #define THUMB_VARIANT NULL
22600 cCE("wfs", e200110
, 1, (RR
), rd
),
22601 cCE("rfs", e300110
, 1, (RR
), rd
),
22602 cCE("wfc", e400110
, 1, (RR
), rd
),
22603 cCE("rfc", e500110
, 1, (RR
), rd
),
22605 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22606 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22607 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22608 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22610 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22611 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22612 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22613 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22615 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
22616 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
22617 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
22618 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
22619 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
22620 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
22621 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
22622 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
22623 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
22624 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
22625 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
22626 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
22628 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
22629 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
22630 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
22631 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
22632 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
22633 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
22634 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
22635 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
22636 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
22637 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
22638 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
22639 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
22641 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
22642 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
22643 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
22644 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
22645 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
22646 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
22647 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
22648 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
22649 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
22650 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
22651 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
22652 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
22654 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
22655 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
22656 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
22657 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
22658 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
22659 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
22660 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
22661 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
22662 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
22663 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
22664 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
22665 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
22667 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
22668 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
22669 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
22670 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
22671 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
22672 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
22673 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
22674 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
22675 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
22676 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
22677 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
22678 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
22680 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
22681 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
22682 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
22683 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
22684 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
22685 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
22686 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
22687 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
22688 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
22689 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
22690 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
22691 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
22693 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
22694 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
22695 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
22696 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
22697 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
22698 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
22699 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
22700 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
22701 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
22702 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
22703 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
22704 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
22706 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
22707 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
22708 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
22709 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
22710 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
22711 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
22712 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
22713 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
22714 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
22715 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
22716 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
22717 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
22719 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
22720 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
22721 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
22722 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
22723 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
22724 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
22725 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
22726 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
22727 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
22728 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
22729 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
22730 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
22732 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
22733 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
22734 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
22735 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
22736 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
22737 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
22738 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
22739 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
22740 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
22741 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
22742 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
22743 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
22745 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
22746 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
22747 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
22748 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
22749 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
22750 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
22751 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
22752 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
22753 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
22754 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
22755 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
22756 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
22758 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
22759 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
22760 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
22761 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
22762 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
22763 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
22764 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
22765 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
22766 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
22767 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
22768 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
22769 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
22771 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
22772 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
22773 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
22774 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
22775 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
22776 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
22777 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
22778 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
22779 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
22780 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
22781 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
22782 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
22784 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
22785 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
22786 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
22787 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
22788 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
22789 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
22790 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
22791 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
22792 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
22793 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
22794 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
22795 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
22797 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
22798 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
22799 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
22800 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
22801 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
22802 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
22803 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
22804 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
22805 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
22806 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
22807 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
22808 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
22810 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
22811 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
22812 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
22813 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
22814 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
22815 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
22816 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
22817 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
22818 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
22819 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
22820 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
22821 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
22823 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22824 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22825 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22826 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22827 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22828 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22829 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22830 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22831 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22832 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22833 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22834 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22836 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22837 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22838 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22839 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22840 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22841 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22842 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22843 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22844 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22845 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22846 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22847 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22849 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22850 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22851 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22852 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22853 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22854 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22855 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22856 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22857 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22858 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22859 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22860 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22862 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22863 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22864 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22865 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22866 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22867 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22868 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22869 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22870 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22871 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22872 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22873 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22875 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22876 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22877 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22878 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22879 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22880 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22881 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22882 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22883 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22884 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22885 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22886 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22888 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22889 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22890 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22891 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22892 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22893 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22894 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22895 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22896 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22897 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22898 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22899 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22901 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22902 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22903 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22904 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22905 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22906 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22907 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22908 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22909 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22910 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22911 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22912 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22914 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22915 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22916 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22917 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22918 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22919 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22920 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22921 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22922 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22923 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22924 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22925 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22927 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22928 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22929 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22930 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22931 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22932 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22933 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22934 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22935 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22936 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22937 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22938 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22940 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22941 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22942 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22943 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22944 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22945 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22946 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22947 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22948 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22949 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22950 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22951 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22953 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22954 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22955 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22956 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22957 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22958 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22959 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22960 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22961 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22962 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22963 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22964 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22966 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22967 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22968 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22969 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22970 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22971 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22972 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22973 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22974 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22975 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22976 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22977 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22979 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22980 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22981 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22982 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22983 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22984 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22985 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22986 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22987 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22988 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22989 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22990 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
22992 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22993 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22994 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22995 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
22997 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
22998 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
22999 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
23000 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
23001 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
23002 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
23003 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
23004 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
23005 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
23006 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
23007 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
23008 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
23010 /* The implementation of the FIX instruction is broken on some
23011 assemblers, in that it accepts a precision specifier as well as a
23012 rounding specifier, despite the fact that this is meaningless.
23013 To be more compatible, we accept it as well, though of course it
23014 does not set any bits. */
23015 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
23016 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
23017 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
23018 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
23019 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
23020 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
23021 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
23022 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
23023 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
23024 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
23025 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
23026 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
23027 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
23029 /* Instructions that were new with the real FPA, call them V2. */
23031 #define ARM_VARIANT & fpu_fpa_ext_v2
23033 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23034 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23035 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23036 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23037 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23038 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23041 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23043 /* Moves and type conversions. */
23044 cCE("fmstat", ef1fa10
, 0, (), noargs
),
23045 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
23046 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
23047 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23048 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23049 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23050 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23051 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23052 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23053 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
23054 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
23056 /* Memory operations. */
23057 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23058 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23059 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23060 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23061 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23062 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23063 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23064 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23065 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23066 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23067 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23068 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23069 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23070 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23071 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23072 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23073 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23074 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23076 /* Monadic operations. */
23077 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23078 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23079 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23081 /* Dyadic operations. */
23082 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23083 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23084 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23085 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23086 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23087 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23088 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23089 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23090 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23093 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23094 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
23095 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23096 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
23098 /* Double precision load/store are still present on single precision
23099 implementations. */
23100 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23101 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23102 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23103 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23104 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23105 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23106 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23107 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23108 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23109 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23112 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23114 /* Moves and type conversions. */
23115 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23116 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23117 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23118 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23119 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23120 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23121 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23122 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23123 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23124 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23125 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23126 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23128 /* Monadic operations. */
23129 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23130 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23131 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23133 /* Dyadic operations. */
23134 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23135 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23136 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23137 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23138 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23139 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23140 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23141 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23142 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23145 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23146 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
23147 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23148 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
23150 /* Instructions which may belong to either the Neon or VFP instruction sets.
23151 Individual encoder functions perform additional architecture checks. */
23153 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23154 #undef THUMB_VARIANT
23155 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23157 /* These mnemonics are unique to VFP. */
23158 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
23159 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
23160 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23161 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23162 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23163 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
23164 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
23165 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
23167 /* Mnemonics shared by Neon and VFP. */
23168 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
23169 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23170 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23172 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23173 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23174 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23175 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23176 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23177 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23179 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
23180 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
23181 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
23182 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
23185 /* NOTE: All VMOV encoding is special-cased! */
23186 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
23188 #undef THUMB_VARIANT
23189 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23190 by different feature bits. Since we are setting the Thumb guard, we can
23191 require Thumb-1 which makes it a nop guard and set the right feature bit in
23192 do_vldr_vstr (). */
23193 #define THUMB_VARIANT & arm_ext_v4t
23194 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23195 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23198 #define ARM_VARIANT & arm_ext_fp16
23199 #undef THUMB_VARIANT
23200 #define THUMB_VARIANT & arm_ext_fp16
23201 /* New instructions added from v8.2, allowing the extraction and insertion of
23202 the upper 16 bits of a 32-bit vector register. */
23203 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
23204 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
23206 /* New backported fma/fms instructions optional in v8.2. */
23207 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
23208 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
23210 #undef THUMB_VARIANT
23211 #define THUMB_VARIANT & fpu_neon_ext_v1
23213 #define ARM_VARIANT & fpu_neon_ext_v1
23215 /* Data processing with three registers of the same length. */
23216 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23217 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
23218 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
23219 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23220 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23221 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23222 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23223 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23224 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23225 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23226 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23227 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23228 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23229 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23230 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23231 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23232 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23233 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23234 /* If not immediate, fall back to neon_dyadic_i64_su.
23235 shl_imm should accept I8 I16 I32 I64,
23236 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23237 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
23238 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
23239 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
23240 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
23241 /* Logic ops, types optional & ignored. */
23242 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23243 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23244 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23245 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23246 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23247 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23248 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
23249 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23250 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
23251 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23252 /* Bitfield ops, untyped. */
23253 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23254 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23255 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23256 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23257 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23258 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23259 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23260 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23261 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23262 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23263 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23264 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23265 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23266 back to neon_dyadic_if_su. */
23267 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23268 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23269 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23270 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23271 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23272 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23273 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23274 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23275 /* Comparison. Type I8 I16 I32 F32. */
23276 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
23277 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
23278 /* As above, D registers only. */
23279 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23280 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23281 /* Int and float variants, signedness unimportant. */
23282 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23283 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23284 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
23285 /* Add/sub take types I8 I16 I32 I64 F32. */
23286 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23287 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23288 /* vtst takes sizes 8, 16, 32. */
23289 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
23290 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
23291 /* VMUL takes I8 I16 I32 F32 P8. */
23292 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
23293 /* VQD{R}MULH takes S16 S32. */
23294 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23295 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23296 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23297 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23298 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23299 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23300 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23301 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23302 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23303 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23304 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23305 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23306 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23307 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23308 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23309 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23310 /* ARM v8.1 extension. */
23311 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23312 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23313 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23314 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23316 /* Two address, int/float. Types S8 S16 S32 F32. */
23317 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23318 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23320 /* Data processing with two registers and a shift amount. */
23321 /* Right shifts, and variants with rounding.
23322 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23323 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23324 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23325 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23326 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23327 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23328 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23329 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23330 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23331 /* Shift and insert. Sizes accepted 8 16 32 64. */
23332 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
23333 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
23334 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
23335 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
23336 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23337 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
23338 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
23339 /* Right shift immediate, saturating & narrowing, with rounding variants.
23340 Types accepted S16 S32 S64 U16 U32 U64. */
23341 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23342 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23343 /* As above, unsigned. Types accepted S16 S32 S64. */
23344 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23345 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23346 /* Right shift narrowing. Types accepted I16 I32 I64. */
23347 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23348 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23349 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23350 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
23351 /* CVT with optional immediate for fixed-point variant. */
23352 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
23354 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
23355 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
23357 /* Data processing, three registers of different lengths. */
23358 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23359 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
23360 /* If not scalar, fall back to neon_dyadic_long.
23361 Vector types as above, scalar types S16 S32 U16 U32. */
23362 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23363 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23364 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23365 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23366 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23367 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23368 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23369 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23370 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23371 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23372 /* Saturating doubling multiplies. Types S16 S32. */
23373 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23374 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23375 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23376 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23377 S16 S32 U16 U32. */
23378 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
23380 /* Extract. Size 8. */
23381 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
23382 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
23384 /* Two registers, miscellaneous. */
23385 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23386 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
23387 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
23388 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
23389 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
23390 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
23391 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
23392 /* Vector replicate. Sizes 8 16 32. */
23393 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
23394 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
23395 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23396 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
23397 /* VMOVN. Types I16 I32 I64. */
23398 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
23399 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
23400 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
23401 /* VQMOVUN. Types S16 S32 S64. */
23402 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
23403 /* VZIP / VUZP. Sizes 8 16 32. */
23404 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23405 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23406 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23407 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23408 /* VQABS / VQNEG. Types S8 S16 S32. */
23409 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23410 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23411 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23412 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23413 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
23414 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23415 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
23416 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23417 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
23418 /* Reciprocal estimates. Types U32 F16 F32. */
23419 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23420 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
23421 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23422 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
23423 /* VCLS. Types S8 S16 S32. */
23424 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
23425 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
23426 /* VCLZ. Types I8 I16 I32. */
23427 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
23428 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
23429 /* VCNT. Size 8. */
23430 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
23431 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
23432 /* Two address, untyped. */
23433 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
23434 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
23435 /* VTRN. Sizes 8 16 32. */
23436 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
23437 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
23439 /* Table lookup. Size 8. */
23440 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23441 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23443 #undef THUMB_VARIANT
23444 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
23446 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
23448 /* Neon element/structure load/store. */
23449 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23450 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23451 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23452 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23453 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23454 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23455 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23456 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23458 #undef THUMB_VARIANT
23459 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
23461 #define ARM_VARIANT & fpu_vfp_ext_v3xd
23462 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
23463 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23464 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23465 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23466 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23467 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23468 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23469 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23470 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23472 #undef THUMB_VARIANT
23473 #define THUMB_VARIANT & fpu_vfp_ext_v3
23475 #define ARM_VARIANT & fpu_vfp_ext_v3
23477 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
23478 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23479 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23480 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23481 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23482 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23483 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23484 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23485 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23488 #define ARM_VARIANT & fpu_vfp_ext_fma
23489 #undef THUMB_VARIANT
23490 #define THUMB_VARIANT & fpu_vfp_ext_fma
23491 /* Mnemonics shared by Neon and VFP. These are included in the
23492 VFP FMA variant; NEON and VFP FMA always includes the NEON
23493 FMA instructions. */
23494 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23495 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23496 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
23497 the v form should always be used. */
23498 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23499 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23500 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23501 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23502 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23503 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23505 #undef THUMB_VARIANT
23507 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
23509 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23510 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23511 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23512 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23513 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23514 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23515 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
23516 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
23519 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
23521 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
23522 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
23523 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
23524 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
23525 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
23526 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
23527 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
23528 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
23529 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
23530 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23531 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23532 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23533 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23534 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23535 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23536 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23537 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23538 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23539 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
23540 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
23541 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23542 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23543 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23544 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23545 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23546 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23547 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
23548 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
23549 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
23550 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
23551 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
23552 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
23553 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
23554 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
23555 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23556 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23557 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23558 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23559 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23560 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23561 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23562 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23563 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23564 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23565 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23566 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23567 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
23568 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23569 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23570 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23571 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23572 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23573 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23574 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23575 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23576 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23577 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23578 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23579 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23580 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23581 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23582 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23583 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23584 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23585 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23586 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23587 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23588 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23589 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23590 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23591 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23592 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23593 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23594 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23595 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23596 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23597 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23598 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23599 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23600 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23601 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23602 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23603 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23604 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23605 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23606 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23607 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23608 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23609 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
23610 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23611 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23612 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23613 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23614 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23615 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23616 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23617 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23618 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23619 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23620 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23621 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23622 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23623 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23624 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23625 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23626 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23627 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23628 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23629 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23630 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23631 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
23632 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23633 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23634 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23635 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23636 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23637 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23638 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23639 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23640 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23641 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23642 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23643 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23644 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23645 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23646 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23647 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23648 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23649 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23650 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23651 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23652 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23653 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23654 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23655 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23656 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23657 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23658 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23659 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23660 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23661 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23662 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23663 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23664 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23665 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23666 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23667 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23668 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23669 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23670 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23671 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23672 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23673 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23674 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23675 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23676 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23677 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23678 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23679 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23680 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23681 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23682 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
23685 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
23687 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
23688 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
23689 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
23690 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23691 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23692 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23693 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23694 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23695 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23696 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23697 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23698 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23699 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23700 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23701 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23702 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23703 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23704 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23705 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23706 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23707 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
23708 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23709 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23710 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23711 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23712 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23713 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23714 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23715 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23716 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23717 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23718 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23719 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23720 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23721 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23722 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23723 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23724 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23725 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23726 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23727 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23728 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23729 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23730 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23731 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23732 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23733 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23734 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23735 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23736 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23737 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23738 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23739 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23740 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23741 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23742 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23743 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23746 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
23748 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23749 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23750 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23751 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23752 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23753 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23754 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23755 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23756 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
23757 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
23758 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
23759 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
23760 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
23761 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
23762 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
23763 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
23764 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
23765 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
23766 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
23767 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
23768 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
23769 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
23770 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
23771 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
23772 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
23773 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
23774 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
23775 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
23776 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
23777 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
23778 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
23779 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
23780 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
23781 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
23782 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
23783 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
23784 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
23785 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
23786 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
23787 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
23788 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
23789 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
23790 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
23791 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
23792 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
23793 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
23794 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
23795 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
23796 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
23797 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
23798 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
23799 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
23800 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
23801 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
23802 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23803 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23804 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23805 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23806 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
23807 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
23808 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
23809 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
23810 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
23811 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
23812 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23813 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23814 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23815 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23816 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23817 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
23818 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23819 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
23820 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23821 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
23822 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23823 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
23825 /* ARMv8.5-A instructions. */
23827 #define ARM_VARIANT & arm_ext_sb
23828 #undef THUMB_VARIANT
23829 #define THUMB_VARIANT & arm_ext_sb
23830 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
23833 #define ARM_VARIANT & arm_ext_predres
23834 #undef THUMB_VARIANT
23835 #define THUMB_VARIANT & arm_ext_predres
23836 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
23837 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
23838 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
23840 /* ARMv8-M instructions. */
23842 #define ARM_VARIANT NULL
23843 #undef THUMB_VARIANT
23844 #define THUMB_VARIANT & arm_ext_v8m
23845 ToU("sg", e97fe97f
, 0, (), noargs
),
23846 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
23847 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
23848 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
23849 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
23850 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
23851 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
23853 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
23854 instructions behave as nop if no VFP is present. */
23855 #undef THUMB_VARIANT
23856 #define THUMB_VARIANT & arm_ext_v8m_main
23857 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
23858 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
23860 /* Armv8.1-M Mainline instructions. */
23861 #undef THUMB_VARIANT
23862 #define THUMB_VARIANT & arm_ext_v8_1m_main
23863 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
23864 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
23865 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23866 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
23867 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
23869 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
23870 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
23871 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
23873 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
23874 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
23876 #undef THUMB_VARIANT
23877 #define THUMB_VARIANT & mve_ext
23879 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23880 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23881 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23882 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23883 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23884 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23885 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23886 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23887 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23888 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23889 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23890 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23891 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23892 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23893 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
23895 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
23896 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
23897 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
23898 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
23899 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
23900 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
23901 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
23902 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
23903 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
23904 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
23905 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
23906 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
23907 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
23908 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
23909 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
23911 /* MVE and MVE FP only. */
23912 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
23913 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
23914 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23915 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23916 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23917 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23918 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23919 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23920 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23921 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23922 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23923 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
23925 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23926 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23927 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23928 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23929 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23930 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23931 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23932 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
23933 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23934 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23935 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23936 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
23937 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23938 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23939 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23940 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23941 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23942 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23943 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23944 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
23946 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
23947 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
23950 #define ARM_VARIANT & fpu_vfp_ext_v1
23951 #undef THUMB_VARIANT
23952 #define THUMB_VARIANT & arm_ext_v6t2
23954 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23957 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23959 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
23960 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
23961 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
23962 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23964 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
23965 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
23966 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
23968 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
23969 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
23971 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
23972 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
23974 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
23975 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
23978 #define ARM_VARIANT & fpu_vfp_ext_v2
23980 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
23981 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
23982 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
23983 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
23986 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23987 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
23988 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
23989 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
23990 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
23993 #define ARM_VARIANT & fpu_neon_ext_v1
23994 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
23995 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
23996 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
23997 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24000 #undef THUMB_VARIANT
24032 /* MD interface: bits in the object file. */
24034 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24035 for use in the a.out file, and stores them in the array pointed to by buf.
24036 This knows about the endian-ness of the target machine and does
24037 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24038 2 (short) and 4 (long) Floating numbers are put out as a series of
24039 LITTLENUMS (shorts, here at least). */
24042 md_number_to_chars (char * buf
, valueT val
, int n
)
24044 if (target_big_endian
)
24045 number_to_chars_bigendian (buf
, val
, n
);
24047 number_to_chars_littleendian (buf
, val
, n
);
24051 md_chars_to_number (char * buf
, int n
)
24054 unsigned char * where
= (unsigned char *) buf
;
24056 if (target_big_endian
)
24061 result
|= (*where
++ & 255);
24069 result
|= (where
[n
] & 255);
24076 /* MD interface: Sections. */
24078 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24079 that an rs_machine_dependent frag may reach. */
24082 arm_frag_max_var (fragS
*fragp
)
24084 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24085 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24087 Note that we generate relaxable instructions even for cases that don't
24088 really need it, like an immediate that's a trivial constant. So we're
24089 overestimating the instruction size for some of those cases. Rather
24090 than putting more intelligence here, it would probably be better to
24091 avoid generating a relaxation frag in the first place when it can be
24092 determined up front that a short instruction will suffice. */
24094 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
24098 /* Estimate the size of a frag before relaxing. Assume everything fits in
24102 md_estimate_size_before_relax (fragS
* fragp
,
24103 segT segtype ATTRIBUTE_UNUSED
)
24109 /* Convert a machine dependent frag. */
24112 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
24114 unsigned long insn
;
24115 unsigned long old_op
;
24123 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24125 old_op
= bfd_get_16(abfd
, buf
);
24126 if (fragp
->fr_symbol
)
24128 exp
.X_op
= O_symbol
;
24129 exp
.X_add_symbol
= fragp
->fr_symbol
;
24133 exp
.X_op
= O_constant
;
24135 exp
.X_add_number
= fragp
->fr_offset
;
24136 opcode
= fragp
->fr_subtype
;
24139 case T_MNEM_ldr_pc
:
24140 case T_MNEM_ldr_pc2
:
24141 case T_MNEM_ldr_sp
:
24142 case T_MNEM_str_sp
:
24149 if (fragp
->fr_var
== 4)
24151 insn
= THUMB_OP32 (opcode
);
24152 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
24154 insn
|= (old_op
& 0x700) << 4;
24158 insn
|= (old_op
& 7) << 12;
24159 insn
|= (old_op
& 0x38) << 13;
24161 insn
|= 0x00000c00;
24162 put_thumb32_insn (buf
, insn
);
24163 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
24167 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
24169 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
24172 if (fragp
->fr_var
== 4)
24174 insn
= THUMB_OP32 (opcode
);
24175 insn
|= (old_op
& 0xf0) << 4;
24176 put_thumb32_insn (buf
, insn
);
24177 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
24181 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24182 exp
.X_add_number
-= 4;
24190 if (fragp
->fr_var
== 4)
24192 int r0off
= (opcode
== T_MNEM_mov
24193 || opcode
== T_MNEM_movs
) ? 0 : 8;
24194 insn
= THUMB_OP32 (opcode
);
24195 insn
= (insn
& 0xe1ffffff) | 0x10000000;
24196 insn
|= (old_op
& 0x700) << r0off
;
24197 put_thumb32_insn (buf
, insn
);
24198 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24202 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
24207 if (fragp
->fr_var
== 4)
24209 insn
= THUMB_OP32(opcode
);
24210 put_thumb32_insn (buf
, insn
);
24211 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
24214 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
24218 if (fragp
->fr_var
== 4)
24220 insn
= THUMB_OP32(opcode
);
24221 insn
|= (old_op
& 0xf00) << 14;
24222 put_thumb32_insn (buf
, insn
);
24223 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
24226 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
24229 case T_MNEM_add_sp
:
24230 case T_MNEM_add_pc
:
24231 case T_MNEM_inc_sp
:
24232 case T_MNEM_dec_sp
:
24233 if (fragp
->fr_var
== 4)
24235 /* ??? Choose between add and addw. */
24236 insn
= THUMB_OP32 (opcode
);
24237 insn
|= (old_op
& 0xf0) << 4;
24238 put_thumb32_insn (buf
, insn
);
24239 if (opcode
== T_MNEM_add_pc
)
24240 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
24242 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24245 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24253 if (fragp
->fr_var
== 4)
24255 insn
= THUMB_OP32 (opcode
);
24256 insn
|= (old_op
& 0xf0) << 4;
24257 insn
|= (old_op
& 0xf) << 16;
24258 put_thumb32_insn (buf
, insn
);
24259 if (insn
& (1 << 20))
24260 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24262 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24265 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24271 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
24272 (enum bfd_reloc_code_real
) reloc_type
);
24273 fixp
->fx_file
= fragp
->fr_file
;
24274 fixp
->fx_line
= fragp
->fr_line
;
24275 fragp
->fr_fix
+= fragp
->fr_var
;
24277 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24278 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
24279 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
24280 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
24283 /* Return the size of a relaxable immediate operand instruction.
24284 SHIFT and SIZE specify the form of the allowable immediate. */
24286 relax_immediate (fragS
*fragp
, int size
, int shift
)
24292 /* ??? Should be able to do better than this. */
24293 if (fragp
->fr_symbol
)
24296 low
= (1 << shift
) - 1;
24297 mask
= (1 << (shift
+ size
)) - (1 << shift
);
24298 offset
= fragp
->fr_offset
;
24299 /* Force misaligned offsets to 32-bit variant. */
24302 if (offset
& ~mask
)
24307 /* Get the address of a symbol during relaxation. */
24309 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
24315 sym
= fragp
->fr_symbol
;
24316 sym_frag
= symbol_get_frag (sym
);
24317 know (S_GET_SEGMENT (sym
) != absolute_section
24318 || sym_frag
== &zero_address_frag
);
24319 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
24321 /* If frag has yet to be reached on this pass, assume it will
24322 move by STRETCH just as we did. If this is not so, it will
24323 be because some frag between grows, and that will force
24327 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
24331 /* Adjust stretch for any alignment frag. Note that if have
24332 been expanding the earlier code, the symbol may be
24333 defined in what appears to be an earlier frag. FIXME:
24334 This doesn't handle the fr_subtype field, which specifies
24335 a maximum number of bytes to skip when doing an
24337 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
24339 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
24342 stretch
= - ((- stretch
)
24343 & ~ ((1 << (int) f
->fr_offset
) - 1));
24345 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
24357 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
24360 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
24365 /* Assume worst case for symbols not known to be in the same section. */
24366 if (fragp
->fr_symbol
== NULL
24367 || !S_IS_DEFINED (fragp
->fr_symbol
)
24368 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24369 || S_IS_WEAK (fragp
->fr_symbol
))
24372 val
= relaxed_symbol_addr (fragp
, stretch
);
24373 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
24374 addr
= (addr
+ 4) & ~3;
24375 /* Force misaligned targets to 32-bit variant. */
24379 if (val
< 0 || val
> 1020)
24384 /* Return the size of a relaxable add/sub immediate instruction. */
24386 relax_addsub (fragS
*fragp
, asection
*sec
)
24391 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24392 op
= bfd_get_16(sec
->owner
, buf
);
24393 if ((op
& 0xf) == ((op
>> 4) & 0xf))
24394 return relax_immediate (fragp
, 8, 0);
24396 return relax_immediate (fragp
, 3, 0);
24399 /* Return TRUE iff the definition of symbol S could be pre-empted
24400 (overridden) at link or load time. */
24402 symbol_preemptible (symbolS
*s
)
24404 /* Weak symbols can always be pre-empted. */
24408 /* Non-global symbols cannot be pre-empted. */
24409 if (! S_IS_EXTERNAL (s
))
24413 /* In ELF, a global symbol can be marked protected, or private. In that
24414 case it can't be pre-empted (other definitions in the same link unit
24415 would violate the ODR). */
24416 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
24420 /* Other global symbols might be pre-empted. */
24424 /* Return the size of a relaxable branch instruction. BITS is the
24425 size of the offset field in the narrow instruction. */
24428 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
24434 /* Assume worst case for symbols not known to be in the same section. */
24435 if (!S_IS_DEFINED (fragp
->fr_symbol
)
24436 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24437 || S_IS_WEAK (fragp
->fr_symbol
))
24441 /* A branch to a function in ARM state will require interworking. */
24442 if (S_IS_DEFINED (fragp
->fr_symbol
)
24443 && ARM_IS_FUNC (fragp
->fr_symbol
))
24447 if (symbol_preemptible (fragp
->fr_symbol
))
24450 val
= relaxed_symbol_addr (fragp
, stretch
);
24451 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
24454 /* Offset is a signed value *2 */
24456 if (val
>= limit
|| val
< -limit
)
24462 /* Relax a machine dependent frag. This returns the amount by which
24463 the current size of the frag should change. */
24466 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
24471 oldsize
= fragp
->fr_var
;
24472 switch (fragp
->fr_subtype
)
24474 case T_MNEM_ldr_pc2
:
24475 newsize
= relax_adr (fragp
, sec
, stretch
);
24477 case T_MNEM_ldr_pc
:
24478 case T_MNEM_ldr_sp
:
24479 case T_MNEM_str_sp
:
24480 newsize
= relax_immediate (fragp
, 8, 2);
24484 newsize
= relax_immediate (fragp
, 5, 2);
24488 newsize
= relax_immediate (fragp
, 5, 1);
24492 newsize
= relax_immediate (fragp
, 5, 0);
24495 newsize
= relax_adr (fragp
, sec
, stretch
);
24501 newsize
= relax_immediate (fragp
, 8, 0);
24504 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
24507 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
24509 case T_MNEM_add_sp
:
24510 case T_MNEM_add_pc
:
24511 newsize
= relax_immediate (fragp
, 8, 2);
24513 case T_MNEM_inc_sp
:
24514 case T_MNEM_dec_sp
:
24515 newsize
= relax_immediate (fragp
, 7, 2);
24521 newsize
= relax_addsub (fragp
, sec
);
24527 fragp
->fr_var
= newsize
;
24528 /* Freeze wide instructions that are at or before the same location as
24529 in the previous pass. This avoids infinite loops.
24530 Don't freeze them unconditionally because targets may be artificially
24531 misaligned by the expansion of preceding frags. */
24532 if (stretch
<= 0 && newsize
> 2)
24534 md_convert_frag (sec
->owner
, sec
, fragp
);
24538 return newsize
- oldsize
;
24541 /* Round up a section size to the appropriate boundary. */
24544 md_section_align (segT segment ATTRIBUTE_UNUSED
,
24550 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
24551 of an rs_align_code fragment. */
24554 arm_handle_align (fragS
* fragP
)
24556 static unsigned char const arm_noop
[2][2][4] =
24559 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
24560 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
24563 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
24564 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
24567 static unsigned char const thumb_noop
[2][2][2] =
24570 {0xc0, 0x46}, /* LE */
24571 {0x46, 0xc0}, /* BE */
24574 {0x00, 0xbf}, /* LE */
24575 {0xbf, 0x00} /* BE */
24578 static unsigned char const wide_thumb_noop
[2][4] =
24579 { /* Wide Thumb-2 */
24580 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
24581 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
24584 unsigned bytes
, fix
, noop_size
;
24586 const unsigned char * noop
;
24587 const unsigned char *narrow_noop
= NULL
;
24592 if (fragP
->fr_type
!= rs_align_code
)
24595 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
24596 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
24599 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24600 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
24602 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
24604 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
24606 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24607 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
24609 narrow_noop
= thumb_noop
[1][target_big_endian
];
24610 noop
= wide_thumb_noop
[target_big_endian
];
24613 noop
= thumb_noop
[0][target_big_endian
];
24621 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24622 ? selected_cpu
: arm_arch_none
,
24624 [target_big_endian
];
24631 fragP
->fr_var
= noop_size
;
24633 if (bytes
& (noop_size
- 1))
24635 fix
= bytes
& (noop_size
- 1);
24637 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
24639 memset (p
, 0, fix
);
24646 if (bytes
& noop_size
)
24648 /* Insert a narrow noop. */
24649 memcpy (p
, narrow_noop
, noop_size
);
24651 bytes
-= noop_size
;
24655 /* Use wide noops for the remainder */
24659 while (bytes
>= noop_size
)
24661 memcpy (p
, noop
, noop_size
);
24663 bytes
-= noop_size
;
24667 fragP
->fr_fix
+= fix
;
24670 /* Called from md_do_align. Used to create an alignment
24671 frag in a code section. */
24674 arm_frag_align_code (int n
, int max
)
24678 /* We assume that there will never be a requirement
24679 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
24680 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24685 _("alignments greater than %d bytes not supported in .text sections."),
24686 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
24687 as_fatal ("%s", err_msg
);
24690 p
= frag_var (rs_align_code
,
24691 MAX_MEM_FOR_RS_ALIGN_CODE
,
24693 (relax_substateT
) max
,
24700 /* Perform target specific initialisation of a frag.
24701 Note - despite the name this initialisation is not done when the frag
24702 is created, but only when its type is assigned. A frag can be created
24703 and used a long time before its type is set, so beware of assuming that
24704 this initialisation is performed first. */
24708 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
24710 /* Record whether this frag is in an ARM or a THUMB area. */
24711 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24714 #else /* OBJ_ELF is defined. */
24716 arm_init_frag (fragS
* fragP
, int max_chars
)
24718 bfd_boolean frag_thumb_mode
;
24720 /* If the current ARM vs THUMB mode has not already
24721 been recorded into this frag then do so now. */
24722 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
24723 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24725 /* PR 21809: Do not set a mapping state for debug sections
24726 - it just confuses other tools. */
24727 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
24730 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
24732 /* Record a mapping symbol for alignment frags. We will delete this
24733 later if the alignment ends up empty. */
24734 switch (fragP
->fr_type
)
24737 case rs_align_test
:
24739 mapping_state_2 (MAP_DATA
, max_chars
);
24741 case rs_align_code
:
24742 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
24749 /* When we change sections we need to issue a new mapping symbol. */
24752 arm_elf_change_section (void)
24754 /* Link an unlinked unwind index table section to the .text section. */
24755 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
24756 && elf_linked_to_section (now_seg
) == NULL
)
24757 elf_linked_to_section (now_seg
) = text_section
;
24761 arm_elf_section_type (const char * str
, size_t len
)
24763 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
24764 return SHT_ARM_EXIDX
;
24769 /* Code to deal with unwinding tables. */
24771 static void add_unwind_adjustsp (offsetT
);
24773 /* Generate any deferred unwind frame offset. */
24776 flush_pending_unwind (void)
24780 offset
= unwind
.pending_offset
;
24781 unwind
.pending_offset
= 0;
24783 add_unwind_adjustsp (offset
);
24786 /* Add an opcode to this list for this function. Two-byte opcodes should
24787 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
24791 add_unwind_opcode (valueT op
, int length
)
24793 /* Add any deferred stack adjustment. */
24794 if (unwind
.pending_offset
)
24795 flush_pending_unwind ();
24797 unwind
.sp_restored
= 0;
24799 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
24801 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
24802 if (unwind
.opcodes
)
24803 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
24804 unwind
.opcode_alloc
);
24806 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
24811 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
24813 unwind
.opcode_count
++;
24817 /* Add unwind opcodes to adjust the stack pointer. */
24820 add_unwind_adjustsp (offsetT offset
)
24824 if (offset
> 0x200)
24826 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
24831 /* Long form: 0xb2, uleb128. */
24832 /* This might not fit in a word so add the individual bytes,
24833 remembering the list is built in reverse order. */
24834 o
= (valueT
) ((offset
- 0x204) >> 2);
24836 add_unwind_opcode (0, 1);
24838 /* Calculate the uleb128 encoding of the offset. */
24842 bytes
[n
] = o
& 0x7f;
24848 /* Add the insn. */
24850 add_unwind_opcode (bytes
[n
- 1], 1);
24851 add_unwind_opcode (0xb2, 1);
24853 else if (offset
> 0x100)
24855 /* Two short opcodes. */
24856 add_unwind_opcode (0x3f, 1);
24857 op
= (offset
- 0x104) >> 2;
24858 add_unwind_opcode (op
, 1);
24860 else if (offset
> 0)
24862 /* Short opcode. */
24863 op
= (offset
- 4) >> 2;
24864 add_unwind_opcode (op
, 1);
24866 else if (offset
< 0)
24869 while (offset
> 0x100)
24871 add_unwind_opcode (0x7f, 1);
24874 op
= ((offset
- 4) >> 2) | 0x40;
24875 add_unwind_opcode (op
, 1);
24879 /* Finish the list of unwind opcodes for this function. */
24882 finish_unwind_opcodes (void)
24886 if (unwind
.fp_used
)
24888 /* Adjust sp as necessary. */
24889 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
24890 flush_pending_unwind ();
24892 /* After restoring sp from the frame pointer. */
24893 op
= 0x90 | unwind
.fp_reg
;
24894 add_unwind_opcode (op
, 1);
24897 flush_pending_unwind ();
24901 /* Start an exception table entry. If idx is nonzero this is an index table
24905 start_unwind_section (const segT text_seg
, int idx
)
24907 const char * text_name
;
24908 const char * prefix
;
24909 const char * prefix_once
;
24910 const char * group_name
;
24918 prefix
= ELF_STRING_ARM_unwind
;
24919 prefix_once
= ELF_STRING_ARM_unwind_once
;
24920 type
= SHT_ARM_EXIDX
;
24924 prefix
= ELF_STRING_ARM_unwind_info
;
24925 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
24926 type
= SHT_PROGBITS
;
24929 text_name
= segment_name (text_seg
);
24930 if (streq (text_name
, ".text"))
24933 if (strncmp (text_name
, ".gnu.linkonce.t.",
24934 strlen (".gnu.linkonce.t.")) == 0)
24936 prefix
= prefix_once
;
24937 text_name
+= strlen (".gnu.linkonce.t.");
24940 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
24946 /* Handle COMDAT group. */
24947 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
24949 group_name
= elf_group_name (text_seg
);
24950 if (group_name
== NULL
)
24952 as_bad (_("Group section `%s' has no group signature"),
24953 segment_name (text_seg
));
24954 ignore_rest_of_line ();
24957 flags
|= SHF_GROUP
;
24961 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
24964 /* Set the section link for index tables. */
24966 elf_linked_to_section (now_seg
) = text_seg
;
24970 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
24971 personality routine data. Returns zero, or the index table value for
24972 an inline entry. */
24975 create_unwind_entry (int have_data
)
24980 /* The current word of data. */
24982 /* The number of bytes left in this word. */
24985 finish_unwind_opcodes ();
24987 /* Remember the current text section. */
24988 unwind
.saved_seg
= now_seg
;
24989 unwind
.saved_subseg
= now_subseg
;
24991 start_unwind_section (now_seg
, 0);
24993 if (unwind
.personality_routine
== NULL
)
24995 if (unwind
.personality_index
== -2)
24998 as_bad (_("handlerdata in cantunwind frame"));
24999 return 1; /* EXIDX_CANTUNWIND. */
25002 /* Use a default personality routine if none is specified. */
25003 if (unwind
.personality_index
== -1)
25005 if (unwind
.opcode_count
> 3)
25006 unwind
.personality_index
= 1;
25008 unwind
.personality_index
= 0;
25011 /* Space for the personality routine entry. */
25012 if (unwind
.personality_index
== 0)
25014 if (unwind
.opcode_count
> 3)
25015 as_bad (_("too many unwind opcodes for personality routine 0"));
25019 /* All the data is inline in the index table. */
25022 while (unwind
.opcode_count
> 0)
25024 unwind
.opcode_count
--;
25025 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25029 /* Pad with "finish" opcodes. */
25031 data
= (data
<< 8) | 0xb0;
25038 /* We get two opcodes "free" in the first word. */
25039 size
= unwind
.opcode_count
- 2;
25043 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25044 if (unwind
.personality_index
!= -1)
25046 as_bad (_("attempt to recreate an unwind entry"));
25050 /* An extra byte is required for the opcode count. */
25051 size
= unwind
.opcode_count
+ 1;
25054 size
= (size
+ 3) >> 2;
25056 as_bad (_("too many unwind opcodes"));
25058 frag_align (2, 0, 0);
25059 record_alignment (now_seg
, 2);
25060 unwind
.table_entry
= expr_build_dot ();
25062 /* Allocate the table entry. */
25063 ptr
= frag_more ((size
<< 2) + 4);
25064 /* PR 13449: Zero the table entries in case some of them are not used. */
25065 memset (ptr
, 0, (size
<< 2) + 4);
25066 where
= frag_now_fix () - ((size
<< 2) + 4);
25068 switch (unwind
.personality_index
)
25071 /* ??? Should this be a PLT generating relocation? */
25072 /* Custom personality routine. */
25073 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
25074 BFD_RELOC_ARM_PREL31
);
25079 /* Set the first byte to the number of additional words. */
25080 data
= size
> 0 ? size
- 1 : 0;
25084 /* ABI defined personality routines. */
25086 /* Three opcodes bytes are packed into the first word. */
25093 /* The size and first two opcode bytes go in the first word. */
25094 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
25099 /* Should never happen. */
25103 /* Pack the opcodes into words (MSB first), reversing the list at the same
25105 while (unwind
.opcode_count
> 0)
25109 md_number_to_chars (ptr
, data
, 4);
25114 unwind
.opcode_count
--;
25116 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25119 /* Finish off the last word. */
25122 /* Pad with "finish" opcodes. */
25124 data
= (data
<< 8) | 0xb0;
25126 md_number_to_chars (ptr
, data
, 4);
25131 /* Add an empty descriptor if there is no user-specified data. */
25132 ptr
= frag_more (4);
25133 md_number_to_chars (ptr
, 0, 4);
25140 /* Initialize the DWARF-2 unwind information for this procedure. */
25143 tc_arm_frame_initial_instructions (void)
25145 cfi_add_CFA_def_cfa (REG_SP
, 0);
25147 #endif /* OBJ_ELF */
25149 /* Convert REGNAME to a DWARF-2 register number. */
25152 tc_arm_regname_to_dw2regnum (char *regname
)
25154 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
25158 /* PR 16694: Allow VFP registers as well. */
25159 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
25163 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
25172 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
25176 exp
.X_op
= O_secrel
;
25177 exp
.X_add_symbol
= symbol
;
25178 exp
.X_add_number
= 0;
25179 emit_expr (&exp
, size
);
25183 /* MD interface: Symbol and relocation handling. */
25185 /* Return the address within the segment that a PC-relative fixup is
25186 relative to. For ARM, PC-relative fixups applied to instructions
25187 are generally relative to the location of the fixup plus 8 bytes.
25188 Thumb branches are offset by 4, and Thumb loads relative to PC
25189 require special handling. */
25192 md_pcrel_from_section (fixS
* fixP
, segT seg
)
25194 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25196 /* If this is pc-relative and we are going to emit a relocation
25197 then we just want to put out any pipeline compensation that the linker
25198 will need. Otherwise we want to use the calculated base.
25199 For WinCE we skip the bias for externals as well, since this
25200 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25202 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25203 || (arm_force_relocation (fixP
)
25205 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
25211 switch (fixP
->fx_r_type
)
25213 /* PC relative addressing on the Thumb is slightly odd as the
25214 bottom two bits of the PC are forced to zero for the
25215 calculation. This happens *after* application of the
25216 pipeline offset. However, Thumb adrl already adjusts for
25217 this, so we need not do it again. */
25218 case BFD_RELOC_ARM_THUMB_ADD
:
25221 case BFD_RELOC_ARM_THUMB_OFFSET
:
25222 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25223 case BFD_RELOC_ARM_T32_ADD_PC12
:
25224 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
25225 return (base
+ 4) & ~3;
25227 /* Thumb branches are simply offset by +4. */
25228 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25229 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25230 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25231 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25232 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25233 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25234 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25235 case BFD_RELOC_ARM_THUMB_BF17
:
25236 case BFD_RELOC_ARM_THUMB_BF19
:
25237 case BFD_RELOC_ARM_THUMB_BF13
:
25238 case BFD_RELOC_ARM_THUMB_LOOP12
:
25241 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25243 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25244 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25245 && ARM_IS_FUNC (fixP
->fx_addsy
)
25246 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25247 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25250 /* BLX is like branches above, but forces the low two bits of PC to
25252 case BFD_RELOC_THUMB_PCREL_BLX
:
25254 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25255 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25256 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25257 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25258 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25259 return (base
+ 4) & ~3;
25261 /* ARM mode branches are offset by +8. However, the Windows CE
25262 loader expects the relocation not to take this into account. */
25263 case BFD_RELOC_ARM_PCREL_BLX
:
25265 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25266 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25267 && ARM_IS_FUNC (fixP
->fx_addsy
)
25268 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25269 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25272 case BFD_RELOC_ARM_PCREL_CALL
:
25274 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25275 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25276 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25277 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25278 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25281 case BFD_RELOC_ARM_PCREL_BRANCH
:
25282 case BFD_RELOC_ARM_PCREL_JUMP
:
25283 case BFD_RELOC_ARM_PLT32
:
25285 /* When handling fixups immediately, because we have already
25286 discovered the value of a symbol, or the address of the frag involved
25287 we must account for the offset by +8, as the OS loader will never see the reloc.
25288 see fixup_segment() in write.c
25289 The S_IS_EXTERNAL test handles the case of global symbols.
25290 Those need the calculated base, not just the pipe compensation the linker will need. */
25292 && fixP
->fx_addsy
!= NULL
25293 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25294 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
25302 /* ARM mode loads relative to PC are also offset by +8. Unlike
25303 branches, the Windows CE loader *does* expect the relocation
25304 to take this into account. */
25305 case BFD_RELOC_ARM_OFFSET_IMM
:
25306 case BFD_RELOC_ARM_OFFSET_IMM8
:
25307 case BFD_RELOC_ARM_HWLITERAL
:
25308 case BFD_RELOC_ARM_LITERAL
:
25309 case BFD_RELOC_ARM_CP_OFF_IMM
:
25313 /* Other PC-relative relocations are un-offset. */
25319 static bfd_boolean flag_warn_syms
= TRUE
;
25322 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
25324 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25325 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25326 does mean that the resulting code might be very confusing to the reader.
25327 Also this warning can be triggered if the user omits an operand before
25328 an immediate address, eg:
25332 GAS treats this as an assignment of the value of the symbol foo to a
25333 symbol LDR, and so (without this code) it will not issue any kind of
25334 warning or error message.
25336 Note - ARM instructions are case-insensitive but the strings in the hash
25337 table are all stored in lower case, so we must first ensure that name is
25339 if (flag_warn_syms
&& arm_ops_hsh
)
25341 char * nbuf
= strdup (name
);
25344 for (p
= nbuf
; *p
; p
++)
25346 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
25348 static struct hash_control
* already_warned
= NULL
;
25350 if (already_warned
== NULL
)
25351 already_warned
= hash_new ();
25352 /* Only warn about the symbol once. To keep the code
25353 simple we let hash_insert do the lookup for us. */
25354 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
25355 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
25364 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
25365 Otherwise we have no need to default values of symbols. */
25368 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
25371 if (name
[0] == '_' && name
[1] == 'G'
25372 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
25376 if (symbol_find (name
))
25377 as_bad (_("GOT already in the symbol table"));
25379 GOT_symbol
= symbol_new (name
, undefined_section
,
25380 (valueT
) 0, & zero_address_frag
);
25390 /* Subroutine of md_apply_fix. Check to see if an immediate can be
25391 computed as two separate immediate values, added together. We
25392 already know that this value cannot be computed by just one ARM
25395 static unsigned int
25396 validate_immediate_twopart (unsigned int val
,
25397 unsigned int * highpart
)
25402 for (i
= 0; i
< 32; i
+= 2)
25403 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
25409 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
25411 else if (a
& 0xff0000)
25413 if (a
& 0xff000000)
25415 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
25419 gas_assert (a
& 0xff000000);
25420 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
25423 return (a
& 0xff) | (i
<< 7);
25430 validate_offset_imm (unsigned int val
, int hwse
)
25432 if ((hwse
&& val
> 255) || val
> 4095)
25437 /* Subroutine of md_apply_fix. Do those data_ops which can take a
25438 negative immediate constant by altering the instruction. A bit of
25443 by inverting the second operand, and
25446 by negating the second operand. */
25449 negate_data_op (unsigned long * instruction
,
25450 unsigned long value
)
25453 unsigned long negated
, inverted
;
25455 negated
= encode_arm_immediate (-value
);
25456 inverted
= encode_arm_immediate (~value
);
25458 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
25461 /* First negates. */
25462 case OPCODE_SUB
: /* ADD <-> SUB */
25463 new_inst
= OPCODE_ADD
;
25468 new_inst
= OPCODE_SUB
;
25472 case OPCODE_CMP
: /* CMP <-> CMN */
25473 new_inst
= OPCODE_CMN
;
25478 new_inst
= OPCODE_CMP
;
25482 /* Now Inverted ops. */
25483 case OPCODE_MOV
: /* MOV <-> MVN */
25484 new_inst
= OPCODE_MVN
;
25489 new_inst
= OPCODE_MOV
;
25493 case OPCODE_AND
: /* AND <-> BIC */
25494 new_inst
= OPCODE_BIC
;
25499 new_inst
= OPCODE_AND
;
25503 case OPCODE_ADC
: /* ADC <-> SBC */
25504 new_inst
= OPCODE_SBC
;
25509 new_inst
= OPCODE_ADC
;
25513 /* We cannot do anything. */
25518 if (value
== (unsigned) FAIL
)
25521 *instruction
&= OPCODE_MASK
;
25522 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
25526 /* Like negate_data_op, but for Thumb-2. */
25528 static unsigned int
25529 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
25533 unsigned int negated
, inverted
;
25535 negated
= encode_thumb32_immediate (-value
);
25536 inverted
= encode_thumb32_immediate (~value
);
25538 rd
= (*instruction
>> 8) & 0xf;
25539 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
25542 /* ADD <-> SUB. Includes CMP <-> CMN. */
25543 case T2_OPCODE_SUB
:
25544 new_inst
= T2_OPCODE_ADD
;
25548 case T2_OPCODE_ADD
:
25549 new_inst
= T2_OPCODE_SUB
;
25553 /* ORR <-> ORN. Includes MOV <-> MVN. */
25554 case T2_OPCODE_ORR
:
25555 new_inst
= T2_OPCODE_ORN
;
25559 case T2_OPCODE_ORN
:
25560 new_inst
= T2_OPCODE_ORR
;
25564 /* AND <-> BIC. TST has no inverted equivalent. */
25565 case T2_OPCODE_AND
:
25566 new_inst
= T2_OPCODE_BIC
;
25573 case T2_OPCODE_BIC
:
25574 new_inst
= T2_OPCODE_AND
;
25579 case T2_OPCODE_ADC
:
25580 new_inst
= T2_OPCODE_SBC
;
25584 case T2_OPCODE_SBC
:
25585 new_inst
= T2_OPCODE_ADC
;
25589 /* We cannot do anything. */
25594 if (value
== (unsigned int)FAIL
)
25597 *instruction
&= T2_OPCODE_MASK
;
25598 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
25602 /* Read a 32-bit thumb instruction from buf. */
25604 static unsigned long
25605 get_thumb32_insn (char * buf
)
25607 unsigned long insn
;
25608 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
25609 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25614 /* We usually want to set the low bit on the address of thumb function
25615 symbols. In particular .word foo - . should have the low bit set.
25616 Generic code tries to fold the difference of two symbols to
25617 a constant. Prevent this and force a relocation when the first symbols
25618 is a thumb function. */
25621 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
25623 if (op
== O_subtract
25624 && l
->X_op
== O_symbol
25625 && r
->X_op
== O_symbol
25626 && THUMB_IS_FUNC (l
->X_add_symbol
))
25628 l
->X_op
= O_subtract
;
25629 l
->X_op_symbol
= r
->X_add_symbol
;
25630 l
->X_add_number
-= r
->X_add_number
;
25634 /* Process as normal. */
25638 /* Encode Thumb2 unconditional branches and calls. The encoding
25639 for the 2 are identical for the immediate values. */
25642 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
25644 #define T2I1I2MASK ((1 << 13) | (1 << 11))
25647 addressT S
, I1
, I2
, lo
, hi
;
25649 S
= (value
>> 24) & 0x01;
25650 I1
= (value
>> 23) & 0x01;
25651 I2
= (value
>> 22) & 0x01;
25652 hi
= (value
>> 12) & 0x3ff;
25653 lo
= (value
>> 1) & 0x7ff;
25654 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25655 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25656 newval
|= (S
<< 10) | hi
;
25657 newval2
&= ~T2I1I2MASK
;
25658 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
25659 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25660 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25664 md_apply_fix (fixS
* fixP
,
25668 offsetT value
= * valP
;
25670 unsigned int newimm
;
25671 unsigned long temp
;
25673 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
25675 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
25677 /* Note whether this will delete the relocation. */
25679 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
25682 /* On a 64-bit host, silently truncate 'value' to 32 bits for
25683 consistency with the behaviour on 32-bit hosts. Remember value
25685 value
&= 0xffffffff;
25686 value
^= 0x80000000;
25687 value
-= 0x80000000;
25690 fixP
->fx_addnumber
= value
;
25692 /* Same treatment for fixP->fx_offset. */
25693 fixP
->fx_offset
&= 0xffffffff;
25694 fixP
->fx_offset
^= 0x80000000;
25695 fixP
->fx_offset
-= 0x80000000;
25697 switch (fixP
->fx_r_type
)
25699 case BFD_RELOC_NONE
:
25700 /* This will need to go in the object file. */
25704 case BFD_RELOC_ARM_IMMEDIATE
:
25705 /* We claim that this fixup has been processed here,
25706 even if in fact we generate an error because we do
25707 not have a reloc for it, so tc_gen_reloc will reject it. */
25710 if (fixP
->fx_addsy
)
25712 const char *msg
= 0;
25714 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25715 msg
= _("undefined symbol %s used as an immediate value");
25716 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25717 msg
= _("symbol %s is in a different section");
25718 else if (S_IS_WEAK (fixP
->fx_addsy
))
25719 msg
= _("symbol %s is weak and may be overridden later");
25723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25724 msg
, S_GET_NAME (fixP
->fx_addsy
));
25729 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25731 /* If the offset is negative, we should use encoding A2 for ADR. */
25732 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
25733 newimm
= negate_data_op (&temp
, value
);
25736 newimm
= encode_arm_immediate (value
);
25738 /* If the instruction will fail, see if we can fix things up by
25739 changing the opcode. */
25740 if (newimm
== (unsigned int) FAIL
)
25741 newimm
= negate_data_op (&temp
, value
);
25742 /* MOV accepts both ARM modified immediate (A1 encoding) and
25743 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
25744 When disassembling, MOV is preferred when there is no encoding
25746 if (newimm
== (unsigned int) FAIL
25747 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
25748 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
25749 && !((temp
>> SBIT_SHIFT
) & 0x1)
25750 && value
>= 0 && value
<= 0xffff)
25752 /* Clear bits[23:20] to change encoding from A1 to A2. */
25753 temp
&= 0xff0fffff;
25754 /* Encoding high 4bits imm. Code below will encode the remaining
25756 temp
|= (value
& 0x0000f000) << 4;
25757 newimm
= value
& 0x00000fff;
25761 if (newimm
== (unsigned int) FAIL
)
25763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25764 _("invalid constant (%lx) after fixup"),
25765 (unsigned long) value
);
25769 newimm
|= (temp
& 0xfffff000);
25770 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25773 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
25775 unsigned int highpart
= 0;
25776 unsigned int newinsn
= 0xe1a00000; /* nop. */
25778 if (fixP
->fx_addsy
)
25780 const char *msg
= 0;
25782 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25783 msg
= _("undefined symbol %s used as an immediate value");
25784 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25785 msg
= _("symbol %s is in a different section");
25786 else if (S_IS_WEAK (fixP
->fx_addsy
))
25787 msg
= _("symbol %s is weak and may be overridden later");
25791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25792 msg
, S_GET_NAME (fixP
->fx_addsy
));
25797 newimm
= encode_arm_immediate (value
);
25798 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25800 /* If the instruction will fail, see if we can fix things up by
25801 changing the opcode. */
25802 if (newimm
== (unsigned int) FAIL
25803 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
25805 /* No ? OK - try using two ADD instructions to generate
25807 newimm
= validate_immediate_twopart (value
, & highpart
);
25809 /* Yes - then make sure that the second instruction is
25811 if (newimm
!= (unsigned int) FAIL
)
25813 /* Still No ? Try using a negated value. */
25814 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
25815 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
25816 /* Otherwise - give up. */
25819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25820 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
25825 /* Replace the first operand in the 2nd instruction (which
25826 is the PC) with the destination register. We have
25827 already added in the PC in the first instruction and we
25828 do not want to do it again. */
25829 newinsn
&= ~ 0xf0000;
25830 newinsn
|= ((newinsn
& 0x0f000) << 4);
25833 newimm
|= (temp
& 0xfffff000);
25834 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
25836 highpart
|= (newinsn
& 0xfffff000);
25837 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
25841 case BFD_RELOC_ARM_OFFSET_IMM
:
25842 if (!fixP
->fx_done
&& seg
->use_rela_p
)
25844 /* Fall through. */
25846 case BFD_RELOC_ARM_LITERAL
:
25852 if (validate_offset_imm (value
, 0) == FAIL
)
25854 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
25855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25856 _("invalid literal constant: pool needs to be closer"));
25858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25859 _("bad immediate value for offset (%ld)"),
25864 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25866 newval
&= 0xfffff000;
25869 newval
&= 0xff7ff000;
25870 newval
|= value
| (sign
? INDEX_UP
: 0);
25872 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25875 case BFD_RELOC_ARM_OFFSET_IMM8
:
25876 case BFD_RELOC_ARM_HWLITERAL
:
25882 if (validate_offset_imm (value
, 1) == FAIL
)
25884 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
25885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25886 _("invalid literal constant: pool needs to be closer"));
25888 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25889 _("bad immediate value for 8-bit offset (%ld)"),
25894 newval
= md_chars_to_number (buf
, INSN_SIZE
);
25896 newval
&= 0xfffff0f0;
25899 newval
&= 0xff7ff0f0;
25900 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
25902 md_number_to_chars (buf
, newval
, INSN_SIZE
);
25905 case BFD_RELOC_ARM_T32_OFFSET_U8
:
25906 if (value
< 0 || value
> 1020 || value
% 4 != 0)
25907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25908 _("bad immediate value for offset (%ld)"), (long) value
);
25911 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
25913 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
25916 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25917 /* This is a complicated relocation used for all varieties of Thumb32
25918 load/store instruction with immediate offset:
25920 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
25921 *4, optional writeback(W)
25922 (doubleword load/store)
25924 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
25925 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
25926 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
25927 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
25928 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
25930 Uppercase letters indicate bits that are already encoded at
25931 this point. Lowercase letters are our problem. For the
25932 second block of instructions, the secondary opcode nybble
25933 (bits 8..11) is present, and bit 23 is zero, even if this is
25934 a PC-relative operation. */
25935 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25937 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
25939 if ((newval
& 0xf0000000) == 0xe0000000)
25941 /* Doubleword load/store: 8-bit offset, scaled by 4. */
25943 newval
|= (1 << 23);
25946 if (value
% 4 != 0)
25948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25949 _("offset not a multiple of 4"));
25955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25956 _("offset out of range"));
25961 else if ((newval
& 0x000f0000) == 0x000f0000)
25963 /* PC-relative, 12-bit offset. */
25965 newval
|= (1 << 23);
25970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25971 _("offset out of range"));
25976 else if ((newval
& 0x00000100) == 0x00000100)
25978 /* Writeback: 8-bit, +/- offset. */
25980 newval
|= (1 << 9);
25985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25986 _("offset out of range"));
25991 else if ((newval
& 0x00000f00) == 0x00000e00)
25993 /* T-instruction: positive 8-bit offset. */
25994 if (value
< 0 || value
> 0xff)
25996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25997 _("offset out of range"));
26005 /* Positive 12-bit or negative 8-bit offset. */
26009 newval
|= (1 << 23);
26019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26020 _("offset out of range"));
26027 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
26028 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
26031 case BFD_RELOC_ARM_SHIFT_IMM
:
26032 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26033 if (((unsigned long) value
) > 32
26035 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
26037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26038 _("shift expression is too large"));
26043 /* Shifts of zero must be done as lsl. */
26045 else if (value
== 32)
26047 newval
&= 0xfffff07f;
26048 newval
|= (value
& 0x1f) << 7;
26049 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26052 case BFD_RELOC_ARM_T32_IMMEDIATE
:
26053 case BFD_RELOC_ARM_T32_ADD_IMM
:
26054 case BFD_RELOC_ARM_T32_IMM12
:
26055 case BFD_RELOC_ARM_T32_ADD_PC12
:
26056 /* We claim that this fixup has been processed here,
26057 even if in fact we generate an error because we do
26058 not have a reloc for it, so tc_gen_reloc will reject it. */
26062 && ! S_IS_DEFINED (fixP
->fx_addsy
))
26064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26065 _("undefined symbol %s used as an immediate value"),
26066 S_GET_NAME (fixP
->fx_addsy
));
26070 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26072 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
26075 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26076 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26077 Thumb2 modified immediate encoding (T2). */
26078 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
26079 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26081 newimm
= encode_thumb32_immediate (value
);
26082 if (newimm
== (unsigned int) FAIL
)
26083 newimm
= thumb32_negate_data_op (&newval
, value
);
26085 if (newimm
== (unsigned int) FAIL
)
26087 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
26089 /* Turn add/sum into addw/subw. */
26090 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26091 newval
= (newval
& 0xfeffffff) | 0x02000000;
26092 /* No flat 12-bit imm encoding for addsw/subsw. */
26093 if ((newval
& 0x00100000) == 0)
26095 /* 12 bit immediate for addw/subw. */
26099 newval
^= 0x00a00000;
26102 newimm
= (unsigned int) FAIL
;
26109 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26110 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26111 disassembling, MOV is preferred when there is no encoding
26113 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
26114 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26115 but with the Rn field [19:16] set to 1111. */
26116 && (((newval
>> 16) & 0xf) == 0xf)
26117 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
26118 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
26119 && value
>= 0 && value
<= 0xffff)
26121 /* Toggle bit[25] to change encoding from T2 to T3. */
26123 /* Clear bits[19:16]. */
26124 newval
&= 0xfff0ffff;
26125 /* Encoding high 4bits imm. Code below will encode the
26126 remaining low 12bits. */
26127 newval
|= (value
& 0x0000f000) << 4;
26128 newimm
= value
& 0x00000fff;
26133 if (newimm
== (unsigned int)FAIL
)
26135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26136 _("invalid constant (%lx) after fixup"),
26137 (unsigned long) value
);
26141 newval
|= (newimm
& 0x800) << 15;
26142 newval
|= (newimm
& 0x700) << 4;
26143 newval
|= (newimm
& 0x0ff);
26145 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
26146 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
26149 case BFD_RELOC_ARM_SMC
:
26150 if (((unsigned long) value
) > 0xffff)
26151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26152 _("invalid smc expression"));
26153 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26154 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26155 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26158 case BFD_RELOC_ARM_HVC
:
26159 if (((unsigned long) value
) > 0xffff)
26160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26161 _("invalid hvc expression"));
26162 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26163 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26164 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26167 case BFD_RELOC_ARM_SWI
:
26168 if (fixP
->tc_fix_data
!= 0)
26170 if (((unsigned long) value
) > 0xff)
26171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26172 _("invalid swi expression"));
26173 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26175 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26179 if (((unsigned long) value
) > 0x00ffffff)
26180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26181 _("invalid swi expression"));
26182 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26184 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26188 case BFD_RELOC_ARM_MULTI
:
26189 if (((unsigned long) value
) > 0xffff)
26190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26191 _("invalid expression in load/store multiple"));
26192 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
26193 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26197 case BFD_RELOC_ARM_PCREL_CALL
:
26199 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26201 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26202 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26203 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26204 /* Flip the bl to blx. This is a simple flip
26205 bit here because we generate PCREL_CALL for
26206 unconditional bls. */
26208 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26209 newval
= newval
| 0x10000000;
26210 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26216 goto arm_branch_common
;
26218 case BFD_RELOC_ARM_PCREL_JUMP
:
26219 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26221 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26222 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26223 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26225 /* This would map to a bl<cond>, b<cond>,
26226 b<always> to a Thumb function. We
26227 need to force a relocation for this particular
26229 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26232 /* Fall through. */
26234 case BFD_RELOC_ARM_PLT32
:
26236 case BFD_RELOC_ARM_PCREL_BRANCH
:
26238 goto arm_branch_common
;
26240 case BFD_RELOC_ARM_PCREL_BLX
:
26243 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26245 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26246 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26247 && ARM_IS_FUNC (fixP
->fx_addsy
))
26249 /* Flip the blx to a bl and warn. */
26250 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26251 newval
= 0xeb000000;
26252 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26253 _("blx to '%s' an ARM ISA state function changed to bl"),
26255 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26261 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
26262 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
26266 /* We are going to store value (shifted right by two) in the
26267 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26268 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26272 _("misaligned branch destination"));
26273 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
26274 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
26275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26277 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26279 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26280 newval
|= (value
>> 2) & 0x00ffffff;
26281 /* Set the H bit on BLX instructions. */
26285 newval
|= 0x01000000;
26287 newval
&= ~0x01000000;
26289 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26293 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
26294 /* CBZ can only branch forward. */
26296 /* Attempts to use CBZ to branch to the next instruction
26297 (which, strictly speaking, are prohibited) will be turned into
26300 FIXME: It may be better to remove the instruction completely and
26301 perform relaxation. */
26304 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26305 newval
= 0xbf00; /* NOP encoding T1 */
26306 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26313 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26316 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
26317 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26322 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
26323 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
26324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26326 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26328 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26329 newval
|= (value
& 0x1ff) >> 1;
26330 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26334 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
26335 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
26336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26338 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26340 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26341 newval
|= (value
& 0xfff) >> 1;
26342 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26346 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26348 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26349 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26350 && ARM_IS_FUNC (fixP
->fx_addsy
)
26351 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26353 /* Force a relocation for a branch 20 bits wide. */
26356 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
26357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26358 _("conditional branch out of range"));
26360 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26363 addressT S
, J1
, J2
, lo
, hi
;
26365 S
= (value
& 0x00100000) >> 20;
26366 J2
= (value
& 0x00080000) >> 19;
26367 J1
= (value
& 0x00040000) >> 18;
26368 hi
= (value
& 0x0003f000) >> 12;
26369 lo
= (value
& 0x00000ffe) >> 1;
26371 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26372 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26373 newval
|= (S
<< 10) | hi
;
26374 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
26375 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26376 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26380 case BFD_RELOC_THUMB_PCREL_BLX
:
26381 /* If there is a blx from a thumb state function to
26382 another thumb function flip this to a bl and warn
26386 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26387 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26388 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26390 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26391 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26392 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
26394 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26395 newval
= newval
| 0x1000;
26396 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26397 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26402 goto thumb_bl_common
;
26404 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26405 /* A bl from Thumb state ISA to an internal ARM state function
26406 is converted to a blx. */
26408 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26409 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26410 && ARM_IS_FUNC (fixP
->fx_addsy
)
26411 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26413 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26414 newval
= newval
& ~0x1000;
26415 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26416 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
26422 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26423 /* For a BLX instruction, make sure that the relocation is rounded up
26424 to a word boundary. This follows the semantics of the instruction
26425 which specifies that bit 1 of the target address will come from bit
26426 1 of the base address. */
26427 value
= (value
+ 3) & ~ 3;
26430 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
26431 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26432 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26435 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
26437 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
26438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26439 else if ((value
& ~0x1ffffff)
26440 && ((value
& ~0x1ffffff) != ~0x1ffffff))
26441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26442 _("Thumb2 branch out of range"));
26445 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26446 encode_thumb2_b_bl_offset (buf
, value
);
26450 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26451 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
26452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26455 encode_thumb2_b_bl_offset (buf
, value
);
26460 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26465 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26466 md_number_to_chars (buf
, value
, 2);
26470 case BFD_RELOC_ARM_TLS_CALL
:
26471 case BFD_RELOC_ARM_THM_TLS_CALL
:
26472 case BFD_RELOC_ARM_TLS_DESCSEQ
:
26473 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
26474 case BFD_RELOC_ARM_TLS_GOTDESC
:
26475 case BFD_RELOC_ARM_TLS_GD32
:
26476 case BFD_RELOC_ARM_TLS_LE32
:
26477 case BFD_RELOC_ARM_TLS_IE32
:
26478 case BFD_RELOC_ARM_TLS_LDM32
:
26479 case BFD_RELOC_ARM_TLS_LDO32
:
26480 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26483 /* Same handling as above, but with the arm_fdpic guard. */
26484 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
26485 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
26486 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
26489 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26494 _("Relocation supported only in FDPIC mode"));
26498 case BFD_RELOC_ARM_GOT32
:
26499 case BFD_RELOC_ARM_GOTOFF
:
26502 case BFD_RELOC_ARM_GOT_PREL
:
26503 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26504 md_number_to_chars (buf
, value
, 4);
26507 case BFD_RELOC_ARM_TARGET2
:
26508 /* TARGET2 is not partial-inplace, so we need to write the
26509 addend here for REL targets, because it won't be written out
26510 during reloc processing later. */
26511 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26512 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
26515 /* Relocations for FDPIC. */
26516 case BFD_RELOC_ARM_GOTFUNCDESC
:
26517 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
26518 case BFD_RELOC_ARM_FUNCDESC
:
26521 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26522 md_number_to_chars (buf
, 0, 4);
26526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26527 _("Relocation supported only in FDPIC mode"));
26532 case BFD_RELOC_RVA
:
26534 case BFD_RELOC_ARM_TARGET1
:
26535 case BFD_RELOC_ARM_ROSEGREL32
:
26536 case BFD_RELOC_ARM_SBREL32
:
26537 case BFD_RELOC_32_PCREL
:
26539 case BFD_RELOC_32_SECREL
:
26541 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26543 /* For WinCE we only do this for pcrel fixups. */
26544 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
26546 md_number_to_chars (buf
, value
, 4);
26550 case BFD_RELOC_ARM_PREL31
:
26551 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26553 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
26554 if ((value
^ (value
>> 1)) & 0x40000000)
26556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26557 _("rel31 relocation overflow"));
26559 newval
|= value
& 0x7fffffff;
26560 md_number_to_chars (buf
, newval
, 4);
26565 case BFD_RELOC_ARM_CP_OFF_IMM
:
26566 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26567 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
26568 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
26569 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26571 newval
= get_thumb32_insn (buf
);
26572 if ((newval
& 0x0f200f00) == 0x0d000900)
26574 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
26575 has permitted values that are multiples of 2, in the range 0
26577 if (value
< -510 || value
> 510 || (value
& 1))
26578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26579 _("co-processor offset out of range"));
26581 else if ((newval
& 0xfe001f80) == 0xec000f80)
26583 if (value
< -511 || value
> 512 || (value
& 3))
26584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26585 _("co-processor offset out of range"));
26587 else if (value
< -1023 || value
> 1023 || (value
& 3))
26588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26589 _("co-processor offset out of range"));
26594 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26595 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26596 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26598 newval
= get_thumb32_insn (buf
);
26601 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26602 newval
&= 0xffffff80;
26604 newval
&= 0xffffff00;
26608 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26609 newval
&= 0xff7fff80;
26611 newval
&= 0xff7fff00;
26612 if ((newval
& 0x0f200f00) == 0x0d000900)
26614 /* This is a fp16 vstr/vldr.
26616 It requires the immediate offset in the instruction is shifted
26617 left by 1 to be a half-word offset.
26619 Here, left shift by 1 first, and later right shift by 2
26620 should get the right offset. */
26623 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
26625 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26626 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26627 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26629 put_thumb32_insn (buf
, newval
);
26632 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
26633 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
26634 if (value
< -255 || value
> 255)
26635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26636 _("co-processor offset out of range"));
26638 goto cp_off_common
;
26640 case BFD_RELOC_ARM_THUMB_OFFSET
:
26641 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26642 /* Exactly what ranges, and where the offset is inserted depends
26643 on the type of instruction, we can establish this from the
26645 switch (newval
>> 12)
26647 case 4: /* PC load. */
26648 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
26649 forced to zero for these loads; md_pcrel_from has already
26650 compensated for this. */
26652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26653 _("invalid offset, target not word aligned (0x%08lX)"),
26654 (((unsigned long) fixP
->fx_frag
->fr_address
26655 + (unsigned long) fixP
->fx_where
) & ~3)
26656 + (unsigned long) value
);
26658 if (value
& ~0x3fc)
26659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26660 _("invalid offset, value too big (0x%08lX)"),
26663 newval
|= value
>> 2;
26666 case 9: /* SP load/store. */
26667 if (value
& ~0x3fc)
26668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26669 _("invalid offset, value too big (0x%08lX)"),
26671 newval
|= value
>> 2;
26674 case 6: /* Word load/store. */
26676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26677 _("invalid offset, value too big (0x%08lX)"),
26679 newval
|= value
<< 4; /* 6 - 2. */
26682 case 7: /* Byte load/store. */
26684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26685 _("invalid offset, value too big (0x%08lX)"),
26687 newval
|= value
<< 6;
26690 case 8: /* Halfword load/store. */
26692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26693 _("invalid offset, value too big (0x%08lX)"),
26695 newval
|= value
<< 5; /* 6 - 1. */
26699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26700 "Unable to process relocation for thumb opcode: %lx",
26701 (unsigned long) newval
);
26704 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26707 case BFD_RELOC_ARM_THUMB_ADD
:
26708 /* This is a complicated relocation, since we use it for all of
26709 the following immediate relocations:
26713 9bit ADD/SUB SP word-aligned
26714 10bit ADD PC/SP word-aligned
26716 The type of instruction being processed is encoded in the
26723 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26725 int rd
= (newval
>> 4) & 0xf;
26726 int rs
= newval
& 0xf;
26727 int subtract
= !!(newval
& 0x8000);
26729 /* Check for HI regs, only very restricted cases allowed:
26730 Adjusting SP, and using PC or SP to get an address. */
26731 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
26732 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
26733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26734 _("invalid Hi register with immediate"));
26736 /* If value is negative, choose the opposite instruction. */
26740 subtract
= !subtract
;
26742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26743 _("immediate value out of range"));
26748 if (value
& ~0x1fc)
26749 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26750 _("invalid immediate for stack address calculation"));
26751 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
26752 newval
|= value
>> 2;
26754 else if (rs
== REG_PC
|| rs
== REG_SP
)
26756 /* PR gas/18541. If the addition is for a defined symbol
26757 within range of an ADR instruction then accept it. */
26760 && fixP
->fx_addsy
!= NULL
)
26764 if (! S_IS_DEFINED (fixP
->fx_addsy
)
26765 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
26766 || S_IS_WEAK (fixP
->fx_addsy
))
26768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26769 _("address calculation needs a strongly defined nearby symbol"));
26773 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26775 /* Round up to the next 4-byte boundary. */
26780 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
26784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26785 _("symbol too far away"));
26795 if (subtract
|| value
& ~0x3fc)
26796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26797 _("invalid immediate for address calculation (value = 0x%08lX)"),
26798 (unsigned long) (subtract
? - value
: value
));
26799 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
26801 newval
|= value
>> 2;
26806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26807 _("immediate value out of range"));
26808 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
26809 newval
|= (rd
<< 8) | value
;
26814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26815 _("immediate value out of range"));
26816 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
26817 newval
|= rd
| (rs
<< 3) | (value
<< 6);
26820 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26823 case BFD_RELOC_ARM_THUMB_IMM
:
26824 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26825 if (value
< 0 || value
> 255)
26826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26827 _("invalid immediate: %ld is out of range"),
26830 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26833 case BFD_RELOC_ARM_THUMB_SHIFT
:
26834 /* 5bit shift value (0..32). LSL cannot take 32. */
26835 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
26836 temp
= newval
& 0xf800;
26837 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
26838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26839 _("invalid shift value: %ld"), (long) value
);
26840 /* Shifts of zero must be encoded as LSL. */
26842 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
26843 /* Shifts of 32 are encoded as zero. */
26844 else if (value
== 32)
26846 newval
|= value
<< 6;
26847 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26850 case BFD_RELOC_VTABLE_INHERIT
:
26851 case BFD_RELOC_VTABLE_ENTRY
:
26855 case BFD_RELOC_ARM_MOVW
:
26856 case BFD_RELOC_ARM_MOVT
:
26857 case BFD_RELOC_ARM_THUMB_MOVW
:
26858 case BFD_RELOC_ARM_THUMB_MOVT
:
26859 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26861 /* REL format relocations are limited to a 16-bit addend. */
26862 if (!fixP
->fx_done
)
26864 if (value
< -0x8000 || value
> 0x7fff)
26865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26866 _("offset out of range"));
26868 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
26869 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26874 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
26875 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
26877 newval
= get_thumb32_insn (buf
);
26878 newval
&= 0xfbf08f00;
26879 newval
|= (value
& 0xf000) << 4;
26880 newval
|= (value
& 0x0800) << 15;
26881 newval
|= (value
& 0x0700) << 4;
26882 newval
|= (value
& 0x00ff);
26883 put_thumb32_insn (buf
, newval
);
26887 newval
= md_chars_to_number (buf
, 4);
26888 newval
&= 0xfff0f000;
26889 newval
|= value
& 0x0fff;
26890 newval
|= (value
& 0xf000) << 4;
26891 md_number_to_chars (buf
, newval
, 4);
26896 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
26897 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
26898 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
26899 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
26900 gas_assert (!fixP
->fx_done
);
26903 bfd_boolean is_mov
;
26904 bfd_vma encoded_addend
= value
;
26906 /* Check that addend can be encoded in instruction. */
26907 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
26908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26909 _("the offset 0x%08lX is not representable"),
26910 (unsigned long) encoded_addend
);
26912 /* Extract the instruction. */
26913 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
26914 is_mov
= (insn
& 0xf800) == 0x2000;
26919 if (!seg
->use_rela_p
)
26920 insn
|= encoded_addend
;
26926 /* Extract the instruction. */
26927 /* Encoding is the following
26932 /* The following conditions must be true :
26937 rd
= (insn
>> 4) & 0xf;
26939 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
26940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26941 _("Unable to process relocation for thumb opcode: %lx"),
26942 (unsigned long) insn
);
26944 /* Encode as ADD immediate8 thumb 1 code. */
26945 insn
= 0x3000 | (rd
<< 8);
26947 /* Place the encoded addend into the first 8 bits of the
26949 if (!seg
->use_rela_p
)
26950 insn
|= encoded_addend
;
26953 /* Update the instruction. */
26954 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
26958 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
26959 case BFD_RELOC_ARM_ALU_PC_G0
:
26960 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
26961 case BFD_RELOC_ARM_ALU_PC_G1
:
26962 case BFD_RELOC_ARM_ALU_PC_G2
:
26963 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
26964 case BFD_RELOC_ARM_ALU_SB_G0
:
26965 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
26966 case BFD_RELOC_ARM_ALU_SB_G1
:
26967 case BFD_RELOC_ARM_ALU_SB_G2
:
26968 gas_assert (!fixP
->fx_done
);
26969 if (!seg
->use_rela_p
)
26972 bfd_vma encoded_addend
;
26973 bfd_vma addend_abs
= llabs (value
);
26975 /* Check that the absolute value of the addend can be
26976 expressed as an 8-bit constant plus a rotation. */
26977 encoded_addend
= encode_arm_immediate (addend_abs
);
26978 if (encoded_addend
== (unsigned int) FAIL
)
26979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26980 _("the offset 0x%08lX is not representable"),
26981 (unsigned long) addend_abs
);
26983 /* Extract the instruction. */
26984 insn
= md_chars_to_number (buf
, INSN_SIZE
);
26986 /* If the addend is positive, use an ADD instruction.
26987 Otherwise use a SUB. Take care not to destroy the S bit. */
26988 insn
&= 0xff1fffff;
26994 /* Place the encoded addend into the first 12 bits of the
26996 insn
&= 0xfffff000;
26997 insn
|= encoded_addend
;
26999 /* Update the instruction. */
27000 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27004 case BFD_RELOC_ARM_LDR_PC_G0
:
27005 case BFD_RELOC_ARM_LDR_PC_G1
:
27006 case BFD_RELOC_ARM_LDR_PC_G2
:
27007 case BFD_RELOC_ARM_LDR_SB_G0
:
27008 case BFD_RELOC_ARM_LDR_SB_G1
:
27009 case BFD_RELOC_ARM_LDR_SB_G2
:
27010 gas_assert (!fixP
->fx_done
);
27011 if (!seg
->use_rela_p
)
27014 bfd_vma addend_abs
= llabs (value
);
27016 /* Check that the absolute value of the addend can be
27017 encoded in 12 bits. */
27018 if (addend_abs
>= 0x1000)
27019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27020 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27021 (unsigned long) addend_abs
);
27023 /* Extract the instruction. */
27024 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27026 /* If the addend is negative, clear bit 23 of the instruction.
27027 Otherwise set it. */
27029 insn
&= ~(1 << 23);
27033 /* Place the absolute value of the addend into the first 12 bits
27034 of the instruction. */
27035 insn
&= 0xfffff000;
27036 insn
|= addend_abs
;
27038 /* Update the instruction. */
27039 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27043 case BFD_RELOC_ARM_LDRS_PC_G0
:
27044 case BFD_RELOC_ARM_LDRS_PC_G1
:
27045 case BFD_RELOC_ARM_LDRS_PC_G2
:
27046 case BFD_RELOC_ARM_LDRS_SB_G0
:
27047 case BFD_RELOC_ARM_LDRS_SB_G1
:
27048 case BFD_RELOC_ARM_LDRS_SB_G2
:
27049 gas_assert (!fixP
->fx_done
);
27050 if (!seg
->use_rela_p
)
27053 bfd_vma addend_abs
= llabs (value
);
27055 /* Check that the absolute value of the addend can be
27056 encoded in 8 bits. */
27057 if (addend_abs
>= 0x100)
27058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27059 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27060 (unsigned long) addend_abs
);
27062 /* Extract the instruction. */
27063 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27065 /* If the addend is negative, clear bit 23 of the instruction.
27066 Otherwise set it. */
27068 insn
&= ~(1 << 23);
27072 /* Place the first four bits of the absolute value of the addend
27073 into the first 4 bits of the instruction, and the remaining
27074 four into bits 8 .. 11. */
27075 insn
&= 0xfffff0f0;
27076 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
27078 /* Update the instruction. */
27079 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27083 case BFD_RELOC_ARM_LDC_PC_G0
:
27084 case BFD_RELOC_ARM_LDC_PC_G1
:
27085 case BFD_RELOC_ARM_LDC_PC_G2
:
27086 case BFD_RELOC_ARM_LDC_SB_G0
:
27087 case BFD_RELOC_ARM_LDC_SB_G1
:
27088 case BFD_RELOC_ARM_LDC_SB_G2
:
27089 gas_assert (!fixP
->fx_done
);
27090 if (!seg
->use_rela_p
)
27093 bfd_vma addend_abs
= llabs (value
);
27095 /* Check that the absolute value of the addend is a multiple of
27096 four and, when divided by four, fits in 8 bits. */
27097 if (addend_abs
& 0x3)
27098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27099 _("bad offset 0x%08lX (must be word-aligned)"),
27100 (unsigned long) addend_abs
);
27102 if ((addend_abs
>> 2) > 0xff)
27103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27104 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27105 (unsigned long) addend_abs
);
27107 /* Extract the instruction. */
27108 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27110 /* If the addend is negative, clear bit 23 of the instruction.
27111 Otherwise set it. */
27113 insn
&= ~(1 << 23);
27117 /* Place the addend (divided by four) into the first eight
27118 bits of the instruction. */
27119 insn
&= 0xfffffff0;
27120 insn
|= addend_abs
>> 2;
27122 /* Update the instruction. */
27123 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27127 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27129 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27130 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27131 && ARM_IS_FUNC (fixP
->fx_addsy
)
27132 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27134 /* Force a relocation for a branch 5 bits wide. */
27137 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
27138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27141 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27143 addressT boff
= value
>> 1;
27145 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27146 newval
|= (boff
<< 7);
27147 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27151 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27153 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27154 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27155 && ARM_IS_FUNC (fixP
->fx_addsy
)
27156 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27160 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
27161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27162 _("branch out of range"));
27164 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27166 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27168 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
27169 addressT diff
= value
- boff
;
27173 newval
|= 1 << 1; /* T bit. */
27175 else if (diff
!= 2)
27177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27178 _("out of range label-relative fixup value"));
27180 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27184 case BFD_RELOC_ARM_THUMB_BF17
:
27186 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27187 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27188 && ARM_IS_FUNC (fixP
->fx_addsy
)
27189 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27191 /* Force a relocation for a branch 17 bits wide. */
27195 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
27196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27199 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27202 addressT immA
, immB
, immC
;
27204 immA
= (value
& 0x0001f000) >> 12;
27205 immB
= (value
& 0x00000ffc) >> 2;
27206 immC
= (value
& 0x00000002) >> 1;
27208 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27209 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27211 newval2
|= (immC
<< 11) | (immB
<< 1);
27212 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27213 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27217 case BFD_RELOC_ARM_THUMB_BF19
:
27219 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27220 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27221 && ARM_IS_FUNC (fixP
->fx_addsy
)
27222 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27224 /* Force a relocation for a branch 19 bits wide. */
27228 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
27229 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27235 addressT immA
, immB
, immC
;
27237 immA
= (value
& 0x0007f000) >> 12;
27238 immB
= (value
& 0x00000ffc) >> 2;
27239 immC
= (value
& 0x00000002) >> 1;
27241 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27242 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27244 newval2
|= (immC
<< 11) | (immB
<< 1);
27245 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27246 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27250 case BFD_RELOC_ARM_THUMB_BF13
:
27252 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27253 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27254 && ARM_IS_FUNC (fixP
->fx_addsy
)
27255 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27257 /* Force a relocation for a branch 13 bits wide. */
27261 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
27262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27265 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27268 addressT immA
, immB
, immC
;
27270 immA
= (value
& 0x00001000) >> 12;
27271 immB
= (value
& 0x00000ffc) >> 2;
27272 immC
= (value
& 0x00000002) >> 1;
27274 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27275 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27277 newval2
|= (immC
<< 11) | (immB
<< 1);
27278 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27279 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27283 case BFD_RELOC_ARM_THUMB_LOOP12
:
27285 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27286 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27287 && ARM_IS_FUNC (fixP
->fx_addsy
)
27288 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27290 /* Force a relocation for a branch 12 bits wide. */
27294 bfd_vma insn
= get_thumb32_insn (buf
);
27295 /* le lr, <label> or le <label> */
27296 if (((insn
& 0xffffffff) == 0xf00fc001)
27297 || ((insn
& 0xffffffff) == 0xf02fc001))
27300 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
27301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27303 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27305 addressT imml
, immh
;
27307 immh
= (value
& 0x00000ffc) >> 2;
27308 imml
= (value
& 0x00000002) >> 1;
27310 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27311 newval
|= (imml
<< 11) | (immh
<< 1);
27312 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
27316 case BFD_RELOC_ARM_V4BX
:
27317 /* This will need to go in the object file. */
27321 case BFD_RELOC_UNUSED
:
27323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27324 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
27328 /* Translate internal representation of relocation info to BFD target
27332 tc_gen_reloc (asection
*section
, fixS
*fixp
)
27335 bfd_reloc_code_real_type code
;
27337 reloc
= XNEW (arelent
);
27339 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
27340 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
27341 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
27343 if (fixp
->fx_pcrel
)
27345 if (section
->use_rela_p
)
27346 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
27348 fixp
->fx_offset
= reloc
->address
;
27350 reloc
->addend
= fixp
->fx_offset
;
27352 switch (fixp
->fx_r_type
)
27355 if (fixp
->fx_pcrel
)
27357 code
= BFD_RELOC_8_PCREL
;
27360 /* Fall through. */
27363 if (fixp
->fx_pcrel
)
27365 code
= BFD_RELOC_16_PCREL
;
27368 /* Fall through. */
27371 if (fixp
->fx_pcrel
)
27373 code
= BFD_RELOC_32_PCREL
;
27376 /* Fall through. */
27378 case BFD_RELOC_ARM_MOVW
:
27379 if (fixp
->fx_pcrel
)
27381 code
= BFD_RELOC_ARM_MOVW_PCREL
;
27384 /* Fall through. */
27386 case BFD_RELOC_ARM_MOVT
:
27387 if (fixp
->fx_pcrel
)
27389 code
= BFD_RELOC_ARM_MOVT_PCREL
;
27392 /* Fall through. */
27394 case BFD_RELOC_ARM_THUMB_MOVW
:
27395 if (fixp
->fx_pcrel
)
27397 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
27400 /* Fall through. */
27402 case BFD_RELOC_ARM_THUMB_MOVT
:
27403 if (fixp
->fx_pcrel
)
27405 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
27408 /* Fall through. */
27410 case BFD_RELOC_NONE
:
27411 case BFD_RELOC_ARM_PCREL_BRANCH
:
27412 case BFD_RELOC_ARM_PCREL_BLX
:
27413 case BFD_RELOC_RVA
:
27414 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27415 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27416 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27417 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27418 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27419 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27420 case BFD_RELOC_VTABLE_ENTRY
:
27421 case BFD_RELOC_VTABLE_INHERIT
:
27423 case BFD_RELOC_32_SECREL
:
27425 code
= fixp
->fx_r_type
;
27428 case BFD_RELOC_THUMB_PCREL_BLX
:
27430 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27431 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27434 code
= BFD_RELOC_THUMB_PCREL_BLX
;
27437 case BFD_RELOC_ARM_LITERAL
:
27438 case BFD_RELOC_ARM_HWLITERAL
:
27439 /* If this is called then the a literal has
27440 been referenced across a section boundary. */
27441 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27442 _("literal referenced across section boundary"));
27446 case BFD_RELOC_ARM_TLS_CALL
:
27447 case BFD_RELOC_ARM_THM_TLS_CALL
:
27448 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27449 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27450 case BFD_RELOC_ARM_GOT32
:
27451 case BFD_RELOC_ARM_GOTOFF
:
27452 case BFD_RELOC_ARM_GOT_PREL
:
27453 case BFD_RELOC_ARM_PLT32
:
27454 case BFD_RELOC_ARM_TARGET1
:
27455 case BFD_RELOC_ARM_ROSEGREL32
:
27456 case BFD_RELOC_ARM_SBREL32
:
27457 case BFD_RELOC_ARM_PREL31
:
27458 case BFD_RELOC_ARM_TARGET2
:
27459 case BFD_RELOC_ARM_TLS_LDO32
:
27460 case BFD_RELOC_ARM_PCREL_CALL
:
27461 case BFD_RELOC_ARM_PCREL_JUMP
:
27462 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27463 case BFD_RELOC_ARM_ALU_PC_G0
:
27464 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27465 case BFD_RELOC_ARM_ALU_PC_G1
:
27466 case BFD_RELOC_ARM_ALU_PC_G2
:
27467 case BFD_RELOC_ARM_LDR_PC_G0
:
27468 case BFD_RELOC_ARM_LDR_PC_G1
:
27469 case BFD_RELOC_ARM_LDR_PC_G2
:
27470 case BFD_RELOC_ARM_LDRS_PC_G0
:
27471 case BFD_RELOC_ARM_LDRS_PC_G1
:
27472 case BFD_RELOC_ARM_LDRS_PC_G2
:
27473 case BFD_RELOC_ARM_LDC_PC_G0
:
27474 case BFD_RELOC_ARM_LDC_PC_G1
:
27475 case BFD_RELOC_ARM_LDC_PC_G2
:
27476 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27477 case BFD_RELOC_ARM_ALU_SB_G0
:
27478 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27479 case BFD_RELOC_ARM_ALU_SB_G1
:
27480 case BFD_RELOC_ARM_ALU_SB_G2
:
27481 case BFD_RELOC_ARM_LDR_SB_G0
:
27482 case BFD_RELOC_ARM_LDR_SB_G1
:
27483 case BFD_RELOC_ARM_LDR_SB_G2
:
27484 case BFD_RELOC_ARM_LDRS_SB_G0
:
27485 case BFD_RELOC_ARM_LDRS_SB_G1
:
27486 case BFD_RELOC_ARM_LDRS_SB_G2
:
27487 case BFD_RELOC_ARM_LDC_SB_G0
:
27488 case BFD_RELOC_ARM_LDC_SB_G1
:
27489 case BFD_RELOC_ARM_LDC_SB_G2
:
27490 case BFD_RELOC_ARM_V4BX
:
27491 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27492 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27493 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27494 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27495 case BFD_RELOC_ARM_GOTFUNCDESC
:
27496 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27497 case BFD_RELOC_ARM_FUNCDESC
:
27498 case BFD_RELOC_ARM_THUMB_BF17
:
27499 case BFD_RELOC_ARM_THUMB_BF19
:
27500 case BFD_RELOC_ARM_THUMB_BF13
:
27501 code
= fixp
->fx_r_type
;
27504 case BFD_RELOC_ARM_TLS_GOTDESC
:
27505 case BFD_RELOC_ARM_TLS_GD32
:
27506 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27507 case BFD_RELOC_ARM_TLS_LE32
:
27508 case BFD_RELOC_ARM_TLS_IE32
:
27509 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27510 case BFD_RELOC_ARM_TLS_LDM32
:
27511 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27512 /* BFD will include the symbol's address in the addend.
27513 But we don't want that, so subtract it out again here. */
27514 if (!S_IS_COMMON (fixp
->fx_addsy
))
27515 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
27516 code
= fixp
->fx_r_type
;
27520 case BFD_RELOC_ARM_IMMEDIATE
:
27521 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27522 _("internal relocation (type: IMMEDIATE) not fixed up"));
27525 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27526 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27527 _("ADRL used for a symbol not defined in the same file"));
27530 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27531 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27532 case BFD_RELOC_ARM_THUMB_LOOP12
:
27533 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27534 _("%s used for a symbol not defined in the same file"),
27535 bfd_get_reloc_code_name (fixp
->fx_r_type
));
27538 case BFD_RELOC_ARM_OFFSET_IMM
:
27539 if (section
->use_rela_p
)
27541 code
= fixp
->fx_r_type
;
27545 if (fixp
->fx_addsy
!= NULL
27546 && !S_IS_DEFINED (fixp
->fx_addsy
)
27547 && S_IS_LOCAL (fixp
->fx_addsy
))
27549 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27550 _("undefined local label `%s'"),
27551 S_GET_NAME (fixp
->fx_addsy
));
27555 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27556 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
27563 switch (fixp
->fx_r_type
)
27565 case BFD_RELOC_NONE
: type
= "NONE"; break;
27566 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
27567 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
27568 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
27569 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
27570 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
27571 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
27572 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
27573 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
27574 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
27575 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
27576 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
27577 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
27578 default: type
= _("<unknown>"); break;
27580 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27581 _("cannot represent %s relocation in this object file format"),
27588 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
27590 && fixp
->fx_addsy
== GOT_symbol
)
27592 code
= BFD_RELOC_ARM_GOTPC
;
27593 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
27597 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
27599 if (reloc
->howto
== NULL
)
27601 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27602 _("cannot represent %s relocation in this object file format"),
27603 bfd_get_reloc_code_name (code
));
27607 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
27608 vtable entry to be used in the relocation's section offset. */
27609 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27610 reloc
->address
= fixp
->fx_offset
;
27615 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
27618 cons_fix_new_arm (fragS
* frag
,
27622 bfd_reloc_code_real_type reloc
)
27627 FIXME: @@ Should look at CPU word size. */
27631 reloc
= BFD_RELOC_8
;
27634 reloc
= BFD_RELOC_16
;
27638 reloc
= BFD_RELOC_32
;
27641 reloc
= BFD_RELOC_64
;
27646 if (exp
->X_op
== O_secrel
)
27648 exp
->X_op
= O_symbol
;
27649 reloc
= BFD_RELOC_32_SECREL
;
27653 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
27656 #if defined (OBJ_COFF)
27658 arm_validate_fix (fixS
* fixP
)
27660 /* If the destination of the branch is a defined symbol which does not have
27661 the THUMB_FUNC attribute, then we must be calling a function which has
27662 the (interfacearm) attribute. We look for the Thumb entry point to that
27663 function and change the branch to refer to that function instead. */
27664 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
27665 && fixP
->fx_addsy
!= NULL
27666 && S_IS_DEFINED (fixP
->fx_addsy
)
27667 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
27669 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
27676 arm_force_relocation (struct fix
* fixp
)
27678 #if defined (OBJ_COFF) && defined (TE_PE)
27679 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
27683 /* In case we have a call or a branch to a function in ARM ISA mode from
27684 a thumb function or vice-versa force the relocation. These relocations
27685 are cleared off for some cores that might have blx and simple transformations
27689 switch (fixp
->fx_r_type
)
27691 case BFD_RELOC_ARM_PCREL_JUMP
:
27692 case BFD_RELOC_ARM_PCREL_CALL
:
27693 case BFD_RELOC_THUMB_PCREL_BLX
:
27694 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
27698 case BFD_RELOC_ARM_PCREL_BLX
:
27699 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27700 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27701 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27702 if (ARM_IS_FUNC (fixp
->fx_addsy
))
27711 /* Resolve these relocations even if the symbol is extern or weak.
27712 Technically this is probably wrong due to symbol preemption.
27713 In practice these relocations do not have enough range to be useful
27714 at dynamic link time, and some code (e.g. in the Linux kernel)
27715 expects these references to be resolved. */
27716 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
27717 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
27718 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
27719 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
27720 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27721 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
27722 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
27723 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
27724 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27725 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
27726 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
27727 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
27728 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
27729 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
27732 /* Always leave these relocations for the linker. */
27733 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27734 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27735 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27738 /* Always generate relocations against function symbols. */
27739 if (fixp
->fx_r_type
== BFD_RELOC_32
27741 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
27744 return generic_force_reloc (fixp
);
27747 #if defined (OBJ_ELF) || defined (OBJ_COFF)
27748 /* Relocations against function names must be left unadjusted,
27749 so that the linker can use this information to generate interworking
27750 stubs. The MIPS version of this function
27751 also prevents relocations that are mips-16 specific, but I do not
27752 know why it does this.
27755 There is one other problem that ought to be addressed here, but
27756 which currently is not: Taking the address of a label (rather
27757 than a function) and then later jumping to that address. Such
27758 addresses also ought to have their bottom bit set (assuming that
27759 they reside in Thumb code), but at the moment they will not. */
27762 arm_fix_adjustable (fixS
* fixP
)
27764 if (fixP
->fx_addsy
== NULL
)
27767 /* Preserve relocations against symbols with function type. */
27768 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
27771 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
27772 && fixP
->fx_subsy
== NULL
)
27775 /* We need the symbol name for the VTABLE entries. */
27776 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
27777 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27780 /* Don't allow symbols to be discarded on GOT related relocs. */
27781 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
27782 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
27783 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
27784 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
27785 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
27786 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
27787 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
27788 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
27789 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
27790 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
27791 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
27792 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
27793 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
27794 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
27795 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
27796 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
27797 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
27800 /* Similarly for group relocations. */
27801 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27802 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27803 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27806 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
27807 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
27808 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27809 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
27810 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
27811 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27812 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
27813 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
27814 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
27817 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
27818 offsets, so keep these symbols. */
27819 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
27820 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
27825 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
27829 elf32_arm_target_format (void)
27832 return (target_big_endian
27833 ? "elf32-bigarm-symbian"
27834 : "elf32-littlearm-symbian");
27835 #elif defined (TE_VXWORKS)
27836 return (target_big_endian
27837 ? "elf32-bigarm-vxworks"
27838 : "elf32-littlearm-vxworks");
27839 #elif defined (TE_NACL)
27840 return (target_big_endian
27841 ? "elf32-bigarm-nacl"
27842 : "elf32-littlearm-nacl");
27846 if (target_big_endian
)
27847 return "elf32-bigarm-fdpic";
27849 return "elf32-littlearm-fdpic";
27853 if (target_big_endian
)
27854 return "elf32-bigarm";
27856 return "elf32-littlearm";
27862 armelf_frob_symbol (symbolS
* symp
,
27865 elf_frob_symbol (symp
, puntp
);
27869 /* MD interface: Finalization. */
27874 literal_pool
* pool
;
27876 /* Ensure that all the predication blocks are properly closed. */
27877 check_pred_blocks_finished ();
27879 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
27881 /* Put it at the end of the relevant section. */
27882 subseg_set (pool
->section
, pool
->sub_section
);
27884 arm_elf_change_section ();
27891 /* Remove any excess mapping symbols generated for alignment frags in
27892 SEC. We may have created a mapping symbol before a zero byte
27893 alignment; remove it if there's a mapping symbol after the
27896 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
27897 void *dummy ATTRIBUTE_UNUSED
)
27899 segment_info_type
*seginfo
= seg_info (sec
);
27902 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
27905 for (fragp
= seginfo
->frchainP
->frch_root
;
27907 fragp
= fragp
->fr_next
)
27909 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
27910 fragS
*next
= fragp
->fr_next
;
27912 /* Variable-sized frags have been converted to fixed size by
27913 this point. But if this was variable-sized to start with,
27914 there will be a fixed-size frag after it. So don't handle
27916 if (sym
== NULL
|| next
== NULL
)
27919 if (S_GET_VALUE (sym
) < next
->fr_address
)
27920 /* Not at the end of this frag. */
27922 know (S_GET_VALUE (sym
) == next
->fr_address
);
27926 if (next
->tc_frag_data
.first_map
!= NULL
)
27928 /* Next frag starts with a mapping symbol. Discard this
27930 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
27934 if (next
->fr_next
== NULL
)
27936 /* This mapping symbol is at the end of the section. Discard
27938 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
27939 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
27943 /* As long as we have empty frags without any mapping symbols,
27945 /* If the next frag is non-empty and does not start with a
27946 mapping symbol, then this mapping symbol is required. */
27947 if (next
->fr_address
!= next
->fr_next
->fr_address
)
27950 next
= next
->fr_next
;
27952 while (next
!= NULL
);
27957 /* Adjust the symbol table. This marks Thumb symbols as distinct from
27961 arm_adjust_symtab (void)
27966 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
27968 if (ARM_IS_THUMB (sym
))
27970 if (THUMB_IS_FUNC (sym
))
27972 /* Mark the symbol as a Thumb function. */
27973 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
27974 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
27975 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
27977 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
27978 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
27980 as_bad (_("%s: unexpected function type: %d"),
27981 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
27983 else switch (S_GET_STORAGE_CLASS (sym
))
27986 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
27989 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
27992 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
28000 if (ARM_IS_INTERWORK (sym
))
28001 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
28008 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28010 if (ARM_IS_THUMB (sym
))
28012 elf_symbol_type
* elf_sym
;
28014 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
28015 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
28017 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
28018 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
28020 /* If it's a .thumb_func, declare it as so,
28021 otherwise tag label as .code 16. */
28022 if (THUMB_IS_FUNC (sym
))
28023 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
28024 ST_BRANCH_TO_THUMB
);
28025 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28026 elf_sym
->internal_elf_sym
.st_info
=
28027 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
28032 /* Remove any overlapping mapping symbols generated by alignment frags. */
28033 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
28034 /* Now do generic ELF adjustments. */
28035 elf_adjust_symtab ();
28039 /* MD interface: Initialization. */
28042 set_constant_flonums (void)
28046 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
28047 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
28051 /* Auto-select Thumb mode if it's the only available instruction set for the
28052 given architecture. */
28055 autoselect_thumb_from_cpu_variant (void)
28057 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
28058 opcode_select (16);
28067 if ( (arm_ops_hsh
= hash_new ()) == NULL
28068 || (arm_cond_hsh
= hash_new ()) == NULL
28069 || (arm_vcond_hsh
= hash_new ()) == NULL
28070 || (arm_shift_hsh
= hash_new ()) == NULL
28071 || (arm_psr_hsh
= hash_new ()) == NULL
28072 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
28073 || (arm_reg_hsh
= hash_new ()) == NULL
28074 || (arm_reloc_hsh
= hash_new ()) == NULL
28075 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
28076 as_fatal (_("virtual memory exhausted"));
28078 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
28079 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
28080 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
28081 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
28082 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
28083 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
28084 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
28085 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
28086 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
28087 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
28088 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
28089 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
28090 (void *) (v7m_psrs
+ i
));
28091 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
28092 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
28094 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
28096 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
28097 (void *) (barrier_opt_names
+ i
));
28099 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
28101 struct reloc_entry
* entry
= reloc_names
+ i
;
28103 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
28104 /* This makes encode_branch() use the EABI versions of this relocation. */
28105 entry
->reloc
= BFD_RELOC_UNUSED
;
28107 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
28111 set_constant_flonums ();
28113 /* Set the cpu variant based on the command-line options. We prefer
28114 -mcpu= over -march= if both are set (as for GCC); and we prefer
28115 -mfpu= over any other way of setting the floating point unit.
28116 Use of legacy options with new options are faulted. */
28119 if (mcpu_cpu_opt
|| march_cpu_opt
)
28120 as_bad (_("use of old and new-style options to set CPU type"));
28122 selected_arch
= *legacy_cpu
;
28124 else if (mcpu_cpu_opt
)
28126 selected_arch
= *mcpu_cpu_opt
;
28127 selected_ext
= *mcpu_ext_opt
;
28129 else if (march_cpu_opt
)
28131 selected_arch
= *march_cpu_opt
;
28132 selected_ext
= *march_ext_opt
;
28134 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28139 as_bad (_("use of old and new-style options to set FPU type"));
28141 selected_fpu
= *legacy_fpu
;
28144 selected_fpu
= *mfpu_opt
;
28147 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28148 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28149 /* Some environments specify a default FPU. If they don't, infer it
28150 from the processor. */
28152 selected_fpu
= *mcpu_fpu_opt
;
28153 else if (march_fpu_opt
)
28154 selected_fpu
= *march_fpu_opt
;
28156 selected_fpu
= fpu_default
;
28160 if (ARM_FEATURE_ZERO (selected_fpu
))
28162 if (!no_cpu_selected ())
28163 selected_fpu
= fpu_default
;
28165 selected_fpu
= fpu_arch_fpa
;
28169 if (ARM_FEATURE_ZERO (selected_arch
))
28171 selected_arch
= cpu_default
;
28172 selected_cpu
= selected_arch
;
28174 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28176 /* Autodection of feature mode: allow all features in cpu_variant but leave
28177 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28178 after all instruction have been processed and we can decide what CPU
28179 should be selected. */
28180 if (ARM_FEATURE_ZERO (selected_arch
))
28181 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28183 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28186 autoselect_thumb_from_cpu_variant ();
28188 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
28190 #if defined OBJ_COFF || defined OBJ_ELF
28192 unsigned int flags
= 0;
28194 #if defined OBJ_ELF
28195 flags
= meabi_flags
;
28197 switch (meabi_flags
)
28199 case EF_ARM_EABI_UNKNOWN
:
28201 /* Set the flags in the private structure. */
28202 if (uses_apcs_26
) flags
|= F_APCS26
;
28203 if (support_interwork
) flags
|= F_INTERWORK
;
28204 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
28205 if (pic_code
) flags
|= F_PIC
;
28206 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
28207 flags
|= F_SOFT_FLOAT
;
28209 switch (mfloat_abi_opt
)
28211 case ARM_FLOAT_ABI_SOFT
:
28212 case ARM_FLOAT_ABI_SOFTFP
:
28213 flags
|= F_SOFT_FLOAT
;
28216 case ARM_FLOAT_ABI_HARD
:
28217 if (flags
& F_SOFT_FLOAT
)
28218 as_bad (_("hard-float conflicts with specified fpu"));
28222 /* Using pure-endian doubles (even if soft-float). */
28223 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
28224 flags
|= F_VFP_FLOAT
;
28226 #if defined OBJ_ELF
28227 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
28228 flags
|= EF_ARM_MAVERICK_FLOAT
;
28231 case EF_ARM_EABI_VER4
:
28232 case EF_ARM_EABI_VER5
:
28233 /* No additional flags to set. */
28240 bfd_set_private_flags (stdoutput
, flags
);
28242 /* We have run out flags in the COFF header to encode the
28243 status of ATPCS support, so instead we create a dummy,
28244 empty, debug section called .arm.atpcs. */
28249 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
28253 bfd_set_section_flags
28254 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
28255 bfd_set_section_size (stdoutput
, sec
, 0);
28256 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
28262 /* Record the CPU type as well. */
28263 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
28264 mach
= bfd_mach_arm_iWMMXt2
;
28265 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
28266 mach
= bfd_mach_arm_iWMMXt
;
28267 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
28268 mach
= bfd_mach_arm_XScale
;
28269 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
28270 mach
= bfd_mach_arm_ep9312
;
28271 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
28272 mach
= bfd_mach_arm_5TE
;
28273 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
28275 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28276 mach
= bfd_mach_arm_5T
;
28278 mach
= bfd_mach_arm_5
;
28280 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
28282 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28283 mach
= bfd_mach_arm_4T
;
28285 mach
= bfd_mach_arm_4
;
28287 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
28288 mach
= bfd_mach_arm_3M
;
28289 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
28290 mach
= bfd_mach_arm_3
;
28291 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
28292 mach
= bfd_mach_arm_2a
;
28293 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
28294 mach
= bfd_mach_arm_2
;
28296 mach
= bfd_mach_arm_unknown
;
28298 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
28301 /* Command line processing. */
28304 Invocation line includes a switch not recognized by the base assembler.
28305 See if it's a processor-specific option.
28307 This routine is somewhat complicated by the need for backwards
28308 compatibility (since older releases of gcc can't be changed).
28309 The new options try to make the interface as compatible as
28312 New options (supported) are:
28314 -mcpu=<cpu name> Assemble for selected processor
28315 -march=<architecture name> Assemble for selected architecture
28316 -mfpu=<fpu architecture> Assemble for selected FPU.
28317 -EB/-mbig-endian Big-endian
28318 -EL/-mlittle-endian Little-endian
28319 -k Generate PIC code
28320 -mthumb Start in Thumb mode
28321 -mthumb-interwork Code supports ARM/Thumb interworking
28323 -m[no-]warn-deprecated Warn about deprecated features
28324 -m[no-]warn-syms Warn when symbols match instructions
28326 For now we will also provide support for:
28328 -mapcs-32 32-bit Program counter
28329 -mapcs-26 26-bit Program counter
28330 -macps-float Floats passed in FP registers
28331 -mapcs-reentrant Reentrant code
28333 (sometime these will probably be replaced with -mapcs=<list of options>
28334 and -matpcs=<list of options>)
28336 The remaining options are only supported for back-wards compatibility.
28337 Cpu variants, the arm part is optional:
28338 -m[arm]1 Currently not supported.
28339 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
28340 -m[arm]3 Arm 3 processor
28341 -m[arm]6[xx], Arm 6 processors
28342 -m[arm]7[xx][t][[d]m] Arm 7 processors
28343 -m[arm]8[10] Arm 8 processors
28344 -m[arm]9[20][tdmi] Arm 9 processors
28345 -mstrongarm[110[0]] StrongARM processors
28346 -mxscale XScale processors
28347 -m[arm]v[2345[t[e]]] Arm architectures
28348 -mall All (except the ARM1)
28350 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
28351 -mfpe-old (No float load/store multiples)
28352 -mvfpxd VFP Single precision
28354 -mno-fpu Disable all floating point instructions
28356 The following CPU names are recognized:
28357 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
28358 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
28359 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
28360 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
28361 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
28362 arm10t arm10e, arm1020t, arm1020e, arm10200e,
28363 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
28367 const char * md_shortopts
= "m:k";
28369 #ifdef ARM_BI_ENDIAN
28370 #define OPTION_EB (OPTION_MD_BASE + 0)
28371 #define OPTION_EL (OPTION_MD_BASE + 1)
28373 #if TARGET_BYTES_BIG_ENDIAN
28374 #define OPTION_EB (OPTION_MD_BASE + 0)
28376 #define OPTION_EL (OPTION_MD_BASE + 1)
28379 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
28380 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
28382 struct option md_longopts
[] =
28385 {"EB", no_argument
, NULL
, OPTION_EB
},
28388 {"EL", no_argument
, NULL
, OPTION_EL
},
28390 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
28392 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
28394 {NULL
, no_argument
, NULL
, 0}
28397 size_t md_longopts_size
= sizeof (md_longopts
);
28399 struct arm_option_table
28401 const char * option
; /* Option name to match. */
28402 const char * help
; /* Help information. */
28403 int * var
; /* Variable to change. */
28404 int value
; /* What to change it to. */
28405 const char * deprecated
; /* If non-null, print this message. */
28408 struct arm_option_table arm_opts
[] =
28410 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
28411 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
28412 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
28413 &support_interwork
, 1, NULL
},
28414 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
28415 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
28416 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
28418 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
28419 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
28420 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
28421 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
28424 /* These are recognized by the assembler, but have no affect on code. */
28425 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
28426 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
28428 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
28429 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
28430 &warn_on_deprecated
, 0, NULL
},
28431 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
28432 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
28433 {NULL
, NULL
, NULL
, 0, NULL
}
28436 struct arm_legacy_option_table
28438 const char * option
; /* Option name to match. */
28439 const arm_feature_set
** var
; /* Variable to change. */
28440 const arm_feature_set value
; /* What to change it to. */
28441 const char * deprecated
; /* If non-null, print this message. */
28444 const struct arm_legacy_option_table arm_legacy_opts
[] =
28446 /* DON'T add any new processors to this list -- we want the whole list
28447 to go away... Add them to the processors table instead. */
28448 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28449 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28450 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28451 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28452 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28453 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28454 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28455 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28456 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28457 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28458 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28459 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28460 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28461 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28462 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28463 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28464 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28465 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28466 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28467 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28468 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28469 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28470 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28471 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28472 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28473 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28474 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28475 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28476 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28477 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28478 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28479 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28480 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28481 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28482 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28483 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28484 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28485 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28486 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28487 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28488 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28489 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28490 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28491 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28492 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28493 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28494 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28495 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28496 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28497 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28498 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28499 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28500 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28501 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28502 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28503 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28504 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28505 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28506 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28507 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28508 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28509 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28510 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28511 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28512 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28513 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28514 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28515 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28516 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
28517 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
28518 N_("use -mcpu=strongarm110")},
28519 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
28520 N_("use -mcpu=strongarm1100")},
28521 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
28522 N_("use -mcpu=strongarm1110")},
28523 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
28524 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
28525 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
28527 /* Architecture variants -- don't add any more to this list either. */
28528 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28529 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28530 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28531 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28532 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28533 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28534 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28535 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28536 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28537 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28538 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28539 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28540 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28541 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28542 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28543 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28544 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28545 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28547 /* Floating point variants -- don't add any more to this list either. */
28548 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
28549 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
28550 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
28551 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
28552 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
28554 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
28557 struct arm_cpu_option_table
28561 const arm_feature_set value
;
28562 const arm_feature_set ext
;
28563 /* For some CPUs we assume an FPU unless the user explicitly sets
28565 const arm_feature_set default_fpu
;
28566 /* The canonical name of the CPU, or NULL to use NAME converted to upper
28568 const char * canonical_name
;
28571 /* This list should, at a minimum, contain all the cpu names
28572 recognized by GCC. */
28573 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
28575 static const struct arm_cpu_option_table arm_cpus
[] =
28577 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
28580 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
28583 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
28586 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
28589 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
28592 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
28595 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
28598 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
28601 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
28604 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
28607 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
28610 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
28613 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
28616 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
28619 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
28622 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
28625 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
28628 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
28631 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
28634 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
28637 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
28640 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
28643 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
28646 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
28649 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
28652 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
28655 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
28658 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
28661 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
28664 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
28667 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
28670 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
28673 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
28676 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
28679 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
28682 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
28685 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
28688 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
28691 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
28694 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
28697 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
28700 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
28703 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
28706 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
28709 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
28712 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
28716 /* For V5 or later processors we default to using VFP; but the user
28717 should really set the FPU type explicitly. */
28718 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
28721 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
28724 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28727 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28730 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
28733 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
28736 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
28739 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
28742 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
28745 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
28748 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
28751 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
28754 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
28757 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
28760 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
28763 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
28766 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
28769 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
28772 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
28775 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
28778 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
28781 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
28784 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
28787 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
28790 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
28793 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
28796 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
28799 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
28802 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
28805 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
28808 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
28811 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
28814 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
28817 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
28820 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
28823 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
28826 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
28827 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28829 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
28831 FPU_ARCH_NEON_VFP_V4
),
28832 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
28833 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
28834 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28835 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
28836 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28837 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
28838 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
28840 FPU_ARCH_NEON_VFP_V4
),
28841 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
28843 FPU_ARCH_NEON_VFP_V4
),
28844 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
28846 FPU_ARCH_NEON_VFP_V4
),
28847 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
28848 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28849 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28850 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
28851 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28852 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28853 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
28854 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28855 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28856 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
28857 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28858 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28859 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
28860 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28861 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28862 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
28863 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28864 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28865 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
28866 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28867 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28868 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
28869 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28870 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28871 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
28872 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28873 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28874 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
28875 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28876 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28877 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
28880 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
28882 FPU_ARCH_VFP_V3D16
),
28883 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
28884 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28886 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
28887 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28888 FPU_ARCH_VFP_V3D16
),
28889 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
28890 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
28891 FPU_ARCH_VFP_V3D16
),
28892 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
28893 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28894 FPU_ARCH_NEON_VFP_ARMV8
),
28895 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
28896 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
28898 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
28901 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
28904 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
28907 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
28910 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
28913 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
28916 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
28919 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
28920 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28921 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28922 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
28923 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
28924 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
28925 /* ??? XSCALE is really an architecture. */
28926 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
28930 /* ??? iwmmxt is not a processor. */
28931 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
28934 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
28937 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
28942 ARM_CPU_OPT ("ep9312", "ARM920T",
28943 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
28944 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
28946 /* Marvell processors. */
28947 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
28948 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28949 FPU_ARCH_VFP_V3D16
),
28950 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
28951 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
28952 FPU_ARCH_NEON_VFP_V4
),
28954 /* APM X-Gene family. */
28955 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
28957 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28958 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
28959 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
28960 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
28962 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
28966 struct arm_ext_table
28970 const arm_feature_set merge
;
28971 const arm_feature_set clear
;
28974 struct arm_arch_option_table
28978 const arm_feature_set value
;
28979 const arm_feature_set default_fpu
;
28980 const struct arm_ext_table
* ext_table
;
28983 /* Used to add support for +E and +noE extension. */
28984 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
28985 /* Used to add support for a +E extension. */
28986 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
28987 /* Used to add support for a +noE extension. */
28988 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
28990 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
28991 ~0 & ~FPU_ENDIAN_PURE)
28993 static const struct arm_ext_table armv5te_ext_table
[] =
28995 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
28996 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
28999 static const struct arm_ext_table armv7_ext_table
[] =
29001 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29002 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29005 static const struct arm_ext_table armv7ve_ext_table
[] =
29007 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
29008 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
29009 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29010 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29011 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29012 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
29013 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29015 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
29016 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29018 /* Aliases for +simd. */
29019 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29021 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29022 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29023 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29025 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29028 static const struct arm_ext_table armv7a_ext_table
[] =
29030 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29031 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29032 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29033 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29034 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29035 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
29036 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29038 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
29039 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29041 /* Aliases for +simd. */
29042 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29043 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29045 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29046 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29048 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
29049 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
29050 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29053 static const struct arm_ext_table armv7r_ext_table
[] =
29055 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
29056 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
29057 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29058 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29059 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
29060 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29061 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29062 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
29063 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29066 static const struct arm_ext_table armv7em_ext_table
[] =
29068 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
29069 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29070 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
29071 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
29072 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29073 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
29074 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29077 static const struct arm_ext_table armv8a_ext_table
[] =
29079 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29080 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29081 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29082 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29084 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29085 should use the +simd option to turn on FP. */
29086 ARM_REMOVE ("fp", ALL_FP
),
29087 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29088 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29089 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29093 static const struct arm_ext_table armv81a_ext_table
[] =
29095 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29096 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29097 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29099 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29100 should use the +simd option to turn on FP. */
29101 ARM_REMOVE ("fp", ALL_FP
),
29102 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29103 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29104 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29107 static const struct arm_ext_table armv82a_ext_table
[] =
29109 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29110 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
29111 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
29112 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29113 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29114 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29116 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29117 should use the +simd option to turn on FP. */
29118 ARM_REMOVE ("fp", ALL_FP
),
29119 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29120 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29121 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29124 static const struct arm_ext_table armv84a_ext_table
[] =
29126 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29127 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29128 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29129 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29131 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29132 should use the +simd option to turn on FP. */
29133 ARM_REMOVE ("fp", ALL_FP
),
29134 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29135 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29136 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29139 static const struct arm_ext_table armv85a_ext_table
[] =
29141 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29142 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29143 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29144 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29146 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29147 should use the +simd option to turn on FP. */
29148 ARM_REMOVE ("fp", ALL_FP
),
29149 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29152 static const struct arm_ext_table armv8m_main_ext_table
[] =
29154 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29155 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29156 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
29157 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29158 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29161 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
29163 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29164 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29166 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29167 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
29170 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29171 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29172 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
29173 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
29175 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29176 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
29177 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29178 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29181 static const struct arm_ext_table armv8r_ext_table
[] =
29183 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29184 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29185 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29186 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29187 ARM_REMOVE ("fp", ALL_FP
),
29188 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
29189 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29192 /* This list should, at a minimum, contain all the architecture names
29193 recognized by GCC. */
29194 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29195 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29196 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29198 static const struct arm_arch_option_table arm_archs
[] =
29200 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
29201 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
29202 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
29203 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29204 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29205 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
29206 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
29207 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
29208 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
29209 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
29210 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
29211 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
29212 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
29213 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
29214 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
29215 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
29216 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
29217 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29218 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29219 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
29220 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
29221 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29222 kept to preserve existing behaviour. */
29223 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29224 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29225 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
29226 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
29227 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
29228 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29229 kept to preserve existing behaviour. */
29230 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29231 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29232 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
29233 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
29234 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
29235 /* The official spelling of the ARMv7 profile variants is the dashed form.
29236 Accept the non-dashed form for compatibility with old toolchains. */
29237 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29238 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
29239 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29240 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29241 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29242 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29243 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29244 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
29245 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
29246 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
29248 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
29250 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
29251 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
29252 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
29253 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
29254 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
29255 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
29256 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
29257 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
29258 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
29259 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
29260 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29262 #undef ARM_ARCH_OPT
29264 /* ISA extensions in the co-processor and main instruction set space. */
29266 struct arm_option_extension_value_table
29270 const arm_feature_set merge_value
;
29271 const arm_feature_set clear_value
;
29272 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29273 indicates that an extension is available for all architectures while
29274 ARM_ANY marks an empty entry. */
29275 const arm_feature_set allowed_archs
[2];
29278 /* The following table must be in alphabetical order with a NULL last entry. */
29280 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29281 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29283 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29284 use the context sensitive approach using arm_ext_table's. */
29285 static const struct arm_option_extension_value_table arm_extensions
[] =
29287 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29288 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29289 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29290 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
29291 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29292 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
29293 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
29295 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29296 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29297 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
29298 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
29299 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29300 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29303 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29304 | ARM_EXT2_FP16_FML
),
29305 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29306 | ARM_EXT2_FP16_FML
),
29308 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29309 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29310 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29311 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29312 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29313 Thumb divide instruction. Due to this having the same name as the
29314 previous entry, this will be ignored when doing command-line parsing and
29315 only considered by build attribute selection code. */
29316 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29317 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29318 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
29319 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
29320 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
29321 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
29322 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
29323 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
29324 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
29325 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29326 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29327 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29328 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29329 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29330 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29331 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
29332 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
29333 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
29334 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29335 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29336 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29338 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
29339 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
29340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29341 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
29342 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
29343 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29344 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29345 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29347 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29348 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29349 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
29350 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29351 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
29352 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
29353 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29354 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
29356 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
29357 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29358 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
29359 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
29360 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
29364 /* ISA floating-point and Advanced SIMD extensions. */
29365 struct arm_option_fpu_value_table
29368 const arm_feature_set value
;
29371 /* This list should, at a minimum, contain all the fpu names
29372 recognized by GCC. */
29373 static const struct arm_option_fpu_value_table arm_fpus
[] =
29375 {"softfpa", FPU_NONE
},
29376 {"fpe", FPU_ARCH_FPE
},
29377 {"fpe2", FPU_ARCH_FPE
},
29378 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
29379 {"fpa", FPU_ARCH_FPA
},
29380 {"fpa10", FPU_ARCH_FPA
},
29381 {"fpa11", FPU_ARCH_FPA
},
29382 {"arm7500fe", FPU_ARCH_FPA
},
29383 {"softvfp", FPU_ARCH_VFP
},
29384 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
29385 {"vfp", FPU_ARCH_VFP_V2
},
29386 {"vfp9", FPU_ARCH_VFP_V2
},
29387 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
29388 {"vfp10", FPU_ARCH_VFP_V2
},
29389 {"vfp10-r0", FPU_ARCH_VFP_V1
},
29390 {"vfpxd", FPU_ARCH_VFP_V1xD
},
29391 {"vfpv2", FPU_ARCH_VFP_V2
},
29392 {"vfpv3", FPU_ARCH_VFP_V3
},
29393 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
29394 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
29395 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
29396 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
29397 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
29398 {"arm1020t", FPU_ARCH_VFP_V1
},
29399 {"arm1020e", FPU_ARCH_VFP_V2
},
29400 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
29401 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
29402 {"maverick", FPU_ARCH_MAVERICK
},
29403 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29404 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29405 {"neon-fp16", FPU_ARCH_NEON_FP16
},
29406 {"vfpv4", FPU_ARCH_VFP_V4
},
29407 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
29408 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
29409 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
29410 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
29411 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
29412 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
29413 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
29414 {"crypto-neon-fp-armv8",
29415 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
29416 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
29417 {"crypto-neon-fp-armv8.1",
29418 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
29419 {NULL
, ARM_ARCH_NONE
}
29422 struct arm_option_value_table
29428 static const struct arm_option_value_table arm_float_abis
[] =
29430 {"hard", ARM_FLOAT_ABI_HARD
},
29431 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
29432 {"soft", ARM_FLOAT_ABI_SOFT
},
29437 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
29438 static const struct arm_option_value_table arm_eabis
[] =
29440 {"gnu", EF_ARM_EABI_UNKNOWN
},
29441 {"4", EF_ARM_EABI_VER4
},
29442 {"5", EF_ARM_EABI_VER5
},
29447 struct arm_long_option_table
29449 const char * option
; /* Substring to match. */
29450 const char * help
; /* Help information. */
29451 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
29452 const char * deprecated
; /* If non-null, print this message. */
29456 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
29457 arm_feature_set
*ext_set
,
29458 const struct arm_ext_table
*ext_table
)
29460 /* We insist on extensions being specified in alphabetical order, and with
29461 extensions being added before being removed. We achieve this by having
29462 the global ARM_EXTENSIONS table in alphabetical order, and using the
29463 ADDING_VALUE variable to indicate whether we are adding an extension (1)
29464 or removing it (0) and only allowing it to change in the order
29466 const struct arm_option_extension_value_table
* opt
= NULL
;
29467 const arm_feature_set arm_any
= ARM_ANY
;
29468 int adding_value
= -1;
29470 while (str
!= NULL
&& *str
!= 0)
29477 as_bad (_("invalid architectural extension"));
29482 ext
= strchr (str
, '+');
29487 len
= strlen (str
);
29489 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
29491 if (adding_value
!= 0)
29494 opt
= arm_extensions
;
29502 if (adding_value
== -1)
29505 opt
= arm_extensions
;
29507 else if (adding_value
!= 1)
29509 as_bad (_("must specify extensions to add before specifying "
29510 "those to remove"));
29517 as_bad (_("missing architectural extension"));
29521 gas_assert (adding_value
!= -1);
29522 gas_assert (opt
!= NULL
);
29524 if (ext_table
!= NULL
)
29526 const struct arm_ext_table
* ext_opt
= ext_table
;
29527 bfd_boolean found
= FALSE
;
29528 for (; ext_opt
->name
!= NULL
; ext_opt
++)
29529 if (ext_opt
->name_len
== len
29530 && strncmp (ext_opt
->name
, str
, len
) == 0)
29534 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
29535 /* TODO: Option not supported. When we remove the
29536 legacy table this case should error out. */
29539 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
29543 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
29544 /* TODO: Option not supported. When we remove the
29545 legacy table this case should error out. */
29547 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
29559 /* Scan over the options table trying to find an exact match. */
29560 for (; opt
->name
!= NULL
; opt
++)
29561 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29563 int i
, nb_allowed_archs
=
29564 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
29565 /* Check we can apply the extension to this architecture. */
29566 for (i
= 0; i
< nb_allowed_archs
; i
++)
29569 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
29571 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
29574 if (i
== nb_allowed_archs
)
29576 as_bad (_("extension does not apply to the base architecture"));
29580 /* Add or remove the extension. */
29582 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
29584 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
29586 /* Allowing Thumb division instructions for ARMv7 in autodetection
29587 rely on this break so that duplicate extensions (extensions
29588 with the same name as a previous extension in the list) are not
29589 considered for command-line parsing. */
29593 if (opt
->name
== NULL
)
29595 /* Did we fail to find an extension because it wasn't specified in
29596 alphabetical order, or because it does not exist? */
29598 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29599 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29602 if (opt
->name
== NULL
)
29603 as_bad (_("unknown architectural extension `%s'"), str
);
29605 as_bad (_("architectural extensions must be specified in "
29606 "alphabetical order"));
29612 /* We should skip the extension we've just matched the next time
29624 arm_parse_cpu (const char *str
)
29626 const struct arm_cpu_option_table
*opt
;
29627 const char *ext
= strchr (str
, '+');
29633 len
= strlen (str
);
29637 as_bad (_("missing cpu name `%s'"), str
);
29641 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
29642 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29644 mcpu_cpu_opt
= &opt
->value
;
29645 if (mcpu_ext_opt
== NULL
)
29646 mcpu_ext_opt
= XNEW (arm_feature_set
);
29647 *mcpu_ext_opt
= opt
->ext
;
29648 mcpu_fpu_opt
= &opt
->default_fpu
;
29649 if (opt
->canonical_name
)
29651 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
29652 strcpy (selected_cpu_name
, opt
->canonical_name
);
29658 if (len
>= sizeof selected_cpu_name
)
29659 len
= (sizeof selected_cpu_name
) - 1;
29661 for (i
= 0; i
< len
; i
++)
29662 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
29663 selected_cpu_name
[i
] = 0;
29667 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
29672 as_bad (_("unknown cpu `%s'"), str
);
29677 arm_parse_arch (const char *str
)
29679 const struct arm_arch_option_table
*opt
;
29680 const char *ext
= strchr (str
, '+');
29686 len
= strlen (str
);
29690 as_bad (_("missing architecture name `%s'"), str
);
29694 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
29695 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29697 march_cpu_opt
= &opt
->value
;
29698 if (march_ext_opt
== NULL
)
29699 march_ext_opt
= XNEW (arm_feature_set
);
29700 *march_ext_opt
= arm_arch_none
;
29701 march_fpu_opt
= &opt
->default_fpu
;
29702 strcpy (selected_cpu_name
, opt
->name
);
29705 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
29711 as_bad (_("unknown architecture `%s'\n"), str
);
29716 arm_parse_fpu (const char * str
)
29718 const struct arm_option_fpu_value_table
* opt
;
29720 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
29721 if (streq (opt
->name
, str
))
29723 mfpu_opt
= &opt
->value
;
29727 as_bad (_("unknown floating point format `%s'\n"), str
);
29732 arm_parse_float_abi (const char * str
)
29734 const struct arm_option_value_table
* opt
;
29736 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
29737 if (streq (opt
->name
, str
))
29739 mfloat_abi_opt
= opt
->value
;
29743 as_bad (_("unknown floating point abi `%s'\n"), str
);
29749 arm_parse_eabi (const char * str
)
29751 const struct arm_option_value_table
*opt
;
29753 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
29754 if (streq (opt
->name
, str
))
29756 meabi_flags
= opt
->value
;
29759 as_bad (_("unknown EABI `%s'\n"), str
);
29765 arm_parse_it_mode (const char * str
)
29767 bfd_boolean ret
= TRUE
;
29769 if (streq ("arm", str
))
29770 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
29771 else if (streq ("thumb", str
))
29772 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
29773 else if (streq ("always", str
))
29774 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
29775 else if (streq ("never", str
))
29776 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
29779 as_bad (_("unknown implicit IT mode `%s', should be "\
29780 "arm, thumb, always, or never."), str
);
29788 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
29790 codecomposer_syntax
= TRUE
;
29791 arm_comment_chars
[0] = ';';
29792 arm_line_separator_chars
[0] = 0;
29796 struct arm_long_option_table arm_long_opts
[] =
29798 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
29799 arm_parse_cpu
, NULL
},
29800 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
29801 arm_parse_arch
, NULL
},
29802 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
29803 arm_parse_fpu
, NULL
},
29804 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
29805 arm_parse_float_abi
, NULL
},
29807 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
29808 arm_parse_eabi
, NULL
},
29810 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
29811 arm_parse_it_mode
, NULL
},
29812 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
29813 arm_ccs_mode
, NULL
},
29814 {NULL
, NULL
, 0, NULL
}
29818 md_parse_option (int c
, const char * arg
)
29820 struct arm_option_table
*opt
;
29821 const struct arm_legacy_option_table
*fopt
;
29822 struct arm_long_option_table
*lopt
;
29828 target_big_endian
= 1;
29834 target_big_endian
= 0;
29838 case OPTION_FIX_V4BX
:
29846 #endif /* OBJ_ELF */
29849 /* Listing option. Just ignore these, we don't support additional
29854 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
29856 if (c
== opt
->option
[0]
29857 && ((arg
== NULL
&& opt
->option
[1] == 0)
29858 || streq (arg
, opt
->option
+ 1)))
29860 /* If the option is deprecated, tell the user. */
29861 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
29862 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29863 arg
? arg
: "", _(opt
->deprecated
));
29865 if (opt
->var
!= NULL
)
29866 *opt
->var
= opt
->value
;
29872 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
29874 if (c
== fopt
->option
[0]
29875 && ((arg
== NULL
&& fopt
->option
[1] == 0)
29876 || streq (arg
, fopt
->option
+ 1)))
29878 /* If the option is deprecated, tell the user. */
29879 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
29880 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
29881 arg
? arg
: "", _(fopt
->deprecated
));
29883 if (fopt
->var
!= NULL
)
29884 *fopt
->var
= &fopt
->value
;
29890 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
29892 /* These options are expected to have an argument. */
29893 if (c
== lopt
->option
[0]
29895 && strncmp (arg
, lopt
->option
+ 1,
29896 strlen (lopt
->option
+ 1)) == 0)
29898 /* If the option is deprecated, tell the user. */
29899 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
29900 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
29901 _(lopt
->deprecated
));
29903 /* Call the sup-option parser. */
29904 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
29915 md_show_usage (FILE * fp
)
29917 struct arm_option_table
*opt
;
29918 struct arm_long_option_table
*lopt
;
29920 fprintf (fp
, _(" ARM-specific assembler options:\n"));
29922 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
29923 if (opt
->help
!= NULL
)
29924 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
29926 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
29927 if (lopt
->help
!= NULL
)
29928 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
29932 -EB assemble code for a big-endian cpu\n"));
29937 -EL assemble code for a little-endian cpu\n"));
29941 --fix-v4bx Allow BX in ARMv4 code\n"));
29945 --fdpic generate an FDPIC object file\n"));
29946 #endif /* OBJ_ELF */
29954 arm_feature_set flags
;
29955 } cpu_arch_ver_table
;
29957 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
29958 chronologically for architectures, with an exception for ARMv6-M and
29959 ARMv6S-M due to legacy reasons. No new architecture should have a
29960 special case. This allows for build attribute selection results to be
29961 stable when new architectures are added. */
29962 static const cpu_arch_ver_table cpu_arch_ver
[] =
29964 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
29965 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
29966 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
29967 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
29968 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
29969 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
29970 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
29971 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
29972 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
29973 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
29974 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
29975 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
29976 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
29977 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
29978 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
29979 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
29980 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
29981 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
29982 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
29983 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
29984 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
29985 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
29986 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
29987 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
29989 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
29990 always selected build attributes to match those of ARMv6-M
29991 (resp. ARMv6S-M). However, due to these architectures being a strict
29992 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
29993 would be selected when fully respecting chronology of architectures.
29994 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
29995 move them before ARMv7 architectures. */
29996 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
29997 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
29999 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
30000 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
30001 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
30002 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
30003 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
30004 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
30005 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
30006 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
30007 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
30008 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
30009 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
30010 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
30011 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
30012 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
30013 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
30014 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
30015 {-1, ARM_ARCH_NONE
}
30018 /* Set an attribute if it has not already been set by the user. */
30021 aeabi_set_attribute_int (int tag
, int value
)
30024 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30025 || !attributes_set_explicitly
[tag
])
30026 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
30030 aeabi_set_attribute_string (int tag
, const char *value
)
30033 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30034 || !attributes_set_explicitly
[tag
])
30035 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
30038 /* Return whether features in the *NEEDED feature set are available via
30039 extensions for the architecture whose feature set is *ARCH_FSET. */
30042 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
30043 const arm_feature_set
*needed
)
30045 int i
, nb_allowed_archs
;
30046 arm_feature_set ext_fset
;
30047 const struct arm_option_extension_value_table
*opt
;
30049 ext_fset
= arm_arch_none
;
30050 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30052 /* Extension does not provide any feature we need. */
30053 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
30057 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30058 for (i
= 0; i
< nb_allowed_archs
; i
++)
30061 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
30064 /* Extension is available, add it. */
30065 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
30066 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
30070 /* Can we enable all features in *needed? */
30071 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
30074 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30075 a given architecture feature set *ARCH_EXT_FSET including extension feature
30076 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30077 - if true, check for an exact match of the architecture modulo extensions;
30078 - otherwise, select build attribute value of the first superset
30079 architecture released so that results remains stable when new architectures
30081 For -march/-mcpu=all the build attribute value of the most featureful
30082 architecture is returned. Tag_CPU_arch_profile result is returned in
30086 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
30087 const arm_feature_set
*ext_fset
,
30088 char *profile
, int exact_match
)
30090 arm_feature_set arch_fset
;
30091 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
30093 /* Select most featureful architecture with all its extensions if building
30094 for -march=all as the feature sets used to set build attributes. */
30095 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
30097 /* Force revisiting of decision for each new architecture. */
30098 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30100 return TAG_CPU_ARCH_V8
;
30103 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
30105 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
30107 arm_feature_set known_arch_fset
;
30109 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
30112 /* Base architecture match user-specified architecture and
30113 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30114 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
30119 /* Base architecture match user-specified architecture only
30120 (eg. ARMv6-M in the same case as above). Record it in case we
30121 find a match with above condition. */
30122 else if (p_ver_ret
== NULL
30123 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
30129 /* Architecture has all features wanted. */
30130 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
30132 arm_feature_set added_fset
;
30134 /* Compute features added by this architecture over the one
30135 recorded in p_ver_ret. */
30136 if (p_ver_ret
!= NULL
)
30137 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
30139 /* First architecture that match incl. with extensions, or the
30140 only difference in features over the recorded match is
30141 features that were optional and are now mandatory. */
30142 if (p_ver_ret
== NULL
30143 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
30149 else if (p_ver_ret
== NULL
)
30151 arm_feature_set needed_ext_fset
;
30153 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
30155 /* Architecture has all features needed when using some
30156 extensions. Record it and continue searching in case there
30157 exist an architecture providing all needed features without
30158 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30160 if (have_ext_for_needed_feat_p (&known_arch_fset
,
30167 if (p_ver_ret
== NULL
)
30171 /* Tag_CPU_arch_profile. */
30172 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
30173 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
30174 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
30175 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
30177 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
30179 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
30183 return p_ver_ret
->val
;
30186 /* Set the public EABI object attributes. */
30189 aeabi_set_public_attributes (void)
30191 char profile
= '\0';
30194 int fp16_optional
= 0;
30195 int skip_exact_match
= 0;
30196 arm_feature_set flags
, flags_arch
, flags_ext
;
30198 /* Autodetection mode, choose the architecture based the instructions
30200 if (no_cpu_selected ())
30202 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
30204 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
30205 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
30207 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
30208 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
30210 /* Code run during relaxation relies on selected_cpu being set. */
30211 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30212 flags_ext
= arm_arch_none
;
30213 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
30214 selected_ext
= flags_ext
;
30215 selected_cpu
= flags
;
30217 /* Otherwise, choose the architecture based on the capabilities of the
30221 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
30222 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
30223 flags_ext
= selected_ext
;
30224 flags
= selected_cpu
;
30226 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
30228 /* Allow the user to override the reported architecture. */
30229 if (!ARM_FEATURE_ZERO (selected_object_arch
))
30231 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
30232 flags_ext
= arm_arch_none
;
30235 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
30237 /* When this function is run again after relaxation has happened there is no
30238 way to determine whether an architecture or CPU was specified by the user:
30239 - selected_cpu is set above for relaxation to work;
30240 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30241 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30242 Therefore, if not in -march=all case we first try an exact match and fall
30243 back to autodetection. */
30244 if (!skip_exact_match
)
30245 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
30247 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
30249 as_bad (_("no architecture contains all the instructions used\n"));
30251 /* Tag_CPU_name. */
30252 if (selected_cpu_name
[0])
30256 q
= selected_cpu_name
;
30257 if (strncmp (q
, "armv", 4) == 0)
30262 for (i
= 0; q
[i
]; i
++)
30263 q
[i
] = TOUPPER (q
[i
]);
30265 aeabi_set_attribute_string (Tag_CPU_name
, q
);
30268 /* Tag_CPU_arch. */
30269 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
30271 /* Tag_CPU_arch_profile. */
30272 if (profile
!= '\0')
30273 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
30275 /* Tag_DSP_extension. */
30276 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
30277 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
30279 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30280 /* Tag_ARM_ISA_use. */
30281 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
30282 || ARM_FEATURE_ZERO (flags_arch
))
30283 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
30285 /* Tag_THUMB_ISA_use. */
30286 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
30287 || ARM_FEATURE_ZERO (flags_arch
))
30291 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30292 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
30294 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
30298 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
30301 /* Tag_VFP_arch. */
30302 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
30303 aeabi_set_attribute_int (Tag_VFP_arch
,
30304 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30306 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
30307 aeabi_set_attribute_int (Tag_VFP_arch
,
30308 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30310 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
30313 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
30315 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
30317 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
30320 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
30321 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
30322 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
30323 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
30324 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
30326 /* Tag_ABI_HardFP_use. */
30327 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
30328 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
30329 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
30331 /* Tag_WMMX_arch. */
30332 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
30333 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
30334 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
30335 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
30337 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
30338 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
30339 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
30340 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
30341 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
30342 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
30344 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
30346 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
30350 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
30355 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
30356 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
30357 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
30358 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
30360 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
30361 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
30362 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
30366 We set Tag_DIV_use to two when integer divide instructions have been used
30367 in ARM state, or when Thumb integer divide instructions have been used,
30368 but we have no architecture profile set, nor have we any ARM instructions.
30370 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
30371 by the base architecture.
30373 For new architectures we will have to check these tests. */
30374 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30375 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30376 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
30377 aeabi_set_attribute_int (Tag_DIV_use
, 0);
30378 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
30379 || (profile
== '\0'
30380 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
30381 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
30382 aeabi_set_attribute_int (Tag_DIV_use
, 2);
30384 /* Tag_MP_extension_use. */
30385 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
30386 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
30388 /* Tag Virtualization_use. */
30389 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
30391 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
30394 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
30397 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
30398 finished and free extension feature bits which will not be used anymore. */
30401 arm_md_post_relax (void)
30403 aeabi_set_public_attributes ();
30404 XDELETE (mcpu_ext_opt
);
30405 mcpu_ext_opt
= NULL
;
30406 XDELETE (march_ext_opt
);
30407 march_ext_opt
= NULL
;
30410 /* Add the default contents for the .ARM.attributes section. */
30415 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30418 aeabi_set_public_attributes ();
30420 #endif /* OBJ_ELF */
30422 /* Parse a .cpu directive. */
30425 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
30427 const struct arm_cpu_option_table
*opt
;
30431 name
= input_line_pointer
;
30432 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30433 input_line_pointer
++;
30434 saved_char
= *input_line_pointer
;
30435 *input_line_pointer
= 0;
30437 /* Skip the first "all" entry. */
30438 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
30439 if (streq (opt
->name
, name
))
30441 selected_arch
= opt
->value
;
30442 selected_ext
= opt
->ext
;
30443 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30444 if (opt
->canonical_name
)
30445 strcpy (selected_cpu_name
, opt
->canonical_name
);
30449 for (i
= 0; opt
->name
[i
]; i
++)
30450 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30452 selected_cpu_name
[i
] = 0;
30454 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30456 *input_line_pointer
= saved_char
;
30457 demand_empty_rest_of_line ();
30460 as_bad (_("unknown cpu `%s'"), name
);
30461 *input_line_pointer
= saved_char
;
30462 ignore_rest_of_line ();
30465 /* Parse a .arch directive. */
30468 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
30470 const struct arm_arch_option_table
*opt
;
30474 name
= input_line_pointer
;
30475 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30476 input_line_pointer
++;
30477 saved_char
= *input_line_pointer
;
30478 *input_line_pointer
= 0;
30480 /* Skip the first "all" entry. */
30481 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30482 if (streq (opt
->name
, name
))
30484 selected_arch
= opt
->value
;
30485 selected_ext
= arm_arch_none
;
30486 selected_cpu
= selected_arch
;
30487 strcpy (selected_cpu_name
, opt
->name
);
30488 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30489 *input_line_pointer
= saved_char
;
30490 demand_empty_rest_of_line ();
30494 as_bad (_("unknown architecture `%s'\n"), name
);
30495 *input_line_pointer
= saved_char
;
30496 ignore_rest_of_line ();
30499 /* Parse a .object_arch directive. */
30502 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
30504 const struct arm_arch_option_table
*opt
;
30508 name
= input_line_pointer
;
30509 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30510 input_line_pointer
++;
30511 saved_char
= *input_line_pointer
;
30512 *input_line_pointer
= 0;
30514 /* Skip the first "all" entry. */
30515 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30516 if (streq (opt
->name
, name
))
30518 selected_object_arch
= opt
->value
;
30519 *input_line_pointer
= saved_char
;
30520 demand_empty_rest_of_line ();
30524 as_bad (_("unknown architecture `%s'\n"), name
);
30525 *input_line_pointer
= saved_char
;
30526 ignore_rest_of_line ();
30529 /* Parse a .arch_extension directive. */
30532 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
30534 const struct arm_option_extension_value_table
*opt
;
30537 int adding_value
= 1;
30539 name
= input_line_pointer
;
30540 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30541 input_line_pointer
++;
30542 saved_char
= *input_line_pointer
;
30543 *input_line_pointer
= 0;
30545 if (strlen (name
) >= 2
30546 && strncmp (name
, "no", 2) == 0)
30552 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30553 if (streq (opt
->name
, name
))
30555 int i
, nb_allowed_archs
=
30556 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
30557 for (i
= 0; i
< nb_allowed_archs
; i
++)
30560 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
30562 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
30566 if (i
== nb_allowed_archs
)
30568 as_bad (_("architectural extension `%s' is not allowed for the "
30569 "current base architecture"), name
);
30574 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
30577 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
30579 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30580 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30581 *input_line_pointer
= saved_char
;
30582 demand_empty_rest_of_line ();
30583 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
30584 on this return so that duplicate extensions (extensions with the
30585 same name as a previous extension in the list) are not considered
30586 for command-line parsing. */
30590 if (opt
->name
== NULL
)
30591 as_bad (_("unknown architecture extension `%s'\n"), name
);
30593 *input_line_pointer
= saved_char
;
30594 ignore_rest_of_line ();
30597 /* Parse a .fpu directive. */
30600 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
30602 const struct arm_option_fpu_value_table
*opt
;
30606 name
= input_line_pointer
;
30607 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30608 input_line_pointer
++;
30609 saved_char
= *input_line_pointer
;
30610 *input_line_pointer
= 0;
30612 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30613 if (streq (opt
->name
, name
))
30615 selected_fpu
= opt
->value
;
30616 #ifndef CPU_DEFAULT
30617 if (no_cpu_selected ())
30618 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30621 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30622 *input_line_pointer
= saved_char
;
30623 demand_empty_rest_of_line ();
30627 as_bad (_("unknown floating point format `%s'\n"), name
);
30628 *input_line_pointer
= saved_char
;
30629 ignore_rest_of_line ();
30632 /* Copy symbol information. */
30635 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
30637 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
30641 /* Given a symbolic attribute NAME, return the proper integer value.
30642 Returns -1 if the attribute is not known. */
30645 arm_convert_symbolic_attribute (const char *name
)
30647 static const struct
30652 attribute_table
[] =
30654 /* When you modify this table you should
30655 also modify the list in doc/c-arm.texi. */
30656 #define T(tag) {#tag, tag}
30657 T (Tag_CPU_raw_name
),
30660 T (Tag_CPU_arch_profile
),
30661 T (Tag_ARM_ISA_use
),
30662 T (Tag_THUMB_ISA_use
),
30666 T (Tag_Advanced_SIMD_arch
),
30667 T (Tag_PCS_config
),
30668 T (Tag_ABI_PCS_R9_use
),
30669 T (Tag_ABI_PCS_RW_data
),
30670 T (Tag_ABI_PCS_RO_data
),
30671 T (Tag_ABI_PCS_GOT_use
),
30672 T (Tag_ABI_PCS_wchar_t
),
30673 T (Tag_ABI_FP_rounding
),
30674 T (Tag_ABI_FP_denormal
),
30675 T (Tag_ABI_FP_exceptions
),
30676 T (Tag_ABI_FP_user_exceptions
),
30677 T (Tag_ABI_FP_number_model
),
30678 T (Tag_ABI_align_needed
),
30679 T (Tag_ABI_align8_needed
),
30680 T (Tag_ABI_align_preserved
),
30681 T (Tag_ABI_align8_preserved
),
30682 T (Tag_ABI_enum_size
),
30683 T (Tag_ABI_HardFP_use
),
30684 T (Tag_ABI_VFP_args
),
30685 T (Tag_ABI_WMMX_args
),
30686 T (Tag_ABI_optimization_goals
),
30687 T (Tag_ABI_FP_optimization_goals
),
30688 T (Tag_compatibility
),
30689 T (Tag_CPU_unaligned_access
),
30690 T (Tag_FP_HP_extension
),
30691 T (Tag_VFP_HP_extension
),
30692 T (Tag_ABI_FP_16bit_format
),
30693 T (Tag_MPextension_use
),
30695 T (Tag_nodefaults
),
30696 T (Tag_also_compatible_with
),
30697 T (Tag_conformance
),
30699 T (Tag_Virtualization_use
),
30700 T (Tag_DSP_extension
),
30702 /* We deliberately do not include Tag_MPextension_use_legacy. */
30710 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
30711 if (streq (name
, attribute_table
[i
].name
))
30712 return attribute_table
[i
].tag
;
30717 /* Apply sym value for relocations only in the case that they are for
30718 local symbols in the same segment as the fixup and you have the
30719 respective architectural feature for blx and simple switches. */
30722 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
30725 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
30726 /* PR 17444: If the local symbol is in a different section then a reloc
30727 will always be generated for it, so applying the symbol value now
30728 will result in a double offset being stored in the relocation. */
30729 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
30730 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
30732 switch (fixP
->fx_r_type
)
30734 case BFD_RELOC_ARM_PCREL_BLX
:
30735 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30736 if (ARM_IS_FUNC (fixP
->fx_addsy
))
30740 case BFD_RELOC_ARM_PCREL_CALL
:
30741 case BFD_RELOC_THUMB_PCREL_BLX
:
30742 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
30753 #endif /* OBJ_ELF */