1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1050 enum fp_16bit_format
1052 ARM_FP16_FORMAT_IEEE
= 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1054 ARM_FP16_FORMAT_DEFAULT
= 0x3
1057 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1061 skip_past_char (char ** str
, char c
)
1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str
);
1075 #define skip_past_comma(str) skip_past_char (str, ',')
1077 /* Arithmetic expressions (possibly involving symbols). */
1079 /* Return TRUE if anything in the expression is a bignum. */
1082 walk_no_bignums (symbolS
* sp
)
1084 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1087 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1089 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1090 || (symbol_get_value_expression (sp
)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1097 static bfd_boolean in_my_get_expression
= FALSE
;
1099 /* Third argument to my_get_expression. */
1100 #define GE_NO_PREFIX 0
1101 #define GE_IMM_PREFIX 1
1102 #define GE_OPT_PREFIX 2
1103 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105 #define GE_OPT_PREFIX_BIG 3
1108 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1112 /* In unified syntax, all prefixes are optional. */
1114 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1117 switch (prefix_mode
)
1119 case GE_NO_PREFIX
: break;
1121 if (!is_immediate_prefix (**str
))
1123 inst
.error
= _("immediate expression requires a # prefix");
1129 case GE_OPT_PREFIX_BIG
:
1130 if (is_immediate_prefix (**str
))
1137 memset (ep
, 0, sizeof (expressionS
));
1139 save_in
= input_line_pointer
;
1140 input_line_pointer
= *str
;
1141 in_my_get_expression
= TRUE
;
1143 in_my_get_expression
= FALSE
;
1145 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1147 /* We found a bad or missing expression in md_operand(). */
1148 *str
= input_line_pointer
;
1149 input_line_pointer
= save_in
;
1150 if (inst
.error
== NULL
)
1151 inst
.error
= (ep
->X_op
== O_absent
1152 ? _("missing expression") :_("bad expression"));
1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
1159 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1160 && (ep
->X_op
== O_big
1161 || (ep
->X_add_symbol
1162 && (walk_no_bignums (ep
->X_add_symbol
)
1164 && walk_no_bignums (ep
->X_op_symbol
))))))
1166 inst
.error
= _("invalid constant");
1167 *str
= input_line_pointer
;
1168 input_line_pointer
= save_in
;
1172 *str
= input_line_pointer
;
1173 input_line_pointer
= save_in
;
1177 /* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1192 md_atof (int type
, char * litP
, int * sizeP
)
1195 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1232 return _("Unrecognized or unsupported floating point constant");
1235 t
= atof_ieee (input_line_pointer
, type
, words
);
1237 input_line_pointer
= t
;
1238 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1240 if (target_big_endian
|| prec
== 1)
1241 for (i
= 0; i
< prec
; i
++)
1243 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1244 litP
+= sizeof (LITTLENUM_TYPE
);
1246 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1247 for (i
= prec
- 1; i
>= 0; i
--)
1249 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1250 litP
+= sizeof (LITTLENUM_TYPE
);
1253 /* For a 4 byte float the order of elements in `words' is 1 0.
1254 For an 8 byte float the order is 1 0 3 2. */
1255 for (i
= 0; i
< prec
; i
+= 2)
1257 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1258 sizeof (LITTLENUM_TYPE
));
1259 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1260 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1261 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1267 /* We handle all bad expressions here, so that we can report the faulty
1268 instruction in the error message. */
1271 md_operand (expressionS
* exp
)
1273 if (in_my_get_expression
)
1274 exp
->X_op
= O_illegal
;
1277 /* Immediate values. */
1280 /* Generic immediate-value read function for use in directives.
1281 Accepts anything that 'expression' can fold to a constant.
1282 *val receives the number. */
1285 immediate_for_directive (int *val
)
1288 exp
.X_op
= O_illegal
;
1290 if (is_immediate_prefix (*input_line_pointer
))
1292 input_line_pointer
++;
1296 if (exp
.X_op
!= O_constant
)
1298 as_bad (_("expected #constant"));
1299 ignore_rest_of_line ();
1302 *val
= exp
.X_add_number
;
1307 /* Register parsing. */
1309 /* Generic register parser. CCP points to what should be the
1310 beginning of a register name. If it is indeed a valid register
1311 name, advance CCP over it and return the reg_entry structure;
1312 otherwise return NULL. Does not issue diagnostics. */
1314 static struct reg_entry
*
1315 arm_reg_parse_multi (char **ccp
)
1319 struct reg_entry
*reg
;
1321 skip_whitespace (start
);
1323 #ifdef REGISTER_PREFIX
1324 if (*start
!= REGISTER_PREFIX
)
1328 #ifdef OPTIONAL_REGISTER_PREFIX
1329 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1334 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1339 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1341 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1351 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1352 enum arm_reg_type type
)
1354 /* Alternative syntaxes are accepted for a few register classes. */
1361 /* Generic coprocessor register names are allowed for these. */
1362 if (reg
&& reg
->type
== REG_TYPE_CN
)
1367 /* For backward compatibility, a bare number is valid here. */
1369 unsigned long processor
= strtoul (start
, ccp
, 10);
1370 if (*ccp
!= start
&& processor
<= 15)
1375 case REG_TYPE_MMXWC
:
1376 /* WC includes WCG. ??? I'm not sure this is true for all
1377 instructions that take WC registers. */
1378 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1389 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1390 return value is the register number or FAIL. */
1393 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1396 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1399 /* Do not allow a scalar (reg+index) to parse as a register. */
1400 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1403 if (reg
&& reg
->type
== type
)
1406 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1413 /* Parse a Neon type specifier. *STR should point at the leading '.'
1414 character. Does no verification at this stage that the type fits the opcode
1421 Can all be legally parsed by this function.
1423 Fills in neon_type struct pointer with parsed information, and updates STR
1424 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1425 type, FAIL if not. */
1428 parse_neon_type (struct neon_type
*type
, char **str
)
1435 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1437 enum neon_el_type thistype
= NT_untyped
;
1438 unsigned thissize
= -1u;
1445 /* Just a size without an explicit type. */
1449 switch (TOLOWER (*ptr
))
1451 case 'i': thistype
= NT_integer
; break;
1452 case 'f': thistype
= NT_float
; break;
1453 case 'p': thistype
= NT_poly
; break;
1454 case 's': thistype
= NT_signed
; break;
1455 case 'u': thistype
= NT_unsigned
; break;
1457 thistype
= NT_float
;
1462 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1468 /* .f is an abbreviation for .f32. */
1469 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1474 thissize
= strtoul (ptr
, &ptr
, 10);
1476 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1479 as_bad (_("bad size %d in type specifier"), thissize
);
1487 type
->el
[type
->elems
].type
= thistype
;
1488 type
->el
[type
->elems
].size
= thissize
;
1493 /* Empty/missing type is not a successful parse. */
1494 if (type
->elems
== 0)
1502 /* Errors may be set multiple times during parsing or bit encoding
1503 (particularly in the Neon bits), but usually the earliest error which is set
1504 will be the most meaningful. Avoid overwriting it with later (cascading)
1505 errors by calling this function. */
1508 first_error (const char *err
)
1514 /* Parse a single type, e.g. ".s32", leading period included. */
1516 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1519 struct neon_type optype
;
1523 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1525 if (optype
.elems
== 1)
1526 *vectype
= optype
.el
[0];
1529 first_error (_("only one type should be specified for operand"));
1535 first_error (_("vector type expected"));
1547 /* Special meanings for indices (which have a range of 0-7), which will fit into
1550 #define NEON_ALL_LANES 15
1551 #define NEON_INTERLEAVE_LANES 14
1553 /* Record a use of the given feature. */
1555 record_feature_use (const arm_feature_set
*feature
)
1558 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1560 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1563 /* If the given feature available in the selected CPU, mark it as used.
1564 Returns TRUE iff feature is available. */
1566 mark_feature_used (const arm_feature_set
*feature
)
1569 /* Do not support the use of MVE only instructions when in auto-detection or
1571 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1572 && ARM_CPU_IS_ANY (cpu_variant
))
1574 first_error (BAD_MVE_AUTO
);
1577 /* Ensure the option is valid on the current architecture. */
1578 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1581 /* Add the appropriate architecture feature for the barrier option used.
1583 record_feature_use (feature
);
1588 /* Parse either a register or a scalar, with an optional type. Return the
1589 register number, and optionally fill in the actual type of the register
1590 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1591 type/index information in *TYPEINFO. */
1594 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1595 enum arm_reg_type
*rtype
,
1596 struct neon_typed_alias
*typeinfo
)
1599 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1600 struct neon_typed_alias atype
;
1601 struct neon_type_el parsetype
;
1605 atype
.eltype
.type
= NT_invtype
;
1606 atype
.eltype
.size
= -1;
1608 /* Try alternate syntax for some types of register. Note these are mutually
1609 exclusive with the Neon syntax extensions. */
1612 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1620 /* Undo polymorphism when a set of register types may be accepted. */
1621 if ((type
== REG_TYPE_NDQ
1622 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1623 || (type
== REG_TYPE_VFSD
1624 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1625 || (type
== REG_TYPE_NSDQ
1626 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1627 || reg
->type
== REG_TYPE_NQ
))
1628 || (type
== REG_TYPE_NSD
1629 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1630 || (type
== REG_TYPE_MMXWC
1631 && (reg
->type
== REG_TYPE_MMXWCG
)))
1632 type
= (enum arm_reg_type
) reg
->type
;
1634 if (type
== REG_TYPE_MQ
)
1636 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1639 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1642 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1644 first_error (_("expected MVE register [q0..q7]"));
1649 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1650 && (type
== REG_TYPE_NQ
))
1654 if (type
!= reg
->type
)
1660 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1662 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1664 first_error (_("can't redefine type for operand"));
1667 atype
.defined
|= NTA_HASTYPE
;
1668 atype
.eltype
= parsetype
;
1671 if (skip_past_char (&str
, '[') == SUCCESS
)
1673 if (type
!= REG_TYPE_VFD
1674 && !(type
== REG_TYPE_VFS
1675 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1676 && !(type
== REG_TYPE_NQ
1677 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1679 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1680 first_error (_("only D and Q registers may be indexed"));
1682 first_error (_("only D registers may be indexed"));
1686 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1688 first_error (_("can't change index for operand"));
1692 atype
.defined
|= NTA_HASINDEX
;
1694 if (skip_past_char (&str
, ']') == SUCCESS
)
1695 atype
.index
= NEON_ALL_LANES
;
1700 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1702 if (exp
.X_op
!= O_constant
)
1704 first_error (_("constant expression required"));
1708 if (skip_past_char (&str
, ']') == FAIL
)
1711 atype
.index
= exp
.X_add_number
;
1726 /* Like arm_reg_parse, but also allow the following extra features:
1727 - If RTYPE is non-zero, return the (possibly restricted) type of the
1728 register (e.g. Neon double or quad reg when either has been requested).
1729 - If this is a Neon vector type with additional type information, fill
1730 in the struct pointed to by VECTYPE (if non-NULL).
1731 This function will fault on encountering a scalar. */
1734 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1735 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1737 struct neon_typed_alias atype
;
1739 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1744 /* Do not allow regname(... to parse as a register. */
1748 /* Do not allow a scalar (reg+index) to parse as a register. */
1749 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1751 first_error (_("register operand expected, but got scalar"));
1756 *vectype
= atype
.eltype
;
1763 #define NEON_SCALAR_REG(X) ((X) >> 4)
1764 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1766 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1767 have enough information to be able to do a good job bounds-checking. So, we
1768 just do easy checks here, and do further checks later. */
1771 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1772 arm_reg_type reg_type
)
1776 struct neon_typed_alias atype
;
1779 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1797 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1800 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1802 first_error (_("scalar must have an index"));
1805 else if (atype
.index
>= reg_size
/ elsize
)
1807 first_error (_("scalar index out of range"));
1812 *type
= atype
.eltype
;
1816 return reg
* 16 + atype
.index
;
1819 /* Types of registers in a list. */
1832 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1835 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1841 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1843 /* We come back here if we get ranges concatenated by '+' or '|'. */
1846 skip_whitespace (str
);
1859 const char apsr_str
[] = "apsr";
1860 int apsr_str_len
= strlen (apsr_str
);
1862 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1863 if (etype
== REGLIST_CLRM
)
1865 if (reg
== REG_SP
|| reg
== REG_PC
)
1867 else if (reg
== FAIL
1868 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1869 && !ISALPHA (*(str
+ apsr_str_len
)))
1872 str
+= apsr_str_len
;
1877 first_error (_("r0-r12, lr or APSR expected"));
1881 else /* etype == REGLIST_RN. */
1885 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1896 first_error (_("bad range in register list"));
1900 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1902 if (range
& (1 << i
))
1904 (_("Warning: duplicated register (r%d) in register list"),
1912 if (range
& (1 << reg
))
1913 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1915 else if (reg
<= cur_reg
)
1916 as_tsktsk (_("Warning: register range not in ascending order"));
1921 while (skip_past_comma (&str
) != FAIL
1922 || (in_range
= 1, *str
++ == '-'));
1925 if (skip_past_char (&str
, '}') == FAIL
)
1927 first_error (_("missing `}'"));
1931 else if (etype
== REGLIST_RN
)
1935 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1938 if (exp
.X_op
== O_constant
)
1940 if (exp
.X_add_number
1941 != (exp
.X_add_number
& 0x0000ffff))
1943 inst
.error
= _("invalid register mask");
1947 if ((range
& exp
.X_add_number
) != 0)
1949 int regno
= range
& exp
.X_add_number
;
1952 regno
= (1 << regno
) - 1;
1954 (_("Warning: duplicated register (r%d) in register list"),
1958 range
|= exp
.X_add_number
;
1962 if (inst
.relocs
[0].type
!= 0)
1964 inst
.error
= _("expression too complex");
1968 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1969 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1970 inst
.relocs
[0].pc_rel
= 0;
1974 if (*str
== '|' || *str
== '+')
1980 while (another_range
);
1986 /* Parse a VFP register list. If the string is invalid return FAIL.
1987 Otherwise return the number of registers, and set PBASE to the first
1988 register. Parses registers of type ETYPE.
1989 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1990 - Q registers can be used to specify pairs of D registers
1991 - { } can be omitted from around a singleton register list
1992 FIXME: This is not implemented, as it would require backtracking in
1995 This could be done (the meaning isn't really ambiguous), but doesn't
1996 fit in well with the current parsing framework.
1997 - 32 D registers may be used (also true for VFPv3).
1998 FIXME: Types are ignored in these register lists, which is probably a
2002 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2003 bfd_boolean
*partial_match
)
2008 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2012 unsigned long mask
= 0;
2014 bfd_boolean vpr_seen
= FALSE
;
2015 bfd_boolean expect_vpr
=
2016 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2018 if (skip_past_char (&str
, '{') == FAIL
)
2020 inst
.error
= _("expecting {");
2027 case REGLIST_VFP_S_VPR
:
2028 regtype
= REG_TYPE_VFS
;
2033 case REGLIST_VFP_D_VPR
:
2034 regtype
= REG_TYPE_VFD
;
2037 case REGLIST_NEON_D
:
2038 regtype
= REG_TYPE_NDQ
;
2045 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2047 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2052 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2055 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2062 base_reg
= max_regs
;
2063 *partial_match
= FALSE
;
2067 int setmask
= 1, addregs
= 1;
2068 const char vpr_str
[] = "vpr";
2069 int vpr_str_len
= strlen (vpr_str
);
2071 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2075 if (new_base
== FAIL
2076 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2077 && !ISALPHA (*(str
+ vpr_str_len
))
2083 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2087 first_error (_("VPR expected last"));
2090 else if (new_base
== FAIL
)
2092 if (regtype
== REG_TYPE_VFS
)
2093 first_error (_("VFP single precision register or VPR "
2095 else /* regtype == REG_TYPE_VFD. */
2096 first_error (_("VFP/Neon double precision register or VPR "
2101 else if (new_base
== FAIL
)
2103 first_error (_(reg_expected_msgs
[regtype
]));
2107 *partial_match
= TRUE
;
2111 if (new_base
>= max_regs
)
2113 first_error (_("register out of range in list"));
2117 /* Note: a value of 2 * n is returned for the register Q<n>. */
2118 if (regtype
== REG_TYPE_NQ
)
2124 if (new_base
< base_reg
)
2125 base_reg
= new_base
;
2127 if (mask
& (setmask
<< new_base
))
2129 first_error (_("invalid register list"));
2133 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2135 as_tsktsk (_("register list not in ascending order"));
2139 mask
|= setmask
<< new_base
;
2142 if (*str
== '-') /* We have the start of a range expression */
2148 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2151 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2155 if (high_range
>= max_regs
)
2157 first_error (_("register out of range in list"));
2161 if (regtype
== REG_TYPE_NQ
)
2162 high_range
= high_range
+ 1;
2164 if (high_range
<= new_base
)
2166 inst
.error
= _("register range not in ascending order");
2170 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2172 if (mask
& (setmask
<< new_base
))
2174 inst
.error
= _("invalid register list");
2178 mask
|= setmask
<< new_base
;
2183 while (skip_past_comma (&str
) != FAIL
);
2187 /* Sanity check -- should have raised a parse error above. */
2188 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2193 if (expect_vpr
&& !vpr_seen
)
2195 first_error (_("VPR expected last"));
2199 /* Final test -- the registers must be consecutive. */
2201 for (i
= 0; i
< count
; i
++)
2203 if ((mask
& (1u << i
)) == 0)
2205 inst
.error
= _("non-contiguous register range");
2215 /* True if two alias types are the same. */
2218 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2226 if (a
->defined
!= b
->defined
)
2229 if ((a
->defined
& NTA_HASTYPE
) != 0
2230 && (a
->eltype
.type
!= b
->eltype
.type
2231 || a
->eltype
.size
!= b
->eltype
.size
))
2234 if ((a
->defined
& NTA_HASINDEX
) != 0
2235 && (a
->index
!= b
->index
))
2241 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2242 The base register is put in *PBASE.
2243 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2245 The register stride (minus one) is put in bit 4 of the return value.
2246 Bits [6:5] encode the list length (minus one).
2247 The type of the list elements is put in *ELTYPE, if non-NULL. */
2249 #define NEON_LANE(X) ((X) & 0xf)
2250 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2251 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2254 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2256 struct neon_type_el
*eltype
)
2263 int leading_brace
= 0;
2264 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2265 const char *const incr_error
= mve
? _("register stride must be 1") :
2266 _("register stride must be 1 or 2");
2267 const char *const type_error
= _("mismatched element/structure types in list");
2268 struct neon_typed_alias firsttype
;
2269 firsttype
.defined
= 0;
2270 firsttype
.eltype
.type
= NT_invtype
;
2271 firsttype
.eltype
.size
= -1;
2272 firsttype
.index
= -1;
2274 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2279 struct neon_typed_alias atype
;
2281 rtype
= REG_TYPE_MQ
;
2282 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2286 first_error (_(reg_expected_msgs
[rtype
]));
2293 if (rtype
== REG_TYPE_NQ
)
2299 else if (reg_incr
== -1)
2301 reg_incr
= getreg
- base_reg
;
2302 if (reg_incr
< 1 || reg_incr
> 2)
2304 first_error (_(incr_error
));
2308 else if (getreg
!= base_reg
+ reg_incr
* count
)
2310 first_error (_(incr_error
));
2314 if (! neon_alias_types_same (&atype
, &firsttype
))
2316 first_error (_(type_error
));
2320 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2324 struct neon_typed_alias htype
;
2325 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2327 lane
= NEON_INTERLEAVE_LANES
;
2328 else if (lane
!= NEON_INTERLEAVE_LANES
)
2330 first_error (_(type_error
));
2335 else if (reg_incr
!= 1)
2337 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2341 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2344 first_error (_(reg_expected_msgs
[rtype
]));
2347 if (! neon_alias_types_same (&htype
, &firsttype
))
2349 first_error (_(type_error
));
2352 count
+= hireg
+ dregs
- getreg
;
2356 /* If we're using Q registers, we can't use [] or [n] syntax. */
2357 if (rtype
== REG_TYPE_NQ
)
2363 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2367 else if (lane
!= atype
.index
)
2369 first_error (_(type_error
));
2373 else if (lane
== -1)
2374 lane
= NEON_INTERLEAVE_LANES
;
2375 else if (lane
!= NEON_INTERLEAVE_LANES
)
2377 first_error (_(type_error
));
2382 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2384 /* No lane set by [x]. We must be interleaving structures. */
2386 lane
= NEON_INTERLEAVE_LANES
;
2389 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2390 || (count
> 1 && reg_incr
== -1))
2392 first_error (_("error parsing element/structure list"));
2396 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2398 first_error (_("expected }"));
2406 *eltype
= firsttype
.eltype
;
2411 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2414 /* Parse an explicit relocation suffix on an expression. This is
2415 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2416 arm_reloc_hsh contains no entries, so this function can only
2417 succeed if there is no () after the word. Returns -1 on error,
2418 BFD_RELOC_UNUSED if there wasn't any suffix. */
2421 parse_reloc (char **str
)
2423 struct reloc_entry
*r
;
2427 return BFD_RELOC_UNUSED
;
2432 while (*q
&& *q
!= ')' && *q
!= ',')
2437 if ((r
= (struct reloc_entry
*)
2438 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2445 /* Directives: register aliases. */
2447 static struct reg_entry
*
2448 insert_reg_alias (char *str
, unsigned number
, int type
)
2450 struct reg_entry
*new_reg
;
2453 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2455 if (new_reg
->builtin
)
2456 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2458 /* Only warn about a redefinition if it's not defined as the
2460 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2461 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2466 name
= xstrdup (str
);
2467 new_reg
= XNEW (struct reg_entry
);
2469 new_reg
->name
= name
;
2470 new_reg
->number
= number
;
2471 new_reg
->type
= type
;
2472 new_reg
->builtin
= FALSE
;
2473 new_reg
->neon
= NULL
;
2475 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2482 insert_neon_reg_alias (char *str
, int number
, int type
,
2483 struct neon_typed_alias
*atype
)
2485 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2489 first_error (_("attempt to redefine typed alias"));
2495 reg
->neon
= XNEW (struct neon_typed_alias
);
2496 *reg
->neon
= *atype
;
2500 /* Look for the .req directive. This is of the form:
2502 new_register_name .req existing_register_name
2504 If we find one, or if it looks sufficiently like one that we want to
2505 handle any error here, return TRUE. Otherwise return FALSE. */
2508 create_register_alias (char * newname
, char *p
)
2510 struct reg_entry
*old
;
2511 char *oldname
, *nbuf
;
2514 /* The input scrubber ensures that whitespace after the mnemonic is
2515 collapsed to single spaces. */
2517 if (strncmp (oldname
, " .req ", 6) != 0)
2521 if (*oldname
== '\0')
2524 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2527 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2531 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2532 the desired alias name, and p points to its end. If not, then
2533 the desired alias name is in the global original_case_string. */
2534 #ifdef TC_CASE_SENSITIVE
2537 newname
= original_case_string
;
2538 nlen
= strlen (newname
);
2541 nbuf
= xmemdup0 (newname
, nlen
);
2543 /* Create aliases under the new name as stated; an all-lowercase
2544 version of the new name; and an all-uppercase version of the new
2546 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2548 for (p
= nbuf
; *p
; p
++)
2551 if (strncmp (nbuf
, newname
, nlen
))
2553 /* If this attempt to create an additional alias fails, do not bother
2554 trying to create the all-lower case alias. We will fail and issue
2555 a second, duplicate error message. This situation arises when the
2556 programmer does something like:
2559 The second .req creates the "Foo" alias but then fails to create
2560 the artificial FOO alias because it has already been created by the
2562 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2569 for (p
= nbuf
; *p
; p
++)
2572 if (strncmp (nbuf
, newname
, nlen
))
2573 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2580 /* Create a Neon typed/indexed register alias using directives, e.g.:
2585 These typed registers can be used instead of the types specified after the
2586 Neon mnemonic, so long as all operands given have types. Types can also be
2587 specified directly, e.g.:
2588 vadd d0.s32, d1.s32, d2.s32 */
2591 create_neon_reg_alias (char *newname
, char *p
)
2593 enum arm_reg_type basetype
;
2594 struct reg_entry
*basereg
;
2595 struct reg_entry mybasereg
;
2596 struct neon_type ntype
;
2597 struct neon_typed_alias typeinfo
;
2598 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2601 typeinfo
.defined
= 0;
2602 typeinfo
.eltype
.type
= NT_invtype
;
2603 typeinfo
.eltype
.size
= -1;
2604 typeinfo
.index
= -1;
2608 if (strncmp (p
, " .dn ", 5) == 0)
2609 basetype
= REG_TYPE_VFD
;
2610 else if (strncmp (p
, " .qn ", 5) == 0)
2611 basetype
= REG_TYPE_NQ
;
2620 basereg
= arm_reg_parse_multi (&p
);
2622 if (basereg
&& basereg
->type
!= basetype
)
2624 as_bad (_("bad type for register"));
2628 if (basereg
== NULL
)
2631 /* Try parsing as an integer. */
2632 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2633 if (exp
.X_op
!= O_constant
)
2635 as_bad (_("expression must be constant"));
2638 basereg
= &mybasereg
;
2639 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2645 typeinfo
= *basereg
->neon
;
2647 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2649 /* We got a type. */
2650 if (typeinfo
.defined
& NTA_HASTYPE
)
2652 as_bad (_("can't redefine the type of a register alias"));
2656 typeinfo
.defined
|= NTA_HASTYPE
;
2657 if (ntype
.elems
!= 1)
2659 as_bad (_("you must specify a single type only"));
2662 typeinfo
.eltype
= ntype
.el
[0];
2665 if (skip_past_char (&p
, '[') == SUCCESS
)
2668 /* We got a scalar index. */
2670 if (typeinfo
.defined
& NTA_HASINDEX
)
2672 as_bad (_("can't redefine the index of a scalar alias"));
2676 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2678 if (exp
.X_op
!= O_constant
)
2680 as_bad (_("scalar index must be constant"));
2684 typeinfo
.defined
|= NTA_HASINDEX
;
2685 typeinfo
.index
= exp
.X_add_number
;
2687 if (skip_past_char (&p
, ']') == FAIL
)
2689 as_bad (_("expecting ]"));
2694 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2695 the desired alias name, and p points to its end. If not, then
2696 the desired alias name is in the global original_case_string. */
2697 #ifdef TC_CASE_SENSITIVE
2698 namelen
= nameend
- newname
;
2700 newname
= original_case_string
;
2701 namelen
= strlen (newname
);
2704 namebuf
= xmemdup0 (newname
, namelen
);
2706 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2707 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2709 /* Insert name in all uppercase. */
2710 for (p
= namebuf
; *p
; p
++)
2713 if (strncmp (namebuf
, newname
, namelen
))
2714 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2715 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2717 /* Insert name in all lowercase. */
2718 for (p
= namebuf
; *p
; p
++)
2721 if (strncmp (namebuf
, newname
, namelen
))
2722 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2723 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2729 /* Should never be called, as .req goes between the alias and the
2730 register name, not at the beginning of the line. */
2733 s_req (int a ATTRIBUTE_UNUSED
)
2735 as_bad (_("invalid syntax for .req directive"));
2739 s_dn (int a ATTRIBUTE_UNUSED
)
2741 as_bad (_("invalid syntax for .dn directive"));
2745 s_qn (int a ATTRIBUTE_UNUSED
)
2747 as_bad (_("invalid syntax for .qn directive"));
2750 /* The .unreq directive deletes an alias which was previously defined
2751 by .req. For example:
2757 s_unreq (int a ATTRIBUTE_UNUSED
)
2762 name
= input_line_pointer
;
2764 while (*input_line_pointer
!= 0
2765 && *input_line_pointer
!= ' '
2766 && *input_line_pointer
!= '\n')
2767 ++input_line_pointer
;
2769 saved_char
= *input_line_pointer
;
2770 *input_line_pointer
= 0;
2773 as_bad (_("invalid syntax for .unreq directive"));
2776 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2780 as_bad (_("unknown register alias '%s'"), name
);
2781 else if (reg
->builtin
)
2782 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2789 hash_delete (arm_reg_hsh
, name
, FALSE
);
2790 free ((char *) reg
->name
);
2795 /* Also locate the all upper case and all lower case versions.
2796 Do not complain if we cannot find one or the other as it
2797 was probably deleted above. */
2799 nbuf
= strdup (name
);
2800 for (p
= nbuf
; *p
; p
++)
2802 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2805 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2806 free ((char *) reg
->name
);
2812 for (p
= nbuf
; *p
; p
++)
2814 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2817 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2818 free ((char *) reg
->name
);
2828 *input_line_pointer
= saved_char
;
2829 demand_empty_rest_of_line ();
2832 /* Directives: Instruction set selection. */
2835 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2836 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2837 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2838 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2840 /* Create a new mapping symbol for the transition to STATE. */
2843 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2846 const char * symname
;
2853 type
= BSF_NO_FLAGS
;
2857 type
= BSF_NO_FLAGS
;
2861 type
= BSF_NO_FLAGS
;
2867 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2868 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2873 THUMB_SET_FUNC (symbolP
, 0);
2874 ARM_SET_THUMB (symbolP
, 0);
2875 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 THUMB_SET_FUNC (symbolP
, 1);
2880 ARM_SET_THUMB (symbolP
, 1);
2881 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2889 /* Save the mapping symbols for future reference. Also check that
2890 we do not place two mapping symbols at the same offset within a
2891 frag. We'll handle overlap between frags in
2892 check_mapping_symbols.
2894 If .fill or other data filling directive generates zero sized data,
2895 the mapping symbol for the following code will have the same value
2896 as the one generated for the data filling directive. In this case,
2897 we replace the old symbol with the new one at the same address. */
2900 if (frag
->tc_frag_data
.first_map
!= NULL
)
2902 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2903 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2905 frag
->tc_frag_data
.first_map
= symbolP
;
2907 if (frag
->tc_frag_data
.last_map
!= NULL
)
2909 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2910 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2911 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2913 frag
->tc_frag_data
.last_map
= symbolP
;
2916 /* We must sometimes convert a region marked as code to data during
2917 code alignment, if an odd number of bytes have to be padded. The
2918 code mapping symbol is pushed to an aligned address. */
2921 insert_data_mapping_symbol (enum mstate state
,
2922 valueT value
, fragS
*frag
, offsetT bytes
)
2924 /* If there was already a mapping symbol, remove it. */
2925 if (frag
->tc_frag_data
.last_map
!= NULL
2926 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2928 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2932 know (frag
->tc_frag_data
.first_map
== symp
);
2933 frag
->tc_frag_data
.first_map
= NULL
;
2935 frag
->tc_frag_data
.last_map
= NULL
;
2936 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2939 make_mapping_symbol (MAP_DATA
, value
, frag
);
2940 make_mapping_symbol (state
, value
+ bytes
, frag
);
2943 static void mapping_state_2 (enum mstate state
, int max_chars
);
2945 /* Set the mapping state to STATE. Only call this when about to
2946 emit some STATE bytes to the file. */
2948 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2950 mapping_state (enum mstate state
)
2952 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2954 if (mapstate
== state
)
2955 /* The mapping symbol has already been emitted.
2956 There is nothing else to do. */
2959 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2961 All ARM instructions require 4-byte alignment.
2962 (Almost) all Thumb instructions require 2-byte alignment.
2964 When emitting instructions into any section, mark the section
2967 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2968 but themselves require 2-byte alignment; this applies to some
2969 PC- relative forms. However, these cases will involve implicit
2970 literal pool generation or an explicit .align >=2, both of
2971 which will cause the section to me marked with sufficient
2972 alignment. Thus, we don't handle those cases here. */
2973 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2975 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2976 /* This case will be evaluated later. */
2979 mapping_state_2 (state
, 0);
2982 /* Same as mapping_state, but MAX_CHARS bytes have already been
2983 allocated. Put the mapping symbol that far back. */
2986 mapping_state_2 (enum mstate state
, int max_chars
)
2988 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2990 if (!SEG_NORMAL (now_seg
))
2993 if (mapstate
== state
)
2994 /* The mapping symbol has already been emitted.
2995 There is nothing else to do. */
2998 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2999 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3001 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3002 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3005 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3008 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3009 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3013 #define mapping_state(x) ((void)0)
3014 #define mapping_state_2(x, y) ((void)0)
3017 /* Find the real, Thumb encoded start of a Thumb function. */
3021 find_real_start (symbolS
* symbolP
)
3024 const char * name
= S_GET_NAME (symbolP
);
3025 symbolS
* new_target
;
3027 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3028 #define STUB_NAME ".real_start_of"
3033 /* The compiler may generate BL instructions to local labels because
3034 it needs to perform a branch to a far away location. These labels
3035 do not have a corresponding ".real_start_of" label. We check
3036 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3037 the ".real_start_of" convention for nonlocal branches. */
3038 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3041 real_start
= concat (STUB_NAME
, name
, NULL
);
3042 new_target
= symbol_find (real_start
);
3045 if (new_target
== NULL
)
3047 as_warn (_("Failed to find real start of function: %s\n"), name
);
3048 new_target
= symbolP
;
3056 opcode_select (int width
)
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3064 as_bad (_("selected processor does not support THUMB opcodes"));
3067 /* No need to force the alignment, since we will have been
3068 coming from ARM mode, which is word-aligned. */
3069 record_alignment (now_seg
, 1);
3076 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3077 as_bad (_("selected processor does not support ARM opcodes"));
3082 frag_align (2, 0, 0);
3084 record_alignment (now_seg
, 1);
3089 as_bad (_("invalid instruction size selected (%d)"), width
);
3094 s_arm (int ignore ATTRIBUTE_UNUSED
)
3097 demand_empty_rest_of_line ();
3101 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3104 demand_empty_rest_of_line ();
3108 s_code (int unused ATTRIBUTE_UNUSED
)
3112 temp
= get_absolute_expression ();
3117 opcode_select (temp
);
3121 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3126 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3128 /* If we are not already in thumb mode go into it, EVEN if
3129 the target processor does not support thumb instructions.
3130 This is used by gcc/config/arm/lib1funcs.asm for example
3131 to compile interworking support functions even if the
3132 target processor should not support interworking. */
3136 record_alignment (now_seg
, 1);
3139 demand_empty_rest_of_line ();
3143 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3147 /* The following label is the name/address of the start of a Thumb function.
3148 We need to know this for the interworking support. */
3149 label_is_thumb_function_name
= TRUE
;
3152 /* Perform a .set directive, but also mark the alias as
3153 being a thumb function. */
3156 s_thumb_set (int equiv
)
3158 /* XXX the following is a duplicate of the code for s_set() in read.c
3159 We cannot just call that code as we need to get at the symbol that
3166 /* Especial apologies for the random logic:
3167 This just grew, and could be parsed much more simply!
3169 delim
= get_symbol_name (& name
);
3170 end_name
= input_line_pointer
;
3171 (void) restore_line_pointer (delim
);
3173 if (*input_line_pointer
!= ',')
3176 as_bad (_("expected comma after name \"%s\""), name
);
3178 ignore_rest_of_line ();
3182 input_line_pointer
++;
3185 if (name
[0] == '.' && name
[1] == '\0')
3187 /* XXX - this should not happen to .thumb_set. */
3191 if ((symbolP
= symbol_find (name
)) == NULL
3192 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3195 /* When doing symbol listings, play games with dummy fragments living
3196 outside the normal fragment chain to record the file and line info
3198 if (listing
& LISTING_SYMBOLS
)
3200 extern struct list_info_struct
* listing_tail
;
3201 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3203 memset (dummy_frag
, 0, sizeof (fragS
));
3204 dummy_frag
->fr_type
= rs_fill
;
3205 dummy_frag
->line
= listing_tail
;
3206 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3207 dummy_frag
->fr_symbol
= symbolP
;
3211 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3214 /* "set" symbols are local unless otherwise specified. */
3215 SF_SET_LOCAL (symbolP
);
3216 #endif /* OBJ_COFF */
3217 } /* Make a new symbol. */
3219 symbol_table_insert (symbolP
);
3224 && S_IS_DEFINED (symbolP
)
3225 && S_GET_SEGMENT (symbolP
) != reg_section
)
3226 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3228 pseudo_set (symbolP
);
3230 demand_empty_rest_of_line ();
3232 /* XXX Now we come to the Thumb specific bit of code. */
3234 THUMB_SET_FUNC (symbolP
, 1);
3235 ARM_SET_THUMB (symbolP
, 1);
3236 #if defined OBJ_ELF || defined OBJ_COFF
3237 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3241 /* Directives: Mode selection. */
3243 /* .syntax [unified|divided] - choose the new unified syntax
3244 (same for Arm and Thumb encoding, modulo slight differences in what
3245 can be represented) or the old divergent syntax for each mode. */
3247 s_syntax (int unused ATTRIBUTE_UNUSED
)
3251 delim
= get_symbol_name (& name
);
3253 if (!strcasecmp (name
, "unified"))
3254 unified_syntax
= TRUE
;
3255 else if (!strcasecmp (name
, "divided"))
3256 unified_syntax
= FALSE
;
3259 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3262 (void) restore_line_pointer (delim
);
3263 demand_empty_rest_of_line ();
3266 /* Directives: sectioning and alignment. */
3269 s_bss (int ignore ATTRIBUTE_UNUSED
)
3271 /* We don't support putting frags in the BSS segment, we fake it by
3272 marking in_bss, then looking at s_skip for clues. */
3273 subseg_set (bss_section
, 0);
3274 demand_empty_rest_of_line ();
3276 #ifdef md_elf_section_change_hook
3277 md_elf_section_change_hook ();
3282 s_even (int ignore ATTRIBUTE_UNUSED
)
3284 /* Never make frag if expect extra pass. */
3286 frag_align (1, 0, 0);
3288 record_alignment (now_seg
, 1);
3290 demand_empty_rest_of_line ();
3293 /* Directives: CodeComposer Studio. */
3295 /* .ref (for CodeComposer Studio syntax only). */
3297 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3299 if (codecomposer_syntax
)
3300 ignore_rest_of_line ();
3302 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3305 /* If name is not NULL, then it is used for marking the beginning of a
3306 function, whereas if it is NULL then it means the function end. */
3308 asmfunc_debug (const char * name
)
3310 static const char * last_name
= NULL
;
3314 gas_assert (last_name
== NULL
);
3317 if (debug_type
== DEBUG_STABS
)
3318 stabs_generate_asm_func (name
, name
);
3322 gas_assert (last_name
!= NULL
);
3324 if (debug_type
== DEBUG_STABS
)
3325 stabs_generate_asm_endfunc (last_name
, last_name
);
3332 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3334 if (codecomposer_syntax
)
3336 switch (asmfunc_state
)
3338 case OUTSIDE_ASMFUNC
:
3339 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3342 case WAITING_ASMFUNC_NAME
:
3343 as_bad (_(".asmfunc repeated."));
3346 case WAITING_ENDASMFUNC
:
3347 as_bad (_(".asmfunc without function."));
3350 demand_empty_rest_of_line ();
3353 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3357 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3359 if (codecomposer_syntax
)
3361 switch (asmfunc_state
)
3363 case OUTSIDE_ASMFUNC
:
3364 as_bad (_(".endasmfunc without a .asmfunc."));
3367 case WAITING_ASMFUNC_NAME
:
3368 as_bad (_(".endasmfunc without function."));
3371 case WAITING_ENDASMFUNC
:
3372 asmfunc_state
= OUTSIDE_ASMFUNC
;
3373 asmfunc_debug (NULL
);
3376 demand_empty_rest_of_line ();
3379 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3383 s_ccs_def (int name
)
3385 if (codecomposer_syntax
)
3388 as_bad (_(".def pseudo-op only available with -mccs flag."));
3391 /* Directives: Literal pools. */
3393 static literal_pool
*
3394 find_literal_pool (void)
3396 literal_pool
* pool
;
3398 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3400 if (pool
->section
== now_seg
3401 && pool
->sub_section
== now_subseg
)
3408 static literal_pool
*
3409 find_or_make_literal_pool (void)
3411 /* Next literal pool ID number. */
3412 static unsigned int latest_pool_num
= 1;
3413 literal_pool
* pool
;
3415 pool
= find_literal_pool ();
3419 /* Create a new pool. */
3420 pool
= XNEW (literal_pool
);
3424 pool
->next_free_entry
= 0;
3425 pool
->section
= now_seg
;
3426 pool
->sub_section
= now_subseg
;
3427 pool
->next
= list_of_pools
;
3428 pool
->symbol
= NULL
;
3429 pool
->alignment
= 2;
3431 /* Add it to the list. */
3432 list_of_pools
= pool
;
3435 /* New pools, and emptied pools, will have a NULL symbol. */
3436 if (pool
->symbol
== NULL
)
3438 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3439 (valueT
) 0, &zero_address_frag
);
3440 pool
->id
= latest_pool_num
++;
3447 /* Add the literal in the global 'inst'
3448 structure to the relevant literal pool. */
3451 add_to_lit_pool (unsigned int nbytes
)
3453 #define PADDING_SLOT 0x1
3454 #define LIT_ENTRY_SIZE_MASK 0xFF
3455 literal_pool
* pool
;
3456 unsigned int entry
, pool_size
= 0;
3457 bfd_boolean padding_slot_p
= FALSE
;
3463 imm1
= inst
.operands
[1].imm
;
3464 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3465 : inst
.relocs
[0].exp
.X_unsigned
? 0
3466 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3467 if (target_big_endian
)
3470 imm2
= inst
.operands
[1].imm
;
3474 pool
= find_or_make_literal_pool ();
3476 /* Check if this literal value is already in the pool. */
3477 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3481 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3482 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3483 && (pool
->literals
[entry
].X_add_number
3484 == inst
.relocs
[0].exp
.X_add_number
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
)
3486 && (pool
->literals
[entry
].X_unsigned
3487 == inst
.relocs
[0].exp
.X_unsigned
))
3490 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3491 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3492 && (pool
->literals
[entry
].X_add_number
3493 == inst
.relocs
[0].exp
.X_add_number
)
3494 && (pool
->literals
[entry
].X_add_symbol
3495 == inst
.relocs
[0].exp
.X_add_symbol
)
3496 && (pool
->literals
[entry
].X_op_symbol
3497 == inst
.relocs
[0].exp
.X_op_symbol
)
3498 && (pool
->literals
[entry
].X_md
== nbytes
))
3501 else if ((nbytes
== 8)
3502 && !(pool_size
& 0x7)
3503 && ((entry
+ 1) != pool
->next_free_entry
)
3504 && (pool
->literals
[entry
].X_op
== O_constant
)
3505 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3506 && (pool
->literals
[entry
].X_unsigned
3507 == inst
.relocs
[0].exp
.X_unsigned
)
3508 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3509 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3510 && (pool
->literals
[entry
+ 1].X_unsigned
3511 == inst
.relocs
[0].exp
.X_unsigned
))
3514 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3515 if (padding_slot_p
&& (nbytes
== 4))
3521 /* Do we need to create a new entry? */
3522 if (entry
== pool
->next_free_entry
)
3524 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3526 inst
.error
= _("literal pool overflow");
3532 /* For 8-byte entries, we align to an 8-byte boundary,
3533 and split it into two 4-byte entries, because on 32-bit
3534 host, 8-byte constants are treated as big num, thus
3535 saved in "generic_bignum" which will be overwritten
3536 by later assignments.
3538 We also need to make sure there is enough space for
3541 We also check to make sure the literal operand is a
3543 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3544 || inst
.relocs
[0].exp
.X_op
== O_big
))
3546 inst
.error
= _("invalid type for literal pool");
3549 else if (pool_size
& 0x7)
3551 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= 0;
3560 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3561 pool
->next_free_entry
+= 1;
3564 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3566 inst
.error
= _("literal pool overflow");
3570 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3571 pool
->literals
[entry
].X_op
= O_constant
;
3572 pool
->literals
[entry
].X_add_number
= imm1
;
3573 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3574 pool
->literals
[entry
++].X_md
= 4;
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_op
= O_constant
;
3577 pool
->literals
[entry
].X_add_number
= imm2
;
3578 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3579 pool
->literals
[entry
].X_md
= 4;
3580 pool
->alignment
= 3;
3581 pool
->next_free_entry
+= 1;
3585 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3586 pool
->literals
[entry
].X_md
= 4;
3590 /* PR ld/12974: Record the location of the first source line to reference
3591 this entry in the literal pool. If it turns out during linking that the
3592 symbol does not exist we will be able to give an accurate line number for
3593 the (first use of the) missing reference. */
3594 if (debug_type
== DEBUG_DWARF2
)
3595 dwarf2_where (pool
->locs
+ entry
);
3597 pool
->next_free_entry
+= 1;
3599 else if (padding_slot_p
)
3601 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3602 pool
->literals
[entry
].X_md
= nbytes
;
3605 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3606 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3607 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3613 tc_start_label_without_colon (void)
3615 bfd_boolean ret
= TRUE
;
3617 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3619 const char *label
= input_line_pointer
;
3621 while (!is_end_of_line
[(int) label
[-1]])
3626 as_bad (_("Invalid label '%s'"), label
);
3630 asmfunc_debug (label
);
3632 asmfunc_state
= WAITING_ENDASMFUNC
;
3638 /* Can't use symbol_new here, so have to create a symbol and then at
3639 a later date assign it a value. That's what these functions do. */
3642 symbol_locate (symbolS
* symbolP
,
3643 const char * name
, /* It is copied, the caller can modify. */
3644 segT segment
, /* Segment identifier (SEG_<something>). */
3645 valueT valu
, /* Symbol value. */
3646 fragS
* frag
) /* Associated fragment. */
3649 char * preserved_copy_of_name
;
3651 name_length
= strlen (name
) + 1; /* +1 for \0. */
3652 obstack_grow (¬es
, name
, name_length
);
3653 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3655 #ifdef tc_canonicalize_symbol_name
3656 preserved_copy_of_name
=
3657 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3660 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3662 S_SET_SEGMENT (symbolP
, segment
);
3663 S_SET_VALUE (symbolP
, valu
);
3664 symbol_clear_list_pointers (symbolP
);
3666 symbol_set_frag (symbolP
, frag
);
3668 /* Link to end of symbol chain. */
3670 extern int symbol_table_frozen
;
3672 if (symbol_table_frozen
)
3676 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3678 obj_symbol_new_hook (symbolP
);
3680 #ifdef tc_symbol_new_hook
3681 tc_symbol_new_hook (symbolP
);
3685 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3686 #endif /* DEBUG_SYMS */
3690 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3693 literal_pool
* pool
;
3696 pool
= find_literal_pool ();
3698 || pool
->symbol
== NULL
3699 || pool
->next_free_entry
== 0)
3702 /* Align pool as you have word accesses.
3703 Only make a frag if we have to. */
3705 frag_align (pool
->alignment
, 0, 0);
3707 record_alignment (now_seg
, 2);
3710 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3711 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3713 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3715 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3716 (valueT
) frag_now_fix (), frag_now
);
3717 symbol_table_insert (pool
->symbol
);
3719 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3721 #if defined OBJ_COFF || defined OBJ_ELF
3722 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3725 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3728 if (debug_type
== DEBUG_DWARF2
)
3729 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3731 /* First output the expression in the instruction to the pool. */
3732 emit_expr (&(pool
->literals
[entry
]),
3733 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3736 /* Mark the pool as empty. */
3737 pool
->next_free_entry
= 0;
3738 pool
->symbol
= NULL
;
3742 /* Forward declarations for functions below, in the MD interface
3744 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3745 static valueT
create_unwind_entry (int);
3746 static void start_unwind_section (const segT
, int);
3747 static void add_unwind_opcode (valueT
, int);
3748 static void flush_pending_unwind (void);
3750 /* Directives: Data. */
3753 s_arm_elf_cons (int nbytes
)
3757 #ifdef md_flush_pending_output
3758 md_flush_pending_output ();
3761 if (is_it_end_of_statement ())
3763 demand_empty_rest_of_line ();
3767 #ifdef md_cons_align
3768 md_cons_align (nbytes
);
3771 mapping_state (MAP_DATA
);
3775 char *base
= input_line_pointer
;
3779 if (exp
.X_op
!= O_symbol
)
3780 emit_expr (&exp
, (unsigned int) nbytes
);
3783 char *before_reloc
= input_line_pointer
;
3784 reloc
= parse_reloc (&input_line_pointer
);
3787 as_bad (_("unrecognized relocation suffix"));
3788 ignore_rest_of_line ();
3791 else if (reloc
== BFD_RELOC_UNUSED
)
3792 emit_expr (&exp
, (unsigned int) nbytes
);
3795 reloc_howto_type
*howto
= (reloc_howto_type
*)
3796 bfd_reloc_type_lookup (stdoutput
,
3797 (bfd_reloc_code_real_type
) reloc
);
3798 int size
= bfd_get_reloc_size (howto
);
3800 if (reloc
== BFD_RELOC_ARM_PLT32
)
3802 as_bad (_("(plt) is only valid on branch targets"));
3803 reloc
= BFD_RELOC_UNUSED
;
3808 as_bad (ngettext ("%s relocations do not fit in %d byte",
3809 "%s relocations do not fit in %d bytes",
3811 howto
->name
, nbytes
);
3814 /* We've parsed an expression stopping at O_symbol.
3815 But there may be more expression left now that we
3816 have parsed the relocation marker. Parse it again.
3817 XXX Surely there is a cleaner way to do this. */
3818 char *p
= input_line_pointer
;
3820 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3822 memcpy (save_buf
, base
, input_line_pointer
- base
);
3823 memmove (base
+ (input_line_pointer
- before_reloc
),
3824 base
, before_reloc
- base
);
3826 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3828 memcpy (base
, save_buf
, p
- base
);
3830 offset
= nbytes
- size
;
3831 p
= frag_more (nbytes
);
3832 memset (p
, 0, nbytes
);
3833 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3834 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3840 while (*input_line_pointer
++ == ',');
3842 /* Put terminator back into stream. */
3843 input_line_pointer
--;
3844 demand_empty_rest_of_line ();
3847 /* Emit an expression containing a 32-bit thumb instruction.
3848 Implementation based on put_thumb32_insn. */
3851 emit_thumb32_expr (expressionS
* exp
)
3853 expressionS exp_high
= *exp
;
3855 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3856 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3857 exp
->X_add_number
&= 0xffff;
3858 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3861 /* Guess the instruction size based on the opcode. */
3864 thumb_insn_size (int opcode
)
3866 if ((unsigned int) opcode
< 0xe800u
)
3868 else if ((unsigned int) opcode
>= 0xe8000000u
)
3875 emit_insn (expressionS
*exp
, int nbytes
)
3879 if (exp
->X_op
== O_constant
)
3884 size
= thumb_insn_size (exp
->X_add_number
);
3888 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3890 as_bad (_(".inst.n operand too big. "\
3891 "Use .inst.w instead"));
3896 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3897 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3899 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3901 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3902 emit_thumb32_expr (exp
);
3904 emit_expr (exp
, (unsigned int) size
);
3906 it_fsm_post_encode ();
3910 as_bad (_("cannot determine Thumb instruction size. " \
3911 "Use .inst.n/.inst.w instead"));
3914 as_bad (_("constant expression required"));
3919 /* Like s_arm_elf_cons but do not use md_cons_align and
3920 set the mapping state to MAP_ARM/MAP_THUMB. */
3923 s_arm_elf_inst (int nbytes
)
3925 if (is_it_end_of_statement ())
3927 demand_empty_rest_of_line ();
3931 /* Calling mapping_state () here will not change ARM/THUMB,
3932 but will ensure not to be in DATA state. */
3935 mapping_state (MAP_THUMB
);
3940 as_bad (_("width suffixes are invalid in ARM mode"));
3941 ignore_rest_of_line ();
3947 mapping_state (MAP_ARM
);
3956 if (! emit_insn (& exp
, nbytes
))
3958 ignore_rest_of_line ();
3962 while (*input_line_pointer
++ == ',');
3964 /* Put terminator back into stream. */
3965 input_line_pointer
--;
3966 demand_empty_rest_of_line ();
3969 /* Parse a .rel31 directive. */
3972 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3979 if (*input_line_pointer
== '1')
3980 highbit
= 0x80000000;
3981 else if (*input_line_pointer
!= '0')
3982 as_bad (_("expected 0 or 1"));
3984 input_line_pointer
++;
3985 if (*input_line_pointer
!= ',')
3986 as_bad (_("missing comma"));
3987 input_line_pointer
++;
3989 #ifdef md_flush_pending_output
3990 md_flush_pending_output ();
3993 #ifdef md_cons_align
3997 mapping_state (MAP_DATA
);
4002 md_number_to_chars (p
, highbit
, 4);
4003 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4004 BFD_RELOC_ARM_PREL31
);
4006 demand_empty_rest_of_line ();
4009 /* Directives: AEABI stack-unwind tables. */
4011 /* Parse an unwind_fnstart directive. Simply records the current location. */
4014 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4016 demand_empty_rest_of_line ();
4017 if (unwind
.proc_start
)
4019 as_bad (_("duplicate .fnstart directive"));
4023 /* Mark the start of the function. */
4024 unwind
.proc_start
= expr_build_dot ();
4026 /* Reset the rest of the unwind info. */
4027 unwind
.opcode_count
= 0;
4028 unwind
.table_entry
= NULL
;
4029 unwind
.personality_routine
= NULL
;
4030 unwind
.personality_index
= -1;
4031 unwind
.frame_size
= 0;
4032 unwind
.fp_offset
= 0;
4033 unwind
.fp_reg
= REG_SP
;
4035 unwind
.sp_restored
= 0;
4039 /* Parse a handlerdata directive. Creates the exception handling table entry
4040 for the function. */
4043 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4045 demand_empty_rest_of_line ();
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 if (unwind
.table_entry
)
4050 as_bad (_("duplicate .handlerdata directive"));
4052 create_unwind_entry (1);
4055 /* Parse an unwind_fnend directive. Generates the index table entry. */
4058 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4063 unsigned int marked_pr_dependency
;
4065 demand_empty_rest_of_line ();
4067 if (!unwind
.proc_start
)
4069 as_bad (_(".fnend directive without .fnstart"));
4073 /* Add eh table entry. */
4074 if (unwind
.table_entry
== NULL
)
4075 val
= create_unwind_entry (0);
4079 /* Add index table entry. This is two words. */
4080 start_unwind_section (unwind
.saved_seg
, 1);
4081 frag_align (2, 0, 0);
4082 record_alignment (now_seg
, 2);
4084 ptr
= frag_more (8);
4086 where
= frag_now_fix () - 8;
4088 /* Self relative offset of the function start. */
4089 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4090 BFD_RELOC_ARM_PREL31
);
4092 /* Indicate dependency on EHABI-defined personality routines to the
4093 linker, if it hasn't been done already. */
4094 marked_pr_dependency
4095 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4096 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4097 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4099 static const char *const name
[] =
4101 "__aeabi_unwind_cpp_pr0",
4102 "__aeabi_unwind_cpp_pr1",
4103 "__aeabi_unwind_cpp_pr2"
4105 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4106 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4107 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4108 |= 1 << unwind
.personality_index
;
4112 /* Inline exception table entry. */
4113 md_number_to_chars (ptr
+ 4, val
, 4);
4115 /* Self relative offset of the table entry. */
4116 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4117 BFD_RELOC_ARM_PREL31
);
4119 /* Restore the original section. */
4120 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4122 unwind
.proc_start
= NULL
;
4126 /* Parse an unwind_cantunwind directive. */
4129 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4131 demand_empty_rest_of_line ();
4132 if (!unwind
.proc_start
)
4133 as_bad (MISSING_FNSTART
);
4135 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4136 as_bad (_("personality routine specified for cantunwind frame"));
4138 unwind
.personality_index
= -2;
4142 /* Parse a personalityindex directive. */
4145 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4149 if (!unwind
.proc_start
)
4150 as_bad (MISSING_FNSTART
);
4152 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4153 as_bad (_("duplicate .personalityindex directive"));
4157 if (exp
.X_op
!= O_constant
4158 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4160 as_bad (_("bad personality routine number"));
4161 ignore_rest_of_line ();
4165 unwind
.personality_index
= exp
.X_add_number
;
4167 demand_empty_rest_of_line ();
4171 /* Parse a personality directive. */
4174 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4178 if (!unwind
.proc_start
)
4179 as_bad (MISSING_FNSTART
);
4181 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4182 as_bad (_("duplicate .personality directive"));
4184 c
= get_symbol_name (& name
);
4185 p
= input_line_pointer
;
4187 ++ input_line_pointer
;
4188 unwind
.personality_routine
= symbol_find_or_make (name
);
4190 demand_empty_rest_of_line ();
4194 /* Parse a directive saving core registers. */
4197 s_arm_unwind_save_core (void)
4203 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4206 as_bad (_("expected register list"));
4207 ignore_rest_of_line ();
4211 demand_empty_rest_of_line ();
4213 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4214 into .unwind_save {..., sp...}. We aren't bothered about the value of
4215 ip because it is clobbered by calls. */
4216 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4217 && (range
& 0x3000) == 0x1000)
4219 unwind
.opcode_count
--;
4220 unwind
.sp_restored
= 0;
4221 range
= (range
| 0x2000) & ~0x1000;
4222 unwind
.pending_offset
= 0;
4228 /* See if we can use the short opcodes. These pop a block of up to 8
4229 registers starting with r4, plus maybe r14. */
4230 for (n
= 0; n
< 8; n
++)
4232 /* Break at the first non-saved register. */
4233 if ((range
& (1 << (n
+ 4))) == 0)
4236 /* See if there are any other bits set. */
4237 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4239 /* Use the long form. */
4240 op
= 0x8000 | ((range
>> 4) & 0xfff);
4241 add_unwind_opcode (op
, 2);
4245 /* Use the short form. */
4247 op
= 0xa8; /* Pop r14. */
4249 op
= 0xa0; /* Do not pop r14. */
4251 add_unwind_opcode (op
, 1);
4258 op
= 0xb100 | (range
& 0xf);
4259 add_unwind_opcode (op
, 2);
4262 /* Record the number of bytes pushed. */
4263 for (n
= 0; n
< 16; n
++)
4265 if (range
& (1 << n
))
4266 unwind
.frame_size
+= 4;
4271 /* Parse a directive saving FPA registers. */
4274 s_arm_unwind_save_fpa (int reg
)
4280 /* Get Number of registers to transfer. */
4281 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4284 exp
.X_op
= O_illegal
;
4286 if (exp
.X_op
!= O_constant
)
4288 as_bad (_("expected , <constant>"));
4289 ignore_rest_of_line ();
4293 num_regs
= exp
.X_add_number
;
4295 if (num_regs
< 1 || num_regs
> 4)
4297 as_bad (_("number of registers must be in the range [1:4]"));
4298 ignore_rest_of_line ();
4302 demand_empty_rest_of_line ();
4307 op
= 0xb4 | (num_regs
- 1);
4308 add_unwind_opcode (op
, 1);
4313 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4314 add_unwind_opcode (op
, 2);
4316 unwind
.frame_size
+= num_regs
* 12;
4320 /* Parse a directive saving VFP registers for ARMv6 and above. */
4323 s_arm_unwind_save_vfp_armv6 (void)
4328 int num_vfpv3_regs
= 0;
4329 int num_regs_below_16
;
4330 bfd_boolean partial_match
;
4332 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4336 as_bad (_("expected register list"));
4337 ignore_rest_of_line ();
4341 demand_empty_rest_of_line ();
4343 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4344 than FSTMX/FLDMX-style ones). */
4346 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4348 num_vfpv3_regs
= count
;
4349 else if (start
+ count
> 16)
4350 num_vfpv3_regs
= start
+ count
- 16;
4352 if (num_vfpv3_regs
> 0)
4354 int start_offset
= start
> 16 ? start
- 16 : 0;
4355 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4356 add_unwind_opcode (op
, 2);
4359 /* Generate opcode for registers numbered in the range 0 .. 15. */
4360 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4361 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4362 if (num_regs_below_16
> 0)
4364 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4365 add_unwind_opcode (op
, 2);
4368 unwind
.frame_size
+= count
* 8;
4372 /* Parse a directive saving VFP registers for pre-ARMv6. */
4375 s_arm_unwind_save_vfp (void)
4380 bfd_boolean partial_match
;
4382 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4386 as_bad (_("expected register list"));
4387 ignore_rest_of_line ();
4391 demand_empty_rest_of_line ();
4396 op
= 0xb8 | (count
- 1);
4397 add_unwind_opcode (op
, 1);
4402 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4403 add_unwind_opcode (op
, 2);
4405 unwind
.frame_size
+= count
* 8 + 4;
4409 /* Parse a directive saving iWMMXt data registers. */
4412 s_arm_unwind_save_mmxwr (void)
4420 if (*input_line_pointer
== '{')
4421 input_line_pointer
++;
4425 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4429 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4434 as_tsktsk (_("register list not in ascending order"));
4437 if (*input_line_pointer
== '-')
4439 input_line_pointer
++;
4440 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4443 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4446 else if (reg
>= hi_reg
)
4448 as_bad (_("bad register range"));
4451 for (; reg
< hi_reg
; reg
++)
4455 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4457 skip_past_char (&input_line_pointer
, '}');
4459 demand_empty_rest_of_line ();
4461 /* Generate any deferred opcodes because we're going to be looking at
4463 flush_pending_unwind ();
4465 for (i
= 0; i
< 16; i
++)
4467 if (mask
& (1 << i
))
4468 unwind
.frame_size
+= 8;
4471 /* Attempt to combine with a previous opcode. We do this because gcc
4472 likes to output separate unwind directives for a single block of
4474 if (unwind
.opcode_count
> 0)
4476 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4477 if ((i
& 0xf8) == 0xc0)
4480 /* Only merge if the blocks are contiguous. */
4483 if ((mask
& 0xfe00) == (1 << 9))
4485 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4486 unwind
.opcode_count
--;
4489 else if (i
== 6 && unwind
.opcode_count
>= 2)
4491 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4495 op
= 0xffff << (reg
- 1);
4497 && ((mask
& op
) == (1u << (reg
- 1))))
4499 op
= (1 << (reg
+ i
+ 1)) - 1;
4500 op
&= ~((1 << reg
) - 1);
4502 unwind
.opcode_count
-= 2;
4509 /* We want to generate opcodes in the order the registers have been
4510 saved, ie. descending order. */
4511 for (reg
= 15; reg
>= -1; reg
--)
4513 /* Save registers in blocks. */
4515 || !(mask
& (1 << reg
)))
4517 /* We found an unsaved reg. Generate opcodes to save the
4524 op
= 0xc0 | (hi_reg
- 10);
4525 add_unwind_opcode (op
, 1);
4530 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4531 add_unwind_opcode (op
, 2);
4540 ignore_rest_of_line ();
4544 s_arm_unwind_save_mmxwcg (void)
4551 if (*input_line_pointer
== '{')
4552 input_line_pointer
++;
4554 skip_whitespace (input_line_pointer
);
4558 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4562 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4568 as_tsktsk (_("register list not in ascending order"));
4571 if (*input_line_pointer
== '-')
4573 input_line_pointer
++;
4574 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4577 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4580 else if (reg
>= hi_reg
)
4582 as_bad (_("bad register range"));
4585 for (; reg
< hi_reg
; reg
++)
4589 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4591 skip_past_char (&input_line_pointer
, '}');
4593 demand_empty_rest_of_line ();
4595 /* Generate any deferred opcodes because we're going to be looking at
4597 flush_pending_unwind ();
4599 for (reg
= 0; reg
< 16; reg
++)
4601 if (mask
& (1 << reg
))
4602 unwind
.frame_size
+= 4;
4605 add_unwind_opcode (op
, 2);
4608 ignore_rest_of_line ();
4612 /* Parse an unwind_save directive.
4613 If the argument is non-zero, this is a .vsave directive. */
4616 s_arm_unwind_save (int arch_v6
)
4619 struct reg_entry
*reg
;
4620 bfd_boolean had_brace
= FALSE
;
4622 if (!unwind
.proc_start
)
4623 as_bad (MISSING_FNSTART
);
4625 /* Figure out what sort of save we have. */
4626 peek
= input_line_pointer
;
4634 reg
= arm_reg_parse_multi (&peek
);
4638 as_bad (_("register expected"));
4639 ignore_rest_of_line ();
4648 as_bad (_("FPA .unwind_save does not take a register list"));
4649 ignore_rest_of_line ();
4652 input_line_pointer
= peek
;
4653 s_arm_unwind_save_fpa (reg
->number
);
4657 s_arm_unwind_save_core ();
4662 s_arm_unwind_save_vfp_armv6 ();
4664 s_arm_unwind_save_vfp ();
4667 case REG_TYPE_MMXWR
:
4668 s_arm_unwind_save_mmxwr ();
4671 case REG_TYPE_MMXWCG
:
4672 s_arm_unwind_save_mmxwcg ();
4676 as_bad (_(".unwind_save does not support this kind of register"));
4677 ignore_rest_of_line ();
4682 /* Parse an unwind_movsp directive. */
4685 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4691 if (!unwind
.proc_start
)
4692 as_bad (MISSING_FNSTART
);
4694 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4697 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4698 ignore_rest_of_line ();
4702 /* Optional constant. */
4703 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4705 if (immediate_for_directive (&offset
) == FAIL
)
4711 demand_empty_rest_of_line ();
4713 if (reg
== REG_SP
|| reg
== REG_PC
)
4715 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4719 if (unwind
.fp_reg
!= REG_SP
)
4720 as_bad (_("unexpected .unwind_movsp directive"));
4722 /* Generate opcode to restore the value. */
4724 add_unwind_opcode (op
, 1);
4726 /* Record the information for later. */
4727 unwind
.fp_reg
= reg
;
4728 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4729 unwind
.sp_restored
= 1;
4732 /* Parse an unwind_pad directive. */
4735 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4739 if (!unwind
.proc_start
)
4740 as_bad (MISSING_FNSTART
);
4742 if (immediate_for_directive (&offset
) == FAIL
)
4747 as_bad (_("stack increment must be multiple of 4"));
4748 ignore_rest_of_line ();
4752 /* Don't generate any opcodes, just record the details for later. */
4753 unwind
.frame_size
+= offset
;
4754 unwind
.pending_offset
+= offset
;
4756 demand_empty_rest_of_line ();
4759 /* Parse an unwind_setfp directive. */
4762 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4768 if (!unwind
.proc_start
)
4769 as_bad (MISSING_FNSTART
);
4771 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4772 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4775 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4777 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4779 as_bad (_("expected <reg>, <reg>"));
4780 ignore_rest_of_line ();
4784 /* Optional constant. */
4785 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4787 if (immediate_for_directive (&offset
) == FAIL
)
4793 demand_empty_rest_of_line ();
4795 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4797 as_bad (_("register must be either sp or set by a previous"
4798 "unwind_movsp directive"));
4802 /* Don't generate any opcodes, just record the information for later. */
4803 unwind
.fp_reg
= fp_reg
;
4805 if (sp_reg
== REG_SP
)
4806 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4808 unwind
.fp_offset
-= offset
;
4811 /* Parse an unwind_raw directive. */
4814 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4817 /* This is an arbitrary limit. */
4818 unsigned char op
[16];
4821 if (!unwind
.proc_start
)
4822 as_bad (MISSING_FNSTART
);
4825 if (exp
.X_op
== O_constant
4826 && skip_past_comma (&input_line_pointer
) != FAIL
)
4828 unwind
.frame_size
+= exp
.X_add_number
;
4832 exp
.X_op
= O_illegal
;
4834 if (exp
.X_op
!= O_constant
)
4836 as_bad (_("expected <offset>, <opcode>"));
4837 ignore_rest_of_line ();
4843 /* Parse the opcode. */
4848 as_bad (_("unwind opcode too long"));
4849 ignore_rest_of_line ();
4851 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4853 as_bad (_("invalid unwind opcode"));
4854 ignore_rest_of_line ();
4857 op
[count
++] = exp
.X_add_number
;
4859 /* Parse the next byte. */
4860 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4866 /* Add the opcode bytes in reverse order. */
4868 add_unwind_opcode (op
[count
], 1);
4870 demand_empty_rest_of_line ();
4874 /* Parse a .eabi_attribute directive. */
4877 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4879 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4881 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4882 attributes_set_explicitly
[tag
] = 1;
4885 /* Emit a tls fix for the symbol. */
4888 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4892 #ifdef md_flush_pending_output
4893 md_flush_pending_output ();
4896 #ifdef md_cons_align
4900 /* Since we're just labelling the code, there's no need to define a
4903 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4904 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4905 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4906 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4908 #endif /* OBJ_ELF */
4910 static void s_arm_arch (int);
4911 static void s_arm_object_arch (int);
4912 static void s_arm_cpu (int);
4913 static void s_arm_fpu (int);
4914 static void s_arm_arch_extension (int);
4919 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4926 if (exp
.X_op
== O_symbol
)
4927 exp
.X_op
= O_secrel
;
4929 emit_expr (&exp
, 4);
4931 while (*input_line_pointer
++ == ',');
4933 input_line_pointer
--;
4934 demand_empty_rest_of_line ();
4939 arm_is_largest_exponent_ok (int precision
)
4941 /* precision == 1 ensures that this will only return
4942 true for 16 bit floats. */
4943 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4947 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4951 enum fp_16bit_format new_format
;
4953 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4955 name
= input_line_pointer
;
4956 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4957 input_line_pointer
++;
4959 saved_char
= *input_line_pointer
;
4960 *input_line_pointer
= 0;
4962 if (strcasecmp (name
, "ieee") == 0)
4963 new_format
= ARM_FP16_FORMAT_IEEE
;
4964 else if (strcasecmp (name
, "alternative") == 0)
4965 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
4968 as_bad (_("unrecognised float16 format \"%s\""), name
);
4972 /* Only set fp16_format if it is still the default (aka not already
4974 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
4975 fp16_format
= new_format
;
4978 if (new_format
!= fp16_format
)
4979 as_warn (_("float16 format cannot be set more than once, ignoring."));
4983 *input_line_pointer
= saved_char
;
4984 ignore_rest_of_line ();
4987 /* This table describes all the machine specific pseudo-ops the assembler
4988 has to support. The fields are:
4989 pseudo-op name without dot
4990 function to call to execute this pseudo-op
4991 Integer arg to pass to the function. */
4993 const pseudo_typeS md_pseudo_table
[] =
4995 /* Never called because '.req' does not start a line. */
4996 { "req", s_req
, 0 },
4997 /* Following two are likewise never called. */
5000 { "unreq", s_unreq
, 0 },
5001 { "bss", s_bss
, 0 },
5002 { "align", s_align_ptwo
, 2 },
5003 { "arm", s_arm
, 0 },
5004 { "thumb", s_thumb
, 0 },
5005 { "code", s_code
, 0 },
5006 { "force_thumb", s_force_thumb
, 0 },
5007 { "thumb_func", s_thumb_func
, 0 },
5008 { "thumb_set", s_thumb_set
, 0 },
5009 { "even", s_even
, 0 },
5010 { "ltorg", s_ltorg
, 0 },
5011 { "pool", s_ltorg
, 0 },
5012 { "syntax", s_syntax
, 0 },
5013 { "cpu", s_arm_cpu
, 0 },
5014 { "arch", s_arm_arch
, 0 },
5015 { "object_arch", s_arm_object_arch
, 0 },
5016 { "fpu", s_arm_fpu
, 0 },
5017 { "arch_extension", s_arm_arch_extension
, 0 },
5019 { "word", s_arm_elf_cons
, 4 },
5020 { "long", s_arm_elf_cons
, 4 },
5021 { "inst.n", s_arm_elf_inst
, 2 },
5022 { "inst.w", s_arm_elf_inst
, 4 },
5023 { "inst", s_arm_elf_inst
, 0 },
5024 { "rel31", s_arm_rel31
, 0 },
5025 { "fnstart", s_arm_unwind_fnstart
, 0 },
5026 { "fnend", s_arm_unwind_fnend
, 0 },
5027 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5028 { "personality", s_arm_unwind_personality
, 0 },
5029 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5030 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5031 { "save", s_arm_unwind_save
, 0 },
5032 { "vsave", s_arm_unwind_save
, 1 },
5033 { "movsp", s_arm_unwind_movsp
, 0 },
5034 { "pad", s_arm_unwind_pad
, 0 },
5035 { "setfp", s_arm_unwind_setfp
, 0 },
5036 { "unwind_raw", s_arm_unwind_raw
, 0 },
5037 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5038 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5042 /* These are used for dwarf. */
5046 /* These are used for dwarf2. */
5047 { "file", dwarf2_directive_file
, 0 },
5048 { "loc", dwarf2_directive_loc
, 0 },
5049 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5051 { "extend", float_cons
, 'x' },
5052 { "ldouble", float_cons
, 'x' },
5053 { "packed", float_cons
, 'p' },
5055 {"secrel32", pe_directive_secrel
, 0},
5058 /* These are for compatibility with CodeComposer Studio. */
5059 {"ref", s_ccs_ref
, 0},
5060 {"def", s_ccs_def
, 0},
5061 {"asmfunc", s_ccs_asmfunc
, 0},
5062 {"endasmfunc", s_ccs_endasmfunc
, 0},
5064 {"float16", float_cons
, 'h' },
5065 {"float16_format", set_fp16_format
, 0 },
5070 /* Parser functions used exclusively in instruction operands. */
5072 /* Generic immediate-value read function for use in insn parsing.
5073 STR points to the beginning of the immediate (the leading #);
5074 VAL receives the value; if the value is outside [MIN, MAX]
5075 issue an error. PREFIX_OPT is true if the immediate prefix is
5079 parse_immediate (char **str
, int *val
, int min
, int max
,
5080 bfd_boolean prefix_opt
)
5084 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5085 if (exp
.X_op
!= O_constant
)
5087 inst
.error
= _("constant expression required");
5091 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5093 inst
.error
= _("immediate value out of range");
5097 *val
= exp
.X_add_number
;
5101 /* Less-generic immediate-value read function with the possibility of loading a
5102 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5103 instructions. Puts the result directly in inst.operands[i]. */
5106 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5107 bfd_boolean allow_symbol_p
)
5110 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5113 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5115 if (exp_p
->X_op
== O_constant
)
5117 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5118 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5119 O_constant. We have to be careful not to break compilation for
5120 32-bit X_add_number, though. */
5121 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5123 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5124 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5126 inst
.operands
[i
].regisimm
= 1;
5129 else if (exp_p
->X_op
== O_big
5130 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5132 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5134 /* Bignums have their least significant bits in
5135 generic_bignum[0]. Make sure we put 32 bits in imm and
5136 32 bits in reg, in a (hopefully) portable way. */
5137 gas_assert (parts
!= 0);
5139 /* Make sure that the number is not too big.
5140 PR 11972: Bignums can now be sign-extended to the
5141 size of a .octa so check that the out of range bits
5142 are all zero or all one. */
5143 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5145 LITTLENUM_TYPE m
= -1;
5147 if (generic_bignum
[parts
* 2] != 0
5148 && generic_bignum
[parts
* 2] != m
)
5151 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5152 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5156 inst
.operands
[i
].imm
= 0;
5157 for (j
= 0; j
< parts
; j
++, idx
++)
5158 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5159 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5160 inst
.operands
[i
].reg
= 0;
5161 for (j
= 0; j
< parts
; j
++, idx
++)
5162 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5163 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5164 inst
.operands
[i
].regisimm
= 1;
5166 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5174 /* Returns the pseudo-register number of an FPA immediate constant,
5175 or FAIL if there isn't a valid constant here. */
5178 parse_fpa_immediate (char ** str
)
5180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5186 /* First try and match exact strings, this is to guarantee
5187 that some formats will work even for cross assembly. */
5189 for (i
= 0; fp_const
[i
]; i
++)
5191 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5195 *str
+= strlen (fp_const
[i
]);
5196 if (is_end_of_line
[(unsigned char) **str
])
5202 /* Just because we didn't get a match doesn't mean that the constant
5203 isn't valid, just that it is in a format that we don't
5204 automatically recognize. Try parsing it with the standard
5205 expression routines. */
5207 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5209 /* Look for a raw floating point number. */
5210 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5211 && is_end_of_line
[(unsigned char) *save_in
])
5213 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5215 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5217 if (words
[j
] != fp_values
[i
][j
])
5221 if (j
== MAX_LITTLENUMS
)
5229 /* Try and parse a more complex expression, this will probably fail
5230 unless the code uses a floating point prefix (eg "0f"). */
5231 save_in
= input_line_pointer
;
5232 input_line_pointer
= *str
;
5233 if (expression (&exp
) == absolute_section
5234 && exp
.X_op
== O_big
5235 && exp
.X_add_number
< 0)
5237 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5239 #define X_PRECISION 5
5240 #define E_PRECISION 15L
5241 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5243 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5245 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5247 if (words
[j
] != fp_values
[i
][j
])
5251 if (j
== MAX_LITTLENUMS
)
5253 *str
= input_line_pointer
;
5254 input_line_pointer
= save_in
;
5261 *str
= input_line_pointer
;
5262 input_line_pointer
= save_in
;
5263 inst
.error
= _("invalid FPA immediate expression");
5267 /* Returns 1 if a number has "quarter-precision" float format
5268 0baBbbbbbc defgh000 00000000 00000000. */
5271 is_quarter_float (unsigned imm
)
5273 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5274 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5278 /* Detect the presence of a floating point or integer zero constant,
5282 parse_ifimm_zero (char **in
)
5286 if (!is_immediate_prefix (**in
))
5288 /* In unified syntax, all prefixes are optional. */
5289 if (!unified_syntax
)
5295 /* Accept #0x0 as a synonym for #0. */
5296 if (strncmp (*in
, "0x", 2) == 0)
5299 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5304 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5305 &generic_floating_point_number
);
5308 && generic_floating_point_number
.sign
== '+'
5309 && (generic_floating_point_number
.low
5310 > generic_floating_point_number
.leader
))
5316 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5317 0baBbbbbbc defgh000 00000000 00000000.
5318 The zero and minus-zero cases need special handling, since they can't be
5319 encoded in the "quarter-precision" float format, but can nonetheless be
5320 loaded as integer constants. */
5323 parse_qfloat_immediate (char **ccp
, int *immed
)
5327 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5328 int found_fpchar
= 0;
5330 skip_past_char (&str
, '#');
5332 /* We must not accidentally parse an integer as a floating-point number. Make
5333 sure that the value we parse is not an integer by checking for special
5334 characters '.' or 'e'.
5335 FIXME: This is a horrible hack, but doing better is tricky because type
5336 information isn't in a very usable state at parse time. */
5338 skip_whitespace (fpnum
);
5340 if (strncmp (fpnum
, "0x", 2) == 0)
5344 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5345 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5355 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5357 unsigned fpword
= 0;
5360 /* Our FP word must be 32 bits (single-precision FP). */
5361 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5363 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5367 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5380 /* Shift operands. */
5383 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5386 struct asm_shift_name
5389 enum shift_kind kind
;
5392 /* Third argument to parse_shift. */
5393 enum parse_shift_mode
5395 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5396 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5397 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5398 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5399 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5400 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5403 /* Parse a <shift> specifier on an ARM data processing instruction.
5404 This has three forms:
5406 (LSL|LSR|ASL|ASR|ROR) Rs
5407 (LSL|LSR|ASL|ASR|ROR) #imm
5410 Note that ASL is assimilated to LSL in the instruction encoding, and
5411 RRX to ROR #0 (which cannot be written as such). */
5414 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5416 const struct asm_shift_name
*shift_name
;
5417 enum shift_kind shift
;
5422 for (p
= *str
; ISALPHA (*p
); p
++)
5427 inst
.error
= _("shift expression expected");
5431 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5434 if (shift_name
== NULL
)
5436 inst
.error
= _("shift expression expected");
5440 shift
= shift_name
->kind
;
5444 case NO_SHIFT_RESTRICT
:
5445 case SHIFT_IMMEDIATE
:
5446 if (shift
== SHIFT_UXTW
)
5448 inst
.error
= _("'UXTW' not allowed here");
5453 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5454 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5456 inst
.error
= _("'LSL' or 'ASR' required");
5461 case SHIFT_LSL_IMMEDIATE
:
5462 if (shift
!= SHIFT_LSL
)
5464 inst
.error
= _("'LSL' required");
5469 case SHIFT_ASR_IMMEDIATE
:
5470 if (shift
!= SHIFT_ASR
)
5472 inst
.error
= _("'ASR' required");
5476 case SHIFT_UXTW_IMMEDIATE
:
5477 if (shift
!= SHIFT_UXTW
)
5479 inst
.error
= _("'UXTW' required");
5487 if (shift
!= SHIFT_RRX
)
5489 /* Whitespace can appear here if the next thing is a bare digit. */
5490 skip_whitespace (p
);
5492 if (mode
== NO_SHIFT_RESTRICT
5493 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5495 inst
.operands
[i
].imm
= reg
;
5496 inst
.operands
[i
].immisreg
= 1;
5498 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5501 inst
.operands
[i
].shift_kind
= shift
;
5502 inst
.operands
[i
].shifted
= 1;
5507 /* Parse a <shifter_operand> for an ARM data processing instruction:
5510 #<immediate>, <rotate>
5514 where <shift> is defined by parse_shift above, and <rotate> is a
5515 multiple of 2 between 0 and 30. Validation of immediate operands
5516 is deferred to md_apply_fix. */
5519 parse_shifter_operand (char **str
, int i
)
5524 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5526 inst
.operands
[i
].reg
= value
;
5527 inst
.operands
[i
].isreg
= 1;
5529 /* parse_shift will override this if appropriate */
5530 inst
.relocs
[0].exp
.X_op
= O_constant
;
5531 inst
.relocs
[0].exp
.X_add_number
= 0;
5533 if (skip_past_comma (str
) == FAIL
)
5536 /* Shift operation on register. */
5537 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5540 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5543 if (skip_past_comma (str
) == SUCCESS
)
5545 /* #x, y -- ie explicit rotation by Y. */
5546 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5549 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5551 inst
.error
= _("constant expression expected");
5555 value
= exp
.X_add_number
;
5556 if (value
< 0 || value
> 30 || value
% 2 != 0)
5558 inst
.error
= _("invalid rotation");
5561 if (inst
.relocs
[0].exp
.X_add_number
< 0
5562 || inst
.relocs
[0].exp
.X_add_number
> 255)
5564 inst
.error
= _("invalid constant");
5568 /* Encode as specified. */
5569 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5573 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5574 inst
.relocs
[0].pc_rel
= 0;
5578 /* Group relocation information. Each entry in the table contains the
5579 textual name of the relocation as may appear in assembler source
5580 and must end with a colon.
5581 Along with this textual name are the relocation codes to be used if
5582 the corresponding instruction is an ALU instruction (ADD or SUB only),
5583 an LDR, an LDRS, or an LDC. */
5585 struct group_reloc_table_entry
5596 /* Varieties of non-ALU group relocation. */
5604 static struct group_reloc_table_entry group_reloc_table
[] =
5605 { /* Program counter relative: */
5607 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5612 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5613 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5614 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5615 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5617 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5622 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5627 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5631 /* Section base relative */
5633 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5638 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5639 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5640 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5641 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5643 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5648 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5653 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5656 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5657 /* Absolute thumb alu relocations. */
5659 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5679 /* Given the address of a pointer pointing to the textual name of a group
5680 relocation as may appear in assembler source, attempt to find its details
5681 in group_reloc_table. The pointer will be updated to the character after
5682 the trailing colon. On failure, FAIL will be returned; SUCCESS
5683 otherwise. On success, *entry will be updated to point at the relevant
5684 group_reloc_table entry. */
5687 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5690 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5692 int length
= strlen (group_reloc_table
[i
].name
);
5694 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5695 && (*str
)[length
] == ':')
5697 *out
= &group_reloc_table
[i
];
5698 *str
+= (length
+ 1);
5706 /* Parse a <shifter_operand> for an ARM data processing instruction
5707 (as for parse_shifter_operand) where group relocations are allowed:
5710 #<immediate>, <rotate>
5711 #:<group_reloc>:<expression>
5715 where <group_reloc> is one of the strings defined in group_reloc_table.
5716 The hashes are optional.
5718 Everything else is as for parse_shifter_operand. */
5720 static parse_operand_result
5721 parse_shifter_operand_group_reloc (char **str
, int i
)
5723 /* Determine if we have the sequence of characters #: or just :
5724 coming next. If we do, then we check for a group relocation.
5725 If we don't, punt the whole lot to parse_shifter_operand. */
5727 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5728 || (*str
)[0] == ':')
5730 struct group_reloc_table_entry
*entry
;
5732 if ((*str
)[0] == '#')
5737 /* Try to parse a group relocation. Anything else is an error. */
5738 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5740 inst
.error
= _("unknown group relocation");
5741 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5744 /* We now have the group relocation table entry corresponding to
5745 the name in the assembler source. Next, we parse the expression. */
5746 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5747 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5749 /* Record the relocation type (always the ALU variant here). */
5750 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5751 gas_assert (inst
.relocs
[0].type
!= 0);
5753 return PARSE_OPERAND_SUCCESS
;
5756 return parse_shifter_operand (str
, i
) == SUCCESS
5757 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5759 /* Never reached. */
5762 /* Parse a Neon alignment expression. Information is written to
5763 inst.operands[i]. We assume the initial ':' has been skipped.
5765 align .imm = align << 8, .immisalign=1, .preind=0 */
5766 static parse_operand_result
5767 parse_neon_alignment (char **str
, int i
)
5772 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5774 if (exp
.X_op
!= O_constant
)
5776 inst
.error
= _("alignment must be constant");
5777 return PARSE_OPERAND_FAIL
;
5780 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5781 inst
.operands
[i
].immisalign
= 1;
5782 /* Alignments are not pre-indexes. */
5783 inst
.operands
[i
].preind
= 0;
5786 return PARSE_OPERAND_SUCCESS
;
5789 /* Parse all forms of an ARM address expression. Information is written
5790 to inst.operands[i] and/or inst.relocs[0].
5792 Preindexed addressing (.preind=1):
5794 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5795 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5796 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5797 .shift_kind=shift .relocs[0].exp=shift_imm
5799 These three may have a trailing ! which causes .writeback to be set also.
5801 Postindexed addressing (.postind=1, .writeback=1):
5803 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5804 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5805 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5806 .shift_kind=shift .relocs[0].exp=shift_imm
5808 Unindexed addressing (.preind=0, .postind=0):
5810 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5814 [Rn]{!} shorthand for [Rn,#0]{!}
5815 =immediate .isreg=0 .relocs[0].exp=immediate
5816 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5818 It is the caller's responsibility to check for addressing modes not
5819 supported by the instruction, and to set inst.relocs[0].type. */
5821 static parse_operand_result
5822 parse_address_main (char **str
, int i
, int group_relocations
,
5823 group_reloc_type group_type
)
5828 if (skip_past_char (&p
, '[') == FAIL
)
5830 if (skip_past_char (&p
, '=') == FAIL
)
5832 /* Bare address - translate to PC-relative offset. */
5833 inst
.relocs
[0].pc_rel
= 1;
5834 inst
.operands
[i
].reg
= REG_PC
;
5835 inst
.operands
[i
].isreg
= 1;
5836 inst
.operands
[i
].preind
= 1;
5838 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5839 return PARSE_OPERAND_FAIL
;
5841 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5842 /*allow_symbol_p=*/TRUE
))
5843 return PARSE_OPERAND_FAIL
;
5846 return PARSE_OPERAND_SUCCESS
;
5849 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5850 skip_whitespace (p
);
5852 if (group_type
== GROUP_MVE
)
5854 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5855 struct neon_type_el et
;
5856 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5858 inst
.operands
[i
].isquad
= 1;
5860 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5862 inst
.error
= BAD_ADDR_MODE
;
5863 return PARSE_OPERAND_FAIL
;
5866 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5868 if (group_type
== GROUP_MVE
)
5869 inst
.error
= BAD_ADDR_MODE
;
5871 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5872 return PARSE_OPERAND_FAIL
;
5874 inst
.operands
[i
].reg
= reg
;
5875 inst
.operands
[i
].isreg
= 1;
5877 if (skip_past_comma (&p
) == SUCCESS
)
5879 inst
.operands
[i
].preind
= 1;
5882 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5884 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5885 struct neon_type_el et
;
5886 if (group_type
== GROUP_MVE
5887 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5889 inst
.operands
[i
].immisreg
= 2;
5890 inst
.operands
[i
].imm
= reg
;
5892 if (skip_past_comma (&p
) == SUCCESS
)
5894 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5896 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5897 inst
.relocs
[0].exp
.X_add_number
= 0;
5900 return PARSE_OPERAND_FAIL
;
5903 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5905 inst
.operands
[i
].imm
= reg
;
5906 inst
.operands
[i
].immisreg
= 1;
5908 if (skip_past_comma (&p
) == SUCCESS
)
5909 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5910 return PARSE_OPERAND_FAIL
;
5912 else if (skip_past_char (&p
, ':') == SUCCESS
)
5914 /* FIXME: '@' should be used here, but it's filtered out by generic
5915 code before we get to see it here. This may be subject to
5917 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5919 if (result
!= PARSE_OPERAND_SUCCESS
)
5924 if (inst
.operands
[i
].negative
)
5926 inst
.operands
[i
].negative
= 0;
5930 if (group_relocations
5931 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5933 struct group_reloc_table_entry
*entry
;
5935 /* Skip over the #: or : sequence. */
5941 /* Try to parse a group relocation. Anything else is an
5943 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5945 inst
.error
= _("unknown group relocation");
5946 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5949 /* We now have the group relocation table entry corresponding to
5950 the name in the assembler source. Next, we parse the
5952 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5953 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5955 /* Record the relocation type. */
5960 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5965 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5970 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5977 if (inst
.relocs
[0].type
== 0)
5979 inst
.error
= _("this group relocation is not allowed on this instruction");
5980 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5987 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5988 return PARSE_OPERAND_FAIL
;
5989 /* If the offset is 0, find out if it's a +0 or -0. */
5990 if (inst
.relocs
[0].exp
.X_op
== O_constant
5991 && inst
.relocs
[0].exp
.X_add_number
== 0)
5993 skip_whitespace (q
);
5997 skip_whitespace (q
);
6000 inst
.operands
[i
].negative
= 1;
6005 else if (skip_past_char (&p
, ':') == SUCCESS
)
6007 /* FIXME: '@' should be used here, but it's filtered out by generic code
6008 before we get to see it here. This may be subject to change. */
6009 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6011 if (result
!= PARSE_OPERAND_SUCCESS
)
6015 if (skip_past_char (&p
, ']') == FAIL
)
6017 inst
.error
= _("']' expected");
6018 return PARSE_OPERAND_FAIL
;
6021 if (skip_past_char (&p
, '!') == SUCCESS
)
6022 inst
.operands
[i
].writeback
= 1;
6024 else if (skip_past_comma (&p
) == SUCCESS
)
6026 if (skip_past_char (&p
, '{') == SUCCESS
)
6028 /* [Rn], {expr} - unindexed, with option */
6029 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6030 0, 255, TRUE
) == FAIL
)
6031 return PARSE_OPERAND_FAIL
;
6033 if (skip_past_char (&p
, '}') == FAIL
)
6035 inst
.error
= _("'}' expected at end of 'option' field");
6036 return PARSE_OPERAND_FAIL
;
6038 if (inst
.operands
[i
].preind
)
6040 inst
.error
= _("cannot combine index with option");
6041 return PARSE_OPERAND_FAIL
;
6044 return PARSE_OPERAND_SUCCESS
;
6048 inst
.operands
[i
].postind
= 1;
6049 inst
.operands
[i
].writeback
= 1;
6051 if (inst
.operands
[i
].preind
)
6053 inst
.error
= _("cannot combine pre- and post-indexing");
6054 return PARSE_OPERAND_FAIL
;
6058 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6060 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6061 struct neon_type_el et
;
6062 if (group_type
== GROUP_MVE
6063 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6065 inst
.operands
[i
].immisreg
= 2;
6066 inst
.operands
[i
].imm
= reg
;
6068 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6070 /* We might be using the immediate for alignment already. If we
6071 are, OR the register number into the low-order bits. */
6072 if (inst
.operands
[i
].immisalign
)
6073 inst
.operands
[i
].imm
|= reg
;
6075 inst
.operands
[i
].imm
= reg
;
6076 inst
.operands
[i
].immisreg
= 1;
6078 if (skip_past_comma (&p
) == SUCCESS
)
6079 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6080 return PARSE_OPERAND_FAIL
;
6086 if (inst
.operands
[i
].negative
)
6088 inst
.operands
[i
].negative
= 0;
6091 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6092 return PARSE_OPERAND_FAIL
;
6093 /* If the offset is 0, find out if it's a +0 or -0. */
6094 if (inst
.relocs
[0].exp
.X_op
== O_constant
6095 && inst
.relocs
[0].exp
.X_add_number
== 0)
6097 skip_whitespace (q
);
6101 skip_whitespace (q
);
6104 inst
.operands
[i
].negative
= 1;
6110 /* If at this point neither .preind nor .postind is set, we have a
6111 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6112 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6114 inst
.operands
[i
].preind
= 1;
6115 inst
.relocs
[0].exp
.X_op
= O_constant
;
6116 inst
.relocs
[0].exp
.X_add_number
= 0;
6119 return PARSE_OPERAND_SUCCESS
;
6123 parse_address (char **str
, int i
)
6125 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6129 static parse_operand_result
6130 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6132 return parse_address_main (str
, i
, 1, type
);
6135 /* Parse an operand for a MOVW or MOVT instruction. */
6137 parse_half (char **str
)
6142 skip_past_char (&p
, '#');
6143 if (strncasecmp (p
, ":lower16:", 9) == 0)
6144 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6145 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6146 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6148 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6151 skip_whitespace (p
);
6154 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6157 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6159 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6161 inst
.error
= _("constant expression expected");
6164 if (inst
.relocs
[0].exp
.X_add_number
< 0
6165 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6167 inst
.error
= _("immediate value out of range");
6175 /* Miscellaneous. */
6177 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6178 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6180 parse_psr (char **str
, bfd_boolean lhs
)
6183 unsigned long psr_field
;
6184 const struct asm_psr
*psr
;
6186 bfd_boolean is_apsr
= FALSE
;
6187 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6189 /* PR gas/12698: If the user has specified -march=all then m_profile will
6190 be TRUE, but we want to ignore it in this case as we are building for any
6191 CPU type, including non-m variants. */
6192 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6195 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6196 feature for ease of use and backwards compatibility. */
6198 if (strncasecmp (p
, "SPSR", 4) == 0)
6201 goto unsupported_psr
;
6203 psr_field
= SPSR_BIT
;
6205 else if (strncasecmp (p
, "CPSR", 4) == 0)
6208 goto unsupported_psr
;
6212 else if (strncasecmp (p
, "APSR", 4) == 0)
6214 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6215 and ARMv7-R architecture CPUs. */
6224 while (ISALNUM (*p
) || *p
== '_');
6226 if (strncasecmp (start
, "iapsr", 5) == 0
6227 || strncasecmp (start
, "eapsr", 5) == 0
6228 || strncasecmp (start
, "xpsr", 4) == 0
6229 || strncasecmp (start
, "psr", 3) == 0)
6230 p
= start
+ strcspn (start
, "rR") + 1;
6232 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6238 /* If APSR is being written, a bitfield may be specified. Note that
6239 APSR itself is handled above. */
6240 if (psr
->field
<= 3)
6242 psr_field
= psr
->field
;
6248 /* M-profile MSR instructions have the mask field set to "10", except
6249 *PSR variants which modify APSR, which may use a different mask (and
6250 have been handled already). Do that by setting the PSR_f field
6252 return psr
->field
| (lhs
? PSR_f
: 0);
6255 goto unsupported_psr
;
6261 /* A suffix follows. */
6267 while (ISALNUM (*p
) || *p
== '_');
6271 /* APSR uses a notation for bits, rather than fields. */
6272 unsigned int nzcvq_bits
= 0;
6273 unsigned int g_bit
= 0;
6276 for (bit
= start
; bit
!= p
; bit
++)
6278 switch (TOLOWER (*bit
))
6281 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6285 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6289 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6293 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6297 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6301 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6305 inst
.error
= _("unexpected bit specified after APSR");
6310 if (nzcvq_bits
== 0x1f)
6315 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6317 inst
.error
= _("selected processor does not "
6318 "support DSP extension");
6325 if ((nzcvq_bits
& 0x20) != 0
6326 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6327 || (g_bit
& 0x2) != 0)
6329 inst
.error
= _("bad bitmask specified after APSR");
6335 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6340 psr_field
|= psr
->field
;
6346 goto error
; /* Garbage after "[CS]PSR". */
6348 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6349 is deprecated, but allow it anyway. */
6353 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6356 else if (!m_profile
)
6357 /* These bits are never right for M-profile devices: don't set them
6358 (only code paths which read/write APSR reach here). */
6359 psr_field
|= (PSR_c
| PSR_f
);
6365 inst
.error
= _("selected processor does not support requested special "
6366 "purpose register");
6370 inst
.error
= _("flag for {c}psr instruction expected");
6375 parse_sys_vldr_vstr (char **str
)
6384 {"FPSCR", 0x1, 0x0},
6385 {"FPSCR_nzcvqc", 0x2, 0x0},
6388 {"FPCXTNS", 0x6, 0x1},
6389 {"FPCXTS", 0x7, 0x1}
6391 char *op_end
= strchr (*str
, ',');
6392 size_t op_strlen
= op_end
- *str
;
6394 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6396 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6398 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6407 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6408 value suitable for splatting into the AIF field of the instruction. */
6411 parse_cps_flags (char **str
)
6420 case '\0': case ',':
6423 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6424 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6425 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6428 inst
.error
= _("unrecognized CPS flag");
6433 if (saw_a_flag
== 0)
6435 inst
.error
= _("missing CPS flags");
6443 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6444 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6447 parse_endian_specifier (char **str
)
6452 if (strncasecmp (s
, "BE", 2))
6454 else if (strncasecmp (s
, "LE", 2))
6458 inst
.error
= _("valid endian specifiers are be or le");
6462 if (ISALNUM (s
[2]) || s
[2] == '_')
6464 inst
.error
= _("valid endian specifiers are be or le");
6469 return little_endian
;
6472 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6473 value suitable for poking into the rotate field of an sxt or sxta
6474 instruction, or FAIL on error. */
6477 parse_ror (char **str
)
6482 if (strncasecmp (s
, "ROR", 3) == 0)
6486 inst
.error
= _("missing rotation field after comma");
6490 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6495 case 0: *str
= s
; return 0x0;
6496 case 8: *str
= s
; return 0x1;
6497 case 16: *str
= s
; return 0x2;
6498 case 24: *str
= s
; return 0x3;
6501 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6506 /* Parse a conditional code (from conds[] below). The value returned is in the
6507 range 0 .. 14, or FAIL. */
6509 parse_cond (char **str
)
6512 const struct asm_cond
*c
;
6514 /* Condition codes are always 2 characters, so matching up to
6515 3 characters is sufficient. */
6520 while (ISALPHA (*q
) && n
< 3)
6522 cond
[n
] = TOLOWER (*q
);
6527 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6530 inst
.error
= _("condition required");
6538 /* Parse an option for a barrier instruction. Returns the encoding for the
6541 parse_barrier (char **str
)
6544 const struct asm_barrier_opt
*o
;
6547 while (ISALPHA (*q
))
6550 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6555 if (!mark_feature_used (&o
->arch
))
6562 /* Parse the operands of a table branch instruction. Similar to a memory
6565 parse_tb (char **str
)
6570 if (skip_past_char (&p
, '[') == FAIL
)
6572 inst
.error
= _("'[' expected");
6576 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6578 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6581 inst
.operands
[0].reg
= reg
;
6583 if (skip_past_comma (&p
) == FAIL
)
6585 inst
.error
= _("',' expected");
6589 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6591 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6594 inst
.operands
[0].imm
= reg
;
6596 if (skip_past_comma (&p
) == SUCCESS
)
6598 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6600 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6602 inst
.error
= _("invalid shift");
6605 inst
.operands
[0].shifted
= 1;
6608 if (skip_past_char (&p
, ']') == FAIL
)
6610 inst
.error
= _("']' expected");
6617 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6618 information on the types the operands can take and how they are encoded.
6619 Up to four operands may be read; this function handles setting the
6620 ".present" field for each read operand itself.
6621 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6622 else returns FAIL. */
6625 parse_neon_mov (char **str
, int *which_operand
)
6627 int i
= *which_operand
, val
;
6628 enum arm_reg_type rtype
;
6630 struct neon_type_el optype
;
6632 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6634 /* Cases 17 or 19. */
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isvec
= 1;
6637 inst
.operands
[i
].isscalar
= 2;
6638 inst
.operands
[i
].vectype
= optype
;
6639 inst
.operands
[i
++].present
= 1;
6641 if (skip_past_comma (&ptr
) == FAIL
)
6644 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6646 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6647 inst
.operands
[i
].reg
= val
;
6648 inst
.operands
[i
].isreg
= 1;
6649 inst
.operands
[i
].present
= 1;
6651 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6653 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6654 inst
.operands
[i
].reg
= val
;
6655 inst
.operands
[i
].isvec
= 1;
6656 inst
.operands
[i
].isscalar
= 2;
6657 inst
.operands
[i
].vectype
= optype
;
6658 inst
.operands
[i
++].present
= 1;
6660 if (skip_past_comma (&ptr
) == FAIL
)
6663 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6666 inst
.operands
[i
].reg
= val
;
6667 inst
.operands
[i
].isreg
= 1;
6668 inst
.operands
[i
++].present
= 1;
6670 if (skip_past_comma (&ptr
) == FAIL
)
6673 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6682 first_error (_("expected ARM or MVE vector register"));
6686 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6688 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isscalar
= 1;
6691 inst
.operands
[i
].vectype
= optype
;
6692 inst
.operands
[i
++].present
= 1;
6694 if (skip_past_comma (&ptr
) == FAIL
)
6697 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.operands
[i
].reg
= val
;
6701 inst
.operands
[i
].isreg
= 1;
6702 inst
.operands
[i
].present
= 1;
6704 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6706 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6709 /* Cases 0, 1, 2, 3, 5 (D only). */
6710 if (skip_past_comma (&ptr
) == FAIL
)
6713 inst
.operands
[i
].reg
= val
;
6714 inst
.operands
[i
].isreg
= 1;
6715 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6716 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6717 inst
.operands
[i
].isvec
= 1;
6718 inst
.operands
[i
].vectype
= optype
;
6719 inst
.operands
[i
++].present
= 1;
6721 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6723 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6724 Case 13: VMOV <Sd>, <Rm> */
6725 inst
.operands
[i
].reg
= val
;
6726 inst
.operands
[i
].isreg
= 1;
6727 inst
.operands
[i
].present
= 1;
6729 if (rtype
== REG_TYPE_NQ
)
6731 first_error (_("can't use Neon quad register here"));
6734 else if (rtype
!= REG_TYPE_VFS
)
6737 if (skip_past_comma (&ptr
) == FAIL
)
6739 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6741 inst
.operands
[i
].reg
= val
;
6742 inst
.operands
[i
].isreg
= 1;
6743 inst
.operands
[i
].present
= 1;
6746 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6749 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6750 Case 1: VMOV<c><q> <Dd>, <Dm>
6751 Case 8: VMOV.F32 <Sd>, <Sm>
6752 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6754 inst
.operands
[i
].reg
= val
;
6755 inst
.operands
[i
].isreg
= 1;
6756 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6757 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6758 inst
.operands
[i
].isvec
= 1;
6759 inst
.operands
[i
].vectype
= optype
;
6760 inst
.operands
[i
].present
= 1;
6762 if (skip_past_comma (&ptr
) == SUCCESS
)
6767 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6770 inst
.operands
[i
].reg
= val
;
6771 inst
.operands
[i
].isreg
= 1;
6772 inst
.operands
[i
++].present
= 1;
6774 if (skip_past_comma (&ptr
) == FAIL
)
6777 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6780 inst
.operands
[i
].reg
= val
;
6781 inst
.operands
[i
].isreg
= 1;
6782 inst
.operands
[i
].present
= 1;
6785 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6786 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6787 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6788 Case 10: VMOV.F32 <Sd>, #<imm>
6789 Case 11: VMOV.F64 <Dd>, #<imm> */
6790 inst
.operands
[i
].immisfloat
= 1;
6791 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6793 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6794 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6798 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6802 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6804 /* Cases 6, 7, 16, 18. */
6805 inst
.operands
[i
].reg
= val
;
6806 inst
.operands
[i
].isreg
= 1;
6807 inst
.operands
[i
++].present
= 1;
6809 if (skip_past_comma (&ptr
) == FAIL
)
6812 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6814 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6815 inst
.operands
[i
].reg
= val
;
6816 inst
.operands
[i
].isscalar
= 2;
6817 inst
.operands
[i
].present
= 1;
6818 inst
.operands
[i
].vectype
= optype
;
6820 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6822 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6823 inst
.operands
[i
].reg
= val
;
6824 inst
.operands
[i
].isscalar
= 1;
6825 inst
.operands
[i
].present
= 1;
6826 inst
.operands
[i
].vectype
= optype
;
6828 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6830 inst
.operands
[i
].reg
= val
;
6831 inst
.operands
[i
].isreg
= 1;
6832 inst
.operands
[i
++].present
= 1;
6834 if (skip_past_comma (&ptr
) == FAIL
)
6837 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6840 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6842 inst
.operands
[i
].reg
= val
;
6843 inst
.operands
[i
].isreg
= 1;
6844 inst
.operands
[i
].isvec
= 1;
6845 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6846 inst
.operands
[i
].vectype
= optype
;
6847 inst
.operands
[i
].present
= 1;
6849 if (rtype
== REG_TYPE_VFS
)
6853 if (skip_past_comma (&ptr
) == FAIL
)
6855 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6858 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6861 inst
.operands
[i
].reg
= val
;
6862 inst
.operands
[i
].isreg
= 1;
6863 inst
.operands
[i
].isvec
= 1;
6864 inst
.operands
[i
].issingle
= 1;
6865 inst
.operands
[i
].vectype
= optype
;
6866 inst
.operands
[i
].present
= 1;
6871 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6874 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6875 inst
.operands
[i
].reg
= val
;
6876 inst
.operands
[i
].isvec
= 1;
6877 inst
.operands
[i
].isscalar
= 2;
6878 inst
.operands
[i
].vectype
= optype
;
6879 inst
.operands
[i
++].present
= 1;
6881 if (skip_past_comma (&ptr
) == FAIL
)
6884 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6887 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6890 inst
.operands
[i
].reg
= val
;
6891 inst
.operands
[i
].isvec
= 1;
6892 inst
.operands
[i
].isscalar
= 2;
6893 inst
.operands
[i
].vectype
= optype
;
6894 inst
.operands
[i
].present
= 1;
6898 first_error (_("VFP single, double or MVE vector register"
6904 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6908 inst
.operands
[i
].reg
= val
;
6909 inst
.operands
[i
].isreg
= 1;
6910 inst
.operands
[i
].isvec
= 1;
6911 inst
.operands
[i
].issingle
= 1;
6912 inst
.operands
[i
].vectype
= optype
;
6913 inst
.operands
[i
].present
= 1;
6918 first_error (_("parse error"));
6922 /* Successfully parsed the operands. Update args. */
6928 first_error (_("expected comma"));
6932 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6936 /* Use this macro when the operand constraints are different
6937 for ARM and THUMB (e.g. ldrd). */
6938 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6939 ((arm_operand) | ((thumb_operand) << 16))
6941 /* Matcher codes for parse_operands. */
6942 enum operand_parse_code
6944 OP_stop
, /* end of line */
6946 OP_RR
, /* ARM register */
6947 OP_RRnpc
, /* ARM register, not r15 */
6948 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6949 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6950 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6951 optional trailing ! */
6952 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6953 OP_RCP
, /* Coprocessor number */
6954 OP_RCN
, /* Coprocessor register */
6955 OP_RF
, /* FPA register */
6956 OP_RVS
, /* VFP single precision register */
6957 OP_RVD
, /* VFP double precision register (0..15) */
6958 OP_RND
, /* Neon double precision register (0..31) */
6959 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6960 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6962 OP_RNQ
, /* Neon quad precision register */
6963 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6964 OP_RVSD
, /* VFP single or double precision register */
6965 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6966 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6967 OP_RNSD
, /* Neon single or double precision register */
6968 OP_RNDQ
, /* Neon double or quad precision register */
6969 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6970 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6971 OP_RNSDQ
, /* Neon single, double or quad precision register */
6972 OP_RNSC
, /* Neon scalar D[X] */
6973 OP_RVC
, /* VFP control register */
6974 OP_RMF
, /* Maverick F register */
6975 OP_RMD
, /* Maverick D register */
6976 OP_RMFX
, /* Maverick FX register */
6977 OP_RMDX
, /* Maverick DX register */
6978 OP_RMAX
, /* Maverick AX register */
6979 OP_RMDS
, /* Maverick DSPSC register */
6980 OP_RIWR
, /* iWMMXt wR register */
6981 OP_RIWC
, /* iWMMXt wC register */
6982 OP_RIWG
, /* iWMMXt wCG register */
6983 OP_RXA
, /* XScale accumulator register */
6985 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6987 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6989 OP_RMQ
, /* MVE vector register. */
6990 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6991 OP_RMQRR
, /* MVE vector or ARM register. */
6993 /* New operands for Armv8.1-M Mainline. */
6994 OP_LR
, /* ARM LR register */
6995 OP_RRe
, /* ARM register, only even numbered. */
6996 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6997 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6998 OP_RR_ZR
, /* ARM register or ZR but no PC */
7000 OP_REGLST
, /* ARM register list */
7001 OP_CLRMLST
, /* CLRM register list */
7002 OP_VRSLST
, /* VFP single-precision register list */
7003 OP_VRDLST
, /* VFP double-precision register list */
7004 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7005 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7006 OP_NSTRLST
, /* Neon element/structure list */
7007 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7008 OP_MSTRLST2
, /* MVE vector list with two elements. */
7009 OP_MSTRLST4
, /* MVE vector list with four elements. */
7011 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7012 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7013 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7014 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7016 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7017 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7018 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7019 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7021 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7022 scalar, or ARM register. */
7023 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7024 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7025 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7027 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7028 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7029 OP_VMOV
, /* Neon VMOV operands. */
7030 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7031 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7033 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7034 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7036 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7037 OP_VLDR
, /* VLDR operand. */
7039 OP_I0
, /* immediate zero */
7040 OP_I7
, /* immediate value 0 .. 7 */
7041 OP_I15
, /* 0 .. 15 */
7042 OP_I16
, /* 1 .. 16 */
7043 OP_I16z
, /* 0 .. 16 */
7044 OP_I31
, /* 0 .. 31 */
7045 OP_I31w
, /* 0 .. 31, optional trailing ! */
7046 OP_I32
, /* 1 .. 32 */
7047 OP_I32z
, /* 0 .. 32 */
7048 OP_I48_I64
, /* 48 or 64 */
7049 OP_I63
, /* 0 .. 63 */
7050 OP_I63s
, /* -64 .. 63 */
7051 OP_I64
, /* 1 .. 64 */
7052 OP_I64z
, /* 0 .. 64 */
7053 OP_I255
, /* 0 .. 255 */
7055 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7056 OP_I7b
, /* 0 .. 7 */
7057 OP_I15b
, /* 0 .. 15 */
7058 OP_I31b
, /* 0 .. 31 */
7060 OP_SH
, /* shifter operand */
7061 OP_SHG
, /* shifter operand with possible group relocation */
7062 OP_ADDR
, /* Memory address expression (any mode) */
7063 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7064 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7065 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7066 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7067 OP_EXP
, /* arbitrary expression */
7068 OP_EXPi
, /* same, with optional immediate prefix */
7069 OP_EXPr
, /* same, with optional relocation suffix */
7070 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7071 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7072 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7073 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7075 OP_CPSF
, /* CPS flags */
7076 OP_ENDI
, /* Endianness specifier */
7077 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7078 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7079 OP_COND
, /* conditional code */
7080 OP_TB
, /* Table branch. */
7082 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7084 OP_RRnpc_I0
, /* ARM register or literal 0 */
7085 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7086 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7087 OP_RF_IF
, /* FPA register or immediate */
7088 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7089 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7091 /* Optional operands. */
7092 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7093 OP_oI31b
, /* 0 .. 31 */
7094 OP_oI32b
, /* 1 .. 32 */
7095 OP_oI32z
, /* 0 .. 32 */
7096 OP_oIffffb
, /* 0 .. 65535 */
7097 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7099 OP_oRR
, /* ARM register */
7100 OP_oLR
, /* ARM LR register */
7101 OP_oRRnpc
, /* ARM register, not the PC */
7102 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7103 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7104 OP_oRND
, /* Optional Neon double precision register */
7105 OP_oRNQ
, /* Optional Neon quad precision register */
7106 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7107 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7108 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7109 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7111 OP_oSHll
, /* LSL immediate */
7112 OP_oSHar
, /* ASR immediate */
7113 OP_oSHllar
, /* LSL or ASR immediate */
7114 OP_oROR
, /* ROR 0/8/16/24 */
7115 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7117 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7119 /* Some pre-defined mixed (ARM/THUMB) operands. */
7120 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7121 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7122 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7124 OP_FIRST_OPTIONAL
= OP_oI7b
7127 /* Generic instruction operand parser. This does no encoding and no
7128 semantic validation; it merely squirrels values away in the inst
7129 structure. Returns SUCCESS or FAIL depending on whether the
7130 specified grammar matched. */
7132 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7134 unsigned const int *upat
= pattern
;
7135 char *backtrack_pos
= 0;
7136 const char *backtrack_error
= 0;
7137 int i
, val
= 0, backtrack_index
= 0;
7138 enum arm_reg_type rtype
;
7139 parse_operand_result result
;
7140 unsigned int op_parse_code
;
7141 bfd_boolean partial_match
;
7143 #define po_char_or_fail(chr) \
7146 if (skip_past_char (&str, chr) == FAIL) \
7151 #define po_reg_or_fail(regtype) \
7154 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7155 & inst.operands[i].vectype); \
7158 first_error (_(reg_expected_msgs[regtype])); \
7161 inst.operands[i].reg = val; \
7162 inst.operands[i].isreg = 1; \
7163 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7164 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7165 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7166 || rtype == REG_TYPE_VFD \
7167 || rtype == REG_TYPE_NQ); \
7168 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7172 #define po_reg_or_goto(regtype, label) \
7175 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7176 & inst.operands[i].vectype); \
7180 inst.operands[i].reg = val; \
7181 inst.operands[i].isreg = 1; \
7182 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7183 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7184 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7185 || rtype == REG_TYPE_VFD \
7186 || rtype == REG_TYPE_NQ); \
7187 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7191 #define po_imm_or_fail(min, max, popt) \
7194 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7196 inst.operands[i].imm = val; \
7200 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7204 my_get_expression (&exp, &str, popt); \
7205 if (exp.X_op != O_constant) \
7207 inst.error = _("constant expression required"); \
7210 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7212 inst.error = _("immediate value 48 or 64 expected"); \
7215 inst.operands[i].imm = exp.X_add_number; \
7219 #define po_scalar_or_goto(elsz, label, reg_type) \
7222 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7226 inst.operands[i].reg = val; \
7227 inst.operands[i].isscalar = 1; \
7231 #define po_misc_or_fail(expr) \
7239 #define po_misc_or_fail_no_backtrack(expr) \
7243 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7244 backtrack_pos = 0; \
7245 if (result != PARSE_OPERAND_SUCCESS) \
7250 #define po_barrier_or_imm(str) \
7253 val = parse_barrier (&str); \
7254 if (val == FAIL && ! ISALPHA (*str)) \
7257 /* ISB can only take SY as an option. */ \
7258 || ((inst.instruction & 0xf0) == 0x60 \
7261 inst.error = _("invalid barrier type"); \
7262 backtrack_pos = 0; \
7268 skip_whitespace (str
);
7270 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7272 op_parse_code
= upat
[i
];
7273 if (op_parse_code
>= 1<<16)
7274 op_parse_code
= thumb
? (op_parse_code
>> 16)
7275 : (op_parse_code
& ((1<<16)-1));
7277 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7279 /* Remember where we are in case we need to backtrack. */
7280 backtrack_pos
= str
;
7281 backtrack_error
= inst
.error
;
7282 backtrack_index
= i
;
7285 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7286 po_char_or_fail (',');
7288 switch (op_parse_code
)
7300 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7301 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7302 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7303 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7304 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7305 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7308 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7312 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7315 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7317 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7319 /* Also accept generic coprocessor regs for unknown registers. */
7321 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7323 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7324 existing register with a value of 0, this seems like the
7325 best way to parse P0. */
7327 if (strncasecmp (str
, "P0", 2) == 0)
7330 inst
.operands
[i
].isreg
= 1;
7331 inst
.operands
[i
].reg
= 13;
7336 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7337 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7338 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7339 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7340 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7341 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7342 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7343 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7344 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7345 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7348 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7351 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7352 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7354 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7359 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7363 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7365 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7368 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7370 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7373 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7375 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7380 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7383 po_reg_or_fail (REG_TYPE_NSDQ
);
7387 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7391 po_reg_or_fail (REG_TYPE_MQ
);
7393 /* Neon scalar. Using an element size of 8 means that some invalid
7394 scalars are accepted here, so deal with those in later code. */
7395 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7399 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7402 po_imm_or_fail (0, 0, TRUE
);
7407 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7411 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7416 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7419 if (parse_ifimm_zero (&str
))
7420 inst
.operands
[i
].imm
= 0;
7424 = _("only floating point zero is allowed as immediate value");
7432 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7435 po_reg_or_fail (REG_TYPE_RN
);
7439 case OP_RNSDQ_RNSC_MQ_RR
:
7440 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7443 case OP_RNSDQ_RNSC_MQ
:
7444 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7449 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7453 po_reg_or_fail (REG_TYPE_NSDQ
);
7460 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7463 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7466 po_reg_or_fail (REG_TYPE_NSD
);
7470 case OP_RNDQMQ_RNSC_RR
:
7471 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7474 case OP_RNDQ_RNSC_RR
:
7475 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7477 case OP_RNDQMQ_RNSC
:
7478 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7483 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7486 po_reg_or_fail (REG_TYPE_NDQ
);
7492 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7495 po_reg_or_fail (REG_TYPE_VFD
);
7500 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7501 not careful then bad things might happen. */
7502 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7505 case OP_RNDQMQ_Ibig
:
7506 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7511 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7514 /* There's a possibility of getting a 64-bit immediate here, so
7515 we need special handling. */
7516 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7519 inst
.error
= _("immediate value is out of range");
7525 case OP_RNDQMQ_I63b_RR
:
7526 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7529 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7534 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7537 po_imm_or_fail (0, 63, TRUE
);
7542 po_char_or_fail ('[');
7543 po_reg_or_fail (REG_TYPE_RN
);
7544 po_char_or_fail (']');
7550 po_reg_or_fail (REG_TYPE_RN
);
7551 if (skip_past_char (&str
, '!') == SUCCESS
)
7552 inst
.operands
[i
].writeback
= 1;
7556 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7557 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7558 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7559 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7560 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7561 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7562 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7563 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7564 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7565 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7566 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7567 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7568 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7570 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7572 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7573 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7575 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7576 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7577 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7578 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7580 /* Immediate variants */
7582 po_char_or_fail ('{');
7583 po_imm_or_fail (0, 255, TRUE
);
7584 po_char_or_fail ('}');
7588 /* The expression parser chokes on a trailing !, so we have
7589 to find it first and zap it. */
7592 while (*s
&& *s
!= ',')
7597 inst
.operands
[i
].writeback
= 1;
7599 po_imm_or_fail (0, 31, TRUE
);
7607 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7612 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7617 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7619 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7621 val
= parse_reloc (&str
);
7624 inst
.error
= _("unrecognized relocation suffix");
7627 else if (val
!= BFD_RELOC_UNUSED
)
7629 inst
.operands
[i
].imm
= val
;
7630 inst
.operands
[i
].hasreloc
= 1;
7636 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7638 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7640 inst
.operands
[i
].hasreloc
= 1;
7642 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7644 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7645 inst
.operands
[i
].hasreloc
= 0;
7649 /* Operand for MOVW or MOVT. */
7651 po_misc_or_fail (parse_half (&str
));
7654 /* Register or expression. */
7655 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7656 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7658 /* Register or immediate. */
7659 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7660 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7662 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7663 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7665 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7667 if (!is_immediate_prefix (*str
))
7670 val
= parse_fpa_immediate (&str
);
7673 /* FPA immediates are encoded as registers 8-15.
7674 parse_fpa_immediate has already applied the offset. */
7675 inst
.operands
[i
].reg
= val
;
7676 inst
.operands
[i
].isreg
= 1;
7679 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7680 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7682 /* Two kinds of register. */
7685 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7687 || (rege
->type
!= REG_TYPE_MMXWR
7688 && rege
->type
!= REG_TYPE_MMXWC
7689 && rege
->type
!= REG_TYPE_MMXWCG
))
7691 inst
.error
= _("iWMMXt data or control register expected");
7694 inst
.operands
[i
].reg
= rege
->number
;
7695 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7701 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7703 || (rege
->type
!= REG_TYPE_MMXWC
7704 && rege
->type
!= REG_TYPE_MMXWCG
))
7706 inst
.error
= _("iWMMXt control register expected");
7709 inst
.operands
[i
].reg
= rege
->number
;
7710 inst
.operands
[i
].isreg
= 1;
7715 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7716 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7717 case OP_oROR
: val
= parse_ror (&str
); break;
7719 case OP_COND
: val
= parse_cond (&str
); break;
7720 case OP_oBARRIER_I15
:
7721 po_barrier_or_imm (str
); break;
7723 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7729 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7730 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7732 inst
.error
= _("Banked registers are not available with this "
7738 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7742 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7745 val
= parse_sys_vldr_vstr (&str
);
7749 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7752 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7754 if (strncasecmp (str
, "APSR_", 5) == 0)
7761 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7762 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7763 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7764 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7765 default: found
= 16;
7769 inst
.operands
[i
].isvec
= 1;
7770 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7771 inst
.operands
[i
].reg
= REG_PC
;
7778 po_misc_or_fail (parse_tb (&str
));
7781 /* Register lists. */
7783 val
= parse_reg_list (&str
, REGLIST_RN
);
7786 inst
.operands
[i
].writeback
= 1;
7792 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7796 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7801 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7806 /* Allow Q registers too. */
7807 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7808 REGLIST_NEON_D
, &partial_match
);
7812 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7813 REGLIST_VFP_S
, &partial_match
);
7814 inst
.operands
[i
].issingle
= 1;
7819 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7820 REGLIST_VFP_D_VPR
, &partial_match
);
7821 if (val
== FAIL
&& !partial_match
)
7824 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7825 REGLIST_VFP_S_VPR
, &partial_match
);
7826 inst
.operands
[i
].issingle
= 1;
7831 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7832 REGLIST_NEON_D
, &partial_match
);
7837 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7838 1, &inst
.operands
[i
].vectype
);
7839 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7843 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7844 0, &inst
.operands
[i
].vectype
);
7847 /* Addressing modes */
7849 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7853 po_misc_or_fail (parse_address (&str
, i
));
7857 po_misc_or_fail_no_backtrack (
7858 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7862 po_misc_or_fail_no_backtrack (
7863 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7867 po_misc_or_fail_no_backtrack (
7868 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7872 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7876 po_misc_or_fail_no_backtrack (
7877 parse_shifter_operand_group_reloc (&str
, i
));
7881 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7885 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7889 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7894 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7899 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7902 po_reg_or_fail (REG_TYPE_ZR
);
7906 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7909 /* Various value-based sanity checks and shared operations. We
7910 do not signal immediate failures for the register constraints;
7911 this allows a syntax error to take precedence. */
7912 switch (op_parse_code
)
7920 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7921 inst
.error
= BAD_PC
;
7926 case OP_RRnpcsp_I32
:
7927 if (inst
.operands
[i
].isreg
)
7929 if (inst
.operands
[i
].reg
== REG_PC
)
7930 inst
.error
= BAD_PC
;
7931 else if (inst
.operands
[i
].reg
== REG_SP
7932 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7933 relaxed since ARMv8-A. */
7934 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7937 inst
.error
= BAD_SP
;
7943 if (inst
.operands
[i
].isreg
7944 && inst
.operands
[i
].reg
== REG_PC
7945 && (inst
.operands
[i
].writeback
|| thumb
))
7946 inst
.error
= BAD_PC
;
7951 if (inst
.operands
[i
].isreg
)
7961 case OP_oBARRIER_I15
:
7974 inst
.operands
[i
].imm
= val
;
7979 if (inst
.operands
[i
].reg
!= REG_LR
)
7980 inst
.error
= _("operand must be LR register");
7986 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7987 inst
.error
= BAD_PC
;
7991 if (inst
.operands
[i
].isreg
7992 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7993 inst
.error
= BAD_ODD
;
7997 if (inst
.operands
[i
].isreg
)
7999 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8000 inst
.error
= BAD_EVEN
;
8001 else if (inst
.operands
[i
].reg
== REG_SP
)
8002 as_tsktsk (MVE_BAD_SP
);
8003 else if (inst
.operands
[i
].reg
== REG_PC
)
8004 inst
.error
= BAD_PC
;
8012 /* If we get here, this operand was successfully parsed. */
8013 inst
.operands
[i
].present
= 1;
8017 inst
.error
= BAD_ARGS
;
8022 /* The parse routine should already have set inst.error, but set a
8023 default here just in case. */
8025 inst
.error
= BAD_SYNTAX
;
8029 /* Do not backtrack over a trailing optional argument that
8030 absorbed some text. We will only fail again, with the
8031 'garbage following instruction' error message, which is
8032 probably less helpful than the current one. */
8033 if (backtrack_index
== i
&& backtrack_pos
!= str
8034 && upat
[i
+1] == OP_stop
)
8037 inst
.error
= BAD_SYNTAX
;
8041 /* Try again, skipping the optional argument at backtrack_pos. */
8042 str
= backtrack_pos
;
8043 inst
.error
= backtrack_error
;
8044 inst
.operands
[backtrack_index
].present
= 0;
8045 i
= backtrack_index
;
8049 /* Check that we have parsed all the arguments. */
8050 if (*str
!= '\0' && !inst
.error
)
8051 inst
.error
= _("garbage following instruction");
8053 return inst
.error
? FAIL
: SUCCESS
;
8056 #undef po_char_or_fail
8057 #undef po_reg_or_fail
8058 #undef po_reg_or_goto
8059 #undef po_imm_or_fail
8060 #undef po_scalar_or_fail
8061 #undef po_barrier_or_imm
8063 /* Shorthand macro for instruction encoding functions issuing errors. */
8064 #define constraint(expr, err) \
8075 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8076 instructions are unpredictable if these registers are used. This
8077 is the BadReg predicate in ARM's Thumb-2 documentation.
8079 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8080 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8081 #define reject_bad_reg(reg) \
8083 if (reg == REG_PC) \
8085 inst.error = BAD_PC; \
8088 else if (reg == REG_SP \
8089 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8091 inst.error = BAD_SP; \
8096 /* If REG is R13 (the stack pointer), warn that its use is
8098 #define warn_deprecated_sp(reg) \
8100 if (warn_on_deprecated && reg == REG_SP) \
8101 as_tsktsk (_("use of r13 is deprecated")); \
8104 /* Functions for operand encoding. ARM, then Thumb. */
8106 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8108 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8110 The only binary encoding difference is the Coprocessor number. Coprocessor
8111 9 is used for half-precision calculations or conversions. The format of the
8112 instruction is the same as the equivalent Coprocessor 10 instruction that
8113 exists for Single-Precision operation. */
8116 do_scalar_fp16_v82_encode (void)
8118 if (inst
.cond
< COND_ALWAYS
)
8119 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8120 " the behaviour is UNPREDICTABLE"));
8121 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8124 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8125 mark_feature_used (&arm_ext_fp16
);
8128 /* If VAL can be encoded in the immediate field of an ARM instruction,
8129 return the encoded form. Otherwise, return FAIL. */
8132 encode_arm_immediate (unsigned int val
)
8139 for (i
= 2; i
< 32; i
+= 2)
8140 if ((a
= rotate_left (val
, i
)) <= 0xff)
8141 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8146 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8147 return the encoded form. Otherwise, return FAIL. */
8149 encode_thumb32_immediate (unsigned int val
)
8156 for (i
= 1; i
<= 24; i
++)
8159 if ((val
& ~(0xff << i
)) == 0)
8160 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8164 if (val
== ((a
<< 16) | a
))
8166 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8170 if (val
== ((a
<< 16) | a
))
8171 return 0x200 | (a
>> 8);
8175 /* Encode a VFP SP or DP register number into inst.instruction. */
8178 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8180 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8183 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8186 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8189 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8194 first_error (_("D register out of range for selected VFP version"));
8202 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8206 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8210 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8214 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8218 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8222 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8230 /* Encode a <shift> in an ARM-format instruction. The immediate,
8231 if any, is handled by md_apply_fix. */
8233 encode_arm_shift (int i
)
8235 /* register-shifted register. */
8236 if (inst
.operands
[i
].immisreg
)
8239 for (op_index
= 0; op_index
<= i
; ++op_index
)
8241 /* Check the operand only when it's presented. In pre-UAL syntax,
8242 if the destination register is the same as the first operand, two
8243 register form of the instruction can be used. */
8244 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8245 && inst
.operands
[op_index
].reg
== REG_PC
)
8246 as_warn (UNPRED_REG ("r15"));
8249 if (inst
.operands
[i
].imm
== REG_PC
)
8250 as_warn (UNPRED_REG ("r15"));
8253 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8254 inst
.instruction
|= SHIFT_ROR
<< 5;
8257 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8258 if (inst
.operands
[i
].immisreg
)
8260 inst
.instruction
|= SHIFT_BY_REG
;
8261 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8264 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8269 encode_arm_shifter_operand (int i
)
8271 if (inst
.operands
[i
].isreg
)
8273 inst
.instruction
|= inst
.operands
[i
].reg
;
8274 encode_arm_shift (i
);
8278 inst
.instruction
|= INST_IMMEDIATE
;
8279 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8280 inst
.instruction
|= inst
.operands
[i
].imm
;
8284 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8286 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8289 Generate an error if the operand is not a register. */
8290 constraint (!inst
.operands
[i
].isreg
,
8291 _("Instruction does not support =N addresses"));
8293 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8295 if (inst
.operands
[i
].preind
)
8299 inst
.error
= _("instruction does not accept preindexed addressing");
8302 inst
.instruction
|= PRE_INDEX
;
8303 if (inst
.operands
[i
].writeback
)
8304 inst
.instruction
|= WRITE_BACK
;
8307 else if (inst
.operands
[i
].postind
)
8309 gas_assert (inst
.operands
[i
].writeback
);
8311 inst
.instruction
|= WRITE_BACK
;
8313 else /* unindexed - only for coprocessor */
8315 inst
.error
= _("instruction does not accept unindexed addressing");
8319 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8320 && (((inst
.instruction
& 0x000f0000) >> 16)
8321 == ((inst
.instruction
& 0x0000f000) >> 12)))
8322 as_warn ((inst
.instruction
& LOAD_BIT
)
8323 ? _("destination register same as write-back base")
8324 : _("source register same as write-back base"));
8327 /* inst.operands[i] was set up by parse_address. Encode it into an
8328 ARM-format mode 2 load or store instruction. If is_t is true,
8329 reject forms that cannot be used with a T instruction (i.e. not
8332 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8334 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8336 encode_arm_addr_mode_common (i
, is_t
);
8338 if (inst
.operands
[i
].immisreg
)
8340 constraint ((inst
.operands
[i
].imm
== REG_PC
8341 || (is_pc
&& inst
.operands
[i
].writeback
)),
8343 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8344 inst
.instruction
|= inst
.operands
[i
].imm
;
8345 if (!inst
.operands
[i
].negative
)
8346 inst
.instruction
|= INDEX_UP
;
8347 if (inst
.operands
[i
].shifted
)
8349 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8350 inst
.instruction
|= SHIFT_ROR
<< 5;
8353 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8354 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8358 else /* immediate offset in inst.relocs[0] */
8360 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8362 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8364 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8365 cannot use PC in addressing.
8366 PC cannot be used in writeback addressing, either. */
8367 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8370 /* Use of PC in str is deprecated for ARMv7. */
8371 if (warn_on_deprecated
8373 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8374 as_tsktsk (_("use of PC in this instruction is deprecated"));
8377 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8379 /* Prefer + for zero encoded value. */
8380 if (!inst
.operands
[i
].negative
)
8381 inst
.instruction
|= INDEX_UP
;
8382 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8387 /* inst.operands[i] was set up by parse_address. Encode it into an
8388 ARM-format mode 3 load or store instruction. Reject forms that
8389 cannot be used with such instructions. If is_t is true, reject
8390 forms that cannot be used with a T instruction (i.e. not
8393 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8395 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8397 inst
.error
= _("instruction does not accept scaled register index");
8401 encode_arm_addr_mode_common (i
, is_t
);
8403 if (inst
.operands
[i
].immisreg
)
8405 constraint ((inst
.operands
[i
].imm
== REG_PC
8406 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8408 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8410 inst
.instruction
|= inst
.operands
[i
].imm
;
8411 if (!inst
.operands
[i
].negative
)
8412 inst
.instruction
|= INDEX_UP
;
8414 else /* immediate offset in inst.relocs[0] */
8416 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8417 && inst
.operands
[i
].writeback
),
8419 inst
.instruction
|= HWOFFSET_IMM
;
8420 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8422 /* Prefer + for zero encoded value. */
8423 if (!inst
.operands
[i
].negative
)
8424 inst
.instruction
|= INDEX_UP
;
8426 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8431 /* Write immediate bits [7:0] to the following locations:
8433 |28/24|23 19|18 16|15 4|3 0|
8434 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8436 This function is used by VMOV/VMVN/VORR/VBIC. */
8439 neon_write_immbits (unsigned immbits
)
8441 inst
.instruction
|= immbits
& 0xf;
8442 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8443 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8446 /* Invert low-order SIZE bits of XHI:XLO. */
8449 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8451 unsigned immlo
= xlo
? *xlo
: 0;
8452 unsigned immhi
= xhi
? *xhi
: 0;
8457 immlo
= (~immlo
) & 0xff;
8461 immlo
= (~immlo
) & 0xffff;
8465 immhi
= (~immhi
) & 0xffffffff;
8469 immlo
= (~immlo
) & 0xffffffff;
8483 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8487 neon_bits_same_in_bytes (unsigned imm
)
8489 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8490 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8491 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8492 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8495 /* For immediate of above form, return 0bABCD. */
8498 neon_squash_bits (unsigned imm
)
8500 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8501 | ((imm
& 0x01000000) >> 21);
8504 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8507 neon_qfloat_bits (unsigned imm
)
8509 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8512 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8513 the instruction. *OP is passed as the initial value of the op field, and
8514 may be set to a different value depending on the constant (i.e.
8515 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8516 MVN). If the immediate looks like a repeated pattern then also
8517 try smaller element sizes. */
8520 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8521 unsigned *immbits
, int *op
, int size
,
8522 enum neon_el_type type
)
8524 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8526 if (type
== NT_float
&& !float_p
)
8529 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8531 if (size
!= 32 || *op
== 1)
8533 *immbits
= neon_qfloat_bits (immlo
);
8539 if (neon_bits_same_in_bytes (immhi
)
8540 && neon_bits_same_in_bytes (immlo
))
8544 *immbits
= (neon_squash_bits (immhi
) << 4)
8545 | neon_squash_bits (immlo
);
8556 if (immlo
== (immlo
& 0x000000ff))
8561 else if (immlo
== (immlo
& 0x0000ff00))
8563 *immbits
= immlo
>> 8;
8566 else if (immlo
== (immlo
& 0x00ff0000))
8568 *immbits
= immlo
>> 16;
8571 else if (immlo
== (immlo
& 0xff000000))
8573 *immbits
= immlo
>> 24;
8576 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8578 *immbits
= (immlo
>> 8) & 0xff;
8581 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8583 *immbits
= (immlo
>> 16) & 0xff;
8587 if ((immlo
& 0xffff) != (immlo
>> 16))
8594 if (immlo
== (immlo
& 0x000000ff))
8599 else if (immlo
== (immlo
& 0x0000ff00))
8601 *immbits
= immlo
>> 8;
8605 if ((immlo
& 0xff) != (immlo
>> 8))
8610 if (immlo
== (immlo
& 0x000000ff))
8612 /* Don't allow MVN with 8-bit immediate. */
8622 #if defined BFD_HOST_64_BIT
8623 /* Returns TRUE if double precision value V may be cast
8624 to single precision without loss of accuracy. */
8627 is_double_a_single (bfd_int64_t v
)
8629 int exp
= (int)((v
>> 52) & 0x7FF);
8630 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8632 return (exp
== 0 || exp
== 0x7FF
8633 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8634 && (mantissa
& 0x1FFFFFFFl
) == 0;
8637 /* Returns a double precision value casted to single precision
8638 (ignoring the least significant bits in exponent and mantissa). */
8641 double_to_single (bfd_int64_t v
)
8643 int sign
= (int) ((v
>> 63) & 1l);
8644 int exp
= (int) ((v
>> 52) & 0x7FF);
8645 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8651 exp
= exp
- 1023 + 127;
8660 /* No denormalized numbers. */
8666 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8668 #endif /* BFD_HOST_64_BIT */
8677 static void do_vfp_nsyn_opcode (const char *);
8679 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8680 Determine whether it can be performed with a move instruction; if
8681 it can, convert inst.instruction to that move instruction and
8682 return TRUE; if it can't, convert inst.instruction to a literal-pool
8683 load and return FALSE. If this is not a valid thing to do in the
8684 current context, set inst.error and return TRUE.
8686 inst.operands[i] describes the destination register. */
8689 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8692 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8693 bfd_boolean arm_p
= (t
== CONST_ARM
);
8696 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8700 if ((inst
.instruction
& tbit
) == 0)
8702 inst
.error
= _("invalid pseudo operation");
8706 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8707 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8708 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8710 inst
.error
= _("constant expression expected");
8714 if (inst
.relocs
[0].exp
.X_op
== O_constant
8715 || inst
.relocs
[0].exp
.X_op
== O_big
)
8717 #if defined BFD_HOST_64_BIT
8722 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8724 LITTLENUM_TYPE w
[X_PRECISION
];
8727 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8729 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8731 /* FIXME: Should we check words w[2..5] ? */
8736 #if defined BFD_HOST_64_BIT
8738 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8739 << LITTLENUM_NUMBER_OF_BITS
)
8740 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8741 << LITTLENUM_NUMBER_OF_BITS
)
8742 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8743 << LITTLENUM_NUMBER_OF_BITS
)
8744 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8746 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8747 | (l
[0] & LITTLENUM_MASK
);
8751 v
= inst
.relocs
[0].exp
.X_add_number
;
8753 if (!inst
.operands
[i
].issingle
)
8757 /* LDR should not use lead in a flag-setting instruction being
8758 chosen so we do not check whether movs can be used. */
8760 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8761 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8762 && inst
.operands
[i
].reg
!= 13
8763 && inst
.operands
[i
].reg
!= 15)
8765 /* Check if on thumb2 it can be done with a mov.w, mvn or
8766 movw instruction. */
8767 unsigned int newimm
;
8768 bfd_boolean isNegated
;
8770 newimm
= encode_thumb32_immediate (v
);
8771 if (newimm
!= (unsigned int) FAIL
)
8775 newimm
= encode_thumb32_immediate (~v
);
8776 if (newimm
!= (unsigned int) FAIL
)
8780 /* The number can be loaded with a mov.w or mvn
8782 if (newimm
!= (unsigned int) FAIL
8783 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8785 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8786 | (inst
.operands
[i
].reg
<< 8));
8787 /* Change to MOVN. */
8788 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8789 inst
.instruction
|= (newimm
& 0x800) << 15;
8790 inst
.instruction
|= (newimm
& 0x700) << 4;
8791 inst
.instruction
|= (newimm
& 0x0ff);
8794 /* The number can be loaded with a movw instruction. */
8795 else if ((v
& ~0xFFFF) == 0
8796 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8798 int imm
= v
& 0xFFFF;
8800 inst
.instruction
= 0xf2400000; /* MOVW. */
8801 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8802 inst
.instruction
|= (imm
& 0xf000) << 4;
8803 inst
.instruction
|= (imm
& 0x0800) << 15;
8804 inst
.instruction
|= (imm
& 0x0700) << 4;
8805 inst
.instruction
|= (imm
& 0x00ff);
8806 /* In case this replacement is being done on Armv8-M
8807 Baseline we need to make sure to disable the
8808 instruction size check, as otherwise GAS will reject
8809 the use of this T32 instruction. */
8817 int value
= encode_arm_immediate (v
);
8821 /* This can be done with a mov instruction. */
8822 inst
.instruction
&= LITERAL_MASK
;
8823 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8824 inst
.instruction
|= value
& 0xfff;
8828 value
= encode_arm_immediate (~ v
);
8831 /* This can be done with a mvn instruction. */
8832 inst
.instruction
&= LITERAL_MASK
;
8833 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8834 inst
.instruction
|= value
& 0xfff;
8838 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8841 unsigned immbits
= 0;
8842 unsigned immlo
= inst
.operands
[1].imm
;
8843 unsigned immhi
= inst
.operands
[1].regisimm
8844 ? inst
.operands
[1].reg
8845 : inst
.relocs
[0].exp
.X_unsigned
8847 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8848 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8849 &op
, 64, NT_invtype
);
8853 neon_invert_size (&immlo
, &immhi
, 64);
8855 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8856 &op
, 64, NT_invtype
);
8861 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8867 /* Fill other bits in vmov encoding for both thumb and arm. */
8869 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8871 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8872 neon_write_immbits (immbits
);
8880 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8881 if (inst
.operands
[i
].issingle
8882 && is_quarter_float (inst
.operands
[1].imm
)
8883 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8885 inst
.operands
[1].imm
=
8886 neon_qfloat_bits (v
);
8887 do_vfp_nsyn_opcode ("fconsts");
8891 /* If our host does not support a 64-bit type then we cannot perform
8892 the following optimization. This mean that there will be a
8893 discrepancy between the output produced by an assembler built for
8894 a 32-bit-only host and the output produced from a 64-bit host, but
8895 this cannot be helped. */
8896 #if defined BFD_HOST_64_BIT
8897 else if (!inst
.operands
[1].issingle
8898 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8900 if (is_double_a_single (v
)
8901 && is_quarter_float (double_to_single (v
)))
8903 inst
.operands
[1].imm
=
8904 neon_qfloat_bits (double_to_single (v
));
8905 do_vfp_nsyn_opcode ("fconstd");
8913 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8914 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8917 inst
.operands
[1].reg
= REG_PC
;
8918 inst
.operands
[1].isreg
= 1;
8919 inst
.operands
[1].preind
= 1;
8920 inst
.relocs
[0].pc_rel
= 1;
8921 inst
.relocs
[0].type
= (thumb_p
8922 ? BFD_RELOC_ARM_THUMB_OFFSET
8924 ? BFD_RELOC_ARM_HWLITERAL
8925 : BFD_RELOC_ARM_LITERAL
));
8929 /* inst.operands[i] was set up by parse_address. Encode it into an
8930 ARM-format instruction. Reject all forms which cannot be encoded
8931 into a coprocessor load/store instruction. If wb_ok is false,
8932 reject use of writeback; if unind_ok is false, reject use of
8933 unindexed addressing. If reloc_override is not 0, use it instead
8934 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8935 (in which case it is preserved). */
8938 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8940 if (!inst
.operands
[i
].isreg
)
8943 if (! inst
.operands
[0].isvec
)
8945 inst
.error
= _("invalid co-processor operand");
8948 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8952 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8954 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8956 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8958 gas_assert (!inst
.operands
[i
].writeback
);
8961 inst
.error
= _("instruction does not support unindexed addressing");
8964 inst
.instruction
|= inst
.operands
[i
].imm
;
8965 inst
.instruction
|= INDEX_UP
;
8969 if (inst
.operands
[i
].preind
)
8970 inst
.instruction
|= PRE_INDEX
;
8972 if (inst
.operands
[i
].writeback
)
8974 if (inst
.operands
[i
].reg
== REG_PC
)
8976 inst
.error
= _("pc may not be used with write-back");
8981 inst
.error
= _("instruction does not support writeback");
8984 inst
.instruction
|= WRITE_BACK
;
8988 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8989 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8990 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8991 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8994 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8996 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8999 /* Prefer + for zero encoded value. */
9000 if (!inst
.operands
[i
].negative
)
9001 inst
.instruction
|= INDEX_UP
;
9006 /* Functions for instruction encoding, sorted by sub-architecture.
9007 First some generics; their names are taken from the conventional
9008 bit positions for register arguments in ARM format instructions. */
9018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9031 inst
.instruction
|= inst
.operands
[1].reg
;
9037 inst
.instruction
|= inst
.operands
[0].reg
;
9038 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9045 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9051 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9052 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9058 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9059 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9063 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9065 if (ARM_CPU_IS_ANY (cpu_variant
))
9067 as_tsktsk ("%s", msg
);
9070 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9082 unsigned Rn
= inst
.operands
[2].reg
;
9083 /* Enforce restrictions on SWP instruction. */
9084 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9086 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9087 _("Rn must not overlap other operands"));
9089 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9091 if (!check_obsolete (&arm_ext_v8
,
9092 _("swp{b} use is obsoleted for ARMv8 and later"))
9093 && warn_on_deprecated
9094 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9095 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 inst
.instruction
|= inst
.operands
[1].reg
;
9100 inst
.instruction
|= Rn
<< 16;
9106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9108 inst
.instruction
|= inst
.operands
[2].reg
;
9114 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9115 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9116 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9117 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9119 inst
.instruction
|= inst
.operands
[0].reg
;
9120 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9121 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9127 inst
.instruction
|= inst
.operands
[0].imm
;
9133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9134 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9137 /* ARM instructions, in alphabetical order by function name (except
9138 that wrapper functions appear immediately after the function they
9141 /* This is a pseudo-op of the form "adr rd, label" to be converted
9142 into a relative address of the form "add rd, pc, #label-.-8". */
9147 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9149 /* Frag hacking will turn this into a sub instruction if the offset turns
9150 out to be negative. */
9151 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9152 inst
.relocs
[0].pc_rel
= 1;
9153 inst
.relocs
[0].exp
.X_add_number
-= 8;
9155 if (support_interwork
9156 && inst
.relocs
[0].exp
.X_op
== O_symbol
9157 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9158 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9159 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9160 inst
.relocs
[0].exp
.X_add_number
|= 1;
9163 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9164 into a relative address of the form:
9165 add rd, pc, #low(label-.-8)"
9166 add rd, rd, #high(label-.-8)" */
9171 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9173 /* Frag hacking will turn this into a sub instruction if the offset turns
9174 out to be negative. */
9175 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9176 inst
.relocs
[0].pc_rel
= 1;
9177 inst
.size
= INSN_SIZE
* 2;
9178 inst
.relocs
[0].exp
.X_add_number
-= 8;
9180 if (support_interwork
9181 && inst
.relocs
[0].exp
.X_op
== O_symbol
9182 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9183 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9184 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9185 inst
.relocs
[0].exp
.X_add_number
|= 1;
9191 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9192 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9194 if (!inst
.operands
[1].present
)
9195 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9196 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9197 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9198 encode_arm_shifter_operand (2);
9204 if (inst
.operands
[0].present
)
9205 inst
.instruction
|= inst
.operands
[0].imm
;
9207 inst
.instruction
|= 0xf;
9213 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9214 constraint (msb
> 32, _("bit-field extends past end of register"));
9215 /* The instruction encoding stores the LSB and MSB,
9216 not the LSB and width. */
9217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9218 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9219 inst
.instruction
|= (msb
- 1) << 16;
9227 /* #0 in second position is alternative syntax for bfc, which is
9228 the same instruction but with REG_PC in the Rm field. */
9229 if (!inst
.operands
[1].isreg
)
9230 inst
.operands
[1].reg
= REG_PC
;
9232 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9233 constraint (msb
> 32, _("bit-field extends past end of register"));
9234 /* The instruction encoding stores the LSB and MSB,
9235 not the LSB and width. */
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9237 inst
.instruction
|= inst
.operands
[1].reg
;
9238 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9239 inst
.instruction
|= (msb
- 1) << 16;
9245 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9246 _("bit-field extends past end of register"));
9247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9248 inst
.instruction
|= inst
.operands
[1].reg
;
9249 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9250 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9253 /* ARM V5 breakpoint instruction (argument parse)
9254 BKPT <16 bit unsigned immediate>
9255 Instruction is not conditional.
9256 The bit pattern given in insns[] has the COND_ALWAYS condition,
9257 and it is an error if the caller tried to override that. */
9262 /* Top 12 of 16 bits to bits 19:8. */
9263 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9265 /* Bottom 4 of 16 bits to bits 3:0. */
9266 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9270 encode_branch (int default_reloc
)
9272 if (inst
.operands
[0].hasreloc
)
9274 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9275 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9276 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9277 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9278 ? BFD_RELOC_ARM_PLT32
9279 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9282 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9283 inst
.relocs
[0].pc_rel
= 1;
9290 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9291 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9294 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9301 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9303 if (inst
.cond
== COND_ALWAYS
)
9304 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9306 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9310 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9313 /* ARM V5 branch-link-exchange instruction (argument parse)
9314 BLX <target_addr> ie BLX(1)
9315 BLX{<condition>} <Rm> ie BLX(2)
9316 Unfortunately, there are two different opcodes for this mnemonic.
9317 So, the insns[].value is not used, and the code here zaps values
9318 into inst.instruction.
9319 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9324 if (inst
.operands
[0].isreg
)
9326 /* Arg is a register; the opcode provided by insns[] is correct.
9327 It is not illegal to do "blx pc", just useless. */
9328 if (inst
.operands
[0].reg
== REG_PC
)
9329 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9331 inst
.instruction
|= inst
.operands
[0].reg
;
9335 /* Arg is an address; this instruction cannot be executed
9336 conditionally, and the opcode must be adjusted.
9337 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9338 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9339 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9340 inst
.instruction
= 0xfa000000;
9341 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9348 bfd_boolean want_reloc
;
9350 if (inst
.operands
[0].reg
== REG_PC
)
9351 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9353 inst
.instruction
|= inst
.operands
[0].reg
;
9354 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9355 it is for ARMv4t or earlier. */
9356 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9357 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9358 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9362 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9367 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9371 /* ARM v5TEJ. Jump to Jazelle code. */
9376 if (inst
.operands
[0].reg
== REG_PC
)
9377 as_tsktsk (_("use of r15 in bxj is not really useful"));
9379 inst
.instruction
|= inst
.operands
[0].reg
;
9382 /* Co-processor data operation:
9383 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9384 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9388 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9389 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9390 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9391 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9392 inst
.instruction
|= inst
.operands
[4].reg
;
9393 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9399 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9400 encode_arm_shifter_operand (1);
9403 /* Transfer between coprocessor and ARM registers.
9404 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9409 No special properties. */
9411 struct deprecated_coproc_regs_s
9418 arm_feature_set deprecated
;
9419 arm_feature_set obsoleted
;
9420 const char *dep_msg
;
9421 const char *obs_msg
;
9424 #define DEPR_ACCESS_V8 \
9425 N_("This coprocessor register access is deprecated in ARMv8")
9427 /* Table of all deprecated coprocessor registers. */
9428 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9430 {15, 0, 7, 10, 5, /* CP15DMB. */
9431 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9432 DEPR_ACCESS_V8
, NULL
},
9433 {15, 0, 7, 10, 4, /* CP15DSB. */
9434 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9435 DEPR_ACCESS_V8
, NULL
},
9436 {15, 0, 7, 5, 4, /* CP15ISB. */
9437 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9438 DEPR_ACCESS_V8
, NULL
},
9439 {14, 6, 1, 0, 0, /* TEEHBR. */
9440 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9441 DEPR_ACCESS_V8
, NULL
},
9442 {14, 6, 0, 0, 0, /* TEECR. */
9443 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9444 DEPR_ACCESS_V8
, NULL
},
9447 #undef DEPR_ACCESS_V8
9449 static const size_t deprecated_coproc_reg_count
=
9450 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9458 Rd
= inst
.operands
[2].reg
;
9461 if (inst
.instruction
== 0xee000010
9462 || inst
.instruction
== 0xfe000010)
9464 reject_bad_reg (Rd
);
9465 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9467 constraint (Rd
== REG_SP
, BAD_SP
);
9472 if (inst
.instruction
== 0xe000010)
9473 constraint (Rd
== REG_PC
, BAD_PC
);
9476 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9478 const struct deprecated_coproc_regs_s
*r
=
9479 deprecated_coproc_regs
+ i
;
9481 if (inst
.operands
[0].reg
== r
->cp
9482 && inst
.operands
[1].imm
== r
->opc1
9483 && inst
.operands
[3].reg
== r
->crn
9484 && inst
.operands
[4].reg
== r
->crm
9485 && inst
.operands
[5].imm
== r
->opc2
)
9487 if (! ARM_CPU_IS_ANY (cpu_variant
)
9488 && warn_on_deprecated
9489 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9490 as_tsktsk ("%s", r
->dep_msg
);
9494 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9495 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9496 inst
.instruction
|= Rd
<< 12;
9497 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9498 inst
.instruction
|= inst
.operands
[4].reg
;
9499 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9502 /* Transfer between coprocessor register and pair of ARM registers.
9503 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9508 Two XScale instructions are special cases of these:
9510 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9511 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9513 Result unpredictable if Rd or Rn is R15. */
9520 Rd
= inst
.operands
[2].reg
;
9521 Rn
= inst
.operands
[3].reg
;
9525 reject_bad_reg (Rd
);
9526 reject_bad_reg (Rn
);
9530 constraint (Rd
== REG_PC
, BAD_PC
);
9531 constraint (Rn
== REG_PC
, BAD_PC
);
9534 /* Only check the MRRC{2} variants. */
9535 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9537 /* If Rd == Rn, error that the operation is
9538 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9539 constraint (Rd
== Rn
, BAD_OVERLAP
);
9542 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9543 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9544 inst
.instruction
|= Rd
<< 12;
9545 inst
.instruction
|= Rn
<< 16;
9546 inst
.instruction
|= inst
.operands
[4].reg
;
9552 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9553 if (inst
.operands
[1].present
)
9555 inst
.instruction
|= CPSI_MMOD
;
9556 inst
.instruction
|= inst
.operands
[1].imm
;
9563 inst
.instruction
|= inst
.operands
[0].imm
;
9569 unsigned Rd
, Rn
, Rm
;
9571 Rd
= inst
.operands
[0].reg
;
9572 Rn
= (inst
.operands
[1].present
9573 ? inst
.operands
[1].reg
: Rd
);
9574 Rm
= inst
.operands
[2].reg
;
9576 constraint ((Rd
== REG_PC
), BAD_PC
);
9577 constraint ((Rn
== REG_PC
), BAD_PC
);
9578 constraint ((Rm
== REG_PC
), BAD_PC
);
9580 inst
.instruction
|= Rd
<< 16;
9581 inst
.instruction
|= Rn
<< 0;
9582 inst
.instruction
|= Rm
<< 8;
9588 /* There is no IT instruction in ARM mode. We
9589 process it to do the validation as if in
9590 thumb mode, just in case the code gets
9591 assembled for thumb using the unified syntax. */
9596 set_pred_insn_type (IT_INSN
);
9597 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9598 now_pred
.cc
= inst
.operands
[0].imm
;
9602 /* If there is only one register in the register list,
9603 then return its register number. Otherwise return -1. */
9605 only_one_reg_in_list (int range
)
9607 int i
= ffs (range
) - 1;
9608 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9612 encode_ldmstm(int from_push_pop_mnem
)
9614 int base_reg
= inst
.operands
[0].reg
;
9615 int range
= inst
.operands
[1].imm
;
9618 inst
.instruction
|= base_reg
<< 16;
9619 inst
.instruction
|= range
;
9621 if (inst
.operands
[1].writeback
)
9622 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9624 if (inst
.operands
[0].writeback
)
9626 inst
.instruction
|= WRITE_BACK
;
9627 /* Check for unpredictable uses of writeback. */
9628 if (inst
.instruction
& LOAD_BIT
)
9630 /* Not allowed in LDM type 2. */
9631 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9632 && ((range
& (1 << REG_PC
)) == 0))
9633 as_warn (_("writeback of base register is UNPREDICTABLE"));
9634 /* Only allowed if base reg not in list for other types. */
9635 else if (range
& (1 << base_reg
))
9636 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9640 /* Not allowed for type 2. */
9641 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9642 as_warn (_("writeback of base register is UNPREDICTABLE"));
9643 /* Only allowed if base reg not in list, or first in list. */
9644 else if ((range
& (1 << base_reg
))
9645 && (range
& ((1 << base_reg
) - 1)))
9646 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9650 /* If PUSH/POP has only one register, then use the A2 encoding. */
9651 one_reg
= only_one_reg_in_list (range
);
9652 if (from_push_pop_mnem
&& one_reg
>= 0)
9654 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9656 if (is_push
&& one_reg
== 13 /* SP */)
9657 /* PR 22483: The A2 encoding cannot be used when
9658 pushing the stack pointer as this is UNPREDICTABLE. */
9661 inst
.instruction
&= A_COND_MASK
;
9662 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9663 inst
.instruction
|= one_reg
<< 12;
9670 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9673 /* ARMv5TE load-consecutive (argument parse)
9682 constraint (inst
.operands
[0].reg
% 2 != 0,
9683 _("first transfer register must be even"));
9684 constraint (inst
.operands
[1].present
9685 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9686 _("can only transfer two consecutive registers"));
9687 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9688 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9690 if (!inst
.operands
[1].present
)
9691 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9693 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9694 register and the first register written; we have to diagnose
9695 overlap between the base and the second register written here. */
9697 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9698 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9699 as_warn (_("base register written back, and overlaps "
9700 "second transfer register"));
9702 if (!(inst
.instruction
& V4_STR_BIT
))
9704 /* For an index-register load, the index register must not overlap the
9705 destination (even if not write-back). */
9706 if (inst
.operands
[2].immisreg
9707 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9708 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9709 as_warn (_("index register overlaps transfer register"));
9711 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9712 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9718 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9719 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9720 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9721 || inst
.operands
[1].negative
9722 /* This can arise if the programmer has written
9724 or if they have mistakenly used a register name as the last
9727 It is very difficult to distinguish between these two cases
9728 because "rX" might actually be a label. ie the register
9729 name has been occluded by a symbol of the same name. So we
9730 just generate a general 'bad addressing mode' type error
9731 message and leave it up to the programmer to discover the
9732 true cause and fix their mistake. */
9733 || (inst
.operands
[1].reg
== REG_PC
),
9736 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9737 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9738 _("offset must be zero in ARM encoding"));
9740 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9742 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9743 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9744 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9750 constraint (inst
.operands
[0].reg
% 2 != 0,
9751 _("even register required"));
9752 constraint (inst
.operands
[1].present
9753 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9754 _("can only load two consecutive registers"));
9755 /* If op 1 were present and equal to PC, this function wouldn't
9756 have been called in the first place. */
9757 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9760 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9763 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9764 which is not a multiple of four is UNPREDICTABLE. */
9766 check_ldr_r15_aligned (void)
9768 constraint (!(inst
.operands
[1].immisreg
)
9769 && (inst
.operands
[0].reg
== REG_PC
9770 && inst
.operands
[1].reg
== REG_PC
9771 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9772 _("ldr to register 15 must be 4-byte aligned"));
9778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9779 if (!inst
.operands
[1].isreg
)
9780 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9782 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9783 check_ldr_r15_aligned ();
9789 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9791 if (inst
.operands
[1].preind
)
9793 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9794 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9795 _("this instruction requires a post-indexed address"));
9797 inst
.operands
[1].preind
= 0;
9798 inst
.operands
[1].postind
= 1;
9799 inst
.operands
[1].writeback
= 1;
9801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9802 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9805 /* Halfword and signed-byte load/store operations. */
9810 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9811 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9812 if (!inst
.operands
[1].isreg
)
9813 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9815 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9821 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9823 if (inst
.operands
[1].preind
)
9825 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9826 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9827 _("this instruction requires a post-indexed address"));
9829 inst
.operands
[1].preind
= 0;
9830 inst
.operands
[1].postind
= 1;
9831 inst
.operands
[1].writeback
= 1;
9833 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9834 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9837 /* Co-processor register load/store.
9838 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9842 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9843 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9844 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9850 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9851 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9852 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9853 && !(inst
.instruction
& 0x00400000))
9854 as_tsktsk (_("Rd and Rm should be different in mla"));
9856 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9857 inst
.instruction
|= inst
.operands
[1].reg
;
9858 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9859 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9865 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9866 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9869 encode_arm_shifter_operand (1);
9872 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9879 top
= (inst
.instruction
& 0x00400000) != 0;
9880 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9881 _(":lower16: not allowed in this instruction"));
9882 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9883 _(":upper16: not allowed in this instruction"));
9884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9885 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9887 imm
= inst
.relocs
[0].exp
.X_add_number
;
9888 /* The value is in two pieces: 0:11, 16:19. */
9889 inst
.instruction
|= (imm
& 0x00000fff);
9890 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9895 do_vfp_nsyn_mrs (void)
9897 if (inst
.operands
[0].isvec
)
9899 if (inst
.operands
[1].reg
!= 1)
9900 first_error (_("operand 1 must be FPSCR"));
9901 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9902 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9903 do_vfp_nsyn_opcode ("fmstat");
9905 else if (inst
.operands
[1].isvec
)
9906 do_vfp_nsyn_opcode ("fmrx");
9914 do_vfp_nsyn_msr (void)
9916 if (inst
.operands
[0].isvec
)
9917 do_vfp_nsyn_opcode ("fmxr");
9927 unsigned Rt
= inst
.operands
[0].reg
;
9929 if (thumb_mode
&& Rt
== REG_SP
)
9931 inst
.error
= BAD_SP
;
9935 switch (inst
.operands
[1].reg
)
9937 /* MVFR2 is only valid for Armv8-A. */
9939 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9943 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9944 case 1: /* fpscr. */
9945 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9946 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9950 case 14: /* fpcxt_ns. */
9951 case 15: /* fpcxt_s. */
9952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9953 _("selected processor does not support instruction"));
9956 case 2: /* fpscr_nzcvqc. */
9959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9960 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9961 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9962 _("selected processor does not support instruction"));
9963 if (inst
.operands
[0].reg
!= 2
9964 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9965 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9972 /* APSR_ sets isvec. All other refs to PC are illegal. */
9973 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9975 inst
.error
= BAD_PC
;
9979 /* If we get through parsing the register name, we just insert the number
9980 generated into the instruction without further validation. */
9981 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9982 inst
.instruction
|= (Rt
<< 12);
9988 unsigned Rt
= inst
.operands
[1].reg
;
9991 reject_bad_reg (Rt
);
9992 else if (Rt
== REG_PC
)
9994 inst
.error
= BAD_PC
;
9998 switch (inst
.operands
[0].reg
)
10000 /* MVFR2 is only valid for Armv8-A. */
10002 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10006 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10007 case 1: /* fpcr. */
10008 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10009 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10013 case 14: /* fpcxt_ns. */
10014 case 15: /* fpcxt_s. */
10015 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10016 _("selected processor does not support instruction"));
10019 case 2: /* fpscr_nzcvqc. */
10020 case 12: /* vpr. */
10022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10023 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10024 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10025 _("selected processor does not support instruction"));
10026 if (inst
.operands
[0].reg
!= 2
10027 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10028 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10035 /* If we get through parsing the register name, we just insert the number
10036 generated into the instruction without further validation. */
10037 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10038 inst
.instruction
|= (Rt
<< 12);
10046 if (do_vfp_nsyn_mrs () == SUCCESS
)
10049 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10052 if (inst
.operands
[1].isreg
)
10054 br
= inst
.operands
[1].reg
;
10055 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10056 as_bad (_("bad register for mrs"));
10060 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10061 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10063 _("'APSR', 'CPSR' or 'SPSR' expected"));
10064 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10067 inst
.instruction
|= br
;
10070 /* Two possible forms:
10071 "{C|S}PSR_<field>, Rm",
10072 "{C|S}PSR_f, #expression". */
10077 if (do_vfp_nsyn_msr () == SUCCESS
)
10080 inst
.instruction
|= inst
.operands
[0].imm
;
10081 if (inst
.operands
[1].isreg
)
10082 inst
.instruction
|= inst
.operands
[1].reg
;
10085 inst
.instruction
|= INST_IMMEDIATE
;
10086 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10087 inst
.relocs
[0].pc_rel
= 0;
10094 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10096 if (!inst
.operands
[2].present
)
10097 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10098 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10099 inst
.instruction
|= inst
.operands
[1].reg
;
10100 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10102 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10103 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10104 as_tsktsk (_("Rd and Rm should be different in mul"));
10107 /* Long Multiply Parser
10108 UMULL RdLo, RdHi, Rm, Rs
10109 SMULL RdLo, RdHi, Rm, Rs
10110 UMLAL RdLo, RdHi, Rm, Rs
10111 SMLAL RdLo, RdHi, Rm, Rs. */
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10118 inst
.instruction
|= inst
.operands
[2].reg
;
10119 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10121 /* rdhi and rdlo must be different. */
10122 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10123 as_tsktsk (_("rdhi and rdlo must be different"));
10125 /* rdhi, rdlo and rm must all be different before armv6. */
10126 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10127 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10128 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10129 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10135 if (inst
.operands
[0].present
10136 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10138 /* Architectural NOP hints are CPSR sets with no bits selected. */
10139 inst
.instruction
&= 0xf0000000;
10140 inst
.instruction
|= 0x0320f000;
10141 if (inst
.operands
[0].present
)
10142 inst
.instruction
|= inst
.operands
[0].imm
;
10146 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10147 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10148 Condition defaults to COND_ALWAYS.
10149 Error if Rd, Rn or Rm are R15. */
10154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10155 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10156 inst
.instruction
|= inst
.operands
[2].reg
;
10157 if (inst
.operands
[3].present
)
10158 encode_arm_shift (3);
10161 /* ARM V6 PKHTB (Argument Parse). */
10166 if (!inst
.operands
[3].present
)
10168 /* If the shift specifier is omitted, turn the instruction
10169 into pkhbt rd, rm, rn. */
10170 inst
.instruction
&= 0xfff00010;
10171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10172 inst
.instruction
|= inst
.operands
[1].reg
;
10173 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10178 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10179 inst
.instruction
|= inst
.operands
[2].reg
;
10180 encode_arm_shift (3);
10184 /* ARMv5TE: Preload-Cache
10185 MP Extensions: Preload for write
10189 Syntactically, like LDR with B=1, W=0, L=1. */
10194 constraint (!inst
.operands
[0].isreg
,
10195 _("'[' expected after PLD mnemonic"));
10196 constraint (inst
.operands
[0].postind
,
10197 _("post-indexed expression used in preload instruction"));
10198 constraint (inst
.operands
[0].writeback
,
10199 _("writeback used in preload instruction"));
10200 constraint (!inst
.operands
[0].preind
,
10201 _("unindexed addressing used in preload instruction"));
10202 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10205 /* ARMv7: PLI <addr_mode> */
10209 constraint (!inst
.operands
[0].isreg
,
10210 _("'[' expected after PLI mnemonic"));
10211 constraint (inst
.operands
[0].postind
,
10212 _("post-indexed expression used in preload instruction"));
10213 constraint (inst
.operands
[0].writeback
,
10214 _("writeback used in preload instruction"));
10215 constraint (!inst
.operands
[0].preind
,
10216 _("unindexed addressing used in preload instruction"));
10217 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10218 inst
.instruction
&= ~PRE_INDEX
;
10224 constraint (inst
.operands
[0].writeback
,
10225 _("push/pop do not support {reglist}^"));
10226 inst
.operands
[1] = inst
.operands
[0];
10227 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10228 inst
.operands
[0].isreg
= 1;
10229 inst
.operands
[0].writeback
= 1;
10230 inst
.operands
[0].reg
= REG_SP
;
10231 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10234 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10235 word at the specified address and the following word
10237 Unconditionally executed.
10238 Error if Rn is R15. */
10243 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10244 if (inst
.operands
[0].writeback
)
10245 inst
.instruction
|= WRITE_BACK
;
10248 /* ARM V6 ssat (argument parse). */
10253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10254 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10255 inst
.instruction
|= inst
.operands
[2].reg
;
10257 if (inst
.operands
[3].present
)
10258 encode_arm_shift (3);
10261 /* ARM V6 usat (argument parse). */
10266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10267 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10268 inst
.instruction
|= inst
.operands
[2].reg
;
10270 if (inst
.operands
[3].present
)
10271 encode_arm_shift (3);
10274 /* ARM V6 ssat16 (argument parse). */
10279 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10280 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10281 inst
.instruction
|= inst
.operands
[2].reg
;
10287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10288 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10289 inst
.instruction
|= inst
.operands
[2].reg
;
10292 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10293 preserving the other bits.
10295 setend <endian_specifier>, where <endian_specifier> is either
10301 if (warn_on_deprecated
10302 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10303 as_tsktsk (_("setend use is deprecated for ARMv8"));
10305 if (inst
.operands
[0].imm
)
10306 inst
.instruction
|= 0x200;
10312 unsigned int Rm
= (inst
.operands
[1].present
10313 ? inst
.operands
[1].reg
10314 : inst
.operands
[0].reg
);
10316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10317 inst
.instruction
|= Rm
;
10318 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10320 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10321 inst
.instruction
|= SHIFT_BY_REG
;
10322 /* PR 12854: Error on extraneous shifts. */
10323 constraint (inst
.operands
[2].shifted
,
10324 _("extraneous shift as part of operand to shift insn"));
10327 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10333 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10334 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10336 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10337 inst
.relocs
[0].pc_rel
= 0;
10343 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10344 inst
.relocs
[0].pc_rel
= 0;
10350 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10351 inst
.relocs
[0].pc_rel
= 0;
10357 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10358 _("selected processor does not support SETPAN instruction"));
10360 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10366 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10367 _("selected processor does not support SETPAN instruction"));
10369 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10372 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10373 SMLAxy{cond} Rd,Rm,Rs,Rn
10374 SMLAWy{cond} Rd,Rm,Rs,Rn
10375 Error if any register is R15. */
10380 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10381 inst
.instruction
|= inst
.operands
[1].reg
;
10382 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10383 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10386 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10387 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10388 Error if any register is R15.
10389 Warning if Rdlo == Rdhi. */
10394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10395 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10396 inst
.instruction
|= inst
.operands
[2].reg
;
10397 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10399 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10400 as_tsktsk (_("rdhi and rdlo must be different"));
10403 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10404 SMULxy{cond} Rd,Rm,Rs
10405 Error if any register is R15. */
10410 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10411 inst
.instruction
|= inst
.operands
[1].reg
;
10412 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10415 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10416 the same for both ARM and Thumb-2. */
10423 if (inst
.operands
[0].present
)
10425 reg
= inst
.operands
[0].reg
;
10426 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10431 inst
.instruction
|= reg
<< 16;
10432 inst
.instruction
|= inst
.operands
[1].imm
;
10433 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10434 inst
.instruction
|= WRITE_BACK
;
10437 /* ARM V6 strex (argument parse). */
10442 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10443 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10444 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10445 || inst
.operands
[2].negative
10446 /* See comment in do_ldrex(). */
10447 || (inst
.operands
[2].reg
== REG_PC
),
10450 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10451 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10453 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10454 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10455 _("offset must be zero in ARM encoding"));
10457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10458 inst
.instruction
|= inst
.operands
[1].reg
;
10459 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10460 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10464 do_t_strexbh (void)
10466 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10467 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10468 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10469 || inst
.operands
[2].negative
,
10472 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10473 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10481 constraint (inst
.operands
[1].reg
% 2 != 0,
10482 _("even register required"));
10483 constraint (inst
.operands
[2].present
10484 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10485 _("can only store two consecutive registers"));
10486 /* If op 2 were present and equal to PC, this function wouldn't
10487 have been called in the first place. */
10488 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10490 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10491 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10492 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10496 inst
.instruction
|= inst
.operands
[1].reg
;
10497 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10504 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10505 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10513 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10514 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10519 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10520 extends it to 32-bits, and adds the result to a value in another
10521 register. You can specify a rotation by 0, 8, 16, or 24 bits
10522 before extracting the 16-bit value.
10523 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10524 Condition defaults to COND_ALWAYS.
10525 Error if any register uses R15. */
10530 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10531 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10532 inst
.instruction
|= inst
.operands
[2].reg
;
10533 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10538 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10539 Condition defaults to COND_ALWAYS.
10540 Error if any register uses R15. */
10545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10546 inst
.instruction
|= inst
.operands
[1].reg
;
10547 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10550 /* VFP instructions. In a logical order: SP variant first, monad
10551 before dyad, arithmetic then move then load/store. */
10554 do_vfp_sp_monadic (void)
10556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10557 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10560 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10561 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10565 do_vfp_sp_dyadic (void)
10567 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10568 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10569 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10573 do_vfp_sp_compare_z (void)
10575 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10579 do_vfp_dp_sp_cvt (void)
10581 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10582 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10586 do_vfp_sp_dp_cvt (void)
10588 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10589 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10593 do_vfp_reg_from_sp (void)
10595 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10596 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10600 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10604 do_vfp_reg2_from_sp2 (void)
10606 constraint (inst
.operands
[2].imm
!= 2,
10607 _("only two consecutive VFP SP registers allowed here"));
10608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10609 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10610 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10614 do_vfp_sp_from_reg (void)
10616 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10617 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10620 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10621 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10625 do_vfp_sp2_from_reg2 (void)
10627 constraint (inst
.operands
[0].imm
!= 2,
10628 _("only two consecutive VFP SP registers allowed here"));
10629 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10630 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10631 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10635 do_vfp_sp_ldst (void)
10637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10638 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10642 do_vfp_dp_ldst (void)
10644 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10645 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10650 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10652 if (inst
.operands
[0].writeback
)
10653 inst
.instruction
|= WRITE_BACK
;
10655 constraint (ldstm_type
!= VFP_LDSTMIA
,
10656 _("this addressing mode requires base-register writeback"));
10657 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10658 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10659 inst
.instruction
|= inst
.operands
[1].imm
;
10663 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10667 if (inst
.operands
[0].writeback
)
10668 inst
.instruction
|= WRITE_BACK
;
10670 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10671 _("this addressing mode requires base-register writeback"));
10673 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10674 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10676 count
= inst
.operands
[1].imm
<< 1;
10677 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10680 inst
.instruction
|= count
;
10684 do_vfp_sp_ldstmia (void)
10686 vfp_sp_ldstm (VFP_LDSTMIA
);
10690 do_vfp_sp_ldstmdb (void)
10692 vfp_sp_ldstm (VFP_LDSTMDB
);
10696 do_vfp_dp_ldstmia (void)
10698 vfp_dp_ldstm (VFP_LDSTMIA
);
10702 do_vfp_dp_ldstmdb (void)
10704 vfp_dp_ldstm (VFP_LDSTMDB
);
10708 do_vfp_xp_ldstmia (void)
10710 vfp_dp_ldstm (VFP_LDSTMIAX
);
10714 do_vfp_xp_ldstmdb (void)
10716 vfp_dp_ldstm (VFP_LDSTMDBX
);
10720 do_vfp_dp_rd_rm (void)
10722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10723 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10727 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10731 do_vfp_dp_rn_rd (void)
10733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10734 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10738 do_vfp_dp_rd_rn (void)
10740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10741 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10745 do_vfp_dp_rd_rn_rm (void)
10747 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10748 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10751 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10752 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10753 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10757 do_vfp_dp_rd (void)
10759 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10763 do_vfp_dp_rm_rd_rn (void)
10765 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10766 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10770 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10771 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10774 /* VFPv3 instructions. */
10776 do_vfp_sp_const (void)
10778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10779 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10780 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10784 do_vfp_dp_const (void)
10786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10787 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10788 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10792 vfp_conv (int srcsize
)
10794 int immbits
= srcsize
- inst
.operands
[1].imm
;
10796 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10798 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10799 i.e. immbits must be in range 0 - 16. */
10800 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10803 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10805 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10806 i.e. immbits must be in range 0 - 31. */
10807 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10811 inst
.instruction
|= (immbits
& 1) << 5;
10812 inst
.instruction
|= (immbits
>> 1);
10816 do_vfp_sp_conv_16 (void)
10818 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10823 do_vfp_dp_conv_16 (void)
10825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10830 do_vfp_sp_conv_32 (void)
10832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10837 do_vfp_dp_conv_32 (void)
10839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10843 /* FPA instructions. Also in a logical order. */
10848 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10849 inst
.instruction
|= inst
.operands
[1].reg
;
10853 do_fpa_ldmstm (void)
10855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10856 switch (inst
.operands
[1].imm
)
10858 case 1: inst
.instruction
|= CP_T_X
; break;
10859 case 2: inst
.instruction
|= CP_T_Y
; break;
10860 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10865 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10867 /* The instruction specified "ea" or "fd", so we can only accept
10868 [Rn]{!}. The instruction does not really support stacking or
10869 unstacking, so we have to emulate these by setting appropriate
10870 bits and offsets. */
10871 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10872 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10873 _("this instruction does not support indexing"));
10875 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10876 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10878 if (!(inst
.instruction
& INDEX_UP
))
10879 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10881 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10883 inst
.operands
[2].preind
= 0;
10884 inst
.operands
[2].postind
= 1;
10888 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10891 /* iWMMXt instructions: strictly in alphabetical order. */
10894 do_iwmmxt_tandorc (void)
10896 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10900 do_iwmmxt_textrc (void)
10902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10903 inst
.instruction
|= inst
.operands
[1].imm
;
10907 do_iwmmxt_textrm (void)
10909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10910 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10911 inst
.instruction
|= inst
.operands
[2].imm
;
10915 do_iwmmxt_tinsr (void)
10917 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10918 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10919 inst
.instruction
|= inst
.operands
[2].imm
;
10923 do_iwmmxt_tmia (void)
10925 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10926 inst
.instruction
|= inst
.operands
[1].reg
;
10927 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10931 do_iwmmxt_waligni (void)
10933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10934 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10935 inst
.instruction
|= inst
.operands
[2].reg
;
10936 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10940 do_iwmmxt_wmerge (void)
10942 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10943 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10944 inst
.instruction
|= inst
.operands
[2].reg
;
10945 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10949 do_iwmmxt_wmov (void)
10951 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10952 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10954 inst
.instruction
|= inst
.operands
[1].reg
;
10958 do_iwmmxt_wldstbh (void)
10961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10963 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10965 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10966 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10970 do_iwmmxt_wldstw (void)
10972 /* RIWR_RIWC clears .isreg for a control register. */
10973 if (!inst
.operands
[0].isreg
)
10975 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10976 inst
.instruction
|= 0xf0000000;
10979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10980 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10984 do_iwmmxt_wldstd (void)
10986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10987 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10988 && inst
.operands
[1].immisreg
)
10990 inst
.instruction
&= ~0x1a000ff;
10991 inst
.instruction
|= (0xfU
<< 28);
10992 if (inst
.operands
[1].preind
)
10993 inst
.instruction
|= PRE_INDEX
;
10994 if (!inst
.operands
[1].negative
)
10995 inst
.instruction
|= INDEX_UP
;
10996 if (inst
.operands
[1].writeback
)
10997 inst
.instruction
|= WRITE_BACK
;
10998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10999 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11000 inst
.instruction
|= inst
.operands
[1].imm
;
11003 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11007 do_iwmmxt_wshufh (void)
11009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11010 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11011 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11012 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11016 do_iwmmxt_wzero (void)
11018 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11019 inst
.instruction
|= inst
.operands
[0].reg
;
11020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11021 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11025 do_iwmmxt_wrwrwr_or_imm5 (void)
11027 if (inst
.operands
[2].isreg
)
11030 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11031 _("immediate operand requires iWMMXt2"));
11033 if (inst
.operands
[2].imm
== 0)
11035 switch ((inst
.instruction
>> 20) & 0xf)
11041 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11042 inst
.operands
[2].imm
= 16;
11043 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11049 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11050 inst
.operands
[2].imm
= 32;
11051 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11058 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11060 wrn
= (inst
.instruction
>> 16) & 0xf;
11061 inst
.instruction
&= 0xff0fff0f;
11062 inst
.instruction
|= wrn
;
11063 /* Bail out here; the instruction is now assembled. */
11068 /* Map 32 -> 0, etc. */
11069 inst
.operands
[2].imm
&= 0x1f;
11070 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11074 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11075 operations first, then control, shift, and load/store. */
11077 /* Insns like "foo X,Y,Z". */
11080 do_mav_triple (void)
11082 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11083 inst
.instruction
|= inst
.operands
[1].reg
;
11084 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11087 /* Insns like "foo W,X,Y,Z".
11088 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11093 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11094 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11095 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11096 inst
.instruction
|= inst
.operands
[3].reg
;
11099 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11101 do_mav_dspsc (void)
11103 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11106 /* Maverick shift immediate instructions.
11107 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11108 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11111 do_mav_shift (void)
11113 int imm
= inst
.operands
[2].imm
;
11115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11118 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11119 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11120 Bit 4 should be 0. */
11121 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11123 inst
.instruction
|= imm
;
11126 /* XScale instructions. Also sorted arithmetic before move. */
11128 /* Xscale multiply-accumulate (argument parse)
11131 MIAxycc acc0,Rm,Rs. */
11136 inst
.instruction
|= inst
.operands
[1].reg
;
11137 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11140 /* Xscale move-accumulator-register (argument parse)
11142 MARcc acc0,RdLo,RdHi. */
11147 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11148 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11151 /* Xscale move-register-accumulator (argument parse)
11153 MRAcc RdLo,RdHi,acc0. */
11158 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11159 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11160 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11163 /* Encoding functions relevant only to Thumb. */
11165 /* inst.operands[i] is a shifted-register operand; encode
11166 it into inst.instruction in the format used by Thumb32. */
11169 encode_thumb32_shifted_operand (int i
)
11171 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11172 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11174 constraint (inst
.operands
[i
].immisreg
,
11175 _("shift by register not allowed in thumb mode"));
11176 inst
.instruction
|= inst
.operands
[i
].reg
;
11177 if (shift
== SHIFT_RRX
)
11178 inst
.instruction
|= SHIFT_ROR
<< 4;
11181 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11182 _("expression too complex"));
11184 constraint (value
> 32
11185 || (value
== 32 && (shift
== SHIFT_LSL
11186 || shift
== SHIFT_ROR
)),
11187 _("shift expression is too large"));
11191 else if (value
== 32)
11194 inst
.instruction
|= shift
<< 4;
11195 inst
.instruction
|= (value
& 0x1c) << 10;
11196 inst
.instruction
|= (value
& 0x03) << 6;
11201 /* inst.operands[i] was set up by parse_address. Encode it into a
11202 Thumb32 format load or store instruction. Reject forms that cannot
11203 be used with such instructions. If is_t is true, reject forms that
11204 cannot be used with a T instruction; if is_d is true, reject forms
11205 that cannot be used with a D instruction. If it is a store insn,
11206 reject PC in Rn. */
11209 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11211 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11213 constraint (!inst
.operands
[i
].isreg
,
11214 _("Instruction does not support =N addresses"));
11216 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11217 if (inst
.operands
[i
].immisreg
)
11219 constraint (is_pc
, BAD_PC_ADDRESSING
);
11220 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11221 constraint (inst
.operands
[i
].negative
,
11222 _("Thumb does not support negative register indexing"));
11223 constraint (inst
.operands
[i
].postind
,
11224 _("Thumb does not support register post-indexing"));
11225 constraint (inst
.operands
[i
].writeback
,
11226 _("Thumb does not support register indexing with writeback"));
11227 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11228 _("Thumb supports only LSL in shifted register indexing"));
11230 inst
.instruction
|= inst
.operands
[i
].imm
;
11231 if (inst
.operands
[i
].shifted
)
11233 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11234 _("expression too complex"));
11235 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11236 || inst
.relocs
[0].exp
.X_add_number
> 3,
11237 _("shift out of range"));
11238 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11240 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11242 else if (inst
.operands
[i
].preind
)
11244 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11245 constraint (is_t
&& inst
.operands
[i
].writeback
,
11246 _("cannot use writeback with this instruction"));
11247 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11248 BAD_PC_ADDRESSING
);
11252 inst
.instruction
|= 0x01000000;
11253 if (inst
.operands
[i
].writeback
)
11254 inst
.instruction
|= 0x00200000;
11258 inst
.instruction
|= 0x00000c00;
11259 if (inst
.operands
[i
].writeback
)
11260 inst
.instruction
|= 0x00000100;
11262 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11264 else if (inst
.operands
[i
].postind
)
11266 gas_assert (inst
.operands
[i
].writeback
);
11267 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11268 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11271 inst
.instruction
|= 0x00200000;
11273 inst
.instruction
|= 0x00000900;
11274 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11276 else /* unindexed - only for coprocessor */
11277 inst
.error
= _("instruction does not accept unindexed addressing");
11280 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11281 encodings (the latter only in post-V6T2 cores). The index is the
11282 value used in the insns table below. When there is more than one
11283 possible 16-bit encoding for the instruction, this table always
11285 Also contains several pseudo-instructions used during relaxation. */
11286 #define T16_32_TAB \
11287 X(_adc, 4140, eb400000), \
11288 X(_adcs, 4140, eb500000), \
11289 X(_add, 1c00, eb000000), \
11290 X(_adds, 1c00, eb100000), \
11291 X(_addi, 0000, f1000000), \
11292 X(_addis, 0000, f1100000), \
11293 X(_add_pc,000f, f20f0000), \
11294 X(_add_sp,000d, f10d0000), \
11295 X(_adr, 000f, f20f0000), \
11296 X(_and, 4000, ea000000), \
11297 X(_ands, 4000, ea100000), \
11298 X(_asr, 1000, fa40f000), \
11299 X(_asrs, 1000, fa50f000), \
11300 X(_b, e000, f000b000), \
11301 X(_bcond, d000, f0008000), \
11302 X(_bf, 0000, f040e001), \
11303 X(_bfcsel,0000, f000e001), \
11304 X(_bfx, 0000, f060e001), \
11305 X(_bfl, 0000, f000c001), \
11306 X(_bflx, 0000, f070e001), \
11307 X(_bic, 4380, ea200000), \
11308 X(_bics, 4380, ea300000), \
11309 X(_cinc, 0000, ea509000), \
11310 X(_cinv, 0000, ea50a000), \
11311 X(_cmn, 42c0, eb100f00), \
11312 X(_cmp, 2800, ebb00f00), \
11313 X(_cneg, 0000, ea50b000), \
11314 X(_cpsie, b660, f3af8400), \
11315 X(_cpsid, b670, f3af8600), \
11316 X(_cpy, 4600, ea4f0000), \
11317 X(_csel, 0000, ea508000), \
11318 X(_cset, 0000, ea5f900f), \
11319 X(_csetm, 0000, ea5fa00f), \
11320 X(_csinc, 0000, ea509000), \
11321 X(_csinv, 0000, ea50a000), \
11322 X(_csneg, 0000, ea50b000), \
11323 X(_dec_sp,80dd, f1ad0d00), \
11324 X(_dls, 0000, f040e001), \
11325 X(_dlstp, 0000, f000e001), \
11326 X(_eor, 4040, ea800000), \
11327 X(_eors, 4040, ea900000), \
11328 X(_inc_sp,00dd, f10d0d00), \
11329 X(_lctp, 0000, f00fe001), \
11330 X(_ldmia, c800, e8900000), \
11331 X(_ldr, 6800, f8500000), \
11332 X(_ldrb, 7800, f8100000), \
11333 X(_ldrh, 8800, f8300000), \
11334 X(_ldrsb, 5600, f9100000), \
11335 X(_ldrsh, 5e00, f9300000), \
11336 X(_ldr_pc,4800, f85f0000), \
11337 X(_ldr_pc2,4800, f85f0000), \
11338 X(_ldr_sp,9800, f85d0000), \
11339 X(_le, 0000, f00fc001), \
11340 X(_letp, 0000, f01fc001), \
11341 X(_lsl, 0000, fa00f000), \
11342 X(_lsls, 0000, fa10f000), \
11343 X(_lsr, 0800, fa20f000), \
11344 X(_lsrs, 0800, fa30f000), \
11345 X(_mov, 2000, ea4f0000), \
11346 X(_movs, 2000, ea5f0000), \
11347 X(_mul, 4340, fb00f000), \
11348 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11349 X(_mvn, 43c0, ea6f0000), \
11350 X(_mvns, 43c0, ea7f0000), \
11351 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11352 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11353 X(_orr, 4300, ea400000), \
11354 X(_orrs, 4300, ea500000), \
11355 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11356 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11357 X(_rev, ba00, fa90f080), \
11358 X(_rev16, ba40, fa90f090), \
11359 X(_revsh, bac0, fa90f0b0), \
11360 X(_ror, 41c0, fa60f000), \
11361 X(_rors, 41c0, fa70f000), \
11362 X(_sbc, 4180, eb600000), \
11363 X(_sbcs, 4180, eb700000), \
11364 X(_stmia, c000, e8800000), \
11365 X(_str, 6000, f8400000), \
11366 X(_strb, 7000, f8000000), \
11367 X(_strh, 8000, f8200000), \
11368 X(_str_sp,9000, f84d0000), \
11369 X(_sub, 1e00, eba00000), \
11370 X(_subs, 1e00, ebb00000), \
11371 X(_subi, 8000, f1a00000), \
11372 X(_subis, 8000, f1b00000), \
11373 X(_sxtb, b240, fa4ff080), \
11374 X(_sxth, b200, fa0ff080), \
11375 X(_tst, 4200, ea100f00), \
11376 X(_uxtb, b2c0, fa5ff080), \
11377 X(_uxth, b280, fa1ff080), \
11378 X(_nop, bf00, f3af8000), \
11379 X(_yield, bf10, f3af8001), \
11380 X(_wfe, bf20, f3af8002), \
11381 X(_wfi, bf30, f3af8003), \
11382 X(_wls, 0000, f040c001), \
11383 X(_wlstp, 0000, f000c001), \
11384 X(_sev, bf40, f3af8004), \
11385 X(_sevl, bf50, f3af8005), \
11386 X(_udf, de00, f7f0a000)
11388 /* To catch errors in encoding functions, the codes are all offset by
11389 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11390 as 16-bit instructions. */
11391 #define X(a,b,c) T_MNEM##a
11392 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11395 #define X(a,b,c) 0x##b
11396 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11397 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11400 #define X(a,b,c) 0x##c
11401 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11402 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11403 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11407 /* Thumb instruction encoders, in alphabetical order. */
11409 /* ADDW or SUBW. */
11412 do_t_add_sub_w (void)
11416 Rd
= inst
.operands
[0].reg
;
11417 Rn
= inst
.operands
[1].reg
;
11419 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11420 is the SP-{plus,minus}-immediate form of the instruction. */
11422 constraint (Rd
== REG_PC
, BAD_PC
);
11424 reject_bad_reg (Rd
);
11426 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11427 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11430 /* Parse an add or subtract instruction. We get here with inst.instruction
11431 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11434 do_t_add_sub (void)
11438 Rd
= inst
.operands
[0].reg
;
11439 Rs
= (inst
.operands
[1].present
11440 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11441 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11444 set_pred_insn_type_last ();
11446 if (unified_syntax
)
11449 bfd_boolean narrow
;
11452 flags
= (inst
.instruction
== T_MNEM_adds
11453 || inst
.instruction
== T_MNEM_subs
);
11455 narrow
= !in_pred_block ();
11457 narrow
= in_pred_block ();
11458 if (!inst
.operands
[2].isreg
)
11462 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11463 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11465 add
= (inst
.instruction
== T_MNEM_add
11466 || inst
.instruction
== T_MNEM_adds
);
11468 if (inst
.size_req
!= 4)
11470 /* Attempt to use a narrow opcode, with relaxation if
11472 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11473 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11474 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11475 opcode
= T_MNEM_add_sp
;
11476 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11477 opcode
= T_MNEM_add_pc
;
11478 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11481 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11483 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11487 inst
.instruction
= THUMB_OP16(opcode
);
11488 inst
.instruction
|= (Rd
<< 4) | Rs
;
11489 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11490 || (inst
.relocs
[0].type
11491 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11493 if (inst
.size_req
== 2)
11494 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11496 inst
.relax
= opcode
;
11500 constraint (inst
.size_req
== 2, BAD_HIREG
);
11502 if (inst
.size_req
== 4
11503 || (inst
.size_req
!= 2 && !opcode
))
11505 constraint ((inst
.relocs
[0].type
11506 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11507 && (inst
.relocs
[0].type
11508 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11509 THUMB1_RELOC_ONLY
);
11512 constraint (add
, BAD_PC
);
11513 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11514 _("only SUBS PC, LR, #const allowed"));
11515 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11516 _("expression too complex"));
11517 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11518 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11519 _("immediate value out of range"));
11520 inst
.instruction
= T2_SUBS_PC_LR
11521 | inst
.relocs
[0].exp
.X_add_number
;
11522 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11525 else if (Rs
== REG_PC
)
11527 /* Always use addw/subw. */
11528 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11529 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11533 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11534 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11537 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11539 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11541 inst
.instruction
|= Rd
<< 8;
11542 inst
.instruction
|= Rs
<< 16;
11547 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11548 unsigned int shift
= inst
.operands
[2].shift_kind
;
11550 Rn
= inst
.operands
[2].reg
;
11551 /* See if we can do this with a 16-bit instruction. */
11552 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11554 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11559 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11560 || inst
.instruction
== T_MNEM_add
)
11562 : T_OPCODE_SUB_R3
);
11563 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11567 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11569 /* Thumb-1 cores (except v6-M) require at least one high
11570 register in a narrow non flag setting add. */
11571 if (Rd
> 7 || Rn
> 7
11572 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11573 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11580 inst
.instruction
= T_OPCODE_ADD_HI
;
11581 inst
.instruction
|= (Rd
& 8) << 4;
11582 inst
.instruction
|= (Rd
& 7);
11583 inst
.instruction
|= Rn
<< 3;
11589 constraint (Rd
== REG_PC
, BAD_PC
);
11590 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11591 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11592 constraint (Rs
== REG_PC
, BAD_PC
);
11593 reject_bad_reg (Rn
);
11595 /* If we get here, it can't be done in 16 bits. */
11596 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11597 _("shift must be constant"));
11598 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11599 inst
.instruction
|= Rd
<< 8;
11600 inst
.instruction
|= Rs
<< 16;
11601 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11602 _("shift value over 3 not allowed in thumb mode"));
11603 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11604 _("only LSL shift allowed in thumb mode"));
11605 encode_thumb32_shifted_operand (2);
11610 constraint (inst
.instruction
== T_MNEM_adds
11611 || inst
.instruction
== T_MNEM_subs
,
11614 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11616 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11617 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11620 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11621 ? 0x0000 : 0x8000);
11622 inst
.instruction
|= (Rd
<< 4) | Rs
;
11623 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11627 Rn
= inst
.operands
[2].reg
;
11628 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11630 /* We now have Rd, Rs, and Rn set to registers. */
11631 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11633 /* Can't do this for SUB. */
11634 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11635 inst
.instruction
= T_OPCODE_ADD_HI
;
11636 inst
.instruction
|= (Rd
& 8) << 4;
11637 inst
.instruction
|= (Rd
& 7);
11639 inst
.instruction
|= Rn
<< 3;
11641 inst
.instruction
|= Rs
<< 3;
11643 constraint (1, _("dest must overlap one source register"));
11647 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11648 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11649 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11659 Rd
= inst
.operands
[0].reg
;
11660 reject_bad_reg (Rd
);
11662 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11664 /* Defer to section relaxation. */
11665 inst
.relax
= inst
.instruction
;
11666 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11667 inst
.instruction
|= Rd
<< 4;
11669 else if (unified_syntax
&& inst
.size_req
!= 2)
11671 /* Generate a 32-bit opcode. */
11672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11673 inst
.instruction
|= Rd
<< 8;
11674 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11675 inst
.relocs
[0].pc_rel
= 1;
11679 /* Generate a 16-bit opcode. */
11680 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11681 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11682 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11683 inst
.relocs
[0].pc_rel
= 1;
11684 inst
.instruction
|= Rd
<< 4;
11687 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11688 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11689 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11690 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11691 inst
.relocs
[0].exp
.X_add_number
+= 1;
11694 /* Arithmetic instructions for which there is just one 16-bit
11695 instruction encoding, and it allows only two low registers.
11696 For maximal compatibility with ARM syntax, we allow three register
11697 operands even when Thumb-32 instructions are not available, as long
11698 as the first two are identical. For instance, both "sbc r0,r1" and
11699 "sbc r0,r0,r1" are allowed. */
11705 Rd
= inst
.operands
[0].reg
;
11706 Rs
= (inst
.operands
[1].present
11707 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11708 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11709 Rn
= inst
.operands
[2].reg
;
11711 reject_bad_reg (Rd
);
11712 reject_bad_reg (Rs
);
11713 if (inst
.operands
[2].isreg
)
11714 reject_bad_reg (Rn
);
11716 if (unified_syntax
)
11718 if (!inst
.operands
[2].isreg
)
11720 /* For an immediate, we always generate a 32-bit opcode;
11721 section relaxation will shrink it later if possible. */
11722 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11723 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11724 inst
.instruction
|= Rd
<< 8;
11725 inst
.instruction
|= Rs
<< 16;
11726 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11730 bfd_boolean narrow
;
11732 /* See if we can do this with a 16-bit instruction. */
11733 if (THUMB_SETS_FLAGS (inst
.instruction
))
11734 narrow
= !in_pred_block ();
11736 narrow
= in_pred_block ();
11738 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11740 if (inst
.operands
[2].shifted
)
11742 if (inst
.size_req
== 4)
11748 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11749 inst
.instruction
|= Rd
;
11750 inst
.instruction
|= Rn
<< 3;
11754 /* If we get here, it can't be done in 16 bits. */
11755 constraint (inst
.operands
[2].shifted
11756 && inst
.operands
[2].immisreg
,
11757 _("shift must be constant"));
11758 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11759 inst
.instruction
|= Rd
<< 8;
11760 inst
.instruction
|= Rs
<< 16;
11761 encode_thumb32_shifted_operand (2);
11766 /* On its face this is a lie - the instruction does set the
11767 flags. However, the only supported mnemonic in this mode
11768 says it doesn't. */
11769 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11771 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11772 _("unshifted register required"));
11773 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11774 constraint (Rd
!= Rs
,
11775 _("dest and source1 must be the same register"));
11777 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11778 inst
.instruction
|= Rd
;
11779 inst
.instruction
|= Rn
<< 3;
11783 /* Similarly, but for instructions where the arithmetic operation is
11784 commutative, so we can allow either of them to be different from
11785 the destination operand in a 16-bit instruction. For instance, all
11786 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11793 Rd
= inst
.operands
[0].reg
;
11794 Rs
= (inst
.operands
[1].present
11795 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11796 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11797 Rn
= inst
.operands
[2].reg
;
11799 reject_bad_reg (Rd
);
11800 reject_bad_reg (Rs
);
11801 if (inst
.operands
[2].isreg
)
11802 reject_bad_reg (Rn
);
11804 if (unified_syntax
)
11806 if (!inst
.operands
[2].isreg
)
11808 /* For an immediate, we always generate a 32-bit opcode;
11809 section relaxation will shrink it later if possible. */
11810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11811 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11812 inst
.instruction
|= Rd
<< 8;
11813 inst
.instruction
|= Rs
<< 16;
11814 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11818 bfd_boolean narrow
;
11820 /* See if we can do this with a 16-bit instruction. */
11821 if (THUMB_SETS_FLAGS (inst
.instruction
))
11822 narrow
= !in_pred_block ();
11824 narrow
= in_pred_block ();
11826 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11828 if (inst
.operands
[2].shifted
)
11830 if (inst
.size_req
== 4)
11837 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11838 inst
.instruction
|= Rd
;
11839 inst
.instruction
|= Rn
<< 3;
11844 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11845 inst
.instruction
|= Rd
;
11846 inst
.instruction
|= Rs
<< 3;
11851 /* If we get here, it can't be done in 16 bits. */
11852 constraint (inst
.operands
[2].shifted
11853 && inst
.operands
[2].immisreg
,
11854 _("shift must be constant"));
11855 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11856 inst
.instruction
|= Rd
<< 8;
11857 inst
.instruction
|= Rs
<< 16;
11858 encode_thumb32_shifted_operand (2);
11863 /* On its face this is a lie - the instruction does set the
11864 flags. However, the only supported mnemonic in this mode
11865 says it doesn't. */
11866 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11868 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11869 _("unshifted register required"));
11870 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11872 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11873 inst
.instruction
|= Rd
;
11876 inst
.instruction
|= Rn
<< 3;
11878 inst
.instruction
|= Rs
<< 3;
11880 constraint (1, _("dest must overlap one source register"));
11888 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11889 constraint (msb
> 32, _("bit-field extends past end of register"));
11890 /* The instruction encoding stores the LSB and MSB,
11891 not the LSB and width. */
11892 Rd
= inst
.operands
[0].reg
;
11893 reject_bad_reg (Rd
);
11894 inst
.instruction
|= Rd
<< 8;
11895 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11896 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11897 inst
.instruction
|= msb
- 1;
11906 Rd
= inst
.operands
[0].reg
;
11907 reject_bad_reg (Rd
);
11909 /* #0 in second position is alternative syntax for bfc, which is
11910 the same instruction but with REG_PC in the Rm field. */
11911 if (!inst
.operands
[1].isreg
)
11915 Rn
= inst
.operands
[1].reg
;
11916 reject_bad_reg (Rn
);
11919 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11920 constraint (msb
> 32, _("bit-field extends past end of register"));
11921 /* The instruction encoding stores the LSB and MSB,
11922 not the LSB and width. */
11923 inst
.instruction
|= Rd
<< 8;
11924 inst
.instruction
|= Rn
<< 16;
11925 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11926 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11927 inst
.instruction
|= msb
- 1;
11935 Rd
= inst
.operands
[0].reg
;
11936 Rn
= inst
.operands
[1].reg
;
11938 reject_bad_reg (Rd
);
11939 reject_bad_reg (Rn
);
11941 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11942 _("bit-field extends past end of register"));
11943 inst
.instruction
|= Rd
<< 8;
11944 inst
.instruction
|= Rn
<< 16;
11945 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11946 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11947 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11950 /* ARM V5 Thumb BLX (argument parse)
11951 BLX <target_addr> which is BLX(1)
11952 BLX <Rm> which is BLX(2)
11953 Unfortunately, there are two different opcodes for this mnemonic.
11954 So, the insns[].value is not used, and the code here zaps values
11955 into inst.instruction.
11957 ??? How to take advantage of the additional two bits of displacement
11958 available in Thumb32 mode? Need new relocation? */
11963 set_pred_insn_type_last ();
11965 if (inst
.operands
[0].isreg
)
11967 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11968 /* We have a register, so this is BLX(2). */
11969 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11973 /* No register. This must be BLX(1). */
11974 inst
.instruction
= 0xf000e800;
11975 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11984 bfd_reloc_code_real_type reloc
;
11987 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11989 if (in_pred_block ())
11991 /* Conditional branches inside IT blocks are encoded as unconditional
11993 cond
= COND_ALWAYS
;
11998 if (cond
!= COND_ALWAYS
)
11999 opcode
= T_MNEM_bcond
;
12001 opcode
= inst
.instruction
;
12004 && (inst
.size_req
== 4
12005 || (inst
.size_req
!= 2
12006 && (inst
.operands
[0].hasreloc
12007 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12009 inst
.instruction
= THUMB_OP32(opcode
);
12010 if (cond
== COND_ALWAYS
)
12011 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12015 _("selected architecture does not support "
12016 "wide conditional branch instruction"));
12018 gas_assert (cond
!= 0xF);
12019 inst
.instruction
|= cond
<< 22;
12020 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12025 inst
.instruction
= THUMB_OP16(opcode
);
12026 if (cond
== COND_ALWAYS
)
12027 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12030 inst
.instruction
|= cond
<< 8;
12031 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12033 /* Allow section relaxation. */
12034 if (unified_syntax
&& inst
.size_req
!= 2)
12035 inst
.relax
= opcode
;
12037 inst
.relocs
[0].type
= reloc
;
12038 inst
.relocs
[0].pc_rel
= 1;
12041 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12042 between the two is the maximum immediate allowed - which is passed in
12045 do_t_bkpt_hlt1 (int range
)
12047 constraint (inst
.cond
!= COND_ALWAYS
,
12048 _("instruction is always unconditional"));
12049 if (inst
.operands
[0].present
)
12051 constraint (inst
.operands
[0].imm
> range
,
12052 _("immediate value out of range"));
12053 inst
.instruction
|= inst
.operands
[0].imm
;
12056 set_pred_insn_type (NEUTRAL_IT_INSN
);
12062 do_t_bkpt_hlt1 (63);
12068 do_t_bkpt_hlt1 (255);
12072 do_t_branch23 (void)
12074 set_pred_insn_type_last ();
12075 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12077 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12078 this file. We used to simply ignore the PLT reloc type here --
12079 the branch encoding is now needed to deal with TLSCALL relocs.
12080 So if we see a PLT reloc now, put it back to how it used to be to
12081 keep the preexisting behaviour. */
12082 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12083 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12085 #if defined(OBJ_COFF)
12086 /* If the destination of the branch is a defined symbol which does not have
12087 the THUMB_FUNC attribute, then we must be calling a function which has
12088 the (interfacearm) attribute. We look for the Thumb entry point to that
12089 function and change the branch to refer to that function instead. */
12090 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12091 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12092 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12093 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12094 inst
.relocs
[0].exp
.X_add_symbol
12095 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12102 set_pred_insn_type_last ();
12103 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12104 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12105 should cause the alignment to be checked once it is known. This is
12106 because BX PC only works if the instruction is word aligned. */
12114 set_pred_insn_type_last ();
12115 Rm
= inst
.operands
[0].reg
;
12116 reject_bad_reg (Rm
);
12117 inst
.instruction
|= Rm
<< 16;
12126 Rd
= inst
.operands
[0].reg
;
12127 Rm
= inst
.operands
[1].reg
;
12129 reject_bad_reg (Rd
);
12130 reject_bad_reg (Rm
);
12132 inst
.instruction
|= Rd
<< 8;
12133 inst
.instruction
|= Rm
<< 16;
12134 inst
.instruction
|= Rm
;
12137 /* For the Armv8.1-M conditional instructions. */
12141 unsigned Rd
, Rn
, Rm
;
12144 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12146 Rd
= inst
.operands
[0].reg
;
12147 switch (inst
.instruction
)
12153 Rn
= inst
.operands
[1].reg
;
12154 Rm
= inst
.operands
[2].reg
;
12155 cond
= inst
.operands
[3].imm
;
12156 constraint (Rn
== REG_SP
, BAD_SP
);
12157 constraint (Rm
== REG_SP
, BAD_SP
);
12163 Rn
= inst
.operands
[1].reg
;
12164 cond
= inst
.operands
[2].imm
;
12165 /* Invert the last bit to invert the cond. */
12166 cond
= TOGGLE_BIT (cond
, 0);
12167 constraint (Rn
== REG_SP
, BAD_SP
);
12173 cond
= inst
.operands
[1].imm
;
12174 /* Invert the last bit to invert the cond. */
12175 cond
= TOGGLE_BIT (cond
, 0);
12183 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12184 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12185 inst
.instruction
|= Rd
<< 8;
12186 inst
.instruction
|= Rn
<< 16;
12187 inst
.instruction
|= Rm
;
12188 inst
.instruction
|= cond
<< 4;
12194 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12200 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12201 inst
.instruction
|= inst
.operands
[0].imm
;
12207 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12209 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12210 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12212 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12213 inst
.instruction
= 0xf3af8000;
12214 inst
.instruction
|= imod
<< 9;
12215 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12216 if (inst
.operands
[1].present
)
12217 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12221 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12222 && (inst
.operands
[0].imm
& 4),
12223 _("selected processor does not support 'A' form "
12224 "of this instruction"));
12225 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12226 _("Thumb does not support the 2-argument "
12227 "form of this instruction"));
12228 inst
.instruction
|= inst
.operands
[0].imm
;
12232 /* THUMB CPY instruction (argument parse). */
12237 if (inst
.size_req
== 4)
12239 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12240 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12241 inst
.instruction
|= inst
.operands
[1].reg
;
12245 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12246 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12247 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12254 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12255 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12256 inst
.instruction
|= inst
.operands
[0].reg
;
12257 inst
.relocs
[0].pc_rel
= 1;
12258 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12264 inst
.instruction
|= inst
.operands
[0].imm
;
12270 unsigned Rd
, Rn
, Rm
;
12272 Rd
= inst
.operands
[0].reg
;
12273 Rn
= (inst
.operands
[1].present
12274 ? inst
.operands
[1].reg
: Rd
);
12275 Rm
= inst
.operands
[2].reg
;
12277 reject_bad_reg (Rd
);
12278 reject_bad_reg (Rn
);
12279 reject_bad_reg (Rm
);
12281 inst
.instruction
|= Rd
<< 8;
12282 inst
.instruction
|= Rn
<< 16;
12283 inst
.instruction
|= Rm
;
12289 if (unified_syntax
&& inst
.size_req
== 4)
12290 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12292 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12298 unsigned int cond
= inst
.operands
[0].imm
;
12300 set_pred_insn_type (IT_INSN
);
12301 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12302 now_pred
.cc
= cond
;
12303 now_pred
.warn_deprecated
= FALSE
;
12304 now_pred
.type
= SCALAR_PRED
;
12306 /* If the condition is a negative condition, invert the mask. */
12307 if ((cond
& 0x1) == 0x0)
12309 unsigned int mask
= inst
.instruction
& 0x000f;
12311 if ((mask
& 0x7) == 0)
12313 /* No conversion needed. */
12314 now_pred
.block_length
= 1;
12316 else if ((mask
& 0x3) == 0)
12319 now_pred
.block_length
= 2;
12321 else if ((mask
& 0x1) == 0)
12324 now_pred
.block_length
= 3;
12329 now_pred
.block_length
= 4;
12332 inst
.instruction
&= 0xfff0;
12333 inst
.instruction
|= mask
;
12336 inst
.instruction
|= cond
<< 4;
12339 /* Helper function used for both push/pop and ldm/stm. */
12341 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12342 bfd_boolean writeback
)
12344 bfd_boolean load
, store
;
12346 gas_assert (base
!= -1 || !do_io
);
12347 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12348 store
= do_io
&& !load
;
12350 if (mask
& (1 << 13))
12351 inst
.error
= _("SP not allowed in register list");
12353 if (do_io
&& (mask
& (1 << base
)) != 0
12355 inst
.error
= _("having the base register in the register list when "
12356 "using write back is UNPREDICTABLE");
12360 if (mask
& (1 << 15))
12362 if (mask
& (1 << 14))
12363 inst
.error
= _("LR and PC should not both be in register list");
12365 set_pred_insn_type_last ();
12370 if (mask
& (1 << 15))
12371 inst
.error
= _("PC not allowed in register list");
12374 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12376 /* Single register transfers implemented as str/ldr. */
12379 if (inst
.instruction
& (1 << 23))
12380 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12382 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12386 if (inst
.instruction
& (1 << 23))
12387 inst
.instruction
= 0x00800000; /* ia -> [base] */
12389 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12392 inst
.instruction
|= 0xf8400000;
12394 inst
.instruction
|= 0x00100000;
12396 mask
= ffs (mask
) - 1;
12399 else if (writeback
)
12400 inst
.instruction
|= WRITE_BACK
;
12402 inst
.instruction
|= mask
;
12404 inst
.instruction
|= base
<< 16;
12410 /* This really doesn't seem worth it. */
12411 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12412 _("expression too complex"));
12413 constraint (inst
.operands
[1].writeback
,
12414 _("Thumb load/store multiple does not support {reglist}^"));
12416 if (unified_syntax
)
12418 bfd_boolean narrow
;
12422 /* See if we can use a 16-bit instruction. */
12423 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12424 && inst
.size_req
!= 4
12425 && !(inst
.operands
[1].imm
& ~0xff))
12427 mask
= 1 << inst
.operands
[0].reg
;
12429 if (inst
.operands
[0].reg
<= 7)
12431 if (inst
.instruction
== T_MNEM_stmia
12432 ? inst
.operands
[0].writeback
12433 : (inst
.operands
[0].writeback
12434 == !(inst
.operands
[1].imm
& mask
)))
12436 if (inst
.instruction
== T_MNEM_stmia
12437 && (inst
.operands
[1].imm
& mask
)
12438 && (inst
.operands
[1].imm
& (mask
- 1)))
12439 as_warn (_("value stored for r%d is UNKNOWN"),
12440 inst
.operands
[0].reg
);
12442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12443 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12444 inst
.instruction
|= inst
.operands
[1].imm
;
12447 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12449 /* This means 1 register in reg list one of 3 situations:
12450 1. Instruction is stmia, but without writeback.
12451 2. lmdia without writeback, but with Rn not in
12453 3. ldmia with writeback, but with Rn in reglist.
12454 Case 3 is UNPREDICTABLE behaviour, so we handle
12455 case 1 and 2 which can be converted into a 16-bit
12456 str or ldr. The SP cases are handled below. */
12457 unsigned long opcode
;
12458 /* First, record an error for Case 3. */
12459 if (inst
.operands
[1].imm
& mask
12460 && inst
.operands
[0].writeback
)
12462 _("having the base register in the register list when "
12463 "using write back is UNPREDICTABLE");
12465 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12467 inst
.instruction
= THUMB_OP16 (opcode
);
12468 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12469 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12473 else if (inst
.operands
[0] .reg
== REG_SP
)
12475 if (inst
.operands
[0].writeback
)
12478 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12479 ? T_MNEM_push
: T_MNEM_pop
);
12480 inst
.instruction
|= inst
.operands
[1].imm
;
12483 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12486 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12487 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12488 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12496 if (inst
.instruction
< 0xffff)
12497 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12499 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12500 inst
.operands
[1].imm
,
12501 inst
.operands
[0].writeback
);
12506 constraint (inst
.operands
[0].reg
> 7
12507 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12508 constraint (inst
.instruction
!= T_MNEM_ldmia
12509 && inst
.instruction
!= T_MNEM_stmia
,
12510 _("Thumb-2 instruction only valid in unified syntax"));
12511 if (inst
.instruction
== T_MNEM_stmia
)
12513 if (!inst
.operands
[0].writeback
)
12514 as_warn (_("this instruction will write back the base register"));
12515 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12516 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12517 as_warn (_("value stored for r%d is UNKNOWN"),
12518 inst
.operands
[0].reg
);
12522 if (!inst
.operands
[0].writeback
12523 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12524 as_warn (_("this instruction will write back the base register"));
12525 else if (inst
.operands
[0].writeback
12526 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12527 as_warn (_("this instruction will not write back the base register"));
12530 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12531 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12532 inst
.instruction
|= inst
.operands
[1].imm
;
12539 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12540 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12541 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12542 || inst
.operands
[1].negative
,
12545 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12548 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12549 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12555 if (!inst
.operands
[1].present
)
12557 constraint (inst
.operands
[0].reg
== REG_LR
,
12558 _("r14 not allowed as first register "
12559 "when second register is omitted"));
12560 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12562 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12566 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12567 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12573 unsigned long opcode
;
12576 if (inst
.operands
[0].isreg
12577 && !inst
.operands
[0].preind
12578 && inst
.operands
[0].reg
== REG_PC
)
12579 set_pred_insn_type_last ();
12581 opcode
= inst
.instruction
;
12582 if (unified_syntax
)
12584 if (!inst
.operands
[1].isreg
)
12586 if (opcode
<= 0xffff)
12587 inst
.instruction
= THUMB_OP32 (opcode
);
12588 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12591 if (inst
.operands
[1].isreg
12592 && !inst
.operands
[1].writeback
12593 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12594 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12595 && opcode
<= 0xffff
12596 && inst
.size_req
!= 4)
12598 /* Insn may have a 16-bit form. */
12599 Rn
= inst
.operands
[1].reg
;
12600 if (inst
.operands
[1].immisreg
)
12602 inst
.instruction
= THUMB_OP16 (opcode
);
12604 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12606 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12607 reject_bad_reg (inst
.operands
[1].imm
);
12609 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12610 && opcode
!= T_MNEM_ldrsb
)
12611 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12612 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12619 if (inst
.relocs
[0].pc_rel
)
12620 opcode
= T_MNEM_ldr_pc2
;
12622 opcode
= T_MNEM_ldr_pc
;
12626 if (opcode
== T_MNEM_ldr
)
12627 opcode
= T_MNEM_ldr_sp
;
12629 opcode
= T_MNEM_str_sp
;
12631 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12635 inst
.instruction
= inst
.operands
[0].reg
;
12636 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12638 inst
.instruction
|= THUMB_OP16 (opcode
);
12639 if (inst
.size_req
== 2)
12640 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12642 inst
.relax
= opcode
;
12646 /* Definitely a 32-bit variant. */
12648 /* Warning for Erratum 752419. */
12649 if (opcode
== T_MNEM_ldr
12650 && inst
.operands
[0].reg
== REG_SP
12651 && inst
.operands
[1].writeback
== 1
12652 && !inst
.operands
[1].immisreg
)
12654 if (no_cpu_selected ()
12655 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12656 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12657 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12658 as_warn (_("This instruction may be unpredictable "
12659 "if executed on M-profile cores "
12660 "with interrupts enabled."));
12663 /* Do some validations regarding addressing modes. */
12664 if (inst
.operands
[1].immisreg
)
12665 reject_bad_reg (inst
.operands
[1].imm
);
12667 constraint (inst
.operands
[1].writeback
== 1
12668 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12671 inst
.instruction
= THUMB_OP32 (opcode
);
12672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12673 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12674 check_ldr_r15_aligned ();
12678 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12680 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12682 /* Only [Rn,Rm] is acceptable. */
12683 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12684 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12685 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12686 || inst
.operands
[1].negative
,
12687 _("Thumb does not support this addressing mode"));
12688 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12692 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12693 if (!inst
.operands
[1].isreg
)
12694 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12697 constraint (!inst
.operands
[1].preind
12698 || inst
.operands
[1].shifted
12699 || inst
.operands
[1].writeback
,
12700 _("Thumb does not support this addressing mode"));
12701 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12703 constraint (inst
.instruction
& 0x0600,
12704 _("byte or halfword not valid for base register"));
12705 constraint (inst
.operands
[1].reg
== REG_PC
12706 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12707 _("r15 based store not allowed"));
12708 constraint (inst
.operands
[1].immisreg
,
12709 _("invalid base register for register offset"));
12711 if (inst
.operands
[1].reg
== REG_PC
)
12712 inst
.instruction
= T_OPCODE_LDR_PC
;
12713 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12714 inst
.instruction
= T_OPCODE_LDR_SP
;
12716 inst
.instruction
= T_OPCODE_STR_SP
;
12718 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12719 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12723 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12724 if (!inst
.operands
[1].immisreg
)
12726 /* Immediate offset. */
12727 inst
.instruction
|= inst
.operands
[0].reg
;
12728 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12729 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12733 /* Register offset. */
12734 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12735 constraint (inst
.operands
[1].negative
,
12736 _("Thumb does not support this addressing mode"));
12739 switch (inst
.instruction
)
12741 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12742 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12743 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12744 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12745 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12746 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12747 case 0x5600 /* ldrsb */:
12748 case 0x5e00 /* ldrsh */: break;
12752 inst
.instruction
|= inst
.operands
[0].reg
;
12753 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12754 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12760 if (!inst
.operands
[1].present
)
12762 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12763 constraint (inst
.operands
[0].reg
== REG_LR
,
12764 _("r14 not allowed here"));
12765 constraint (inst
.operands
[0].reg
== REG_R12
,
12766 _("r12 not allowed here"));
12769 if (inst
.operands
[2].writeback
12770 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12771 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12772 as_warn (_("base register written back, and overlaps "
12773 "one of transfer registers"));
12775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12776 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12777 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12783 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12784 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12790 unsigned Rd
, Rn
, Rm
, Ra
;
12792 Rd
= inst
.operands
[0].reg
;
12793 Rn
= inst
.operands
[1].reg
;
12794 Rm
= inst
.operands
[2].reg
;
12795 Ra
= inst
.operands
[3].reg
;
12797 reject_bad_reg (Rd
);
12798 reject_bad_reg (Rn
);
12799 reject_bad_reg (Rm
);
12800 reject_bad_reg (Ra
);
12802 inst
.instruction
|= Rd
<< 8;
12803 inst
.instruction
|= Rn
<< 16;
12804 inst
.instruction
|= Rm
;
12805 inst
.instruction
|= Ra
<< 12;
12811 unsigned RdLo
, RdHi
, Rn
, Rm
;
12813 RdLo
= inst
.operands
[0].reg
;
12814 RdHi
= inst
.operands
[1].reg
;
12815 Rn
= inst
.operands
[2].reg
;
12816 Rm
= inst
.operands
[3].reg
;
12818 reject_bad_reg (RdLo
);
12819 reject_bad_reg (RdHi
);
12820 reject_bad_reg (Rn
);
12821 reject_bad_reg (Rm
);
12823 inst
.instruction
|= RdLo
<< 12;
12824 inst
.instruction
|= RdHi
<< 8;
12825 inst
.instruction
|= Rn
<< 16;
12826 inst
.instruction
|= Rm
;
12830 do_t_mov_cmp (void)
12834 Rn
= inst
.operands
[0].reg
;
12835 Rm
= inst
.operands
[1].reg
;
12838 set_pred_insn_type_last ();
12840 if (unified_syntax
)
12842 int r0off
= (inst
.instruction
== T_MNEM_mov
12843 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12844 unsigned long opcode
;
12845 bfd_boolean narrow
;
12846 bfd_boolean low_regs
;
12848 low_regs
= (Rn
<= 7 && Rm
<= 7);
12849 opcode
= inst
.instruction
;
12850 if (in_pred_block ())
12851 narrow
= opcode
!= T_MNEM_movs
;
12853 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12854 if (inst
.size_req
== 4
12855 || inst
.operands
[1].shifted
)
12858 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12859 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12860 && !inst
.operands
[1].shifted
12864 inst
.instruction
= T2_SUBS_PC_LR
;
12868 if (opcode
== T_MNEM_cmp
)
12870 constraint (Rn
== REG_PC
, BAD_PC
);
12873 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12875 warn_deprecated_sp (Rm
);
12876 /* R15 was documented as a valid choice for Rm in ARMv6,
12877 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12878 tools reject R15, so we do too. */
12879 constraint (Rm
== REG_PC
, BAD_PC
);
12882 reject_bad_reg (Rm
);
12884 else if (opcode
== T_MNEM_mov
12885 || opcode
== T_MNEM_movs
)
12887 if (inst
.operands
[1].isreg
)
12889 if (opcode
== T_MNEM_movs
)
12891 reject_bad_reg (Rn
);
12892 reject_bad_reg (Rm
);
12896 /* This is mov.n. */
12897 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12898 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12900 as_tsktsk (_("Use of r%u as a source register is "
12901 "deprecated when r%u is the destination "
12902 "register."), Rm
, Rn
);
12907 /* This is mov.w. */
12908 constraint (Rn
== REG_PC
, BAD_PC
);
12909 constraint (Rm
== REG_PC
, BAD_PC
);
12910 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12911 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12915 reject_bad_reg (Rn
);
12918 if (!inst
.operands
[1].isreg
)
12920 /* Immediate operand. */
12921 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12923 if (low_regs
&& narrow
)
12925 inst
.instruction
= THUMB_OP16 (opcode
);
12926 inst
.instruction
|= Rn
<< 8;
12927 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12928 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12930 if (inst
.size_req
== 2)
12931 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12933 inst
.relax
= opcode
;
12938 constraint ((inst
.relocs
[0].type
12939 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12940 && (inst
.relocs
[0].type
12941 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12942 THUMB1_RELOC_ONLY
);
12944 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12945 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12946 inst
.instruction
|= Rn
<< r0off
;
12947 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12950 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12951 && (inst
.instruction
== T_MNEM_mov
12952 || inst
.instruction
== T_MNEM_movs
))
12954 /* Register shifts are encoded as separate shift instructions. */
12955 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12957 if (in_pred_block ())
12962 if (inst
.size_req
== 4)
12965 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12971 switch (inst
.operands
[1].shift_kind
)
12974 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12977 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12980 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12983 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12989 inst
.instruction
= opcode
;
12992 inst
.instruction
|= Rn
;
12993 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12998 inst
.instruction
|= CONDS_BIT
;
13000 inst
.instruction
|= Rn
<< 8;
13001 inst
.instruction
|= Rm
<< 16;
13002 inst
.instruction
|= inst
.operands
[1].imm
;
13007 /* Some mov with immediate shift have narrow variants.
13008 Register shifts are handled above. */
13009 if (low_regs
&& inst
.operands
[1].shifted
13010 && (inst
.instruction
== T_MNEM_mov
13011 || inst
.instruction
== T_MNEM_movs
))
13013 if (in_pred_block ())
13014 narrow
= (inst
.instruction
== T_MNEM_mov
);
13016 narrow
= (inst
.instruction
== T_MNEM_movs
);
13021 switch (inst
.operands
[1].shift_kind
)
13023 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13024 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13025 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13026 default: narrow
= FALSE
; break;
13032 inst
.instruction
|= Rn
;
13033 inst
.instruction
|= Rm
<< 3;
13034 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13038 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13039 inst
.instruction
|= Rn
<< r0off
;
13040 encode_thumb32_shifted_operand (1);
13044 switch (inst
.instruction
)
13047 /* In v4t or v5t a move of two lowregs produces unpredictable
13048 results. Don't allow this. */
13051 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13052 "MOV Rd, Rs with two low registers is not "
13053 "permitted on this architecture");
13054 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13058 inst
.instruction
= T_OPCODE_MOV_HR
;
13059 inst
.instruction
|= (Rn
& 0x8) << 4;
13060 inst
.instruction
|= (Rn
& 0x7);
13061 inst
.instruction
|= Rm
<< 3;
13065 /* We know we have low registers at this point.
13066 Generate LSLS Rd, Rs, #0. */
13067 inst
.instruction
= T_OPCODE_LSL_I
;
13068 inst
.instruction
|= Rn
;
13069 inst
.instruction
|= Rm
<< 3;
13075 inst
.instruction
= T_OPCODE_CMP_LR
;
13076 inst
.instruction
|= Rn
;
13077 inst
.instruction
|= Rm
<< 3;
13081 inst
.instruction
= T_OPCODE_CMP_HR
;
13082 inst
.instruction
|= (Rn
& 0x8) << 4;
13083 inst
.instruction
|= (Rn
& 0x7);
13084 inst
.instruction
|= Rm
<< 3;
13091 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13093 /* PR 10443: Do not silently ignore shifted operands. */
13094 constraint (inst
.operands
[1].shifted
,
13095 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13097 if (inst
.operands
[1].isreg
)
13099 if (Rn
< 8 && Rm
< 8)
13101 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13102 since a MOV instruction produces unpredictable results. */
13103 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13104 inst
.instruction
= T_OPCODE_ADD_I3
;
13106 inst
.instruction
= T_OPCODE_CMP_LR
;
13108 inst
.instruction
|= Rn
;
13109 inst
.instruction
|= Rm
<< 3;
13113 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13114 inst
.instruction
= T_OPCODE_MOV_HR
;
13116 inst
.instruction
= T_OPCODE_CMP_HR
;
13122 constraint (Rn
> 7,
13123 _("only lo regs allowed with immediate"));
13124 inst
.instruction
|= Rn
<< 8;
13125 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13136 top
= (inst
.instruction
& 0x00800000) != 0;
13137 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13139 constraint (top
, _(":lower16: not allowed in this instruction"));
13140 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13142 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13144 constraint (!top
, _(":upper16: not allowed in this instruction"));
13145 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13148 Rd
= inst
.operands
[0].reg
;
13149 reject_bad_reg (Rd
);
13151 inst
.instruction
|= Rd
<< 8;
13152 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13154 imm
= inst
.relocs
[0].exp
.X_add_number
;
13155 inst
.instruction
|= (imm
& 0xf000) << 4;
13156 inst
.instruction
|= (imm
& 0x0800) << 15;
13157 inst
.instruction
|= (imm
& 0x0700) << 4;
13158 inst
.instruction
|= (imm
& 0x00ff);
13163 do_t_mvn_tst (void)
13167 Rn
= inst
.operands
[0].reg
;
13168 Rm
= inst
.operands
[1].reg
;
13170 if (inst
.instruction
== T_MNEM_cmp
13171 || inst
.instruction
== T_MNEM_cmn
)
13172 constraint (Rn
== REG_PC
, BAD_PC
);
13174 reject_bad_reg (Rn
);
13175 reject_bad_reg (Rm
);
13177 if (unified_syntax
)
13179 int r0off
= (inst
.instruction
== T_MNEM_mvn
13180 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13181 bfd_boolean narrow
;
13183 if (inst
.size_req
== 4
13184 || inst
.instruction
> 0xffff
13185 || inst
.operands
[1].shifted
13186 || Rn
> 7 || Rm
> 7)
13188 else if (inst
.instruction
== T_MNEM_cmn
13189 || inst
.instruction
== T_MNEM_tst
)
13191 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13192 narrow
= !in_pred_block ();
13194 narrow
= in_pred_block ();
13196 if (!inst
.operands
[1].isreg
)
13198 /* For an immediate, we always generate a 32-bit opcode;
13199 section relaxation will shrink it later if possible. */
13200 if (inst
.instruction
< 0xffff)
13201 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13202 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13203 inst
.instruction
|= Rn
<< r0off
;
13204 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13208 /* See if we can do this with a 16-bit instruction. */
13211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13212 inst
.instruction
|= Rn
;
13213 inst
.instruction
|= Rm
<< 3;
13217 constraint (inst
.operands
[1].shifted
13218 && inst
.operands
[1].immisreg
,
13219 _("shift must be constant"));
13220 if (inst
.instruction
< 0xffff)
13221 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13222 inst
.instruction
|= Rn
<< r0off
;
13223 encode_thumb32_shifted_operand (1);
13229 constraint (inst
.instruction
> 0xffff
13230 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13231 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13232 _("unshifted register required"));
13233 constraint (Rn
> 7 || Rm
> 7,
13236 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13237 inst
.instruction
|= Rn
;
13238 inst
.instruction
|= Rm
<< 3;
13247 if (do_vfp_nsyn_mrs () == SUCCESS
)
13250 Rd
= inst
.operands
[0].reg
;
13251 reject_bad_reg (Rd
);
13252 inst
.instruction
|= Rd
<< 8;
13254 if (inst
.operands
[1].isreg
)
13256 unsigned br
= inst
.operands
[1].reg
;
13257 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13258 as_bad (_("bad register for mrs"));
13260 inst
.instruction
|= br
& (0xf << 16);
13261 inst
.instruction
|= (br
& 0x300) >> 4;
13262 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13266 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13268 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13270 /* PR gas/12698: The constraint is only applied for m_profile.
13271 If the user has specified -march=all, we want to ignore it as
13272 we are building for any CPU type, including non-m variants. */
13273 bfd_boolean m_profile
=
13274 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13275 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13276 "not support requested special purpose register"));
13279 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13281 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13282 _("'APSR', 'CPSR' or 'SPSR' expected"));
13284 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13285 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13286 inst
.instruction
|= 0xf0000;
13296 if (do_vfp_nsyn_msr () == SUCCESS
)
13299 constraint (!inst
.operands
[1].isreg
,
13300 _("Thumb encoding does not support an immediate here"));
13302 if (inst
.operands
[0].isreg
)
13303 flags
= (int)(inst
.operands
[0].reg
);
13305 flags
= inst
.operands
[0].imm
;
13307 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13309 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13311 /* PR gas/12698: The constraint is only applied for m_profile.
13312 If the user has specified -march=all, we want to ignore it as
13313 we are building for any CPU type, including non-m variants. */
13314 bfd_boolean m_profile
=
13315 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13316 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13317 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13318 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13319 && bits
!= PSR_f
)) && m_profile
,
13320 _("selected processor does not support requested special "
13321 "purpose register"));
13324 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13325 "requested special purpose register"));
13327 Rn
= inst
.operands
[1].reg
;
13328 reject_bad_reg (Rn
);
13330 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13331 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13332 inst
.instruction
|= (flags
& 0x300) >> 4;
13333 inst
.instruction
|= (flags
& 0xff);
13334 inst
.instruction
|= Rn
<< 16;
13340 bfd_boolean narrow
;
13341 unsigned Rd
, Rn
, Rm
;
13343 if (!inst
.operands
[2].present
)
13344 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13346 Rd
= inst
.operands
[0].reg
;
13347 Rn
= inst
.operands
[1].reg
;
13348 Rm
= inst
.operands
[2].reg
;
13350 if (unified_syntax
)
13352 if (inst
.size_req
== 4
13358 else if (inst
.instruction
== T_MNEM_muls
)
13359 narrow
= !in_pred_block ();
13361 narrow
= in_pred_block ();
13365 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13366 constraint (Rn
> 7 || Rm
> 7,
13373 /* 16-bit MULS/Conditional MUL. */
13374 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13375 inst
.instruction
|= Rd
;
13378 inst
.instruction
|= Rm
<< 3;
13380 inst
.instruction
|= Rn
<< 3;
13382 constraint (1, _("dest must overlap one source register"));
13386 constraint (inst
.instruction
!= T_MNEM_mul
,
13387 _("Thumb-2 MUL must not set flags"));
13389 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13390 inst
.instruction
|= Rd
<< 8;
13391 inst
.instruction
|= Rn
<< 16;
13392 inst
.instruction
|= Rm
<< 0;
13394 reject_bad_reg (Rd
);
13395 reject_bad_reg (Rn
);
13396 reject_bad_reg (Rm
);
13403 unsigned RdLo
, RdHi
, Rn
, Rm
;
13405 RdLo
= inst
.operands
[0].reg
;
13406 RdHi
= inst
.operands
[1].reg
;
13407 Rn
= inst
.operands
[2].reg
;
13408 Rm
= inst
.operands
[3].reg
;
13410 reject_bad_reg (RdLo
);
13411 reject_bad_reg (RdHi
);
13412 reject_bad_reg (Rn
);
13413 reject_bad_reg (Rm
);
13415 inst
.instruction
|= RdLo
<< 12;
13416 inst
.instruction
|= RdHi
<< 8;
13417 inst
.instruction
|= Rn
<< 16;
13418 inst
.instruction
|= Rm
;
13421 as_tsktsk (_("rdhi and rdlo must be different"));
13427 set_pred_insn_type (NEUTRAL_IT_INSN
);
13429 if (unified_syntax
)
13431 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13433 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13434 inst
.instruction
|= inst
.operands
[0].imm
;
13438 /* PR9722: Check for Thumb2 availability before
13439 generating a thumb2 nop instruction. */
13440 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13442 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13443 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13446 inst
.instruction
= 0x46c0;
13451 constraint (inst
.operands
[0].present
,
13452 _("Thumb does not support NOP with hints"));
13453 inst
.instruction
= 0x46c0;
13460 if (unified_syntax
)
13462 bfd_boolean narrow
;
13464 if (THUMB_SETS_FLAGS (inst
.instruction
))
13465 narrow
= !in_pred_block ();
13467 narrow
= in_pred_block ();
13468 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13470 if (inst
.size_req
== 4)
13475 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13476 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13477 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13481 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13482 inst
.instruction
|= inst
.operands
[0].reg
;
13483 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13488 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13490 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13492 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13493 inst
.instruction
|= inst
.operands
[0].reg
;
13494 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13503 Rd
= inst
.operands
[0].reg
;
13504 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13506 reject_bad_reg (Rd
);
13507 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13508 reject_bad_reg (Rn
);
13510 inst
.instruction
|= Rd
<< 8;
13511 inst
.instruction
|= Rn
<< 16;
13513 if (!inst
.operands
[2].isreg
)
13515 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13516 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13522 Rm
= inst
.operands
[2].reg
;
13523 reject_bad_reg (Rm
);
13525 constraint (inst
.operands
[2].shifted
13526 && inst
.operands
[2].immisreg
,
13527 _("shift must be constant"));
13528 encode_thumb32_shifted_operand (2);
13535 unsigned Rd
, Rn
, Rm
;
13537 Rd
= inst
.operands
[0].reg
;
13538 Rn
= inst
.operands
[1].reg
;
13539 Rm
= inst
.operands
[2].reg
;
13541 reject_bad_reg (Rd
);
13542 reject_bad_reg (Rn
);
13543 reject_bad_reg (Rm
);
13545 inst
.instruction
|= Rd
<< 8;
13546 inst
.instruction
|= Rn
<< 16;
13547 inst
.instruction
|= Rm
;
13548 if (inst
.operands
[3].present
)
13550 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13551 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13552 _("expression too complex"));
13553 inst
.instruction
|= (val
& 0x1c) << 10;
13554 inst
.instruction
|= (val
& 0x03) << 6;
13561 if (!inst
.operands
[3].present
)
13565 inst
.instruction
&= ~0x00000020;
13567 /* PR 10168. Swap the Rm and Rn registers. */
13568 Rtmp
= inst
.operands
[1].reg
;
13569 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13570 inst
.operands
[2].reg
= Rtmp
;
13578 if (inst
.operands
[0].immisreg
)
13579 reject_bad_reg (inst
.operands
[0].imm
);
13581 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13585 do_t_push_pop (void)
13589 constraint (inst
.operands
[0].writeback
,
13590 _("push/pop do not support {reglist}^"));
13591 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13592 _("expression too complex"));
13594 mask
= inst
.operands
[0].imm
;
13595 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13596 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13597 else if (inst
.size_req
!= 4
13598 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13599 ? REG_LR
: REG_PC
)))
13601 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13602 inst
.instruction
|= THUMB_PP_PC_LR
;
13603 inst
.instruction
|= mask
& 0xff;
13605 else if (unified_syntax
)
13607 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13608 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13612 inst
.error
= _("invalid register list to push/pop instruction");
13620 if (unified_syntax
)
13621 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13624 inst
.error
= _("invalid register list to push/pop instruction");
13630 do_t_vscclrm (void)
13632 if (inst
.operands
[0].issingle
)
13634 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13635 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13636 inst
.instruction
|= inst
.operands
[0].imm
;
13640 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13641 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13642 inst
.instruction
|= 1 << 8;
13643 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13652 Rd
= inst
.operands
[0].reg
;
13653 Rm
= inst
.operands
[1].reg
;
13655 reject_bad_reg (Rd
);
13656 reject_bad_reg (Rm
);
13658 inst
.instruction
|= Rd
<< 8;
13659 inst
.instruction
|= Rm
<< 16;
13660 inst
.instruction
|= Rm
;
13668 Rd
= inst
.operands
[0].reg
;
13669 Rm
= inst
.operands
[1].reg
;
13671 reject_bad_reg (Rd
);
13672 reject_bad_reg (Rm
);
13674 if (Rd
<= 7 && Rm
<= 7
13675 && inst
.size_req
!= 4)
13677 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13678 inst
.instruction
|= Rd
;
13679 inst
.instruction
|= Rm
<< 3;
13681 else if (unified_syntax
)
13683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13684 inst
.instruction
|= Rd
<< 8;
13685 inst
.instruction
|= Rm
<< 16;
13686 inst
.instruction
|= Rm
;
13689 inst
.error
= BAD_HIREG
;
13697 Rd
= inst
.operands
[0].reg
;
13698 Rm
= inst
.operands
[1].reg
;
13700 reject_bad_reg (Rd
);
13701 reject_bad_reg (Rm
);
13703 inst
.instruction
|= Rd
<< 8;
13704 inst
.instruction
|= Rm
;
13712 Rd
= inst
.operands
[0].reg
;
13713 Rs
= (inst
.operands
[1].present
13714 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13715 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13717 reject_bad_reg (Rd
);
13718 reject_bad_reg (Rs
);
13719 if (inst
.operands
[2].isreg
)
13720 reject_bad_reg (inst
.operands
[2].reg
);
13722 inst
.instruction
|= Rd
<< 8;
13723 inst
.instruction
|= Rs
<< 16;
13724 if (!inst
.operands
[2].isreg
)
13726 bfd_boolean narrow
;
13728 if ((inst
.instruction
& 0x00100000) != 0)
13729 narrow
= !in_pred_block ();
13731 narrow
= in_pred_block ();
13733 if (Rd
> 7 || Rs
> 7)
13736 if (inst
.size_req
== 4 || !unified_syntax
)
13739 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13740 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13743 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13744 relaxation, but it doesn't seem worth the hassle. */
13747 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13748 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13749 inst
.instruction
|= Rs
<< 3;
13750 inst
.instruction
|= Rd
;
13754 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13755 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13759 encode_thumb32_shifted_operand (2);
13765 if (warn_on_deprecated
13766 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13767 as_tsktsk (_("setend use is deprecated for ARMv8"));
13769 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13770 if (inst
.operands
[0].imm
)
13771 inst
.instruction
|= 0x8;
13777 if (!inst
.operands
[1].present
)
13778 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13780 if (unified_syntax
)
13782 bfd_boolean narrow
;
13785 switch (inst
.instruction
)
13788 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13790 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13792 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13794 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13798 if (THUMB_SETS_FLAGS (inst
.instruction
))
13799 narrow
= !in_pred_block ();
13801 narrow
= in_pred_block ();
13802 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13804 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13806 if (inst
.operands
[2].isreg
13807 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13808 || inst
.operands
[2].reg
> 7))
13810 if (inst
.size_req
== 4)
13813 reject_bad_reg (inst
.operands
[0].reg
);
13814 reject_bad_reg (inst
.operands
[1].reg
);
13818 if (inst
.operands
[2].isreg
)
13820 reject_bad_reg (inst
.operands
[2].reg
);
13821 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13822 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13823 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13824 inst
.instruction
|= inst
.operands
[2].reg
;
13826 /* PR 12854: Error on extraneous shifts. */
13827 constraint (inst
.operands
[2].shifted
,
13828 _("extraneous shift as part of operand to shift insn"));
13832 inst
.operands
[1].shifted
= 1;
13833 inst
.operands
[1].shift_kind
= shift_kind
;
13834 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13835 ? T_MNEM_movs
: T_MNEM_mov
);
13836 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13837 encode_thumb32_shifted_operand (1);
13838 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13839 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13844 if (inst
.operands
[2].isreg
)
13846 switch (shift_kind
)
13848 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13849 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13850 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13851 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13855 inst
.instruction
|= inst
.operands
[0].reg
;
13856 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13858 /* PR 12854: Error on extraneous shifts. */
13859 constraint (inst
.operands
[2].shifted
,
13860 _("extraneous shift as part of operand to shift insn"));
13864 switch (shift_kind
)
13866 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13867 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13868 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13871 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13872 inst
.instruction
|= inst
.operands
[0].reg
;
13873 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13879 constraint (inst
.operands
[0].reg
> 7
13880 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13881 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13883 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13885 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13886 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13887 _("source1 and dest must be same register"));
13889 switch (inst
.instruction
)
13891 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13892 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13893 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13894 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13898 inst
.instruction
|= inst
.operands
[0].reg
;
13899 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13901 /* PR 12854: Error on extraneous shifts. */
13902 constraint (inst
.operands
[2].shifted
,
13903 _("extraneous shift as part of operand to shift insn"));
13907 switch (inst
.instruction
)
13909 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13910 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13911 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13912 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13915 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13916 inst
.instruction
|= inst
.operands
[0].reg
;
13917 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13925 unsigned Rd
, Rn
, Rm
;
13927 Rd
= inst
.operands
[0].reg
;
13928 Rn
= inst
.operands
[1].reg
;
13929 Rm
= inst
.operands
[2].reg
;
13931 reject_bad_reg (Rd
);
13932 reject_bad_reg (Rn
);
13933 reject_bad_reg (Rm
);
13935 inst
.instruction
|= Rd
<< 8;
13936 inst
.instruction
|= Rn
<< 16;
13937 inst
.instruction
|= Rm
;
13943 unsigned Rd
, Rn
, Rm
;
13945 Rd
= inst
.operands
[0].reg
;
13946 Rm
= inst
.operands
[1].reg
;
13947 Rn
= inst
.operands
[2].reg
;
13949 reject_bad_reg (Rd
);
13950 reject_bad_reg (Rn
);
13951 reject_bad_reg (Rm
);
13953 inst
.instruction
|= Rd
<< 8;
13954 inst
.instruction
|= Rn
<< 16;
13955 inst
.instruction
|= Rm
;
13961 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13962 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13963 _("SMC is not permitted on this architecture"));
13964 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13965 _("expression too complex"));
13966 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13968 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13969 inst
.instruction
|= (value
& 0x000f) << 16;
13971 /* PR gas/15623: SMC instructions must be last in an IT block. */
13972 set_pred_insn_type_last ();
13978 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13980 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13981 inst
.instruction
|= (value
& 0x0fff);
13982 inst
.instruction
|= (value
& 0xf000) << 4;
13986 do_t_ssat_usat (int bias
)
13990 Rd
= inst
.operands
[0].reg
;
13991 Rn
= inst
.operands
[2].reg
;
13993 reject_bad_reg (Rd
);
13994 reject_bad_reg (Rn
);
13996 inst
.instruction
|= Rd
<< 8;
13997 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13998 inst
.instruction
|= Rn
<< 16;
14000 if (inst
.operands
[3].present
)
14002 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14004 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14006 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14007 _("expression too complex"));
14009 if (shift_amount
!= 0)
14011 constraint (shift_amount
> 31,
14012 _("shift expression is too large"));
14014 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14015 inst
.instruction
|= 0x00200000; /* sh bit. */
14017 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14018 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14026 do_t_ssat_usat (1);
14034 Rd
= inst
.operands
[0].reg
;
14035 Rn
= inst
.operands
[2].reg
;
14037 reject_bad_reg (Rd
);
14038 reject_bad_reg (Rn
);
14040 inst
.instruction
|= Rd
<< 8;
14041 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14042 inst
.instruction
|= Rn
<< 16;
14048 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14049 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14050 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14051 || inst
.operands
[2].negative
,
14054 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14056 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14058 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14059 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14065 if (!inst
.operands
[2].present
)
14066 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14068 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14069 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14070 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14073 inst
.instruction
|= inst
.operands
[0].reg
;
14074 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14075 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14076 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14082 unsigned Rd
, Rn
, Rm
;
14084 Rd
= inst
.operands
[0].reg
;
14085 Rn
= inst
.operands
[1].reg
;
14086 Rm
= inst
.operands
[2].reg
;
14088 reject_bad_reg (Rd
);
14089 reject_bad_reg (Rn
);
14090 reject_bad_reg (Rm
);
14092 inst
.instruction
|= Rd
<< 8;
14093 inst
.instruction
|= Rn
<< 16;
14094 inst
.instruction
|= Rm
;
14095 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14103 Rd
= inst
.operands
[0].reg
;
14104 Rm
= inst
.operands
[1].reg
;
14106 reject_bad_reg (Rd
);
14107 reject_bad_reg (Rm
);
14109 if (inst
.instruction
<= 0xffff
14110 && inst
.size_req
!= 4
14111 && Rd
<= 7 && Rm
<= 7
14112 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14114 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14115 inst
.instruction
|= Rd
;
14116 inst
.instruction
|= Rm
<< 3;
14118 else if (unified_syntax
)
14120 if (inst
.instruction
<= 0xffff)
14121 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14122 inst
.instruction
|= Rd
<< 8;
14123 inst
.instruction
|= Rm
;
14124 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14128 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14129 _("Thumb encoding does not support rotation"));
14130 constraint (1, BAD_HIREG
);
14137 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14146 half
= (inst
.instruction
& 0x10) != 0;
14147 set_pred_insn_type_last ();
14148 constraint (inst
.operands
[0].immisreg
,
14149 _("instruction requires register index"));
14151 Rn
= inst
.operands
[0].reg
;
14152 Rm
= inst
.operands
[0].imm
;
14154 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14155 constraint (Rn
== REG_SP
, BAD_SP
);
14156 reject_bad_reg (Rm
);
14158 constraint (!half
&& inst
.operands
[0].shifted
,
14159 _("instruction does not allow shifted index"));
14160 inst
.instruction
|= (Rn
<< 16) | Rm
;
14166 if (!inst
.operands
[0].present
)
14167 inst
.operands
[0].imm
= 0;
14169 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14171 constraint (inst
.size_req
== 2,
14172 _("immediate value out of range"));
14173 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14174 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14175 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14179 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14180 inst
.instruction
|= inst
.operands
[0].imm
;
14183 set_pred_insn_type (NEUTRAL_IT_INSN
);
14190 do_t_ssat_usat (0);
14198 Rd
= inst
.operands
[0].reg
;
14199 Rn
= inst
.operands
[2].reg
;
14201 reject_bad_reg (Rd
);
14202 reject_bad_reg (Rn
);
14204 inst
.instruction
|= Rd
<< 8;
14205 inst
.instruction
|= inst
.operands
[1].imm
;
14206 inst
.instruction
|= Rn
<< 16;
14209 /* Checking the range of the branch offset (VAL) with NBITS bits
14210 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14212 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14214 gas_assert (nbits
> 0 && nbits
<= 32);
14217 int cmp
= (1 << (nbits
- 1));
14218 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14223 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14229 /* For branches in Armv8.1-M Mainline. */
14231 do_t_branch_future (void)
14233 unsigned long insn
= inst
.instruction
;
14235 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14236 if (inst
.operands
[0].hasreloc
== 0)
14238 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14239 as_bad (BAD_BRANCH_OFF
);
14241 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14245 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14246 inst
.relocs
[0].pc_rel
= 1;
14252 if (inst
.operands
[1].hasreloc
== 0)
14254 int val
= inst
.operands
[1].imm
;
14255 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14256 as_bad (BAD_BRANCH_OFF
);
14258 int immA
= (val
& 0x0001f000) >> 12;
14259 int immB
= (val
& 0x00000ffc) >> 2;
14260 int immC
= (val
& 0x00000002) >> 1;
14261 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14265 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14266 inst
.relocs
[1].pc_rel
= 1;
14271 if (inst
.operands
[1].hasreloc
== 0)
14273 int val
= inst
.operands
[1].imm
;
14274 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14275 as_bad (BAD_BRANCH_OFF
);
14277 int immA
= (val
& 0x0007f000) >> 12;
14278 int immB
= (val
& 0x00000ffc) >> 2;
14279 int immC
= (val
& 0x00000002) >> 1;
14280 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14284 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14285 inst
.relocs
[1].pc_rel
= 1;
14289 case T_MNEM_bfcsel
:
14291 if (inst
.operands
[1].hasreloc
== 0)
14293 int val
= inst
.operands
[1].imm
;
14294 int immA
= (val
& 0x00001000) >> 12;
14295 int immB
= (val
& 0x00000ffc) >> 2;
14296 int immC
= (val
& 0x00000002) >> 1;
14297 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14301 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14302 inst
.relocs
[1].pc_rel
= 1;
14306 if (inst
.operands
[2].hasreloc
== 0)
14308 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14309 int val2
= inst
.operands
[2].imm
;
14310 int val0
= inst
.operands
[0].imm
& 0x1f;
14311 int diff
= val2
- val0
;
14313 inst
.instruction
|= 1 << 17; /* T bit. */
14314 else if (diff
!= 2)
14315 as_bad (_("out of range label-relative fixup value"));
14319 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14320 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14321 inst
.relocs
[2].pc_rel
= 1;
14325 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14326 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14331 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14338 /* Helper function for do_t_loloop to handle relocations. */
14340 v8_1_loop_reloc (int is_le
)
14342 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14344 int value
= inst
.relocs
[0].exp
.X_add_number
;
14345 value
= (is_le
) ? -value
: value
;
14347 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14348 as_bad (BAD_BRANCH_OFF
);
14352 immh
= (value
& 0x00000ffc) >> 2;
14353 imml
= (value
& 0x00000002) >> 1;
14355 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14359 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14360 inst
.relocs
[0].pc_rel
= 1;
14364 /* For shifts with four operands in MVE. */
14366 do_mve_scalar_shift1 (void)
14368 unsigned int value
= inst
.operands
[2].imm
;
14370 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14371 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14373 /* Setting the bit for saturation. */
14374 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14376 /* Assuming Rm is already checked not to be 11x1. */
14377 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14378 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14379 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14382 /* For shifts in MVE. */
14384 do_mve_scalar_shift (void)
14386 if (!inst
.operands
[2].present
)
14388 inst
.operands
[2] = inst
.operands
[1];
14389 inst
.operands
[1].reg
= 0xf;
14392 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14393 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14395 if (inst
.operands
[2].isreg
)
14397 /* Assuming Rm is already checked not to be 11x1. */
14398 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14399 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14400 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14404 /* Assuming imm is already checked as [1,32]. */
14405 unsigned int value
= inst
.operands
[2].imm
;
14406 inst
.instruction
|= (value
& 0x1c) << 10;
14407 inst
.instruction
|= (value
& 0x03) << 6;
14408 /* Change last 4 bits from 0xd to 0xf. */
14409 inst
.instruction
|= 0x2;
14413 /* MVE instruction encoder helpers. */
14414 #define M_MNEM_vabav 0xee800f01
14415 #define M_MNEM_vmladav 0xeef00e00
14416 #define M_MNEM_vmladava 0xeef00e20
14417 #define M_MNEM_vmladavx 0xeef01e00
14418 #define M_MNEM_vmladavax 0xeef01e20
14419 #define M_MNEM_vmlsdav 0xeef00e01
14420 #define M_MNEM_vmlsdava 0xeef00e21
14421 #define M_MNEM_vmlsdavx 0xeef01e01
14422 #define M_MNEM_vmlsdavax 0xeef01e21
14423 #define M_MNEM_vmullt 0xee011e00
14424 #define M_MNEM_vmullb 0xee010e00
14425 #define M_MNEM_vst20 0xfc801e00
14426 #define M_MNEM_vst21 0xfc801e20
14427 #define M_MNEM_vst40 0xfc801e01
14428 #define M_MNEM_vst41 0xfc801e21
14429 #define M_MNEM_vst42 0xfc801e41
14430 #define M_MNEM_vst43 0xfc801e61
14431 #define M_MNEM_vld20 0xfc901e00
14432 #define M_MNEM_vld21 0xfc901e20
14433 #define M_MNEM_vld40 0xfc901e01
14434 #define M_MNEM_vld41 0xfc901e21
14435 #define M_MNEM_vld42 0xfc901e41
14436 #define M_MNEM_vld43 0xfc901e61
14437 #define M_MNEM_vstrb 0xec000e00
14438 #define M_MNEM_vstrh 0xec000e10
14439 #define M_MNEM_vstrw 0xec000e40
14440 #define M_MNEM_vstrd 0xec000e50
14441 #define M_MNEM_vldrb 0xec100e00
14442 #define M_MNEM_vldrh 0xec100e10
14443 #define M_MNEM_vldrw 0xec100e40
14444 #define M_MNEM_vldrd 0xec100e50
14445 #define M_MNEM_vmovlt 0xeea01f40
14446 #define M_MNEM_vmovlb 0xeea00f40
14447 #define M_MNEM_vmovnt 0xfe311e81
14448 #define M_MNEM_vmovnb 0xfe310e81
14449 #define M_MNEM_vadc 0xee300f00
14450 #define M_MNEM_vadci 0xee301f00
14451 #define M_MNEM_vbrsr 0xfe011e60
14452 #define M_MNEM_vaddlv 0xee890f00
14453 #define M_MNEM_vaddlva 0xee890f20
14454 #define M_MNEM_vaddv 0xeef10f00
14455 #define M_MNEM_vaddva 0xeef10f20
14456 #define M_MNEM_vddup 0xee011f6e
14457 #define M_MNEM_vdwdup 0xee011f60
14458 #define M_MNEM_vidup 0xee010f6e
14459 #define M_MNEM_viwdup 0xee010f60
14460 #define M_MNEM_vmaxv 0xeee20f00
14461 #define M_MNEM_vmaxav 0xeee00f00
14462 #define M_MNEM_vminv 0xeee20f80
14463 #define M_MNEM_vminav 0xeee00f80
14464 #define M_MNEM_vmlaldav 0xee800e00
14465 #define M_MNEM_vmlaldava 0xee800e20
14466 #define M_MNEM_vmlaldavx 0xee801e00
14467 #define M_MNEM_vmlaldavax 0xee801e20
14468 #define M_MNEM_vmlsldav 0xee800e01
14469 #define M_MNEM_vmlsldava 0xee800e21
14470 #define M_MNEM_vmlsldavx 0xee801e01
14471 #define M_MNEM_vmlsldavax 0xee801e21
14472 #define M_MNEM_vrmlaldavhx 0xee801f00
14473 #define M_MNEM_vrmlaldavhax 0xee801f20
14474 #define M_MNEM_vrmlsldavh 0xfe800e01
14475 #define M_MNEM_vrmlsldavha 0xfe800e21
14476 #define M_MNEM_vrmlsldavhx 0xfe801e01
14477 #define M_MNEM_vrmlsldavhax 0xfe801e21
14478 #define M_MNEM_vqmovnt 0xee331e01
14479 #define M_MNEM_vqmovnb 0xee330e01
14480 #define M_MNEM_vqmovunt 0xee311e81
14481 #define M_MNEM_vqmovunb 0xee310e81
14482 #define M_MNEM_vshrnt 0xee801fc1
14483 #define M_MNEM_vshrnb 0xee800fc1
14484 #define M_MNEM_vrshrnt 0xfe801fc1
14485 #define M_MNEM_vqshrnt 0xee801f40
14486 #define M_MNEM_vqshrnb 0xee800f40
14487 #define M_MNEM_vqshrunt 0xee801fc0
14488 #define M_MNEM_vqshrunb 0xee800fc0
14489 #define M_MNEM_vrshrnb 0xfe800fc1
14490 #define M_MNEM_vqrshrnt 0xee801f41
14491 #define M_MNEM_vqrshrnb 0xee800f41
14492 #define M_MNEM_vqrshrunt 0xfe801fc0
14493 #define M_MNEM_vqrshrunb 0xfe800fc0
14495 /* Neon instruction encoder helpers. */
14497 /* Encodings for the different types for various Neon opcodes. */
14499 /* An "invalid" code for the following tables. */
14502 struct neon_tab_entry
14505 unsigned float_or_poly
;
14506 unsigned scalar_or_imm
;
14509 /* Map overloaded Neon opcodes to their respective encodings. */
14510 #define NEON_ENC_TAB \
14511 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14512 X(vabdl, 0x0800700, N_INV, N_INV), \
14513 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14514 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14515 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14516 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14517 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14518 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14519 X(vaddl, 0x0800000, N_INV, N_INV), \
14520 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14521 X(vsubl, 0x0800200, N_INV, N_INV), \
14522 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14523 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14524 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14525 /* Register variants of the following two instructions are encoded as
14526 vcge / vcgt with the operands reversed. */ \
14527 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14528 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14529 X(vfma, N_INV, 0x0000c10, N_INV), \
14530 X(vfms, N_INV, 0x0200c10, N_INV), \
14531 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14532 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14533 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14534 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14535 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14536 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14537 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14538 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14539 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14540 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14541 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14542 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14543 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14544 X(vshl, 0x0000400, N_INV, 0x0800510), \
14545 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14546 X(vand, 0x0000110, N_INV, 0x0800030), \
14547 X(vbic, 0x0100110, N_INV, 0x0800030), \
14548 X(veor, 0x1000110, N_INV, N_INV), \
14549 X(vorn, 0x0300110, N_INV, 0x0800010), \
14550 X(vorr, 0x0200110, N_INV, 0x0800010), \
14551 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14552 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14553 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14554 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14555 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14556 X(vst1, 0x0000000, 0x0800000, N_INV), \
14557 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14558 X(vst2, 0x0000100, 0x0800100, N_INV), \
14559 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14560 X(vst3, 0x0000200, 0x0800200, N_INV), \
14561 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14562 X(vst4, 0x0000300, 0x0800300, N_INV), \
14563 X(vmovn, 0x1b20200, N_INV, N_INV), \
14564 X(vtrn, 0x1b20080, N_INV, N_INV), \
14565 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14566 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14567 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14568 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14569 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14570 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14571 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14572 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14573 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14574 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14575 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14576 X(vseleq, 0xe000a00, N_INV, N_INV), \
14577 X(vselvs, 0xe100a00, N_INV, N_INV), \
14578 X(vselge, 0xe200a00, N_INV, N_INV), \
14579 X(vselgt, 0xe300a00, N_INV, N_INV), \
14580 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14581 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14582 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14583 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14584 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14585 X(aes, 0x3b00300, N_INV, N_INV), \
14586 X(sha3op, 0x2000c00, N_INV, N_INV), \
14587 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14588 X(sha2op, 0x3ba0380, N_INV, N_INV)
14592 #define X(OPC,I,F,S) N_MNEM_##OPC
14597 static const struct neon_tab_entry neon_enc_tab
[] =
14599 #define X(OPC,I,F,S) { (I), (F), (S) }
14604 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14605 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14606 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14607 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14608 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14609 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14610 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14611 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14612 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14613 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14614 #define NEON_ENC_SINGLE_(X) \
14615 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14616 #define NEON_ENC_DOUBLE_(X) \
14617 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14618 #define NEON_ENC_FPV8_(X) \
14619 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14621 #define NEON_ENCODE(type, inst) \
14624 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14625 inst.is_neon = 1; \
14629 #define check_neon_suffixes \
14632 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14634 as_bad (_("invalid neon suffix for non neon instruction")); \
14640 /* Define shapes for instruction operands. The following mnemonic characters
14641 are used in this table:
14643 F - VFP S<n> register
14644 D - Neon D<n> register
14645 Q - Neon Q<n> register
14649 L - D<n> register list
14651 This table is used to generate various data:
14652 - enumerations of the form NS_DDR to be used as arguments to
14654 - a table classifying shapes into single, double, quad, mixed.
14655 - a table used to drive neon_select_shape. */
14657 #define NEON_SHAPE_DEF \
14658 X(4, (R, R, Q, Q), QUAD), \
14659 X(4, (Q, R, R, I), QUAD), \
14660 X(4, (R, R, S, S), QUAD), \
14661 X(4, (S, S, R, R), QUAD), \
14662 X(3, (Q, R, I), QUAD), \
14663 X(3, (I, Q, Q), QUAD), \
14664 X(3, (I, Q, R), QUAD), \
14665 X(3, (R, Q, Q), QUAD), \
14666 X(3, (D, D, D), DOUBLE), \
14667 X(3, (Q, Q, Q), QUAD), \
14668 X(3, (D, D, I), DOUBLE), \
14669 X(3, (Q, Q, I), QUAD), \
14670 X(3, (D, D, S), DOUBLE), \
14671 X(3, (Q, Q, S), QUAD), \
14672 X(3, (Q, Q, R), QUAD), \
14673 X(3, (R, R, Q), QUAD), \
14674 X(2, (R, Q), QUAD), \
14675 X(2, (D, D), DOUBLE), \
14676 X(2, (Q, Q), QUAD), \
14677 X(2, (D, S), DOUBLE), \
14678 X(2, (Q, S), QUAD), \
14679 X(2, (D, R), DOUBLE), \
14680 X(2, (Q, R), QUAD), \
14681 X(2, (D, I), DOUBLE), \
14682 X(2, (Q, I), QUAD), \
14683 X(3, (D, L, D), DOUBLE), \
14684 X(2, (D, Q), MIXED), \
14685 X(2, (Q, D), MIXED), \
14686 X(3, (D, Q, I), MIXED), \
14687 X(3, (Q, D, I), MIXED), \
14688 X(3, (Q, D, D), MIXED), \
14689 X(3, (D, Q, Q), MIXED), \
14690 X(3, (Q, Q, D), MIXED), \
14691 X(3, (Q, D, S), MIXED), \
14692 X(3, (D, Q, S), MIXED), \
14693 X(4, (D, D, D, I), DOUBLE), \
14694 X(4, (Q, Q, Q, I), QUAD), \
14695 X(4, (D, D, S, I), DOUBLE), \
14696 X(4, (Q, Q, S, I), QUAD), \
14697 X(2, (F, F), SINGLE), \
14698 X(3, (F, F, F), SINGLE), \
14699 X(2, (F, I), SINGLE), \
14700 X(2, (F, D), MIXED), \
14701 X(2, (D, F), MIXED), \
14702 X(3, (F, F, I), MIXED), \
14703 X(4, (R, R, F, F), SINGLE), \
14704 X(4, (F, F, R, R), SINGLE), \
14705 X(3, (D, R, R), DOUBLE), \
14706 X(3, (R, R, D), DOUBLE), \
14707 X(2, (S, R), SINGLE), \
14708 X(2, (R, S), SINGLE), \
14709 X(2, (F, R), SINGLE), \
14710 X(2, (R, F), SINGLE), \
14711 /* Used for MVE tail predicated loop instructions. */\
14712 X(2, (R, R), QUAD), \
14713 /* Half float shape supported so far. */\
14714 X (2, (H, D), MIXED), \
14715 X (2, (D, H), MIXED), \
14716 X (2, (H, F), MIXED), \
14717 X (2, (F, H), MIXED), \
14718 X (2, (H, H), HALF), \
14719 X (2, (H, R), HALF), \
14720 X (2, (R, H), HALF), \
14721 X (2, (H, I), HALF), \
14722 X (3, (H, H, H), HALF), \
14723 X (3, (H, F, I), MIXED), \
14724 X (3, (F, H, I), MIXED), \
14725 X (3, (D, H, H), MIXED), \
14726 X (3, (D, H, S), MIXED)
14728 #define S2(A,B) NS_##A##B
14729 #define S3(A,B,C) NS_##A##B##C
14730 #define S4(A,B,C,D) NS_##A##B##C##D
14732 #define X(N, L, C) S##N L
14745 enum neon_shape_class
14754 #define X(N, L, C) SC_##C
14756 static enum neon_shape_class neon_shape_class
[] =
14775 /* Register widths of above. */
14776 static unsigned neon_shape_el_size
[] =
14788 struct neon_shape_info
14791 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14794 #define S2(A,B) { SE_##A, SE_##B }
14795 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14796 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14798 #define X(N, L, C) { N, S##N L }
14800 static struct neon_shape_info neon_shape_tab
[] =
14810 /* Bit masks used in type checking given instructions.
14811 'N_EQK' means the type must be the same as (or based on in some way) the key
14812 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14813 set, various other bits can be set as well in order to modify the meaning of
14814 the type constraint. */
14816 enum neon_type_mask
14840 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14841 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14842 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14843 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14844 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14845 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14846 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14847 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14848 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14849 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14850 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14852 N_MAX_NONSPECIAL
= N_P64
14855 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14857 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14858 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14859 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14860 #define N_S_32 (N_S8 | N_S16 | N_S32)
14861 #define N_F_16_32 (N_F16 | N_F32)
14862 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14863 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14864 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14865 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14866 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14867 #define N_F_MVE (N_F16 | N_F32)
14868 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14870 /* Pass this as the first type argument to neon_check_type to ignore types
14872 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14874 /* Select a "shape" for the current instruction (describing register types or
14875 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14876 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14877 function of operand parsing, so this function doesn't need to be called.
14878 Shapes should be listed in order of decreasing length. */
14880 static enum neon_shape
14881 neon_select_shape (enum neon_shape shape
, ...)
14884 enum neon_shape first_shape
= shape
;
14886 /* Fix missing optional operands. FIXME: we don't know at this point how
14887 many arguments we should have, so this makes the assumption that we have
14888 > 1. This is true of all current Neon opcodes, I think, but may not be
14889 true in the future. */
14890 if (!inst
.operands
[1].present
)
14891 inst
.operands
[1] = inst
.operands
[0];
14893 va_start (ap
, shape
);
14895 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14900 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14902 if (!inst
.operands
[j
].present
)
14908 switch (neon_shape_tab
[shape
].el
[j
])
14910 /* If a .f16, .16, .u16, .s16 type specifier is given over
14911 a VFP single precision register operand, it's essentially
14912 means only half of the register is used.
14914 If the type specifier is given after the mnemonics, the
14915 information is stored in inst.vectype. If the type specifier
14916 is given after register operand, the information is stored
14917 in inst.operands[].vectype.
14919 When there is only one type specifier, and all the register
14920 operands are the same type of hardware register, the type
14921 specifier applies to all register operands.
14923 If no type specifier is given, the shape is inferred from
14924 operand information.
14927 vadd.f16 s0, s1, s2: NS_HHH
14928 vabs.f16 s0, s1: NS_HH
14929 vmov.f16 s0, r1: NS_HR
14930 vmov.f16 r0, s1: NS_RH
14931 vcvt.f16 r0, s1: NS_RH
14932 vcvt.f16.s32 s2, s2, #29: NS_HFI
14933 vcvt.f16.s32 s2, s2: NS_HF
14936 if (!(inst
.operands
[j
].isreg
14937 && inst
.operands
[j
].isvec
14938 && inst
.operands
[j
].issingle
14939 && !inst
.operands
[j
].isquad
14940 && ((inst
.vectype
.elems
== 1
14941 && inst
.vectype
.el
[0].size
== 16)
14942 || (inst
.vectype
.elems
> 1
14943 && inst
.vectype
.el
[j
].size
== 16)
14944 || (inst
.vectype
.elems
== 0
14945 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14946 && inst
.operands
[j
].vectype
.size
== 16))))
14951 if (!(inst
.operands
[j
].isreg
14952 && inst
.operands
[j
].isvec
14953 && inst
.operands
[j
].issingle
14954 && !inst
.operands
[j
].isquad
14955 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14956 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14957 || (inst
.vectype
.elems
== 0
14958 && (inst
.operands
[j
].vectype
.size
== 32
14959 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14964 if (!(inst
.operands
[j
].isreg
14965 && inst
.operands
[j
].isvec
14966 && !inst
.operands
[j
].isquad
14967 && !inst
.operands
[j
].issingle
))
14972 if (!(inst
.operands
[j
].isreg
14973 && !inst
.operands
[j
].isvec
))
14978 if (!(inst
.operands
[j
].isreg
14979 && inst
.operands
[j
].isvec
14980 && inst
.operands
[j
].isquad
14981 && !inst
.operands
[j
].issingle
))
14986 if (!(!inst
.operands
[j
].isreg
14987 && !inst
.operands
[j
].isscalar
))
14992 if (!(!inst
.operands
[j
].isreg
14993 && inst
.operands
[j
].isscalar
))
15003 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15004 /* We've matched all the entries in the shape table, and we don't
15005 have any left over operands which have not been matched. */
15011 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15012 first_error (_("invalid instruction shape"));
15017 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15018 means the Q bit should be set). */
15021 neon_quad (enum neon_shape shape
)
15023 return neon_shape_class
[shape
] == SC_QUAD
;
15027 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15030 /* Allow modification to be made to types which are constrained to be
15031 based on the key element, based on bits set alongside N_EQK. */
15032 if ((typebits
& N_EQK
) != 0)
15034 if ((typebits
& N_HLF
) != 0)
15036 else if ((typebits
& N_DBL
) != 0)
15038 if ((typebits
& N_SGN
) != 0)
15039 *g_type
= NT_signed
;
15040 else if ((typebits
& N_UNS
) != 0)
15041 *g_type
= NT_unsigned
;
15042 else if ((typebits
& N_INT
) != 0)
15043 *g_type
= NT_integer
;
15044 else if ((typebits
& N_FLT
) != 0)
15045 *g_type
= NT_float
;
15046 else if ((typebits
& N_SIZ
) != 0)
15047 *g_type
= NT_untyped
;
15051 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15052 operand type, i.e. the single type specified in a Neon instruction when it
15053 is the only one given. */
15055 static struct neon_type_el
15056 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15058 struct neon_type_el dest
= *key
;
15060 gas_assert ((thisarg
& N_EQK
) != 0);
15062 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15067 /* Convert Neon type and size into compact bitmask representation. */
15069 static enum neon_type_mask
15070 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15077 case 8: return N_8
;
15078 case 16: return N_16
;
15079 case 32: return N_32
;
15080 case 64: return N_64
;
15088 case 8: return N_I8
;
15089 case 16: return N_I16
;
15090 case 32: return N_I32
;
15091 case 64: return N_I64
;
15099 case 16: return N_F16
;
15100 case 32: return N_F32
;
15101 case 64: return N_F64
;
15109 case 8: return N_P8
;
15110 case 16: return N_P16
;
15111 case 64: return N_P64
;
15119 case 8: return N_S8
;
15120 case 16: return N_S16
;
15121 case 32: return N_S32
;
15122 case 64: return N_S64
;
15130 case 8: return N_U8
;
15131 case 16: return N_U16
;
15132 case 32: return N_U32
;
15133 case 64: return N_U64
;
15144 /* Convert compact Neon bitmask type representation to a type and size. Only
15145 handles the case where a single bit is set in the mask. */
15148 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15149 enum neon_type_mask mask
)
15151 if ((mask
& N_EQK
) != 0)
15154 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15156 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15158 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15160 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15165 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15167 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15168 *type
= NT_unsigned
;
15169 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15170 *type
= NT_integer
;
15171 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15172 *type
= NT_untyped
;
15173 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15175 else if ((mask
& (N_F_ALL
)) != 0)
15183 /* Modify a bitmask of allowed types. This is only needed for type
15187 modify_types_allowed (unsigned allowed
, unsigned mods
)
15190 enum neon_el_type type
;
15196 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15198 if (el_type_of_type_chk (&type
, &size
,
15199 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15201 neon_modify_type_size (mods
, &type
, &size
);
15202 destmask
|= type_chk_of_el_type (type
, size
);
15209 /* Check type and return type classification.
15210 The manual states (paraphrase): If one datatype is given, it indicates the
15212 - the second operand, if there is one
15213 - the operand, if there is no second operand
15214 - the result, if there are no operands.
15215 This isn't quite good enough though, so we use a concept of a "key" datatype
15216 which is set on a per-instruction basis, which is the one which matters when
15217 only one data type is written.
15218 Note: this function has side-effects (e.g. filling in missing operands). All
15219 Neon instructions should call it before performing bit encoding. */
15221 static struct neon_type_el
15222 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15225 unsigned i
, pass
, key_el
= 0;
15226 unsigned types
[NEON_MAX_TYPE_ELS
];
15227 enum neon_el_type k_type
= NT_invtype
;
15228 unsigned k_size
= -1u;
15229 struct neon_type_el badtype
= {NT_invtype
, -1};
15230 unsigned key_allowed
= 0;
15232 /* Optional registers in Neon instructions are always (not) in operand 1.
15233 Fill in the missing operand here, if it was omitted. */
15234 if (els
> 1 && !inst
.operands
[1].present
)
15235 inst
.operands
[1] = inst
.operands
[0];
15237 /* Suck up all the varargs. */
15239 for (i
= 0; i
< els
; i
++)
15241 unsigned thisarg
= va_arg (ap
, unsigned);
15242 if (thisarg
== N_IGNORE_TYPE
)
15247 types
[i
] = thisarg
;
15248 if ((thisarg
& N_KEY
) != 0)
15253 if (inst
.vectype
.elems
> 0)
15254 for (i
= 0; i
< els
; i
++)
15255 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15257 first_error (_("types specified in both the mnemonic and operands"));
15261 /* Duplicate inst.vectype elements here as necessary.
15262 FIXME: No idea if this is exactly the same as the ARM assembler,
15263 particularly when an insn takes one register and one non-register
15265 if (inst
.vectype
.elems
== 1 && els
> 1)
15268 inst
.vectype
.elems
= els
;
15269 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15270 for (j
= 0; j
< els
; j
++)
15272 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15275 else if (inst
.vectype
.elems
== 0 && els
> 0)
15278 /* No types were given after the mnemonic, so look for types specified
15279 after each operand. We allow some flexibility here; as long as the
15280 "key" operand has a type, we can infer the others. */
15281 for (j
= 0; j
< els
; j
++)
15282 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15283 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15285 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15287 for (j
= 0; j
< els
; j
++)
15288 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15289 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15294 first_error (_("operand types can't be inferred"));
15298 else if (inst
.vectype
.elems
!= els
)
15300 first_error (_("type specifier has the wrong number of parts"));
15304 for (pass
= 0; pass
< 2; pass
++)
15306 for (i
= 0; i
< els
; i
++)
15308 unsigned thisarg
= types
[i
];
15309 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15310 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15311 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15312 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15314 /* Decay more-specific signed & unsigned types to sign-insensitive
15315 integer types if sign-specific variants are unavailable. */
15316 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15317 && (types_allowed
& N_SU_ALL
) == 0)
15318 g_type
= NT_integer
;
15320 /* If only untyped args are allowed, decay any more specific types to
15321 them. Some instructions only care about signs for some element
15322 sizes, so handle that properly. */
15323 if (((types_allowed
& N_UNT
) == 0)
15324 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15325 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15326 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15327 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15328 g_type
= NT_untyped
;
15332 if ((thisarg
& N_KEY
) != 0)
15336 key_allowed
= thisarg
& ~N_KEY
;
15338 /* Check architecture constraint on FP16 extension. */
15340 && k_type
== NT_float
15341 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15343 inst
.error
= _(BAD_FP16
);
15350 if ((thisarg
& N_VFP
) != 0)
15352 enum neon_shape_el regshape
;
15353 unsigned regwidth
, match
;
15355 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15358 first_error (_("invalid instruction shape"));
15361 regshape
= neon_shape_tab
[ns
].el
[i
];
15362 regwidth
= neon_shape_el_size
[regshape
];
15364 /* In VFP mode, operands must match register widths. If we
15365 have a key operand, use its width, else use the width of
15366 the current operand. */
15372 /* FP16 will use a single precision register. */
15373 if (regwidth
== 32 && match
== 16)
15375 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15379 inst
.error
= _(BAD_FP16
);
15384 if (regwidth
!= match
)
15386 first_error (_("operand size must match register width"));
15391 if ((thisarg
& N_EQK
) == 0)
15393 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15395 if ((given_type
& types_allowed
) == 0)
15397 first_error (BAD_SIMD_TYPE
);
15403 enum neon_el_type mod_k_type
= k_type
;
15404 unsigned mod_k_size
= k_size
;
15405 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15406 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15408 first_error (_("inconsistent types in Neon instruction"));
15416 return inst
.vectype
.el
[key_el
];
15419 /* Neon-style VFP instruction forwarding. */
15421 /* Thumb VFP instructions have 0xE in the condition field. */
15424 do_vfp_cond_or_thumb (void)
15429 inst
.instruction
|= 0xe0000000;
15431 inst
.instruction
|= inst
.cond
<< 28;
15434 /* Look up and encode a simple mnemonic, for use as a helper function for the
15435 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15436 etc. It is assumed that operand parsing has already been done, and that the
15437 operands are in the form expected by the given opcode (this isn't necessarily
15438 the same as the form in which they were parsed, hence some massaging must
15439 take place before this function is called).
15440 Checks current arch version against that in the looked-up opcode. */
15443 do_vfp_nsyn_opcode (const char *opname
)
15445 const struct asm_opcode
*opcode
;
15447 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15453 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15460 inst
.instruction
= opcode
->tvalue
;
15461 opcode
->tencode ();
15465 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15466 opcode
->aencode ();
15471 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15473 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15475 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15478 do_vfp_nsyn_opcode ("fadds");
15480 do_vfp_nsyn_opcode ("fsubs");
15482 /* ARMv8.2 fp16 instruction. */
15484 do_scalar_fp16_v82_encode ();
15489 do_vfp_nsyn_opcode ("faddd");
15491 do_vfp_nsyn_opcode ("fsubd");
15495 /* Check operand types to see if this is a VFP instruction, and if so call
15499 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15501 enum neon_shape rs
;
15502 struct neon_type_el et
;
15507 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15508 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15512 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15513 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15514 N_F_ALL
| N_KEY
| N_VFP
);
15521 if (et
.type
!= NT_invtype
)
15532 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15534 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15536 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15539 do_vfp_nsyn_opcode ("fmacs");
15541 do_vfp_nsyn_opcode ("fnmacs");
15543 /* ARMv8.2 fp16 instruction. */
15545 do_scalar_fp16_v82_encode ();
15550 do_vfp_nsyn_opcode ("fmacd");
15552 do_vfp_nsyn_opcode ("fnmacd");
15557 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15559 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15561 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15564 do_vfp_nsyn_opcode ("ffmas");
15566 do_vfp_nsyn_opcode ("ffnmas");
15568 /* ARMv8.2 fp16 instruction. */
15570 do_scalar_fp16_v82_encode ();
15575 do_vfp_nsyn_opcode ("ffmad");
15577 do_vfp_nsyn_opcode ("ffnmad");
15582 do_vfp_nsyn_mul (enum neon_shape rs
)
15584 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15586 do_vfp_nsyn_opcode ("fmuls");
15588 /* ARMv8.2 fp16 instruction. */
15590 do_scalar_fp16_v82_encode ();
15593 do_vfp_nsyn_opcode ("fmuld");
15597 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15599 int is_neg
= (inst
.instruction
& 0x80) != 0;
15600 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15602 if (rs
== NS_FF
|| rs
== NS_HH
)
15605 do_vfp_nsyn_opcode ("fnegs");
15607 do_vfp_nsyn_opcode ("fabss");
15609 /* ARMv8.2 fp16 instruction. */
15611 do_scalar_fp16_v82_encode ();
15616 do_vfp_nsyn_opcode ("fnegd");
15618 do_vfp_nsyn_opcode ("fabsd");
15622 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15623 insns belong to Neon, and are handled elsewhere. */
15626 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15628 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15632 do_vfp_nsyn_opcode ("fldmdbs");
15634 do_vfp_nsyn_opcode ("fldmias");
15639 do_vfp_nsyn_opcode ("fstmdbs");
15641 do_vfp_nsyn_opcode ("fstmias");
15646 do_vfp_nsyn_sqrt (void)
15648 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15649 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15651 if (rs
== NS_FF
|| rs
== NS_HH
)
15653 do_vfp_nsyn_opcode ("fsqrts");
15655 /* ARMv8.2 fp16 instruction. */
15657 do_scalar_fp16_v82_encode ();
15660 do_vfp_nsyn_opcode ("fsqrtd");
15664 do_vfp_nsyn_div (void)
15666 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15667 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15668 N_F_ALL
| N_KEY
| N_VFP
);
15670 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15672 do_vfp_nsyn_opcode ("fdivs");
15674 /* ARMv8.2 fp16 instruction. */
15676 do_scalar_fp16_v82_encode ();
15679 do_vfp_nsyn_opcode ("fdivd");
15683 do_vfp_nsyn_nmul (void)
15685 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15686 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15687 N_F_ALL
| N_KEY
| N_VFP
);
15689 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15691 NEON_ENCODE (SINGLE
, inst
);
15692 do_vfp_sp_dyadic ();
15694 /* ARMv8.2 fp16 instruction. */
15696 do_scalar_fp16_v82_encode ();
15700 NEON_ENCODE (DOUBLE
, inst
);
15701 do_vfp_dp_rd_rn_rm ();
15703 do_vfp_cond_or_thumb ();
15707 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15711 neon_logbits (unsigned x
)
15713 return ffs (x
) - 4;
15716 #define LOW4(R) ((R) & 0xf)
15717 #define HI1(R) (((R) >> 4) & 1)
15720 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15725 first_error (BAD_EL_TYPE
);
15728 switch (inst
.operands
[0].imm
)
15731 first_error (_("invalid condition"));
15753 /* only accept eq and ne. */
15754 if (inst
.operands
[0].imm
> 1)
15756 first_error (_("invalid condition"));
15759 return inst
.operands
[0].imm
;
15761 if (inst
.operands
[0].imm
== 0x2)
15763 else if (inst
.operands
[0].imm
== 0x8)
15767 first_error (_("invalid condition"));
15771 switch (inst
.operands
[0].imm
)
15774 first_error (_("invalid condition"));
15790 /* Should be unreachable. */
15797 /* We are dealing with a vector predicated block. */
15798 if (inst
.operands
[0].present
)
15800 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15801 struct neon_type_el et
15802 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15805 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15807 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15809 if (et
.type
== NT_invtype
)
15812 if (et
.type
== NT_float
)
15814 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15816 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15817 inst
.instruction
|= (et
.size
== 16) << 28;
15818 inst
.instruction
|= 0x3 << 20;
15822 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15824 inst
.instruction
|= 1 << 28;
15825 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15828 if (inst
.operands
[2].isquad
)
15830 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15831 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15832 inst
.instruction
|= (fcond
& 0x2) >> 1;
15836 if (inst
.operands
[2].reg
== REG_SP
)
15837 as_tsktsk (MVE_BAD_SP
);
15838 inst
.instruction
|= 1 << 6;
15839 inst
.instruction
|= (fcond
& 0x2) << 4;
15840 inst
.instruction
|= inst
.operands
[2].reg
;
15842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15843 inst
.instruction
|= (fcond
& 0x4) << 10;
15844 inst
.instruction
|= (fcond
& 0x1) << 7;
15847 set_pred_insn_type (VPT_INSN
);
15849 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15850 | ((inst
.instruction
& 0xe000) >> 13);
15851 now_pred
.warn_deprecated
= FALSE
;
15852 now_pred
.type
= VECTOR_PRED
;
15859 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15860 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15861 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15862 if (!inst
.operands
[2].present
)
15863 first_error (_("MVE vector or ARM register expected"));
15864 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15866 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15867 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15868 && inst
.operands
[1].isquad
)
15870 inst
.instruction
= N_MNEM_vcmp
;
15874 if (inst
.cond
> COND_ALWAYS
)
15875 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15877 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15879 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15880 struct neon_type_el et
15881 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15884 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15885 && !inst
.operands
[2].iszr
, BAD_PC
);
15887 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15889 inst
.instruction
= 0xee010f00;
15890 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15891 inst
.instruction
|= (fcond
& 0x4) << 10;
15892 inst
.instruction
|= (fcond
& 0x1) << 7;
15893 if (et
.type
== NT_float
)
15895 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15897 inst
.instruction
|= (et
.size
== 16) << 28;
15898 inst
.instruction
|= 0x3 << 20;
15902 inst
.instruction
|= 1 << 28;
15903 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15905 if (inst
.operands
[2].isquad
)
15907 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15908 inst
.instruction
|= (fcond
& 0x2) >> 1;
15909 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15913 if (inst
.operands
[2].reg
== REG_SP
)
15914 as_tsktsk (MVE_BAD_SP
);
15915 inst
.instruction
|= 1 << 6;
15916 inst
.instruction
|= (fcond
& 0x2) << 4;
15917 inst
.instruction
|= inst
.operands
[2].reg
;
15925 do_mve_vmaxa_vmina (void)
15927 if (inst
.cond
> COND_ALWAYS
)
15928 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15930 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15932 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15933 struct neon_type_el et
15934 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15936 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15937 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15938 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15939 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15940 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15945 do_mve_vfmas (void)
15947 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15948 struct neon_type_el et
15949 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15951 if (inst
.cond
> COND_ALWAYS
)
15952 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15954 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15956 if (inst
.operands
[2].reg
== REG_SP
)
15957 as_tsktsk (MVE_BAD_SP
);
15958 else if (inst
.operands
[2].reg
== REG_PC
)
15959 as_tsktsk (MVE_BAD_PC
);
15961 inst
.instruction
|= (et
.size
== 16) << 28;
15962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15963 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15964 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15966 inst
.instruction
|= inst
.operands
[2].reg
;
15971 do_mve_viddup (void)
15973 if (inst
.cond
> COND_ALWAYS
)
15974 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15976 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15978 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15979 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15980 _("immediate must be either 1, 2, 4 or 8"));
15982 enum neon_shape rs
;
15983 struct neon_type_el et
;
15985 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15987 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15988 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15993 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15994 if (inst
.operands
[2].reg
== REG_SP
)
15995 as_tsktsk (MVE_BAD_SP
);
15996 else if (inst
.operands
[2].reg
== REG_PC
)
15997 first_error (BAD_PC
);
15999 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16000 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16001 Rm
= inst
.operands
[2].reg
>> 1;
16003 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16004 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16005 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16007 inst
.instruction
|= (imm
> 2) << 7;
16008 inst
.instruction
|= Rm
<< 1;
16009 inst
.instruction
|= (imm
== 2 || imm
== 8);
16014 do_mve_vmlas (void)
16016 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16017 struct neon_type_el et
16018 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16020 if (inst
.operands
[2].reg
== REG_PC
)
16021 as_tsktsk (MVE_BAD_PC
);
16022 else if (inst
.operands
[2].reg
== REG_SP
)
16023 as_tsktsk (MVE_BAD_SP
);
16025 if (inst
.cond
> COND_ALWAYS
)
16026 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16028 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16030 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16031 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16032 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16033 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16035 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16036 inst
.instruction
|= inst
.operands
[2].reg
;
16041 do_mve_vshll (void)
16043 struct neon_type_el et
16044 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16046 if (inst
.cond
> COND_ALWAYS
)
16047 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16049 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16051 int imm
= inst
.operands
[2].imm
;
16052 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16053 _("immediate value out of range"));
16055 if ((unsigned)imm
== et
.size
)
16057 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16058 inst
.instruction
|= 0x110001;
16062 inst
.instruction
|= (et
.size
+ imm
) << 16;
16063 inst
.instruction
|= 0x800140;
16066 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16067 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16068 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16069 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16070 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16075 do_mve_vshlc (void)
16077 if (inst
.cond
> COND_ALWAYS
)
16078 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16080 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16082 if (inst
.operands
[1].reg
== REG_PC
)
16083 as_tsktsk (MVE_BAD_PC
);
16084 else if (inst
.operands
[1].reg
== REG_SP
)
16085 as_tsktsk (MVE_BAD_SP
);
16087 int imm
= inst
.operands
[2].imm
;
16088 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16091 inst
.instruction
|= (imm
& 0x1f) << 16;
16092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16093 inst
.instruction
|= inst
.operands
[1].reg
;
16098 do_mve_vshrn (void)
16101 switch (inst
.instruction
)
16103 case M_MNEM_vshrnt
:
16104 case M_MNEM_vshrnb
:
16105 case M_MNEM_vrshrnt
:
16106 case M_MNEM_vrshrnb
:
16107 types
= N_I16
| N_I32
;
16109 case M_MNEM_vqshrnt
:
16110 case M_MNEM_vqshrnb
:
16111 case M_MNEM_vqrshrnt
:
16112 case M_MNEM_vqrshrnb
:
16113 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16115 case M_MNEM_vqshrunt
:
16116 case M_MNEM_vqshrunb
:
16117 case M_MNEM_vqrshrunt
:
16118 case M_MNEM_vqrshrunb
:
16119 types
= N_S16
| N_S32
;
16125 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16127 if (inst
.cond
> COND_ALWAYS
)
16128 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16130 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16132 unsigned Qd
= inst
.operands
[0].reg
;
16133 unsigned Qm
= inst
.operands
[1].reg
;
16134 unsigned imm
= inst
.operands
[2].imm
;
16135 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16137 ? _("immediate operand expected in the range [1,8]")
16138 : _("immediate operand expected in the range [1,16]"));
16140 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16141 inst
.instruction
|= HI1 (Qd
) << 22;
16142 inst
.instruction
|= (et
.size
- imm
) << 16;
16143 inst
.instruction
|= LOW4 (Qd
) << 12;
16144 inst
.instruction
|= HI1 (Qm
) << 5;
16145 inst
.instruction
|= LOW4 (Qm
);
16150 do_mve_vqmovn (void)
16152 struct neon_type_el et
;
16153 if (inst
.instruction
== M_MNEM_vqmovnt
16154 || inst
.instruction
== M_MNEM_vqmovnb
)
16155 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16156 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16158 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16160 if (inst
.cond
> COND_ALWAYS
)
16161 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16163 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16165 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16166 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16167 inst
.instruction
|= (et
.size
== 32) << 18;
16168 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16169 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16170 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16175 do_mve_vpsel (void)
16177 neon_select_shape (NS_QQQ
, NS_NULL
);
16179 if (inst
.cond
> COND_ALWAYS
)
16180 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16182 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16184 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16185 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16187 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16188 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16189 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16194 do_mve_vpnot (void)
16196 if (inst
.cond
> COND_ALWAYS
)
16197 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16199 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16203 do_mve_vmaxnma_vminnma (void)
16205 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16206 struct neon_type_el et
16207 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16209 if (inst
.cond
> COND_ALWAYS
)
16210 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16212 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16214 inst
.instruction
|= (et
.size
== 16) << 28;
16215 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16216 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16217 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16218 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16223 do_mve_vcmul (void)
16225 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16226 struct neon_type_el et
16227 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16229 if (inst
.cond
> COND_ALWAYS
)
16230 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16232 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16234 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16235 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16236 _("immediate out of range"));
16238 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16239 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16240 as_tsktsk (BAD_MVE_SRCDEST
);
16242 inst
.instruction
|= (et
.size
== 32) << 28;
16243 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16244 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16246 inst
.instruction
|= (rot
> 90) << 12;
16247 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16248 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16249 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16250 inst
.instruction
|= (rot
== 90 || rot
== 270);
16254 /* To handle the Low Overhead Loop instructions
16255 in Armv8.1-M Mainline and MVE. */
16259 unsigned long insn
= inst
.instruction
;
16261 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16263 if (insn
== T_MNEM_lctp
)
16266 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16268 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16270 struct neon_type_el et
16271 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16272 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16279 constraint (!inst
.operands
[0].present
,
16281 /* fall through. */
16284 if (!inst
.operands
[0].present
)
16285 inst
.instruction
|= 1 << 21;
16287 v8_1_loop_reloc (TRUE
);
16292 v8_1_loop_reloc (FALSE
);
16293 /* fall through. */
16296 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16298 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16299 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16300 else if (inst
.operands
[1].reg
== REG_PC
)
16301 as_tsktsk (MVE_BAD_PC
);
16302 if (inst
.operands
[1].reg
== REG_SP
)
16303 as_tsktsk (MVE_BAD_SP
);
16305 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16315 do_vfp_nsyn_cmp (void)
16317 enum neon_shape rs
;
16318 if (!inst
.operands
[0].isreg
)
16325 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16330 if (inst
.operands
[1].isreg
)
16332 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16333 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16335 if (rs
== NS_FF
|| rs
== NS_HH
)
16337 NEON_ENCODE (SINGLE
, inst
);
16338 do_vfp_sp_monadic ();
16342 NEON_ENCODE (DOUBLE
, inst
);
16343 do_vfp_dp_rd_rm ();
16348 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16349 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16351 switch (inst
.instruction
& 0x0fffffff)
16354 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16357 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16363 if (rs
== NS_FI
|| rs
== NS_HI
)
16365 NEON_ENCODE (SINGLE
, inst
);
16366 do_vfp_sp_compare_z ();
16370 NEON_ENCODE (DOUBLE
, inst
);
16374 do_vfp_cond_or_thumb ();
16376 /* ARMv8.2 fp16 instruction. */
16377 if (rs
== NS_HI
|| rs
== NS_HH
)
16378 do_scalar_fp16_v82_encode ();
16382 nsyn_insert_sp (void)
16384 inst
.operands
[1] = inst
.operands
[0];
16385 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16386 inst
.operands
[0].reg
= REG_SP
;
16387 inst
.operands
[0].isreg
= 1;
16388 inst
.operands
[0].writeback
= 1;
16389 inst
.operands
[0].present
= 1;
16393 do_vfp_nsyn_push (void)
16397 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16398 _("register list must contain at least 1 and at most 16 "
16401 if (inst
.operands
[1].issingle
)
16402 do_vfp_nsyn_opcode ("fstmdbs");
16404 do_vfp_nsyn_opcode ("fstmdbd");
16408 do_vfp_nsyn_pop (void)
16412 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16413 _("register list must contain at least 1 and at most 16 "
16416 if (inst
.operands
[1].issingle
)
16417 do_vfp_nsyn_opcode ("fldmias");
16419 do_vfp_nsyn_opcode ("fldmiad");
16422 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16423 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16426 neon_dp_fixup (struct arm_it
* insn
)
16428 unsigned int i
= insn
->instruction
;
16433 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16444 insn
->instruction
= i
;
16448 mve_encode_qqr (int size
, int U
, int fp
)
16450 if (inst
.operands
[2].reg
== REG_SP
)
16451 as_tsktsk (MVE_BAD_SP
);
16452 else if (inst
.operands
[2].reg
== REG_PC
)
16453 as_tsktsk (MVE_BAD_PC
);
16458 if (((unsigned)inst
.instruction
) == 0xd00)
16459 inst
.instruction
= 0xee300f40;
16461 else if (((unsigned)inst
.instruction
) == 0x200d00)
16462 inst
.instruction
= 0xee301f40;
16464 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16465 inst
.instruction
= 0xee310e60;
16467 /* Setting size which is 1 for F16 and 0 for F32. */
16468 inst
.instruction
|= (size
== 16) << 28;
16473 if (((unsigned)inst
.instruction
) == 0x800)
16474 inst
.instruction
= 0xee010f40;
16476 else if (((unsigned)inst
.instruction
) == 0x1000800)
16477 inst
.instruction
= 0xee011f40;
16479 else if (((unsigned)inst
.instruction
) == 0)
16480 inst
.instruction
= 0xee000f40;
16482 else if (((unsigned)inst
.instruction
) == 0x200)
16483 inst
.instruction
= 0xee001f40;
16485 else if (((unsigned)inst
.instruction
) == 0x900)
16486 inst
.instruction
= 0xee010e40;
16488 else if (((unsigned)inst
.instruction
) == 0x910)
16489 inst
.instruction
= 0xee011e60;
16491 else if (((unsigned)inst
.instruction
) == 0x10)
16492 inst
.instruction
= 0xee000f60;
16494 else if (((unsigned)inst
.instruction
) == 0x210)
16495 inst
.instruction
= 0xee001f60;
16497 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16498 inst
.instruction
= 0xee000e40;
16500 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16501 inst
.instruction
= 0xee010e60;
16503 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16504 inst
.instruction
= 0xfe010e60;
16507 inst
.instruction
|= U
<< 28;
16509 /* Setting bits for size. */
16510 inst
.instruction
|= neon_logbits (size
) << 20;
16512 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16513 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16514 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16515 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16516 inst
.instruction
|= inst
.operands
[2].reg
;
16521 mve_encode_rqq (unsigned bit28
, unsigned size
)
16523 inst
.instruction
|= bit28
<< 28;
16524 inst
.instruction
|= neon_logbits (size
) << 20;
16525 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16526 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16527 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16528 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16529 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16534 mve_encode_qqq (int ubit
, int size
)
16537 inst
.instruction
|= (ubit
!= 0) << 28;
16538 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16539 inst
.instruction
|= neon_logbits (size
) << 20;
16540 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16541 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16542 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16543 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16544 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16550 mve_encode_rq (unsigned bit28
, unsigned size
)
16552 inst
.instruction
|= bit28
<< 28;
16553 inst
.instruction
|= neon_logbits (size
) << 18;
16554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16560 mve_encode_rrqq (unsigned U
, unsigned size
)
16562 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16564 inst
.instruction
|= U
<< 28;
16565 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16566 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16567 inst
.instruction
|= (size
== 32) << 16;
16568 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16569 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16570 inst
.instruction
|= inst
.operands
[3].reg
;
16574 /* Encode insns with bit pattern:
16576 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16577 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16579 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16580 different meaning for some instruction. */
16583 neon_three_same (int isquad
, int ubit
, int size
)
16585 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16586 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16587 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16588 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16589 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16590 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16591 inst
.instruction
|= (isquad
!= 0) << 6;
16592 inst
.instruction
|= (ubit
!= 0) << 24;
16594 inst
.instruction
|= neon_logbits (size
) << 20;
16596 neon_dp_fixup (&inst
);
16599 /* Encode instructions of the form:
16601 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16602 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16604 Don't write size if SIZE == -1. */
16607 neon_two_same (int qbit
, int ubit
, int size
)
16609 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16610 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16611 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16612 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16613 inst
.instruction
|= (qbit
!= 0) << 6;
16614 inst
.instruction
|= (ubit
!= 0) << 24;
16617 inst
.instruction
|= neon_logbits (size
) << 18;
16619 neon_dp_fixup (&inst
);
16622 enum vfp_or_neon_is_neon_bits
16625 NEON_CHECK_ARCH
= 2,
16626 NEON_CHECK_ARCH8
= 4
16629 /* Call this function if an instruction which may have belonged to the VFP or
16630 Neon instruction sets, but turned out to be a Neon instruction (due to the
16631 operand types involved, etc.). We have to check and/or fix-up a couple of
16634 - Make sure the user hasn't attempted to make a Neon instruction
16636 - Alter the value in the condition code field if necessary.
16637 - Make sure that the arch supports Neon instructions.
16639 Which of these operations take place depends on bits from enum
16640 vfp_or_neon_is_neon_bits.
16642 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16643 current instruction's condition is COND_ALWAYS, the condition field is
16644 changed to inst.uncond_value. This is necessary because instructions shared
16645 between VFP and Neon may be conditional for the VFP variants only, and the
16646 unconditional Neon version must have, e.g., 0xF in the condition field. */
16649 vfp_or_neon_is_neon (unsigned check
)
16651 /* Conditions are always legal in Thumb mode (IT blocks). */
16652 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16654 if (inst
.cond
!= COND_ALWAYS
)
16656 first_error (_(BAD_COND
));
16659 if (inst
.uncond_value
!= -1)
16660 inst
.instruction
|= inst
.uncond_value
<< 28;
16664 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16665 || ((check
& NEON_CHECK_ARCH8
)
16666 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16668 first_error (_(BAD_FPU
));
16676 /* Return TRUE if the SIMD instruction is available for the current
16677 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16678 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16679 vfp_or_neon_is_neon for the NEON specific checks. */
16682 check_simd_pred_availability (int fp
, unsigned check
)
16684 if (inst
.cond
> COND_ALWAYS
)
16686 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16688 inst
.error
= BAD_FPU
;
16691 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16693 else if (inst
.cond
< COND_ALWAYS
)
16695 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16696 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16697 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16702 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16703 && vfp_or_neon_is_neon (check
) == FAIL
)
16706 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16707 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16712 /* Neon instruction encoders, in approximate order of appearance. */
16715 do_neon_dyadic_i_su (void)
16717 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16720 enum neon_shape rs
;
16721 struct neon_type_el et
;
16722 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16723 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16725 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16727 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16731 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16733 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16737 do_neon_dyadic_i64_su (void)
16739 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16741 enum neon_shape rs
;
16742 struct neon_type_el et
;
16743 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16745 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16746 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16750 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16751 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16754 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16756 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16760 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16763 unsigned size
= et
.size
>> 3;
16764 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16765 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16766 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16767 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16768 inst
.instruction
|= (isquad
!= 0) << 6;
16769 inst
.instruction
|= immbits
<< 16;
16770 inst
.instruction
|= (size
>> 3) << 7;
16771 inst
.instruction
|= (size
& 0x7) << 19;
16773 inst
.instruction
|= (uval
!= 0) << 24;
16775 neon_dp_fixup (&inst
);
16781 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16784 if (!inst
.operands
[2].isreg
)
16786 enum neon_shape rs
;
16787 struct neon_type_el et
;
16788 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16790 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16791 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16795 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16796 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16798 int imm
= inst
.operands
[2].imm
;
16800 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16801 _("immediate out of range for shift"));
16802 NEON_ENCODE (IMMED
, inst
);
16803 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16807 enum neon_shape rs
;
16808 struct neon_type_el et
;
16809 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16811 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16812 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16816 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16817 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16823 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16824 _("invalid instruction shape"));
16825 if (inst
.operands
[2].reg
== REG_SP
)
16826 as_tsktsk (MVE_BAD_SP
);
16827 else if (inst
.operands
[2].reg
== REG_PC
)
16828 as_tsktsk (MVE_BAD_PC
);
16830 inst
.instruction
= 0xee311e60;
16831 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16832 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16833 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16834 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16835 inst
.instruction
|= inst
.operands
[2].reg
;
16842 /* VSHL/VQSHL 3-register variants have syntax such as:
16844 whereas other 3-register operations encoded by neon_three_same have
16847 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16848 operands[2].reg here. */
16849 tmp
= inst
.operands
[2].reg
;
16850 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16851 inst
.operands
[1].reg
= tmp
;
16852 NEON_ENCODE (INTEGER
, inst
);
16853 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16859 do_neon_qshl (void)
16861 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16864 if (!inst
.operands
[2].isreg
)
16866 enum neon_shape rs
;
16867 struct neon_type_el et
;
16868 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16870 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16871 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16875 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16876 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16878 int imm
= inst
.operands
[2].imm
;
16880 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16881 _("immediate out of range for shift"));
16882 NEON_ENCODE (IMMED
, inst
);
16883 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16887 enum neon_shape rs
;
16888 struct neon_type_el et
;
16890 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16892 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16893 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16897 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16898 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16903 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16904 _("invalid instruction shape"));
16905 if (inst
.operands
[2].reg
== REG_SP
)
16906 as_tsktsk (MVE_BAD_SP
);
16907 else if (inst
.operands
[2].reg
== REG_PC
)
16908 as_tsktsk (MVE_BAD_PC
);
16910 inst
.instruction
= 0xee311ee0;
16911 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16912 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16913 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16914 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16915 inst
.instruction
|= inst
.operands
[2].reg
;
16922 /* See note in do_neon_shl. */
16923 tmp
= inst
.operands
[2].reg
;
16924 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16925 inst
.operands
[1].reg
= tmp
;
16926 NEON_ENCODE (INTEGER
, inst
);
16927 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16933 do_neon_rshl (void)
16935 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16938 enum neon_shape rs
;
16939 struct neon_type_el et
;
16940 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16942 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16943 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16947 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16948 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16955 if (inst
.operands
[2].reg
== REG_PC
)
16956 as_tsktsk (MVE_BAD_PC
);
16957 else if (inst
.operands
[2].reg
== REG_SP
)
16958 as_tsktsk (MVE_BAD_SP
);
16960 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16961 _("invalid instruction shape"));
16963 if (inst
.instruction
== 0x0000510)
16964 /* We are dealing with vqrshl. */
16965 inst
.instruction
= 0xee331ee0;
16967 /* We are dealing with vrshl. */
16968 inst
.instruction
= 0xee331e60;
16970 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16971 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16972 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16973 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16974 inst
.instruction
|= inst
.operands
[2].reg
;
16979 tmp
= inst
.operands
[2].reg
;
16980 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16981 inst
.operands
[1].reg
= tmp
;
16982 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16987 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16989 /* Handle .I8 pseudo-instructions. */
16992 /* Unfortunately, this will make everything apart from zero out-of-range.
16993 FIXME is this the intended semantics? There doesn't seem much point in
16994 accepting .I8 if so. */
16995 immediate
|= immediate
<< 8;
17001 if (immediate
== (immediate
& 0x000000ff))
17003 *immbits
= immediate
;
17006 else if (immediate
== (immediate
& 0x0000ff00))
17008 *immbits
= immediate
>> 8;
17011 else if (immediate
== (immediate
& 0x00ff0000))
17013 *immbits
= immediate
>> 16;
17016 else if (immediate
== (immediate
& 0xff000000))
17018 *immbits
= immediate
>> 24;
17021 if ((immediate
& 0xffff) != (immediate
>> 16))
17022 goto bad_immediate
;
17023 immediate
&= 0xffff;
17026 if (immediate
== (immediate
& 0x000000ff))
17028 *immbits
= immediate
;
17031 else if (immediate
== (immediate
& 0x0000ff00))
17033 *immbits
= immediate
>> 8;
17038 first_error (_("immediate value out of range"));
17043 do_neon_logic (void)
17045 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17047 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17049 && !check_simd_pred_availability (FALSE
,
17050 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17052 else if (rs
!= NS_QQQ
17053 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17054 first_error (BAD_FPU
);
17056 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17057 /* U bit and size field were set as part of the bitmask. */
17058 NEON_ENCODE (INTEGER
, inst
);
17059 neon_three_same (neon_quad (rs
), 0, -1);
17063 const int three_ops_form
= (inst
.operands
[2].present
17064 && !inst
.operands
[2].isreg
);
17065 const int immoperand
= (three_ops_form
? 2 : 1);
17066 enum neon_shape rs
= (three_ops_form
17067 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17068 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17069 /* Because neon_select_shape makes the second operand a copy of the first
17070 if the second operand is not present. */
17072 && !check_simd_pred_availability (FALSE
,
17073 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17075 else if (rs
!= NS_QQI
17076 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17077 first_error (BAD_FPU
);
17079 struct neon_type_el et
;
17080 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17081 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17083 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17086 if (et
.type
== NT_invtype
)
17088 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17093 if (three_ops_form
)
17094 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17095 _("first and second operands shall be the same register"));
17097 NEON_ENCODE (IMMED
, inst
);
17099 immbits
= inst
.operands
[immoperand
].imm
;
17102 /* .i64 is a pseudo-op, so the immediate must be a repeating
17104 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17105 inst
.operands
[immoperand
].reg
: 0))
17107 /* Set immbits to an invalid constant. */
17108 immbits
= 0xdeadbeef;
17115 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17119 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17123 /* Pseudo-instruction for VBIC. */
17124 neon_invert_size (&immbits
, 0, et
.size
);
17125 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17129 /* Pseudo-instruction for VORR. */
17130 neon_invert_size (&immbits
, 0, et
.size
);
17131 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17141 inst
.instruction
|= neon_quad (rs
) << 6;
17142 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17143 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17144 inst
.instruction
|= cmode
<< 8;
17145 neon_write_immbits (immbits
);
17147 neon_dp_fixup (&inst
);
17152 do_neon_bitfield (void)
17154 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17155 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17156 neon_three_same (neon_quad (rs
), 0, -1);
17160 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17163 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17164 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17166 if (et
.type
== NT_float
)
17168 NEON_ENCODE (FLOAT
, inst
);
17170 mve_encode_qqr (et
.size
, 0, 1);
17172 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17176 NEON_ENCODE (INTEGER
, inst
);
17178 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17180 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17186 do_neon_dyadic_if_su_d (void)
17188 /* This version only allow D registers, but that constraint is enforced during
17189 operand parsing so we don't need to do anything extra here. */
17190 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17194 do_neon_dyadic_if_i_d (void)
17196 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17197 affected if we specify unsigned args. */
17198 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17202 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17204 constraint (size
< 32, BAD_ADDR_MODE
);
17205 constraint (size
!= elsize
, BAD_EL_TYPE
);
17206 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17207 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17208 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17209 _("destination register and offset register may not be the"
17212 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17219 constraint ((imm
% (size
/ 8) != 0)
17220 || imm
> (0x7f << neon_logbits (size
)),
17221 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17222 " range of +/-[0,508]")
17223 : _("immediate must be a multiple of 8 in the"
17224 " range of +/-[0,1016]"));
17225 inst
.instruction
|= 0x11 << 24;
17226 inst
.instruction
|= add
<< 23;
17227 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17228 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17229 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17230 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17231 inst
.instruction
|= 1 << 12;
17232 inst
.instruction
|= (size
== 64) << 8;
17233 inst
.instruction
&= 0xffffff00;
17234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17235 inst
.instruction
|= imm
>> neon_logbits (size
);
17239 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17241 unsigned os
= inst
.operands
[1].imm
>> 5;
17242 constraint (os
!= 0 && size
== 8,
17243 _("can not shift offsets when accessing less than half-word"));
17244 constraint (os
&& os
!= neon_logbits (size
),
17245 _("shift immediate must be 1, 2 or 3 for half-word, word"
17246 " or double-word accesses respectively"));
17247 if (inst
.operands
[1].reg
== REG_PC
)
17248 as_tsktsk (MVE_BAD_PC
);
17253 constraint (elsize
>= 64, BAD_EL_TYPE
);
17256 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17260 constraint (elsize
!= size
, BAD_EL_TYPE
);
17265 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17269 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17270 _("destination register and offset register may not be"
17272 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17274 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17275 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17276 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17280 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17283 inst
.instruction
|= 1 << 23;
17284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17286 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17287 inst
.instruction
|= neon_logbits (elsize
) << 7;
17288 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17289 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17290 inst
.instruction
|= !!os
;
17294 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17296 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17298 constraint (size
>= 64, BAD_ADDR_MODE
);
17302 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17305 constraint (elsize
!= size
, BAD_EL_TYPE
);
17312 constraint (elsize
!= size
&& type
!= NT_unsigned
17313 && type
!= NT_signed
, BAD_EL_TYPE
);
17317 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17320 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17328 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17333 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17336 constraint (1, _("immediate must be a multiple of 2 in the"
17337 " range of +/-[0,254]"));
17340 constraint (1, _("immediate must be a multiple of 4 in the"
17341 " range of +/-[0,508]"));
17346 if (size
!= elsize
)
17348 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17349 constraint (inst
.operands
[0].reg
> 14,
17350 _("MVE vector register in the range [Q0..Q7] expected"));
17351 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17352 inst
.instruction
|= (size
== 16) << 19;
17353 inst
.instruction
|= neon_logbits (elsize
) << 7;
17357 if (inst
.operands
[1].reg
== REG_PC
)
17358 as_tsktsk (MVE_BAD_PC
);
17359 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17360 as_tsktsk (MVE_BAD_SP
);
17361 inst
.instruction
|= 1 << 12;
17362 inst
.instruction
|= neon_logbits (size
) << 7;
17364 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17365 inst
.instruction
|= add
<< 23;
17366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17367 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17368 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17369 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17370 inst
.instruction
&= 0xffffff80;
17371 inst
.instruction
|= imm
>> neon_logbits (size
);
17376 do_mve_vstr_vldr (void)
17381 if (inst
.cond
> COND_ALWAYS
)
17382 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17384 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17386 switch (inst
.instruction
)
17393 /* fall through. */
17399 /* fall through. */
17405 /* fall through. */
17411 /* fall through. */
17416 unsigned elsize
= inst
.vectype
.el
[0].size
;
17418 if (inst
.operands
[1].isquad
)
17420 /* We are dealing with [Q, imm]{!} cases. */
17421 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17425 if (inst
.operands
[1].immisreg
== 2)
17427 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17428 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17430 else if (!inst
.operands
[1].immisreg
)
17432 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17433 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17436 constraint (1, BAD_ADDR_MODE
);
17443 do_mve_vst_vld (void)
17445 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17448 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17449 || inst
.relocs
[0].exp
.X_add_number
!= 0
17450 || inst
.operands
[1].immisreg
!= 0,
17452 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17453 if (inst
.operands
[1].reg
== REG_PC
)
17454 as_tsktsk (MVE_BAD_PC
);
17455 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17456 as_tsktsk (MVE_BAD_SP
);
17459 /* These instructions are one of the "exceptions" mentioned in
17460 handle_pred_state. They are MVE instructions that are not VPT compatible
17461 and do not accept a VPT code, thus appending such a code is a syntax
17463 if (inst
.cond
> COND_ALWAYS
)
17464 first_error (BAD_SYNTAX
);
17465 /* If we append a scalar condition code we can set this to
17466 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17467 else if (inst
.cond
< COND_ALWAYS
)
17468 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17470 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17472 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17473 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17474 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17476 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17481 do_mve_vaddlv (void)
17483 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17484 struct neon_type_el et
17485 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17487 if (et
.type
== NT_invtype
)
17488 first_error (BAD_EL_TYPE
);
17490 if (inst
.cond
> COND_ALWAYS
)
17491 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17493 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17495 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17497 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17498 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17500 inst
.instruction
|= inst
.operands
[2].reg
;
17505 do_neon_dyadic_if_su (void)
17507 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17508 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17511 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17512 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17513 && et
.type
== NT_float
17514 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17516 if (!check_simd_pred_availability (et
.type
== NT_float
,
17517 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17520 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17524 do_neon_addsub_if_i (void)
17526 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17527 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17530 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17531 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17532 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17534 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17535 /* If we are parsing Q registers and the element types match MVE, which NEON
17536 also supports, then we must check whether this is an instruction that can
17537 be used by both MVE/NEON. This distinction can be made based on whether
17538 they are predicated or not. */
17539 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17541 if (!check_simd_pred_availability (et
.type
== NT_float
,
17542 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17547 /* If they are either in a D register or are using an unsupported. */
17549 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17553 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17554 affected if we specify unsigned args. */
17555 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17558 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17560 V<op> A,B (A is operand 0, B is operand 2)
17565 so handle that case specially. */
17568 neon_exchange_operands (void)
17570 if (inst
.operands
[1].present
)
17572 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17574 /* Swap operands[1] and operands[2]. */
17575 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17576 inst
.operands
[1] = inst
.operands
[2];
17577 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17582 inst
.operands
[1] = inst
.operands
[2];
17583 inst
.operands
[2] = inst
.operands
[0];
17588 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17590 if (inst
.operands
[2].isreg
)
17593 neon_exchange_operands ();
17594 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17598 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17599 struct neon_type_el et
= neon_check_type (2, rs
,
17600 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17602 NEON_ENCODE (IMMED
, inst
);
17603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17605 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17606 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17607 inst
.instruction
|= neon_quad (rs
) << 6;
17608 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17609 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17611 neon_dp_fixup (&inst
);
17618 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17622 do_neon_cmp_inv (void)
17624 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17630 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17633 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17634 scalars, which are encoded in 5 bits, M : Rm.
17635 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17636 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17639 Dot Product instructions are similar to multiply instructions except elsize
17640 should always be 32.
17642 This function translates SCALAR, which is GAS's internal encoding of indexed
17643 scalar register, to raw encoding. There is also register and index range
17644 check based on ELSIZE. */
17647 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17649 unsigned regno
= NEON_SCALAR_REG (scalar
);
17650 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17655 if (regno
> 7 || elno
> 3)
17657 return regno
| (elno
<< 3);
17660 if (regno
> 15 || elno
> 1)
17662 return regno
| (elno
<< 4);
17666 first_error (_("scalar out of range for multiply instruction"));
17672 /* Encode multiply / multiply-accumulate scalar instructions. */
17675 neon_mul_mac (struct neon_type_el et
, int ubit
)
17679 /* Give a more helpful error message if we have an invalid type. */
17680 if (et
.type
== NT_invtype
)
17683 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17684 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17685 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17686 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17688 inst
.instruction
|= LOW4 (scalar
);
17689 inst
.instruction
|= HI1 (scalar
) << 5;
17690 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17691 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17692 inst
.instruction
|= (ubit
!= 0) << 24;
17694 neon_dp_fixup (&inst
);
17698 do_neon_mac_maybe_scalar (void)
17700 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17703 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17706 if (inst
.operands
[2].isscalar
)
17708 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17709 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17710 struct neon_type_el et
= neon_check_type (3, rs
,
17711 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17712 NEON_ENCODE (SCALAR
, inst
);
17713 neon_mul_mac (et
, neon_quad (rs
));
17715 else if (!inst
.operands
[2].isvec
)
17717 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17719 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17720 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17722 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17726 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17727 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17728 affected if we specify unsigned args. */
17729 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17734 do_neon_fmac (void)
17736 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17737 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17740 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17743 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17745 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17746 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17751 if (inst
.operands
[2].reg
== REG_SP
)
17752 as_tsktsk (MVE_BAD_SP
);
17753 else if (inst
.operands
[2].reg
== REG_PC
)
17754 as_tsktsk (MVE_BAD_PC
);
17756 inst
.instruction
= 0xee310e40;
17757 inst
.instruction
|= (et
.size
== 16) << 28;
17758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17761 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17762 inst
.instruction
|= inst
.operands
[2].reg
;
17769 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17772 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17778 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17779 struct neon_type_el et
= neon_check_type (3, rs
,
17780 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17781 neon_three_same (neon_quad (rs
), 0, et
.size
);
17784 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17785 same types as the MAC equivalents. The polynomial type for this instruction
17786 is encoded the same as the integer type. */
17791 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17794 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17797 if (inst
.operands
[2].isscalar
)
17799 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17800 do_neon_mac_maybe_scalar ();
17804 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17806 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17807 struct neon_type_el et
17808 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17809 if (et
.type
== NT_float
)
17810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17813 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17817 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17818 neon_dyadic_misc (NT_poly
,
17819 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17825 do_neon_qdmulh (void)
17827 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17830 if (inst
.operands
[2].isscalar
)
17832 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17833 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17834 struct neon_type_el et
= neon_check_type (3, rs
,
17835 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17836 NEON_ENCODE (SCALAR
, inst
);
17837 neon_mul_mac (et
, neon_quad (rs
));
17841 enum neon_shape rs
;
17842 struct neon_type_el et
;
17843 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17845 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17846 et
= neon_check_type (3, rs
,
17847 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17851 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17852 et
= neon_check_type (3, rs
,
17853 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17856 NEON_ENCODE (INTEGER
, inst
);
17858 mve_encode_qqr (et
.size
, 0, 0);
17860 /* The U bit (rounding) comes from bit mask. */
17861 neon_three_same (neon_quad (rs
), 0, et
.size
);
17866 do_mve_vaddv (void)
17868 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17869 struct neon_type_el et
17870 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17872 if (et
.type
== NT_invtype
)
17873 first_error (BAD_EL_TYPE
);
17875 if (inst
.cond
> COND_ALWAYS
)
17876 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17878 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17880 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17882 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17886 do_mve_vhcadd (void)
17888 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17889 struct neon_type_el et
17890 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17892 if (inst
.cond
> COND_ALWAYS
)
17893 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17895 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17897 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17898 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17900 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17901 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17902 "operand makes instruction UNPREDICTABLE"));
17904 mve_encode_qqq (0, et
.size
);
17905 inst
.instruction
|= (rot
== 270) << 12;
17910 do_mve_vqdmull (void)
17912 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17913 struct neon_type_el et
17914 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17917 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17918 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17919 as_tsktsk (BAD_MVE_SRCDEST
);
17921 if (inst
.cond
> COND_ALWAYS
)
17922 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17924 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17928 mve_encode_qqq (et
.size
== 32, 64);
17929 inst
.instruction
|= 1;
17933 mve_encode_qqr (64, et
.size
== 32, 0);
17934 inst
.instruction
|= 0x3 << 5;
17941 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17942 struct neon_type_el et
17943 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17945 if (et
.type
== NT_invtype
)
17946 first_error (BAD_EL_TYPE
);
17948 if (inst
.cond
> COND_ALWAYS
)
17949 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17951 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17953 mve_encode_qqq (0, 64);
17957 do_mve_vbrsr (void)
17959 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17960 struct neon_type_el et
17961 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17963 if (inst
.cond
> COND_ALWAYS
)
17964 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17966 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17968 mve_encode_qqr (et
.size
, 0, 0);
17974 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17976 if (inst
.cond
> COND_ALWAYS
)
17977 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17979 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17981 mve_encode_qqq (1, 64);
17985 do_mve_vmulh (void)
17987 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17988 struct neon_type_el et
17989 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17991 if (inst
.cond
> COND_ALWAYS
)
17992 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17994 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17996 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18000 do_mve_vqdmlah (void)
18002 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18003 struct neon_type_el et
18004 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18006 if (inst
.cond
> COND_ALWAYS
)
18007 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18009 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18011 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18015 do_mve_vqdmladh (void)
18017 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18018 struct neon_type_el et
18019 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18021 if (inst
.cond
> COND_ALWAYS
)
18022 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18024 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18026 mve_encode_qqq (0, et
.size
);
18031 do_mve_vmull (void)
18034 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18035 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18036 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18037 && inst
.cond
== COND_ALWAYS
18038 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18043 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18044 N_SUF_32
| N_F64
| N_P8
18045 | N_P16
| N_I_MVE
| N_KEY
);
18046 if (((et
.type
== NT_poly
) && et
.size
== 8
18047 && ARM_CPU_IS_ANY (cpu_variant
))
18048 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18055 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18056 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18057 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18059 /* We are dealing with MVE's vmullt. */
18061 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18062 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18063 as_tsktsk (BAD_MVE_SRCDEST
);
18065 if (inst
.cond
> COND_ALWAYS
)
18066 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18068 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18070 if (et
.type
== NT_poly
)
18071 mve_encode_qqq (neon_logbits (et
.size
), 64);
18073 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18078 inst
.instruction
= N_MNEM_vmul
;
18081 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18086 do_mve_vabav (void)
18088 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18093 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18096 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18097 | N_S16
| N_S32
| N_U8
| N_U16
18100 if (inst
.cond
> COND_ALWAYS
)
18101 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18103 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18105 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18109 do_mve_vmladav (void)
18111 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18112 struct neon_type_el et
= neon_check_type (3, rs
,
18113 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18115 if (et
.type
== NT_unsigned
18116 && (inst
.instruction
== M_MNEM_vmladavx
18117 || inst
.instruction
== M_MNEM_vmladavax
18118 || inst
.instruction
== M_MNEM_vmlsdav
18119 || inst
.instruction
== M_MNEM_vmlsdava
18120 || inst
.instruction
== M_MNEM_vmlsdavx
18121 || inst
.instruction
== M_MNEM_vmlsdavax
))
18122 first_error (BAD_SIMD_TYPE
);
18124 constraint (inst
.operands
[2].reg
> 14,
18125 _("MVE vector register in the range [Q0..Q7] expected"));
18127 if (inst
.cond
> COND_ALWAYS
)
18128 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18130 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18132 if (inst
.instruction
== M_MNEM_vmlsdav
18133 || inst
.instruction
== M_MNEM_vmlsdava
18134 || inst
.instruction
== M_MNEM_vmlsdavx
18135 || inst
.instruction
== M_MNEM_vmlsdavax
)
18136 inst
.instruction
|= (et
.size
== 8) << 28;
18138 inst
.instruction
|= (et
.size
== 8) << 8;
18140 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18141 inst
.instruction
|= (et
.size
== 32) << 16;
18145 do_mve_vmlaldav (void)
18147 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18148 struct neon_type_el et
18149 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18150 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18152 if (et
.type
== NT_unsigned
18153 && (inst
.instruction
== M_MNEM_vmlsldav
18154 || inst
.instruction
== M_MNEM_vmlsldava
18155 || inst
.instruction
== M_MNEM_vmlsldavx
18156 || inst
.instruction
== M_MNEM_vmlsldavax
))
18157 first_error (BAD_SIMD_TYPE
);
18159 if (inst
.cond
> COND_ALWAYS
)
18160 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18162 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18164 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18168 do_mve_vrmlaldavh (void)
18170 struct neon_type_el et
;
18171 if (inst
.instruction
== M_MNEM_vrmlsldavh
18172 || inst
.instruction
== M_MNEM_vrmlsldavha
18173 || inst
.instruction
== M_MNEM_vrmlsldavhx
18174 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18176 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18177 if (inst
.operands
[1].reg
== REG_SP
)
18178 as_tsktsk (MVE_BAD_SP
);
18182 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18183 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18184 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18186 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18187 N_U32
| N_S32
| N_KEY
);
18188 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18189 with vmax/min instructions, making the use of SP in assembly really
18190 nonsensical, so instead of issuing a warning like we do for other uses
18191 of SP for the odd register operand we error out. */
18192 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18195 /* Make sure we still check the second operand is an odd one and that PC is
18196 disallowed. This because we are parsing for any GPR operand, to be able
18197 to distinguish between giving a warning or an error for SP as described
18199 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18200 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18202 if (inst
.cond
> COND_ALWAYS
)
18203 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18205 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18207 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18212 do_mve_vmaxnmv (void)
18214 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18215 struct neon_type_el et
18216 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18218 if (inst
.cond
> COND_ALWAYS
)
18219 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18221 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18223 if (inst
.operands
[0].reg
== REG_SP
)
18224 as_tsktsk (MVE_BAD_SP
);
18225 else if (inst
.operands
[0].reg
== REG_PC
)
18226 as_tsktsk (MVE_BAD_PC
);
18228 mve_encode_rq (et
.size
== 16, 64);
18232 do_mve_vmaxv (void)
18234 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18235 struct neon_type_el et
;
18237 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18238 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18240 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18242 if (inst
.cond
> COND_ALWAYS
)
18243 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18245 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18247 if (inst
.operands
[0].reg
== REG_SP
)
18248 as_tsktsk (MVE_BAD_SP
);
18249 else if (inst
.operands
[0].reg
== REG_PC
)
18250 as_tsktsk (MVE_BAD_PC
);
18252 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18257 do_neon_qrdmlah (void)
18259 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18261 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18263 /* Check we're on the correct architecture. */
18264 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18266 = _("instruction form not available on this architecture.");
18267 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18269 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18270 record_feature_use (&fpu_neon_ext_v8_1
);
18272 if (inst
.operands
[2].isscalar
)
18274 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18275 struct neon_type_el et
= neon_check_type (3, rs
,
18276 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18277 NEON_ENCODE (SCALAR
, inst
);
18278 neon_mul_mac (et
, neon_quad (rs
));
18282 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18283 struct neon_type_el et
= neon_check_type (3, rs
,
18284 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18285 NEON_ENCODE (INTEGER
, inst
);
18286 /* The U bit (rounding) comes from bit mask. */
18287 neon_three_same (neon_quad (rs
), 0, et
.size
);
18292 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18293 struct neon_type_el et
18294 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18296 NEON_ENCODE (INTEGER
, inst
);
18297 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18302 do_neon_fcmp_absolute (void)
18304 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18305 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18306 N_F_16_32
| N_KEY
);
18307 /* Size field comes from bit mask. */
18308 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18312 do_neon_fcmp_absolute_inv (void)
18314 neon_exchange_operands ();
18315 do_neon_fcmp_absolute ();
18319 do_neon_step (void)
18321 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18322 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18323 N_F_16_32
| N_KEY
);
18324 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18328 do_neon_abs_neg (void)
18330 enum neon_shape rs
;
18331 struct neon_type_el et
;
18333 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18336 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18337 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18339 if (!check_simd_pred_availability (et
.type
== NT_float
,
18340 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18343 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18344 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18345 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18346 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18347 inst
.instruction
|= neon_quad (rs
) << 6;
18348 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18349 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18351 neon_dp_fixup (&inst
);
18357 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18360 enum neon_shape rs
;
18361 struct neon_type_el et
;
18362 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18364 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18365 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18369 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18370 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18374 int imm
= inst
.operands
[2].imm
;
18375 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18376 _("immediate out of range for insert"));
18377 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18383 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18386 enum neon_shape rs
;
18387 struct neon_type_el et
;
18388 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18390 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18391 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18395 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18396 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18399 int imm
= inst
.operands
[2].imm
;
18400 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18401 _("immediate out of range for insert"));
18402 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18406 do_neon_qshlu_imm (void)
18408 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18411 enum neon_shape rs
;
18412 struct neon_type_el et
;
18413 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18415 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18416 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18420 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18421 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18422 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18425 int imm
= inst
.operands
[2].imm
;
18426 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18427 _("immediate out of range for shift"));
18428 /* Only encodes the 'U present' variant of the instruction.
18429 In this case, signed types have OP (bit 8) set to 0.
18430 Unsigned types have OP set to 1. */
18431 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18432 /* The rest of the bits are the same as other immediate shifts. */
18433 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18437 do_neon_qmovn (void)
18439 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18440 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18441 /* Saturating move where operands can be signed or unsigned, and the
18442 destination has the same signedness. */
18443 NEON_ENCODE (INTEGER
, inst
);
18444 if (et
.type
== NT_unsigned
)
18445 inst
.instruction
|= 0xc0;
18447 inst
.instruction
|= 0x80;
18448 neon_two_same (0, 1, et
.size
/ 2);
18452 do_neon_qmovun (void)
18454 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18455 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18456 /* Saturating move with unsigned results. Operands must be signed. */
18457 NEON_ENCODE (INTEGER
, inst
);
18458 neon_two_same (0, 1, et
.size
/ 2);
18462 do_neon_rshift_sat_narrow (void)
18464 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18465 or unsigned. If operands are unsigned, results must also be unsigned. */
18466 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18467 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18468 int imm
= inst
.operands
[2].imm
;
18469 /* This gets the bounds check, size encoding and immediate bits calculation
18473 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18474 VQMOVN.I<size> <Dd>, <Qm>. */
18477 inst
.operands
[2].present
= 0;
18478 inst
.instruction
= N_MNEM_vqmovn
;
18483 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18484 _("immediate out of range"));
18485 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18489 do_neon_rshift_sat_narrow_u (void)
18491 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18492 or unsigned. If operands are unsigned, results must also be unsigned. */
18493 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18494 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18495 int imm
= inst
.operands
[2].imm
;
18496 /* This gets the bounds check, size encoding and immediate bits calculation
18500 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18501 VQMOVUN.I<size> <Dd>, <Qm>. */
18504 inst
.operands
[2].present
= 0;
18505 inst
.instruction
= N_MNEM_vqmovun
;
18510 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18511 _("immediate out of range"));
18512 /* FIXME: The manual is kind of unclear about what value U should have in
18513 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18515 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18519 do_neon_movn (void)
18521 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18522 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18523 NEON_ENCODE (INTEGER
, inst
);
18524 neon_two_same (0, 1, et
.size
/ 2);
18528 do_neon_rshift_narrow (void)
18530 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18531 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18532 int imm
= inst
.operands
[2].imm
;
18533 /* This gets the bounds check, size encoding and immediate bits calculation
18537 /* If immediate is zero then we are a pseudo-instruction for
18538 VMOVN.I<size> <Dd>, <Qm> */
18541 inst
.operands
[2].present
= 0;
18542 inst
.instruction
= N_MNEM_vmovn
;
18547 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18548 _("immediate out of range for narrowing operation"));
18549 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18553 do_neon_shll (void)
18555 /* FIXME: Type checking when lengthening. */
18556 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18557 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18558 unsigned imm
= inst
.operands
[2].imm
;
18560 if (imm
== et
.size
)
18562 /* Maximum shift variant. */
18563 NEON_ENCODE (INTEGER
, inst
);
18564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18568 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18570 neon_dp_fixup (&inst
);
18574 /* A more-specific type check for non-max versions. */
18575 et
= neon_check_type (2, NS_QDI
,
18576 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18577 NEON_ENCODE (IMMED
, inst
);
18578 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18582 /* Check the various types for the VCVT instruction, and return which version
18583 the current instruction is. */
18585 #define CVT_FLAVOUR_VAR \
18586 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18587 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18588 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18589 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18590 /* Half-precision conversions. */ \
18591 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18592 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18593 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18594 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18595 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18596 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18597 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18598 Compared with single/double precision variants, only the co-processor \
18599 field is different, so the encoding flow is reused here. */ \
18600 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18601 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18602 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18603 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18604 /* VFP instructions. */ \
18605 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18606 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18607 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18608 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18609 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18610 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18611 /* VFP instructions with bitshift. */ \
18612 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18613 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18614 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18615 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18616 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18617 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18618 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18619 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18621 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18622 neon_cvt_flavour_##C,
18624 /* The different types of conversions we can do. */
18625 enum neon_cvt_flavour
18628 neon_cvt_flavour_invalid
,
18629 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18634 static enum neon_cvt_flavour
18635 get_neon_cvt_flavour (enum neon_shape rs
)
18637 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18638 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18639 if (et.type != NT_invtype) \
18641 inst.error = NULL; \
18642 return (neon_cvt_flavour_##C); \
18645 struct neon_type_el et
;
18646 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18647 || rs
== NS_FF
) ? N_VFP
: 0;
18648 /* The instruction versions which take an immediate take one register
18649 argument, which is extended to the width of the full register. Thus the
18650 "source" and "destination" registers must have the same width. Hack that
18651 here by making the size equal to the key (wider, in this case) operand. */
18652 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18656 return neon_cvt_flavour_invalid
;
18671 /* Neon-syntax VFP conversions. */
18674 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18676 const char *opname
= 0;
18678 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18679 || rs
== NS_FHI
|| rs
== NS_HFI
)
18681 /* Conversions with immediate bitshift. */
18682 const char *enc
[] =
18684 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18690 if (flavour
< (int) ARRAY_SIZE (enc
))
18692 opname
= enc
[flavour
];
18693 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18694 _("operands 0 and 1 must be the same register"));
18695 inst
.operands
[1] = inst
.operands
[2];
18696 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18701 /* Conversions without bitshift. */
18702 const char *enc
[] =
18704 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18710 if (flavour
< (int) ARRAY_SIZE (enc
))
18711 opname
= enc
[flavour
];
18715 do_vfp_nsyn_opcode (opname
);
18717 /* ARMv8.2 fp16 VCVT instruction. */
18718 if (flavour
== neon_cvt_flavour_s32_f16
18719 || flavour
== neon_cvt_flavour_u32_f16
18720 || flavour
== neon_cvt_flavour_f16_u32
18721 || flavour
== neon_cvt_flavour_f16_s32
)
18722 do_scalar_fp16_v82_encode ();
18726 do_vfp_nsyn_cvtz (void)
18728 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18729 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18730 const char *enc
[] =
18732 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18738 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18739 do_vfp_nsyn_opcode (enc
[flavour
]);
18743 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18744 enum neon_cvt_mode mode
)
18749 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18750 D register operands. */
18751 if (flavour
== neon_cvt_flavour_s32_f64
18752 || flavour
== neon_cvt_flavour_u32_f64
)
18753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18756 if (flavour
== neon_cvt_flavour_s32_f16
18757 || flavour
== neon_cvt_flavour_u32_f16
)
18758 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18761 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18765 case neon_cvt_flavour_s32_f64
:
18769 case neon_cvt_flavour_s32_f32
:
18773 case neon_cvt_flavour_s32_f16
:
18777 case neon_cvt_flavour_u32_f64
:
18781 case neon_cvt_flavour_u32_f32
:
18785 case neon_cvt_flavour_u32_f16
:
18790 first_error (_("invalid instruction shape"));
18796 case neon_cvt_mode_a
: rm
= 0; break;
18797 case neon_cvt_mode_n
: rm
= 1; break;
18798 case neon_cvt_mode_p
: rm
= 2; break;
18799 case neon_cvt_mode_m
: rm
= 3; break;
18800 default: first_error (_("invalid rounding mode")); return;
18803 NEON_ENCODE (FPV8
, inst
);
18804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18805 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18806 inst
.instruction
|= sz
<< 8;
18808 /* ARMv8.2 fp16 VCVT instruction. */
18809 if (flavour
== neon_cvt_flavour_s32_f16
18810 ||flavour
== neon_cvt_flavour_u32_f16
)
18811 do_scalar_fp16_v82_encode ();
18812 inst
.instruction
|= op
<< 7;
18813 inst
.instruction
|= rm
<< 16;
18814 inst
.instruction
|= 0xf0000000;
18815 inst
.is_neon
= TRUE
;
18819 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18821 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18822 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18823 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18825 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18827 if (flavour
== neon_cvt_flavour_invalid
)
18830 /* PR11109: Handle round-to-zero for VCVT conversions. */
18831 if (mode
== neon_cvt_mode_z
18832 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18833 && (flavour
== neon_cvt_flavour_s16_f16
18834 || flavour
== neon_cvt_flavour_u16_f16
18835 || flavour
== neon_cvt_flavour_s32_f32
18836 || flavour
== neon_cvt_flavour_u32_f32
18837 || flavour
== neon_cvt_flavour_s32_f64
18838 || flavour
== neon_cvt_flavour_u32_f64
)
18839 && (rs
== NS_FD
|| rs
== NS_FF
))
18841 do_vfp_nsyn_cvtz ();
18845 /* ARMv8.2 fp16 VCVT conversions. */
18846 if (mode
== neon_cvt_mode_z
18847 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18848 && (flavour
== neon_cvt_flavour_s32_f16
18849 || flavour
== neon_cvt_flavour_u32_f16
)
18852 do_vfp_nsyn_cvtz ();
18853 do_scalar_fp16_v82_encode ();
18857 /* VFP rather than Neon conversions. */
18858 if (flavour
>= neon_cvt_flavour_first_fp
)
18860 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18861 do_vfp_nsyn_cvt (rs
, flavour
);
18863 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18871 if (mode
== neon_cvt_mode_z
18872 && (flavour
== neon_cvt_flavour_f16_s16
18873 || flavour
== neon_cvt_flavour_f16_u16
18874 || flavour
== neon_cvt_flavour_s16_f16
18875 || flavour
== neon_cvt_flavour_u16_f16
18876 || flavour
== neon_cvt_flavour_f32_u32
18877 || flavour
== neon_cvt_flavour_f32_s32
18878 || flavour
== neon_cvt_flavour_s32_f32
18879 || flavour
== neon_cvt_flavour_u32_f32
))
18881 if (!check_simd_pred_availability (TRUE
,
18882 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18885 else if (mode
== neon_cvt_mode_n
)
18887 /* We are dealing with vcvt with the 'ne' condition. */
18889 inst
.instruction
= N_MNEM_vcvt
;
18890 do_neon_cvt_1 (neon_cvt_mode_z
);
18893 /* fall through. */
18897 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18898 0x0000100, 0x1000100, 0x0, 0x1000000};
18900 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18901 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18904 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18906 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18907 _("immediate value out of range"));
18910 case neon_cvt_flavour_f16_s16
:
18911 case neon_cvt_flavour_f16_u16
:
18912 case neon_cvt_flavour_s16_f16
:
18913 case neon_cvt_flavour_u16_f16
:
18914 constraint (inst
.operands
[2].imm
> 16,
18915 _("immediate value out of range"));
18917 case neon_cvt_flavour_f32_u32
:
18918 case neon_cvt_flavour_f32_s32
:
18919 case neon_cvt_flavour_s32_f32
:
18920 case neon_cvt_flavour_u32_f32
:
18921 constraint (inst
.operands
[2].imm
> 32,
18922 _("immediate value out of range"));
18925 inst
.error
= BAD_FPU
;
18930 /* Fixed-point conversion with #0 immediate is encoded as an
18931 integer conversion. */
18932 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18934 NEON_ENCODE (IMMED
, inst
);
18935 if (flavour
!= neon_cvt_flavour_invalid
)
18936 inst
.instruction
|= enctab
[flavour
];
18937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18941 inst
.instruction
|= neon_quad (rs
) << 6;
18942 inst
.instruction
|= 1 << 21;
18943 if (flavour
< neon_cvt_flavour_s16_f16
)
18945 inst
.instruction
|= 1 << 21;
18946 immbits
= 32 - inst
.operands
[2].imm
;
18947 inst
.instruction
|= immbits
<< 16;
18951 inst
.instruction
|= 3 << 20;
18952 immbits
= 16 - inst
.operands
[2].imm
;
18953 inst
.instruction
|= immbits
<< 16;
18954 inst
.instruction
&= ~(1 << 9);
18957 neon_dp_fixup (&inst
);
18962 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18963 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18964 && (flavour
== neon_cvt_flavour_s16_f16
18965 || flavour
== neon_cvt_flavour_u16_f16
18966 || flavour
== neon_cvt_flavour_s32_f32
18967 || flavour
== neon_cvt_flavour_u32_f32
))
18969 if (!check_simd_pred_availability (TRUE
,
18970 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18973 else if (mode
== neon_cvt_mode_z
18974 && (flavour
== neon_cvt_flavour_f16_s16
18975 || flavour
== neon_cvt_flavour_f16_u16
18976 || flavour
== neon_cvt_flavour_s16_f16
18977 || flavour
== neon_cvt_flavour_u16_f16
18978 || flavour
== neon_cvt_flavour_f32_u32
18979 || flavour
== neon_cvt_flavour_f32_s32
18980 || flavour
== neon_cvt_flavour_s32_f32
18981 || flavour
== neon_cvt_flavour_u32_f32
))
18983 if (!check_simd_pred_availability (TRUE
,
18984 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18987 /* fall through. */
18989 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18992 NEON_ENCODE (FLOAT
, inst
);
18993 if (!check_simd_pred_availability (TRUE
,
18994 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18997 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18998 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18999 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19000 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19001 inst
.instruction
|= neon_quad (rs
) << 6;
19002 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19003 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19004 inst
.instruction
|= mode
<< 8;
19005 if (flavour
== neon_cvt_flavour_u16_f16
19006 || flavour
== neon_cvt_flavour_s16_f16
)
19007 /* Mask off the original size bits and reencode them. */
19008 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19011 inst
.instruction
|= 0xfc000000;
19013 inst
.instruction
|= 0xf0000000;
19019 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19020 0x100, 0x180, 0x0, 0x080};
19022 NEON_ENCODE (INTEGER
, inst
);
19024 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19026 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19030 if (flavour
!= neon_cvt_flavour_invalid
)
19031 inst
.instruction
|= enctab
[flavour
];
19033 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19034 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19035 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19036 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19037 inst
.instruction
|= neon_quad (rs
) << 6;
19038 if (flavour
>= neon_cvt_flavour_s16_f16
19039 && flavour
<= neon_cvt_flavour_f16_u16
)
19040 /* Half precision. */
19041 inst
.instruction
|= 1 << 18;
19043 inst
.instruction
|= 2 << 18;
19045 neon_dp_fixup (&inst
);
19050 /* Half-precision conversions for Advanced SIMD -- neon. */
19053 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19057 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19059 as_bad (_("operand size must match register width"));
19064 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19066 as_bad (_("operand size must match register width"));
19071 inst
.instruction
= 0x3b60600;
19073 inst
.instruction
= 0x3b60700;
19075 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19076 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19078 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19079 neon_dp_fixup (&inst
);
19083 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19084 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19085 do_vfp_nsyn_cvt (rs
, flavour
);
19087 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19092 do_neon_cvtr (void)
19094 do_neon_cvt_1 (neon_cvt_mode_x
);
19100 do_neon_cvt_1 (neon_cvt_mode_z
);
19104 do_neon_cvta (void)
19106 do_neon_cvt_1 (neon_cvt_mode_a
);
19110 do_neon_cvtn (void)
19112 do_neon_cvt_1 (neon_cvt_mode_n
);
19116 do_neon_cvtp (void)
19118 do_neon_cvt_1 (neon_cvt_mode_p
);
19122 do_neon_cvtm (void)
19124 do_neon_cvt_1 (neon_cvt_mode_m
);
19128 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19131 mark_feature_used (&fpu_vfp_ext_armv8
);
19133 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19134 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19135 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19136 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19137 inst
.instruction
|= to
? 0x10000 : 0;
19138 inst
.instruction
|= t
? 0x80 : 0;
19139 inst
.instruction
|= is_double
? 0x100 : 0;
19140 do_vfp_cond_or_thumb ();
19144 do_neon_cvttb_1 (bfd_boolean t
)
19146 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19147 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19151 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19153 int single_to_half
= 0;
19154 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19157 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19160 && (flavour
== neon_cvt_flavour_u16_f16
19161 || flavour
== neon_cvt_flavour_s16_f16
19162 || flavour
== neon_cvt_flavour_f16_s16
19163 || flavour
== neon_cvt_flavour_f16_u16
19164 || flavour
== neon_cvt_flavour_u32_f32
19165 || flavour
== neon_cvt_flavour_s32_f32
19166 || flavour
== neon_cvt_flavour_f32_s32
19167 || flavour
== neon_cvt_flavour_f32_u32
))
19170 inst
.instruction
= N_MNEM_vcvt
;
19171 set_pred_insn_type (INSIDE_VPT_INSN
);
19172 do_neon_cvt_1 (neon_cvt_mode_z
);
19175 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19176 single_to_half
= 1;
19177 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19179 first_error (BAD_FPU
);
19183 inst
.instruction
= 0xee3f0e01;
19184 inst
.instruction
|= single_to_half
<< 28;
19185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19186 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19187 inst
.instruction
|= t
<< 12;
19188 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19189 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19192 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19195 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19197 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19200 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19202 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19204 /* The VCVTB and VCVTT instructions with D-register operands
19205 don't work for SP only targets. */
19206 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19210 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19212 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19214 /* The VCVTB and VCVTT instructions with D-register operands
19215 don't work for SP only targets. */
19216 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19220 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19227 do_neon_cvtb (void)
19229 do_neon_cvttb_1 (FALSE
);
19234 do_neon_cvtt (void)
19236 do_neon_cvttb_1 (TRUE
);
19240 neon_move_immediate (void)
19242 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19243 struct neon_type_el et
= neon_check_type (2, rs
,
19244 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19245 unsigned immlo
, immhi
= 0, immbits
;
19246 int op
, cmode
, float_p
;
19248 constraint (et
.type
== NT_invtype
,
19249 _("operand size must be specified for immediate VMOV"));
19251 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19252 op
= (inst
.instruction
& (1 << 5)) != 0;
19254 immlo
= inst
.operands
[1].imm
;
19255 if (inst
.operands
[1].regisimm
)
19256 immhi
= inst
.operands
[1].reg
;
19258 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19259 _("immediate has bits set outside the operand size"));
19261 float_p
= inst
.operands
[1].immisfloat
;
19263 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19264 et
.size
, et
.type
)) == FAIL
)
19266 /* Invert relevant bits only. */
19267 neon_invert_size (&immlo
, &immhi
, et
.size
);
19268 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19269 with one or the other; those cases are caught by
19270 neon_cmode_for_move_imm. */
19272 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19273 &op
, et
.size
, et
.type
)) == FAIL
)
19275 first_error (_("immediate out of range"));
19280 inst
.instruction
&= ~(1 << 5);
19281 inst
.instruction
|= op
<< 5;
19283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19285 inst
.instruction
|= neon_quad (rs
) << 6;
19286 inst
.instruction
|= cmode
<< 8;
19288 neon_write_immbits (immbits
);
19294 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19297 if (inst
.operands
[1].isreg
)
19299 enum neon_shape rs
;
19300 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19301 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19303 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19305 NEON_ENCODE (INTEGER
, inst
);
19306 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19307 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19308 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19309 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19310 inst
.instruction
|= neon_quad (rs
) << 6;
19314 NEON_ENCODE (IMMED
, inst
);
19315 neon_move_immediate ();
19318 neon_dp_fixup (&inst
);
19320 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19322 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19323 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19324 _("immediate value out of range"));
19328 /* Encode instructions of form:
19330 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19331 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19334 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19337 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19338 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19340 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19341 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19342 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19343 inst
.instruction
|= neon_logbits (size
) << 20;
19345 neon_dp_fixup (&inst
);
19349 do_neon_dyadic_long (void)
19351 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19354 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19357 NEON_ENCODE (INTEGER
, inst
);
19358 /* FIXME: Type checking for lengthening op. */
19359 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19360 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19361 neon_mixed_length (et
, et
.size
);
19363 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19364 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19366 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19367 in an IT block with le/lt conditions. */
19369 if (inst
.cond
== 0xf)
19371 else if (inst
.cond
== 0x10)
19374 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19376 if (inst
.instruction
== N_MNEM_vaddl
)
19378 inst
.instruction
= N_MNEM_vadd
;
19379 do_neon_addsub_if_i ();
19381 else if (inst
.instruction
== N_MNEM_vsubl
)
19383 inst
.instruction
= N_MNEM_vsub
;
19384 do_neon_addsub_if_i ();
19386 else if (inst
.instruction
== N_MNEM_vabdl
)
19388 inst
.instruction
= N_MNEM_vabd
;
19389 do_neon_dyadic_if_su ();
19393 first_error (BAD_FPU
);
19397 do_neon_abal (void)
19399 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19400 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19401 neon_mixed_length (et
, et
.size
);
19405 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19407 if (inst
.operands
[2].isscalar
)
19409 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19410 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19411 NEON_ENCODE (SCALAR
, inst
);
19412 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19416 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19417 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19418 NEON_ENCODE (INTEGER
, inst
);
19419 neon_mixed_length (et
, et
.size
);
19424 do_neon_mac_maybe_scalar_long (void)
19426 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19429 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19430 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19433 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19435 unsigned regno
= NEON_SCALAR_REG (scalar
);
19436 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19440 if (regno
> 7 || elno
> 3)
19443 return ((regno
& 0x7)
19444 | ((elno
& 0x1) << 3)
19445 | (((elno
>> 1) & 0x1) << 5));
19449 if (regno
> 15 || elno
> 1)
19452 return (((regno
& 0x1) << 5)
19453 | ((regno
>> 1) & 0x7)
19454 | ((elno
& 0x1) << 3));
19458 first_error (_("scalar out of range for multiply instruction"));
19463 do_neon_fmac_maybe_scalar_long (int subtype
)
19465 enum neon_shape rs
;
19467 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19468 field (bits[21:20]) has different meaning. For scalar index variant, it's
19469 used to differentiate add and subtract, otherwise it's with fixed value
19473 if (inst
.cond
!= COND_ALWAYS
)
19474 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19475 "behaviour is UNPREDICTABLE"));
19477 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19480 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19483 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19484 be a scalar index register. */
19485 if (inst
.operands
[2].isscalar
)
19487 high8
= 0xfe000000;
19490 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19494 high8
= 0xfc000000;
19497 inst
.instruction
|= (0x1 << 23);
19498 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19501 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19503 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19504 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19505 so we simply pass -1 as size. */
19506 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19507 neon_three_same (quad_p
, 0, size
);
19509 /* Undo neon_dp_fixup. Redo the high eight bits. */
19510 inst
.instruction
&= 0x00ffffff;
19511 inst
.instruction
|= high8
;
19513 #define LOW1(R) ((R) & 0x1)
19514 #define HI4(R) (((R) >> 1) & 0xf)
19515 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19516 whether the instruction is in Q form and whether Vm is a scalar indexed
19518 if (inst
.operands
[2].isscalar
)
19521 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19522 inst
.instruction
&= 0xffffffd0;
19523 inst
.instruction
|= rm
;
19527 /* Redo Rn as well. */
19528 inst
.instruction
&= 0xfff0ff7f;
19529 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19530 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19535 /* Redo Rn and Rm. */
19536 inst
.instruction
&= 0xfff0ff50;
19537 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19538 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19539 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19540 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19545 do_neon_vfmal (void)
19547 return do_neon_fmac_maybe_scalar_long (0);
19551 do_neon_vfmsl (void)
19553 return do_neon_fmac_maybe_scalar_long (1);
19557 do_neon_dyadic_wide (void)
19559 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19560 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19561 neon_mixed_length (et
, et
.size
);
19565 do_neon_dyadic_narrow (void)
19567 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19568 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19569 /* Operand sign is unimportant, and the U bit is part of the opcode,
19570 so force the operand type to integer. */
19571 et
.type
= NT_integer
;
19572 neon_mixed_length (et
, et
.size
/ 2);
19576 do_neon_mul_sat_scalar_long (void)
19578 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19582 do_neon_vmull (void)
19584 if (inst
.operands
[2].isscalar
)
19585 do_neon_mac_maybe_scalar_long ();
19588 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19589 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19591 if (et
.type
== NT_poly
)
19592 NEON_ENCODE (POLY
, inst
);
19594 NEON_ENCODE (INTEGER
, inst
);
19596 /* For polynomial encoding the U bit must be zero, and the size must
19597 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19598 obviously, as 0b10). */
19601 /* Check we're on the correct architecture. */
19602 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19604 _("Instruction form not available on this architecture.");
19609 neon_mixed_length (et
, et
.size
);
19616 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19617 struct neon_type_el et
= neon_check_type (3, rs
,
19618 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19619 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19621 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19622 _("shift out of range"));
19623 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19624 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19625 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19626 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19627 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19628 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19629 inst
.instruction
|= neon_quad (rs
) << 6;
19630 inst
.instruction
|= imm
<< 8;
19632 neon_dp_fixup (&inst
);
19638 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19641 enum neon_shape rs
;
19642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19643 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19645 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19647 struct neon_type_el et
= neon_check_type (2, rs
,
19648 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19650 unsigned op
= (inst
.instruction
>> 7) & 3;
19651 /* N (width of reversed regions) is encoded as part of the bitmask. We
19652 extract it here to check the elements to be reversed are smaller.
19653 Otherwise we'd get a reserved instruction. */
19654 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19656 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19657 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19658 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19659 " operands makes instruction UNPREDICTABLE"));
19661 gas_assert (elsize
!= 0);
19662 constraint (et
.size
>= elsize
,
19663 _("elements must be smaller than reversal region"));
19664 neon_two_same (neon_quad (rs
), 1, et
.size
);
19670 if (inst
.operands
[1].isscalar
)
19672 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19674 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19675 struct neon_type_el et
= neon_check_type (2, rs
,
19676 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19677 unsigned sizebits
= et
.size
>> 3;
19678 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19679 int logsize
= neon_logbits (et
.size
);
19680 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19682 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19685 NEON_ENCODE (SCALAR
, inst
);
19686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19688 inst
.instruction
|= LOW4 (dm
);
19689 inst
.instruction
|= HI1 (dm
) << 5;
19690 inst
.instruction
|= neon_quad (rs
) << 6;
19691 inst
.instruction
|= x
<< 17;
19692 inst
.instruction
|= sizebits
<< 16;
19694 neon_dp_fixup (&inst
);
19698 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19699 struct neon_type_el et
= neon_check_type (2, rs
,
19700 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19703 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19710 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19712 if (inst
.operands
[1].reg
== REG_SP
)
19713 as_tsktsk (MVE_BAD_SP
);
19714 else if (inst
.operands
[1].reg
== REG_PC
)
19715 as_tsktsk (MVE_BAD_PC
);
19718 /* Duplicate ARM register to lanes of vector. */
19719 NEON_ENCODE (ARMREG
, inst
);
19722 case 8: inst
.instruction
|= 0x400000; break;
19723 case 16: inst
.instruction
|= 0x000020; break;
19724 case 32: inst
.instruction
|= 0x000000; break;
19727 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19730 inst
.instruction
|= neon_quad (rs
) << 21;
19731 /* The encoding for this instruction is identical for the ARM and Thumb
19732 variants, except for the condition field. */
19733 do_vfp_cond_or_thumb ();
19738 do_mve_mov (int toQ
)
19740 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19742 if (inst
.cond
> COND_ALWAYS
)
19743 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19745 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19754 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19755 _("Index one must be [2,3] and index two must be two less than"
19757 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19758 _("General purpose registers may not be the same"));
19759 constraint (inst
.operands
[Rt
].reg
== REG_SP
19760 || inst
.operands
[Rt2
].reg
== REG_SP
,
19762 constraint (inst
.operands
[Rt
].reg
== REG_PC
19763 || inst
.operands
[Rt2
].reg
== REG_PC
,
19766 inst
.instruction
= 0xec000f00;
19767 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19768 inst
.instruction
|= !!toQ
<< 20;
19769 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19770 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19771 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19772 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19781 if (inst
.cond
> COND_ALWAYS
)
19782 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19784 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19786 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19789 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19790 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19791 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19792 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19793 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19798 /* VMOV has particularly many variations. It can be one of:
19799 0. VMOV<c><q> <Qd>, <Qm>
19800 1. VMOV<c><q> <Dd>, <Dm>
19801 (Register operations, which are VORR with Rm = Rn.)
19802 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19803 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19805 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19806 (ARM register to scalar.)
19807 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19808 (Two ARM registers to vector.)
19809 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19810 (Scalar to ARM register.)
19811 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19812 (Vector to two ARM registers.)
19813 8. VMOV.F32 <Sd>, <Sm>
19814 9. VMOV.F64 <Dd>, <Dm>
19815 (VFP register moves.)
19816 10. VMOV.F32 <Sd>, #imm
19817 11. VMOV.F64 <Dd>, #imm
19818 (VFP float immediate load.)
19819 12. VMOV <Rd>, <Sm>
19820 (VFP single to ARM reg.)
19821 13. VMOV <Sd>, <Rm>
19822 (ARM reg to VFP single.)
19823 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19824 (Two ARM regs to two VFP singles.)
19825 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19826 (Two VFP singles to two ARM regs.)
19827 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19828 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19829 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19830 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19832 These cases can be disambiguated using neon_select_shape, except cases 1/9
19833 and 3/11 which depend on the operand type too.
19835 All the encoded bits are hardcoded by this function.
19837 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19838 Cases 5, 7 may be used with VFPv2 and above.
19840 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19841 can specify a type where it doesn't make sense to, and is ignored). */
19846 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19847 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19848 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19849 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19851 struct neon_type_el et
;
19852 const char *ldconst
= 0;
19856 case NS_DD
: /* case 1/9. */
19857 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19858 /* It is not an error here if no type is given. */
19860 if (et
.type
== NT_float
&& et
.size
== 64)
19862 do_vfp_nsyn_opcode ("fcpyd");
19865 /* fall through. */
19867 case NS_QQ
: /* case 0/1. */
19869 if (!check_simd_pred_availability (FALSE
,
19870 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19872 /* The architecture manual I have doesn't explicitly state which
19873 value the U bit should have for register->register moves, but
19874 the equivalent VORR instruction has U = 0, so do that. */
19875 inst
.instruction
= 0x0200110;
19876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19878 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19879 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19880 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19881 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19882 inst
.instruction
|= neon_quad (rs
) << 6;
19884 neon_dp_fixup (&inst
);
19888 case NS_DI
: /* case 3/11. */
19889 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19891 if (et
.type
== NT_float
&& et
.size
== 64)
19893 /* case 11 (fconstd). */
19894 ldconst
= "fconstd";
19895 goto encode_fconstd
;
19897 /* fall through. */
19899 case NS_QI
: /* case 2/3. */
19900 if (!check_simd_pred_availability (FALSE
,
19901 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19903 inst
.instruction
= 0x0800010;
19904 neon_move_immediate ();
19905 neon_dp_fixup (&inst
);
19908 case NS_SR
: /* case 4. */
19910 unsigned bcdebits
= 0;
19912 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19913 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19915 /* .<size> is optional here, defaulting to .32. */
19916 if (inst
.vectype
.elems
== 0
19917 && inst
.operands
[0].vectype
.type
== NT_invtype
19918 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19920 inst
.vectype
.el
[0].type
= NT_untyped
;
19921 inst
.vectype
.el
[0].size
= 32;
19922 inst
.vectype
.elems
= 1;
19925 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19926 logsize
= neon_logbits (et
.size
);
19930 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19931 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19936 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19937 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19943 if (inst
.operands
[1].reg
== REG_SP
)
19944 as_tsktsk (MVE_BAD_SP
);
19945 else if (inst
.operands
[1].reg
== REG_PC
)
19946 as_tsktsk (MVE_BAD_PC
);
19948 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19950 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19951 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19956 case 8: bcdebits
= 0x8; break;
19957 case 16: bcdebits
= 0x1; break;
19958 case 32: bcdebits
= 0x0; break;
19962 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19964 inst
.instruction
= 0xe000b10;
19965 do_vfp_cond_or_thumb ();
19966 inst
.instruction
|= LOW4 (dn
) << 16;
19967 inst
.instruction
|= HI1 (dn
) << 7;
19968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19969 inst
.instruction
|= (bcdebits
& 3) << 5;
19970 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19971 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19975 case NS_DRR
: /* case 5 (fmdrr). */
19976 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19977 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19980 inst
.instruction
= 0xc400b10;
19981 do_vfp_cond_or_thumb ();
19982 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19983 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19984 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19985 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19988 case NS_RS
: /* case 6. */
19991 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19992 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19993 unsigned abcdebits
= 0;
19995 /* .<dt> is optional here, defaulting to .32. */
19996 if (inst
.vectype
.elems
== 0
19997 && inst
.operands
[0].vectype
.type
== NT_invtype
19998 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20000 inst
.vectype
.el
[0].type
= NT_untyped
;
20001 inst
.vectype
.el
[0].size
= 32;
20002 inst
.vectype
.elems
= 1;
20005 et
= neon_check_type (2, NS_NULL
,
20006 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20007 logsize
= neon_logbits (et
.size
);
20011 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20012 && vfp_or_neon_is_neon (NEON_CHECK_CC
20013 | NEON_CHECK_ARCH
) == FAIL
)
20018 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20019 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20023 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20025 if (inst
.operands
[0].reg
== REG_SP
)
20026 as_tsktsk (MVE_BAD_SP
);
20027 else if (inst
.operands
[0].reg
== REG_PC
)
20028 as_tsktsk (MVE_BAD_PC
);
20031 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20033 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20034 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20038 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20039 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20040 case 32: abcdebits
= 0x00; break;
20044 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20045 inst
.instruction
= 0xe100b10;
20046 do_vfp_cond_or_thumb ();
20047 inst
.instruction
|= LOW4 (dn
) << 16;
20048 inst
.instruction
|= HI1 (dn
) << 7;
20049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20050 inst
.instruction
|= (abcdebits
& 3) << 5;
20051 inst
.instruction
|= (abcdebits
>> 2) << 21;
20052 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20056 case NS_RRD
: /* case 7 (fmrrd). */
20057 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20058 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20061 inst
.instruction
= 0xc500b10;
20062 do_vfp_cond_or_thumb ();
20063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20064 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20065 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20066 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20069 case NS_FF
: /* case 8 (fcpys). */
20070 do_vfp_nsyn_opcode ("fcpys");
20074 case NS_FI
: /* case 10 (fconsts). */
20075 ldconst
= "fconsts";
20077 if (!inst
.operands
[1].immisfloat
)
20080 /* Immediate has to fit in 8 bits so float is enough. */
20081 float imm
= (float) inst
.operands
[1].imm
;
20082 memcpy (&new_imm
, &imm
, sizeof (float));
20083 /* But the assembly may have been written to provide an integer
20084 bit pattern that equates to a float, so check that the
20085 conversion has worked. */
20086 if (is_quarter_float (new_imm
))
20088 if (is_quarter_float (inst
.operands
[1].imm
))
20089 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20091 inst
.operands
[1].imm
= new_imm
;
20092 inst
.operands
[1].immisfloat
= 1;
20096 if (is_quarter_float (inst
.operands
[1].imm
))
20098 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20099 do_vfp_nsyn_opcode (ldconst
);
20101 /* ARMv8.2 fp16 vmov.f16 instruction. */
20103 do_scalar_fp16_v82_encode ();
20106 first_error (_("immediate out of range"));
20110 case NS_RF
: /* case 12 (fmrs). */
20111 do_vfp_nsyn_opcode ("fmrs");
20112 /* ARMv8.2 fp16 vmov.f16 instruction. */
20114 do_scalar_fp16_v82_encode ();
20118 case NS_FR
: /* case 13 (fmsr). */
20119 do_vfp_nsyn_opcode ("fmsr");
20120 /* ARMv8.2 fp16 vmov.f16 instruction. */
20122 do_scalar_fp16_v82_encode ();
20132 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20133 (one of which is a list), but we have parsed four. Do some fiddling to
20134 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20136 case NS_RRFF
: /* case 14 (fmrrs). */
20137 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20138 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20140 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20141 _("VFP registers must be adjacent"));
20142 inst
.operands
[2].imm
= 2;
20143 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20144 do_vfp_nsyn_opcode ("fmrrs");
20147 case NS_FFRR
: /* case 15 (fmsrr). */
20148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20149 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20151 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20152 _("VFP registers must be adjacent"));
20153 inst
.operands
[1] = inst
.operands
[2];
20154 inst
.operands
[2] = inst
.operands
[3];
20155 inst
.operands
[0].imm
= 2;
20156 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20157 do_vfp_nsyn_opcode ("fmsrr");
20161 /* neon_select_shape has determined that the instruction
20162 shape is wrong and has already set the error message. */
20173 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20174 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20175 && !inst
.operands
[2].present
))
20177 inst
.instruction
= 0;
20180 set_pred_insn_type (INSIDE_IT_INSN
);
20185 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20188 if (inst
.cond
!= COND_ALWAYS
)
20189 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20191 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20192 | N_S16
| N_U16
| N_KEY
);
20194 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20195 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20196 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20197 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20198 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20199 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20204 do_neon_rshift_round_imm (void)
20206 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20209 enum neon_shape rs
;
20210 struct neon_type_el et
;
20212 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20214 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20215 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20219 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20220 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20222 int imm
= inst
.operands
[2].imm
;
20224 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20227 inst
.operands
[2].present
= 0;
20232 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20233 _("immediate out of range for shift"));
20234 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20239 do_neon_movhf (void)
20241 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20242 constraint (rs
!= NS_HH
, _("invalid suffix"));
20244 if (inst
.cond
!= COND_ALWAYS
)
20248 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20249 " the behaviour is UNPREDICTABLE"));
20253 inst
.error
= BAD_COND
;
20258 do_vfp_sp_monadic ();
20261 inst
.instruction
|= 0xf0000000;
20265 do_neon_movl (void)
20267 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20268 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20269 unsigned sizebits
= et
.size
>> 3;
20270 inst
.instruction
|= sizebits
<< 19;
20271 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20277 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20278 struct neon_type_el et
= neon_check_type (2, rs
,
20279 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20280 NEON_ENCODE (INTEGER
, inst
);
20281 neon_two_same (neon_quad (rs
), 1, et
.size
);
20285 do_neon_zip_uzp (void)
20287 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20288 struct neon_type_el et
= neon_check_type (2, rs
,
20289 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20290 if (rs
== NS_DD
&& et
.size
== 32)
20292 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20293 inst
.instruction
= N_MNEM_vtrn
;
20297 neon_two_same (neon_quad (rs
), 1, et
.size
);
20301 do_neon_sat_abs_neg (void)
20303 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20306 enum neon_shape rs
;
20307 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20308 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20310 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20311 struct neon_type_el et
= neon_check_type (2, rs
,
20312 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20313 neon_two_same (neon_quad (rs
), 1, et
.size
);
20317 do_neon_pair_long (void)
20319 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20320 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20321 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20322 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20323 neon_two_same (neon_quad (rs
), 1, et
.size
);
20327 do_neon_recip_est (void)
20329 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20330 struct neon_type_el et
= neon_check_type (2, rs
,
20331 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20332 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20333 neon_two_same (neon_quad (rs
), 1, et
.size
);
20339 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20342 enum neon_shape rs
;
20343 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20344 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20346 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20348 struct neon_type_el et
= neon_check_type (2, rs
,
20349 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20350 neon_two_same (neon_quad (rs
), 1, et
.size
);
20356 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20359 enum neon_shape rs
;
20360 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20361 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20363 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20365 struct neon_type_el et
= neon_check_type (2, rs
,
20366 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20367 neon_two_same (neon_quad (rs
), 1, et
.size
);
20373 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20374 struct neon_type_el et
= neon_check_type (2, rs
,
20375 N_EQK
| N_INT
, N_8
| N_KEY
);
20376 neon_two_same (neon_quad (rs
), 1, et
.size
);
20382 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20383 neon_two_same (neon_quad (rs
), 1, -1);
20387 do_neon_tbl_tbx (void)
20389 unsigned listlenbits
;
20390 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20392 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20394 first_error (_("bad list length for table lookup"));
20398 listlenbits
= inst
.operands
[1].imm
- 1;
20399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20401 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20402 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20403 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20404 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20405 inst
.instruction
|= listlenbits
<< 8;
20407 neon_dp_fixup (&inst
);
20411 do_neon_ldm_stm (void)
20413 /* P, U and L bits are part of bitmask. */
20414 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20415 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20417 if (inst
.operands
[1].issingle
)
20419 do_vfp_nsyn_ldm_stm (is_dbmode
);
20423 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20424 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20426 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20427 _("register list must contain at least 1 and at most 16 "
20430 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20431 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20432 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20433 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20435 inst
.instruction
|= offsetbits
;
20437 do_vfp_cond_or_thumb ();
20441 do_neon_ldr_str (void)
20443 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20445 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20446 And is UNPREDICTABLE in thumb mode. */
20448 && inst
.operands
[1].reg
== REG_PC
20449 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20452 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20453 else if (warn_on_deprecated
)
20454 as_tsktsk (_("Use of PC here is deprecated"));
20457 if (inst
.operands
[0].issingle
)
20460 do_vfp_nsyn_opcode ("flds");
20462 do_vfp_nsyn_opcode ("fsts");
20464 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20465 if (inst
.vectype
.el
[0].size
== 16)
20466 do_scalar_fp16_v82_encode ();
20471 do_vfp_nsyn_opcode ("fldd");
20473 do_vfp_nsyn_opcode ("fstd");
20478 do_t_vldr_vstr_sysreg (void)
20480 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20481 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20483 /* Use of PC is UNPREDICTABLE. */
20484 if (inst
.operands
[1].reg
== REG_PC
)
20485 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20487 if (inst
.operands
[1].immisreg
)
20488 inst
.error
= _("instruction does not accept register index");
20490 if (!inst
.operands
[1].isreg
)
20491 inst
.error
= _("instruction does not accept PC-relative addressing");
20493 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20494 inst
.error
= _("immediate value out of range");
20496 inst
.instruction
= 0xec000f80;
20498 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20499 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20500 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20501 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20505 do_vldr_vstr (void)
20507 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20509 /* VLDR/VSTR (System Register). */
20512 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20513 as_bad (_("Instruction not permitted on this architecture"));
20515 do_t_vldr_vstr_sysreg ();
20520 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20521 as_bad (_("Instruction not permitted on this architecture"));
20522 do_neon_ldr_str ();
20526 /* "interleave" version also handles non-interleaving register VLD1/VST1
20530 do_neon_ld_st_interleave (void)
20532 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20533 N_8
| N_16
| N_32
| N_64
);
20534 unsigned alignbits
= 0;
20536 /* The bits in this table go:
20537 0: register stride of one (0) or two (1)
20538 1,2: register list length, minus one (1, 2, 3, 4).
20539 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20540 We use -1 for invalid entries. */
20541 const int typetable
[] =
20543 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20544 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20545 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20546 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20550 if (et
.type
== NT_invtype
)
20553 if (inst
.operands
[1].immisalign
)
20554 switch (inst
.operands
[1].imm
>> 8)
20556 case 64: alignbits
= 1; break;
20558 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20559 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20560 goto bad_alignment
;
20564 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20565 goto bad_alignment
;
20570 first_error (_("bad alignment"));
20574 inst
.instruction
|= alignbits
<< 4;
20575 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20577 /* Bits [4:6] of the immediate in a list specifier encode register stride
20578 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20579 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20580 up the right value for "type" in a table based on this value and the given
20581 list style, then stick it back. */
20582 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20583 | (((inst
.instruction
>> 8) & 3) << 3);
20585 typebits
= typetable
[idx
];
20587 constraint (typebits
== -1, _("bad list type for instruction"));
20588 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20591 inst
.instruction
&= ~0xf00;
20592 inst
.instruction
|= typebits
<< 8;
20595 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20596 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20597 otherwise. The variable arguments are a list of pairs of legal (size, align)
20598 values, terminated with -1. */
20601 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20604 int result
= FAIL
, thissize
, thisalign
;
20606 if (!inst
.operands
[1].immisalign
)
20612 va_start (ap
, do_alignment
);
20616 thissize
= va_arg (ap
, int);
20617 if (thissize
== -1)
20619 thisalign
= va_arg (ap
, int);
20621 if (size
== thissize
&& align
== thisalign
)
20624 while (result
!= SUCCESS
);
20628 if (result
== SUCCESS
)
20631 first_error (_("unsupported alignment for instruction"));
20637 do_neon_ld_st_lane (void)
20639 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20640 int align_good
, do_alignment
= 0;
20641 int logsize
= neon_logbits (et
.size
);
20642 int align
= inst
.operands
[1].imm
>> 8;
20643 int n
= (inst
.instruction
>> 8) & 3;
20644 int max_el
= 64 / et
.size
;
20646 if (et
.type
== NT_invtype
)
20649 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20650 _("bad list length"));
20651 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20652 _("scalar index out of range"));
20653 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20655 _("stride of 2 unavailable when element size is 8"));
20659 case 0: /* VLD1 / VST1. */
20660 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20662 if (align_good
== FAIL
)
20666 unsigned alignbits
= 0;
20669 case 16: alignbits
= 0x1; break;
20670 case 32: alignbits
= 0x3; break;
20673 inst
.instruction
|= alignbits
<< 4;
20677 case 1: /* VLD2 / VST2. */
20678 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20679 16, 32, 32, 64, -1);
20680 if (align_good
== FAIL
)
20683 inst
.instruction
|= 1 << 4;
20686 case 2: /* VLD3 / VST3. */
20687 constraint (inst
.operands
[1].immisalign
,
20688 _("can't use alignment with this instruction"));
20691 case 3: /* VLD4 / VST4. */
20692 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20693 16, 64, 32, 64, 32, 128, -1);
20694 if (align_good
== FAIL
)
20698 unsigned alignbits
= 0;
20701 case 8: alignbits
= 0x1; break;
20702 case 16: alignbits
= 0x1; break;
20703 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20706 inst
.instruction
|= alignbits
<< 4;
20713 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20714 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20715 inst
.instruction
|= 1 << (4 + logsize
);
20717 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20718 inst
.instruction
|= logsize
<< 10;
20721 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20724 do_neon_ld_dup (void)
20726 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20727 int align_good
, do_alignment
= 0;
20729 if (et
.type
== NT_invtype
)
20732 switch ((inst
.instruction
>> 8) & 3)
20734 case 0: /* VLD1. */
20735 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20736 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20737 &do_alignment
, 16, 16, 32, 32, -1);
20738 if (align_good
== FAIL
)
20740 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20743 case 2: inst
.instruction
|= 1 << 5; break;
20744 default: first_error (_("bad list length")); return;
20746 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20749 case 1: /* VLD2. */
20750 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20751 &do_alignment
, 8, 16, 16, 32, 32, 64,
20753 if (align_good
== FAIL
)
20755 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20756 _("bad list length"));
20757 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20758 inst
.instruction
|= 1 << 5;
20759 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20762 case 2: /* VLD3. */
20763 constraint (inst
.operands
[1].immisalign
,
20764 _("can't use alignment with this instruction"));
20765 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20766 _("bad list length"));
20767 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20768 inst
.instruction
|= 1 << 5;
20769 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20772 case 3: /* VLD4. */
20774 int align
= inst
.operands
[1].imm
>> 8;
20775 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20776 16, 64, 32, 64, 32, 128, -1);
20777 if (align_good
== FAIL
)
20779 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20780 _("bad list length"));
20781 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20782 inst
.instruction
|= 1 << 5;
20783 if (et
.size
== 32 && align
== 128)
20784 inst
.instruction
|= 0x3 << 6;
20786 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20793 inst
.instruction
|= do_alignment
<< 4;
20796 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20797 apart from bits [11:4]. */
20800 do_neon_ldx_stx (void)
20802 if (inst
.operands
[1].isreg
)
20803 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20805 switch (NEON_LANE (inst
.operands
[0].imm
))
20807 case NEON_INTERLEAVE_LANES
:
20808 NEON_ENCODE (INTERLV
, inst
);
20809 do_neon_ld_st_interleave ();
20812 case NEON_ALL_LANES
:
20813 NEON_ENCODE (DUP
, inst
);
20814 if (inst
.instruction
== N_INV
)
20816 first_error ("only loads support such operands");
20823 NEON_ENCODE (LANE
, inst
);
20824 do_neon_ld_st_lane ();
20827 /* L bit comes from bit mask. */
20828 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20829 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20830 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20832 if (inst
.operands
[1].postind
)
20834 int postreg
= inst
.operands
[1].imm
& 0xf;
20835 constraint (!inst
.operands
[1].immisreg
,
20836 _("post-index must be a register"));
20837 constraint (postreg
== 0xd || postreg
== 0xf,
20838 _("bad register for post-index"));
20839 inst
.instruction
|= postreg
;
20843 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20844 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20845 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20848 if (inst
.operands
[1].writeback
)
20850 inst
.instruction
|= 0xd;
20853 inst
.instruction
|= 0xf;
20857 inst
.instruction
|= 0xf9000000;
20859 inst
.instruction
|= 0xf4000000;
20864 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20866 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20867 D register operands. */
20868 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20869 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20872 NEON_ENCODE (FPV8
, inst
);
20874 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20876 do_vfp_sp_dyadic ();
20878 /* ARMv8.2 fp16 instruction. */
20880 do_scalar_fp16_v82_encode ();
20883 do_vfp_dp_rd_rn_rm ();
20886 inst
.instruction
|= 0x100;
20888 inst
.instruction
|= 0xf0000000;
20894 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20896 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20897 first_error (_("invalid instruction shape"));
20903 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20904 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20906 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20909 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20912 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20916 do_vrint_1 (enum neon_cvt_mode mode
)
20918 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20919 struct neon_type_el et
;
20924 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20925 D register operands. */
20926 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20927 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20930 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20932 if (et
.type
!= NT_invtype
)
20934 /* VFP encodings. */
20935 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20936 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20937 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20939 NEON_ENCODE (FPV8
, inst
);
20940 if (rs
== NS_FF
|| rs
== NS_HH
)
20941 do_vfp_sp_monadic ();
20943 do_vfp_dp_rd_rm ();
20947 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20948 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20949 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20950 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20951 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20952 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20953 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20957 inst
.instruction
|= (rs
== NS_DD
) << 8;
20958 do_vfp_cond_or_thumb ();
20960 /* ARMv8.2 fp16 vrint instruction. */
20962 do_scalar_fp16_v82_encode ();
20966 /* Neon encodings (or something broken...). */
20968 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20970 if (et
.type
== NT_invtype
)
20973 if (!check_simd_pred_availability (TRUE
,
20974 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20977 NEON_ENCODE (FLOAT
, inst
);
20979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20981 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20982 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20983 inst
.instruction
|= neon_quad (rs
) << 6;
20984 /* Mask off the original size bits and reencode them. */
20985 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20986 | neon_logbits (et
.size
) << 18);
20990 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20991 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20992 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20993 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20994 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20995 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20996 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21001 inst
.instruction
|= 0xfc000000;
21003 inst
.instruction
|= 0xf0000000;
21010 do_vrint_1 (neon_cvt_mode_x
);
21016 do_vrint_1 (neon_cvt_mode_z
);
21022 do_vrint_1 (neon_cvt_mode_r
);
21028 do_vrint_1 (neon_cvt_mode_a
);
21034 do_vrint_1 (neon_cvt_mode_n
);
21040 do_vrint_1 (neon_cvt_mode_p
);
21046 do_vrint_1 (neon_cvt_mode_m
);
21050 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21052 unsigned regno
= NEON_SCALAR_REG (opnd
);
21053 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21055 if (elsize
== 16 && elno
< 2 && regno
< 16)
21056 return regno
| (elno
<< 4);
21057 else if (elsize
== 32 && elno
== 0)
21060 first_error (_("scalar out of range"));
21067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21068 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21069 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21070 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21071 _("expression too complex"));
21072 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21073 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21074 _("immediate out of range"));
21077 if (!check_simd_pred_availability (TRUE
,
21078 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21081 if (inst
.operands
[2].isscalar
)
21083 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21084 first_error (_("invalid instruction shape"));
21085 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21086 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21087 N_KEY
| N_F16
| N_F32
).size
;
21088 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21090 inst
.instruction
= 0xfe000800;
21091 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21092 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21093 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21094 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21095 inst
.instruction
|= LOW4 (m
);
21096 inst
.instruction
|= HI1 (m
) << 5;
21097 inst
.instruction
|= neon_quad (rs
) << 6;
21098 inst
.instruction
|= rot
<< 20;
21099 inst
.instruction
|= (size
== 32) << 23;
21103 enum neon_shape rs
;
21104 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21105 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21107 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21109 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21110 N_KEY
| N_F16
| N_F32
).size
;
21111 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21112 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21113 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21114 as_tsktsk (BAD_MVE_SRCDEST
);
21116 neon_three_same (neon_quad (rs
), 0, -1);
21117 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21118 inst
.instruction
|= 0xfc200800;
21119 inst
.instruction
|= rot
<< 23;
21120 inst
.instruction
|= (size
== 32) << 20;
21127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21128 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21129 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21130 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21131 _("expression too complex"));
21133 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21134 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21135 enum neon_shape rs
;
21136 struct neon_type_el et
;
21137 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21139 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21140 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21144 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21145 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21147 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21148 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21149 "operand makes instruction UNPREDICTABLE"));
21152 if (et
.type
== NT_invtype
)
21155 if (!check_simd_pred_availability (et
.type
== NT_float
,
21156 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21159 if (et
.type
== NT_float
)
21161 neon_three_same (neon_quad (rs
), 0, -1);
21162 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21163 inst
.instruction
|= 0xfc800800;
21164 inst
.instruction
|= (rot
== 270) << 24;
21165 inst
.instruction
|= (et
.size
== 32) << 20;
21169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21170 inst
.instruction
= 0xfe000f00;
21171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21172 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21174 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21175 inst
.instruction
|= (rot
== 270) << 12;
21176 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21177 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21178 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21183 /* Dot Product instructions encoding support. */
21186 do_neon_dotproduct (int unsigned_p
)
21188 enum neon_shape rs
;
21189 unsigned scalar_oprd2
= 0;
21192 if (inst
.cond
!= COND_ALWAYS
)
21193 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21194 "is UNPREDICTABLE"));
21196 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21199 /* Dot Product instructions are in three-same D/Q register format or the third
21200 operand can be a scalar index register. */
21201 if (inst
.operands
[2].isscalar
)
21203 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21204 high8
= 0xfe000000;
21205 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21209 high8
= 0xfc000000;
21210 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21214 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21216 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21218 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21219 Product instruction, so we pass 0 as the "ubit" parameter. And the
21220 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21221 neon_three_same (neon_quad (rs
), 0, 32);
21223 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21224 different NEON three-same encoding. */
21225 inst
.instruction
&= 0x00ffffff;
21226 inst
.instruction
|= high8
;
21227 /* Encode 'U' bit which indicates signedness. */
21228 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21229 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21230 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21231 the instruction encoding. */
21232 if (inst
.operands
[2].isscalar
)
21234 inst
.instruction
&= 0xffffffd0;
21235 inst
.instruction
|= LOW4 (scalar_oprd2
);
21236 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21240 /* Dot Product instructions for signed integer. */
21243 do_neon_dotproduct_s (void)
21245 return do_neon_dotproduct (0);
21248 /* Dot Product instructions for unsigned integer. */
21251 do_neon_dotproduct_u (void)
21253 return do_neon_dotproduct (1);
21256 /* Crypto v1 instructions. */
21258 do_crypto_2op_1 (unsigned elttype
, int op
)
21260 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21262 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21268 NEON_ENCODE (INTEGER
, inst
);
21269 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21270 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21271 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21272 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21274 inst
.instruction
|= op
<< 6;
21277 inst
.instruction
|= 0xfc000000;
21279 inst
.instruction
|= 0xf0000000;
21283 do_crypto_3op_1 (int u
, int op
)
21285 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21287 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21288 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21293 NEON_ENCODE (INTEGER
, inst
);
21294 neon_three_same (1, u
, 8 << op
);
21300 do_crypto_2op_1 (N_8
, 0);
21306 do_crypto_2op_1 (N_8
, 1);
21312 do_crypto_2op_1 (N_8
, 2);
21318 do_crypto_2op_1 (N_8
, 3);
21324 do_crypto_3op_1 (0, 0);
21330 do_crypto_3op_1 (0, 1);
21336 do_crypto_3op_1 (0, 2);
21342 do_crypto_3op_1 (0, 3);
21348 do_crypto_3op_1 (1, 0);
21354 do_crypto_3op_1 (1, 1);
21358 do_sha256su1 (void)
21360 do_crypto_3op_1 (1, 2);
21366 do_crypto_2op_1 (N_32
, -1);
21372 do_crypto_2op_1 (N_32
, 0);
21376 do_sha256su0 (void)
21378 do_crypto_2op_1 (N_32
, 1);
21382 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21384 unsigned int Rd
= inst
.operands
[0].reg
;
21385 unsigned int Rn
= inst
.operands
[1].reg
;
21386 unsigned int Rm
= inst
.operands
[2].reg
;
21388 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21389 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21390 inst
.instruction
|= LOW4 (Rn
) << 16;
21391 inst
.instruction
|= LOW4 (Rm
);
21392 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21393 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21395 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21396 as_warn (UNPRED_REG ("r15"));
21438 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21440 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21441 do_vfp_sp_dp_cvt ();
21442 do_vfp_cond_or_thumb ();
21446 /* Overall per-instruction processing. */
21448 /* We need to be able to fix up arbitrary expressions in some statements.
21449 This is so that we can handle symbols that are an arbitrary distance from
21450 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21451 which returns part of an address in a form which will be valid for
21452 a data instruction. We do this by pushing the expression into a symbol
21453 in the expr_section, and creating a fix for that. */
21456 fix_new_arm (fragS
* frag
,
21470 /* Create an absolute valued symbol, so we have something to
21471 refer to in the object file. Unfortunately for us, gas's
21472 generic expression parsing will already have folded out
21473 any use of .set foo/.type foo %function that may have
21474 been used to set type information of the target location,
21475 that's being specified symbolically. We have to presume
21476 the user knows what they are doing. */
21480 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21482 symbol
= symbol_find_or_make (name
);
21483 S_SET_SEGMENT (symbol
, absolute_section
);
21484 symbol_set_frag (symbol
, &zero_address_frag
);
21485 S_SET_VALUE (symbol
, exp
->X_add_number
);
21486 exp
->X_op
= O_symbol
;
21487 exp
->X_add_symbol
= symbol
;
21488 exp
->X_add_number
= 0;
21494 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21495 (enum bfd_reloc_code_real
) reloc
);
21499 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21500 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21504 /* Mark whether the fix is to a THUMB instruction, or an ARM
21506 new_fix
->tc_fix_data
= thumb_mode
;
21509 /* Create a frg for an instruction requiring relaxation. */
21511 output_relax_insn (void)
21517 /* The size of the instruction is unknown, so tie the debug info to the
21518 start of the instruction. */
21519 dwarf2_emit_insn (0);
21521 switch (inst
.relocs
[0].exp
.X_op
)
21524 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21525 offset
= inst
.relocs
[0].exp
.X_add_number
;
21529 offset
= inst
.relocs
[0].exp
.X_add_number
;
21532 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21536 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21537 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21538 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21541 /* Write a 32-bit thumb instruction to buf. */
21543 put_thumb32_insn (char * buf
, unsigned long insn
)
21545 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21546 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21550 output_inst (const char * str
)
21556 as_bad ("%s -- `%s'", inst
.error
, str
);
21561 output_relax_insn ();
21564 if (inst
.size
== 0)
21567 to
= frag_more (inst
.size
);
21568 /* PR 9814: Record the thumb mode into the current frag so that we know
21569 what type of NOP padding to use, if necessary. We override any previous
21570 setting so that if the mode has changed then the NOPS that we use will
21571 match the encoding of the last instruction in the frag. */
21572 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21574 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21576 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21577 put_thumb32_insn (to
, inst
.instruction
);
21579 else if (inst
.size
> INSN_SIZE
)
21581 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21582 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21583 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21586 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21589 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21591 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21592 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21593 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21594 inst
.relocs
[r
].type
);
21597 dwarf2_emit_insn (inst
.size
);
21601 output_it_inst (int cond
, int mask
, char * to
)
21603 unsigned long instruction
= 0xbf00;
21606 instruction
|= mask
;
21607 instruction
|= cond
<< 4;
21611 to
= frag_more (2);
21613 dwarf2_emit_insn (2);
21617 md_number_to_chars (to
, instruction
, 2);
21622 /* Tag values used in struct asm_opcode's tag field. */
21625 OT_unconditional
, /* Instruction cannot be conditionalized.
21626 The ARM condition field is still 0xE. */
21627 OT_unconditionalF
, /* Instruction cannot be conditionalized
21628 and carries 0xF in its ARM condition field. */
21629 OT_csuffix
, /* Instruction takes a conditional suffix. */
21630 OT_csuffixF
, /* Some forms of the instruction take a scalar
21631 conditional suffix, others place 0xF where the
21632 condition field would be, others take a vector
21633 conditional suffix. */
21634 OT_cinfix3
, /* Instruction takes a conditional infix,
21635 beginning at character index 3. (In
21636 unified mode, it becomes a suffix.) */
21637 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21638 tsts, cmps, cmns, and teqs. */
21639 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21640 character index 3, even in unified mode. Used for
21641 legacy instructions where suffix and infix forms
21642 may be ambiguous. */
21643 OT_csuf_or_in3
, /* Instruction takes either a conditional
21644 suffix or an infix at character index 3. */
21645 OT_odd_infix_unc
, /* This is the unconditional variant of an
21646 instruction that takes a conditional infix
21647 at an unusual position. In unified mode,
21648 this variant will accept a suffix. */
21649 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21650 are the conditional variants of instructions that
21651 take conditional infixes in unusual positions.
21652 The infix appears at character index
21653 (tag - OT_odd_infix_0). These are not accepted
21654 in unified mode. */
21657 /* Subroutine of md_assemble, responsible for looking up the primary
21658 opcode from the mnemonic the user wrote. STR points to the
21659 beginning of the mnemonic.
21661 This is not simply a hash table lookup, because of conditional
21662 variants. Most instructions have conditional variants, which are
21663 expressed with a _conditional affix_ to the mnemonic. If we were
21664 to encode each conditional variant as a literal string in the opcode
21665 table, it would have approximately 20,000 entries.
21667 Most mnemonics take this affix as a suffix, and in unified syntax,
21668 'most' is upgraded to 'all'. However, in the divided syntax, some
21669 instructions take the affix as an infix, notably the s-variants of
21670 the arithmetic instructions. Of those instructions, all but six
21671 have the infix appear after the third character of the mnemonic.
21673 Accordingly, the algorithm for looking up primary opcodes given
21676 1. Look up the identifier in the opcode table.
21677 If we find a match, go to step U.
21679 2. Look up the last two characters of the identifier in the
21680 conditions table. If we find a match, look up the first N-2
21681 characters of the identifier in the opcode table. If we
21682 find a match, go to step CE.
21684 3. Look up the fourth and fifth characters of the identifier in
21685 the conditions table. If we find a match, extract those
21686 characters from the identifier, and look up the remaining
21687 characters in the opcode table. If we find a match, go
21692 U. Examine the tag field of the opcode structure, in case this is
21693 one of the six instructions with its conditional infix in an
21694 unusual place. If it is, the tag tells us where to find the
21695 infix; look it up in the conditions table and set inst.cond
21696 accordingly. Otherwise, this is an unconditional instruction.
21697 Again set inst.cond accordingly. Return the opcode structure.
21699 CE. Examine the tag field to make sure this is an instruction that
21700 should receive a conditional suffix. If it is not, fail.
21701 Otherwise, set inst.cond from the suffix we already looked up,
21702 and return the opcode structure.
21704 CM. Examine the tag field to make sure this is an instruction that
21705 should receive a conditional infix after the third character.
21706 If it is not, fail. Otherwise, undo the edits to the current
21707 line of input and proceed as for case CE. */
21709 static const struct asm_opcode
*
21710 opcode_lookup (char **str
)
21714 const struct asm_opcode
*opcode
;
21715 const struct asm_cond
*cond
;
21718 /* Scan up to the end of the mnemonic, which must end in white space,
21719 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21720 for (base
= end
= *str
; *end
!= '\0'; end
++)
21721 if (*end
== ' ' || *end
== '.')
21727 /* Handle a possible width suffix and/or Neon type suffix. */
21732 /* The .w and .n suffixes are only valid if the unified syntax is in
21734 if (unified_syntax
&& end
[1] == 'w')
21736 else if (unified_syntax
&& end
[1] == 'n')
21741 inst
.vectype
.elems
= 0;
21743 *str
= end
+ offset
;
21745 if (end
[offset
] == '.')
21747 /* See if we have a Neon type suffix (possible in either unified or
21748 non-unified ARM syntax mode). */
21749 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21752 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21758 /* Look for unaffixed or special-case affixed mnemonic. */
21759 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21764 if (opcode
->tag
< OT_odd_infix_0
)
21766 inst
.cond
= COND_ALWAYS
;
21770 if (warn_on_deprecated
&& unified_syntax
)
21771 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21772 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21773 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21776 inst
.cond
= cond
->value
;
21779 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21781 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21783 if (end
- base
< 2)
21786 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21787 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21789 /* If this opcode can not be vector predicated then don't accept it with a
21790 vector predication code. */
21791 if (opcode
&& !opcode
->mayBeVecPred
)
21794 if (!opcode
|| !cond
)
21796 /* Cannot have a conditional suffix on a mnemonic of less than two
21798 if (end
- base
< 3)
21801 /* Look for suffixed mnemonic. */
21803 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21804 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21808 if (opcode
&& cond
)
21811 switch (opcode
->tag
)
21813 case OT_cinfix3_legacy
:
21814 /* Ignore conditional suffixes matched on infix only mnemonics. */
21818 case OT_cinfix3_deprecated
:
21819 case OT_odd_infix_unc
:
21820 if (!unified_syntax
)
21822 /* Fall through. */
21826 case OT_csuf_or_in3
:
21827 inst
.cond
= cond
->value
;
21830 case OT_unconditional
:
21831 case OT_unconditionalF
:
21833 inst
.cond
= cond
->value
;
21836 /* Delayed diagnostic. */
21837 inst
.error
= BAD_COND
;
21838 inst
.cond
= COND_ALWAYS
;
21847 /* Cannot have a usual-position infix on a mnemonic of less than
21848 six characters (five would be a suffix). */
21849 if (end
- base
< 6)
21852 /* Look for infixed mnemonic in the usual position. */
21854 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21858 memcpy (save
, affix
, 2);
21859 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21860 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21862 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21863 memcpy (affix
, save
, 2);
21866 && (opcode
->tag
== OT_cinfix3
21867 || opcode
->tag
== OT_cinfix3_deprecated
21868 || opcode
->tag
== OT_csuf_or_in3
21869 || opcode
->tag
== OT_cinfix3_legacy
))
21872 if (warn_on_deprecated
&& unified_syntax
21873 && (opcode
->tag
== OT_cinfix3
21874 || opcode
->tag
== OT_cinfix3_deprecated
))
21875 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21877 inst
.cond
= cond
->value
;
21884 /* This function generates an initial IT instruction, leaving its block
21885 virtually open for the new instructions. Eventually,
21886 the mask will be updated by now_pred_add_mask () each time
21887 a new instruction needs to be included in the IT block.
21888 Finally, the block is closed with close_automatic_it_block ().
21889 The block closure can be requested either from md_assemble (),
21890 a tencode (), or due to a label hook. */
21893 new_automatic_it_block (int cond
)
21895 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21896 now_pred
.mask
= 0x18;
21897 now_pred
.cc
= cond
;
21898 now_pred
.block_length
= 1;
21899 mapping_state (MAP_THUMB
);
21900 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21901 now_pred
.warn_deprecated
= FALSE
;
21902 now_pred
.insn_cond
= TRUE
;
21905 /* Close an automatic IT block.
21906 See comments in new_automatic_it_block (). */
21909 close_automatic_it_block (void)
21911 now_pred
.mask
= 0x10;
21912 now_pred
.block_length
= 0;
21915 /* Update the mask of the current automatically-generated IT
21916 instruction. See comments in new_automatic_it_block (). */
21919 now_pred_add_mask (int cond
)
21921 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21922 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21923 | ((bitvalue) << (nbit)))
21924 const int resulting_bit
= (cond
& 1);
21926 now_pred
.mask
&= 0xf;
21927 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21929 (5 - now_pred
.block_length
));
21930 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21932 ((5 - now_pred
.block_length
) - 1));
21933 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21936 #undef SET_BIT_VALUE
21939 /* The IT blocks handling machinery is accessed through the these functions:
21940 it_fsm_pre_encode () from md_assemble ()
21941 set_pred_insn_type () optional, from the tencode functions
21942 set_pred_insn_type_last () ditto
21943 in_pred_block () ditto
21944 it_fsm_post_encode () from md_assemble ()
21945 force_automatic_it_block_close () from label handling functions
21948 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21949 initializing the IT insn type with a generic initial value depending
21950 on the inst.condition.
21951 2) During the tencode function, two things may happen:
21952 a) The tencode function overrides the IT insn type by
21953 calling either set_pred_insn_type (type) or
21954 set_pred_insn_type_last ().
21955 b) The tencode function queries the IT block state by
21956 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21958 Both set_pred_insn_type and in_pred_block run the internal FSM state
21959 handling function (handle_pred_state), because: a) setting the IT insn
21960 type may incur in an invalid state (exiting the function),
21961 and b) querying the state requires the FSM to be updated.
21962 Specifically we want to avoid creating an IT block for conditional
21963 branches, so it_fsm_pre_encode is actually a guess and we can't
21964 determine whether an IT block is required until the tencode () routine
21965 has decided what type of instruction this actually it.
21966 Because of this, if set_pred_insn_type and in_pred_block have to be
21967 used, set_pred_insn_type has to be called first.
21969 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21970 that determines the insn IT type depending on the inst.cond code.
21971 When a tencode () routine encodes an instruction that can be
21972 either outside an IT block, or, in the case of being inside, has to be
21973 the last one, set_pred_insn_type_last () will determine the proper
21974 IT instruction type based on the inst.cond code. Otherwise,
21975 set_pred_insn_type can be called for overriding that logic or
21976 for covering other cases.
21978 Calling handle_pred_state () may not transition the IT block state to
21979 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21980 still queried. Instead, if the FSM determines that the state should
21981 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21982 after the tencode () function: that's what it_fsm_post_encode () does.
21984 Since in_pred_block () calls the state handling function to get an
21985 updated state, an error may occur (due to invalid insns combination).
21986 In that case, inst.error is set.
21987 Therefore, inst.error has to be checked after the execution of
21988 the tencode () routine.
21990 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21991 any pending state change (if any) that didn't take place in
21992 handle_pred_state () as explained above. */
21995 it_fsm_pre_encode (void)
21997 if (inst
.cond
!= COND_ALWAYS
)
21998 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22000 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22002 now_pred
.state_handled
= 0;
22005 /* IT state FSM handling function. */
22006 /* MVE instructions and non-MVE instructions are handled differently because of
22007 the introduction of VPT blocks.
22008 Specifications say that any non-MVE instruction inside a VPT block is
22009 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22010 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22011 few exceptions we have MVE_UNPREDICABLE_INSN.
22012 The error messages provided depending on the different combinations possible
22013 are described in the cases below:
22014 For 'most' MVE instructions:
22015 1) In an IT block, with an IT code: syntax error
22016 2) In an IT block, with a VPT code: error: must be in a VPT block
22017 3) In an IT block, with no code: warning: UNPREDICTABLE
22018 4) In a VPT block, with an IT code: syntax error
22019 5) In a VPT block, with a VPT code: OK!
22020 6) In a VPT block, with no code: error: missing code
22021 7) Outside a pred block, with an IT code: error: syntax error
22022 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22023 9) Outside a pred block, with no code: OK!
22024 For non-MVE instructions:
22025 10) In an IT block, with an IT code: OK!
22026 11) In an IT block, with a VPT code: syntax error
22027 12) In an IT block, with no code: error: missing code
22028 13) In a VPT block, with an IT code: error: should be in an IT block
22029 14) In a VPT block, with a VPT code: syntax error
22030 15) In a VPT block, with no code: UNPREDICTABLE
22031 16) Outside a pred block, with an IT code: error: should be in an IT block
22032 17) Outside a pred block, with a VPT code: syntax error
22033 18) Outside a pred block, with no code: OK!
22038 handle_pred_state (void)
22040 now_pred
.state_handled
= 1;
22041 now_pred
.insn_cond
= FALSE
;
22043 switch (now_pred
.state
)
22045 case OUTSIDE_PRED_BLOCK
:
22046 switch (inst
.pred_insn_type
)
22048 case MVE_UNPREDICABLE_INSN
:
22049 case MVE_OUTSIDE_PRED_INSN
:
22050 if (inst
.cond
< COND_ALWAYS
)
22052 /* Case 7: Outside a pred block, with an IT code: error: syntax
22054 inst
.error
= BAD_SYNTAX
;
22057 /* Case 9: Outside a pred block, with no code: OK! */
22059 case OUTSIDE_PRED_INSN
:
22060 if (inst
.cond
> COND_ALWAYS
)
22062 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22064 inst
.error
= BAD_SYNTAX
;
22067 /* Case 18: Outside a pred block, with no code: OK! */
22070 case INSIDE_VPT_INSN
:
22071 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22073 inst
.error
= BAD_OUT_VPT
;
22076 case INSIDE_IT_INSN
:
22077 case INSIDE_IT_LAST_INSN
:
22078 if (inst
.cond
< COND_ALWAYS
)
22080 /* Case 16: Outside a pred block, with an IT code: error: should
22081 be in an IT block. */
22082 if (thumb_mode
== 0)
22085 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22086 as_tsktsk (_("Warning: conditional outside an IT block"\
22091 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22092 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22094 /* Automatically generate the IT instruction. */
22095 new_automatic_it_block (inst
.cond
);
22096 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22097 close_automatic_it_block ();
22101 inst
.error
= BAD_OUT_IT
;
22107 else if (inst
.cond
> COND_ALWAYS
)
22109 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22111 inst
.error
= BAD_SYNTAX
;
22116 case IF_INSIDE_IT_LAST_INSN
:
22117 case NEUTRAL_IT_INSN
:
22121 if (inst
.cond
!= COND_ALWAYS
)
22122 first_error (BAD_SYNTAX
);
22123 now_pred
.state
= MANUAL_PRED_BLOCK
;
22124 now_pred
.block_length
= 0;
22125 now_pred
.type
= VECTOR_PRED
;
22129 now_pred
.state
= MANUAL_PRED_BLOCK
;
22130 now_pred
.block_length
= 0;
22131 now_pred
.type
= SCALAR_PRED
;
22136 case AUTOMATIC_PRED_BLOCK
:
22137 /* Three things may happen now:
22138 a) We should increment current it block size;
22139 b) We should close current it block (closing insn or 4 insns);
22140 c) We should close current it block and start a new one (due
22141 to incompatible conditions or
22142 4 insns-length block reached). */
22144 switch (inst
.pred_insn_type
)
22146 case INSIDE_VPT_INSN
:
22148 case MVE_UNPREDICABLE_INSN
:
22149 case MVE_OUTSIDE_PRED_INSN
:
22151 case OUTSIDE_PRED_INSN
:
22152 /* The closure of the block shall happen immediately,
22153 so any in_pred_block () call reports the block as closed. */
22154 force_automatic_it_block_close ();
22157 case INSIDE_IT_INSN
:
22158 case INSIDE_IT_LAST_INSN
:
22159 case IF_INSIDE_IT_LAST_INSN
:
22160 now_pred
.block_length
++;
22162 if (now_pred
.block_length
> 4
22163 || !now_pred_compatible (inst
.cond
))
22165 force_automatic_it_block_close ();
22166 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22167 new_automatic_it_block (inst
.cond
);
22171 now_pred
.insn_cond
= TRUE
;
22172 now_pred_add_mask (inst
.cond
);
22175 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22176 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22177 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22178 close_automatic_it_block ();
22181 case NEUTRAL_IT_INSN
:
22182 now_pred
.block_length
++;
22183 now_pred
.insn_cond
= TRUE
;
22185 if (now_pred
.block_length
> 4)
22186 force_automatic_it_block_close ();
22188 now_pred_add_mask (now_pred
.cc
& 1);
22192 close_automatic_it_block ();
22193 now_pred
.state
= MANUAL_PRED_BLOCK
;
22198 case MANUAL_PRED_BLOCK
:
22201 if (now_pred
.type
== SCALAR_PRED
)
22203 /* Check conditional suffixes. */
22204 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22205 now_pred
.mask
<<= 1;
22206 now_pred
.mask
&= 0x1f;
22207 is_last
= (now_pred
.mask
== 0x10);
22211 now_pred
.cc
^= (now_pred
.mask
>> 4);
22212 cond
= now_pred
.cc
+ 0xf;
22213 now_pred
.mask
<<= 1;
22214 now_pred
.mask
&= 0x1f;
22215 is_last
= now_pred
.mask
== 0x10;
22217 now_pred
.insn_cond
= TRUE
;
22219 switch (inst
.pred_insn_type
)
22221 case OUTSIDE_PRED_INSN
:
22222 if (now_pred
.type
== SCALAR_PRED
)
22224 if (inst
.cond
== COND_ALWAYS
)
22226 /* Case 12: In an IT block, with no code: error: missing
22228 inst
.error
= BAD_NOT_IT
;
22231 else if (inst
.cond
> COND_ALWAYS
)
22233 /* Case 11: In an IT block, with a VPT code: syntax error.
22235 inst
.error
= BAD_SYNTAX
;
22238 else if (thumb_mode
)
22240 /* This is for some special cases where a non-MVE
22241 instruction is not allowed in an IT block, such as cbz,
22242 but are put into one with a condition code.
22243 You could argue this should be a syntax error, but we
22244 gave the 'not allowed in IT block' diagnostic in the
22245 past so we will keep doing so. */
22246 inst
.error
= BAD_NOT_IT
;
22253 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22254 as_tsktsk (MVE_NOT_VPT
);
22257 case MVE_OUTSIDE_PRED_INSN
:
22258 if (now_pred
.type
== SCALAR_PRED
)
22260 if (inst
.cond
== COND_ALWAYS
)
22262 /* Case 3: In an IT block, with no code: warning:
22264 as_tsktsk (MVE_NOT_IT
);
22267 else if (inst
.cond
< COND_ALWAYS
)
22269 /* Case 1: In an IT block, with an IT code: syntax error.
22271 inst
.error
= BAD_SYNTAX
;
22279 if (inst
.cond
< COND_ALWAYS
)
22281 /* Case 4: In a VPT block, with an IT code: syntax error.
22283 inst
.error
= BAD_SYNTAX
;
22286 else if (inst
.cond
== COND_ALWAYS
)
22288 /* Case 6: In a VPT block, with no code: error: missing
22290 inst
.error
= BAD_NOT_VPT
;
22298 case MVE_UNPREDICABLE_INSN
:
22299 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22301 case INSIDE_IT_INSN
:
22302 if (inst
.cond
> COND_ALWAYS
)
22304 /* Case 11: In an IT block, with a VPT code: syntax error. */
22305 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22306 inst
.error
= BAD_SYNTAX
;
22309 else if (now_pred
.type
== SCALAR_PRED
)
22311 /* Case 10: In an IT block, with an IT code: OK! */
22312 if (cond
!= inst
.cond
)
22314 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22321 /* Case 13: In a VPT block, with an IT code: error: should be
22323 inst
.error
= BAD_OUT_IT
;
22328 case INSIDE_VPT_INSN
:
22329 if (now_pred
.type
== SCALAR_PRED
)
22331 /* Case 2: In an IT block, with a VPT code: error: must be in a
22333 inst
.error
= BAD_OUT_VPT
;
22336 /* Case 5: In a VPT block, with a VPT code: OK! */
22337 else if (cond
!= inst
.cond
)
22339 inst
.error
= BAD_VPT_COND
;
22343 case INSIDE_IT_LAST_INSN
:
22344 case IF_INSIDE_IT_LAST_INSN
:
22345 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22347 /* Case 4: In a VPT block, with an IT code: syntax error. */
22348 /* Case 11: In an IT block, with a VPT code: syntax error. */
22349 inst
.error
= BAD_SYNTAX
;
22352 else if (cond
!= inst
.cond
)
22354 inst
.error
= BAD_IT_COND
;
22359 inst
.error
= BAD_BRANCH
;
22364 case NEUTRAL_IT_INSN
:
22365 /* The BKPT instruction is unconditional even in a IT or VPT
22370 if (now_pred
.type
== SCALAR_PRED
)
22372 inst
.error
= BAD_IT_IT
;
22375 /* fall through. */
22377 if (inst
.cond
== COND_ALWAYS
)
22379 /* Executing a VPT/VPST instruction inside an IT block or a
22380 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22382 if (now_pred
.type
== SCALAR_PRED
)
22383 as_tsktsk (MVE_NOT_IT
);
22385 as_tsktsk (MVE_NOT_VPT
);
22390 /* VPT/VPST do not accept condition codes. */
22391 inst
.error
= BAD_SYNTAX
;
22402 struct depr_insn_mask
22404 unsigned long pattern
;
22405 unsigned long mask
;
22406 const char* description
;
22409 /* List of 16-bit instruction patterns deprecated in an IT block in
22411 static const struct depr_insn_mask depr_it_insns
[] = {
22412 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22413 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22414 { 0xa000, 0xb800, N_("ADR") },
22415 { 0x4800, 0xf800, N_("Literal loads") },
22416 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22417 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22418 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22419 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22420 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22425 it_fsm_post_encode (void)
22429 if (!now_pred
.state_handled
)
22430 handle_pred_state ();
22432 if (now_pred
.insn_cond
22433 && !now_pred
.warn_deprecated
22434 && warn_on_deprecated
22435 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22436 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22438 if (inst
.instruction
>= 0x10000)
22440 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22441 "performance deprecated in ARMv8-A and ARMv8-R"));
22442 now_pred
.warn_deprecated
= TRUE
;
22446 const struct depr_insn_mask
*p
= depr_it_insns
;
22448 while (p
->mask
!= 0)
22450 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22452 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22453 "instructions of the following class are "
22454 "performance deprecated in ARMv8-A and "
22455 "ARMv8-R: %s"), p
->description
);
22456 now_pred
.warn_deprecated
= TRUE
;
22464 if (now_pred
.block_length
> 1)
22466 as_tsktsk (_("IT blocks containing more than one conditional "
22467 "instruction are performance deprecated in ARMv8-A and "
22469 now_pred
.warn_deprecated
= TRUE
;
22473 is_last
= (now_pred
.mask
== 0x10);
22476 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22482 force_automatic_it_block_close (void)
22484 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22486 close_automatic_it_block ();
22487 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22493 in_pred_block (void)
22495 if (!now_pred
.state_handled
)
22496 handle_pred_state ();
22498 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22501 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22502 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22503 here, hence the "known" in the function name. */
22506 known_t32_only_insn (const struct asm_opcode
*opcode
)
22508 /* Original Thumb-1 wide instruction. */
22509 if (opcode
->tencode
== do_t_blx
22510 || opcode
->tencode
== do_t_branch23
22511 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22512 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22515 /* Wide-only instruction added to ARMv8-M Baseline. */
22516 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22517 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22518 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22519 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22525 /* Whether wide instruction variant can be used if available for a valid OPCODE
22529 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22531 if (known_t32_only_insn (opcode
))
22534 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22535 of variant T3 of B.W is checked in do_t_branch. */
22536 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22537 && opcode
->tencode
== do_t_branch
)
22540 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22541 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22542 && opcode
->tencode
== do_t_mov_cmp
22543 /* Make sure CMP instruction is not affected. */
22544 && opcode
->aencode
== do_mov
)
22547 /* Wide instruction variants of all instructions with narrow *and* wide
22548 variants become available with ARMv6t2. Other opcodes are either
22549 narrow-only or wide-only and are thus available if OPCODE is valid. */
22550 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22553 /* OPCODE with narrow only instruction variant or wide variant not
22559 md_assemble (char *str
)
22562 const struct asm_opcode
* opcode
;
22564 /* Align the previous label if needed. */
22565 if (last_label_seen
!= NULL
)
22567 symbol_set_frag (last_label_seen
, frag_now
);
22568 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22569 S_SET_SEGMENT (last_label_seen
, now_seg
);
22572 memset (&inst
, '\0', sizeof (inst
));
22574 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22575 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22577 opcode
= opcode_lookup (&p
);
22580 /* It wasn't an instruction, but it might be a register alias of
22581 the form alias .req reg, or a Neon .dn/.qn directive. */
22582 if (! create_register_alias (str
, p
)
22583 && ! create_neon_reg_alias (str
, p
))
22584 as_bad (_("bad instruction `%s'"), str
);
22589 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22590 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22592 /* The value which unconditional instructions should have in place of the
22593 condition field. */
22594 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22598 arm_feature_set variant
;
22600 variant
= cpu_variant
;
22601 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22602 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22603 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22604 /* Check that this instruction is supported for this CPU. */
22605 if (!opcode
->tvariant
22606 || (thumb_mode
== 1
22607 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22609 if (opcode
->tencode
== do_t_swi
)
22610 as_bad (_("SVC is not permitted on this architecture"));
22612 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22615 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22616 && opcode
->tencode
!= do_t_branch
)
22618 as_bad (_("Thumb does not support conditional execution"));
22622 /* Two things are addressed here:
22623 1) Implicit require narrow instructions on Thumb-1.
22624 This avoids relaxation accidentally introducing Thumb-2
22626 2) Reject wide instructions in non Thumb-2 cores.
22628 Only instructions with narrow and wide variants need to be handled
22629 but selecting all non wide-only instructions is easier. */
22630 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22631 && !t32_insn_ok (variant
, opcode
))
22633 if (inst
.size_req
== 0)
22635 else if (inst
.size_req
== 4)
22637 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22638 as_bad (_("selected processor does not support 32bit wide "
22639 "variant of instruction `%s'"), str
);
22641 as_bad (_("selected processor does not support `%s' in "
22642 "Thumb-2 mode"), str
);
22647 inst
.instruction
= opcode
->tvalue
;
22649 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22651 /* Prepare the pred_insn_type for those encodings that don't set
22653 it_fsm_pre_encode ();
22655 opcode
->tencode ();
22657 it_fsm_post_encode ();
22660 if (!(inst
.error
|| inst
.relax
))
22662 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22663 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22664 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22666 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22671 /* Something has gone badly wrong if we try to relax a fixed size
22673 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22675 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22676 *opcode
->tvariant
);
22677 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22678 set those bits when Thumb-2 32-bit instructions are seen. The impact
22679 of relaxable instructions will be considered later after we finish all
22681 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22682 variant
= arm_arch_none
;
22684 variant
= cpu_variant
;
22685 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22686 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22689 check_neon_suffixes
;
22693 mapping_state (MAP_THUMB
);
22696 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22700 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22701 is_bx
= (opcode
->aencode
== do_bx
);
22703 /* Check that this instruction is supported for this CPU. */
22704 if (!(is_bx
&& fix_v4bx
)
22705 && !(opcode
->avariant
&&
22706 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22708 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22713 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22717 inst
.instruction
= opcode
->avalue
;
22718 if (opcode
->tag
== OT_unconditionalF
)
22719 inst
.instruction
|= 0xFU
<< 28;
22721 inst
.instruction
|= inst
.cond
<< 28;
22722 inst
.size
= INSN_SIZE
;
22723 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22725 it_fsm_pre_encode ();
22726 opcode
->aencode ();
22727 it_fsm_post_encode ();
22729 /* Arm mode bx is marked as both v4T and v5 because it's still required
22730 on a hypothetical non-thumb v5 core. */
22732 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22734 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22735 *opcode
->avariant
);
22737 check_neon_suffixes
;
22741 mapping_state (MAP_ARM
);
22746 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22754 check_pred_blocks_finished (void)
22759 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22760 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22761 == MANUAL_PRED_BLOCK
)
22763 if (now_pred
.type
== SCALAR_PRED
)
22764 as_warn (_("section '%s' finished with an open IT block."),
22767 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22771 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22773 if (now_pred
.type
== SCALAR_PRED
)
22774 as_warn (_("file finished with an open IT block."));
22776 as_warn (_("file finished with an open VPT/VPST block."));
22781 /* Various frobbings of labels and their addresses. */
22784 arm_start_line_hook (void)
22786 last_label_seen
= NULL
;
22790 arm_frob_label (symbolS
* sym
)
22792 last_label_seen
= sym
;
22794 ARM_SET_THUMB (sym
, thumb_mode
);
22796 #if defined OBJ_COFF || defined OBJ_ELF
22797 ARM_SET_INTERWORK (sym
, support_interwork
);
22800 force_automatic_it_block_close ();
22802 /* Note - do not allow local symbols (.Lxxx) to be labelled
22803 as Thumb functions. This is because these labels, whilst
22804 they exist inside Thumb code, are not the entry points for
22805 possible ARM->Thumb calls. Also, these labels can be used
22806 as part of a computed goto or switch statement. eg gcc
22807 can generate code that looks like this:
22809 ldr r2, [pc, .Laaa]
22819 The first instruction loads the address of the jump table.
22820 The second instruction converts a table index into a byte offset.
22821 The third instruction gets the jump address out of the table.
22822 The fourth instruction performs the jump.
22824 If the address stored at .Laaa is that of a symbol which has the
22825 Thumb_Func bit set, then the linker will arrange for this address
22826 to have the bottom bit set, which in turn would mean that the
22827 address computation performed by the third instruction would end
22828 up with the bottom bit set. Since the ARM is capable of unaligned
22829 word loads, the instruction would then load the incorrect address
22830 out of the jump table, and chaos would ensue. */
22831 if (label_is_thumb_function_name
22832 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22833 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22835 /* When the address of a Thumb function is taken the bottom
22836 bit of that address should be set. This will allow
22837 interworking between Arm and Thumb functions to work
22840 THUMB_SET_FUNC (sym
, 1);
22842 label_is_thumb_function_name
= FALSE
;
22845 dwarf2_emit_label (sym
);
22849 arm_data_in_code (void)
22851 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22853 *input_line_pointer
= '/';
22854 input_line_pointer
+= 5;
22855 *input_line_pointer
= 0;
22863 arm_canonicalize_symbol_name (char * name
)
22867 if (thumb_mode
&& (len
= strlen (name
)) > 5
22868 && streq (name
+ len
- 5, "/data"))
22869 *(name
+ len
- 5) = 0;
22874 /* Table of all register names defined by default. The user can
22875 define additional names with .req. Note that all register names
22876 should appear in both upper and lowercase variants. Some registers
22877 also have mixed-case names. */
22879 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22880 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22881 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22882 #define REGSET(p,t) \
22883 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22884 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22885 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22886 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22887 #define REGSETH(p,t) \
22888 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22889 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22890 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22891 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22892 #define REGSET2(p,t) \
22893 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22894 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22895 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22896 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22897 #define SPLRBANK(base,bank,t) \
22898 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22899 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22900 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22901 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22902 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22903 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22905 static const struct reg_entry reg_names
[] =
22907 /* ARM integer registers. */
22908 REGSET(r
, RN
), REGSET(R
, RN
),
22910 /* ATPCS synonyms. */
22911 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22912 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22913 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22915 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22916 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22917 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22919 /* Well-known aliases. */
22920 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22921 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22923 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22924 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22926 /* Defining the new Zero register from ARMv8.1-M. */
22930 /* Coprocessor numbers. */
22931 REGSET(p
, CP
), REGSET(P
, CP
),
22933 /* Coprocessor register numbers. The "cr" variants are for backward
22935 REGSET(c
, CN
), REGSET(C
, CN
),
22936 REGSET(cr
, CN
), REGSET(CR
, CN
),
22938 /* ARM banked registers. */
22939 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22940 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22941 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22942 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22943 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22944 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22945 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22947 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22948 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22949 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22950 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22951 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22952 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22953 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22954 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22956 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22957 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22958 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22959 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22960 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22961 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22962 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22963 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22964 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22966 /* FPA registers. */
22967 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22968 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22970 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22971 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22973 /* VFP SP registers. */
22974 REGSET(s
,VFS
), REGSET(S
,VFS
),
22975 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22977 /* VFP DP Registers. */
22978 REGSET(d
,VFD
), REGSET(D
,VFD
),
22979 /* Extra Neon DP registers. */
22980 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22982 /* Neon QP registers. */
22983 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22985 /* VFP control registers. */
22986 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22987 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22988 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22989 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22990 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22991 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22992 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22993 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
22994 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
22995 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
22996 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
22998 /* Maverick DSP coprocessor registers. */
22999 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23000 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23002 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23003 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23004 REGDEF(dspsc
,0,DSPSC
),
23006 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23007 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23008 REGDEF(DSPSC
,0,DSPSC
),
23010 /* iWMMXt data registers - p0, c0-15. */
23011 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23013 /* iWMMXt control registers - p1, c0-3. */
23014 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23015 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23016 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23017 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23019 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23020 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23021 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23022 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23023 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23025 /* XScale accumulator registers. */
23026 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23032 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23033 within psr_required_here. */
23034 static const struct asm_psr psrs
[] =
23036 /* Backward compatibility notation. Note that "all" is no longer
23037 truly all possible PSR bits. */
23038 {"all", PSR_c
| PSR_f
},
23042 /* Individual flags. */
23048 /* Combinations of flags. */
23049 {"fs", PSR_f
| PSR_s
},
23050 {"fx", PSR_f
| PSR_x
},
23051 {"fc", PSR_f
| PSR_c
},
23052 {"sf", PSR_s
| PSR_f
},
23053 {"sx", PSR_s
| PSR_x
},
23054 {"sc", PSR_s
| PSR_c
},
23055 {"xf", PSR_x
| PSR_f
},
23056 {"xs", PSR_x
| PSR_s
},
23057 {"xc", PSR_x
| PSR_c
},
23058 {"cf", PSR_c
| PSR_f
},
23059 {"cs", PSR_c
| PSR_s
},
23060 {"cx", PSR_c
| PSR_x
},
23061 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23062 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23063 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23064 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23065 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23066 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23067 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23068 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23069 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23070 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23071 {"scf", PSR_s
| PSR_c
| PSR_f
},
23072 {"scx", PSR_s
| PSR_c
| PSR_x
},
23073 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23074 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23075 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23076 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23077 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23078 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23079 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23080 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23081 {"csf", PSR_c
| PSR_s
| PSR_f
},
23082 {"csx", PSR_c
| PSR_s
| PSR_x
},
23083 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23084 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23085 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23086 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23087 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23088 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23089 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23090 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23091 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23092 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23093 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23094 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23095 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23096 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23097 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23098 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23099 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23100 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23101 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23102 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23103 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23104 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23105 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23106 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23107 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23108 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23111 /* Table of V7M psr names. */
23112 static const struct asm_psr v7m_psrs
[] =
23114 {"apsr", 0x0 }, {"APSR", 0x0 },
23115 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23116 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23117 {"psr", 0x3 }, {"PSR", 0x3 },
23118 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23119 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23120 {"epsr", 0x6 }, {"EPSR", 0x6 },
23121 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23122 {"msp", 0x8 }, {"MSP", 0x8 },
23123 {"psp", 0x9 }, {"PSP", 0x9 },
23124 {"msplim", 0xa }, {"MSPLIM", 0xa },
23125 {"psplim", 0xb }, {"PSPLIM", 0xb },
23126 {"primask", 0x10}, {"PRIMASK", 0x10},
23127 {"basepri", 0x11}, {"BASEPRI", 0x11},
23128 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23129 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23130 {"control", 0x14}, {"CONTROL", 0x14},
23131 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23132 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23133 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23134 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23135 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23136 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23137 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23138 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23139 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23142 /* Table of all shift-in-operand names. */
23143 static const struct asm_shift_name shift_names
[] =
23145 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23146 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23147 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23148 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23149 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23150 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23151 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23154 /* Table of all explicit relocation names. */
23156 static struct reloc_entry reloc_names
[] =
23158 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23159 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23160 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23161 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23162 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23163 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23164 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23165 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23166 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23167 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23168 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23169 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23170 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23171 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23172 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23173 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23174 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23175 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23176 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23177 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23178 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23179 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23180 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23181 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23182 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23183 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23184 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23188 /* Table of all conditional affixes. */
23189 static const struct asm_cond conds
[] =
23193 {"cs", 0x2}, {"hs", 0x2},
23194 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23207 static const struct asm_cond vconds
[] =
23213 #define UL_BARRIER(L,U,CODE,FEAT) \
23214 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23215 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23217 static struct asm_barrier_opt barrier_opt_names
[] =
23219 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23220 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23221 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23222 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23223 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23224 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23225 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23226 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23227 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23228 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23229 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23230 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23231 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23232 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23233 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23234 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23239 /* Table of ARM-format instructions. */
23241 /* Macros for gluing together operand strings. N.B. In all cases
23242 other than OPS0, the trailing OP_stop comes from default
23243 zero-initialization of the unspecified elements of the array. */
23244 #define OPS0() { OP_stop, }
23245 #define OPS1(a) { OP_##a, }
23246 #define OPS2(a,b) { OP_##a,OP_##b, }
23247 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23248 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23249 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23250 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23252 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23253 This is useful when mixing operands for ARM and THUMB, i.e. using the
23254 MIX_ARM_THUMB_OPERANDS macro.
23255 In order to use these macros, prefix the number of operands with _
23257 #define OPS_1(a) { a, }
23258 #define OPS_2(a,b) { a,b, }
23259 #define OPS_3(a,b,c) { a,b,c, }
23260 #define OPS_4(a,b,c,d) { a,b,c,d, }
23261 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23262 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23264 /* These macros abstract out the exact format of the mnemonic table and
23265 save some repeated characters. */
23267 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23268 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23269 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23270 THUMB_VARIANT, do_##ae, do_##te, 0 }
23272 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23273 a T_MNEM_xyz enumerator. */
23274 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23275 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23276 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23277 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23279 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23280 infix after the third character. */
23281 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23282 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23283 THUMB_VARIANT, do_##ae, do_##te, 0 }
23284 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23285 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23286 THUMB_VARIANT, do_##ae, do_##te, 0 }
23287 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23288 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23289 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23290 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23291 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23292 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23293 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23294 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23296 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23297 field is still 0xE. Many of the Thumb variants can be executed
23298 conditionally, so this is checked separately. */
23299 #define TUE(mnem, op, top, nops, ops, ae, te) \
23300 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23301 THUMB_VARIANT, do_##ae, do_##te, 0 }
23303 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23304 Used by mnemonics that have very minimal differences in the encoding for
23305 ARM and Thumb variants and can be handled in a common function. */
23306 #define TUEc(mnem, op, top, nops, ops, en) \
23307 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23308 THUMB_VARIANT, do_##en, do_##en, 0 }
23310 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23311 condition code field. */
23312 #define TUF(mnem, op, top, nops, ops, ae, te) \
23313 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23314 THUMB_VARIANT, do_##ae, do_##te, 0 }
23316 /* ARM-only variants of all the above. */
23317 #define CE(mnem, op, nops, ops, ae) \
23318 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23320 #define C3(mnem, op, nops, ops, ae) \
23321 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23323 /* Thumb-only variants of TCE and TUE. */
23324 #define ToC(mnem, top, nops, ops, te) \
23325 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23328 #define ToU(mnem, top, nops, ops, te) \
23329 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23332 /* T_MNEM_xyz enumerator variants of ToC. */
23333 #define toC(mnem, top, nops, ops, te) \
23334 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23337 /* T_MNEM_xyz enumerator variants of ToU. */
23338 #define toU(mnem, top, nops, ops, te) \
23339 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23342 /* Legacy mnemonics that always have conditional infix after the third
23344 #define CL(mnem, op, nops, ops, ae) \
23345 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23346 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23348 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23349 #define cCE(mnem, op, nops, ops, ae) \
23350 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23352 /* mov instructions that are shared between coprocessor and MVE. */
23353 #define mcCE(mnem, op, nops, ops, ae) \
23354 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23356 /* Legacy coprocessor instructions where conditional infix and conditional
23357 suffix are ambiguous. For consistency this includes all FPA instructions,
23358 not just the potentially ambiguous ones. */
23359 #define cCL(mnem, op, nops, ops, ae) \
23360 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23361 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23363 /* Coprocessor, takes either a suffix or a position-3 infix
23364 (for an FPA corner case). */
23365 #define C3E(mnem, op, nops, ops, ae) \
23366 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23367 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23369 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23370 { m1 #m2 m3, OPS##nops ops, \
23371 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23372 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23374 #define CM(m1, m2, op, nops, ops, ae) \
23375 xCM_ (m1, , m2, op, nops, ops, ae), \
23376 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23377 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23378 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23379 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23380 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23381 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23382 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23383 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23384 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23385 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23386 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23387 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23388 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23389 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23390 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23391 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23392 xCM_ (m1, le, m2, op, nops, ops, ae), \
23393 xCM_ (m1, al, m2, op, nops, ops, ae)
23395 #define UE(mnem, op, nops, ops, ae) \
23396 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23398 #define UF(mnem, op, nops, ops, ae) \
23399 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23401 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23402 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23403 use the same encoding function for each. */
23404 #define NUF(mnem, op, nops, ops, enc) \
23405 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23406 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23408 /* Neon data processing, version which indirects through neon_enc_tab for
23409 the various overloaded versions of opcodes. */
23410 #define nUF(mnem, op, nops, ops, enc) \
23411 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23412 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23414 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23416 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23417 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23418 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23420 #define NCE(mnem, op, nops, ops, enc) \
23421 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23423 #define NCEF(mnem, op, nops, ops, enc) \
23424 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23426 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23427 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23428 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23429 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23431 #define nCE(mnem, op, nops, ops, enc) \
23432 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23434 #define nCEF(mnem, op, nops, ops, enc) \
23435 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23438 #define mCEF(mnem, op, nops, ops, enc) \
23439 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23440 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23443 /* nCEF but for MVE predicated instructions. */
23444 #define mnCEF(mnem, op, nops, ops, enc) \
23445 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23447 /* nCE but for MVE predicated instructions. */
23448 #define mnCE(mnem, op, nops, ops, enc) \
23449 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23451 /* NUF but for potentially MVE predicated instructions. */
23452 #define MNUF(mnem, op, nops, ops, enc) \
23453 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23454 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23456 /* nUF but for potentially MVE predicated instructions. */
23457 #define mnUF(mnem, op, nops, ops, enc) \
23458 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23459 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23461 /* ToC but for potentially MVE predicated instructions. */
23462 #define mToC(mnem, top, nops, ops, te) \
23463 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23466 /* NCE but for MVE predicated instructions. */
23467 #define MNCE(mnem, op, nops, ops, enc) \
23468 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23470 /* NCEF but for MVE predicated instructions. */
23471 #define MNCEF(mnem, op, nops, ops, enc) \
23472 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23475 static const struct asm_opcode insns
[] =
23477 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23478 #define THUMB_VARIANT & arm_ext_v4t
23479 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23480 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23481 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23482 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23483 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23484 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23485 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23486 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23487 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23488 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23489 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23490 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23491 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23492 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23493 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23494 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23496 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23497 for setting PSR flag bits. They are obsolete in V6 and do not
23498 have Thumb equivalents. */
23499 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23500 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23501 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23502 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23503 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23504 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23505 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23506 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23507 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23509 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23510 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23511 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23512 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23514 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23515 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23516 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23518 OP_ADDRGLDR
),ldst
, t_ldst
),
23519 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23521 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23522 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23523 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23524 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23525 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23526 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23528 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23529 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23532 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23533 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23534 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23535 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23537 /* Thumb-compatibility pseudo ops. */
23538 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23539 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23540 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23541 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23542 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23543 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23544 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23545 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23546 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23547 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23548 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23549 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23551 /* These may simplify to neg. */
23552 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23553 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23555 #undef THUMB_VARIANT
23556 #define THUMB_VARIANT & arm_ext_os
23558 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23559 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23561 #undef THUMB_VARIANT
23562 #define THUMB_VARIANT & arm_ext_v6
23564 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23566 /* V1 instructions with no Thumb analogue prior to V6T2. */
23567 #undef THUMB_VARIANT
23568 #define THUMB_VARIANT & arm_ext_v6t2
23570 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23571 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23572 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23574 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23575 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23576 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23577 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23579 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23580 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23582 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23583 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23585 /* V1 instructions with no Thumb analogue at all. */
23586 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23587 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23589 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23590 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23591 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23592 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23593 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23594 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23595 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23596 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23599 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23600 #undef THUMB_VARIANT
23601 #define THUMB_VARIANT & arm_ext_v4t
23603 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23604 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23606 #undef THUMB_VARIANT
23607 #define THUMB_VARIANT & arm_ext_v6t2
23609 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23610 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23612 /* Generic coprocessor instructions. */
23613 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23614 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23615 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23616 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23617 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23618 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23619 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23622 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23624 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23625 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23628 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23629 #undef THUMB_VARIANT
23630 #define THUMB_VARIANT & arm_ext_msr
23632 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23633 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23636 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23637 #undef THUMB_VARIANT
23638 #define THUMB_VARIANT & arm_ext_v6t2
23640 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23641 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23642 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23643 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23644 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23645 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23646 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23647 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23650 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23651 #undef THUMB_VARIANT
23652 #define THUMB_VARIANT & arm_ext_v4t
23654 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23655 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23656 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23657 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23658 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23659 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23662 #define ARM_VARIANT & arm_ext_v4t_5
23664 /* ARM Architecture 4T. */
23665 /* Note: bx (and blx) are required on V5, even if the processor does
23666 not support Thumb. */
23667 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23670 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23671 #undef THUMB_VARIANT
23672 #define THUMB_VARIANT & arm_ext_v5t
23674 /* Note: blx has 2 variants; the .value coded here is for
23675 BLX(2). Only this variant has conditional execution. */
23676 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23677 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23679 #undef THUMB_VARIANT
23680 #define THUMB_VARIANT & arm_ext_v6t2
23682 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23683 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23684 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23685 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23686 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23687 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23688 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23689 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23692 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23693 #undef THUMB_VARIANT
23694 #define THUMB_VARIANT & arm_ext_v5exp
23696 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23697 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23698 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23699 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23701 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23702 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23704 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23705 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23706 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23707 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23709 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23710 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23711 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23712 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23714 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23715 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23717 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23718 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23719 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23720 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23723 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23724 #undef THUMB_VARIANT
23725 #define THUMB_VARIANT & arm_ext_v6t2
23727 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23728 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23730 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23731 ADDRGLDRS
), ldrd
, t_ldstd
),
23733 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23734 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23737 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23739 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23742 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23743 #undef THUMB_VARIANT
23744 #define THUMB_VARIANT & arm_ext_v6
23746 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23747 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23748 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23749 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23750 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23751 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23752 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23753 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23754 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23755 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23757 #undef THUMB_VARIANT
23758 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23760 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23761 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23763 #undef THUMB_VARIANT
23764 #define THUMB_VARIANT & arm_ext_v6t2
23766 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23767 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23769 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23770 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23772 /* ARM V6 not included in V7M. */
23773 #undef THUMB_VARIANT
23774 #define THUMB_VARIANT & arm_ext_v6_notm
23775 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23776 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23777 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23778 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23779 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23780 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23781 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23782 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23783 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23784 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23785 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23786 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23787 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23788 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23789 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23790 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23791 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23792 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23793 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23795 /* ARM V6 not included in V7M (eg. integer SIMD). */
23796 #undef THUMB_VARIANT
23797 #define THUMB_VARIANT & arm_ext_v6_dsp
23798 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23799 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23800 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23801 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23802 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23803 /* Old name for QASX. */
23804 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23805 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23806 /* Old name for QSAX. */
23807 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23808 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23809 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23810 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23811 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23812 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23813 /* Old name for SASX. */
23814 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23815 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23816 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23817 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23818 /* Old name for SHASX. */
23819 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23820 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23821 /* Old name for SHSAX. */
23822 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23823 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23824 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23825 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23826 /* Old name for SSAX. */
23827 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23828 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23829 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23830 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23831 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23832 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23833 /* Old name for UASX. */
23834 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23835 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23836 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23837 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23838 /* Old name for UHASX. */
23839 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23840 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23841 /* Old name for UHSAX. */
23842 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23843 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23844 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23845 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23846 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23847 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23848 /* Old name for UQASX. */
23849 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23850 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23851 /* Old name for UQSAX. */
23852 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23853 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23854 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23855 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23856 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23857 /* Old name for USAX. */
23858 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23859 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23860 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23861 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23862 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23863 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23864 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23865 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23866 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23867 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23868 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23869 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23870 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23871 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23872 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23873 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23874 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23875 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23876 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23877 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23878 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23879 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23880 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23881 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23882 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23883 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23884 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23885 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23886 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23887 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23888 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23889 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23890 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23891 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23894 #define ARM_VARIANT & arm_ext_v6k_v6t2
23895 #undef THUMB_VARIANT
23896 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23898 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23899 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23900 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23901 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23903 #undef THUMB_VARIANT
23904 #define THUMB_VARIANT & arm_ext_v6_notm
23905 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23907 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23908 RRnpcb
), strexd
, t_strexd
),
23910 #undef THUMB_VARIANT
23911 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23912 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23914 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23916 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23918 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23920 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23923 #define ARM_VARIANT & arm_ext_sec
23924 #undef THUMB_VARIANT
23925 #define THUMB_VARIANT & arm_ext_sec
23927 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23930 #define ARM_VARIANT & arm_ext_virt
23931 #undef THUMB_VARIANT
23932 #define THUMB_VARIANT & arm_ext_virt
23934 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23935 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23938 #define ARM_VARIANT & arm_ext_pan
23939 #undef THUMB_VARIANT
23940 #define THUMB_VARIANT & arm_ext_pan
23942 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23945 #define ARM_VARIANT & arm_ext_v6t2
23946 #undef THUMB_VARIANT
23947 #define THUMB_VARIANT & arm_ext_v6t2
23949 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23950 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23951 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23952 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23954 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23955 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23957 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23958 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23959 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23960 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23963 #define ARM_VARIANT & arm_ext_v3
23964 #undef THUMB_VARIANT
23965 #define THUMB_VARIANT & arm_ext_v6t2
23967 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23968 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23969 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23972 #define ARM_VARIANT & arm_ext_v6t2
23973 #undef THUMB_VARIANT
23974 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23975 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23976 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23978 /* Thumb-only instructions. */
23980 #define ARM_VARIANT NULL
23981 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23982 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23984 /* ARM does not really have an IT instruction, so always allow it.
23985 The opcode is copied from Thumb in order to allow warnings in
23986 -mimplicit-it=[never | arm] modes. */
23988 #define ARM_VARIANT & arm_ext_v1
23989 #undef THUMB_VARIANT
23990 #define THUMB_VARIANT & arm_ext_v6t2
23992 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23993 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23994 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23995 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23996 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23997 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23998 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23999 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24000 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24001 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24002 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24003 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24004 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24005 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24006 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24007 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24008 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24009 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24011 /* Thumb2 only instructions. */
24013 #define ARM_VARIANT NULL
24015 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24016 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24017 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24018 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24019 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24020 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24022 /* Hardware division instructions. */
24024 #define ARM_VARIANT & arm_ext_adiv
24025 #undef THUMB_VARIANT
24026 #define THUMB_VARIANT & arm_ext_div
24028 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24029 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24031 /* ARM V6M/V7 instructions. */
24033 #define ARM_VARIANT & arm_ext_barrier
24034 #undef THUMB_VARIANT
24035 #define THUMB_VARIANT & arm_ext_barrier
24037 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24038 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24039 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24041 /* ARM V7 instructions. */
24043 #define ARM_VARIANT & arm_ext_v7
24044 #undef THUMB_VARIANT
24045 #define THUMB_VARIANT & arm_ext_v7
24047 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24048 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24051 #define ARM_VARIANT & arm_ext_mp
24052 #undef THUMB_VARIANT
24053 #define THUMB_VARIANT & arm_ext_mp
24055 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24057 /* AArchv8 instructions. */
24059 #define ARM_VARIANT & arm_ext_v8
24061 /* Instructions shared between armv8-a and armv8-m. */
24062 #undef THUMB_VARIANT
24063 #define THUMB_VARIANT & arm_ext_atomics
24065 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24066 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24067 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24068 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24069 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24070 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24071 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24072 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24073 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24074 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24076 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24078 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24080 #undef THUMB_VARIANT
24081 #define THUMB_VARIANT & arm_ext_v8
24083 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24084 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24086 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24089 /* Defined in V8 but is in undefined encoding space for earlier
24090 architectures. However earlier architectures are required to treat
24091 this instuction as a semihosting trap as well. Hence while not explicitly
24092 defined as such, it is in fact correct to define the instruction for all
24094 #undef THUMB_VARIANT
24095 #define THUMB_VARIANT & arm_ext_v1
24097 #define ARM_VARIANT & arm_ext_v1
24098 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24100 /* ARMv8 T32 only. */
24102 #define ARM_VARIANT NULL
24103 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24104 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24105 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24107 /* FP for ARMv8. */
24109 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24110 #undef THUMB_VARIANT
24111 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24113 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24114 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24115 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24116 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24117 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24118 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24119 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24120 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24121 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24122 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24123 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24125 /* Crypto v1 extensions. */
24127 #define ARM_VARIANT & fpu_crypto_ext_armv8
24128 #undef THUMB_VARIANT
24129 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24131 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24132 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24133 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24134 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24135 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24136 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24137 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24138 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24139 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24140 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24141 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24142 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24143 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24144 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24147 #define ARM_VARIANT & crc_ext_armv8
24148 #undef THUMB_VARIANT
24149 #define THUMB_VARIANT & crc_ext_armv8
24150 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24151 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24152 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24153 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24154 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24155 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24157 /* ARMv8.2 RAS extension. */
24159 #define ARM_VARIANT & arm_ext_ras
24160 #undef THUMB_VARIANT
24161 #define THUMB_VARIANT & arm_ext_ras
24162 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24165 #define ARM_VARIANT & arm_ext_v8_3
24166 #undef THUMB_VARIANT
24167 #define THUMB_VARIANT & arm_ext_v8_3
24168 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24171 #define ARM_VARIANT & fpu_neon_ext_dotprod
24172 #undef THUMB_VARIANT
24173 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24174 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24175 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24178 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24179 #undef THUMB_VARIANT
24180 #define THUMB_VARIANT NULL
24182 cCE("wfs", e200110
, 1, (RR
), rd
),
24183 cCE("rfs", e300110
, 1, (RR
), rd
),
24184 cCE("wfc", e400110
, 1, (RR
), rd
),
24185 cCE("rfc", e500110
, 1, (RR
), rd
),
24187 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24188 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24189 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24190 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24192 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24193 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24194 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24195 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24197 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24198 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24199 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24200 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24201 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24202 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24203 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24204 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24205 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24206 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24207 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24208 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24210 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24211 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24212 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24213 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24214 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24215 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24216 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24217 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24218 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24219 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24220 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24221 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24223 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24224 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24225 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24226 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24227 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24228 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24229 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24230 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24231 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24232 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24233 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24234 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24236 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24237 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24238 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24239 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24240 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24241 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24242 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24243 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24244 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24245 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24246 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24247 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24249 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24250 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24251 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24252 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24253 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24254 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24255 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24256 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24257 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24263 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24266 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24267 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24269 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24270 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24276 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24279 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24280 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24282 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24283 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24289 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24292 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24293 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24295 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24296 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24302 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24305 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24306 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24308 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24309 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24310 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24311 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24312 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24314 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24315 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24316 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24317 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24318 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24319 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24320 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24321 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24322 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24323 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24324 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24325 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24327 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24328 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24329 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24330 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24331 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24332 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24333 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24334 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24335 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24336 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24337 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24338 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24340 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24341 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24342 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24343 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24344 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24345 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24346 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24347 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24348 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24349 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24350 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24351 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24353 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24354 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24355 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24356 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24357 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24358 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24359 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24360 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24361 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24362 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24363 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24364 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24366 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24367 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24368 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24369 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24370 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24371 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24372 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24373 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24374 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24375 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24376 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24377 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24379 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24380 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24381 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24382 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24383 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24384 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24385 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24386 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24387 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24388 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24389 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24390 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24392 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24393 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24394 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24395 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24396 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24397 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24398 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24399 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24400 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24401 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24402 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24403 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24405 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24406 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24407 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24408 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24409 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24410 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24411 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24412 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24413 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24414 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24415 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24416 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24418 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24419 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24420 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24421 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24422 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24423 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24424 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24425 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24426 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24427 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24428 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24429 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24431 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24432 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24433 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24434 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24435 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24436 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24437 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24438 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24439 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24440 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24441 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24442 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24444 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24445 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24446 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24447 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24448 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24449 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24450 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24451 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24452 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24453 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24454 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24455 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24457 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24458 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24459 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24460 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24461 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24462 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24463 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24464 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24465 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24471 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24474 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24475 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24477 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24478 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24479 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24480 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24481 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24483 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24484 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24485 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24486 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24487 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24488 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24489 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24490 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24491 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24492 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24493 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24494 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24496 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24497 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24498 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24499 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24500 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24501 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24502 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24503 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24504 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24505 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24506 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24507 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24509 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24510 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24511 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24512 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24513 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24514 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24515 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24516 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24517 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24518 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24519 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24520 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24522 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24523 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24524 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24525 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24526 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24527 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24528 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24529 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24530 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24531 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24532 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24533 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24535 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24536 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24537 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24538 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24539 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24540 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24541 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24542 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24543 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24544 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24545 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24546 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24548 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24549 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24550 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24551 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24552 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24553 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24554 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24555 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24556 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24557 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24558 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24559 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24561 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24562 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24563 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24564 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24565 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24566 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24567 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24568 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24569 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24570 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24571 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24572 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24574 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24575 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24576 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24577 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24579 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24580 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24581 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24582 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24583 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24584 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24585 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24586 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24587 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24588 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24589 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24590 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24592 /* The implementation of the FIX instruction is broken on some
24593 assemblers, in that it accepts a precision specifier as well as a
24594 rounding specifier, despite the fact that this is meaningless.
24595 To be more compatible, we accept it as well, though of course it
24596 does not set any bits. */
24597 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24598 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24599 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24600 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24601 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24602 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24603 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24604 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24605 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24606 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24607 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24608 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24609 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24611 /* Instructions that were new with the real FPA, call them V2. */
24613 #define ARM_VARIANT & fpu_fpa_ext_v2
24615 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24616 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24617 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24618 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24619 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24620 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24623 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24624 #undef THUMB_VARIANT
24625 #define THUMB_VARIANT & arm_ext_v6t2
24626 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24627 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24628 #undef THUMB_VARIANT
24630 /* Moves and type conversions. */
24631 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24632 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24633 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24634 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24635 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24636 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24637 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24638 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24639 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24641 /* Memory operations. */
24642 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24643 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24644 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24645 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24646 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24647 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24648 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24649 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24650 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24651 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24652 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24653 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24654 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24655 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24656 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24657 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24658 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24659 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24661 /* Monadic operations. */
24662 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24663 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24664 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24666 /* Dyadic operations. */
24667 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24668 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24669 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24670 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24671 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24672 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24673 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24674 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24675 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24678 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24679 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24680 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24681 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24683 /* Double precision load/store are still present on single precision
24684 implementations. */
24685 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24686 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24687 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24688 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24689 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24690 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24691 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24692 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24693 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24694 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24697 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24699 /* Moves and type conversions. */
24700 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24701 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24702 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24703 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24704 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24705 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24706 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24707 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24708 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24709 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24710 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24711 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24713 /* Monadic operations. */
24714 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24715 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24716 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24718 /* Dyadic operations. */
24719 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24720 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24721 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24722 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24723 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24724 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24725 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24726 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24727 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24730 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24731 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24732 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24733 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24735 /* Instructions which may belong to either the Neon or VFP instruction sets.
24736 Individual encoder functions perform additional architecture checks. */
24738 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24739 #undef THUMB_VARIANT
24740 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24742 /* These mnemonics are unique to VFP. */
24743 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24744 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24745 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24746 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24747 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24748 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24749 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24750 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24752 /* Mnemonics shared by Neon and VFP. */
24753 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24755 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24756 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24757 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24758 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24759 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24760 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24762 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24763 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24764 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24765 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24768 /* NOTE: All VMOV encoding is special-cased! */
24769 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24771 #undef THUMB_VARIANT
24772 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24773 by different feature bits. Since we are setting the Thumb guard, we can
24774 require Thumb-1 which makes it a nop guard and set the right feature bit in
24775 do_vldr_vstr (). */
24776 #define THUMB_VARIANT & arm_ext_v4t
24777 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24778 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24781 #define ARM_VARIANT & arm_ext_fp16
24782 #undef THUMB_VARIANT
24783 #define THUMB_VARIANT & arm_ext_fp16
24784 /* New instructions added from v8.2, allowing the extraction and insertion of
24785 the upper 16 bits of a 32-bit vector register. */
24786 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24787 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24789 /* New backported fma/fms instructions optional in v8.2. */
24790 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24791 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24793 #undef THUMB_VARIANT
24794 #define THUMB_VARIANT & fpu_neon_ext_v1
24796 #define ARM_VARIANT & fpu_neon_ext_v1
24798 /* Data processing with three registers of the same length. */
24799 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24800 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24801 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24802 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24803 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24804 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24805 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24806 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24807 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24808 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24809 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24810 /* If not immediate, fall back to neon_dyadic_i64_su.
24811 shl should accept I8 I16 I32 I64,
24812 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24813 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24814 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24815 /* Logic ops, types optional & ignored. */
24816 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24817 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24818 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24819 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24820 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24821 /* Bitfield ops, untyped. */
24822 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24823 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24824 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24825 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24826 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24827 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24828 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24829 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24830 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24831 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24832 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24833 back to neon_dyadic_if_su. */
24834 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24835 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24836 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24837 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24838 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24839 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24840 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24841 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24842 /* Comparison. Type I8 I16 I32 F32. */
24843 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24844 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24845 /* As above, D registers only. */
24846 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24847 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24848 /* Int and float variants, signedness unimportant. */
24849 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24850 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24851 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24852 /* Add/sub take types I8 I16 I32 I64 F32. */
24853 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24854 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24855 /* vtst takes sizes 8, 16, 32. */
24856 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24857 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24858 /* VMUL takes I8 I16 I32 F32 P8. */
24859 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24860 /* VQD{R}MULH takes S16 S32. */
24861 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24862 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24863 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24864 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24865 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24866 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24867 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24868 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24869 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24870 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24871 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24872 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24873 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24874 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24875 /* ARM v8.1 extension. */
24876 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24877 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24878 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24880 /* Two address, int/float. Types S8 S16 S32 F32. */
24881 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24882 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24884 /* Data processing with two registers and a shift amount. */
24885 /* Right shifts, and variants with rounding.
24886 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24887 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24888 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24889 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24890 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24891 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24892 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24893 /* Shift and insert. Sizes accepted 8 16 32 64. */
24894 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24895 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24896 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24897 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24898 /* Right shift immediate, saturating & narrowing, with rounding variants.
24899 Types accepted S16 S32 S64 U16 U32 U64. */
24900 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24901 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24902 /* As above, unsigned. Types accepted S16 S32 S64. */
24903 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24904 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24905 /* Right shift narrowing. Types accepted I16 I32 I64. */
24906 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24907 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24908 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24909 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24910 /* CVT with optional immediate for fixed-point variant. */
24911 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24913 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24915 /* Data processing, three registers of different lengths. */
24916 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24917 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24918 /* If not scalar, fall back to neon_dyadic_long.
24919 Vector types as above, scalar types S16 S32 U16 U32. */
24920 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24921 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24922 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24923 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24924 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24925 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24926 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24927 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24928 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24929 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24930 /* Saturating doubling multiplies. Types S16 S32. */
24931 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24932 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24933 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24934 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24935 S16 S32 U16 U32. */
24936 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24938 /* Extract. Size 8. */
24939 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24940 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24942 /* Two registers, miscellaneous. */
24943 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24944 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24945 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24946 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24947 /* Vector replicate. Sizes 8 16 32. */
24948 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24949 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24950 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24951 /* VMOVN. Types I16 I32 I64. */
24952 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24953 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24954 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24955 /* VQMOVUN. Types S16 S32 S64. */
24956 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24957 /* VZIP / VUZP. Sizes 8 16 32. */
24958 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24959 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24960 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24961 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24962 /* VQABS / VQNEG. Types S8 S16 S32. */
24963 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24964 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24965 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24966 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24967 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24968 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24969 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24970 /* Reciprocal estimates. Types U32 F16 F32. */
24971 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24972 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24973 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24974 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24975 /* VCLS. Types S8 S16 S32. */
24976 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24977 /* VCLZ. Types I8 I16 I32. */
24978 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24979 /* VCNT. Size 8. */
24980 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24981 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24982 /* Two address, untyped. */
24983 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24984 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24985 /* VTRN. Sizes 8 16 32. */
24986 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24987 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24989 /* Table lookup. Size 8. */
24990 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24991 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24993 #undef THUMB_VARIANT
24994 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24996 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24998 /* Neon element/structure load/store. */
24999 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25000 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25001 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25002 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25003 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25004 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25005 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25006 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25008 #undef THUMB_VARIANT
25009 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25011 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25012 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25013 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25014 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25015 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25016 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25017 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25018 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25019 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25020 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25022 #undef THUMB_VARIANT
25023 #define THUMB_VARIANT & fpu_vfp_ext_v3
25025 #define ARM_VARIANT & fpu_vfp_ext_v3
25027 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25028 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25029 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25030 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25031 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25032 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25033 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25034 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25035 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25038 #define ARM_VARIANT & fpu_vfp_ext_fma
25039 #undef THUMB_VARIANT
25040 #define THUMB_VARIANT & fpu_vfp_ext_fma
25041 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
25042 VFP FMA variant; NEON and VFP FMA always includes the NEON
25043 FMA instructions. */
25044 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25045 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25047 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25048 the v form should always be used. */
25049 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25050 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25051 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25052 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25053 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25054 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25056 #undef THUMB_VARIANT
25058 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25060 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25061 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25062 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25063 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25064 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25065 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25066 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25067 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25070 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25072 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25073 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25074 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25075 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25076 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25077 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25078 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25079 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25080 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25081 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25082 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25083 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25084 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25085 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25086 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25087 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25088 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25089 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25090 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25091 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25092 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25093 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25094 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25095 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25096 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25097 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25098 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25099 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25100 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25101 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25102 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25103 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25104 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25105 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25106 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25107 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25108 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25109 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25110 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25111 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25112 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25113 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25114 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25115 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25116 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25117 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25118 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25119 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25120 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25121 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25122 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25123 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25124 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25125 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25126 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25127 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25128 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25129 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25130 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25131 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25132 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25133 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25134 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25135 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25136 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25137 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25138 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25139 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25140 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25141 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25142 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25143 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25144 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25145 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25146 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25147 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25148 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25149 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25150 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25151 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25152 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25153 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25154 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25155 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25156 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25157 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25158 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25159 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25160 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25161 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25162 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25163 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25164 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25165 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25166 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25167 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25168 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25169 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25170 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25171 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25173 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25174 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25175 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25176 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25177 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25178 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25179 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25180 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25181 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25182 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25183 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25184 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25185 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25186 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25187 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25188 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25189 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25190 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25191 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25192 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25193 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25194 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25195 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25196 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25197 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25198 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25199 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25200 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25201 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25202 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25203 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25204 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25205 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25206 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25207 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25208 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25209 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25210 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25211 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25212 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25213 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25214 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25215 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25216 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25217 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25218 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25219 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25220 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25221 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25222 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25223 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25224 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25225 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25226 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25227 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25228 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25229 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25230 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25231 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25232 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25233 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25236 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25238 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25239 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25240 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25241 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25242 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25243 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25244 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25245 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25246 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25247 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25248 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25249 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25250 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25251 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25252 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25253 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25254 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25255 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25256 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25257 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25258 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25259 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25260 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25261 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25262 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25263 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25264 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25265 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25266 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25267 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25268 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25269 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25270 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25271 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25272 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25273 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25274 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25275 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25276 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25277 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25278 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25279 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25280 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25281 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25282 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25283 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25284 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25285 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25286 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25287 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25288 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25289 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25290 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25291 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25292 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25293 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25294 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25297 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25299 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25300 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25301 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25302 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25303 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25304 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25305 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25306 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25307 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25308 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25309 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25310 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25311 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25312 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25313 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25314 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25315 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25316 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25317 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25318 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25319 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25320 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25321 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25322 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25323 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25324 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25325 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25326 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25327 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25328 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25329 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25330 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25331 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25332 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25333 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25334 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25335 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25336 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25337 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25338 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25339 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25340 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25341 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25342 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25343 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25344 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25345 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25346 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25347 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25348 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25349 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25350 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25351 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25352 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25353 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25354 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25355 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25356 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25357 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25358 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25359 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25360 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25361 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25362 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25363 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25364 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25365 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25366 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25367 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25368 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25369 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25370 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25371 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25372 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25373 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25374 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25376 /* ARMv8.5-A instructions. */
25378 #define ARM_VARIANT & arm_ext_sb
25379 #undef THUMB_VARIANT
25380 #define THUMB_VARIANT & arm_ext_sb
25381 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25384 #define ARM_VARIANT & arm_ext_predres
25385 #undef THUMB_VARIANT
25386 #define THUMB_VARIANT & arm_ext_predres
25387 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25388 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25389 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25391 /* ARMv8-M instructions. */
25393 #define ARM_VARIANT NULL
25394 #undef THUMB_VARIANT
25395 #define THUMB_VARIANT & arm_ext_v8m
25396 ToU("sg", e97fe97f
, 0, (), noargs
),
25397 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25398 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25399 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25400 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25401 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25402 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25404 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25405 instructions behave as nop if no VFP is present. */
25406 #undef THUMB_VARIANT
25407 #define THUMB_VARIANT & arm_ext_v8m_main
25408 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25409 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25411 /* Armv8.1-M Mainline instructions. */
25412 #undef THUMB_VARIANT
25413 #define THUMB_VARIANT & arm_ext_v8_1m_main
25414 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25415 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25416 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25417 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25418 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25419 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25420 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25421 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25422 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25424 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25425 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25426 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25427 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25428 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25430 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25431 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25432 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25434 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25435 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25437 #undef THUMB_VARIANT
25438 #define THUMB_VARIANT & mve_ext
25439 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25440 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25441 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25442 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25443 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25444 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25445 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25446 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25447 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25448 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25449 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25450 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25451 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25452 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25453 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25455 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25456 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25457 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25458 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25459 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25460 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25461 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25462 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25463 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25464 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25465 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25466 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25467 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25468 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25469 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25471 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25472 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25473 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25474 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25475 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25476 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25477 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25478 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25479 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25480 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25481 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25482 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25483 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25484 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25485 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25487 /* MVE and MVE FP only. */
25488 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25489 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25490 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25491 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25492 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25493 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25494 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25495 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25496 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25497 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25498 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25499 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25500 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25501 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25502 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25503 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25504 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25506 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25507 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25508 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25509 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25510 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25511 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25512 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25513 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25514 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25515 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25516 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25517 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25518 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25519 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25520 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25521 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25522 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25523 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25524 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25525 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25527 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25528 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25529 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25530 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25531 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25532 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25533 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25534 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25535 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25536 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25537 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25538 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25539 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25540 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25541 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25542 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25543 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25545 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25546 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25547 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25548 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25549 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25550 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25551 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25552 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25553 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25554 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25555 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25556 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25557 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25558 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25559 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25560 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25561 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25562 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25563 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25564 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25566 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25567 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25568 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25569 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25570 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25572 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25573 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25574 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25575 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25576 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25577 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25578 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25579 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25580 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25581 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25582 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25583 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25584 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25585 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25586 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25587 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25588 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25590 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25591 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25592 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25593 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25594 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25595 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25596 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25597 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25598 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25599 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25600 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25601 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25603 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25604 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25605 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25607 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25608 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25609 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25610 toU("lctp", _lctp
, 0, (), t_loloop
),
25612 #undef THUMB_VARIANT
25613 #define THUMB_VARIANT & mve_fp_ext
25614 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25615 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25616 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25617 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25618 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25619 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25620 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25621 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25624 #define ARM_VARIANT & fpu_vfp_ext_v1
25625 #undef THUMB_VARIANT
25626 #define THUMB_VARIANT & arm_ext_v6t2
25627 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25628 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25630 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25633 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25635 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25636 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25637 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25638 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25640 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25641 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25642 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25644 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25645 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25647 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25648 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25650 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25651 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25654 #define ARM_VARIANT & fpu_vfp_ext_v2
25656 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25657 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25658 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25659 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25662 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25663 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25664 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25665 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25666 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25667 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25668 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25671 #define ARM_VARIANT & fpu_neon_ext_v1
25672 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25673 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25674 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25675 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25676 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25677 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25678 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25679 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25680 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25681 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25682 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25683 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25684 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25685 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25686 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25687 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25688 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25689 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25690 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25691 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25692 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25693 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25694 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25695 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25696 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25697 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25698 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25699 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25700 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25701 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25702 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25703 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25704 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25705 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25706 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25707 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25708 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25711 #define ARM_VARIANT & arm_ext_v8_3
25712 #undef THUMB_VARIANT
25713 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25714 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25715 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25718 #undef THUMB_VARIANT
25750 /* MD interface: bits in the object file. */
25752 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25753 for use in the a.out file, and stores them in the array pointed to by buf.
25754 This knows about the endian-ness of the target machine and does
25755 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25756 2 (short) and 4 (long) Floating numbers are put out as a series of
25757 LITTLENUMS (shorts, here at least). */
25760 md_number_to_chars (char * buf
, valueT val
, int n
)
25762 if (target_big_endian
)
25763 number_to_chars_bigendian (buf
, val
, n
);
25765 number_to_chars_littleendian (buf
, val
, n
);
25769 md_chars_to_number (char * buf
, int n
)
25772 unsigned char * where
= (unsigned char *) buf
;
25774 if (target_big_endian
)
25779 result
|= (*where
++ & 255);
25787 result
|= (where
[n
] & 255);
25794 /* MD interface: Sections. */
25796 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25797 that an rs_machine_dependent frag may reach. */
25800 arm_frag_max_var (fragS
*fragp
)
25802 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25803 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25805 Note that we generate relaxable instructions even for cases that don't
25806 really need it, like an immediate that's a trivial constant. So we're
25807 overestimating the instruction size for some of those cases. Rather
25808 than putting more intelligence here, it would probably be better to
25809 avoid generating a relaxation frag in the first place when it can be
25810 determined up front that a short instruction will suffice. */
25812 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25816 /* Estimate the size of a frag before relaxing. Assume everything fits in
25820 md_estimate_size_before_relax (fragS
* fragp
,
25821 segT segtype ATTRIBUTE_UNUSED
)
25827 /* Convert a machine dependent frag. */
25830 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25832 unsigned long insn
;
25833 unsigned long old_op
;
25841 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25843 old_op
= bfd_get_16(abfd
, buf
);
25844 if (fragp
->fr_symbol
)
25846 exp
.X_op
= O_symbol
;
25847 exp
.X_add_symbol
= fragp
->fr_symbol
;
25851 exp
.X_op
= O_constant
;
25853 exp
.X_add_number
= fragp
->fr_offset
;
25854 opcode
= fragp
->fr_subtype
;
25857 case T_MNEM_ldr_pc
:
25858 case T_MNEM_ldr_pc2
:
25859 case T_MNEM_ldr_sp
:
25860 case T_MNEM_str_sp
:
25867 if (fragp
->fr_var
== 4)
25869 insn
= THUMB_OP32 (opcode
);
25870 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25872 insn
|= (old_op
& 0x700) << 4;
25876 insn
|= (old_op
& 7) << 12;
25877 insn
|= (old_op
& 0x38) << 13;
25879 insn
|= 0x00000c00;
25880 put_thumb32_insn (buf
, insn
);
25881 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25885 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25887 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25890 if (fragp
->fr_var
== 4)
25892 insn
= THUMB_OP32 (opcode
);
25893 insn
|= (old_op
& 0xf0) << 4;
25894 put_thumb32_insn (buf
, insn
);
25895 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25899 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25900 exp
.X_add_number
-= 4;
25908 if (fragp
->fr_var
== 4)
25910 int r0off
= (opcode
== T_MNEM_mov
25911 || opcode
== T_MNEM_movs
) ? 0 : 8;
25912 insn
= THUMB_OP32 (opcode
);
25913 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25914 insn
|= (old_op
& 0x700) << r0off
;
25915 put_thumb32_insn (buf
, insn
);
25916 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25920 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25925 if (fragp
->fr_var
== 4)
25927 insn
= THUMB_OP32(opcode
);
25928 put_thumb32_insn (buf
, insn
);
25929 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25932 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25936 if (fragp
->fr_var
== 4)
25938 insn
= THUMB_OP32(opcode
);
25939 insn
|= (old_op
& 0xf00) << 14;
25940 put_thumb32_insn (buf
, insn
);
25941 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25944 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25947 case T_MNEM_add_sp
:
25948 case T_MNEM_add_pc
:
25949 case T_MNEM_inc_sp
:
25950 case T_MNEM_dec_sp
:
25951 if (fragp
->fr_var
== 4)
25953 /* ??? Choose between add and addw. */
25954 insn
= THUMB_OP32 (opcode
);
25955 insn
|= (old_op
& 0xf0) << 4;
25956 put_thumb32_insn (buf
, insn
);
25957 if (opcode
== T_MNEM_add_pc
)
25958 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25960 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25963 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25971 if (fragp
->fr_var
== 4)
25973 insn
= THUMB_OP32 (opcode
);
25974 insn
|= (old_op
& 0xf0) << 4;
25975 insn
|= (old_op
& 0xf) << 16;
25976 put_thumb32_insn (buf
, insn
);
25977 if (insn
& (1 << 20))
25978 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25980 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25983 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25989 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25990 (enum bfd_reloc_code_real
) reloc_type
);
25991 fixp
->fx_file
= fragp
->fr_file
;
25992 fixp
->fx_line
= fragp
->fr_line
;
25993 fragp
->fr_fix
+= fragp
->fr_var
;
25995 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25996 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25997 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25998 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26001 /* Return the size of a relaxable immediate operand instruction.
26002 SHIFT and SIZE specify the form of the allowable immediate. */
26004 relax_immediate (fragS
*fragp
, int size
, int shift
)
26010 /* ??? Should be able to do better than this. */
26011 if (fragp
->fr_symbol
)
26014 low
= (1 << shift
) - 1;
26015 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26016 offset
= fragp
->fr_offset
;
26017 /* Force misaligned offsets to 32-bit variant. */
26020 if (offset
& ~mask
)
26025 /* Get the address of a symbol during relaxation. */
26027 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26033 sym
= fragp
->fr_symbol
;
26034 sym_frag
= symbol_get_frag (sym
);
26035 know (S_GET_SEGMENT (sym
) != absolute_section
26036 || sym_frag
== &zero_address_frag
);
26037 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26039 /* If frag has yet to be reached on this pass, assume it will
26040 move by STRETCH just as we did. If this is not so, it will
26041 be because some frag between grows, and that will force
26045 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26049 /* Adjust stretch for any alignment frag. Note that if have
26050 been expanding the earlier code, the symbol may be
26051 defined in what appears to be an earlier frag. FIXME:
26052 This doesn't handle the fr_subtype field, which specifies
26053 a maximum number of bytes to skip when doing an
26055 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26057 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26060 stretch
= - ((- stretch
)
26061 & ~ ((1 << (int) f
->fr_offset
) - 1));
26063 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26075 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26078 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26083 /* Assume worst case for symbols not known to be in the same section. */
26084 if (fragp
->fr_symbol
== NULL
26085 || !S_IS_DEFINED (fragp
->fr_symbol
)
26086 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26087 || S_IS_WEAK (fragp
->fr_symbol
))
26090 val
= relaxed_symbol_addr (fragp
, stretch
);
26091 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26092 addr
= (addr
+ 4) & ~3;
26093 /* Force misaligned targets to 32-bit variant. */
26097 if (val
< 0 || val
> 1020)
26102 /* Return the size of a relaxable add/sub immediate instruction. */
26104 relax_addsub (fragS
*fragp
, asection
*sec
)
26109 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26110 op
= bfd_get_16(sec
->owner
, buf
);
26111 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26112 return relax_immediate (fragp
, 8, 0);
26114 return relax_immediate (fragp
, 3, 0);
26117 /* Return TRUE iff the definition of symbol S could be pre-empted
26118 (overridden) at link or load time. */
26120 symbol_preemptible (symbolS
*s
)
26122 /* Weak symbols can always be pre-empted. */
26126 /* Non-global symbols cannot be pre-empted. */
26127 if (! S_IS_EXTERNAL (s
))
26131 /* In ELF, a global symbol can be marked protected, or private. In that
26132 case it can't be pre-empted (other definitions in the same link unit
26133 would violate the ODR). */
26134 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26138 /* Other global symbols might be pre-empted. */
26142 /* Return the size of a relaxable branch instruction. BITS is the
26143 size of the offset field in the narrow instruction. */
26146 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26152 /* Assume worst case for symbols not known to be in the same section. */
26153 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26154 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26155 || S_IS_WEAK (fragp
->fr_symbol
))
26159 /* A branch to a function in ARM state will require interworking. */
26160 if (S_IS_DEFINED (fragp
->fr_symbol
)
26161 && ARM_IS_FUNC (fragp
->fr_symbol
))
26165 if (symbol_preemptible (fragp
->fr_symbol
))
26168 val
= relaxed_symbol_addr (fragp
, stretch
);
26169 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26172 /* Offset is a signed value *2 */
26174 if (val
>= limit
|| val
< -limit
)
26180 /* Relax a machine dependent frag. This returns the amount by which
26181 the current size of the frag should change. */
26184 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26189 oldsize
= fragp
->fr_var
;
26190 switch (fragp
->fr_subtype
)
26192 case T_MNEM_ldr_pc2
:
26193 newsize
= relax_adr (fragp
, sec
, stretch
);
26195 case T_MNEM_ldr_pc
:
26196 case T_MNEM_ldr_sp
:
26197 case T_MNEM_str_sp
:
26198 newsize
= relax_immediate (fragp
, 8, 2);
26202 newsize
= relax_immediate (fragp
, 5, 2);
26206 newsize
= relax_immediate (fragp
, 5, 1);
26210 newsize
= relax_immediate (fragp
, 5, 0);
26213 newsize
= relax_adr (fragp
, sec
, stretch
);
26219 newsize
= relax_immediate (fragp
, 8, 0);
26222 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26225 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26227 case T_MNEM_add_sp
:
26228 case T_MNEM_add_pc
:
26229 newsize
= relax_immediate (fragp
, 8, 2);
26231 case T_MNEM_inc_sp
:
26232 case T_MNEM_dec_sp
:
26233 newsize
= relax_immediate (fragp
, 7, 2);
26239 newsize
= relax_addsub (fragp
, sec
);
26245 fragp
->fr_var
= newsize
;
26246 /* Freeze wide instructions that are at or before the same location as
26247 in the previous pass. This avoids infinite loops.
26248 Don't freeze them unconditionally because targets may be artificially
26249 misaligned by the expansion of preceding frags. */
26250 if (stretch
<= 0 && newsize
> 2)
26252 md_convert_frag (sec
->owner
, sec
, fragp
);
26256 return newsize
- oldsize
;
26259 /* Round up a section size to the appropriate boundary. */
26262 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26268 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26269 of an rs_align_code fragment. */
26272 arm_handle_align (fragS
* fragP
)
26274 static unsigned char const arm_noop
[2][2][4] =
26277 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26278 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26281 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26282 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26285 static unsigned char const thumb_noop
[2][2][2] =
26288 {0xc0, 0x46}, /* LE */
26289 {0x46, 0xc0}, /* BE */
26292 {0x00, 0xbf}, /* LE */
26293 {0xbf, 0x00} /* BE */
26296 static unsigned char const wide_thumb_noop
[2][4] =
26297 { /* Wide Thumb-2 */
26298 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26299 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26302 unsigned bytes
, fix
, noop_size
;
26304 const unsigned char * noop
;
26305 const unsigned char *narrow_noop
= NULL
;
26310 if (fragP
->fr_type
!= rs_align_code
)
26313 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26314 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26317 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26318 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26320 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26322 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26324 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26325 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26327 narrow_noop
= thumb_noop
[1][target_big_endian
];
26328 noop
= wide_thumb_noop
[target_big_endian
];
26331 noop
= thumb_noop
[0][target_big_endian
];
26339 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26340 ? selected_cpu
: arm_arch_none
,
26342 [target_big_endian
];
26349 fragP
->fr_var
= noop_size
;
26351 if (bytes
& (noop_size
- 1))
26353 fix
= bytes
& (noop_size
- 1);
26355 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26357 memset (p
, 0, fix
);
26364 if (bytes
& noop_size
)
26366 /* Insert a narrow noop. */
26367 memcpy (p
, narrow_noop
, noop_size
);
26369 bytes
-= noop_size
;
26373 /* Use wide noops for the remainder */
26377 while (bytes
>= noop_size
)
26379 memcpy (p
, noop
, noop_size
);
26381 bytes
-= noop_size
;
26385 fragP
->fr_fix
+= fix
;
26388 /* Called from md_do_align. Used to create an alignment
26389 frag in a code section. */
26392 arm_frag_align_code (int n
, int max
)
26396 /* We assume that there will never be a requirement
26397 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26398 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26403 _("alignments greater than %d bytes not supported in .text sections."),
26404 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26405 as_fatal ("%s", err_msg
);
26408 p
= frag_var (rs_align_code
,
26409 MAX_MEM_FOR_RS_ALIGN_CODE
,
26411 (relax_substateT
) max
,
26418 /* Perform target specific initialisation of a frag.
26419 Note - despite the name this initialisation is not done when the frag
26420 is created, but only when its type is assigned. A frag can be created
26421 and used a long time before its type is set, so beware of assuming that
26422 this initialisation is performed first. */
26426 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26428 /* Record whether this frag is in an ARM or a THUMB area. */
26429 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26432 #else /* OBJ_ELF is defined. */
26434 arm_init_frag (fragS
* fragP
, int max_chars
)
26436 bfd_boolean frag_thumb_mode
;
26438 /* If the current ARM vs THUMB mode has not already
26439 been recorded into this frag then do so now. */
26440 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26441 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26443 /* PR 21809: Do not set a mapping state for debug sections
26444 - it just confuses other tools. */
26445 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26448 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26450 /* Record a mapping symbol for alignment frags. We will delete this
26451 later if the alignment ends up empty. */
26452 switch (fragP
->fr_type
)
26455 case rs_align_test
:
26457 mapping_state_2 (MAP_DATA
, max_chars
);
26459 case rs_align_code
:
26460 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26467 /* When we change sections we need to issue a new mapping symbol. */
26470 arm_elf_change_section (void)
26472 /* Link an unlinked unwind index table section to the .text section. */
26473 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26474 && elf_linked_to_section (now_seg
) == NULL
)
26475 elf_linked_to_section (now_seg
) = text_section
;
26479 arm_elf_section_type (const char * str
, size_t len
)
26481 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26482 return SHT_ARM_EXIDX
;
26487 /* Code to deal with unwinding tables. */
26489 static void add_unwind_adjustsp (offsetT
);
26491 /* Generate any deferred unwind frame offset. */
26494 flush_pending_unwind (void)
26498 offset
= unwind
.pending_offset
;
26499 unwind
.pending_offset
= 0;
26501 add_unwind_adjustsp (offset
);
26504 /* Add an opcode to this list for this function. Two-byte opcodes should
26505 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26509 add_unwind_opcode (valueT op
, int length
)
26511 /* Add any deferred stack adjustment. */
26512 if (unwind
.pending_offset
)
26513 flush_pending_unwind ();
26515 unwind
.sp_restored
= 0;
26517 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26519 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26520 if (unwind
.opcodes
)
26521 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26522 unwind
.opcode_alloc
);
26524 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26529 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26531 unwind
.opcode_count
++;
26535 /* Add unwind opcodes to adjust the stack pointer. */
26538 add_unwind_adjustsp (offsetT offset
)
26542 if (offset
> 0x200)
26544 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26549 /* Long form: 0xb2, uleb128. */
26550 /* This might not fit in a word so add the individual bytes,
26551 remembering the list is built in reverse order. */
26552 o
= (valueT
) ((offset
- 0x204) >> 2);
26554 add_unwind_opcode (0, 1);
26556 /* Calculate the uleb128 encoding of the offset. */
26560 bytes
[n
] = o
& 0x7f;
26566 /* Add the insn. */
26568 add_unwind_opcode (bytes
[n
- 1], 1);
26569 add_unwind_opcode (0xb2, 1);
26571 else if (offset
> 0x100)
26573 /* Two short opcodes. */
26574 add_unwind_opcode (0x3f, 1);
26575 op
= (offset
- 0x104) >> 2;
26576 add_unwind_opcode (op
, 1);
26578 else if (offset
> 0)
26580 /* Short opcode. */
26581 op
= (offset
- 4) >> 2;
26582 add_unwind_opcode (op
, 1);
26584 else if (offset
< 0)
26587 while (offset
> 0x100)
26589 add_unwind_opcode (0x7f, 1);
26592 op
= ((offset
- 4) >> 2) | 0x40;
26593 add_unwind_opcode (op
, 1);
26597 /* Finish the list of unwind opcodes for this function. */
26600 finish_unwind_opcodes (void)
26604 if (unwind
.fp_used
)
26606 /* Adjust sp as necessary. */
26607 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26608 flush_pending_unwind ();
26610 /* After restoring sp from the frame pointer. */
26611 op
= 0x90 | unwind
.fp_reg
;
26612 add_unwind_opcode (op
, 1);
26615 flush_pending_unwind ();
26619 /* Start an exception table entry. If idx is nonzero this is an index table
26623 start_unwind_section (const segT text_seg
, int idx
)
26625 const char * text_name
;
26626 const char * prefix
;
26627 const char * prefix_once
;
26628 const char * group_name
;
26636 prefix
= ELF_STRING_ARM_unwind
;
26637 prefix_once
= ELF_STRING_ARM_unwind_once
;
26638 type
= SHT_ARM_EXIDX
;
26642 prefix
= ELF_STRING_ARM_unwind_info
;
26643 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26644 type
= SHT_PROGBITS
;
26647 text_name
= segment_name (text_seg
);
26648 if (streq (text_name
, ".text"))
26651 if (strncmp (text_name
, ".gnu.linkonce.t.",
26652 strlen (".gnu.linkonce.t.")) == 0)
26654 prefix
= prefix_once
;
26655 text_name
+= strlen (".gnu.linkonce.t.");
26658 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26664 /* Handle COMDAT group. */
26665 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26667 group_name
= elf_group_name (text_seg
);
26668 if (group_name
== NULL
)
26670 as_bad (_("Group section `%s' has no group signature"),
26671 segment_name (text_seg
));
26672 ignore_rest_of_line ();
26675 flags
|= SHF_GROUP
;
26679 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26682 /* Set the section link for index tables. */
26684 elf_linked_to_section (now_seg
) = text_seg
;
26688 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26689 personality routine data. Returns zero, or the index table value for
26690 an inline entry. */
26693 create_unwind_entry (int have_data
)
26698 /* The current word of data. */
26700 /* The number of bytes left in this word. */
26703 finish_unwind_opcodes ();
26705 /* Remember the current text section. */
26706 unwind
.saved_seg
= now_seg
;
26707 unwind
.saved_subseg
= now_subseg
;
26709 start_unwind_section (now_seg
, 0);
26711 if (unwind
.personality_routine
== NULL
)
26713 if (unwind
.personality_index
== -2)
26716 as_bad (_("handlerdata in cantunwind frame"));
26717 return 1; /* EXIDX_CANTUNWIND. */
26720 /* Use a default personality routine if none is specified. */
26721 if (unwind
.personality_index
== -1)
26723 if (unwind
.opcode_count
> 3)
26724 unwind
.personality_index
= 1;
26726 unwind
.personality_index
= 0;
26729 /* Space for the personality routine entry. */
26730 if (unwind
.personality_index
== 0)
26732 if (unwind
.opcode_count
> 3)
26733 as_bad (_("too many unwind opcodes for personality routine 0"));
26737 /* All the data is inline in the index table. */
26740 while (unwind
.opcode_count
> 0)
26742 unwind
.opcode_count
--;
26743 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26747 /* Pad with "finish" opcodes. */
26749 data
= (data
<< 8) | 0xb0;
26756 /* We get two opcodes "free" in the first word. */
26757 size
= unwind
.opcode_count
- 2;
26761 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26762 if (unwind
.personality_index
!= -1)
26764 as_bad (_("attempt to recreate an unwind entry"));
26768 /* An extra byte is required for the opcode count. */
26769 size
= unwind
.opcode_count
+ 1;
26772 size
= (size
+ 3) >> 2;
26774 as_bad (_("too many unwind opcodes"));
26776 frag_align (2, 0, 0);
26777 record_alignment (now_seg
, 2);
26778 unwind
.table_entry
= expr_build_dot ();
26780 /* Allocate the table entry. */
26781 ptr
= frag_more ((size
<< 2) + 4);
26782 /* PR 13449: Zero the table entries in case some of them are not used. */
26783 memset (ptr
, 0, (size
<< 2) + 4);
26784 where
= frag_now_fix () - ((size
<< 2) + 4);
26786 switch (unwind
.personality_index
)
26789 /* ??? Should this be a PLT generating relocation? */
26790 /* Custom personality routine. */
26791 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26792 BFD_RELOC_ARM_PREL31
);
26797 /* Set the first byte to the number of additional words. */
26798 data
= size
> 0 ? size
- 1 : 0;
26802 /* ABI defined personality routines. */
26804 /* Three opcodes bytes are packed into the first word. */
26811 /* The size and first two opcode bytes go in the first word. */
26812 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26817 /* Should never happen. */
26821 /* Pack the opcodes into words (MSB first), reversing the list at the same
26823 while (unwind
.opcode_count
> 0)
26827 md_number_to_chars (ptr
, data
, 4);
26832 unwind
.opcode_count
--;
26834 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26837 /* Finish off the last word. */
26840 /* Pad with "finish" opcodes. */
26842 data
= (data
<< 8) | 0xb0;
26844 md_number_to_chars (ptr
, data
, 4);
26849 /* Add an empty descriptor if there is no user-specified data. */
26850 ptr
= frag_more (4);
26851 md_number_to_chars (ptr
, 0, 4);
26858 /* Initialize the DWARF-2 unwind information for this procedure. */
26861 tc_arm_frame_initial_instructions (void)
26863 cfi_add_CFA_def_cfa (REG_SP
, 0);
26865 #endif /* OBJ_ELF */
26867 /* Convert REGNAME to a DWARF-2 register number. */
26870 tc_arm_regname_to_dw2regnum (char *regname
)
26872 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26876 /* PR 16694: Allow VFP registers as well. */
26877 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26881 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26890 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26894 exp
.X_op
= O_secrel
;
26895 exp
.X_add_symbol
= symbol
;
26896 exp
.X_add_number
= 0;
26897 emit_expr (&exp
, size
);
26901 /* MD interface: Symbol and relocation handling. */
26903 /* Return the address within the segment that a PC-relative fixup is
26904 relative to. For ARM, PC-relative fixups applied to instructions
26905 are generally relative to the location of the fixup plus 8 bytes.
26906 Thumb branches are offset by 4, and Thumb loads relative to PC
26907 require special handling. */
26910 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26912 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26914 /* If this is pc-relative and we are going to emit a relocation
26915 then we just want to put out any pipeline compensation that the linker
26916 will need. Otherwise we want to use the calculated base.
26917 For WinCE we skip the bias for externals as well, since this
26918 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26920 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26921 || (arm_force_relocation (fixP
)
26923 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26929 switch (fixP
->fx_r_type
)
26931 /* PC relative addressing on the Thumb is slightly odd as the
26932 bottom two bits of the PC are forced to zero for the
26933 calculation. This happens *after* application of the
26934 pipeline offset. However, Thumb adrl already adjusts for
26935 this, so we need not do it again. */
26936 case BFD_RELOC_ARM_THUMB_ADD
:
26939 case BFD_RELOC_ARM_THUMB_OFFSET
:
26940 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26941 case BFD_RELOC_ARM_T32_ADD_PC12
:
26942 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26943 return (base
+ 4) & ~3;
26945 /* Thumb branches are simply offset by +4. */
26946 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26947 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26948 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26949 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26950 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26951 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26952 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26953 case BFD_RELOC_ARM_THUMB_BF17
:
26954 case BFD_RELOC_ARM_THUMB_BF19
:
26955 case BFD_RELOC_ARM_THUMB_BF13
:
26956 case BFD_RELOC_ARM_THUMB_LOOP12
:
26959 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26961 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26962 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26963 && ARM_IS_FUNC (fixP
->fx_addsy
)
26964 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26965 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26968 /* BLX is like branches above, but forces the low two bits of PC to
26970 case BFD_RELOC_THUMB_PCREL_BLX
:
26972 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26973 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26974 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26975 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26976 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26977 return (base
+ 4) & ~3;
26979 /* ARM mode branches are offset by +8. However, the Windows CE
26980 loader expects the relocation not to take this into account. */
26981 case BFD_RELOC_ARM_PCREL_BLX
:
26983 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26984 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26985 && ARM_IS_FUNC (fixP
->fx_addsy
)
26986 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26987 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26990 case BFD_RELOC_ARM_PCREL_CALL
:
26992 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26993 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26994 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26995 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26996 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26999 case BFD_RELOC_ARM_PCREL_BRANCH
:
27000 case BFD_RELOC_ARM_PCREL_JUMP
:
27001 case BFD_RELOC_ARM_PLT32
:
27003 /* When handling fixups immediately, because we have already
27004 discovered the value of a symbol, or the address of the frag involved
27005 we must account for the offset by +8, as the OS loader will never see the reloc.
27006 see fixup_segment() in write.c
27007 The S_IS_EXTERNAL test handles the case of global symbols.
27008 Those need the calculated base, not just the pipe compensation the linker will need. */
27010 && fixP
->fx_addsy
!= NULL
27011 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27012 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27020 /* ARM mode loads relative to PC are also offset by +8. Unlike
27021 branches, the Windows CE loader *does* expect the relocation
27022 to take this into account. */
27023 case BFD_RELOC_ARM_OFFSET_IMM
:
27024 case BFD_RELOC_ARM_OFFSET_IMM8
:
27025 case BFD_RELOC_ARM_HWLITERAL
:
27026 case BFD_RELOC_ARM_LITERAL
:
27027 case BFD_RELOC_ARM_CP_OFF_IMM
:
27031 /* Other PC-relative relocations are un-offset. */
27037 static bfd_boolean flag_warn_syms
= TRUE
;
27040 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27042 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27043 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27044 does mean that the resulting code might be very confusing to the reader.
27045 Also this warning can be triggered if the user omits an operand before
27046 an immediate address, eg:
27050 GAS treats this as an assignment of the value of the symbol foo to a
27051 symbol LDR, and so (without this code) it will not issue any kind of
27052 warning or error message.
27054 Note - ARM instructions are case-insensitive but the strings in the hash
27055 table are all stored in lower case, so we must first ensure that name is
27057 if (flag_warn_syms
&& arm_ops_hsh
)
27059 char * nbuf
= strdup (name
);
27062 for (p
= nbuf
; *p
; p
++)
27064 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27066 static struct hash_control
* already_warned
= NULL
;
27068 if (already_warned
== NULL
)
27069 already_warned
= hash_new ();
27070 /* Only warn about the symbol once. To keep the code
27071 simple we let hash_insert do the lookup for us. */
27072 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27073 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27082 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27083 Otherwise we have no need to default values of symbols. */
27086 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27089 if (name
[0] == '_' && name
[1] == 'G'
27090 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27094 if (symbol_find (name
))
27095 as_bad (_("GOT already in the symbol table"));
27097 GOT_symbol
= symbol_new (name
, undefined_section
,
27098 (valueT
) 0, & zero_address_frag
);
27108 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27109 computed as two separate immediate values, added together. We
27110 already know that this value cannot be computed by just one ARM
27113 static unsigned int
27114 validate_immediate_twopart (unsigned int val
,
27115 unsigned int * highpart
)
27120 for (i
= 0; i
< 32; i
+= 2)
27121 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27127 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27129 else if (a
& 0xff0000)
27131 if (a
& 0xff000000)
27133 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27137 gas_assert (a
& 0xff000000);
27138 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27141 return (a
& 0xff) | (i
<< 7);
27148 validate_offset_imm (unsigned int val
, int hwse
)
27150 if ((hwse
&& val
> 255) || val
> 4095)
27155 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27156 negative immediate constant by altering the instruction. A bit of
27161 by inverting the second operand, and
27164 by negating the second operand. */
27167 negate_data_op (unsigned long * instruction
,
27168 unsigned long value
)
27171 unsigned long negated
, inverted
;
27173 negated
= encode_arm_immediate (-value
);
27174 inverted
= encode_arm_immediate (~value
);
27176 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27179 /* First negates. */
27180 case OPCODE_SUB
: /* ADD <-> SUB */
27181 new_inst
= OPCODE_ADD
;
27186 new_inst
= OPCODE_SUB
;
27190 case OPCODE_CMP
: /* CMP <-> CMN */
27191 new_inst
= OPCODE_CMN
;
27196 new_inst
= OPCODE_CMP
;
27200 /* Now Inverted ops. */
27201 case OPCODE_MOV
: /* MOV <-> MVN */
27202 new_inst
= OPCODE_MVN
;
27207 new_inst
= OPCODE_MOV
;
27211 case OPCODE_AND
: /* AND <-> BIC */
27212 new_inst
= OPCODE_BIC
;
27217 new_inst
= OPCODE_AND
;
27221 case OPCODE_ADC
: /* ADC <-> SBC */
27222 new_inst
= OPCODE_SBC
;
27227 new_inst
= OPCODE_ADC
;
27231 /* We cannot do anything. */
27236 if (value
== (unsigned) FAIL
)
27239 *instruction
&= OPCODE_MASK
;
27240 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27244 /* Like negate_data_op, but for Thumb-2. */
27246 static unsigned int
27247 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27251 unsigned int negated
, inverted
;
27253 negated
= encode_thumb32_immediate (-value
);
27254 inverted
= encode_thumb32_immediate (~value
);
27256 rd
= (*instruction
>> 8) & 0xf;
27257 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27260 /* ADD <-> SUB. Includes CMP <-> CMN. */
27261 case T2_OPCODE_SUB
:
27262 new_inst
= T2_OPCODE_ADD
;
27266 case T2_OPCODE_ADD
:
27267 new_inst
= T2_OPCODE_SUB
;
27271 /* ORR <-> ORN. Includes MOV <-> MVN. */
27272 case T2_OPCODE_ORR
:
27273 new_inst
= T2_OPCODE_ORN
;
27277 case T2_OPCODE_ORN
:
27278 new_inst
= T2_OPCODE_ORR
;
27282 /* AND <-> BIC. TST has no inverted equivalent. */
27283 case T2_OPCODE_AND
:
27284 new_inst
= T2_OPCODE_BIC
;
27291 case T2_OPCODE_BIC
:
27292 new_inst
= T2_OPCODE_AND
;
27297 case T2_OPCODE_ADC
:
27298 new_inst
= T2_OPCODE_SBC
;
27302 case T2_OPCODE_SBC
:
27303 new_inst
= T2_OPCODE_ADC
;
27307 /* We cannot do anything. */
27312 if (value
== (unsigned int)FAIL
)
27315 *instruction
&= T2_OPCODE_MASK
;
27316 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27320 /* Read a 32-bit thumb instruction from buf. */
27322 static unsigned long
27323 get_thumb32_insn (char * buf
)
27325 unsigned long insn
;
27326 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27327 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27332 /* We usually want to set the low bit on the address of thumb function
27333 symbols. In particular .word foo - . should have the low bit set.
27334 Generic code tries to fold the difference of two symbols to
27335 a constant. Prevent this and force a relocation when the first symbols
27336 is a thumb function. */
27339 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27341 if (op
== O_subtract
27342 && l
->X_op
== O_symbol
27343 && r
->X_op
== O_symbol
27344 && THUMB_IS_FUNC (l
->X_add_symbol
))
27346 l
->X_op
= O_subtract
;
27347 l
->X_op_symbol
= r
->X_add_symbol
;
27348 l
->X_add_number
-= r
->X_add_number
;
27352 /* Process as normal. */
27356 /* Encode Thumb2 unconditional branches and calls. The encoding
27357 for the 2 are identical for the immediate values. */
27360 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27362 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27365 addressT S
, I1
, I2
, lo
, hi
;
27367 S
= (value
>> 24) & 0x01;
27368 I1
= (value
>> 23) & 0x01;
27369 I2
= (value
>> 22) & 0x01;
27370 hi
= (value
>> 12) & 0x3ff;
27371 lo
= (value
>> 1) & 0x7ff;
27372 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27373 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27374 newval
|= (S
<< 10) | hi
;
27375 newval2
&= ~T2I1I2MASK
;
27376 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27377 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27378 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27382 md_apply_fix (fixS
* fixP
,
27386 offsetT value
= * valP
;
27388 unsigned int newimm
;
27389 unsigned long temp
;
27391 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27393 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27395 /* Note whether this will delete the relocation. */
27397 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27400 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27401 consistency with the behaviour on 32-bit hosts. Remember value
27403 value
&= 0xffffffff;
27404 value
^= 0x80000000;
27405 value
-= 0x80000000;
27408 fixP
->fx_addnumber
= value
;
27410 /* Same treatment for fixP->fx_offset. */
27411 fixP
->fx_offset
&= 0xffffffff;
27412 fixP
->fx_offset
^= 0x80000000;
27413 fixP
->fx_offset
-= 0x80000000;
27415 switch (fixP
->fx_r_type
)
27417 case BFD_RELOC_NONE
:
27418 /* This will need to go in the object file. */
27422 case BFD_RELOC_ARM_IMMEDIATE
:
27423 /* We claim that this fixup has been processed here,
27424 even if in fact we generate an error because we do
27425 not have a reloc for it, so tc_gen_reloc will reject it. */
27428 if (fixP
->fx_addsy
)
27430 const char *msg
= 0;
27432 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27433 msg
= _("undefined symbol %s used as an immediate value");
27434 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27435 msg
= _("symbol %s is in a different section");
27436 else if (S_IS_WEAK (fixP
->fx_addsy
))
27437 msg
= _("symbol %s is weak and may be overridden later");
27441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27442 msg
, S_GET_NAME (fixP
->fx_addsy
));
27447 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27449 /* If the offset is negative, we should use encoding A2 for ADR. */
27450 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27451 newimm
= negate_data_op (&temp
, value
);
27454 newimm
= encode_arm_immediate (value
);
27456 /* If the instruction will fail, see if we can fix things up by
27457 changing the opcode. */
27458 if (newimm
== (unsigned int) FAIL
)
27459 newimm
= negate_data_op (&temp
, value
);
27460 /* MOV accepts both ARM modified immediate (A1 encoding) and
27461 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27462 When disassembling, MOV is preferred when there is no encoding
27464 if (newimm
== (unsigned int) FAIL
27465 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27466 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27467 && !((temp
>> SBIT_SHIFT
) & 0x1)
27468 && value
>= 0 && value
<= 0xffff)
27470 /* Clear bits[23:20] to change encoding from A1 to A2. */
27471 temp
&= 0xff0fffff;
27472 /* Encoding high 4bits imm. Code below will encode the remaining
27474 temp
|= (value
& 0x0000f000) << 4;
27475 newimm
= value
& 0x00000fff;
27479 if (newimm
== (unsigned int) FAIL
)
27481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27482 _("invalid constant (%lx) after fixup"),
27483 (unsigned long) value
);
27487 newimm
|= (temp
& 0xfffff000);
27488 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27491 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27493 unsigned int highpart
= 0;
27494 unsigned int newinsn
= 0xe1a00000; /* nop. */
27496 if (fixP
->fx_addsy
)
27498 const char *msg
= 0;
27500 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27501 msg
= _("undefined symbol %s used as an immediate value");
27502 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27503 msg
= _("symbol %s is in a different section");
27504 else if (S_IS_WEAK (fixP
->fx_addsy
))
27505 msg
= _("symbol %s is weak and may be overridden later");
27509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27510 msg
, S_GET_NAME (fixP
->fx_addsy
));
27515 newimm
= encode_arm_immediate (value
);
27516 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27518 /* If the instruction will fail, see if we can fix things up by
27519 changing the opcode. */
27520 if (newimm
== (unsigned int) FAIL
27521 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27523 /* No ? OK - try using two ADD instructions to generate
27525 newimm
= validate_immediate_twopart (value
, & highpart
);
27527 /* Yes - then make sure that the second instruction is
27529 if (newimm
!= (unsigned int) FAIL
)
27531 /* Still No ? Try using a negated value. */
27532 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27533 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27534 /* Otherwise - give up. */
27537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27538 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27543 /* Replace the first operand in the 2nd instruction (which
27544 is the PC) with the destination register. We have
27545 already added in the PC in the first instruction and we
27546 do not want to do it again. */
27547 newinsn
&= ~ 0xf0000;
27548 newinsn
|= ((newinsn
& 0x0f000) << 4);
27551 newimm
|= (temp
& 0xfffff000);
27552 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27554 highpart
|= (newinsn
& 0xfffff000);
27555 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27559 case BFD_RELOC_ARM_OFFSET_IMM
:
27560 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27562 /* Fall through. */
27564 case BFD_RELOC_ARM_LITERAL
:
27570 if (validate_offset_imm (value
, 0) == FAIL
)
27572 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27574 _("invalid literal constant: pool needs to be closer"));
27576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27577 _("bad immediate value for offset (%ld)"),
27582 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27584 newval
&= 0xfffff000;
27587 newval
&= 0xff7ff000;
27588 newval
|= value
| (sign
? INDEX_UP
: 0);
27590 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27593 case BFD_RELOC_ARM_OFFSET_IMM8
:
27594 case BFD_RELOC_ARM_HWLITERAL
:
27600 if (validate_offset_imm (value
, 1) == FAIL
)
27602 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27604 _("invalid literal constant: pool needs to be closer"));
27606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27607 _("bad immediate value for 8-bit offset (%ld)"),
27612 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27614 newval
&= 0xfffff0f0;
27617 newval
&= 0xff7ff0f0;
27618 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27620 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27623 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27624 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27626 _("bad immediate value for offset (%ld)"), (long) value
);
27629 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27631 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27634 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27635 /* This is a complicated relocation used for all varieties of Thumb32
27636 load/store instruction with immediate offset:
27638 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27639 *4, optional writeback(W)
27640 (doubleword load/store)
27642 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27643 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27644 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27645 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27646 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27648 Uppercase letters indicate bits that are already encoded at
27649 this point. Lowercase letters are our problem. For the
27650 second block of instructions, the secondary opcode nybble
27651 (bits 8..11) is present, and bit 23 is zero, even if this is
27652 a PC-relative operation. */
27653 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27655 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27657 if ((newval
& 0xf0000000) == 0xe0000000)
27659 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27661 newval
|= (1 << 23);
27664 if (value
% 4 != 0)
27666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27667 _("offset not a multiple of 4"));
27673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27674 _("offset out of range"));
27679 else if ((newval
& 0x000f0000) == 0x000f0000)
27681 /* PC-relative, 12-bit offset. */
27683 newval
|= (1 << 23);
27688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27689 _("offset out of range"));
27694 else if ((newval
& 0x00000100) == 0x00000100)
27696 /* Writeback: 8-bit, +/- offset. */
27698 newval
|= (1 << 9);
27703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27704 _("offset out of range"));
27709 else if ((newval
& 0x00000f00) == 0x00000e00)
27711 /* T-instruction: positive 8-bit offset. */
27712 if (value
< 0 || value
> 0xff)
27714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27715 _("offset out of range"));
27723 /* Positive 12-bit or negative 8-bit offset. */
27727 newval
|= (1 << 23);
27737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27738 _("offset out of range"));
27745 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27746 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27749 case BFD_RELOC_ARM_SHIFT_IMM
:
27750 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27751 if (((unsigned long) value
) > 32
27753 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27756 _("shift expression is too large"));
27761 /* Shifts of zero must be done as lsl. */
27763 else if (value
== 32)
27765 newval
&= 0xfffff07f;
27766 newval
|= (value
& 0x1f) << 7;
27767 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27770 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27771 case BFD_RELOC_ARM_T32_ADD_IMM
:
27772 case BFD_RELOC_ARM_T32_IMM12
:
27773 case BFD_RELOC_ARM_T32_ADD_PC12
:
27774 /* We claim that this fixup has been processed here,
27775 even if in fact we generate an error because we do
27776 not have a reloc for it, so tc_gen_reloc will reject it. */
27780 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27783 _("undefined symbol %s used as an immediate value"),
27784 S_GET_NAME (fixP
->fx_addsy
));
27788 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27790 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27793 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27794 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27795 Thumb2 modified immediate encoding (T2). */
27796 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27797 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27799 newimm
= encode_thumb32_immediate (value
);
27800 if (newimm
== (unsigned int) FAIL
)
27801 newimm
= thumb32_negate_data_op (&newval
, value
);
27803 if (newimm
== (unsigned int) FAIL
)
27805 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27807 /* Turn add/sum into addw/subw. */
27808 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27809 newval
= (newval
& 0xfeffffff) | 0x02000000;
27810 /* No flat 12-bit imm encoding for addsw/subsw. */
27811 if ((newval
& 0x00100000) == 0)
27813 /* 12 bit immediate for addw/subw. */
27817 newval
^= 0x00a00000;
27820 newimm
= (unsigned int) FAIL
;
27827 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27828 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27829 disassembling, MOV is preferred when there is no encoding
27831 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27832 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27833 but with the Rn field [19:16] set to 1111. */
27834 && (((newval
>> 16) & 0xf) == 0xf)
27835 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27836 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27837 && value
>= 0 && value
<= 0xffff)
27839 /* Toggle bit[25] to change encoding from T2 to T3. */
27841 /* Clear bits[19:16]. */
27842 newval
&= 0xfff0ffff;
27843 /* Encoding high 4bits imm. Code below will encode the
27844 remaining low 12bits. */
27845 newval
|= (value
& 0x0000f000) << 4;
27846 newimm
= value
& 0x00000fff;
27851 if (newimm
== (unsigned int)FAIL
)
27853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27854 _("invalid constant (%lx) after fixup"),
27855 (unsigned long) value
);
27859 newval
|= (newimm
& 0x800) << 15;
27860 newval
|= (newimm
& 0x700) << 4;
27861 newval
|= (newimm
& 0x0ff);
27863 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27864 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27867 case BFD_RELOC_ARM_SMC
:
27868 if (((unsigned long) value
) > 0xf)
27869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27870 _("invalid smc expression"));
27872 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27873 newval
|= (value
& 0xf);
27874 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27877 case BFD_RELOC_ARM_HVC
:
27878 if (((unsigned long) value
) > 0xffff)
27879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27880 _("invalid hvc expression"));
27881 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27882 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27883 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27886 case BFD_RELOC_ARM_SWI
:
27887 if (fixP
->tc_fix_data
!= 0)
27889 if (((unsigned long) value
) > 0xff)
27890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27891 _("invalid swi expression"));
27892 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27894 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27898 if (((unsigned long) value
) > 0x00ffffff)
27899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27900 _("invalid swi expression"));
27901 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27903 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27907 case BFD_RELOC_ARM_MULTI
:
27908 if (((unsigned long) value
) > 0xffff)
27909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27910 _("invalid expression in load/store multiple"));
27911 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27912 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27916 case BFD_RELOC_ARM_PCREL_CALL
:
27918 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27920 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27921 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27922 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27923 /* Flip the bl to blx. This is a simple flip
27924 bit here because we generate PCREL_CALL for
27925 unconditional bls. */
27927 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27928 newval
= newval
| 0x10000000;
27929 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27935 goto arm_branch_common
;
27937 case BFD_RELOC_ARM_PCREL_JUMP
:
27938 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27940 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27941 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27942 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27944 /* This would map to a bl<cond>, b<cond>,
27945 b<always> to a Thumb function. We
27946 need to force a relocation for this particular
27948 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27951 /* Fall through. */
27953 case BFD_RELOC_ARM_PLT32
:
27955 case BFD_RELOC_ARM_PCREL_BRANCH
:
27957 goto arm_branch_common
;
27959 case BFD_RELOC_ARM_PCREL_BLX
:
27962 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27964 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27965 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27966 && ARM_IS_FUNC (fixP
->fx_addsy
))
27968 /* Flip the blx to a bl and warn. */
27969 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27970 newval
= 0xeb000000;
27971 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27972 _("blx to '%s' an ARM ISA state function changed to bl"),
27974 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27980 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27981 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27985 /* We are going to store value (shifted right by two) in the
27986 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27987 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27991 _("misaligned branch destination"));
27992 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27993 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27996 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27998 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27999 newval
|= (value
>> 2) & 0x00ffffff;
28000 /* Set the H bit on BLX instructions. */
28004 newval
|= 0x01000000;
28006 newval
&= ~0x01000000;
28008 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28012 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28013 /* CBZ can only branch forward. */
28015 /* Attempts to use CBZ to branch to the next instruction
28016 (which, strictly speaking, are prohibited) will be turned into
28019 FIXME: It may be better to remove the instruction completely and
28020 perform relaxation. */
28023 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28024 newval
= 0xbf00; /* NOP encoding T1 */
28025 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28032 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28034 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28035 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28036 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28041 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28042 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
28043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28045 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28048 newval
|= (value
& 0x1ff) >> 1;
28049 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28053 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28054 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
28055 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28057 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28059 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28060 newval
|= (value
& 0xfff) >> 1;
28061 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28065 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28067 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28068 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28069 && ARM_IS_FUNC (fixP
->fx_addsy
)
28070 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28072 /* Force a relocation for a branch 20 bits wide. */
28075 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
28076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28077 _("conditional branch out of range"));
28079 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28082 addressT S
, J1
, J2
, lo
, hi
;
28084 S
= (value
& 0x00100000) >> 20;
28085 J2
= (value
& 0x00080000) >> 19;
28086 J1
= (value
& 0x00040000) >> 18;
28087 hi
= (value
& 0x0003f000) >> 12;
28088 lo
= (value
& 0x00000ffe) >> 1;
28090 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28091 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28092 newval
|= (S
<< 10) | hi
;
28093 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28094 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28095 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28099 case BFD_RELOC_THUMB_PCREL_BLX
:
28100 /* If there is a blx from a thumb state function to
28101 another thumb function flip this to a bl and warn
28105 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28106 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28107 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28109 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28110 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28111 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28113 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28114 newval
= newval
| 0x1000;
28115 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28116 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28121 goto thumb_bl_common
;
28123 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28124 /* A bl from Thumb state ISA to an internal ARM state function
28125 is converted to a blx. */
28127 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28128 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28129 && ARM_IS_FUNC (fixP
->fx_addsy
)
28130 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28132 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28133 newval
= newval
& ~0x1000;
28134 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28135 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28141 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28142 /* For a BLX instruction, make sure that the relocation is rounded up
28143 to a word boundary. This follows the semantics of the instruction
28144 which specifies that bit 1 of the target address will come from bit
28145 1 of the base address. */
28146 value
= (value
+ 3) & ~ 3;
28149 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28150 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28151 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28154 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
28156 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28158 else if ((value
& ~0x1ffffff)
28159 && ((value
& ~0x1ffffff) != ~0x1ffffff))
28160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28161 _("Thumb2 branch out of range"));
28164 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28165 encode_thumb2_b_bl_offset (buf
, value
);
28169 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28170 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
28171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28174 encode_thumb2_b_bl_offset (buf
, value
);
28179 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28184 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28185 md_number_to_chars (buf
, value
, 2);
28189 case BFD_RELOC_ARM_TLS_CALL
:
28190 case BFD_RELOC_ARM_THM_TLS_CALL
:
28191 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28192 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28193 case BFD_RELOC_ARM_TLS_GOTDESC
:
28194 case BFD_RELOC_ARM_TLS_GD32
:
28195 case BFD_RELOC_ARM_TLS_LE32
:
28196 case BFD_RELOC_ARM_TLS_IE32
:
28197 case BFD_RELOC_ARM_TLS_LDM32
:
28198 case BFD_RELOC_ARM_TLS_LDO32
:
28199 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28202 /* Same handling as above, but with the arm_fdpic guard. */
28203 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28204 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28205 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28208 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28213 _("Relocation supported only in FDPIC mode"));
28217 case BFD_RELOC_ARM_GOT32
:
28218 case BFD_RELOC_ARM_GOTOFF
:
28221 case BFD_RELOC_ARM_GOT_PREL
:
28222 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28223 md_number_to_chars (buf
, value
, 4);
28226 case BFD_RELOC_ARM_TARGET2
:
28227 /* TARGET2 is not partial-inplace, so we need to write the
28228 addend here for REL targets, because it won't be written out
28229 during reloc processing later. */
28230 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28231 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28234 /* Relocations for FDPIC. */
28235 case BFD_RELOC_ARM_GOTFUNCDESC
:
28236 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28237 case BFD_RELOC_ARM_FUNCDESC
:
28240 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28241 md_number_to_chars (buf
, 0, 4);
28245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28246 _("Relocation supported only in FDPIC mode"));
28251 case BFD_RELOC_RVA
:
28253 case BFD_RELOC_ARM_TARGET1
:
28254 case BFD_RELOC_ARM_ROSEGREL32
:
28255 case BFD_RELOC_ARM_SBREL32
:
28256 case BFD_RELOC_32_PCREL
:
28258 case BFD_RELOC_32_SECREL
:
28260 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28262 /* For WinCE we only do this for pcrel fixups. */
28263 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28265 md_number_to_chars (buf
, value
, 4);
28269 case BFD_RELOC_ARM_PREL31
:
28270 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28272 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28273 if ((value
^ (value
>> 1)) & 0x40000000)
28275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28276 _("rel31 relocation overflow"));
28278 newval
|= value
& 0x7fffffff;
28279 md_number_to_chars (buf
, newval
, 4);
28284 case BFD_RELOC_ARM_CP_OFF_IMM
:
28285 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28286 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28287 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28288 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28290 newval
= get_thumb32_insn (buf
);
28291 if ((newval
& 0x0f200f00) == 0x0d000900)
28293 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28294 has permitted values that are multiples of 2, in the range 0
28296 if (value
< -510 || value
> 510 || (value
& 1))
28297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28298 _("co-processor offset out of range"));
28300 else if ((newval
& 0xfe001f80) == 0xec000f80)
28302 if (value
< -511 || value
> 512 || (value
& 3))
28303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28304 _("co-processor offset out of range"));
28306 else if (value
< -1023 || value
> 1023 || (value
& 3))
28307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28308 _("co-processor offset out of range"));
28313 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28314 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28315 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28317 newval
= get_thumb32_insn (buf
);
28320 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28321 newval
&= 0xffffff80;
28323 newval
&= 0xffffff00;
28327 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28328 newval
&= 0xff7fff80;
28330 newval
&= 0xff7fff00;
28331 if ((newval
& 0x0f200f00) == 0x0d000900)
28333 /* This is a fp16 vstr/vldr.
28335 It requires the immediate offset in the instruction is shifted
28336 left by 1 to be a half-word offset.
28338 Here, left shift by 1 first, and later right shift by 2
28339 should get the right offset. */
28342 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28344 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28345 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28346 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28348 put_thumb32_insn (buf
, newval
);
28351 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28352 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28353 if (value
< -255 || value
> 255)
28354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28355 _("co-processor offset out of range"));
28357 goto cp_off_common
;
28359 case BFD_RELOC_ARM_THUMB_OFFSET
:
28360 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28361 /* Exactly what ranges, and where the offset is inserted depends
28362 on the type of instruction, we can establish this from the
28364 switch (newval
>> 12)
28366 case 4: /* PC load. */
28367 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28368 forced to zero for these loads; md_pcrel_from has already
28369 compensated for this. */
28371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28372 _("invalid offset, target not word aligned (0x%08lX)"),
28373 (((unsigned long) fixP
->fx_frag
->fr_address
28374 + (unsigned long) fixP
->fx_where
) & ~3)
28375 + (unsigned long) value
);
28377 if (value
& ~0x3fc)
28378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28379 _("invalid offset, value too big (0x%08lX)"),
28382 newval
|= value
>> 2;
28385 case 9: /* SP load/store. */
28386 if (value
& ~0x3fc)
28387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28388 _("invalid offset, value too big (0x%08lX)"),
28390 newval
|= value
>> 2;
28393 case 6: /* Word load/store. */
28395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28396 _("invalid offset, value too big (0x%08lX)"),
28398 newval
|= value
<< 4; /* 6 - 2. */
28401 case 7: /* Byte load/store. */
28403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28404 _("invalid offset, value too big (0x%08lX)"),
28406 newval
|= value
<< 6;
28409 case 8: /* Halfword load/store. */
28411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28412 _("invalid offset, value too big (0x%08lX)"),
28414 newval
|= value
<< 5; /* 6 - 1. */
28418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28419 "Unable to process relocation for thumb opcode: %lx",
28420 (unsigned long) newval
);
28423 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28426 case BFD_RELOC_ARM_THUMB_ADD
:
28427 /* This is a complicated relocation, since we use it for all of
28428 the following immediate relocations:
28432 9bit ADD/SUB SP word-aligned
28433 10bit ADD PC/SP word-aligned
28435 The type of instruction being processed is encoded in the
28442 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28444 int rd
= (newval
>> 4) & 0xf;
28445 int rs
= newval
& 0xf;
28446 int subtract
= !!(newval
& 0x8000);
28448 /* Check for HI regs, only very restricted cases allowed:
28449 Adjusting SP, and using PC or SP to get an address. */
28450 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28451 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28453 _("invalid Hi register with immediate"));
28455 /* If value is negative, choose the opposite instruction. */
28459 subtract
= !subtract
;
28461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28462 _("immediate value out of range"));
28467 if (value
& ~0x1fc)
28468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28469 _("invalid immediate for stack address calculation"));
28470 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28471 newval
|= value
>> 2;
28473 else if (rs
== REG_PC
|| rs
== REG_SP
)
28475 /* PR gas/18541. If the addition is for a defined symbol
28476 within range of an ADR instruction then accept it. */
28479 && fixP
->fx_addsy
!= NULL
)
28483 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28484 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28485 || S_IS_WEAK (fixP
->fx_addsy
))
28487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28488 _("address calculation needs a strongly defined nearby symbol"));
28492 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28494 /* Round up to the next 4-byte boundary. */
28499 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28504 _("symbol too far away"));
28514 if (subtract
|| value
& ~0x3fc)
28515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28516 _("invalid immediate for address calculation (value = 0x%08lX)"),
28517 (unsigned long) (subtract
? - value
: value
));
28518 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28520 newval
|= value
>> 2;
28525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28526 _("immediate value out of range"));
28527 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28528 newval
|= (rd
<< 8) | value
;
28533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28534 _("immediate value out of range"));
28535 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28536 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28539 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28542 case BFD_RELOC_ARM_THUMB_IMM
:
28543 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28544 if (value
< 0 || value
> 255)
28545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28546 _("invalid immediate: %ld is out of range"),
28549 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28552 case BFD_RELOC_ARM_THUMB_SHIFT
:
28553 /* 5bit shift value (0..32). LSL cannot take 32. */
28554 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28555 temp
= newval
& 0xf800;
28556 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28558 _("invalid shift value: %ld"), (long) value
);
28559 /* Shifts of zero must be encoded as LSL. */
28561 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28562 /* Shifts of 32 are encoded as zero. */
28563 else if (value
== 32)
28565 newval
|= value
<< 6;
28566 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28569 case BFD_RELOC_VTABLE_INHERIT
:
28570 case BFD_RELOC_VTABLE_ENTRY
:
28574 case BFD_RELOC_ARM_MOVW
:
28575 case BFD_RELOC_ARM_MOVT
:
28576 case BFD_RELOC_ARM_THUMB_MOVW
:
28577 case BFD_RELOC_ARM_THUMB_MOVT
:
28578 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28580 /* REL format relocations are limited to a 16-bit addend. */
28581 if (!fixP
->fx_done
)
28583 if (value
< -0x8000 || value
> 0x7fff)
28584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28585 _("offset out of range"));
28587 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28588 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28593 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28594 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28596 newval
= get_thumb32_insn (buf
);
28597 newval
&= 0xfbf08f00;
28598 newval
|= (value
& 0xf000) << 4;
28599 newval
|= (value
& 0x0800) << 15;
28600 newval
|= (value
& 0x0700) << 4;
28601 newval
|= (value
& 0x00ff);
28602 put_thumb32_insn (buf
, newval
);
28606 newval
= md_chars_to_number (buf
, 4);
28607 newval
&= 0xfff0f000;
28608 newval
|= value
& 0x0fff;
28609 newval
|= (value
& 0xf000) << 4;
28610 md_number_to_chars (buf
, newval
, 4);
28615 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28616 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28617 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28618 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28619 gas_assert (!fixP
->fx_done
);
28622 bfd_boolean is_mov
;
28623 bfd_vma encoded_addend
= value
;
28625 /* Check that addend can be encoded in instruction. */
28626 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28628 _("the offset 0x%08lX is not representable"),
28629 (unsigned long) encoded_addend
);
28631 /* Extract the instruction. */
28632 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28633 is_mov
= (insn
& 0xf800) == 0x2000;
28638 if (!seg
->use_rela_p
)
28639 insn
|= encoded_addend
;
28645 /* Extract the instruction. */
28646 /* Encoding is the following
28651 /* The following conditions must be true :
28656 rd
= (insn
>> 4) & 0xf;
28658 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28660 _("Unable to process relocation for thumb opcode: %lx"),
28661 (unsigned long) insn
);
28663 /* Encode as ADD immediate8 thumb 1 code. */
28664 insn
= 0x3000 | (rd
<< 8);
28666 /* Place the encoded addend into the first 8 bits of the
28668 if (!seg
->use_rela_p
)
28669 insn
|= encoded_addend
;
28672 /* Update the instruction. */
28673 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28677 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28678 case BFD_RELOC_ARM_ALU_PC_G0
:
28679 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28680 case BFD_RELOC_ARM_ALU_PC_G1
:
28681 case BFD_RELOC_ARM_ALU_PC_G2
:
28682 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28683 case BFD_RELOC_ARM_ALU_SB_G0
:
28684 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28685 case BFD_RELOC_ARM_ALU_SB_G1
:
28686 case BFD_RELOC_ARM_ALU_SB_G2
:
28687 gas_assert (!fixP
->fx_done
);
28688 if (!seg
->use_rela_p
)
28691 bfd_vma encoded_addend
;
28692 bfd_vma addend_abs
= llabs (value
);
28694 /* Check that the absolute value of the addend can be
28695 expressed as an 8-bit constant plus a rotation. */
28696 encoded_addend
= encode_arm_immediate (addend_abs
);
28697 if (encoded_addend
== (unsigned int) FAIL
)
28698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28699 _("the offset 0x%08lX is not representable"),
28700 (unsigned long) addend_abs
);
28702 /* Extract the instruction. */
28703 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28705 /* If the addend is positive, use an ADD instruction.
28706 Otherwise use a SUB. Take care not to destroy the S bit. */
28707 insn
&= 0xff1fffff;
28713 /* Place the encoded addend into the first 12 bits of the
28715 insn
&= 0xfffff000;
28716 insn
|= encoded_addend
;
28718 /* Update the instruction. */
28719 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28723 case BFD_RELOC_ARM_LDR_PC_G0
:
28724 case BFD_RELOC_ARM_LDR_PC_G1
:
28725 case BFD_RELOC_ARM_LDR_PC_G2
:
28726 case BFD_RELOC_ARM_LDR_SB_G0
:
28727 case BFD_RELOC_ARM_LDR_SB_G1
:
28728 case BFD_RELOC_ARM_LDR_SB_G2
:
28729 gas_assert (!fixP
->fx_done
);
28730 if (!seg
->use_rela_p
)
28733 bfd_vma addend_abs
= llabs (value
);
28735 /* Check that the absolute value of the addend can be
28736 encoded in 12 bits. */
28737 if (addend_abs
>= 0x1000)
28738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28739 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28740 (unsigned long) addend_abs
);
28742 /* Extract the instruction. */
28743 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28745 /* If the addend is negative, clear bit 23 of the instruction.
28746 Otherwise set it. */
28748 insn
&= ~(1 << 23);
28752 /* Place the absolute value of the addend into the first 12 bits
28753 of the instruction. */
28754 insn
&= 0xfffff000;
28755 insn
|= addend_abs
;
28757 /* Update the instruction. */
28758 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28762 case BFD_RELOC_ARM_LDRS_PC_G0
:
28763 case BFD_RELOC_ARM_LDRS_PC_G1
:
28764 case BFD_RELOC_ARM_LDRS_PC_G2
:
28765 case BFD_RELOC_ARM_LDRS_SB_G0
:
28766 case BFD_RELOC_ARM_LDRS_SB_G1
:
28767 case BFD_RELOC_ARM_LDRS_SB_G2
:
28768 gas_assert (!fixP
->fx_done
);
28769 if (!seg
->use_rela_p
)
28772 bfd_vma addend_abs
= llabs (value
);
28774 /* Check that the absolute value of the addend can be
28775 encoded in 8 bits. */
28776 if (addend_abs
>= 0x100)
28777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28778 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28779 (unsigned long) addend_abs
);
28781 /* Extract the instruction. */
28782 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28784 /* If the addend is negative, clear bit 23 of the instruction.
28785 Otherwise set it. */
28787 insn
&= ~(1 << 23);
28791 /* Place the first four bits of the absolute value of the addend
28792 into the first 4 bits of the instruction, and the remaining
28793 four into bits 8 .. 11. */
28794 insn
&= 0xfffff0f0;
28795 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28797 /* Update the instruction. */
28798 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28802 case BFD_RELOC_ARM_LDC_PC_G0
:
28803 case BFD_RELOC_ARM_LDC_PC_G1
:
28804 case BFD_RELOC_ARM_LDC_PC_G2
:
28805 case BFD_RELOC_ARM_LDC_SB_G0
:
28806 case BFD_RELOC_ARM_LDC_SB_G1
:
28807 case BFD_RELOC_ARM_LDC_SB_G2
:
28808 gas_assert (!fixP
->fx_done
);
28809 if (!seg
->use_rela_p
)
28812 bfd_vma addend_abs
= llabs (value
);
28814 /* Check that the absolute value of the addend is a multiple of
28815 four and, when divided by four, fits in 8 bits. */
28816 if (addend_abs
& 0x3)
28817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28818 _("bad offset 0x%08lX (must be word-aligned)"),
28819 (unsigned long) addend_abs
);
28821 if ((addend_abs
>> 2) > 0xff)
28822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28823 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28824 (unsigned long) addend_abs
);
28826 /* Extract the instruction. */
28827 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28829 /* If the addend is negative, clear bit 23 of the instruction.
28830 Otherwise set it. */
28832 insn
&= ~(1 << 23);
28836 /* Place the addend (divided by four) into the first eight
28837 bits of the instruction. */
28838 insn
&= 0xfffffff0;
28839 insn
|= addend_abs
>> 2;
28841 /* Update the instruction. */
28842 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28846 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28848 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28849 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28850 && ARM_IS_FUNC (fixP
->fx_addsy
)
28851 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28853 /* Force a relocation for a branch 5 bits wide. */
28856 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28862 addressT boff
= value
>> 1;
28864 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28865 newval
|= (boff
<< 7);
28866 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28870 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28872 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28873 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28874 && ARM_IS_FUNC (fixP
->fx_addsy
)
28875 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28879 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28881 _("branch out of range"));
28883 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28885 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28887 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28888 addressT diff
= value
- boff
;
28892 newval
|= 1 << 1; /* T bit. */
28894 else if (diff
!= 2)
28896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28897 _("out of range label-relative fixup value"));
28899 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28903 case BFD_RELOC_ARM_THUMB_BF17
:
28905 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28906 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28907 && ARM_IS_FUNC (fixP
->fx_addsy
)
28908 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28910 /* Force a relocation for a branch 17 bits wide. */
28914 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28918 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28921 addressT immA
, immB
, immC
;
28923 immA
= (value
& 0x0001f000) >> 12;
28924 immB
= (value
& 0x00000ffc) >> 2;
28925 immC
= (value
& 0x00000002) >> 1;
28927 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28928 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28930 newval2
|= (immC
<< 11) | (immB
<< 1);
28931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28932 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28936 case BFD_RELOC_ARM_THUMB_BF19
:
28938 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28939 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28940 && ARM_IS_FUNC (fixP
->fx_addsy
)
28941 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28943 /* Force a relocation for a branch 19 bits wide. */
28947 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28951 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28954 addressT immA
, immB
, immC
;
28956 immA
= (value
& 0x0007f000) >> 12;
28957 immB
= (value
& 0x00000ffc) >> 2;
28958 immC
= (value
& 0x00000002) >> 1;
28960 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28961 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28963 newval2
|= (immC
<< 11) | (immB
<< 1);
28964 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28965 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28969 case BFD_RELOC_ARM_THUMB_BF13
:
28971 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28972 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28973 && ARM_IS_FUNC (fixP
->fx_addsy
)
28974 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28976 /* Force a relocation for a branch 13 bits wide. */
28980 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28984 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28987 addressT immA
, immB
, immC
;
28989 immA
= (value
& 0x00001000) >> 12;
28990 immB
= (value
& 0x00000ffc) >> 2;
28991 immC
= (value
& 0x00000002) >> 1;
28993 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28994 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28996 newval2
|= (immC
<< 11) | (immB
<< 1);
28997 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28998 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29002 case BFD_RELOC_ARM_THUMB_LOOP12
:
29004 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29005 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29006 && ARM_IS_FUNC (fixP
->fx_addsy
)
29007 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29009 /* Force a relocation for a branch 12 bits wide. */
29013 bfd_vma insn
= get_thumb32_insn (buf
);
29014 /* le lr, <label>, le <label> or letp lr, <label> */
29015 if (((insn
& 0xffffffff) == 0xf00fc001)
29016 || ((insn
& 0xffffffff) == 0xf02fc001)
29017 || ((insn
& 0xffffffff) == 0xf01fc001))
29020 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29025 addressT imml
, immh
;
29027 immh
= (value
& 0x00000ffc) >> 2;
29028 imml
= (value
& 0x00000002) >> 1;
29030 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29031 newval
|= (imml
<< 11) | (immh
<< 1);
29032 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29036 case BFD_RELOC_ARM_V4BX
:
29037 /* This will need to go in the object file. */
29041 case BFD_RELOC_UNUSED
:
29043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29044 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29048 /* Translate internal representation of relocation info to BFD target
29052 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29055 bfd_reloc_code_real_type code
;
29057 reloc
= XNEW (arelent
);
29059 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29060 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29061 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29063 if (fixp
->fx_pcrel
)
29065 if (section
->use_rela_p
)
29066 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29068 fixp
->fx_offset
= reloc
->address
;
29070 reloc
->addend
= fixp
->fx_offset
;
29072 switch (fixp
->fx_r_type
)
29075 if (fixp
->fx_pcrel
)
29077 code
= BFD_RELOC_8_PCREL
;
29080 /* Fall through. */
29083 if (fixp
->fx_pcrel
)
29085 code
= BFD_RELOC_16_PCREL
;
29088 /* Fall through. */
29091 if (fixp
->fx_pcrel
)
29093 code
= BFD_RELOC_32_PCREL
;
29096 /* Fall through. */
29098 case BFD_RELOC_ARM_MOVW
:
29099 if (fixp
->fx_pcrel
)
29101 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29104 /* Fall through. */
29106 case BFD_RELOC_ARM_MOVT
:
29107 if (fixp
->fx_pcrel
)
29109 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29112 /* Fall through. */
29114 case BFD_RELOC_ARM_THUMB_MOVW
:
29115 if (fixp
->fx_pcrel
)
29117 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29120 /* Fall through. */
29122 case BFD_RELOC_ARM_THUMB_MOVT
:
29123 if (fixp
->fx_pcrel
)
29125 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29128 /* Fall through. */
29130 case BFD_RELOC_NONE
:
29131 case BFD_RELOC_ARM_PCREL_BRANCH
:
29132 case BFD_RELOC_ARM_PCREL_BLX
:
29133 case BFD_RELOC_RVA
:
29134 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29135 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29136 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29137 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29138 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29139 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29140 case BFD_RELOC_VTABLE_ENTRY
:
29141 case BFD_RELOC_VTABLE_INHERIT
:
29143 case BFD_RELOC_32_SECREL
:
29145 code
= fixp
->fx_r_type
;
29148 case BFD_RELOC_THUMB_PCREL_BLX
:
29150 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29151 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29154 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29157 case BFD_RELOC_ARM_LITERAL
:
29158 case BFD_RELOC_ARM_HWLITERAL
:
29159 /* If this is called then the a literal has
29160 been referenced across a section boundary. */
29161 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29162 _("literal referenced across section boundary"));
29166 case BFD_RELOC_ARM_TLS_CALL
:
29167 case BFD_RELOC_ARM_THM_TLS_CALL
:
29168 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29169 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29170 case BFD_RELOC_ARM_GOT32
:
29171 case BFD_RELOC_ARM_GOTOFF
:
29172 case BFD_RELOC_ARM_GOT_PREL
:
29173 case BFD_RELOC_ARM_PLT32
:
29174 case BFD_RELOC_ARM_TARGET1
:
29175 case BFD_RELOC_ARM_ROSEGREL32
:
29176 case BFD_RELOC_ARM_SBREL32
:
29177 case BFD_RELOC_ARM_PREL31
:
29178 case BFD_RELOC_ARM_TARGET2
:
29179 case BFD_RELOC_ARM_TLS_LDO32
:
29180 case BFD_RELOC_ARM_PCREL_CALL
:
29181 case BFD_RELOC_ARM_PCREL_JUMP
:
29182 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29183 case BFD_RELOC_ARM_ALU_PC_G0
:
29184 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29185 case BFD_RELOC_ARM_ALU_PC_G1
:
29186 case BFD_RELOC_ARM_ALU_PC_G2
:
29187 case BFD_RELOC_ARM_LDR_PC_G0
:
29188 case BFD_RELOC_ARM_LDR_PC_G1
:
29189 case BFD_RELOC_ARM_LDR_PC_G2
:
29190 case BFD_RELOC_ARM_LDRS_PC_G0
:
29191 case BFD_RELOC_ARM_LDRS_PC_G1
:
29192 case BFD_RELOC_ARM_LDRS_PC_G2
:
29193 case BFD_RELOC_ARM_LDC_PC_G0
:
29194 case BFD_RELOC_ARM_LDC_PC_G1
:
29195 case BFD_RELOC_ARM_LDC_PC_G2
:
29196 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29197 case BFD_RELOC_ARM_ALU_SB_G0
:
29198 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29199 case BFD_RELOC_ARM_ALU_SB_G1
:
29200 case BFD_RELOC_ARM_ALU_SB_G2
:
29201 case BFD_RELOC_ARM_LDR_SB_G0
:
29202 case BFD_RELOC_ARM_LDR_SB_G1
:
29203 case BFD_RELOC_ARM_LDR_SB_G2
:
29204 case BFD_RELOC_ARM_LDRS_SB_G0
:
29205 case BFD_RELOC_ARM_LDRS_SB_G1
:
29206 case BFD_RELOC_ARM_LDRS_SB_G2
:
29207 case BFD_RELOC_ARM_LDC_SB_G0
:
29208 case BFD_RELOC_ARM_LDC_SB_G1
:
29209 case BFD_RELOC_ARM_LDC_SB_G2
:
29210 case BFD_RELOC_ARM_V4BX
:
29211 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29212 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29213 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29214 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29215 case BFD_RELOC_ARM_GOTFUNCDESC
:
29216 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29217 case BFD_RELOC_ARM_FUNCDESC
:
29218 case BFD_RELOC_ARM_THUMB_BF17
:
29219 case BFD_RELOC_ARM_THUMB_BF19
:
29220 case BFD_RELOC_ARM_THUMB_BF13
:
29221 code
= fixp
->fx_r_type
;
29224 case BFD_RELOC_ARM_TLS_GOTDESC
:
29225 case BFD_RELOC_ARM_TLS_GD32
:
29226 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29227 case BFD_RELOC_ARM_TLS_LE32
:
29228 case BFD_RELOC_ARM_TLS_IE32
:
29229 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29230 case BFD_RELOC_ARM_TLS_LDM32
:
29231 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29232 /* BFD will include the symbol's address in the addend.
29233 But we don't want that, so subtract it out again here. */
29234 if (!S_IS_COMMON (fixp
->fx_addsy
))
29235 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29236 code
= fixp
->fx_r_type
;
29240 case BFD_RELOC_ARM_IMMEDIATE
:
29241 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29242 _("internal relocation (type: IMMEDIATE) not fixed up"));
29245 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29246 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29247 _("ADRL used for a symbol not defined in the same file"));
29250 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29251 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29252 case BFD_RELOC_ARM_THUMB_LOOP12
:
29253 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29254 _("%s used for a symbol not defined in the same file"),
29255 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29258 case BFD_RELOC_ARM_OFFSET_IMM
:
29259 if (section
->use_rela_p
)
29261 code
= fixp
->fx_r_type
;
29265 if (fixp
->fx_addsy
!= NULL
29266 && !S_IS_DEFINED (fixp
->fx_addsy
)
29267 && S_IS_LOCAL (fixp
->fx_addsy
))
29269 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29270 _("undefined local label `%s'"),
29271 S_GET_NAME (fixp
->fx_addsy
));
29275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29276 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29283 switch (fixp
->fx_r_type
)
29285 case BFD_RELOC_NONE
: type
= "NONE"; break;
29286 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29287 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29288 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29289 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29290 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29291 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29292 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29293 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29294 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29295 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29296 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29297 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29298 default: type
= _("<unknown>"); break;
29300 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29301 _("cannot represent %s relocation in this object file format"),
29308 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29310 && fixp
->fx_addsy
== GOT_symbol
)
29312 code
= BFD_RELOC_ARM_GOTPC
;
29313 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29317 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29319 if (reloc
->howto
== NULL
)
29321 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29322 _("cannot represent %s relocation in this object file format"),
29323 bfd_get_reloc_code_name (code
));
29327 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29328 vtable entry to be used in the relocation's section offset. */
29329 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29330 reloc
->address
= fixp
->fx_offset
;
29335 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29338 cons_fix_new_arm (fragS
* frag
,
29342 bfd_reloc_code_real_type reloc
)
29347 FIXME: @@ Should look at CPU word size. */
29351 reloc
= BFD_RELOC_8
;
29354 reloc
= BFD_RELOC_16
;
29358 reloc
= BFD_RELOC_32
;
29361 reloc
= BFD_RELOC_64
;
29366 if (exp
->X_op
== O_secrel
)
29368 exp
->X_op
= O_symbol
;
29369 reloc
= BFD_RELOC_32_SECREL
;
29373 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29376 #if defined (OBJ_COFF)
29378 arm_validate_fix (fixS
* fixP
)
29380 /* If the destination of the branch is a defined symbol which does not have
29381 the THUMB_FUNC attribute, then we must be calling a function which has
29382 the (interfacearm) attribute. We look for the Thumb entry point to that
29383 function and change the branch to refer to that function instead. */
29384 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29385 && fixP
->fx_addsy
!= NULL
29386 && S_IS_DEFINED (fixP
->fx_addsy
)
29387 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29389 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29396 arm_force_relocation (struct fix
* fixp
)
29398 #if defined (OBJ_COFF) && defined (TE_PE)
29399 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29403 /* In case we have a call or a branch to a function in ARM ISA mode from
29404 a thumb function or vice-versa force the relocation. These relocations
29405 are cleared off for some cores that might have blx and simple transformations
29409 switch (fixp
->fx_r_type
)
29411 case BFD_RELOC_ARM_PCREL_JUMP
:
29412 case BFD_RELOC_ARM_PCREL_CALL
:
29413 case BFD_RELOC_THUMB_PCREL_BLX
:
29414 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29418 case BFD_RELOC_ARM_PCREL_BLX
:
29419 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29420 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29421 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29422 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29431 /* Resolve these relocations even if the symbol is extern or weak.
29432 Technically this is probably wrong due to symbol preemption.
29433 In practice these relocations do not have enough range to be useful
29434 at dynamic link time, and some code (e.g. in the Linux kernel)
29435 expects these references to be resolved. */
29436 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29437 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29438 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29439 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29440 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29441 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29442 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29443 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29444 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29445 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29446 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29447 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29448 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29449 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29452 /* Always leave these relocations for the linker. */
29453 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29454 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29455 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29458 /* Always generate relocations against function symbols. */
29459 if (fixp
->fx_r_type
== BFD_RELOC_32
29461 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29464 return generic_force_reloc (fixp
);
29467 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29468 /* Relocations against function names must be left unadjusted,
29469 so that the linker can use this information to generate interworking
29470 stubs. The MIPS version of this function
29471 also prevents relocations that are mips-16 specific, but I do not
29472 know why it does this.
29475 There is one other problem that ought to be addressed here, but
29476 which currently is not: Taking the address of a label (rather
29477 than a function) and then later jumping to that address. Such
29478 addresses also ought to have their bottom bit set (assuming that
29479 they reside in Thumb code), but at the moment they will not. */
29482 arm_fix_adjustable (fixS
* fixP
)
29484 if (fixP
->fx_addsy
== NULL
)
29487 /* Preserve relocations against symbols with function type. */
29488 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29491 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29492 && fixP
->fx_subsy
== NULL
)
29495 /* We need the symbol name for the VTABLE entries. */
29496 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29497 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29500 /* Don't allow symbols to be discarded on GOT related relocs. */
29501 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29502 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29503 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29504 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29505 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29506 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29507 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29508 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29509 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29510 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29511 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29512 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29513 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29514 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29515 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29516 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29517 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29520 /* Similarly for group relocations. */
29521 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29522 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29523 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29526 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29527 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29528 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29529 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29530 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29531 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29532 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29533 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29534 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29537 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29538 offsets, so keep these symbols. */
29539 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29540 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29545 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29549 elf32_arm_target_format (void)
29552 return (target_big_endian
29553 ? "elf32-bigarm-symbian"
29554 : "elf32-littlearm-symbian");
29555 #elif defined (TE_VXWORKS)
29556 return (target_big_endian
29557 ? "elf32-bigarm-vxworks"
29558 : "elf32-littlearm-vxworks");
29559 #elif defined (TE_NACL)
29560 return (target_big_endian
29561 ? "elf32-bigarm-nacl"
29562 : "elf32-littlearm-nacl");
29566 if (target_big_endian
)
29567 return "elf32-bigarm-fdpic";
29569 return "elf32-littlearm-fdpic";
29573 if (target_big_endian
)
29574 return "elf32-bigarm";
29576 return "elf32-littlearm";
29582 armelf_frob_symbol (symbolS
* symp
,
29585 elf_frob_symbol (symp
, puntp
);
29589 /* MD interface: Finalization. */
29594 literal_pool
* pool
;
29596 /* Ensure that all the predication blocks are properly closed. */
29597 check_pred_blocks_finished ();
29599 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29601 /* Put it at the end of the relevant section. */
29602 subseg_set (pool
->section
, pool
->sub_section
);
29604 arm_elf_change_section ();
29611 /* Remove any excess mapping symbols generated for alignment frags in
29612 SEC. We may have created a mapping symbol before a zero byte
29613 alignment; remove it if there's a mapping symbol after the
29616 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29617 void *dummy ATTRIBUTE_UNUSED
)
29619 segment_info_type
*seginfo
= seg_info (sec
);
29622 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29625 for (fragp
= seginfo
->frchainP
->frch_root
;
29627 fragp
= fragp
->fr_next
)
29629 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29630 fragS
*next
= fragp
->fr_next
;
29632 /* Variable-sized frags have been converted to fixed size by
29633 this point. But if this was variable-sized to start with,
29634 there will be a fixed-size frag after it. So don't handle
29636 if (sym
== NULL
|| next
== NULL
)
29639 if (S_GET_VALUE (sym
) < next
->fr_address
)
29640 /* Not at the end of this frag. */
29642 know (S_GET_VALUE (sym
) == next
->fr_address
);
29646 if (next
->tc_frag_data
.first_map
!= NULL
)
29648 /* Next frag starts with a mapping symbol. Discard this
29650 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29654 if (next
->fr_next
== NULL
)
29656 /* This mapping symbol is at the end of the section. Discard
29658 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29659 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29663 /* As long as we have empty frags without any mapping symbols,
29665 /* If the next frag is non-empty and does not start with a
29666 mapping symbol, then this mapping symbol is required. */
29667 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29670 next
= next
->fr_next
;
29672 while (next
!= NULL
);
29677 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29681 arm_adjust_symtab (void)
29686 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29688 if (ARM_IS_THUMB (sym
))
29690 if (THUMB_IS_FUNC (sym
))
29692 /* Mark the symbol as a Thumb function. */
29693 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29694 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29695 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29697 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29698 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29700 as_bad (_("%s: unexpected function type: %d"),
29701 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29703 else switch (S_GET_STORAGE_CLASS (sym
))
29706 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29709 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29712 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29720 if (ARM_IS_INTERWORK (sym
))
29721 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29728 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29730 if (ARM_IS_THUMB (sym
))
29732 elf_symbol_type
* elf_sym
;
29734 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29735 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29737 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29738 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29740 /* If it's a .thumb_func, declare it as so,
29741 otherwise tag label as .code 16. */
29742 if (THUMB_IS_FUNC (sym
))
29743 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29744 ST_BRANCH_TO_THUMB
);
29745 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29746 elf_sym
->internal_elf_sym
.st_info
=
29747 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29752 /* Remove any overlapping mapping symbols generated by alignment frags. */
29753 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29754 /* Now do generic ELF adjustments. */
29755 elf_adjust_symtab ();
29759 /* MD interface: Initialization. */
29762 set_constant_flonums (void)
29766 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29767 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29771 /* Auto-select Thumb mode if it's the only available instruction set for the
29772 given architecture. */
29775 autoselect_thumb_from_cpu_variant (void)
29777 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29778 opcode_select (16);
29787 if ( (arm_ops_hsh
= hash_new ()) == NULL
29788 || (arm_cond_hsh
= hash_new ()) == NULL
29789 || (arm_vcond_hsh
= hash_new ()) == NULL
29790 || (arm_shift_hsh
= hash_new ()) == NULL
29791 || (arm_psr_hsh
= hash_new ()) == NULL
29792 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29793 || (arm_reg_hsh
= hash_new ()) == NULL
29794 || (arm_reloc_hsh
= hash_new ()) == NULL
29795 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29796 as_fatal (_("virtual memory exhausted"));
29798 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29799 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29800 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29801 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29802 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29803 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29804 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29805 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29806 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29807 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29808 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29809 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29810 (void *) (v7m_psrs
+ i
));
29811 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29812 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29814 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29816 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29817 (void *) (barrier_opt_names
+ i
));
29819 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29821 struct reloc_entry
* entry
= reloc_names
+ i
;
29823 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29824 /* This makes encode_branch() use the EABI versions of this relocation. */
29825 entry
->reloc
= BFD_RELOC_UNUSED
;
29827 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29831 set_constant_flonums ();
29833 /* Set the cpu variant based on the command-line options. We prefer
29834 -mcpu= over -march= if both are set (as for GCC); and we prefer
29835 -mfpu= over any other way of setting the floating point unit.
29836 Use of legacy options with new options are faulted. */
29839 if (mcpu_cpu_opt
|| march_cpu_opt
)
29840 as_bad (_("use of old and new-style options to set CPU type"));
29842 selected_arch
= *legacy_cpu
;
29844 else if (mcpu_cpu_opt
)
29846 selected_arch
= *mcpu_cpu_opt
;
29847 selected_ext
= *mcpu_ext_opt
;
29849 else if (march_cpu_opt
)
29851 selected_arch
= *march_cpu_opt
;
29852 selected_ext
= *march_ext_opt
;
29854 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29859 as_bad (_("use of old and new-style options to set FPU type"));
29861 selected_fpu
= *legacy_fpu
;
29864 selected_fpu
= *mfpu_opt
;
29867 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29868 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29869 /* Some environments specify a default FPU. If they don't, infer it
29870 from the processor. */
29872 selected_fpu
= *mcpu_fpu_opt
;
29873 else if (march_fpu_opt
)
29874 selected_fpu
= *march_fpu_opt
;
29876 selected_fpu
= fpu_default
;
29880 if (ARM_FEATURE_ZERO (selected_fpu
))
29882 if (!no_cpu_selected ())
29883 selected_fpu
= fpu_default
;
29885 selected_fpu
= fpu_arch_fpa
;
29889 if (ARM_FEATURE_ZERO (selected_arch
))
29891 selected_arch
= cpu_default
;
29892 selected_cpu
= selected_arch
;
29894 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29896 /* Autodection of feature mode: allow all features in cpu_variant but leave
29897 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29898 after all instruction have been processed and we can decide what CPU
29899 should be selected. */
29900 if (ARM_FEATURE_ZERO (selected_arch
))
29901 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29903 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29906 autoselect_thumb_from_cpu_variant ();
29908 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29910 #if defined OBJ_COFF || defined OBJ_ELF
29912 unsigned int flags
= 0;
29914 #if defined OBJ_ELF
29915 flags
= meabi_flags
;
29917 switch (meabi_flags
)
29919 case EF_ARM_EABI_UNKNOWN
:
29921 /* Set the flags in the private structure. */
29922 if (uses_apcs_26
) flags
|= F_APCS26
;
29923 if (support_interwork
) flags
|= F_INTERWORK
;
29924 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29925 if (pic_code
) flags
|= F_PIC
;
29926 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29927 flags
|= F_SOFT_FLOAT
;
29929 switch (mfloat_abi_opt
)
29931 case ARM_FLOAT_ABI_SOFT
:
29932 case ARM_FLOAT_ABI_SOFTFP
:
29933 flags
|= F_SOFT_FLOAT
;
29936 case ARM_FLOAT_ABI_HARD
:
29937 if (flags
& F_SOFT_FLOAT
)
29938 as_bad (_("hard-float conflicts with specified fpu"));
29942 /* Using pure-endian doubles (even if soft-float). */
29943 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29944 flags
|= F_VFP_FLOAT
;
29946 #if defined OBJ_ELF
29947 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29948 flags
|= EF_ARM_MAVERICK_FLOAT
;
29951 case EF_ARM_EABI_VER4
:
29952 case EF_ARM_EABI_VER5
:
29953 /* No additional flags to set. */
29960 bfd_set_private_flags (stdoutput
, flags
);
29962 /* We have run out flags in the COFF header to encode the
29963 status of ATPCS support, so instead we create a dummy,
29964 empty, debug section called .arm.atpcs. */
29969 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29973 bfd_set_section_flags
29974 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29975 bfd_set_section_size (stdoutput
, sec
, 0);
29976 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29982 /* Record the CPU type as well. */
29983 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29984 mach
= bfd_mach_arm_iWMMXt2
;
29985 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29986 mach
= bfd_mach_arm_iWMMXt
;
29987 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29988 mach
= bfd_mach_arm_XScale
;
29989 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29990 mach
= bfd_mach_arm_ep9312
;
29991 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29992 mach
= bfd_mach_arm_5TE
;
29993 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29995 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29996 mach
= bfd_mach_arm_5T
;
29998 mach
= bfd_mach_arm_5
;
30000 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30002 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30003 mach
= bfd_mach_arm_4T
;
30005 mach
= bfd_mach_arm_4
;
30007 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30008 mach
= bfd_mach_arm_3M
;
30009 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30010 mach
= bfd_mach_arm_3
;
30011 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30012 mach
= bfd_mach_arm_2a
;
30013 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30014 mach
= bfd_mach_arm_2
;
30016 mach
= bfd_mach_arm_unknown
;
30018 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30021 /* Command line processing. */
30024 Invocation line includes a switch not recognized by the base assembler.
30025 See if it's a processor-specific option.
30027 This routine is somewhat complicated by the need for backwards
30028 compatibility (since older releases of gcc can't be changed).
30029 The new options try to make the interface as compatible as
30032 New options (supported) are:
30034 -mcpu=<cpu name> Assemble for selected processor
30035 -march=<architecture name> Assemble for selected architecture
30036 -mfpu=<fpu architecture> Assemble for selected FPU.
30037 -EB/-mbig-endian Big-endian
30038 -EL/-mlittle-endian Little-endian
30039 -k Generate PIC code
30040 -mthumb Start in Thumb mode
30041 -mthumb-interwork Code supports ARM/Thumb interworking
30043 -m[no-]warn-deprecated Warn about deprecated features
30044 -m[no-]warn-syms Warn when symbols match instructions
30046 For now we will also provide support for:
30048 -mapcs-32 32-bit Program counter
30049 -mapcs-26 26-bit Program counter
30050 -macps-float Floats passed in FP registers
30051 -mapcs-reentrant Reentrant code
30053 (sometime these will probably be replaced with -mapcs=<list of options>
30054 and -matpcs=<list of options>)
30056 The remaining options are only supported for back-wards compatibility.
30057 Cpu variants, the arm part is optional:
30058 -m[arm]1 Currently not supported.
30059 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30060 -m[arm]3 Arm 3 processor
30061 -m[arm]6[xx], Arm 6 processors
30062 -m[arm]7[xx][t][[d]m] Arm 7 processors
30063 -m[arm]8[10] Arm 8 processors
30064 -m[arm]9[20][tdmi] Arm 9 processors
30065 -mstrongarm[110[0]] StrongARM processors
30066 -mxscale XScale processors
30067 -m[arm]v[2345[t[e]]] Arm architectures
30068 -mall All (except the ARM1)
30070 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30071 -mfpe-old (No float load/store multiples)
30072 -mvfpxd VFP Single precision
30074 -mno-fpu Disable all floating point instructions
30076 The following CPU names are recognized:
30077 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30078 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30079 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30080 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30081 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30082 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30083 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30087 const char * md_shortopts
= "m:k";
30089 #ifdef ARM_BI_ENDIAN
30090 #define OPTION_EB (OPTION_MD_BASE + 0)
30091 #define OPTION_EL (OPTION_MD_BASE + 1)
30093 #if TARGET_BYTES_BIG_ENDIAN
30094 #define OPTION_EB (OPTION_MD_BASE + 0)
30096 #define OPTION_EL (OPTION_MD_BASE + 1)
30099 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30100 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30102 struct option md_longopts
[] =
30105 {"EB", no_argument
, NULL
, OPTION_EB
},
30108 {"EL", no_argument
, NULL
, OPTION_EL
},
30110 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30112 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30114 {NULL
, no_argument
, NULL
, 0}
30117 size_t md_longopts_size
= sizeof (md_longopts
);
30119 struct arm_option_table
30121 const char * option
; /* Option name to match. */
30122 const char * help
; /* Help information. */
30123 int * var
; /* Variable to change. */
30124 int value
; /* What to change it to. */
30125 const char * deprecated
; /* If non-null, print this message. */
30128 struct arm_option_table arm_opts
[] =
30130 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30131 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30132 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30133 &support_interwork
, 1, NULL
},
30134 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30135 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30136 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30138 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30139 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30140 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30141 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30144 /* These are recognized by the assembler, but have no affect on code. */
30145 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30146 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30148 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30149 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30150 &warn_on_deprecated
, 0, NULL
},
30151 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30152 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30153 {NULL
, NULL
, NULL
, 0, NULL
}
30156 struct arm_legacy_option_table
30158 const char * option
; /* Option name to match. */
30159 const arm_feature_set
** var
; /* Variable to change. */
30160 const arm_feature_set value
; /* What to change it to. */
30161 const char * deprecated
; /* If non-null, print this message. */
30164 const struct arm_legacy_option_table arm_legacy_opts
[] =
30166 /* DON'T add any new processors to this list -- we want the whole list
30167 to go away... Add them to the processors table instead. */
30168 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30169 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30170 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30171 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30172 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30173 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30174 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30175 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30176 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30177 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30178 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30179 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30180 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30181 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30182 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30183 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30184 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30185 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30186 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30187 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30188 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30189 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30190 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30191 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30192 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30193 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30194 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30195 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30196 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30197 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30198 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30199 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30200 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30201 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30202 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30203 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30204 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30205 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30206 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30207 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30208 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30209 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30210 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30211 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30212 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30213 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30214 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30215 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30216 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30217 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30218 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30219 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30220 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30221 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30222 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30223 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30224 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30225 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30226 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30227 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30228 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30229 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30230 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30231 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30232 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30233 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30234 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30235 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30236 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30237 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30238 N_("use -mcpu=strongarm110")},
30239 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30240 N_("use -mcpu=strongarm1100")},
30241 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30242 N_("use -mcpu=strongarm1110")},
30243 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30244 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30245 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30247 /* Architecture variants -- don't add any more to this list either. */
30248 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30249 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30250 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30251 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30252 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30253 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30254 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30255 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30256 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30257 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30258 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30259 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30260 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30261 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30262 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30263 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30264 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30265 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30267 /* Floating point variants -- don't add any more to this list either. */
30268 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30269 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30270 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30271 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30272 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30274 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30277 struct arm_cpu_option_table
30281 const arm_feature_set value
;
30282 const arm_feature_set ext
;
30283 /* For some CPUs we assume an FPU unless the user explicitly sets
30285 const arm_feature_set default_fpu
;
30286 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30288 const char * canonical_name
;
30291 /* This list should, at a minimum, contain all the cpu names
30292 recognized by GCC. */
30293 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30295 static const struct arm_cpu_option_table arm_cpus
[] =
30297 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30300 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30303 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30306 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30309 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30312 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30315 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30318 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30321 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30324 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30327 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30330 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30333 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30336 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30339 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30342 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30345 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30348 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30351 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30354 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30357 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30360 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30363 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30366 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30369 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30372 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30375 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30378 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30381 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30384 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30387 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30390 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30393 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30396 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30399 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30402 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30405 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30408 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30411 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30414 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30417 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30420 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30423 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30426 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30429 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30432 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30436 /* For V5 or later processors we default to using VFP; but the user
30437 should really set the FPU type explicitly. */
30438 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30441 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30444 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30447 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30450 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30453 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30456 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30459 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30462 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30465 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30468 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30471 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30474 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30477 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30480 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30483 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30486 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30489 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30492 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30495 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30498 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30501 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30504 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30507 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30510 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30513 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30516 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30519 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30522 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30525 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30528 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30531 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30534 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30537 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30540 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30543 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30546 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30547 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30549 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30551 FPU_ARCH_NEON_VFP_V4
),
30552 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30553 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30554 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30555 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30556 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30557 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30558 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30560 FPU_ARCH_NEON_VFP_V4
),
30561 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30563 FPU_ARCH_NEON_VFP_V4
),
30564 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30566 FPU_ARCH_NEON_VFP_V4
),
30567 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30568 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30569 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30570 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30571 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30572 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30573 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30574 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30575 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30576 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30577 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30578 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30579 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30580 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30581 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30582 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30583 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30584 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30585 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30586 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30587 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30588 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30589 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30590 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30591 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30592 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30593 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30594 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30595 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30596 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30597 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30600 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30602 FPU_ARCH_VFP_V3D16
),
30603 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30604 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30606 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30607 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30608 FPU_ARCH_VFP_V3D16
),
30609 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30610 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30611 FPU_ARCH_VFP_V3D16
),
30612 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30613 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30614 FPU_ARCH_NEON_VFP_ARMV8
),
30615 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30616 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30618 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30621 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30624 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30627 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30630 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30633 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30636 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30639 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30640 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30641 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30642 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30643 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30644 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30645 /* ??? XSCALE is really an architecture. */
30646 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30650 /* ??? iwmmxt is not a processor. */
30651 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30654 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30657 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30662 ARM_CPU_OPT ("ep9312", "ARM920T",
30663 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30664 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30666 /* Marvell processors. */
30667 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30668 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30669 FPU_ARCH_VFP_V3D16
),
30670 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30671 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30672 FPU_ARCH_NEON_VFP_V4
),
30674 /* APM X-Gene family. */
30675 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30677 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30678 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30679 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30680 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30682 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30686 struct arm_ext_table
30690 const arm_feature_set merge
;
30691 const arm_feature_set clear
;
30694 struct arm_arch_option_table
30698 const arm_feature_set value
;
30699 const arm_feature_set default_fpu
;
30700 const struct arm_ext_table
* ext_table
;
30703 /* Used to add support for +E and +noE extension. */
30704 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30705 /* Used to add support for a +E extension. */
30706 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30707 /* Used to add support for a +noE extension. */
30708 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30710 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30711 ~0 & ~FPU_ENDIAN_PURE)
30713 static const struct arm_ext_table armv5te_ext_table
[] =
30715 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30716 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30719 static const struct arm_ext_table armv7_ext_table
[] =
30721 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30722 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30725 static const struct arm_ext_table armv7ve_ext_table
[] =
30727 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30728 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30729 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30730 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30731 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30732 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30733 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30735 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30736 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30738 /* Aliases for +simd. */
30739 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30741 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30742 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30743 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30745 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30748 static const struct arm_ext_table armv7a_ext_table
[] =
30750 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30751 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30752 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30753 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30754 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30755 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30756 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30758 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30759 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30761 /* Aliases for +simd. */
30762 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30763 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30765 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30766 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30768 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30769 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30770 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30773 static const struct arm_ext_table armv7r_ext_table
[] =
30775 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30776 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30777 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30778 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30779 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30780 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30781 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30782 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30783 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30786 static const struct arm_ext_table armv7em_ext_table
[] =
30788 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30789 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30790 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30791 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30792 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30793 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30794 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30797 static const struct arm_ext_table armv8a_ext_table
[] =
30799 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30800 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30801 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30802 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30804 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30805 should use the +simd option to turn on FP. */
30806 ARM_REMOVE ("fp", ALL_FP
),
30807 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30808 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30809 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30813 static const struct arm_ext_table armv81a_ext_table
[] =
30815 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30816 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30817 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30819 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30820 should use the +simd option to turn on FP. */
30821 ARM_REMOVE ("fp", ALL_FP
),
30822 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30823 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30824 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30827 static const struct arm_ext_table armv82a_ext_table
[] =
30829 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30830 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30831 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30832 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30833 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30834 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30836 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30837 should use the +simd option to turn on FP. */
30838 ARM_REMOVE ("fp", ALL_FP
),
30839 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30840 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30841 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30844 static const struct arm_ext_table armv84a_ext_table
[] =
30846 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30847 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30848 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30849 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30851 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30852 should use the +simd option to turn on FP. */
30853 ARM_REMOVE ("fp", ALL_FP
),
30854 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30855 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30856 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30859 static const struct arm_ext_table armv85a_ext_table
[] =
30861 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30862 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30863 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30864 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30866 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30867 should use the +simd option to turn on FP. */
30868 ARM_REMOVE ("fp", ALL_FP
),
30869 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30872 static const struct arm_ext_table armv8m_main_ext_table
[] =
30874 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30875 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30876 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30877 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30878 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30881 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30883 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30884 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30886 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30887 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30890 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30891 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30892 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30893 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30895 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30896 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30897 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30898 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30901 static const struct arm_ext_table armv8r_ext_table
[] =
30903 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30904 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30905 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30906 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30907 ARM_REMOVE ("fp", ALL_FP
),
30908 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30909 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30912 /* This list should, at a minimum, contain all the architecture names
30913 recognized by GCC. */
30914 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30915 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30916 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30918 static const struct arm_arch_option_table arm_archs
[] =
30920 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30921 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30922 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30923 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30924 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30925 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30926 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30927 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30928 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30929 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30930 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30931 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30932 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30933 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30934 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30935 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30936 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30937 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30938 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30939 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30940 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30941 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30942 kept to preserve existing behaviour. */
30943 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30944 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30945 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30946 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30947 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30948 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30949 kept to preserve existing behaviour. */
30950 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30951 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30952 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30953 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30954 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30955 /* The official spelling of the ARMv7 profile variants is the dashed form.
30956 Accept the non-dashed form for compatibility with old toolchains. */
30957 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30958 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30959 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30960 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30961 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30962 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30963 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30964 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30965 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30966 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30968 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30970 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30971 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30972 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30973 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30974 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30975 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30976 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30977 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30978 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30979 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30980 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30982 #undef ARM_ARCH_OPT
30984 /* ISA extensions in the co-processor and main instruction set space. */
30986 struct arm_option_extension_value_table
30990 const arm_feature_set merge_value
;
30991 const arm_feature_set clear_value
;
30992 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30993 indicates that an extension is available for all architectures while
30994 ARM_ANY marks an empty entry. */
30995 const arm_feature_set allowed_archs
[2];
30998 /* The following table must be in alphabetical order with a NULL last entry. */
31000 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31001 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31003 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31004 use the context sensitive approach using arm_ext_table's. */
31005 static const struct arm_option_extension_value_table arm_extensions
[] =
31007 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31008 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31009 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31010 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31011 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31012 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31013 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31015 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31016 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31017 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31018 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31019 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31020 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31021 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31023 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31024 | ARM_EXT2_FP16_FML
),
31025 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31026 | ARM_EXT2_FP16_FML
),
31028 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31029 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31030 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31031 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31032 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31033 Thumb divide instruction. Due to this having the same name as the
31034 previous entry, this will be ignored when doing command-line parsing and
31035 only considered by build attribute selection code. */
31036 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31037 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31038 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31039 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31040 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31041 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31042 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31043 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31044 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31045 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31046 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31047 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31048 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31049 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31050 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31051 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31052 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31053 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31054 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31055 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31056 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31058 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31059 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31060 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31061 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31062 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31063 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31064 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31065 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31067 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31068 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31069 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31070 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31071 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31072 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31073 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31074 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31076 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31077 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31078 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31079 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31080 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31084 /* ISA floating-point and Advanced SIMD extensions. */
31085 struct arm_option_fpu_value_table
31088 const arm_feature_set value
;
31091 /* This list should, at a minimum, contain all the fpu names
31092 recognized by GCC. */
31093 static const struct arm_option_fpu_value_table arm_fpus
[] =
31095 {"softfpa", FPU_NONE
},
31096 {"fpe", FPU_ARCH_FPE
},
31097 {"fpe2", FPU_ARCH_FPE
},
31098 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31099 {"fpa", FPU_ARCH_FPA
},
31100 {"fpa10", FPU_ARCH_FPA
},
31101 {"fpa11", FPU_ARCH_FPA
},
31102 {"arm7500fe", FPU_ARCH_FPA
},
31103 {"softvfp", FPU_ARCH_VFP
},
31104 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31105 {"vfp", FPU_ARCH_VFP_V2
},
31106 {"vfp9", FPU_ARCH_VFP_V2
},
31107 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31108 {"vfp10", FPU_ARCH_VFP_V2
},
31109 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31110 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31111 {"vfpv2", FPU_ARCH_VFP_V2
},
31112 {"vfpv3", FPU_ARCH_VFP_V3
},
31113 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31114 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31115 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31116 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31117 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31118 {"arm1020t", FPU_ARCH_VFP_V1
},
31119 {"arm1020e", FPU_ARCH_VFP_V2
},
31120 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31121 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31122 {"maverick", FPU_ARCH_MAVERICK
},
31123 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31124 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31125 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31126 {"vfpv4", FPU_ARCH_VFP_V4
},
31127 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31128 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31129 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31130 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31131 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31132 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31133 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31134 {"crypto-neon-fp-armv8",
31135 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31136 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31137 {"crypto-neon-fp-armv8.1",
31138 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31139 {NULL
, ARM_ARCH_NONE
}
31142 struct arm_option_value_table
31148 static const struct arm_option_value_table arm_float_abis
[] =
31150 {"hard", ARM_FLOAT_ABI_HARD
},
31151 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31152 {"soft", ARM_FLOAT_ABI_SOFT
},
31157 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31158 static const struct arm_option_value_table arm_eabis
[] =
31160 {"gnu", EF_ARM_EABI_UNKNOWN
},
31161 {"4", EF_ARM_EABI_VER4
},
31162 {"5", EF_ARM_EABI_VER5
},
31167 struct arm_long_option_table
31169 const char * option
; /* Substring to match. */
31170 const char * help
; /* Help information. */
31171 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31172 const char * deprecated
; /* If non-null, print this message. */
31176 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31177 arm_feature_set
*ext_set
,
31178 const struct arm_ext_table
*ext_table
)
31180 /* We insist on extensions being specified in alphabetical order, and with
31181 extensions being added before being removed. We achieve this by having
31182 the global ARM_EXTENSIONS table in alphabetical order, and using the
31183 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31184 or removing it (0) and only allowing it to change in the order
31186 const struct arm_option_extension_value_table
* opt
= NULL
;
31187 const arm_feature_set arm_any
= ARM_ANY
;
31188 int adding_value
= -1;
31190 while (str
!= NULL
&& *str
!= 0)
31197 as_bad (_("invalid architectural extension"));
31202 ext
= strchr (str
, '+');
31207 len
= strlen (str
);
31209 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31211 if (adding_value
!= 0)
31214 opt
= arm_extensions
;
31222 if (adding_value
== -1)
31225 opt
= arm_extensions
;
31227 else if (adding_value
!= 1)
31229 as_bad (_("must specify extensions to add before specifying "
31230 "those to remove"));
31237 as_bad (_("missing architectural extension"));
31241 gas_assert (adding_value
!= -1);
31242 gas_assert (opt
!= NULL
);
31244 if (ext_table
!= NULL
)
31246 const struct arm_ext_table
* ext_opt
= ext_table
;
31247 bfd_boolean found
= FALSE
;
31248 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31249 if (ext_opt
->name_len
== len
31250 && strncmp (ext_opt
->name
, str
, len
) == 0)
31254 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31255 /* TODO: Option not supported. When we remove the
31256 legacy table this case should error out. */
31259 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31263 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31264 /* TODO: Option not supported. When we remove the
31265 legacy table this case should error out. */
31267 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31279 /* Scan over the options table trying to find an exact match. */
31280 for (; opt
->name
!= NULL
; opt
++)
31281 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31283 int i
, nb_allowed_archs
=
31284 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31285 /* Check we can apply the extension to this architecture. */
31286 for (i
= 0; i
< nb_allowed_archs
; i
++)
31289 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31291 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31294 if (i
== nb_allowed_archs
)
31296 as_bad (_("extension does not apply to the base architecture"));
31300 /* Add or remove the extension. */
31302 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31304 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31306 /* Allowing Thumb division instructions for ARMv7 in autodetection
31307 rely on this break so that duplicate extensions (extensions
31308 with the same name as a previous extension in the list) are not
31309 considered for command-line parsing. */
31313 if (opt
->name
== NULL
)
31315 /* Did we fail to find an extension because it wasn't specified in
31316 alphabetical order, or because it does not exist? */
31318 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31319 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31322 if (opt
->name
== NULL
)
31323 as_bad (_("unknown architectural extension `%s'"), str
);
31325 as_bad (_("architectural extensions must be specified in "
31326 "alphabetical order"));
31332 /* We should skip the extension we've just matched the next time
31344 arm_parse_fp16_opt (const char *str
)
31346 if (strcasecmp (str
, "ieee") == 0)
31347 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31348 else if (strcasecmp (str
, "alternative") == 0)
31349 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31352 as_bad (_("unrecognised float16 format \"%s\""), str
);
31360 arm_parse_cpu (const char *str
)
31362 const struct arm_cpu_option_table
*opt
;
31363 const char *ext
= strchr (str
, '+');
31369 len
= strlen (str
);
31373 as_bad (_("missing cpu name `%s'"), str
);
31377 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31378 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31380 mcpu_cpu_opt
= &opt
->value
;
31381 if (mcpu_ext_opt
== NULL
)
31382 mcpu_ext_opt
= XNEW (arm_feature_set
);
31383 *mcpu_ext_opt
= opt
->ext
;
31384 mcpu_fpu_opt
= &opt
->default_fpu
;
31385 if (opt
->canonical_name
)
31387 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31388 strcpy (selected_cpu_name
, opt
->canonical_name
);
31394 if (len
>= sizeof selected_cpu_name
)
31395 len
= (sizeof selected_cpu_name
) - 1;
31397 for (i
= 0; i
< len
; i
++)
31398 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31399 selected_cpu_name
[i
] = 0;
31403 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31408 as_bad (_("unknown cpu `%s'"), str
);
31413 arm_parse_arch (const char *str
)
31415 const struct arm_arch_option_table
*opt
;
31416 const char *ext
= strchr (str
, '+');
31422 len
= strlen (str
);
31426 as_bad (_("missing architecture name `%s'"), str
);
31430 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31431 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31433 march_cpu_opt
= &opt
->value
;
31434 if (march_ext_opt
== NULL
)
31435 march_ext_opt
= XNEW (arm_feature_set
);
31436 *march_ext_opt
= arm_arch_none
;
31437 march_fpu_opt
= &opt
->default_fpu
;
31438 strcpy (selected_cpu_name
, opt
->name
);
31441 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31447 as_bad (_("unknown architecture `%s'\n"), str
);
31452 arm_parse_fpu (const char * str
)
31454 const struct arm_option_fpu_value_table
* opt
;
31456 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31457 if (streq (opt
->name
, str
))
31459 mfpu_opt
= &opt
->value
;
31463 as_bad (_("unknown floating point format `%s'\n"), str
);
31468 arm_parse_float_abi (const char * str
)
31470 const struct arm_option_value_table
* opt
;
31472 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31473 if (streq (opt
->name
, str
))
31475 mfloat_abi_opt
= opt
->value
;
31479 as_bad (_("unknown floating point abi `%s'\n"), str
);
31485 arm_parse_eabi (const char * str
)
31487 const struct arm_option_value_table
*opt
;
31489 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31490 if (streq (opt
->name
, str
))
31492 meabi_flags
= opt
->value
;
31495 as_bad (_("unknown EABI `%s'\n"), str
);
31501 arm_parse_it_mode (const char * str
)
31503 bfd_boolean ret
= TRUE
;
31505 if (streq ("arm", str
))
31506 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31507 else if (streq ("thumb", str
))
31508 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31509 else if (streq ("always", str
))
31510 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31511 else if (streq ("never", str
))
31512 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31515 as_bad (_("unknown implicit IT mode `%s', should be "\
31516 "arm, thumb, always, or never."), str
);
31524 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31526 codecomposer_syntax
= TRUE
;
31527 arm_comment_chars
[0] = ';';
31528 arm_line_separator_chars
[0] = 0;
31532 struct arm_long_option_table arm_long_opts
[] =
31534 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31535 arm_parse_cpu
, NULL
},
31536 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31537 arm_parse_arch
, NULL
},
31538 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31539 arm_parse_fpu
, NULL
},
31540 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31541 arm_parse_float_abi
, NULL
},
31543 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31544 arm_parse_eabi
, NULL
},
31546 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31547 arm_parse_it_mode
, NULL
},
31548 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31549 arm_ccs_mode
, NULL
},
31551 N_("[ieee|alternative]\n\
31552 set the encoding for half precision floating point "
31553 "numbers to IEEE\n\
31554 or Arm alternative format."),
31555 arm_parse_fp16_opt
, NULL
},
31556 {NULL
, NULL
, 0, NULL
}
31560 md_parse_option (int c
, const char * arg
)
31562 struct arm_option_table
*opt
;
31563 const struct arm_legacy_option_table
*fopt
;
31564 struct arm_long_option_table
*lopt
;
31570 target_big_endian
= 1;
31576 target_big_endian
= 0;
31580 case OPTION_FIX_V4BX
:
31588 #endif /* OBJ_ELF */
31591 /* Listing option. Just ignore these, we don't support additional
31596 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31598 if (c
== opt
->option
[0]
31599 && ((arg
== NULL
&& opt
->option
[1] == 0)
31600 || streq (arg
, opt
->option
+ 1)))
31602 /* If the option is deprecated, tell the user. */
31603 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31604 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31605 arg
? arg
: "", _(opt
->deprecated
));
31607 if (opt
->var
!= NULL
)
31608 *opt
->var
= opt
->value
;
31614 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31616 if (c
== fopt
->option
[0]
31617 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31618 || streq (arg
, fopt
->option
+ 1)))
31620 /* If the option is deprecated, tell the user. */
31621 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31622 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31623 arg
? arg
: "", _(fopt
->deprecated
));
31625 if (fopt
->var
!= NULL
)
31626 *fopt
->var
= &fopt
->value
;
31632 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31634 /* These options are expected to have an argument. */
31635 if (c
== lopt
->option
[0]
31637 && strncmp (arg
, lopt
->option
+ 1,
31638 strlen (lopt
->option
+ 1)) == 0)
31640 /* If the option is deprecated, tell the user. */
31641 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31642 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31643 _(lopt
->deprecated
));
31645 /* Call the sup-option parser. */
31646 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31657 md_show_usage (FILE * fp
)
31659 struct arm_option_table
*opt
;
31660 struct arm_long_option_table
*lopt
;
31662 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31664 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31665 if (opt
->help
!= NULL
)
31666 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31668 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31669 if (lopt
->help
!= NULL
)
31670 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31674 -EB assemble code for a big-endian cpu\n"));
31679 -EL assemble code for a little-endian cpu\n"));
31683 --fix-v4bx Allow BX in ARMv4 code\n"));
31687 --fdpic generate an FDPIC object file\n"));
31688 #endif /* OBJ_ELF */
31696 arm_feature_set flags
;
31697 } cpu_arch_ver_table
;
31699 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31700 chronologically for architectures, with an exception for ARMv6-M and
31701 ARMv6S-M due to legacy reasons. No new architecture should have a
31702 special case. This allows for build attribute selection results to be
31703 stable when new architectures are added. */
31704 static const cpu_arch_ver_table cpu_arch_ver
[] =
31706 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31707 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31708 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31709 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31710 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31711 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31712 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31713 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31714 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31715 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31716 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31717 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31718 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31719 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31720 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31721 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31722 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31723 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31724 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31725 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31726 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31727 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31728 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31729 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31731 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31732 always selected build attributes to match those of ARMv6-M
31733 (resp. ARMv6S-M). However, due to these architectures being a strict
31734 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31735 would be selected when fully respecting chronology of architectures.
31736 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31737 move them before ARMv7 architectures. */
31738 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31739 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31741 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31742 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31743 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31744 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31745 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31746 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31747 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31748 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31749 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31750 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31751 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31752 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31753 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31754 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31755 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31756 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31757 {-1, ARM_ARCH_NONE
}
31760 /* Set an attribute if it has not already been set by the user. */
31763 aeabi_set_attribute_int (int tag
, int value
)
31766 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31767 || !attributes_set_explicitly
[tag
])
31768 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31772 aeabi_set_attribute_string (int tag
, const char *value
)
31775 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31776 || !attributes_set_explicitly
[tag
])
31777 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31780 /* Return whether features in the *NEEDED feature set are available via
31781 extensions for the architecture whose feature set is *ARCH_FSET. */
31784 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31785 const arm_feature_set
*needed
)
31787 int i
, nb_allowed_archs
;
31788 arm_feature_set ext_fset
;
31789 const struct arm_option_extension_value_table
*opt
;
31791 ext_fset
= arm_arch_none
;
31792 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31794 /* Extension does not provide any feature we need. */
31795 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31799 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31800 for (i
= 0; i
< nb_allowed_archs
; i
++)
31803 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31806 /* Extension is available, add it. */
31807 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31808 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31812 /* Can we enable all features in *needed? */
31813 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31816 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31817 a given architecture feature set *ARCH_EXT_FSET including extension feature
31818 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31819 - if true, check for an exact match of the architecture modulo extensions;
31820 - otherwise, select build attribute value of the first superset
31821 architecture released so that results remains stable when new architectures
31823 For -march/-mcpu=all the build attribute value of the most featureful
31824 architecture is returned. Tag_CPU_arch_profile result is returned in
31828 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31829 const arm_feature_set
*ext_fset
,
31830 char *profile
, int exact_match
)
31832 arm_feature_set arch_fset
;
31833 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31835 /* Select most featureful architecture with all its extensions if building
31836 for -march=all as the feature sets used to set build attributes. */
31837 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31839 /* Force revisiting of decision for each new architecture. */
31840 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31842 return TAG_CPU_ARCH_V8
;
31845 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31847 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31849 arm_feature_set known_arch_fset
;
31851 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31854 /* Base architecture match user-specified architecture and
31855 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31856 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31861 /* Base architecture match user-specified architecture only
31862 (eg. ARMv6-M in the same case as above). Record it in case we
31863 find a match with above condition. */
31864 else if (p_ver_ret
== NULL
31865 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31871 /* Architecture has all features wanted. */
31872 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31874 arm_feature_set added_fset
;
31876 /* Compute features added by this architecture over the one
31877 recorded in p_ver_ret. */
31878 if (p_ver_ret
!= NULL
)
31879 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31881 /* First architecture that match incl. with extensions, or the
31882 only difference in features over the recorded match is
31883 features that were optional and are now mandatory. */
31884 if (p_ver_ret
== NULL
31885 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31891 else if (p_ver_ret
== NULL
)
31893 arm_feature_set needed_ext_fset
;
31895 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31897 /* Architecture has all features needed when using some
31898 extensions. Record it and continue searching in case there
31899 exist an architecture providing all needed features without
31900 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31902 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31909 if (p_ver_ret
== NULL
)
31913 /* Tag_CPU_arch_profile. */
31914 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31915 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31916 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31917 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31919 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31921 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31925 return p_ver_ret
->val
;
31928 /* Set the public EABI object attributes. */
31931 aeabi_set_public_attributes (void)
31933 char profile
= '\0';
31936 int fp16_optional
= 0;
31937 int skip_exact_match
= 0;
31938 arm_feature_set flags
, flags_arch
, flags_ext
;
31940 /* Autodetection mode, choose the architecture based the instructions
31942 if (no_cpu_selected ())
31944 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31946 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31947 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31949 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31950 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31952 /* Code run during relaxation relies on selected_cpu being set. */
31953 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31954 flags_ext
= arm_arch_none
;
31955 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31956 selected_ext
= flags_ext
;
31957 selected_cpu
= flags
;
31959 /* Otherwise, choose the architecture based on the capabilities of the
31963 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31964 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31965 flags_ext
= selected_ext
;
31966 flags
= selected_cpu
;
31968 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31970 /* Allow the user to override the reported architecture. */
31971 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31973 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31974 flags_ext
= arm_arch_none
;
31977 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31979 /* When this function is run again after relaxation has happened there is no
31980 way to determine whether an architecture or CPU was specified by the user:
31981 - selected_cpu is set above for relaxation to work;
31982 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31983 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31984 Therefore, if not in -march=all case we first try an exact match and fall
31985 back to autodetection. */
31986 if (!skip_exact_match
)
31987 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31989 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31991 as_bad (_("no architecture contains all the instructions used\n"));
31993 /* Tag_CPU_name. */
31994 if (selected_cpu_name
[0])
31998 q
= selected_cpu_name
;
31999 if (strncmp (q
, "armv", 4) == 0)
32004 for (i
= 0; q
[i
]; i
++)
32005 q
[i
] = TOUPPER (q
[i
]);
32007 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32010 /* Tag_CPU_arch. */
32011 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32013 /* Tag_CPU_arch_profile. */
32014 if (profile
!= '\0')
32015 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32017 /* Tag_DSP_extension. */
32018 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32019 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32021 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32022 /* Tag_ARM_ISA_use. */
32023 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32024 || ARM_FEATURE_ZERO (flags_arch
))
32025 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32027 /* Tag_THUMB_ISA_use. */
32028 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32029 || ARM_FEATURE_ZERO (flags_arch
))
32033 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32034 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32036 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32040 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32043 /* Tag_VFP_arch. */
32044 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32045 aeabi_set_attribute_int (Tag_VFP_arch
,
32046 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32048 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32049 aeabi_set_attribute_int (Tag_VFP_arch
,
32050 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32052 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32055 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32057 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32059 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32062 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32063 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32064 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32065 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32066 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32068 /* Tag_ABI_HardFP_use. */
32069 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32070 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32071 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32073 /* Tag_WMMX_arch. */
32074 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32075 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32076 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32077 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32079 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32080 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32081 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32082 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32083 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32084 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32086 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32088 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32092 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32097 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32098 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32099 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32100 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32102 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32103 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32104 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32108 We set Tag_DIV_use to two when integer divide instructions have been used
32109 in ARM state, or when Thumb integer divide instructions have been used,
32110 but we have no architecture profile set, nor have we any ARM instructions.
32112 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32113 by the base architecture.
32115 For new architectures we will have to check these tests. */
32116 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32117 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32118 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32119 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32120 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32121 || (profile
== '\0'
32122 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32123 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32124 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32126 /* Tag_MP_extension_use. */
32127 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32128 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32130 /* Tag Virtualization_use. */
32131 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32133 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32136 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32138 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32139 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32142 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32143 finished and free extension feature bits which will not be used anymore. */
32146 arm_md_post_relax (void)
32148 aeabi_set_public_attributes ();
32149 XDELETE (mcpu_ext_opt
);
32150 mcpu_ext_opt
= NULL
;
32151 XDELETE (march_ext_opt
);
32152 march_ext_opt
= NULL
;
32155 /* Add the default contents for the .ARM.attributes section. */
32160 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32163 aeabi_set_public_attributes ();
32165 #endif /* OBJ_ELF */
32167 /* Parse a .cpu directive. */
32170 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32172 const struct arm_cpu_option_table
*opt
;
32176 name
= input_line_pointer
;
32177 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32178 input_line_pointer
++;
32179 saved_char
= *input_line_pointer
;
32180 *input_line_pointer
= 0;
32182 /* Skip the first "all" entry. */
32183 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32184 if (streq (opt
->name
, name
))
32186 selected_arch
= opt
->value
;
32187 selected_ext
= opt
->ext
;
32188 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32189 if (opt
->canonical_name
)
32190 strcpy (selected_cpu_name
, opt
->canonical_name
);
32194 for (i
= 0; opt
->name
[i
]; i
++)
32195 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32197 selected_cpu_name
[i
] = 0;
32199 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32201 *input_line_pointer
= saved_char
;
32202 demand_empty_rest_of_line ();
32205 as_bad (_("unknown cpu `%s'"), name
);
32206 *input_line_pointer
= saved_char
;
32207 ignore_rest_of_line ();
32210 /* Parse a .arch directive. */
32213 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32215 const struct arm_arch_option_table
*opt
;
32219 name
= input_line_pointer
;
32220 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32221 input_line_pointer
++;
32222 saved_char
= *input_line_pointer
;
32223 *input_line_pointer
= 0;
32225 /* Skip the first "all" entry. */
32226 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32227 if (streq (opt
->name
, name
))
32229 selected_arch
= opt
->value
;
32230 selected_ext
= arm_arch_none
;
32231 selected_cpu
= selected_arch
;
32232 strcpy (selected_cpu_name
, opt
->name
);
32233 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32234 *input_line_pointer
= saved_char
;
32235 demand_empty_rest_of_line ();
32239 as_bad (_("unknown architecture `%s'\n"), name
);
32240 *input_line_pointer
= saved_char
;
32241 ignore_rest_of_line ();
32244 /* Parse a .object_arch directive. */
32247 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32249 const struct arm_arch_option_table
*opt
;
32253 name
= input_line_pointer
;
32254 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32255 input_line_pointer
++;
32256 saved_char
= *input_line_pointer
;
32257 *input_line_pointer
= 0;
32259 /* Skip the first "all" entry. */
32260 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32261 if (streq (opt
->name
, name
))
32263 selected_object_arch
= opt
->value
;
32264 *input_line_pointer
= saved_char
;
32265 demand_empty_rest_of_line ();
32269 as_bad (_("unknown architecture `%s'\n"), name
);
32270 *input_line_pointer
= saved_char
;
32271 ignore_rest_of_line ();
32274 /* Parse a .arch_extension directive. */
32277 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32279 const struct arm_option_extension_value_table
*opt
;
32282 int adding_value
= 1;
32284 name
= input_line_pointer
;
32285 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32286 input_line_pointer
++;
32287 saved_char
= *input_line_pointer
;
32288 *input_line_pointer
= 0;
32290 if (strlen (name
) >= 2
32291 && strncmp (name
, "no", 2) == 0)
32297 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32298 if (streq (opt
->name
, name
))
32300 int i
, nb_allowed_archs
=
32301 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32302 for (i
= 0; i
< nb_allowed_archs
; i
++)
32305 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32307 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32311 if (i
== nb_allowed_archs
)
32313 as_bad (_("architectural extension `%s' is not allowed for the "
32314 "current base architecture"), name
);
32319 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32322 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32324 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32325 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32326 *input_line_pointer
= saved_char
;
32327 demand_empty_rest_of_line ();
32328 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32329 on this return so that duplicate extensions (extensions with the
32330 same name as a previous extension in the list) are not considered
32331 for command-line parsing. */
32335 if (opt
->name
== NULL
)
32336 as_bad (_("unknown architecture extension `%s'\n"), name
);
32338 *input_line_pointer
= saved_char
;
32339 ignore_rest_of_line ();
32342 /* Parse a .fpu directive. */
32345 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32347 const struct arm_option_fpu_value_table
*opt
;
32351 name
= input_line_pointer
;
32352 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32353 input_line_pointer
++;
32354 saved_char
= *input_line_pointer
;
32355 *input_line_pointer
= 0;
32357 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32358 if (streq (opt
->name
, name
))
32360 selected_fpu
= opt
->value
;
32361 #ifndef CPU_DEFAULT
32362 if (no_cpu_selected ())
32363 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32366 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32367 *input_line_pointer
= saved_char
;
32368 demand_empty_rest_of_line ();
32372 as_bad (_("unknown floating point format `%s'\n"), name
);
32373 *input_line_pointer
= saved_char
;
32374 ignore_rest_of_line ();
32377 /* Copy symbol information. */
32380 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32382 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32386 /* Given a symbolic attribute NAME, return the proper integer value.
32387 Returns -1 if the attribute is not known. */
32390 arm_convert_symbolic_attribute (const char *name
)
32392 static const struct
32397 attribute_table
[] =
32399 /* When you modify this table you should
32400 also modify the list in doc/c-arm.texi. */
32401 #define T(tag) {#tag, tag}
32402 T (Tag_CPU_raw_name
),
32405 T (Tag_CPU_arch_profile
),
32406 T (Tag_ARM_ISA_use
),
32407 T (Tag_THUMB_ISA_use
),
32411 T (Tag_Advanced_SIMD_arch
),
32412 T (Tag_PCS_config
),
32413 T (Tag_ABI_PCS_R9_use
),
32414 T (Tag_ABI_PCS_RW_data
),
32415 T (Tag_ABI_PCS_RO_data
),
32416 T (Tag_ABI_PCS_GOT_use
),
32417 T (Tag_ABI_PCS_wchar_t
),
32418 T (Tag_ABI_FP_rounding
),
32419 T (Tag_ABI_FP_denormal
),
32420 T (Tag_ABI_FP_exceptions
),
32421 T (Tag_ABI_FP_user_exceptions
),
32422 T (Tag_ABI_FP_number_model
),
32423 T (Tag_ABI_align_needed
),
32424 T (Tag_ABI_align8_needed
),
32425 T (Tag_ABI_align_preserved
),
32426 T (Tag_ABI_align8_preserved
),
32427 T (Tag_ABI_enum_size
),
32428 T (Tag_ABI_HardFP_use
),
32429 T (Tag_ABI_VFP_args
),
32430 T (Tag_ABI_WMMX_args
),
32431 T (Tag_ABI_optimization_goals
),
32432 T (Tag_ABI_FP_optimization_goals
),
32433 T (Tag_compatibility
),
32434 T (Tag_CPU_unaligned_access
),
32435 T (Tag_FP_HP_extension
),
32436 T (Tag_VFP_HP_extension
),
32437 T (Tag_ABI_FP_16bit_format
),
32438 T (Tag_MPextension_use
),
32440 T (Tag_nodefaults
),
32441 T (Tag_also_compatible_with
),
32442 T (Tag_conformance
),
32444 T (Tag_Virtualization_use
),
32445 T (Tag_DSP_extension
),
32447 /* We deliberately do not include Tag_MPextension_use_legacy. */
32455 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32456 if (streq (name
, attribute_table
[i
].name
))
32457 return attribute_table
[i
].tag
;
32462 /* Apply sym value for relocations only in the case that they are for
32463 local symbols in the same segment as the fixup and you have the
32464 respective architectural feature for blx and simple switches. */
32467 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32470 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32471 /* PR 17444: If the local symbol is in a different section then a reloc
32472 will always be generated for it, so applying the symbol value now
32473 will result in a double offset being stored in the relocation. */
32474 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32475 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32477 switch (fixP
->fx_r_type
)
32479 case BFD_RELOC_ARM_PCREL_BLX
:
32480 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32481 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32485 case BFD_RELOC_ARM_PCREL_CALL
:
32486 case BFD_RELOC_THUMB_PCREL_BLX
:
32487 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32498 #endif /* OBJ_ELF */