1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS
* table_entry
;
61 symbolS
* personality_routine
;
62 int personality_index
;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes
;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset
;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored
:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency
= 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
119 #define CPU_DEFAULT ARM_ANY
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant
;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26
= FALSE
;
148 static int atpcs
= FALSE
;
149 static int support_interwork
= FALSE
;
150 static int uses_apcs_float
= FALSE
;
151 static int pic_code
= FALSE
;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu
= -1;
157 static int legacy_fpu
= -1;
159 static int mcpu_cpu_opt
= -1;
160 static int mcpu_fpu_opt
= -1;
161 static int march_cpu_opt
= -1;
162 static int march_fpu_opt
= -1;
163 static int mfpu_opt
= -1;
164 static int mfloat_abi_opt
= -1;
167 static int meabi_flags
= EABI_DEFAULT
;
169 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS
* GOT_symbol
;
178 /* Size of relocation record. */
179 const int md_reloc_size
= 8;
181 /* 0: assemble for ARM,
182 1: assemble for Thumb,
183 2: assemble for Thumb even though target CPU does not support thumb
185 static int thumb_mode
= 0;
187 /* If unified_syntax is true, we are processing the new unified
188 ARM/Thumb syntax. Important differences from the old ARM mode:
190 - Immediate operands do not require a # prefix.
191 - Conditional affixes always appear at the end of the
192 instruction. (For backward compatibility, those instructions
193 that formerly had them in the middle, continue to accept them
195 - The IT instruction may appear, and if it does is validated
196 against subsequent conditional affixes. It does not generate
199 Important differences from the old Thumb mode:
201 - Immediate operands do not require a # prefix.
202 - Most of the V6T2 instructions are only available in unified mode.
203 - The .N and .W suffixes are recognized and honored (it is an error
204 if they cannot be honored).
205 - All instructions set the flags if and only if they have an 's' affix.
206 - Conditional affixes may be used. They are validated against
207 preceding IT instructions. Unlike ARM mode, you cannot use a
208 conditional affix except in the scope of an IT instruction. */
210 static bfd_boolean unified_syntax
= FALSE
;
215 unsigned long instruction
;
221 bfd_reloc_code_real_type type
;
230 unsigned present
: 1; /* operand present */
231 unsigned isreg
: 1; /* operand was a register */
232 unsigned immisreg
: 1; /* .imm field is a second register */
233 unsigned hasreloc
: 1; /* operand has relocation suffix */
234 unsigned writeback
: 1; /* operand has trailing ! */
235 unsigned preind
: 1; /* preindexed address */
236 unsigned postind
: 1; /* postindexed address */
237 unsigned negative
: 1; /* index register was negated */
238 unsigned shifted
: 1; /* shift applied to operation */
239 unsigned shift_kind
: 3; /* shift operation (enum shift_kind) */
243 static struct arm_it inst
;
245 #define NUM_FLOAT_VALS 8
247 const char * fp_const
[] =
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
252 /* Number of littlenums required to hold an extended precision number. */
253 #define MAX_LITTLENUMS 6
255 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
265 #define CP_T_X 0x00008000
266 #define CP_T_Y 0x00400000
268 #define CONDS_BIT 0x00100000
269 #define LOAD_BIT 0x00100000
271 #define DOUBLE_LOAD_FLAG 0x00000001
275 const char * template;
279 #define COND_ALWAYS 0xE
283 const char *template;
287 /* The bit that distinguishes CPSR and SPSR. */
288 #define SPSR_BIT (1 << 22)
290 /* The individual PSR flag bits. */
291 #define PSR_c (1 << 16)
292 #define PSR_x (1 << 17)
293 #define PSR_s (1 << 18)
294 #define PSR_f (1 << 19)
299 bfd_reloc_code_real_type reloc
;
304 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
309 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
312 /* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
335 /* Structure for a hash table entry for a register. */
339 unsigned char number
;
341 unsigned char builtin
;
344 /* Diagnostics used when we don't get a register of the expected type. */
345 const char *const reg_expected_msgs
[] =
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
366 /* Some well known registers that we refer to directly elsewhere. */
371 /* ARM instructions take 4bytes in the object file, Thumb instructions
377 /* Basic string to match. */
378 const char *template;
380 /* Parameters to instruction. */
381 unsigned char operands
[8];
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag
: 4;
386 /* Basic instruction code. */
387 unsigned int avalue
: 28;
389 /* Thumb-format instruction code. */
392 /* Which architecture variant provides this instruction. */
393 unsigned long avariant
;
394 unsigned long tvariant
;
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode
) (void);
399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode
) (void);
403 /* Defines for various bits that we will want to toggle. */
404 #define INST_IMMEDIATE 0x02000000
405 #define OFFSET_REG 0x02000000
406 #define HWOFFSET_IMM 0x00400000
407 #define SHIFT_BY_REG 0x00000010
408 #define PRE_INDEX 0x01000000
409 #define INDEX_UP 0x00800000
410 #define WRITE_BACK 0x00200000
411 #define LDM_TYPE_2_OR_3 0x00400000
413 #define LITERAL_MASK 0xf000f000
414 #define OPCODE_MASK 0xfe1fffff
415 #define V4_STR_BIT 0x00000020
417 #define DATA_OP_SHIFT 21
419 /* Codes to distinguish the arithmetic instructions. */
430 #define OPCODE_CMP 10
431 #define OPCODE_CMN 11
432 #define OPCODE_ORR 12
433 #define OPCODE_MOV 13
434 #define OPCODE_BIC 14
435 #define OPCODE_MVN 15
437 #define T_OPCODE_MUL 0x4340
438 #define T_OPCODE_TST 0x4200
439 #define T_OPCODE_CMN 0x42c0
440 #define T_OPCODE_NEG 0x4240
441 #define T_OPCODE_MVN 0x43c0
443 #define T_OPCODE_ADD_R3 0x1800
444 #define T_OPCODE_SUB_R3 0x1a00
445 #define T_OPCODE_ADD_HI 0x4400
446 #define T_OPCODE_ADD_ST 0xb000
447 #define T_OPCODE_SUB_ST 0xb080
448 #define T_OPCODE_ADD_SP 0xa800
449 #define T_OPCODE_ADD_PC 0xa000
450 #define T_OPCODE_ADD_I8 0x3000
451 #define T_OPCODE_SUB_I8 0x3800
452 #define T_OPCODE_ADD_I3 0x1c00
453 #define T_OPCODE_SUB_I3 0x1e00
455 #define T_OPCODE_ASR_R 0x4100
456 #define T_OPCODE_LSL_R 0x4080
457 #define T_OPCODE_LSR_R 0x40c0
458 #define T_OPCODE_ROR_R 0x41c0
459 #define T_OPCODE_ASR_I 0x1000
460 #define T_OPCODE_LSL_I 0x0000
461 #define T_OPCODE_LSR_I 0x0800
463 #define T_OPCODE_MOV_I8 0x2000
464 #define T_OPCODE_CMP_I8 0x2800
465 #define T_OPCODE_CMP_LR 0x4280
466 #define T_OPCODE_MOV_HR 0x4600
467 #define T_OPCODE_CMP_HR 0x4500
469 #define T_OPCODE_LDR_PC 0x4800
470 #define T_OPCODE_LDR_SP 0x9800
471 #define T_OPCODE_STR_SP 0x9000
472 #define T_OPCODE_LDR_IW 0x6800
473 #define T_OPCODE_STR_IW 0x6000
474 #define T_OPCODE_LDR_IH 0x8800
475 #define T_OPCODE_STR_IH 0x8000
476 #define T_OPCODE_LDR_IB 0x7800
477 #define T_OPCODE_STR_IB 0x7000
478 #define T_OPCODE_LDR_RW 0x5800
479 #define T_OPCODE_STR_RW 0x5000
480 #define T_OPCODE_LDR_RH 0x5a00
481 #define T_OPCODE_STR_RH 0x5200
482 #define T_OPCODE_LDR_RB 0x5c00
483 #define T_OPCODE_STR_RB 0x5400
485 #define T_OPCODE_PUSH 0xb400
486 #define T_OPCODE_POP 0xbc00
488 #define T_OPCODE_BRANCH 0xe000
490 #define THUMB_SIZE 2 /* Size of thumb instruction. */
491 #define THUMB_PP_PC_LR 0x0100
492 #define THUMB_LOAD_BIT 0x0800
494 #define BAD_ARGS _("bad arguments to instruction")
495 #define BAD_PC _("r15 not allowed here")
496 #define BAD_COND _("instruction cannot be conditional")
497 #define BAD_OVERLAP _("registers may not be the same")
498 #define BAD_HIREG _("lo register required")
499 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
501 static struct hash_control
*arm_ops_hsh
;
502 static struct hash_control
*arm_cond_hsh
;
503 static struct hash_control
*arm_shift_hsh
;
504 static struct hash_control
*arm_psr_hsh
;
505 static struct hash_control
*arm_reg_hsh
;
506 static struct hash_control
*arm_reloc_hsh
;
508 /* Stuff needed to resolve the label ambiguity
518 symbolS
* last_label_seen
;
519 static int label_is_thumb_function_name
= FALSE
;
521 /* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
524 #define MAX_LITERAL_POOL_SIZE 1024
525 typedef struct literal_pool
527 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
528 unsigned int next_free_entry
;
533 struct literal_pool
* next
;
536 /* Pointer to a linked list of literal pools. */
537 literal_pool
* list_of_pools
= NULL
;
541 /* This array holds the chars that always start a comment. If the
542 pre-processor is disabled, these aren't very useful. */
543 const char comment_chars
[] = "@";
545 /* This array holds the chars that only start a comment at the beginning of
546 a line. If the line seems to have the form '# 123 filename'
547 .line and .file directives will appear in the pre-processed output. */
548 /* Note that input_file.c hand checks for '#' at the beginning of the
549 first line of the input file. This is because the compiler outputs
550 #NO_APP at the beginning of its output. */
551 /* Also note that comments like this one will always work. */
552 const char line_comment_chars
[] = "#";
554 const char line_separator_chars
[] = ";";
556 /* Chars that can be used to separate mant
557 from exp in floating point numbers. */
558 const char EXP_CHARS
[] = "eE";
560 /* Chars that mean this number is a floating point constant. */
564 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
566 /* Prefix characters that indicate the start of an immediate
568 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
570 /* Separator character handling. */
572 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
575 skip_past_char (char ** str
, char c
)
585 #define skip_past_comma(str) skip_past_char (str, ',')
587 /* Arithmetic expressions (possibly involving symbols). */
589 /* Return TRUE if anything in the expression is a bignum. */
592 walk_no_bignums (symbolS
* sp
)
594 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
597 if (symbol_get_value_expression (sp
)->X_add_symbol
)
599 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
600 || (symbol_get_value_expression (sp
)->X_op_symbol
601 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
607 static int in_my_get_expression
= 0;
609 /* Third argument to my_get_expression. */
610 #define GE_NO_PREFIX 0
611 #define GE_IMM_PREFIX 1
612 #define GE_OPT_PREFIX 2
615 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
620 /* In unified syntax, all prefixes are optional. */
622 prefix_mode
= GE_OPT_PREFIX
;
626 case GE_NO_PREFIX
: break;
628 if (!is_immediate_prefix (**str
))
630 inst
.error
= _("immediate expression requires a # prefix");
636 if (is_immediate_prefix (**str
))
642 memset (ep
, 0, sizeof (expressionS
));
644 save_in
= input_line_pointer
;
645 input_line_pointer
= *str
;
646 in_my_get_expression
= 1;
647 seg
= expression (ep
);
648 in_my_get_expression
= 0;
650 if (ep
->X_op
== O_illegal
)
652 /* We found a bad expression in md_operand(). */
653 *str
= input_line_pointer
;
654 input_line_pointer
= save_in
;
655 if (inst
.error
== NULL
)
656 inst
.error
= _("bad expression");
661 if (seg
!= absolute_section
662 && seg
!= text_section
663 && seg
!= data_section
664 && seg
!= bss_section
665 && seg
!= undefined_section
)
667 inst
.error
= _("bad segment");
668 *str
= input_line_pointer
;
669 input_line_pointer
= save_in
;
674 /* Get rid of any bignums now, so that we don't generate an error for which
675 we can't establish a line number later on. Big numbers are never valid
676 in instructions, which is where this routine is always called. */
677 if (ep
->X_op
== O_big
679 && (walk_no_bignums (ep
->X_add_symbol
)
681 && walk_no_bignums (ep
->X_op_symbol
)))))
683 inst
.error
= _("invalid constant");
684 *str
= input_line_pointer
;
685 input_line_pointer
= save_in
;
689 *str
= input_line_pointer
;
690 input_line_pointer
= save_in
;
694 /* Turn a string in input_line_pointer into a floating point constant
695 of type TYPE, and store the appropriate bytes in *LITP. The number
696 of LITTLENUMS emitted is stored in *SIZEP. An error message is
697 returned, or NULL on OK.
699 Note that fp constants aren't represent in the normal way on the ARM.
700 In big endian mode, things are as expected. However, in little endian
701 mode fp constants are big-endian word-wise, and little-endian byte-wise
702 within the words. For example, (double) 1.1 in big endian mode is
703 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
704 the byte sequence 99 99 f1 3f 9a 99 99 99.
706 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
709 md_atof (int type
, char * litP
, int * sizeP
)
712 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
744 return _("bad call to MD_ATOF()");
747 t
= atof_ieee (input_line_pointer
, type
, words
);
749 input_line_pointer
= t
;
752 if (target_big_endian
)
754 for (i
= 0; i
< prec
; i
++)
756 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
762 if (cpu_variant
& FPU_ARCH_VFP
)
763 for (i
= prec
- 1; i
>= 0; i
--)
765 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
769 /* For a 4 byte float the order of elements in `words' is 1 0.
770 For an 8 byte float the order is 1 0 3 2. */
771 for (i
= 0; i
< prec
; i
+= 2)
773 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
774 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
782 /* We handle all bad expressions here, so that we can report the faulty
783 instruction in the error message. */
785 md_operand (expressionS
* expr
)
787 if (in_my_get_expression
)
788 expr
->X_op
= O_illegal
;
791 /* Immediate values. */
793 /* Generic immediate-value read function for use in directives.
794 Accepts anything that 'expression' can fold to a constant.
795 *val receives the number. */
798 immediate_for_directive (int *val
)
801 exp
.X_op
= O_illegal
;
803 if (is_immediate_prefix (*input_line_pointer
))
805 input_line_pointer
++;
809 if (exp
.X_op
!= O_constant
)
811 as_bad (_("expected #constant"));
812 ignore_rest_of_line ();
815 *val
= exp
.X_add_number
;
820 /* Register parsing. */
822 /* Generic register parser. CCP points to what should be the
823 beginning of a register name. If it is indeed a valid register
824 name, advance CCP over it and return the reg_entry structure;
825 otherwise return NULL. Does not issue diagnostics. */
827 static struct reg_entry
*
828 arm_reg_parse_multi (char **ccp
)
832 struct reg_entry
*reg
;
834 #ifdef REGISTER_PREFIX
835 if (*start
!= REGISTER_PREFIX
)
839 #ifdef OPTIONAL_REGISTER_PREFIX
840 if (*start
== OPTIONAL_REGISTER_PREFIX
)
845 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
850 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
852 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
861 /* As above, but the register must be of type TYPE, and the return
862 value is the register number or NULL. */
865 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
868 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
870 if (reg
&& reg
->type
== type
)
873 /* Alternative syntaxes are accepted for a few register classes. */
880 /* Generic coprocessor register names are allowed for these. */
881 if (reg
->type
== REG_TYPE_CN
)
886 /* For backward compatibility, a bare number is valid here. */
888 unsigned long processor
= strtoul (start
, ccp
, 10);
889 if (*ccp
!= start
&& processor
<= 15)
894 /* WC includes WCG. ??? I'm not sure this is true for all
895 instructions that take WC registers. */
896 if (reg
->type
== REG_TYPE_MMXWCG
)
908 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
910 parse_reg_list (char ** strp
)
916 /* We come back here if we get ranges concatenated by '+' or '|'. */
931 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
933 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
943 inst
.error
= _("bad range in register list");
947 for (i
= cur_reg
+ 1; i
< reg
; i
++)
949 if (range
& (1 << i
))
951 (_("Warning: duplicated register (r%d) in register list"),
959 if (range
& (1 << reg
))
960 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
962 else if (reg
<= cur_reg
)
963 as_tsktsk (_("Warning: register range not in ascending order"));
968 while (skip_past_comma (&str
) != FAIL
969 || (in_range
= 1, *str
++ == '-'));
974 inst
.error
= _("missing `}'");
982 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
985 if (expr
.X_op
== O_constant
)
987 if (expr
.X_add_number
988 != (expr
.X_add_number
& 0x0000ffff))
990 inst
.error
= _("invalid register mask");
994 if ((range
& expr
.X_add_number
) != 0)
996 int regno
= range
& expr
.X_add_number
;
999 regno
= (1 << regno
) - 1;
1001 (_("Warning: duplicated register (r%d) in register list"),
1005 range
|= expr
.X_add_number
;
1009 if (inst
.reloc
.type
!= 0)
1011 inst
.error
= _("expression too complex");
1015 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1016 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1017 inst
.reloc
.pc_rel
= 0;
1021 if (*str
== '|' || *str
== '+')
1027 while (another_range
);
1033 /* Parse a VFP register list. If the string is invalid return FAIL.
1034 Otherwise return the number of registers, and set PBASE to the first
1035 register. Double precision registers are matched if DP is nonzero. */
1038 parse_vfp_reg_list (char **str
, int *pbase
, int dp
)
1046 unsigned long mask
= 0;
1056 regtype
= REG_TYPE_VFD
;
1061 regtype
= REG_TYPE_VFS
;
1065 base_reg
= max_regs
;
1069 new_base
= arm_reg_parse (str
, regtype
);
1070 if (new_base
== FAIL
)
1072 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1076 if (new_base
< base_reg
)
1077 base_reg
= new_base
;
1079 if (mask
& (1 << new_base
))
1081 inst
.error
= _("invalid register list");
1085 if ((mask
>> new_base
) != 0 && ! warned
)
1087 as_tsktsk (_("register list not in ascending order"));
1091 mask
|= 1 << new_base
;
1094 if (**str
== '-') /* We have the start of a range expression */
1100 if ((high_range
= arm_reg_parse (str
, regtype
)) == FAIL
)
1102 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1106 if (high_range
<= new_base
)
1108 inst
.error
= _("register range not in ascending order");
1112 for (new_base
++; new_base
<= high_range
; new_base
++)
1114 if (mask
& (1 << new_base
))
1116 inst
.error
= _("invalid register list");
1120 mask
|= 1 << new_base
;
1125 while (skip_past_comma (str
) != FAIL
);
1129 /* Sanity check -- should have raised a parse error above. */
1130 if (count
== 0 || count
> max_regs
)
1135 /* Final test -- the registers must be consecutive. */
1137 for (i
= 0; i
< count
; i
++)
1139 if ((mask
& (1u << i
)) == 0)
1141 inst
.error
= _("non-contiguous register range");
1149 /* Parse an explicit relocation suffix on an expression. This is
1150 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1151 arm_reloc_hsh contains no entries, so this function can only
1152 succeed if there is no () after the word. Returns -1 on error,
1153 BFD_RELOC_UNUSED if there wasn't any suffix. */
1155 parse_reloc (char **str
)
1157 struct reloc_entry
*r
;
1161 return BFD_RELOC_UNUSED
;
1166 while (*q
&& *q
!= ')' && *q
!= ',')
1171 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1178 /* Directives: register aliases. */
1181 insert_reg_alias (char *str
, int number
, int type
)
1183 struct reg_entry
*new;
1186 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1189 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1191 /* Only warn about a redefinition if it's not defined as the
1193 else if (new->number
!= number
|| new->type
!= type
)
1194 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1199 name
= xstrdup (str
);
1200 new = xmalloc (sizeof (struct reg_entry
));
1203 new->number
= number
;
1205 new->builtin
= FALSE
;
1207 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1211 /* Look for the .req directive. This is of the form:
1213 new_register_name .req existing_register_name
1215 If we find one, or if it looks sufficiently like one that we want to
1216 handle any error here, return non-zero. Otherwise return zero. */
1219 create_register_alias (char * newname
, char *p
)
1221 struct reg_entry
*old
;
1222 char *oldname
, *nbuf
;
1225 /* The input scrubber ensures that whitespace after the mnemonic is
1226 collapsed to single spaces. */
1228 if (strncmp (oldname
, " .req ", 6) != 0)
1232 if (*oldname
== '\0')
1235 old
= hash_find (arm_reg_hsh
, oldname
);
1238 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1242 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1243 the desired alias name, and p points to its end. If not, then
1244 the desired alias name is in the global original_case_string. */
1245 #ifdef TC_CASE_SENSITIVE
1248 newname
= original_case_string
;
1249 nlen
= strlen (newname
);
1252 nbuf
= alloca (nlen
+ 1);
1253 memcpy (nbuf
, newname
, nlen
);
1256 /* Create aliases under the new name as stated; an all-lowercase
1257 version of the new name; and an all-uppercase version of the new
1259 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1261 for (p
= nbuf
; *p
; p
++)
1264 if (strncmp (nbuf
, newname
, nlen
))
1265 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1267 for (p
= nbuf
; *p
; p
++)
1270 if (strncmp (nbuf
, newname
, nlen
))
1271 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1276 /* Should never be called, as .req goes between the alias and the
1277 register name, not at the beginning of the line. */
1279 s_req (int a ATTRIBUTE_UNUSED
)
1281 as_bad (_("invalid syntax for .req directive"));
1284 /* The .unreq directive deletes an alias which was previously defined
1285 by .req. For example:
1291 s_unreq (int a ATTRIBUTE_UNUSED
)
1296 name
= input_line_pointer
;
1298 while (*input_line_pointer
!= 0
1299 && *input_line_pointer
!= ' '
1300 && *input_line_pointer
!= '\n')
1301 ++input_line_pointer
;
1303 saved_char
= *input_line_pointer
;
1304 *input_line_pointer
= 0;
1307 as_bad (_("invalid syntax for .unreq directive"));
1310 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
1313 as_bad (_("unknown register alias '%s'"), name
);
1314 else if (reg
->builtin
)
1315 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1319 hash_delete (arm_reg_hsh
, name
);
1320 free ((char *) reg
->name
);
1325 *input_line_pointer
= saved_char
;
1326 demand_empty_rest_of_line ();
1329 /* Directives: Instruction set selection. */
1332 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1333 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1334 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1335 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1337 static enum mstate mapstate
= MAP_UNDEFINED
;
1340 mapping_state (enum mstate state
)
1343 const char * symname
;
1346 if (mapstate
== state
)
1347 /* The mapping symbol has already been emitted.
1348 There is nothing else to do. */
1357 type
= BSF_NO_FLAGS
;
1361 type
= BSF_NO_FLAGS
;
1365 type
= BSF_NO_FLAGS
;
1373 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1375 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
1376 symbol_table_insert (symbolP
);
1377 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1382 THUMB_SET_FUNC (symbolP
, 0);
1383 ARM_SET_THUMB (symbolP
, 0);
1384 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1388 THUMB_SET_FUNC (symbolP
, 1);
1389 ARM_SET_THUMB (symbolP
, 1);
1390 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1399 #define mapping_state(x) /* nothing */
1402 /* Find the real, Thumb encoded start of a Thumb function. */
1405 find_real_start (symbolS
* symbolP
)
1408 const char * name
= S_GET_NAME (symbolP
);
1409 symbolS
* new_target
;
1411 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1412 #define STUB_NAME ".real_start_of"
1417 /* The compiler may generate BL instructions to local labels because
1418 it needs to perform a branch to a far away location. These labels
1419 do not have a corresponding ".real_start_of" label. We check
1420 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1421 the ".real_start_of" convention for nonlocal branches. */
1422 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
1425 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
1426 new_target
= symbol_find (real_start
);
1428 if (new_target
== NULL
)
1430 as_warn ("Failed to find real start of function: %s\n", name
);
1431 new_target
= symbolP
;
1438 opcode_select (int width
)
1445 if (! (cpu_variant
& ARM_EXT_V4T
))
1446 as_bad (_("selected processor does not support THUMB opcodes"));
1449 /* No need to force the alignment, since we will have been
1450 coming from ARM mode, which is word-aligned. */
1451 record_alignment (now_seg
, 1);
1453 mapping_state (MAP_THUMB
);
1459 if ((cpu_variant
& ARM_ALL
) == ARM_EXT_V4T
)
1460 as_bad (_("selected processor does not support ARM opcodes"));
1465 frag_align (2, 0, 0);
1467 record_alignment (now_seg
, 1);
1469 mapping_state (MAP_ARM
);
1473 as_bad (_("invalid instruction size selected (%d)"), width
);
1478 s_arm (int ignore ATTRIBUTE_UNUSED
)
1481 demand_empty_rest_of_line ();
1485 s_thumb (int ignore ATTRIBUTE_UNUSED
)
1488 demand_empty_rest_of_line ();
1492 s_code (int unused ATTRIBUTE_UNUSED
)
1496 temp
= get_absolute_expression ();
1501 opcode_select (temp
);
1505 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1510 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
1512 /* If we are not already in thumb mode go into it, EVEN if
1513 the target processor does not support thumb instructions.
1514 This is used by gcc/config/arm/lib1funcs.asm for example
1515 to compile interworking support functions even if the
1516 target processor should not support interworking. */
1520 record_alignment (now_seg
, 1);
1523 demand_empty_rest_of_line ();
1527 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
1531 /* The following label is the name/address of the start of a Thumb function.
1532 We need to know this for the interworking support. */
1533 label_is_thumb_function_name
= TRUE
;
1536 /* Perform a .set directive, but also mark the alias as
1537 being a thumb function. */
1540 s_thumb_set (int equiv
)
1542 /* XXX the following is a duplicate of the code for s_set() in read.c
1543 We cannot just call that code as we need to get at the symbol that
1550 /* Especial apologies for the random logic:
1551 This just grew, and could be parsed much more simply!
1553 name
= input_line_pointer
;
1554 delim
= get_symbol_end ();
1555 end_name
= input_line_pointer
;
1558 if (*input_line_pointer
!= ',')
1561 as_bad (_("expected comma after name \"%s\""), name
);
1563 ignore_rest_of_line ();
1567 input_line_pointer
++;
1570 if (name
[0] == '.' && name
[1] == '\0')
1572 /* XXX - this should not happen to .thumb_set. */
1576 if ((symbolP
= symbol_find (name
)) == NULL
1577 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1580 /* When doing symbol listings, play games with dummy fragments living
1581 outside the normal fragment chain to record the file and line info
1583 if (listing
& LISTING_SYMBOLS
)
1585 extern struct list_info_struct
* listing_tail
;
1586 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
1588 memset (dummy_frag
, 0, sizeof (fragS
));
1589 dummy_frag
->fr_type
= rs_fill
;
1590 dummy_frag
->line
= listing_tail
;
1591 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1592 dummy_frag
->fr_symbol
= symbolP
;
1596 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1599 /* "set" symbols are local unless otherwise specified. */
1600 SF_SET_LOCAL (symbolP
);
1601 #endif /* OBJ_COFF */
1602 } /* Make a new symbol. */
1604 symbol_table_insert (symbolP
);
1609 && S_IS_DEFINED (symbolP
)
1610 && S_GET_SEGMENT (symbolP
) != reg_section
)
1611 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1613 pseudo_set (symbolP
);
1615 demand_empty_rest_of_line ();
1617 /* XXX Now we come to the Thumb specific bit of code. */
1619 THUMB_SET_FUNC (symbolP
, 1);
1620 ARM_SET_THUMB (symbolP
, 1);
1621 #if defined OBJ_ELF || defined OBJ_COFF
1622 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1626 /* Directives: Mode selection. */
1628 /* .syntax [unified|divided] - choose the new unified syntax
1629 (same for Arm and Thumb encoding, modulo slight differences in what
1630 can be represented) or the old divergent syntax for each mode. */
1632 s_syntax (int unused ATTRIBUTE_UNUSED
)
1636 name
= input_line_pointer
;
1637 delim
= get_symbol_end ();
1639 if (!strcasecmp (name
, "unified"))
1640 unified_syntax
= TRUE
;
1641 else if (!strcasecmp (name
, "divided"))
1642 unified_syntax
= FALSE
;
1645 as_bad (_("unrecognized syntax mode \"%s\""), name
);
1648 *input_line_pointer
= delim
;
1649 demand_empty_rest_of_line ();
1652 /* Directives: sectioning and alignment. */
1654 /* Same as s_align_ptwo but align 0 => align 2. */
1657 s_align (int unused ATTRIBUTE_UNUSED
)
1661 long max_alignment
= 15;
1663 temp
= get_absolute_expression ();
1664 if (temp
> max_alignment
)
1665 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
1668 as_bad (_("alignment negative. 0 assumed."));
1672 if (*input_line_pointer
== ',')
1674 input_line_pointer
++;
1675 temp_fill
= get_absolute_expression ();
1683 /* Only make a frag if we HAVE to. */
1684 if (temp
&& !need_pass_2
)
1685 frag_align (temp
, (int) temp_fill
, 0);
1686 demand_empty_rest_of_line ();
1688 record_alignment (now_seg
, temp
);
1692 s_bss (int ignore ATTRIBUTE_UNUSED
)
1694 /* We don't support putting frags in the BSS segment, we fake it by
1695 marking in_bss, then looking at s_skip for clues. */
1696 subseg_set (bss_section
, 0);
1697 demand_empty_rest_of_line ();
1698 mapping_state (MAP_DATA
);
1702 s_even (int ignore ATTRIBUTE_UNUSED
)
1704 /* Never make frag if expect extra pass. */
1706 frag_align (1, 0, 0);
1708 record_alignment (now_seg
, 1);
1710 demand_empty_rest_of_line ();
1713 /* Directives: Literal pools. */
1715 static literal_pool
*
1716 find_literal_pool (void)
1718 literal_pool
* pool
;
1720 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1722 if (pool
->section
== now_seg
1723 && pool
->sub_section
== now_subseg
)
1730 static literal_pool
*
1731 find_or_make_literal_pool (void)
1733 /* Next literal pool ID number. */
1734 static unsigned int latest_pool_num
= 1;
1735 literal_pool
* pool
;
1737 pool
= find_literal_pool ();
1741 /* Create a new pool. */
1742 pool
= xmalloc (sizeof (* pool
));
1746 pool
->next_free_entry
= 0;
1747 pool
->section
= now_seg
;
1748 pool
->sub_section
= now_subseg
;
1749 pool
->next
= list_of_pools
;
1750 pool
->symbol
= NULL
;
1752 /* Add it to the list. */
1753 list_of_pools
= pool
;
1756 /* New pools, and emptied pools, will have a NULL symbol. */
1757 if (pool
->symbol
== NULL
)
1759 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1760 (valueT
) 0, &zero_address_frag
);
1761 pool
->id
= latest_pool_num
++;
1768 /* Add the literal in the global 'inst'
1769 structure to the relevent literal pool. */
1772 add_to_lit_pool (void)
1774 literal_pool
* pool
;
1777 pool
= find_or_make_literal_pool ();
1779 /* Check if this literal value is already in the pool. */
1780 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1782 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1783 && (inst
.reloc
.exp
.X_op
== O_constant
)
1784 && (pool
->literals
[entry
].X_add_number
1785 == inst
.reloc
.exp
.X_add_number
)
1786 && (pool
->literals
[entry
].X_unsigned
1787 == inst
.reloc
.exp
.X_unsigned
))
1790 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1791 && (inst
.reloc
.exp
.X_op
== O_symbol
)
1792 && (pool
->literals
[entry
].X_add_number
1793 == inst
.reloc
.exp
.X_add_number
)
1794 && (pool
->literals
[entry
].X_add_symbol
1795 == inst
.reloc
.exp
.X_add_symbol
)
1796 && (pool
->literals
[entry
].X_op_symbol
1797 == inst
.reloc
.exp
.X_op_symbol
))
1801 /* Do we need to create a new entry? */
1802 if (entry
== pool
->next_free_entry
)
1804 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1806 inst
.error
= _("literal pool overflow");
1810 pool
->literals
[entry
] = inst
.reloc
.exp
;
1811 pool
->next_free_entry
+= 1;
1814 inst
.reloc
.exp
.X_op
= O_symbol
;
1815 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
1816 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
1821 /* Can't use symbol_new here, so have to create a symbol and then at
1822 a later date assign it a value. Thats what these functions do. */
1825 symbol_locate (symbolS
* symbolP
,
1826 const char * name
, /* It is copied, the caller can modify. */
1827 segT segment
, /* Segment identifier (SEG_<something>). */
1828 valueT valu
, /* Symbol value. */
1829 fragS
* frag
) /* Associated fragment. */
1831 unsigned int name_length
;
1832 char * preserved_copy_of_name
;
1834 name_length
= strlen (name
) + 1; /* +1 for \0. */
1835 obstack_grow (¬es
, name
, name_length
);
1836 preserved_copy_of_name
= obstack_finish (¬es
);
1838 #ifdef tc_canonicalize_symbol_name
1839 preserved_copy_of_name
=
1840 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1843 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1845 S_SET_SEGMENT (symbolP
, segment
);
1846 S_SET_VALUE (symbolP
, valu
);
1847 symbol_clear_list_pointers (symbolP
);
1849 symbol_set_frag (symbolP
, frag
);
1851 /* Link to end of symbol chain. */
1853 extern int symbol_table_frozen
;
1855 if (symbol_table_frozen
)
1859 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1861 obj_symbol_new_hook (symbolP
);
1863 #ifdef tc_symbol_new_hook
1864 tc_symbol_new_hook (symbolP
);
1868 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1869 #endif /* DEBUG_SYMS */
1874 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1877 literal_pool
* pool
;
1880 pool
= find_literal_pool ();
1882 || pool
->symbol
== NULL
1883 || pool
->next_free_entry
== 0)
1886 mapping_state (MAP_DATA
);
1888 /* Align pool as you have word accesses.
1889 Only make a frag if we have to. */
1891 frag_align (2, 0, 0);
1893 record_alignment (now_seg
, 2);
1895 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1897 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1898 (valueT
) frag_now_fix (), frag_now
);
1899 symbol_table_insert (pool
->symbol
);
1901 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
1903 #if defined OBJ_COFF || defined OBJ_ELF
1904 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
1907 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1908 /* First output the expression in the instruction to the pool. */
1909 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
1911 /* Mark the pool as empty. */
1912 pool
->next_free_entry
= 0;
1913 pool
->symbol
= NULL
;
1917 /* Forward declarations for functions below, in the MD interface
1919 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
1920 static valueT
create_unwind_entry (int);
1921 static void start_unwind_section (const segT
, int);
1922 static void add_unwind_opcode (valueT
, int);
1923 static void flush_pending_unwind (void);
1925 /* Directives: Data. */
1928 s_arm_elf_cons (int nbytes
)
1932 #ifdef md_flush_pending_output
1933 md_flush_pending_output ();
1936 if (is_it_end_of_statement ())
1938 demand_empty_rest_of_line ();
1942 #ifdef md_cons_align
1943 md_cons_align (nbytes
);
1946 mapping_state (MAP_DATA
);
1950 char *base
= input_line_pointer
;
1954 if (exp
.X_op
!= O_symbol
)
1955 emit_expr (&exp
, (unsigned int) nbytes
);
1958 char *before_reloc
= input_line_pointer
;
1959 reloc
= parse_reloc (&input_line_pointer
);
1962 as_bad (_("unrecognized relocation suffix"));
1963 ignore_rest_of_line ();
1966 else if (reloc
== BFD_RELOC_UNUSED
)
1967 emit_expr (&exp
, (unsigned int) nbytes
);
1970 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
1971 int size
= bfd_get_reloc_size (howto
);
1973 if (reloc
== BFD_RELOC_ARM_PLT32
)
1975 as_bad (_("(plt) is only valid on branch targets"));
1976 reloc
= BFD_RELOC_UNUSED
;
1981 as_bad (_("%s relocations do not fit in %d bytes"),
1982 howto
->name
, nbytes
);
1985 /* We've parsed an expression stopping at O_symbol.
1986 But there may be more expression left now that we
1987 have parsed the relocation marker. Parse it again.
1988 XXX Surely there is a cleaner way to do this. */
1989 char *p
= input_line_pointer
;
1991 char *save_buf
= alloca (input_line_pointer
- base
);
1992 memcpy (save_buf
, base
, input_line_pointer
- base
);
1993 memmove (base
+ (input_line_pointer
- before_reloc
),
1994 base
, before_reloc
- base
);
1996 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
1998 memcpy (base
, save_buf
, p
- base
);
2000 offset
= nbytes
- size
;
2001 p
= frag_more ((int) nbytes
);
2002 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2003 size
, &exp
, 0, reloc
);
2008 while (*input_line_pointer
++ == ',');
2010 /* Put terminator back into stream. */
2011 input_line_pointer
--;
2012 demand_empty_rest_of_line ();
2016 /* Parse a .rel31 directive. */
2019 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2026 if (*input_line_pointer
== '1')
2027 highbit
= 0x80000000;
2028 else if (*input_line_pointer
!= '0')
2029 as_bad (_("expected 0 or 1"));
2031 input_line_pointer
++;
2032 if (*input_line_pointer
!= ',')
2033 as_bad (_("missing comma"));
2034 input_line_pointer
++;
2036 #ifdef md_flush_pending_output
2037 md_flush_pending_output ();
2040 #ifdef md_cons_align
2044 mapping_state (MAP_DATA
);
2049 md_number_to_chars (p
, highbit
, 4);
2050 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2051 BFD_RELOC_ARM_PREL31
);
2053 demand_empty_rest_of_line ();
2056 /* Directives: AEABI stack-unwind tables. */
2058 /* Parse an unwind_fnstart directive. Simply records the current location. */
2061 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
2063 demand_empty_rest_of_line ();
2064 /* Mark the start of the function. */
2065 unwind
.proc_start
= expr_build_dot ();
2067 /* Reset the rest of the unwind info. */
2068 unwind
.opcode_count
= 0;
2069 unwind
.table_entry
= NULL
;
2070 unwind
.personality_routine
= NULL
;
2071 unwind
.personality_index
= -1;
2072 unwind
.frame_size
= 0;
2073 unwind
.fp_offset
= 0;
2076 unwind
.sp_restored
= 0;
2080 /* Parse a handlerdata directive. Creates the exception handling table entry
2081 for the function. */
2084 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
2086 demand_empty_rest_of_line ();
2087 if (unwind
.table_entry
)
2088 as_bad (_("dupicate .handlerdata directive"));
2090 create_unwind_entry (1);
2093 /* Parse an unwind_fnend directive. Generates the index table entry. */
2096 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
2102 demand_empty_rest_of_line ();
2104 /* Add eh table entry. */
2105 if (unwind
.table_entry
== NULL
)
2106 val
= create_unwind_entry (0);
2110 /* Add index table entry. This is two words. */
2111 start_unwind_section (unwind
.saved_seg
, 1);
2112 frag_align (2, 0, 0);
2113 record_alignment (now_seg
, 2);
2115 ptr
= frag_more (8);
2116 where
= frag_now_fix () - 8;
2118 /* Self relative offset of the function start. */
2119 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
2120 BFD_RELOC_ARM_PREL31
);
2122 /* Indicate dependency on EHABI-defined personality routines to the
2123 linker, if it hasn't been done already. */
2124 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
2125 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
2127 static const char *const name
[] = {
2128 "__aeabi_unwind_cpp_pr0",
2129 "__aeabi_unwind_cpp_pr1",
2130 "__aeabi_unwind_cpp_pr2"
2132 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
2133 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
2134 marked_pr_dependency
|= 1 << unwind
.personality_index
;
2135 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
2136 = marked_pr_dependency
;
2140 /* Inline exception table entry. */
2141 md_number_to_chars (ptr
+ 4, val
, 4);
2143 /* Self relative offset of the table entry. */
2144 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
2145 BFD_RELOC_ARM_PREL31
);
2147 /* Restore the original section. */
2148 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
2152 /* Parse an unwind_cantunwind directive. */
2155 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
2157 demand_empty_rest_of_line ();
2158 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2159 as_bad (_("personality routine specified for cantunwind frame"));
2161 unwind
.personality_index
= -2;
2165 /* Parse a personalityindex directive. */
2168 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
2172 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2173 as_bad (_("duplicate .personalityindex directive"));
2177 if (exp
.X_op
!= O_constant
2178 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
2180 as_bad (_("bad personality routine number"));
2181 ignore_rest_of_line ();
2185 unwind
.personality_index
= exp
.X_add_number
;
2187 demand_empty_rest_of_line ();
2191 /* Parse a personality directive. */
2194 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
2198 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2199 as_bad (_("duplicate .personality directive"));
2201 name
= input_line_pointer
;
2202 c
= get_symbol_end ();
2203 p
= input_line_pointer
;
2204 unwind
.personality_routine
= symbol_find_or_make (name
);
2206 demand_empty_rest_of_line ();
2210 /* Parse a directive saving core registers. */
2213 s_arm_unwind_save_core (void)
2219 range
= parse_reg_list (&input_line_pointer
);
2222 as_bad (_("expected register list"));
2223 ignore_rest_of_line ();
2227 demand_empty_rest_of_line ();
2229 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2230 into .unwind_save {..., sp...}. We aren't bothered about the value of
2231 ip because it is clobbered by calls. */
2232 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
2233 && (range
& 0x3000) == 0x1000)
2235 unwind
.opcode_count
--;
2236 unwind
.sp_restored
= 0;
2237 range
= (range
| 0x2000) & ~0x1000;
2238 unwind
.pending_offset
= 0;
2241 /* See if we can use the short opcodes. These pop a block of upto 8
2242 registers starting with r4, plus maybe r14. */
2243 for (n
= 0; n
< 8; n
++)
2245 /* Break at the first non-saved register. */
2246 if ((range
& (1 << (n
+ 4))) == 0)
2249 /* See if there are any other bits set. */
2250 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
2252 /* Use the long form. */
2253 op
= 0x8000 | ((range
>> 4) & 0xfff);
2254 add_unwind_opcode (op
, 2);
2258 /* Use the short form. */
2260 op
= 0xa8; /* Pop r14. */
2262 op
= 0xa0; /* Do not pop r14. */
2264 add_unwind_opcode (op
, 1);
2270 op
= 0xb100 | (range
& 0xf);
2271 add_unwind_opcode (op
, 2);
2274 /* Record the number of bytes pushed. */
2275 for (n
= 0; n
< 16; n
++)
2277 if (range
& (1 << n
))
2278 unwind
.frame_size
+= 4;
2283 /* Parse a directive saving FPA registers. */
2286 s_arm_unwind_save_fpa (int reg
)
2292 /* Get Number of registers to transfer. */
2293 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2296 exp
.X_op
= O_illegal
;
2298 if (exp
.X_op
!= O_constant
)
2300 as_bad (_("expected , <constant>"));
2301 ignore_rest_of_line ();
2305 num_regs
= exp
.X_add_number
;
2307 if (num_regs
< 1 || num_regs
> 4)
2309 as_bad (_("number of registers must be in the range [1:4]"));
2310 ignore_rest_of_line ();
2314 demand_empty_rest_of_line ();
2319 op
= 0xb4 | (num_regs
- 1);
2320 add_unwind_opcode (op
, 1);
2325 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
2326 add_unwind_opcode (op
, 2);
2328 unwind
.frame_size
+= num_regs
* 12;
2332 /* Parse a directive saving VFP registers. */
2335 s_arm_unwind_save_vfp (void)
2341 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, 1);
2344 as_bad (_("expected register list"));
2345 ignore_rest_of_line ();
2349 demand_empty_rest_of_line ();
2354 op
= 0xb8 | (count
- 1);
2355 add_unwind_opcode (op
, 1);
2360 op
= 0xb300 | (reg
<< 4) | (count
- 1);
2361 add_unwind_opcode (op
, 2);
2363 unwind
.frame_size
+= count
* 8 + 4;
2367 /* Parse a directive saving iWMMXt data registers. */
2370 s_arm_unwind_save_mmxwr (void)
2378 if (*input_line_pointer
== '{')
2379 input_line_pointer
++;
2383 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2387 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2392 as_tsktsk (_("register list not in ascending order"));
2395 if (*input_line_pointer
== '-')
2397 input_line_pointer
++;
2398 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2401 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2404 else if (reg
>= hi_reg
)
2406 as_bad (_("bad register range"));
2409 for (; reg
< hi_reg
; reg
++)
2413 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2415 if (*input_line_pointer
== '}')
2416 input_line_pointer
++;
2418 demand_empty_rest_of_line ();
2420 /* Generate any deferred opcodes becuuse we're going to be looking at
2422 flush_pending_unwind ();
2424 for (i
= 0; i
< 16; i
++)
2426 if (mask
& (1 << i
))
2427 unwind
.frame_size
+= 8;
2430 /* Attempt to combine with a previous opcode. We do this because gcc
2431 likes to output separate unwind directives for a single block of
2433 if (unwind
.opcode_count
> 0)
2435 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
2436 if ((i
& 0xf8) == 0xc0)
2439 /* Only merge if the blocks are contiguous. */
2442 if ((mask
& 0xfe00) == (1 << 9))
2444 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
2445 unwind
.opcode_count
--;
2448 else if (i
== 6 && unwind
.opcode_count
>= 2)
2450 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
2454 op
= 0xffff << (reg
- 1);
2456 || ((mask
& op
) == (1u << (reg
- 1))))
2458 op
= (1 << (reg
+ i
+ 1)) - 1;
2459 op
&= ~((1 << reg
) - 1);
2461 unwind
.opcode_count
-= 2;
2468 /* We want to generate opcodes in the order the registers have been
2469 saved, ie. descending order. */
2470 for (reg
= 15; reg
>= -1; reg
--)
2472 /* Save registers in blocks. */
2474 || !(mask
& (1 << reg
)))
2476 /* We found an unsaved reg. Generate opcodes to save the
2477 preceeding block. */
2483 op
= 0xc0 | (hi_reg
- 10);
2484 add_unwind_opcode (op
, 1);
2489 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
2490 add_unwind_opcode (op
, 2);
2499 ignore_rest_of_line ();
2503 s_arm_unwind_save_mmxwcg (void)
2510 if (*input_line_pointer
== '{')
2511 input_line_pointer
++;
2515 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2519 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2525 as_tsktsk (_("register list not in ascending order"));
2528 if (*input_line_pointer
== '-')
2530 input_line_pointer
++;
2531 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2534 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2537 else if (reg
>= hi_reg
)
2539 as_bad (_("bad register range"));
2542 for (; reg
< hi_reg
; reg
++)
2546 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2548 if (*input_line_pointer
== '}')
2549 input_line_pointer
++;
2551 demand_empty_rest_of_line ();
2553 /* Generate any deferred opcodes becuuse we're going to be looking at
2555 flush_pending_unwind ();
2557 for (reg
= 0; reg
< 16; reg
++)
2559 if (mask
& (1 << reg
))
2560 unwind
.frame_size
+= 4;
2563 add_unwind_opcode (op
, 2);
2566 ignore_rest_of_line ();
2570 /* Parse an unwind_save directive. */
2573 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED
)
2576 struct reg_entry
*reg
;
2577 bfd_boolean had_brace
= FALSE
;
2579 /* Figure out what sort of save we have. */
2580 peek
= input_line_pointer
;
2588 reg
= arm_reg_parse_multi (&peek
);
2592 as_bad (_("register expected"));
2593 ignore_rest_of_line ();
2602 as_bad (_("FPA .unwind_save does not take a register list"));
2603 ignore_rest_of_line ();
2606 s_arm_unwind_save_fpa (reg
->number
);
2609 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
2610 case REG_TYPE_VFD
: s_arm_unwind_save_vfp (); return;
2611 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
2612 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
2615 as_bad (_(".unwind_save does not support this kind of register"));
2616 ignore_rest_of_line ();
2621 /* Parse an unwind_movsp directive. */
2624 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
2629 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2632 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
2633 ignore_rest_of_line ();
2636 demand_empty_rest_of_line ();
2638 if (reg
== REG_SP
|| reg
== REG_PC
)
2640 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2644 if (unwind
.fp_reg
!= REG_SP
)
2645 as_bad (_("unexpected .unwind_movsp directive"));
2647 /* Generate opcode to restore the value. */
2649 add_unwind_opcode (op
, 1);
2651 /* Record the information for later. */
2652 unwind
.fp_reg
= reg
;
2653 unwind
.fp_offset
= unwind
.frame_size
;
2654 unwind
.sp_restored
= 1;
2657 /* Parse an unwind_pad directive. */
2660 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
2664 if (immediate_for_directive (&offset
) == FAIL
)
2669 as_bad (_("stack increment must be multiple of 4"));
2670 ignore_rest_of_line ();
2674 /* Don't generate any opcodes, just record the details for later. */
2675 unwind
.frame_size
+= offset
;
2676 unwind
.pending_offset
+= offset
;
2678 demand_empty_rest_of_line ();
2681 /* Parse an unwind_setfp directive. */
2684 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
2690 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2691 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2694 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2696 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
2698 as_bad (_("expected <reg>, <reg>"));
2699 ignore_rest_of_line ();
2703 /* Optional constant. */
2704 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2706 if (immediate_for_directive (&offset
) == FAIL
)
2712 demand_empty_rest_of_line ();
2714 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
2716 as_bad (_("register must be either sp or set by a previous"
2717 "unwind_movsp directive"));
2721 /* Don't generate any opcodes, just record the information for later. */
2722 unwind
.fp_reg
= fp_reg
;
2725 unwind
.fp_offset
= unwind
.frame_size
- offset
;
2727 unwind
.fp_offset
-= offset
;
2730 /* Parse an unwind_raw directive. */
2733 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
2736 /* This is an arbitary limit. */
2737 unsigned char op
[16];
2741 if (exp
.X_op
== O_constant
2742 && skip_past_comma (&input_line_pointer
) != FAIL
)
2744 unwind
.frame_size
+= exp
.X_add_number
;
2748 exp
.X_op
= O_illegal
;
2750 if (exp
.X_op
!= O_constant
)
2752 as_bad (_("expected <offset>, <opcode>"));
2753 ignore_rest_of_line ();
2759 /* Parse the opcode. */
2764 as_bad (_("unwind opcode too long"));
2765 ignore_rest_of_line ();
2767 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
2769 as_bad (_("invalid unwind opcode"));
2770 ignore_rest_of_line ();
2773 op
[count
++] = exp
.X_add_number
;
2775 /* Parse the next byte. */
2776 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2782 /* Add the opcode bytes in reverse order. */
2784 add_unwind_opcode (op
[count
], 1);
2786 demand_empty_rest_of_line ();
2788 #endif /* OBJ_ELF */
2790 /* This table describes all the machine specific pseudo-ops the assembler
2791 has to support. The fields are:
2792 pseudo-op name without dot
2793 function to call to execute this pseudo-op
2794 Integer arg to pass to the function. */
2796 const pseudo_typeS md_pseudo_table
[] =
2798 /* Never called because '.req' does not start a line. */
2799 { "req", s_req
, 0 },
2800 { "unreq", s_unreq
, 0 },
2801 { "bss", s_bss
, 0 },
2802 { "align", s_align
, 0 },
2803 { "arm", s_arm
, 0 },
2804 { "thumb", s_thumb
, 0 },
2805 { "code", s_code
, 0 },
2806 { "force_thumb", s_force_thumb
, 0 },
2807 { "thumb_func", s_thumb_func
, 0 },
2808 { "thumb_set", s_thumb_set
, 0 },
2809 { "even", s_even
, 0 },
2810 { "ltorg", s_ltorg
, 0 },
2811 { "pool", s_ltorg
, 0 },
2812 { "syntax", s_syntax
, 0 },
2814 { "word", s_arm_elf_cons
, 4 },
2815 { "long", s_arm_elf_cons
, 4 },
2816 { "rel31", s_arm_rel31
, 0 },
2817 { "fnstart", s_arm_unwind_fnstart
, 0 },
2818 { "fnend", s_arm_unwind_fnend
, 0 },
2819 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
2820 { "personality", s_arm_unwind_personality
, 0 },
2821 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
2822 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
2823 { "save", s_arm_unwind_save
, 0 },
2824 { "movsp", s_arm_unwind_movsp
, 0 },
2825 { "pad", s_arm_unwind_pad
, 0 },
2826 { "setfp", s_arm_unwind_setfp
, 0 },
2827 { "unwind_raw", s_arm_unwind_raw
, 0 },
2831 { "extend", float_cons
, 'x' },
2832 { "ldouble", float_cons
, 'x' },
2833 { "packed", float_cons
, 'p' },
2837 /* Parser functions used exclusively in instruction operands. */
2839 /* Generic immediate-value read function for use in insn parsing.
2840 STR points to the beginning of the immediate (the leading #);
2841 VAL receives the value; if the value is outside [MIN, MAX]
2842 issue an error. PREFIX_OPT is true if the immediate prefix is
2846 parse_immediate (char **str
, int *val
, int min
, int max
,
2847 bfd_boolean prefix_opt
)
2850 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
2851 if (exp
.X_op
!= O_constant
)
2853 inst
.error
= _("constant expression required");
2857 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
2859 inst
.error
= _("immediate value out of range");
2863 *val
= exp
.X_add_number
;
2867 /* Returns the pseudo-register number of an FPA immediate constant,
2868 or FAIL if there isn't a valid constant here. */
2871 parse_fpa_immediate (char ** str
)
2873 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2879 /* First try and match exact strings, this is to guarantee
2880 that some formats will work even for cross assembly. */
2882 for (i
= 0; fp_const
[i
]; i
++)
2884 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2888 *str
+= strlen (fp_const
[i
]);
2889 if (is_end_of_line
[(unsigned char) **str
])
2895 /* Just because we didn't get a match doesn't mean that the constant
2896 isn't valid, just that it is in a format that we don't
2897 automatically recognize. Try parsing it with the standard
2898 expression routines. */
2900 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
2902 /* Look for a raw floating point number. */
2903 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
2904 && is_end_of_line
[(unsigned char) *save_in
])
2906 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2908 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2910 if (words
[j
] != fp_values
[i
][j
])
2914 if (j
== MAX_LITTLENUMS
)
2922 /* Try and parse a more complex expression, this will probably fail
2923 unless the code uses a floating point prefix (eg "0f"). */
2924 save_in
= input_line_pointer
;
2925 input_line_pointer
= *str
;
2926 if (expression (&exp
) == absolute_section
2927 && exp
.X_op
== O_big
2928 && exp
.X_add_number
< 0)
2930 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2932 if (gen_to_words (words
, 5, (long) 15) == 0)
2934 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2936 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2938 if (words
[j
] != fp_values
[i
][j
])
2942 if (j
== MAX_LITTLENUMS
)
2944 *str
= input_line_pointer
;
2945 input_line_pointer
= save_in
;
2952 *str
= input_line_pointer
;
2953 input_line_pointer
= save_in
;
2954 inst
.error
= _("invalid FPA immediate expression");
2958 /* Shift operands. */
2961 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
2964 struct asm_shift_name
2967 enum shift_kind kind
;
2970 /* Third argument to parse_shift. */
2971 enum parse_shift_mode
2973 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
2974 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
2975 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
2976 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
2977 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
2980 /* Parse a <shift> specifier on an ARM data processing instruction.
2981 This has three forms:
2983 (LSL|LSR|ASL|ASR|ROR) Rs
2984 (LSL|LSR|ASL|ASR|ROR) #imm
2987 Note that ASL is assimilated to LSL in the instruction encoding, and
2988 RRX to ROR #0 (which cannot be written as such). */
2991 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
2993 const struct asm_shift_name
*shift_name
;
2994 enum shift_kind shift
;
2999 for (p
= *str
; ISALPHA (*p
); p
++)
3004 inst
.error
= _("shift expression expected");
3008 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
3010 if (shift_name
== NULL
)
3012 inst
.error
= _("shift expression expected");
3016 shift
= shift_name
->kind
;
3020 case NO_SHIFT_RESTRICT
:
3021 case SHIFT_IMMEDIATE
: break;
3023 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
3024 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
3026 inst
.error
= _("'LSL' or 'ASR' required");
3031 case SHIFT_LSL_IMMEDIATE
:
3032 if (shift
!= SHIFT_LSL
)
3034 inst
.error
= _("'LSL' required");
3039 case SHIFT_ASR_IMMEDIATE
:
3040 if (shift
!= SHIFT_ASR
)
3042 inst
.error
= _("'ASR' required");
3050 if (shift
!= SHIFT_RRX
)
3052 /* Whitespace can appear here if the next thing is a bare digit. */
3053 skip_whitespace (p
);
3055 if (mode
== NO_SHIFT_RESTRICT
3056 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3058 inst
.operands
[i
].imm
= reg
;
3059 inst
.operands
[i
].immisreg
= 1;
3061 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3064 inst
.operands
[i
].shift_kind
= shift
;
3065 inst
.operands
[i
].shifted
= 1;
3070 /* Parse a <shifter_operand> for an ARM data processing instruction:
3073 #<immediate>, <rotate>
3077 where <shift> is defined by parse_shift above, and <rotate> is a
3078 multiple of 2 between 0 and 30. Validation of immediate operands
3079 is deferred to md_apply_fix. */
3082 parse_shifter_operand (char **str
, int i
)
3087 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
3089 inst
.operands
[i
].reg
= value
;
3090 inst
.operands
[i
].isreg
= 1;
3092 /* parse_shift will override this if appropriate */
3093 inst
.reloc
.exp
.X_op
= O_constant
;
3094 inst
.reloc
.exp
.X_add_number
= 0;
3096 if (skip_past_comma (str
) == FAIL
)
3099 /* Shift operation on register. */
3100 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
3103 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
3106 if (skip_past_comma (str
) == SUCCESS
)
3108 /* #x, y -- ie explicit rotation by Y. */
3109 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
3112 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
3114 inst
.error
= _("constant expression expected");
3118 value
= expr
.X_add_number
;
3119 if (value
< 0 || value
> 30 || value
% 2 != 0)
3121 inst
.error
= _("invalid rotation");
3124 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
3126 inst
.error
= _("invalid constant");
3130 /* Convert to decoded value. md_apply_fix will put it back. */
3131 inst
.reloc
.exp
.X_add_number
3132 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
3133 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
3136 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3137 inst
.reloc
.pc_rel
= 0;
3141 /* Parse all forms of an ARM address expression. Information is written
3142 to inst.operands[i] and/or inst.reloc.
3144 Preindexed addressing (.preind=1):
3146 [Rn, #offset] .reg=Rn .reloc.exp=offset
3147 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3148 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3149 .shift_kind=shift .reloc.exp=shift_imm
3151 These three may have a trailing ! which causes .writeback to be set also.
3153 Postindexed addressing (.postind=1, .writeback=1):
3155 [Rn], #offset .reg=Rn .reloc.exp=offset
3156 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3157 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3158 .shift_kind=shift .reloc.exp=shift_imm
3160 Unindexed addressing (.preind=0, .postind=0):
3162 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3166 [Rn]{!} shorthand for [Rn,#0]{!}
3167 =immediate .isreg=0 .reloc.exp=immediate
3168 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3170 It is the caller's responsibility to check for addressing modes not
3171 supported by the instruction, and to set inst.reloc.type. */
3174 parse_address (char **str
, int i
)
3179 if (skip_past_char (&p
, '[') == FAIL
)
3181 if (skip_past_char (&p
, '=') == FAIL
)
3183 /* bare address - translate to PC-relative offset */
3184 inst
.reloc
.pc_rel
= 1;
3185 inst
.operands
[i
].reg
= REG_PC
;
3186 inst
.operands
[i
].isreg
= 1;
3187 inst
.operands
[i
].preind
= 1;
3189 /* else a load-constant pseudo op, no special treatment needed here */
3191 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
3198 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3200 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3203 inst
.operands
[i
].reg
= reg
;
3204 inst
.operands
[i
].isreg
= 1;
3206 if (skip_past_comma (&p
) == SUCCESS
)
3208 inst
.operands
[i
].preind
= 1;
3211 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3213 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3215 inst
.operands
[i
].imm
= reg
;
3216 inst
.operands
[i
].immisreg
= 1;
3218 if (skip_past_comma (&p
) == SUCCESS
)
3219 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3224 if (inst
.operands
[i
].negative
)
3226 inst
.operands
[i
].negative
= 0;
3229 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3234 if (skip_past_char (&p
, ']') == FAIL
)
3236 inst
.error
= _("']' expected");
3240 if (skip_past_char (&p
, '!') == SUCCESS
)
3241 inst
.operands
[i
].writeback
= 1;
3243 else if (skip_past_comma (&p
) == SUCCESS
)
3245 if (skip_past_char (&p
, '{') == SUCCESS
)
3247 /* [Rn], {expr} - unindexed, with option */
3248 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
3249 0, 255, TRUE
) == FAIL
)
3252 if (skip_past_char (&p
, '}') == FAIL
)
3254 inst
.error
= _("'}' expected at end of 'option' field");
3257 if (inst
.operands
[i
].preind
)
3259 inst
.error
= _("cannot combine index with option");
3267 inst
.operands
[i
].postind
= 1;
3268 inst
.operands
[i
].writeback
= 1;
3270 if (inst
.operands
[i
].preind
)
3272 inst
.error
= _("cannot combine pre- and post-indexing");
3277 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3279 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3281 inst
.operands
[i
].imm
= reg
;
3282 inst
.operands
[i
].immisreg
= 1;
3284 if (skip_past_comma (&p
) == SUCCESS
)
3285 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3290 if (inst
.operands
[i
].negative
)
3292 inst
.operands
[i
].negative
= 0;
3295 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3301 /* If at this point neither .preind nor .postind is set, we have a
3302 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3303 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
3305 inst
.operands
[i
].preind
= 1;
3306 inst
.reloc
.exp
.X_op
= O_constant
;
3307 inst
.reloc
.exp
.X_add_number
= 0;
3313 /* Miscellaneous. */
3315 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3316 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3318 parse_psr (char **str
)
3321 unsigned long psr_field
;
3323 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3324 feature for ease of use and backwards compatibility. */
3326 if (*p
== 's' || *p
== 'S')
3327 psr_field
= SPSR_BIT
;
3328 else if (*p
== 'c' || *p
== 'C')
3334 if (strncasecmp (p
, "PSR", 3) != 0)
3340 /* A suffix follows. */
3341 const struct asm_psr
*psr
;
3349 while (ISALNUM (*p
) || *p
== '_');
3351 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
3355 psr_field
|= psr
->field
;
3360 goto error
; /* Garbage after "[CS]PSR". */
3362 psr_field
|= (PSR_c
| PSR_f
);
3368 inst
.error
= _("flag for {c}psr instruction expected");
3372 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3373 value suitable for splatting into the AIF field of the instruction. */
3376 parse_cps_flags (char **str
)
3385 case '\0': case ',':
3388 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
3389 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
3390 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
3393 inst
.error
= _("unrecognized CPS flag");
3398 if (saw_a_flag
== 0)
3400 inst
.error
= _("missing CPS flags");
3408 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3409 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3412 parse_endian_specifier (char **str
)
3417 if (strncasecmp (s
, "BE", 2))
3419 else if (strncasecmp (s
, "LE", 2))
3423 inst
.error
= _("valid endian specifiers are be or le");
3427 if (ISALNUM (s
[2]) || s
[2] == '_')
3429 inst
.error
= _("valid endian specifiers are be or le");
3434 return little_endian
;
3437 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3438 value suitable for poking into the rotate field of an sxt or sxta
3439 instruction, or FAIL on error. */
3442 parse_ror (char **str
)
3447 if (strncasecmp (s
, "ROR", 3) == 0)
3451 inst
.error
= _("missing rotation field after comma");
3455 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
3460 case 0: *str
= s
; return 0x0;
3461 case 8: *str
= s
; return 0x1;
3462 case 16: *str
= s
; return 0x2;
3463 case 24: *str
= s
; return 0x3;
3466 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
3471 /* Parse a conditional code (from conds[] below). The value returned is in the
3472 range 0 .. 14, or FAIL. */
3474 parse_cond (char **str
)
3477 const struct asm_cond
*c
;
3480 while (ISALPHA (*q
))
3483 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
3486 inst
.error
= _("condition required");
3494 /* Matcher codes for parse_operands. */
3495 enum operand_parse_code
3497 OP_stop
, /* end of line */
3499 OP_RR
, /* ARM register */
3500 OP_RRnpc
, /* ARM register, not r15 */
3501 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
3502 OP_RRw
, /* ARM register, not r15, optional trailing ! */
3503 OP_RCP
, /* Coprocessor number */
3504 OP_RCN
, /* Coprocessor register */
3505 OP_RF
, /* FPA register */
3506 OP_RVS
, /* VFP single precision register */
3507 OP_RVD
, /* VFP double precision register */
3508 OP_RVC
, /* VFP control register */
3509 OP_RMF
, /* Maverick F register */
3510 OP_RMD
, /* Maverick D register */
3511 OP_RMFX
, /* Maverick FX register */
3512 OP_RMDX
, /* Maverick DX register */
3513 OP_RMAX
, /* Maverick AX register */
3514 OP_RMDS
, /* Maverick DSPSC register */
3515 OP_RIWR
, /* iWMMXt wR register */
3516 OP_RIWC
, /* iWMMXt wC register */
3517 OP_RIWG
, /* iWMMXt wCG register */
3518 OP_RXA
, /* XScale accumulator register */
3520 OP_REGLST
, /* ARM register list */
3521 OP_VRSLST
, /* VFP single-precision register list */
3522 OP_VRDLST
, /* VFP double-precision register list */
3524 OP_I7
, /* immediate value 0 .. 7 */
3525 OP_I15
, /* 0 .. 15 */
3526 OP_I16
, /* 1 .. 16 */
3527 OP_I31
, /* 0 .. 31 */
3528 OP_I31w
, /* 0 .. 31, optional trailing ! */
3529 OP_I32
, /* 1 .. 32 */
3530 OP_I63s
, /* -64 .. 63 */
3531 OP_I255
, /* 0 .. 255 */
3532 OP_Iffff
, /* 0 .. 65535 */
3534 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
3535 OP_I7b
, /* 0 .. 7 */
3536 OP_I15b
, /* 0 .. 15 */
3537 OP_I31b
, /* 0 .. 31 */
3539 OP_SH
, /* shifter operand */
3540 OP_ADDR
, /* Memory address expression (any mode) */
3541 OP_EXP
, /* arbitrary expression */
3542 OP_EXPi
, /* same, with optional immediate prefix */
3543 OP_EXPr
, /* same, with optional relocation suffix */
3545 OP_CPSF
, /* CPS flags */
3546 OP_ENDI
, /* Endianness specifier */
3547 OP_PSR
, /* CPSR/SPSR mask for msr */
3548 OP_COND
, /* conditional code */
3550 OP_RRnpc_I0
, /* ARM register or literal 0 */
3551 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
3552 OP_RR_EXi
, /* ARM register or expression with imm prefix */
3553 OP_RF_IF
, /* FPA register or immediate */
3554 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
3556 /* Optional operands. */
3557 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
3558 OP_oI31b
, /* 0 .. 31 */
3559 OP_oIffffb
, /* 0 .. 65535 */
3560 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
3562 OP_oRR
, /* ARM register */
3563 OP_oRRnpc
, /* ARM register, not the PC */
3564 OP_oSHll
, /* LSL immediate */
3565 OP_oSHar
, /* ASR immediate */
3566 OP_oSHllar
, /* LSL or ASR immediate */
3567 OP_oROR
, /* ROR 0/8/16/24 */
3569 OP_FIRST_OPTIONAL
= OP_oI7b
3572 /* Generic instruction operand parser. This does no encoding and no
3573 semantic validation; it merely squirrels values away in the inst
3574 structure. Returns SUCCESS or FAIL depending on whether the
3575 specified grammar matched. */
3577 parse_operands (char *str
, const char *pattern
)
3579 unsigned const char *upat
= pattern
;
3580 char *backtrack_pos
= 0;
3581 const char *backtrack_error
= 0;
3582 int i
, val
, backtrack_index
= 0;
3584 #define po_char_or_fail(chr) do { \
3585 if (skip_past_char (&str, chr) == FAIL) \
3589 #define po_reg_or_fail(regtype) do { \
3590 val = arm_reg_parse (&str, regtype); \
3593 inst.error = _(reg_expected_msgs[regtype]); \
3596 inst.operands[i].reg = val; \
3597 inst.operands[i].isreg = 1; \
3600 #define po_reg_or_goto(regtype, label) do { \
3601 val = arm_reg_parse (&str, regtype); \
3605 inst.operands[i].reg = val; \
3606 inst.operands[i].isreg = 1; \
3609 #define po_imm_or_fail(min, max, popt) do { \
3610 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3612 inst.operands[i].imm = val; \
3615 #define po_misc_or_fail(expr) do { \
3620 skip_whitespace (str
);
3622 for (i
= 0; upat
[i
] != OP_stop
; i
++)
3624 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
3626 /* Remember where we are in case we need to backtrack. */
3627 assert (!backtrack_pos
);
3628 backtrack_pos
= str
;
3629 backtrack_error
= inst
.error
;
3630 backtrack_index
= i
;
3634 po_char_or_fail (',');
3642 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
3643 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
3644 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
3645 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
3646 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
3647 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
3648 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
3649 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
3650 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
3651 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
3652 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
3653 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
3654 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
3655 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
3656 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
3657 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
3658 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
3661 po_char_or_fail ('[');
3662 po_reg_or_fail (REG_TYPE_RN
);
3663 po_char_or_fail (']');
3667 po_reg_or_fail (REG_TYPE_RN
);
3668 if (skip_past_char (&str
, '!') == SUCCESS
)
3669 inst
.operands
[i
].writeback
= 1;
3673 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
3674 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
3675 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
3676 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
3677 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
3678 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
3679 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
3680 case OP_Iffff
: po_imm_or_fail ( 0, 0xffff, FALSE
); break;
3682 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
3684 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
3685 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
3687 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
3688 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
3690 /* Immediate variants */
3692 po_char_or_fail ('{');
3693 po_imm_or_fail (0, 255, TRUE
);
3694 po_char_or_fail ('}');
3698 /* The expression parser chokes on a trailing !, so we have
3699 to find it first and zap it. */
3702 while (*s
&& *s
!= ',')
3707 inst
.operands
[i
].writeback
= 1;
3709 po_imm_or_fail (0, 31, TRUE
);
3717 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3722 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3727 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3729 if (inst
.reloc
.exp
.X_op
== O_symbol
)
3731 val
= parse_reloc (&str
);
3734 inst
.error
= _("unrecognized relocation suffix");
3737 else if (val
!= BFD_RELOC_UNUSED
)
3739 inst
.operands
[i
].imm
= val
;
3740 inst
.operands
[i
].hasreloc
= 1;
3745 /* Register or expression */
3746 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
3747 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
3749 /* Register or immediate */
3750 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
3751 I0
: po_imm_or_fail (0, 0, FALSE
); break;
3753 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
3755 if (!is_immediate_prefix (*str
))
3758 val
= parse_fpa_immediate (&str
);
3761 /* FPA immediates are encoded as registers 8-15.
3762 parse_fpa_immediate has already applied the offset. */
3763 inst
.operands
[i
].reg
= val
;
3764 inst
.operands
[i
].isreg
= 1;
3767 /* Two kinds of register */
3770 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
3771 if (rege
->type
!= REG_TYPE_MMXWR
3772 && rege
->type
!= REG_TYPE_MMXWC
3773 && rege
->type
!= REG_TYPE_MMXWCG
)
3775 inst
.error
= _("iWMMXt data or control register expected");
3778 inst
.operands
[i
].reg
= rege
->number
;
3779 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
3784 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
3785 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
3786 case OP_oROR
: val
= parse_ror (&str
); break;
3787 case OP_PSR
: val
= parse_psr (&str
); break;
3788 case OP_COND
: val
= parse_cond (&str
); break;
3790 /* Register lists */
3792 val
= parse_reg_list (&str
);
3795 inst
.operands
[1].writeback
= 1;
3801 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 0);
3805 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 1);
3808 /* Addressing modes */
3810 po_misc_or_fail (parse_address (&str
, i
));
3814 po_misc_or_fail (parse_shifter_operand (&str
, i
));
3818 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
3822 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
3826 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
3830 as_fatal ("unhandled operand code %d", upat
[i
]);
3833 /* Various value-based sanity checks and shared operations. We
3834 do not signal immediate failures for the register constraints;
3835 this allows a syntax error to take precedence. */
3843 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
3844 inst
.error
= BAD_PC
;
3857 inst
.operands
[i
].imm
= val
;
3864 /* If we get here, this operand was successfully parsed. */
3865 inst
.operands
[i
].present
= 1;
3869 inst
.error
= BAD_ARGS
;
3875 /* Do not backtrack over a trailing optional argument that
3876 absorbed some text. We will only fail again, with the
3877 'garbage following instruction' error message, which is
3878 probably less helpful than the current one. */
3879 if (backtrack_index
== i
&& backtrack_pos
!= str
3880 && upat
[i
+1] == OP_stop
)
3883 /* Try again, skipping the optional argument at backtrack_pos. */
3884 str
= backtrack_pos
;
3885 inst
.error
= backtrack_error
;
3886 inst
.operands
[backtrack_index
].present
= 0;
3887 i
= backtrack_index
;
3891 /* Check that we have parsed all the arguments. */
3892 if (*str
!= '\0' && !inst
.error
)
3893 inst
.error
= _("garbage following instruction");
3895 return inst
.error
? FAIL
: SUCCESS
;
3898 #undef po_char_or_fail
3899 #undef po_reg_or_fail
3900 #undef po_reg_or_goto
3901 #undef po_imm_or_fail
3903 /* Shorthand macro for instruction encoding functions issuing errors. */
3904 #define constraint(expr, err) do { \
3912 /* Functions for operand encoding. ARM, then Thumb. */
3914 #define rotate_left(v, n) (v << n | v >> (32 - n))
3916 /* If VAL can be encoded in the immediate field of an ARM instruction,
3917 return the encoded form. Otherwise, return FAIL. */
3920 encode_arm_immediate (unsigned int val
)
3924 for (i
= 0; i
< 32; i
+= 2)
3925 if ((a
= rotate_left (val
, i
)) <= 0xff)
3926 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
3931 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3932 return the encoded form. Otherwise, return FAIL. */
3934 encode_thumb32_immediate (unsigned int val
)
3941 for (i
= 0; i
< 32; i
++)
3943 a
= rotate_left (val
, i
);
3944 if (a
>= 128 && a
<= 255)
3945 return (a
& 0x7f) | (i
<< 7);
3949 if (val
== ((a
<< 16) | a
))
3951 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
3955 if (val
== ((a
<< 16) | a
))
3956 return 0x200 | (a
>> 8);
3960 /* Encode a VFP SP register number into inst.instruction. */
3963 encode_arm_vfp_sp_reg (int reg
, enum vfp_sp_reg_pos pos
)
3968 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
3972 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
3976 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
3984 /* Encode a <shift> in an ARM-format instruction. The immediate,
3985 if any, is handled by md_apply_fix. */
3987 encode_arm_shift (int i
)
3989 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
3990 inst
.instruction
|= SHIFT_ROR
<< 5;
3993 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
3994 if (inst
.operands
[i
].immisreg
)
3996 inst
.instruction
|= SHIFT_BY_REG
;
3997 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
4000 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4005 encode_arm_shifter_operand (int i
)
4007 if (inst
.operands
[i
].isreg
)
4009 inst
.instruction
|= inst
.operands
[i
].reg
;
4010 encode_arm_shift (i
);
4013 inst
.instruction
|= INST_IMMEDIATE
;
4016 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4018 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
4020 assert (inst
.operands
[i
].isreg
);
4021 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4023 if (inst
.operands
[i
].preind
)
4027 inst
.error
= _("instruction does not accept preindexed addressing");
4030 inst
.instruction
|= PRE_INDEX
;
4031 if (inst
.operands
[i
].writeback
)
4032 inst
.instruction
|= WRITE_BACK
;
4035 else if (inst
.operands
[i
].postind
)
4037 assert (inst
.operands
[i
].writeback
);
4039 inst
.instruction
|= WRITE_BACK
;
4041 else /* unindexed - only for coprocessor */
4043 inst
.error
= _("instruction does not accept unindexed addressing");
4047 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
4048 && (((inst
.instruction
& 0x000f0000) >> 16)
4049 == ((inst
.instruction
& 0x0000f000) >> 12)))
4050 as_warn ((inst
.instruction
& LOAD_BIT
)
4051 ? _("destination register same as write-back base")
4052 : _("source register same as write-back base"));
4055 /* inst.operands[i] was set up by parse_address. Encode it into an
4056 ARM-format mode 2 load or store instruction. If is_t is true,
4057 reject forms that cannot be used with a T instruction (i.e. not
4060 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
4062 encode_arm_addr_mode_common (i
, is_t
);
4064 if (inst
.operands
[i
].immisreg
)
4066 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
4067 inst
.instruction
|= inst
.operands
[i
].imm
;
4068 if (!inst
.operands
[i
].negative
)
4069 inst
.instruction
|= INDEX_UP
;
4070 if (inst
.operands
[i
].shifted
)
4072 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4073 inst
.instruction
|= SHIFT_ROR
<< 5;
4076 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4077 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4081 else /* immediate offset in inst.reloc */
4083 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4084 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4088 /* inst.operands[i] was set up by parse_address. Encode it into an
4089 ARM-format mode 3 load or store instruction. Reject forms that
4090 cannot be used with such instructions. If is_t is true, reject
4091 forms that cannot be used with a T instruction (i.e. not
4094 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
4096 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
4098 inst
.error
= _("instruction does not accept scaled register index");
4102 encode_arm_addr_mode_common (i
, is_t
);
4104 if (inst
.operands
[i
].immisreg
)
4106 inst
.instruction
|= inst
.operands
[i
].imm
;
4107 if (!inst
.operands
[i
].negative
)
4108 inst
.instruction
|= INDEX_UP
;
4110 else /* immediate offset in inst.reloc */
4112 inst
.instruction
|= HWOFFSET_IMM
;
4113 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4114 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4118 /* inst.operands[i] was set up by parse_address. Encode it into an
4119 ARM-format instruction. Reject all forms which cannot be encoded
4120 into a coprocessor load/store instruction. If wb_ok is false,
4121 reject use of writeback; if unind_ok is false, reject use of
4122 unindexed addressing. If reloc_override is not 0, use it instead
4123 of BFD_ARM_CP_OFF_IMM. */
4126 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
4128 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4130 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
4132 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
4134 assert (!inst
.operands
[i
].writeback
);
4137 inst
.error
= _("instruction does not support unindexed addressing");
4140 inst
.instruction
|= inst
.operands
[i
].imm
;
4141 inst
.instruction
|= INDEX_UP
;
4145 if (inst
.operands
[i
].preind
)
4146 inst
.instruction
|= PRE_INDEX
;
4148 if (inst
.operands
[i
].writeback
)
4150 if (inst
.operands
[i
].reg
== REG_PC
)
4152 inst
.error
= _("pc may not be used with write-back");
4157 inst
.error
= _("instruction does not support writeback");
4160 inst
.instruction
|= WRITE_BACK
;
4164 inst
.reloc
.type
= reloc_override
;
4166 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
4170 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4171 Determine whether it can be performed with a move instruction; if
4172 it can, convert inst.instruction to that move instruction and
4173 return 1; if it can't, convert inst.instruction to a literal-pool
4174 load and return 0. If this is not a valid thing to do in the
4175 current context, set inst.error and return 1.
4177 inst.operands[i] describes the destination register. */
4180 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
4182 if ((inst
.instruction
& (thumb_p
? THUMB_LOAD_BIT
: LOAD_BIT
)) == 0)
4184 inst
.error
= _("invalid pseudo operation");
4187 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
4189 inst
.error
= _("constant expression expected");
4192 if (inst
.reloc
.exp
.X_op
== O_constant
)
4196 if ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
4198 /* This can be done with a mov(1) instruction. */
4199 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
4200 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4206 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
4209 /* This can be done with a mov instruction. */
4210 inst
.instruction
&= LITERAL_MASK
;
4211 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4212 inst
.instruction
|= value
& 0xfff;
4216 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
4219 /* This can be done with a mvn instruction. */
4220 inst
.instruction
&= LITERAL_MASK
;
4221 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
4222 inst
.instruction
|= value
& 0xfff;
4228 if (add_to_lit_pool () == FAIL
)
4230 inst
.error
= _("literal pool insertion failed");
4233 inst
.operands
[1].reg
= REG_PC
;
4234 inst
.operands
[1].isreg
= 1;
4235 inst
.operands
[1].preind
= 1;
4236 inst
.reloc
.pc_rel
= 1;
4237 inst
.reloc
.type
= (thumb_p
4238 ? BFD_RELOC_ARM_THUMB_OFFSET
4240 ? BFD_RELOC_ARM_HWLITERAL
4241 : BFD_RELOC_ARM_LITERAL
));
4245 /* Functions for instruction encoding, sorted by subarchitecture.
4246 First some generics; their names are taken from the conventional
4247 bit positions for register arguments in ARM format instructions. */
4257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4264 inst
.instruction
|= inst
.operands
[1].reg
;
4270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4271 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4277 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4278 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4285 inst
.instruction
|= inst
.operands
[1].reg
;
4286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4294 inst
.instruction
|= inst
.operands
[2].reg
;
4300 inst
.instruction
|= inst
.operands
[0].reg
;
4301 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4302 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4308 inst
.instruction
|= inst
.operands
[0].imm
;
4314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4315 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
4318 /* ARM instructions, in alphabetical order by function name (except
4319 that wrapper functions appear immediately after the function they
4322 /* This is a pseudo-op of the form "adr rd, label" to be converted
4323 into a relative address of the form "add rd, pc, #label-.-8". */
4328 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4330 /* Frag hacking will turn this into a sub instruction if the offset turns
4331 out to be negative. */
4332 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4333 inst
.reloc
.pc_rel
= 1;
4334 inst
.reloc
.exp
.X_add_number
-= 8;
4337 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4338 into a relative address of the form:
4339 add rd, pc, #low(label-.-8)"
4340 add rd, rd, #high(label-.-8)" */
4345 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4347 /* Frag hacking will turn this into a sub instruction if the offset turns
4348 out to be negative. */
4349 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4350 inst
.reloc
.pc_rel
= 1;
4351 inst
.size
= INSN_SIZE
* 2;
4352 inst
.reloc
.exp
.X_add_number
-= 8;
4358 if (!inst
.operands
[1].present
)
4359 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
4360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4361 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4362 encode_arm_shifter_operand (2);
4368 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
4369 constraint (msb
> 32, _("bit-field extends past end of register"));
4370 /* The instruction encoding stores the LSB and MSB,
4371 not the LSB and width. */
4372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4373 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
4374 inst
.instruction
|= (msb
- 1) << 16;
4382 /* #0 in second position is alternative syntax for bfc, which is
4383 the same instruction but with REG_PC in the Rm field. */
4384 if (!inst
.operands
[1].isreg
)
4385 inst
.operands
[1].reg
= REG_PC
;
4387 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
4388 constraint (msb
> 32, _("bit-field extends past end of register"));
4389 /* The instruction encoding stores the LSB and MSB,
4390 not the LSB and width. */
4391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4392 inst
.instruction
|= inst
.operands
[1].reg
;
4393 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4394 inst
.instruction
|= (msb
- 1) << 16;
4400 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
4401 _("bit-field extends past end of register"));
4402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4403 inst
.instruction
|= inst
.operands
[1].reg
;
4404 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4405 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
4408 /* ARM V5 breakpoint instruction (argument parse)
4409 BKPT <16 bit unsigned immediate>
4410 Instruction is not conditional.
4411 The bit pattern given in insns[] has the COND_ALWAYS condition,
4412 and it is an error if the caller tried to override that. */
4417 /* Top 12 of 16 bits to bits 19:8. */
4418 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
4420 /* Bottom 4 of 16 bits to bits 3:0. */
4421 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
4425 encode_branch (int default_reloc
)
4427 if (inst
.operands
[0].hasreloc
)
4429 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
4430 _("the only suffix valid here is '(plt)'"));
4431 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4435 inst
.reloc
.type
= default_reloc
;
4437 inst
.reloc
.pc_rel
= 1;
4443 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4446 /* ARM V5 branch-link-exchange instruction (argument parse)
4447 BLX <target_addr> ie BLX(1)
4448 BLX{<condition>} <Rm> ie BLX(2)
4449 Unfortunately, there are two different opcodes for this mnemonic.
4450 So, the insns[].value is not used, and the code here zaps values
4451 into inst.instruction.
4452 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4457 if (inst
.operands
[0].isreg
)
4459 /* Arg is a register; the opcode provided by insns[] is correct.
4460 It is not illegal to do "blx pc", just useless. */
4461 if (inst
.operands
[0].reg
== REG_PC
)
4462 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4464 inst
.instruction
|= inst
.operands
[0].reg
;
4468 /* Arg is an address; this instruction cannot be executed
4469 conditionally, and the opcode must be adjusted. */
4470 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
4471 inst
.instruction
= 0xfa000000;
4472 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
4479 if (inst
.operands
[0].reg
== REG_PC
)
4480 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4482 inst
.instruction
|= inst
.operands
[0].reg
;
4486 /* ARM v5TEJ. Jump to Jazelle code. */
4491 if (inst
.operands
[0].reg
== REG_PC
)
4492 as_tsktsk (_("use of r15 in bxj is not really useful"));
4494 inst
.instruction
|= inst
.operands
[0].reg
;
4497 /* Co-processor data operation:
4498 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4499 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4503 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4504 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
4505 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4506 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4507 inst
.instruction
|= inst
.operands
[4].reg
;
4508 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4514 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4515 encode_arm_shifter_operand (1);
4518 /* Transfer between coprocessor and ARM registers.
4519 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4524 No special properties. */
4529 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4530 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
4531 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4532 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4533 inst
.instruction
|= inst
.operands
[4].reg
;
4534 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4537 /* Transfer between coprocessor register and pair of ARM registers.
4538 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4543 Two XScale instructions are special cases of these:
4545 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4546 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4548 Result unpredicatable if Rd or Rn is R15. */
4553 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4554 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
4555 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4556 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4557 inst
.instruction
|= inst
.operands
[4].reg
;
4563 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
4564 inst
.instruction
|= inst
.operands
[1].imm
;
4570 /* There is no IT instruction in ARM mode. We
4571 process it but do not generate code for it. */
4578 int base_reg
= inst
.operands
[0].reg
;
4579 int range
= inst
.operands
[1].imm
;
4581 inst
.instruction
|= base_reg
<< 16;
4582 inst
.instruction
|= range
;
4584 if (inst
.operands
[1].writeback
)
4585 inst
.instruction
|= LDM_TYPE_2_OR_3
;
4587 if (inst
.operands
[0].writeback
)
4589 inst
.instruction
|= WRITE_BACK
;
4590 /* Check for unpredictable uses of writeback. */
4591 if (inst
.instruction
& LOAD_BIT
)
4593 /* Not allowed in LDM type 2. */
4594 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
4595 && ((range
& (1 << REG_PC
)) == 0))
4596 as_warn (_("writeback of base register is UNPREDICTABLE"));
4597 /* Only allowed if base reg not in list for other types. */
4598 else if (range
& (1 << base_reg
))
4599 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4603 /* Not allowed for type 2. */
4604 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
4605 as_warn (_("writeback of base register is UNPREDICTABLE"));
4606 /* Only allowed if base reg not in list, or first in list. */
4607 else if ((range
& (1 << base_reg
))
4608 && (range
& ((1 << base_reg
) - 1)))
4609 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4614 /* ARMv5TE load-consecutive (argument parse)
4623 constraint (inst
.operands
[0].reg
% 2 != 0,
4624 _("first destination register must be even"));
4625 constraint (inst
.operands
[1].present
4626 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4627 _("can only load two consecutive registers"));
4628 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4629 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
4631 if (!inst
.operands
[1].present
)
4632 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
4634 if (inst
.instruction
& LOAD_BIT
)
4636 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4637 register and the first register written; we have to diagnose
4638 overlap between the base and the second register written here. */
4640 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
4641 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
4642 as_warn (_("base register written back, and overlaps "
4643 "second destination register"));
4645 /* For an index-register load, the index register must not overlap the
4646 destination (even if not write-back). */
4647 else if (inst
.operands
[2].immisreg
4648 && (inst
.operands
[2].imm
== inst
.operands
[0].reg
4649 || inst
.operands
[2].imm
== inst
.operands
[1].reg
))
4650 as_warn (_("index register overlaps destination register"));
4653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4654 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
4660 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
4661 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
4662 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
4663 || inst
.operands
[1].negative
,
4664 _("instruction does not accept this addressing mode"));
4666 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
4668 constraint (inst
.reloc
.exp
.X_op
!= O_constant
4669 || inst
.reloc
.exp
.X_add_number
!= 0,
4670 _("offset must be zero in ARM encoding"));
4672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4673 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4674 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4680 constraint (inst
.operands
[0].reg
% 2 != 0,
4681 _("even register required"));
4682 constraint (inst
.operands
[1].present
4683 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4684 _("can only load two consecutive registers"));
4685 /* If op 1 were present and equal to PC, this function wouldn't
4686 have been called in the first place. */
4687 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4690 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4697 if (!inst
.operands
[1].isreg
)
4698 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
4700 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
4706 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4708 if (inst
.operands
[1].preind
)
4710 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4711 inst
.reloc
.exp
.X_add_number
!= 0,
4712 _("this instruction requires a post-indexed address"));
4714 inst
.operands
[1].preind
= 0;
4715 inst
.operands
[1].postind
= 1;
4716 inst
.operands
[1].writeback
= 1;
4718 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4719 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
4722 /* Halfword and signed-byte load/store operations. */
4727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4728 if (!inst
.operands
[1].isreg
)
4729 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
4731 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
4737 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4739 if (inst
.operands
[1].preind
)
4741 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4742 inst
.reloc
.exp
.X_add_number
!= 0,
4743 _("this instruction requires a post-indexed address"));
4745 inst
.operands
[1].preind
= 0;
4746 inst
.operands
[1].postind
= 1;
4747 inst
.operands
[1].writeback
= 1;
4749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4750 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
4753 /* Co-processor register load/store.
4754 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4758 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4759 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4760 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
4766 /* This restriction does not apply to mls (nor to mla in v6, but
4767 that's hard to detect at present). */
4768 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
4769 && !(inst
.instruction
& 0x00400000))
4770 as_tsktsk (_("rd and rm should be different in mla"));
4772 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4773 inst
.instruction
|= inst
.operands
[1].reg
;
4774 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
4775 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
4782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4783 encode_arm_shifter_operand (1);
4786 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4791 /* The value is in two pieces: 0:11, 16:19. */
4792 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00000fff);
4793 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0000f000) << 4;
4799 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4800 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
4802 _("'CPSR' or 'SPSR' expected"));
4803 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4804 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
4807 /* Two possible forms:
4808 "{C|S}PSR_<field>, Rm",
4809 "{C|S}PSR_f, #expression". */
4814 inst
.instruction
|= inst
.operands
[0].imm
;
4815 if (inst
.operands
[1].isreg
)
4816 inst
.instruction
|= inst
.operands
[1].reg
;
4819 inst
.instruction
|= INST_IMMEDIATE
;
4820 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4821 inst
.reloc
.pc_rel
= 0;
4828 if (!inst
.operands
[2].present
)
4829 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
4830 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4831 inst
.instruction
|= inst
.operands
[1].reg
;
4832 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
4834 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
4835 as_tsktsk (_("rd and rm should be different in mul"));
4838 /* Long Multiply Parser
4839 UMULL RdLo, RdHi, Rm, Rs
4840 SMULL RdLo, RdHi, Rm, Rs
4841 UMLAL RdLo, RdHi, Rm, Rs
4842 SMLAL RdLo, RdHi, Rm, Rs. */
4847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4848 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4849 inst
.instruction
|= inst
.operands
[2].reg
;
4850 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
4852 /* rdhi, rdlo and rm must all be different. */
4853 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
4854 || inst
.operands
[0].reg
== inst
.operands
[2].reg
4855 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
4856 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4862 if (inst
.operands
[0].present
)
4864 /* Architectural NOP hints are CPSR sets with no bits selected. */
4865 inst
.instruction
&= 0xf0000000;
4866 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
4870 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4871 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4872 Condition defaults to COND_ALWAYS.
4873 Error if Rd, Rn or Rm are R15. */
4878 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4879 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4880 inst
.instruction
|= inst
.operands
[2].reg
;
4881 if (inst
.operands
[3].present
)
4882 encode_arm_shift (3);
4885 /* ARM V6 PKHTB (Argument Parse). */
4890 if (!inst
.operands
[3].present
)
4892 /* If the shift specifier is omitted, turn the instruction
4893 into pkhbt rd, rm, rn. */
4894 inst
.instruction
&= 0xfff00010;
4895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4896 inst
.instruction
|= inst
.operands
[1].reg
;
4897 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4902 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4903 inst
.instruction
|= inst
.operands
[2].reg
;
4904 encode_arm_shift (3);
4908 /* ARMv5TE: Preload-Cache
4912 Syntactically, like LDR with B=1, W=0, L=1. */
4917 constraint (!inst
.operands
[0].isreg
,
4918 _("'[' expected after PLD mnemonic"));
4919 constraint (inst
.operands
[0].postind
,
4920 _("post-indexed expression used in preload instruction"));
4921 constraint (inst
.operands
[0].writeback
,
4922 _("writeback used in preload instruction"));
4923 constraint (!inst
.operands
[0].preind
,
4924 _("unindexed addressing used in preload instruction"));
4925 inst
.instruction
|= inst
.operands
[0].reg
;
4926 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
4932 inst
.operands
[1] = inst
.operands
[0];
4933 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
4934 inst
.operands
[0].isreg
= 1;
4935 inst
.operands
[0].writeback
= 1;
4936 inst
.operands
[0].reg
= REG_SP
;
4940 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
4941 word at the specified address and the following word
4943 Unconditionally executed.
4944 Error if Rn is R15. */
4949 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4950 if (inst
.operands
[0].writeback
)
4951 inst
.instruction
|= WRITE_BACK
;
4954 /* ARM V6 ssat (argument parse). */
4959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4960 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
4961 inst
.instruction
|= inst
.operands
[2].reg
;
4963 if (inst
.operands
[3].present
)
4964 encode_arm_shift (3);
4967 /* ARM V6 usat (argument parse). */
4972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4973 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
4974 inst
.instruction
|= inst
.operands
[2].reg
;
4976 if (inst
.operands
[3].present
)
4977 encode_arm_shift (3);
4980 /* ARM V6 ssat16 (argument parse). */
4985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4986 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
4987 inst
.instruction
|= inst
.operands
[2].reg
;
4993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4994 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
4995 inst
.instruction
|= inst
.operands
[2].reg
;
4998 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
4999 preserving the other bits.
5001 setend <endian_specifier>, where <endian_specifier> is either
5007 if (inst
.operands
[0].imm
)
5008 inst
.instruction
|= 0x200;
5014 unsigned int Rm
= (inst
.operands
[1].present
5015 ? inst
.operands
[1].reg
5016 : inst
.operands
[0].reg
);
5018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5019 inst
.instruction
|= Rm
;
5020 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
5022 constraint (inst
.operands
[0].reg
!= Rm
,
5023 _("source1 and dest must be same register"));
5024 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5025 inst
.instruction
|= SHIFT_BY_REG
;
5028 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
5034 inst
.reloc
.type
= BFD_RELOC_ARM_SMI
;
5035 inst
.reloc
.pc_rel
= 0;
5041 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
5042 inst
.reloc
.pc_rel
= 0;
5045 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5046 SMLAxy{cond} Rd,Rm,Rs,Rn
5047 SMLAWy{cond} Rd,Rm,Rs,Rn
5048 Error if any register is R15. */
5053 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5054 inst
.instruction
|= inst
.operands
[1].reg
;
5055 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5056 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5059 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5060 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5061 Error if any register is R15.
5062 Warning if Rdlo == Rdhi. */
5067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5068 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5069 inst
.instruction
|= inst
.operands
[2].reg
;
5070 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5072 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5073 as_tsktsk (_("rdhi and rdlo must be different"));
5076 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5077 SMULxy{cond} Rd,Rm,Rs
5078 Error if any register is R15. */
5083 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5084 inst
.instruction
|= inst
.operands
[1].reg
;
5085 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5088 /* ARM V6 srs (argument parse). */
5093 inst
.instruction
|= inst
.operands
[0].imm
;
5094 if (inst
.operands
[0].writeback
)
5095 inst
.instruction
|= WRITE_BACK
;
5098 /* ARM V6 strex (argument parse). */
5103 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
5104 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
5105 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
5106 || inst
.operands
[2].negative
,
5107 _("instruction does not accept this addressing mode"));
5109 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
5111 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5112 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
5114 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5115 || inst
.reloc
.exp
.X_add_number
!= 0,
5116 _("offset must be zero in ARM encoding"));
5118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5119 inst
.instruction
|= inst
.operands
[1].reg
;
5120 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5121 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5127 constraint (inst
.operands
[1].reg
% 2 != 0,
5128 _("even register required"));
5129 constraint (inst
.operands
[2].present
5130 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
5131 _("can only store two consecutive registers"));
5132 /* If op 2 were present and equal to PC, this function wouldn't
5133 have been called in the first place. */
5134 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
5136 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5137 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
5138 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
5141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5142 inst
.instruction
|= inst
.operands
[1].reg
;
5143 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
5146 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5147 extends it to 32-bits, and adds the result to a value in another
5148 register. You can specify a rotation by 0, 8, 16, or 24 bits
5149 before extracting the 16-bit value.
5150 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5151 Condition defaults to COND_ALWAYS.
5152 Error if any register uses R15. */
5157 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5158 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5159 inst
.instruction
|= inst
.operands
[2].reg
;
5160 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
5165 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5166 Condition defaults to COND_ALWAYS.
5167 Error if any register uses R15. */
5172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5173 inst
.instruction
|= inst
.operands
[1].reg
;
5174 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
5177 /* VFP instructions. In a logical order: SP variant first, monad
5178 before dyad, arithmetic then move then load/store. */
5181 do_vfp_sp_monadic (void)
5183 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5184 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5188 do_vfp_sp_dyadic (void)
5190 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5191 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5192 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5196 do_vfp_sp_compare_z (void)
5198 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5202 do_vfp_dp_sp_cvt (void)
5204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5205 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5209 do_vfp_sp_dp_cvt (void)
5211 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5212 inst
.instruction
|= inst
.operands
[1].reg
;
5216 do_vfp_reg_from_sp (void)
5218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5219 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5223 do_vfp_reg2_from_sp2 (void)
5225 constraint (inst
.operands
[2].imm
!= 2,
5226 _("only two consecutive VFP SP registers allowed here"));
5227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5229 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5233 do_vfp_sp_from_reg (void)
5235 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
5236 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5240 do_vfp_sp2_from_reg2 (void)
5242 constraint (inst
.operands
[0].imm
!= 2,
5243 _("only two consecutive VFP SP registers allowed here"));
5244 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
5245 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5246 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5250 do_vfp_sp_ldst (void)
5252 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5253 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5257 do_vfp_dp_ldst (void)
5259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5260 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5265 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
5267 if (inst
.operands
[0].writeback
)
5268 inst
.instruction
|= WRITE_BACK
;
5270 constraint (ldstm_type
!= VFP_LDSTMIA
,
5271 _("this addressing mode requires base-register writeback"));
5272 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5273 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
5274 inst
.instruction
|= inst
.operands
[1].imm
;
5278 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
5282 if (inst
.operands
[0].writeback
)
5283 inst
.instruction
|= WRITE_BACK
;
5285 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
5286 _("this addressing mode requires base-register writeback"));
5288 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5289 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5291 count
= inst
.operands
[1].imm
<< 1;
5292 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
5295 inst
.instruction
|= count
;
5299 do_vfp_sp_ldstmia (void)
5301 vfp_sp_ldstm (VFP_LDSTMIA
);
5305 do_vfp_sp_ldstmdb (void)
5307 vfp_sp_ldstm (VFP_LDSTMDB
);
5311 do_vfp_dp_ldstmia (void)
5313 vfp_dp_ldstm (VFP_LDSTMIA
);
5317 do_vfp_dp_ldstmdb (void)
5319 vfp_dp_ldstm (VFP_LDSTMDB
);
5323 do_vfp_xp_ldstmia (void)
5325 vfp_dp_ldstm (VFP_LDSTMIAX
);
5329 do_vfp_xp_ldstmdb (void)
5331 vfp_dp_ldstm (VFP_LDSTMDBX
);
5334 /* FPA instructions. Also in a logical order. */
5339 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5340 inst
.instruction
|= inst
.operands
[1].reg
;
5344 do_fpa_ldmstm (void)
5346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5347 switch (inst
.operands
[1].imm
)
5349 case 1: inst
.instruction
|= CP_T_X
; break;
5350 case 2: inst
.instruction
|= CP_T_Y
; break;
5351 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
5356 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
5358 /* The instruction specified "ea" or "fd", so we can only accept
5359 [Rn]{!}. The instruction does not really support stacking or
5360 unstacking, so we have to emulate these by setting appropriate
5361 bits and offsets. */
5362 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5363 || inst
.reloc
.exp
.X_add_number
!= 0,
5364 _("this instruction does not support indexing"));
5366 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
5367 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
5369 if (!(inst
.instruction
& INDEX_UP
))
5370 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
5372 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
5374 inst
.operands
[2].preind
= 0;
5375 inst
.operands
[2].postind
= 1;
5379 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5382 /* iWMMXt instructions: strictly in alphabetical order. */
5385 do_iwmmxt_tandorc (void)
5387 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
5391 do_iwmmxt_textrc (void)
5393 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5394 inst
.instruction
|= inst
.operands
[1].imm
;
5398 do_iwmmxt_textrm (void)
5400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5401 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5402 inst
.instruction
|= inst
.operands
[2].imm
;
5406 do_iwmmxt_tinsr (void)
5408 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5409 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5410 inst
.instruction
|= inst
.operands
[2].imm
;
5414 do_iwmmxt_tmia (void)
5416 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5417 inst
.instruction
|= inst
.operands
[1].reg
;
5418 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5422 do_iwmmxt_waligni (void)
5424 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5425 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5426 inst
.instruction
|= inst
.operands
[2].reg
;
5427 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
5431 do_iwmmxt_wmov (void)
5433 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5435 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5436 inst
.instruction
|= inst
.operands
[1].reg
;
5440 do_iwmmxt_wldstbh (void)
5442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5443 inst
.reloc
.exp
.X_add_number
*= 4;
5444 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_CP_OFF_IMM_S2
);
5448 do_iwmmxt_wldstw (void)
5450 /* RIWR_RIWC clears .isreg for a control register. */
5451 if (!inst
.operands
[0].isreg
)
5453 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
5454 inst
.instruction
|= 0xf0000000;
5457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5458 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
5462 do_iwmmxt_wldstd (void)
5464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5465 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_CP_OFF_IMM_S2
);
5469 do_iwmmxt_wshufh (void)
5471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5472 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5473 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
5474 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
5478 do_iwmmxt_wzero (void)
5480 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5481 inst
.instruction
|= inst
.operands
[0].reg
;
5482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5483 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5486 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5487 operations first, then control, shift, and load/store. */
5489 /* Insns like "foo X,Y,Z". */
5492 do_mav_triple (void)
5494 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5495 inst
.instruction
|= inst
.operands
[1].reg
;
5496 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5499 /* Insns like "foo W,X,Y,Z".
5500 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5505 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5506 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5507 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5508 inst
.instruction
|= inst
.operands
[3].reg
;
5511 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5515 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5518 /* Maverick shift immediate instructions.
5519 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5520 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5525 int imm
= inst
.operands
[2].imm
;
5527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5528 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5530 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5531 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5532 Bit 4 should be 0. */
5533 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
5535 inst
.instruction
|= imm
;
5538 /* XScale instructions. Also sorted arithmetic before move. */
5540 /* Xscale multiply-accumulate (argument parse)
5543 MIAxycc acc0,Rm,Rs. */
5548 inst
.instruction
|= inst
.operands
[1].reg
;
5549 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5552 /* Xscale move-accumulator-register (argument parse)
5554 MARcc acc0,RdLo,RdHi. */
5559 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5560 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5563 /* Xscale move-register-accumulator (argument parse)
5565 MRAcc RdLo,RdHi,acc0. */
5570 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
5571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5572 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5575 /* Encoding functions relevant only to Thumb. */
5577 /* inst.operands[i] is a shifted-register operand; encode
5578 it into inst.instruction in the format used by Thumb32. */
5581 encode_thumb32_shifted_operand (int i
)
5583 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
5584 unsigned int shift
= inst
.operands
[i
].shift_kind
;
5586 inst
.instruction
|= inst
.operands
[i
].reg
;
5587 if (shift
== SHIFT_RRX
)
5588 inst
.instruction
|= SHIFT_ROR
<< 4;
5591 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5592 _("expression too complex"));
5594 constraint (value
> 32
5595 || (value
== 32 && (shift
== SHIFT_LSL
5596 || shift
== SHIFT_ROR
)),
5597 _("shift expression is too large"));
5601 else if (value
== 32)
5604 inst
.instruction
|= shift
<< 4;
5605 inst
.instruction
|= (value
& 0x1c) << 10;
5606 inst
.instruction
|= (value
& 0x03) << 6;
5611 /* inst.operands[i] was set up by parse_address. Encode it into a
5612 Thumb32 format load or store instruction. Reject forms that cannot
5613 be used with such instructions. If is_t is true, reject forms that
5614 cannot be used with a T instruction; if is_d is true, reject forms
5615 that cannot be used with a D instruction. */
5618 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
5620 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
5622 constraint (!inst
.operands
[i
].isreg
,
5623 _("Thumb does not support the ldr =N pseudo-operation"));
5625 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
5626 if (inst
.operands
[i
].immisreg
)
5628 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
5629 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
5630 constraint (inst
.operands
[i
].negative
,
5631 _("Thumb does not support negative register indexing"));
5632 constraint (inst
.operands
[i
].postind
,
5633 _("Thumb does not support register post-indexing"));
5634 constraint (inst
.operands
[i
].writeback
,
5635 _("Thumb does not support register indexing with writeback"));
5636 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
5637 _("Thumb supports only LSL in shifted register indexing"));
5639 inst
.instruction
|= inst
.operands
[1].imm
;
5640 if (inst
.operands
[i
].shifted
)
5642 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5643 _("expression too complex"));
5644 constraint (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 3,
5645 _("shift out of range"));
5646 inst
.instruction
|= inst
.reloc
.exp
.X_op
<< 4;
5648 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5650 else if (inst
.operands
[i
].preind
)
5652 constraint (is_pc
&& inst
.operands
[i
].writeback
,
5653 _("cannot use writeback with PC-relative addressing"));
5654 constraint (is_t
&& inst
.operands
[1].writeback
,
5655 _("cannot use writeback with this instruction"));
5659 inst
.instruction
|= 0x01000000;
5660 if (inst
.operands
[i
].writeback
)
5661 inst
.instruction
|= 0x00200000;
5665 inst
.instruction
|= 0x00000c00;
5666 if (inst
.operands
[i
].writeback
)
5667 inst
.instruction
|= 0x00000100;
5669 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5670 inst
.reloc
.pc_rel
= is_pc
;
5672 else if (inst
.operands
[i
].postind
)
5674 assert (inst
.operands
[i
].writeback
);
5675 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
5676 constraint (is_t
, _("cannot use post-indexing with this instruction"));
5679 inst
.instruction
|= 0x00200000;
5681 inst
.instruction
|= 0x00000900;
5682 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5684 else /* unindexed - only for coprocessor */
5685 inst
.error
= _("instruction does not accept unindexed addressing");
5688 /* Table of Thumb instructions which exist in both 16- and 32-bit
5689 encodings (the latter only in post-V6T2 cores). The index is the
5690 value used in the insns table below. When there is more than one
5691 possible 16-bit encoding for the instruction, this table always
5692 holds variant (1). */
5693 #define T16_32_TAB \
5694 X(adc, 4140, eb400000), \
5695 X(adcs, 4140, eb500000), \
5696 X(add, 1c00, eb000000), \
5697 X(adds, 1c00, eb100000), \
5698 X(and, 4000, ea000000), \
5699 X(ands, 4000, ea100000), \
5700 X(asr, 1000, fa40f000), \
5701 X(asrs, 1000, fa50f000), \
5702 X(bic, 4380, ea200000), \
5703 X(bics, 4380, ea300000), \
5704 X(cmn, 42c0, eb100f00), \
5705 X(cmp, 2800, ebb00f00), \
5706 X(cpsie, b660, f3af8400), \
5707 X(cpsid, b670, f3af8600), \
5708 X(cpy, 4600, ea4f0000), \
5709 X(eor, 4040, ea800000), \
5710 X(eors, 4040, ea900000), \
5711 X(ldmia, c800, e8900000), \
5712 X(ldr, 6800, f8500000), \
5713 X(ldrb, 7800, f8100000), \
5714 X(ldrh, 8800, f8300000), \
5715 X(ldrsb, 5600, f9100000), \
5716 X(ldrsh, 5e00, f9300000), \
5717 X(lsl, 0000, fa00f000), \
5718 X(lsls, 0000, fa10f000), \
5719 X(lsr, 0800, fa20f000), \
5720 X(lsrs, 0800, fa30f000), \
5721 X(mov, 2000, ea4f0000), \
5722 X(movs, 2000, ea5f0000), \
5723 X(mul, 4340, fb00f000), \
5724 X(muls, 4340, ffffffff), /* no 32b muls */ \
5725 X(mvn, 43c0, ea6f0000), \
5726 X(mvns, 43c0, ea7f0000), \
5727 X(neg, 4240, f1c00000), /* rsb #0 */ \
5728 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5729 X(orr, 4300, ea400000), \
5730 X(orrs, 4300, ea500000), \
5731 X(pop, bc00, e8ad0000), /* ldmia sp!,... */ \
5732 X(push, b400, e8bd0000), /* stmia sp!,... */ \
5733 X(rev, ba00, fa90f080), \
5734 X(rev16, ba40, fa90f090), \
5735 X(revsh, bac0, fa90f0b0), \
5736 X(ror, 41c0, fa60f000), \
5737 X(rors, 41c0, fa70f000), \
5738 X(sbc, 4180, eb600000), \
5739 X(sbcs, 4180, eb700000), \
5740 X(stmia, c000, e8800000), \
5741 X(str, 6000, f8400000), \
5742 X(strb, 7000, f8000000), \
5743 X(strh, 8000, f8200000), \
5744 X(sub, 1e00, eba00000), \
5745 X(subs, 1e00, ebb00000), \
5746 X(sxtb, b240, fa4ff080), \
5747 X(sxth, b200, fa0ff080), \
5748 X(tst, 4200, ea100f00), \
5749 X(uxtb, b2c0, fa5ff080), \
5750 X(uxth, b280, fa1ff080), \
5751 X(nop, bf00, f3af8000), \
5752 X(yield, bf10, f3af8001), \
5753 X(wfe, bf20, f3af8002), \
5754 X(wfi, bf30, f3af8003), \
5755 X(sev, bf40, f3af9004), /* typo, 8004? */
5757 /* To catch errors in encoding functions, the codes are all offset by
5758 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5759 as 16-bit instructions. */
5760 #define X(a,b,c) T_MNEM_##a
5761 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
5764 #define X(a,b,c) 0x##b
5765 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
5766 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5769 #define X(a,b,c) 0x##c
5770 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
5771 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5772 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5776 /* Thumb instruction encoders, in alphabetical order. */
5778 /* Parse an add or subtract instruction. We get here with inst.instruction
5779 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5786 Rd
= inst
.operands
[0].reg
;
5787 Rs
= (inst
.operands
[1].present
5788 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
5789 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
5793 if (!inst
.operands
[2].isreg
)
5795 /* For an immediate, we always generate a 32-bit opcode;
5796 section relaxation will shrink it later if possible. */
5797 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5798 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
5799 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
5800 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5801 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
5805 Rn
= inst
.operands
[2].reg
;
5806 /* See if we can do this with a 16-bit instruction. */
5807 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
5809 if (Rd
<= 7 && Rn
<= 7 && Rn
<= 7
5810 && (inst
.instruction
== T_MNEM_adds
5811 || inst
.instruction
== T_MNEM_subs
))
5813 inst
.instruction
= (inst
.instruction
== T_MNEM_adds
5816 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5820 if (inst
.instruction
== T_MNEM_add
)
5824 inst
.instruction
= T_OPCODE_ADD_HI
;
5825 inst
.instruction
|= (Rd
& 8) << 4;
5826 inst
.instruction
|= (Rd
& 7);
5827 inst
.instruction
|= Rn
<< 3;
5830 /* ... because addition is commutative! */
5833 inst
.instruction
= T_OPCODE_ADD_HI
;
5834 inst
.instruction
|= (Rd
& 8) << 4;
5835 inst
.instruction
|= (Rd
& 7);
5836 inst
.instruction
|= Rs
<< 3;
5841 /* If we get here, it can't be done in 16 bits. */
5842 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
5843 _("shift must be constant"));
5844 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5845 inst
.instruction
|= Rd
<< 8;
5846 inst
.instruction
|= Rs
<< 16;
5847 encode_thumb32_shifted_operand (2);
5852 constraint (inst
.instruction
== T_MNEM_adds
5853 || inst
.instruction
== T_MNEM_subs
,
5856 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
5858 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
5859 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
5862 inst
.instruction
= (inst
.instruction
== T_MNEM_add
5864 inst
.instruction
|= (Rd
<< 4) | Rs
;
5865 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5869 Rn
= inst
.operands
[2].reg
;
5870 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
5872 /* We now have Rd, Rs, and Rn set to registers. */
5873 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
5875 /* Can't do this for SUB. */
5876 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
5877 inst
.instruction
= T_OPCODE_ADD_HI
;
5878 inst
.instruction
|= (Rd
& 8) << 4;
5879 inst
.instruction
|= (Rd
& 7);
5881 inst
.instruction
|= Rn
<< 3;
5883 inst
.instruction
|= Rs
<< 3;
5885 constraint (1, _("dest must overlap one source register"));
5889 inst
.instruction
= (inst
.instruction
== T_MNEM_add
5890 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
5891 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
5899 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5900 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
5901 inst
.reloc
.pc_rel
= 1;
5903 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
5906 /* Arithmetic instructions for which there is just one 16-bit
5907 instruction encoding, and it allows only two low registers.
5908 For maximal compatibility with ARM syntax, we allow three register
5909 operands even when Thumb-32 instructions are not available, as long
5910 as the first two are identical. For instance, both "sbc r0,r1" and
5911 "sbc r0,r0,r1" are allowed. */
5917 Rd
= inst
.operands
[0].reg
;
5918 Rs
= (inst
.operands
[1].present
5919 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
5920 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
5921 Rn
= inst
.operands
[2].reg
;
5925 if (!inst
.operands
[2].isreg
)
5927 /* For an immediate, we always generate a 32-bit opcode;
5928 section relaxation will shrink it later if possible. */
5929 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5930 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
5931 inst
.instruction
|= Rd
<< 8;
5932 inst
.instruction
|= Rs
<< 16;
5933 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
5937 /* See if we can do this with a 16-bit instruction. */
5938 if (THUMB_SETS_FLAGS (inst
.instruction
)
5939 && !inst
.operands
[2].shifted
5940 && inst
.size_req
!= 4
5943 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
5944 inst
.instruction
|= Rd
;
5945 inst
.instruction
|= Rn
<< 3;
5949 /* If we get here, it can't be done in 16 bits. */
5950 constraint (inst
.operands
[2].shifted
5951 && inst
.operands
[2].immisreg
,
5952 _("shift must be constant"));
5953 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
5954 inst
.instruction
|= Rd
<< 8;
5955 inst
.instruction
|= Rs
<< 16;
5956 encode_thumb32_shifted_operand (2);
5961 /* On its face this is a lie - the instruction does set the
5962 flags. However, the only supported mnemonic in this mode
5964 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
5966 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
5967 _("unshifted register required"));
5968 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
5969 constraint (Rd
!= Rs
,
5970 _("dest and source1 must be the same register"));
5972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
5973 inst
.instruction
|= Rd
;
5974 inst
.instruction
|= Rn
<< 3;
5978 /* Similarly, but for instructions where the arithmetic operation is
5979 commutative, so we can allow either of them to be different from
5980 the destination operand in a 16-bit instruction. For instance, all
5981 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
5988 Rd
= inst
.operands
[0].reg
;
5989 Rs
= (inst
.operands
[1].present
5990 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
5991 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
5992 Rn
= inst
.operands
[2].reg
;
5996 if (!inst
.operands
[2].isreg
)
5998 /* For an immediate, we always generate a 32-bit opcode;
5999 section relaxation will shrink it later if possible. */
6000 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6001 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6002 inst
.instruction
|= Rd
<< 8;
6003 inst
.instruction
|= Rs
<< 16;
6004 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6008 /* See if we can do this with a 16-bit instruction. */
6009 if (THUMB_SETS_FLAGS (inst
.instruction
)
6010 && !inst
.operands
[2].shifted
6011 && inst
.size_req
!= 4)
6015 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6016 inst
.instruction
|= Rd
;
6017 inst
.instruction
|= Rn
<< 3;
6022 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6023 inst
.instruction
|= Rd
;
6024 inst
.instruction
|= Rs
<< 3;
6029 /* If we get here, it can't be done in 16 bits. */
6030 constraint (inst
.operands
[2].shifted
6031 && inst
.operands
[2].immisreg
,
6032 _("shift must be constant"));
6033 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6034 inst
.instruction
|= Rd
<< 8;
6035 inst
.instruction
|= Rs
<< 16;
6036 encode_thumb32_shifted_operand (2);
6041 /* On its face this is a lie - the instruction does set the
6042 flags. However, the only supported mnemonic in this mode
6044 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6046 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6047 _("unshifted register required"));
6048 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6050 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6051 inst
.instruction
|= Rd
;
6054 inst
.instruction
|= Rn
<< 3;
6056 inst
.instruction
|= Rs
<< 3;
6058 constraint (1, _("dest must overlap one source register"));
6065 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6066 constraint (msb
> 32, _("bit-field extends past end of register"));
6067 /* The instruction encoding stores the LSB and MSB,
6068 not the LSB and width. */
6069 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6070 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
6071 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
6072 inst
.instruction
|= msb
- 1;
6080 /* #0 in second position is alternative syntax for bfc, which is
6081 the same instruction but with REG_PC in the Rm field. */
6082 if (!inst
.operands
[1].isreg
)
6083 inst
.operands
[1].reg
= REG_PC
;
6085 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6086 constraint (msb
> 32, _("bit-field extends past end of register"));
6087 /* The instruction encoding stores the LSB and MSB,
6088 not the LSB and width. */
6089 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6090 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6091 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6092 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6093 inst
.instruction
|= msb
- 1;
6099 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6100 _("bit-field extends past end of register"));
6101 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6102 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6103 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6104 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6105 inst
.instruction
|= inst
.operands
[3].imm
- 1;
6108 /* ARM V5 Thumb BLX (argument parse)
6109 BLX <target_addr> which is BLX(1)
6110 BLX <Rm> which is BLX(2)
6111 Unfortunately, there are two different opcodes for this mnemonic.
6112 So, the insns[].value is not used, and the code here zaps values
6113 into inst.instruction.
6115 ??? How to take advantage of the additional two bits of displacement
6116 available in Thumb32 mode? Need new relocation? */
6121 if (inst
.operands
[0].isreg
)
6122 /* We have a register, so this is BLX(2). */
6123 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6126 /* No register. This must be BLX(1). */
6127 inst
.instruction
= 0xf000e800;
6128 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
6129 inst
.reloc
.pc_rel
= 1;
6136 if (unified_syntax
&& inst
.size_req
!= 2)
6138 if (inst
.cond
== COND_ALWAYS
)
6140 inst
.instruction
= 0xf000b000;
6141 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
6145 assert (inst
.cond
!= 0xF);
6146 inst
.instruction
= (inst
.cond
<< 22) | 0xf0008000;
6147 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
6152 if (inst
.cond
== COND_ALWAYS
)
6153 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6156 inst
.instruction
= 0xd000 | (inst
.cond
<< 8);
6157 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6161 inst
.reloc
.pc_rel
= 1;
6167 if (inst
.operands
[0].present
)
6169 constraint (inst
.operands
[0].imm
> 255,
6170 _("immediate value out of range"));
6171 inst
.instruction
|= inst
.operands
[0].imm
;
6176 do_t_branch23 (void)
6178 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6179 inst
.reloc
.pc_rel
= 1;
6181 /* If the destination of the branch is a defined symbol which does not have
6182 the THUMB_FUNC attribute, then we must be calling a function which has
6183 the (interfacearm) attribute. We look for the Thumb entry point to that
6184 function and change the branch to refer to that function instead. */
6185 if ( inst
.reloc
.exp
.X_op
== O_symbol
6186 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6187 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6188 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6189 inst
.reloc
.exp
.X_add_symbol
=
6190 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6196 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6197 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6198 should cause the alignment to be checked once it is known. This is
6199 because BX PC only works if the instruction is word aligned. */
6205 if (inst
.operands
[0].reg
== REG_PC
)
6206 as_tsktsk (_("use of r15 in bxj is not really useful"));
6208 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6214 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6215 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6216 inst
.instruction
|= inst
.operands
[1].reg
;
6223 && (inst
.operands
[1].present
|| inst
.size_req
== 4))
6225 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
6226 inst
.instruction
= 0xf3af8000;
6227 inst
.instruction
|= imod
<< 9;
6228 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
6229 if (inst
.operands
[1].present
)
6230 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
6234 constraint (inst
.operands
[1].present
,
6235 _("Thumb does not support the 2-argument "
6236 "form of this instruction"));
6237 inst
.instruction
|= inst
.operands
[0].imm
;
6241 /* THUMB CPY instruction (argument parse). */
6246 if (inst
.size_req
== 4)
6248 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
6249 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6250 inst
.instruction
|= inst
.operands
[1].reg
;
6254 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6255 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6256 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6263 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6264 inst
.instruction
|= inst
.operands
[0].reg
;
6265 inst
.reloc
.pc_rel
= 1;
6266 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
6272 if (unified_syntax
&& inst
.size_req
== 4)
6273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6281 unsigned int cond
= inst
.operands
[0].imm
;
6282 if ((cond
& 0x1) == 0x0)
6284 unsigned int mask
= inst
.instruction
& 0x000f;
6285 inst
.instruction
&= 0xfff0;
6287 if ((mask
& 0x7) == 0)
6288 /* no conversion needed */;
6289 else if ((mask
& 0x3) == 0)
6290 mask
= (~(mask
& 0x8) & 0x8) | 0x4;
6291 else if ((mask
& 1) == 0)
6292 mask
= (~(mask
& 0xC) & 0xC) | 0x2;
6294 mask
= (~(mask
& 0xE) & 0xE) | 0x1;
6296 inst
.instruction
|= (mask
& 0xF);
6299 inst
.instruction
|= cond
<< 4;
6305 /* This really doesn't seem worth it. */
6306 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
6307 _("expression too complex"));
6308 constraint (inst
.operands
[1].writeback
,
6309 _("Thumb load/store multiple does not support {reglist}^"));
6313 /* See if we can use a 16-bit instruction. */
6314 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
6315 && inst
.size_req
!= 4
6316 && inst
.operands
[0].reg
<= 7
6317 && !(inst
.operands
[1].imm
& ~0xff)
6318 && (inst
.instruction
== T_MNEM_stmia
6319 ? inst
.operands
[0].writeback
6320 : (inst
.operands
[0].writeback
6321 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
6323 if (inst
.instruction
== T_MNEM_stmia
6324 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6325 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6326 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6327 inst
.operands
[0].reg
);
6329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6330 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6331 inst
.instruction
|= inst
.operands
[1].imm
;
6335 if (inst
.operands
[1].imm
& (1 << 13))
6336 as_warn (_("SP should not be in register list"));
6337 if (inst
.instruction
== T_MNEM_stmia
)
6339 if (inst
.operands
[1].imm
& (1 << 15))
6340 as_warn (_("PC should not be in register list"));
6341 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6342 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6343 inst
.operands
[0].reg
);
6347 if (inst
.operands
[1].imm
& (1 << 14)
6348 && inst
.operands
[1].imm
& (1 << 15))
6349 as_warn (_("LR and PC should not both be in register list"));
6350 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6351 && inst
.operands
[0].writeback
)
6352 as_warn (_("base register should not be in register list "
6353 "when written back"));
6355 if (inst
.instruction
< 0xffff)
6356 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6357 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6358 inst
.instruction
|= inst
.operands
[1].imm
;
6359 if (inst
.operands
[0].writeback
)
6360 inst
.instruction
|= WRITE_BACK
;
6365 constraint (inst
.operands
[0].reg
> 7
6366 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
6367 if (inst
.instruction
== T_MNEM_stmia
)
6369 if (!inst
.operands
[0].writeback
)
6370 as_warn (_("this instruction will write back the base register"));
6371 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6372 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6373 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6374 inst
.operands
[0].reg
);
6378 if (!inst
.operands
[0].writeback
6379 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6380 as_warn (_("this instruction will write back the base register"));
6381 else if (inst
.operands
[0].writeback
6382 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6383 as_warn (_("this instruction will not write back the base register"));
6386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6388 inst
.instruction
|= inst
.operands
[1].imm
;
6395 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6396 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6397 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6398 || inst
.operands
[1].negative
,
6399 _("instruction does not accept this addressing mode"));
6401 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6402 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6403 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
6409 if (!inst
.operands
[1].present
)
6411 constraint (inst
.operands
[0].reg
== REG_LR
,
6412 _("r14 not allowed as first register "
6413 "when second register is omitted"));
6414 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6416 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
6419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6420 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6421 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6429 /* Generation of 16-bit instructions for anything other than
6430 Rd, [Rn, Ri] is deferred to section relaxation time. */
6431 if (inst
.operands
[1].isreg
&& inst
.operands
[1].immisreg
6432 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
6433 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
6434 && inst
.operands
[1].reg
<= 7 && inst
.operands
[1].imm
<= 7
6435 && inst
.instruction
<= 0xffff)
6437 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6441 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6443 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
6447 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6449 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
6451 /* Only [Rn,Rm] is acceptable. */
6452 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
6453 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
6454 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
6455 || inst
.operands
[1].negative
,
6456 _("Thumb does not support this addressing mode"));
6457 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6461 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6462 if (!inst
.operands
[1].isreg
)
6463 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
6466 constraint (!inst
.operands
[1].preind
6467 || inst
.operands
[1].shifted
6468 || inst
.operands
[1].writeback
,
6469 _("Thumb does not support this addressing mode"));
6470 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
6472 constraint (inst
.instruction
& 0x0600,
6473 _("byte or halfword not valid for base register"));
6474 constraint (inst
.operands
[1].reg
== REG_PC
6475 && !(inst
.instruction
& THUMB_LOAD_BIT
),
6476 _("r15 based store not allowed"));
6477 constraint (inst
.operands
[1].immisreg
,
6478 _("invalid base register for register offset"));
6480 if (inst
.operands
[1].reg
== REG_PC
)
6481 inst
.instruction
= T_OPCODE_LDR_PC
;
6482 else if (inst
.instruction
& THUMB_LOAD_BIT
)
6483 inst
.instruction
= T_OPCODE_LDR_SP
;
6485 inst
.instruction
= T_OPCODE_STR_SP
;
6487 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6488 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6492 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
6493 if (!inst
.operands
[1].immisreg
)
6495 /* Immediate offset. */
6496 inst
.instruction
|= inst
.operands
[0].reg
;
6497 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6498 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6502 /* Register offset. */
6503 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
6504 constraint (inst
.operands
[1].negative
,
6505 _("Thumb does not support this addressing mode"));
6508 switch (inst
.instruction
)
6510 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
6511 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
6512 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
6513 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
6514 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
6515 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
6516 case 0x5600 /* ldrsb */:
6517 case 0x5e00 /* ldrsh */: break;
6521 inst
.instruction
|= inst
.operands
[0].reg
;
6522 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6523 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
6529 if (!inst
.operands
[1].present
)
6531 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6532 constraint (inst
.operands
[0].reg
== REG_LR
,
6533 _("r14 not allowed here"));
6535 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6536 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6537 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
6544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6545 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
6551 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6552 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6553 inst
.instruction
|= inst
.operands
[2].reg
;
6554 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6560 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6561 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6562 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6563 inst
.instruction
|= inst
.operands
[3].reg
;
6571 int r0off
= (inst
.instruction
== T_MNEM_mov
6572 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
6573 if (!inst
.operands
[1].isreg
)
6575 /* For an immediate, we always generate a 32-bit opcode;
6576 section relaxation will shrink it later if possible. */
6577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6578 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6579 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6580 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6582 else if (inst
.size_req
== 4
6583 || inst
.operands
[1].shifted
6584 || (inst
.instruction
== T_MNEM_movs
6585 && (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)))
6587 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6588 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6589 encode_thumb32_shifted_operand (1);
6592 switch (inst
.instruction
)
6595 inst
.instruction
= T_OPCODE_MOV_HR
;
6596 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6597 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6598 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6602 /* We know we have low registers at this point.
6603 Generate ADD Rd, Rs, #0. */
6604 inst
.instruction
= T_OPCODE_ADD_I3
;
6605 inst
.instruction
|= inst
.operands
[0].reg
;
6606 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6610 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7)
6612 inst
.instruction
= T_OPCODE_CMP_LR
;
6613 inst
.instruction
|= inst
.operands
[0].reg
;
6614 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6618 inst
.instruction
= T_OPCODE_CMP_HR
;
6619 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6620 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6621 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6628 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6629 if (inst
.operands
[1].isreg
)
6631 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
6633 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6634 since a MOV instruction produces unpredictable results. */
6635 if (inst
.instruction
== T_OPCODE_MOV_I8
)
6636 inst
.instruction
= T_OPCODE_ADD_I3
;
6638 inst
.instruction
= T_OPCODE_CMP_LR
;
6640 inst
.instruction
|= inst
.operands
[0].reg
;
6641 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6645 if (inst
.instruction
== T_OPCODE_MOV_I8
)
6646 inst
.instruction
= T_OPCODE_MOV_HR
;
6648 inst
.instruction
= T_OPCODE_CMP_HR
;
6654 constraint (inst
.operands
[0].reg
> 7,
6655 _("only lo regs allowed with immediate"));
6656 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6657 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
6664 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6665 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf000) << 4;
6666 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0800) << 15;
6667 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0700) << 4;
6668 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00ff);
6676 int r0off
= (inst
.instruction
== T_MNEM_mvn
6677 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
6678 if (!inst
.operands
[1].isreg
)
6680 /* For an immediate, we always generate a 32-bit opcode;
6681 section relaxation will shrink it later if possible. */
6682 if (inst
.instruction
< 0xffff)
6683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6684 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6685 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6686 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6690 /* See if we can do this with a 16-bit instruction. */
6691 if (inst
.instruction
< 0xffff
6692 && THUMB_SETS_FLAGS (inst
.instruction
)
6693 && !inst
.operands
[1].shifted
6694 && inst
.operands
[0].reg
<= 7
6695 && inst
.operands
[1].reg
<= 7
6696 && inst
.size_req
!= 4)
6698 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6699 inst
.instruction
|= inst
.operands
[0].reg
;
6700 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6704 constraint (inst
.operands
[1].shifted
6705 && inst
.operands
[1].immisreg
,
6706 _("shift must be constant"));
6707 if (inst
.instruction
< 0xffff)
6708 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6709 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
6710 encode_thumb32_shifted_operand (1);
6716 constraint (inst
.instruction
> 0xffff
6717 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
6718 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
6719 _("unshifted register required"));
6720 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6723 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6724 inst
.instruction
|= inst
.operands
[0].reg
;
6725 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6732 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6733 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
6735 _("'CPSR' or 'SPSR' expected"));
6736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6737 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
) >> 2;
6743 constraint (!inst
.operands
[1].isreg
,
6744 _("Thumb encoding does not support an immediate here"));
6745 inst
.instruction
|= (inst
.operands
[0].imm
& SPSR_BIT
) >> 2;
6746 inst
.instruction
|= (inst
.operands
[0].imm
& ~SPSR_BIT
) >> 8;
6747 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6753 if (!inst
.operands
[2].present
)
6754 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
6756 /* There is no 32-bit MULS and no 16-bit MUL. */
6757 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
6759 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6760 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6761 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6762 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
6766 constraint (!unified_syntax
6767 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
6768 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6771 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6772 inst
.instruction
|= inst
.operands
[0].reg
;
6774 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
6775 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
6776 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
6777 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6779 constraint (1, _("dest must overlap one source register"));
6786 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6787 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6788 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6789 inst
.instruction
|= inst
.operands
[3].reg
;
6791 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
6792 as_tsktsk (_("rdhi and rdlo must be different"));
6800 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
6802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6803 inst
.instruction
|= inst
.operands
[0].imm
;
6807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6808 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
6813 constraint (inst
.operands
[0].present
,
6814 _("Thumb does not support NOP with hints"));
6815 inst
.instruction
= 0x46c0;
6824 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7
6825 || !THUMB_SETS_FLAGS (inst
.instruction
)
6826 || inst
.size_req
== 4)
6828 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6829 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6830 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6834 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6835 inst
.instruction
|= inst
.operands
[0].reg
;
6836 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6841 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
6843 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6845 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6846 inst
.instruction
|= inst
.operands
[0].reg
;
6847 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6854 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6855 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6856 inst
.instruction
|= inst
.operands
[2].reg
;
6857 if (inst
.operands
[3].present
)
6859 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
6860 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
6861 _("expression too complex"));
6862 inst
.instruction
|= (val
& 0x1c) << 10;
6863 inst
.instruction
|= (val
& 0x03) << 6;
6870 if (!inst
.operands
[3].present
)
6871 inst
.instruction
&= ~0x00000020;
6878 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
6882 do_t_push_pop (void)
6884 constraint (inst
.operands
[0].writeback
,
6885 _("push/pop do not support {reglist}^"));
6886 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
6887 _("expression too complex"));
6889 if ((inst
.operands
[0].imm
& ~0xff) == 0)
6890 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6891 else if ((inst
.instruction
== T_MNEM_push
6892 && (inst
.operands
[0].imm
& ~0xff) == 1 << REG_LR
)
6893 || (inst
.instruction
== T_MNEM_pop
6894 && (inst
.operands
[0].imm
& ~0xff) == 1 << REG_PC
))
6896 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6897 inst
.instruction
|= THUMB_PP_PC_LR
;
6898 inst
.operands
[0].imm
&= 0xff;
6900 else if (unified_syntax
)
6902 if (inst
.operands
[1].imm
& (1 << 13))
6903 as_warn (_("SP should not be in register list"));
6904 if (inst
.instruction
== T_MNEM_push
)
6906 if (inst
.operands
[1].imm
& (1 << 15))
6907 as_warn (_("PC should not be in register list"));
6911 if (inst
.operands
[1].imm
& (1 << 14)
6912 && inst
.operands
[1].imm
& (1 << 15))
6913 as_warn (_("LR and PC should not both be in register list"));
6916 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6920 inst
.error
= _("invalid register list to push/pop instruction");
6924 inst
.instruction
|= inst
.operands
[0].imm
;
6930 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6931 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6937 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
6938 && inst
.size_req
!= 4)
6940 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6941 inst
.instruction
|= inst
.operands
[0].reg
;
6942 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6944 else if (unified_syntax
)
6946 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6947 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6948 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6949 inst
.instruction
|= inst
.operands
[1].reg
;
6952 inst
.error
= BAD_HIREG
;
6960 Rd
= inst
.operands
[0].reg
;
6961 Rs
= (inst
.operands
[1].present
6962 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6963 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6965 inst
.instruction
|= Rd
<< 8;
6966 inst
.instruction
|= Rs
<< 16;
6967 if (!inst
.operands
[2].isreg
)
6969 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6970 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6973 encode_thumb32_shifted_operand (2);
6979 if (inst
.operands
[0].imm
)
6980 inst
.instruction
|= 0x8;
6986 if (!inst
.operands
[1].present
)
6987 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6991 if (inst
.operands
[0].reg
> 7
6992 || inst
.operands
[1].reg
> 7
6993 || !THUMB_SETS_FLAGS (inst
.instruction
)
6994 || (!inst
.operands
[2].isreg
&& inst
.instruction
== T_MNEM_rors
)
6995 || (inst
.operands
[2].isreg
&& inst
.operands
[1].reg
!= inst
.operands
[0].reg
)
6996 || inst
.size_req
== 4)
6998 if (inst
.operands
[2].isreg
)
7000 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7001 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7002 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7003 inst
.instruction
|= inst
.operands
[2].reg
;
7007 inst
.operands
[1].shifted
= 1;
7008 switch (inst
.instruction
)
7011 case T_MNEM_asrs
: inst
.operands
[1].shift_kind
= SHIFT_ASR
; break;
7013 case T_MNEM_lsls
: inst
.operands
[1].shift_kind
= SHIFT_LSL
; break;
7015 case T_MNEM_lsrs
: inst
.operands
[1].shift_kind
= SHIFT_LSR
; break;
7017 case T_MNEM_rors
: inst
.operands
[1].shift_kind
= SHIFT_ROR
; break;
7021 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
7022 ? T_MNEM_movs
: T_MNEM_mov
);
7023 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7024 encode_thumb32_shifted_operand (1);
7025 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7026 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7031 if (inst
.operands
[2].isreg
)
7033 switch (inst
.instruction
)
7035 case T_MNEM_asrs
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7036 case T_MNEM_lsls
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7037 case T_MNEM_lsrs
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7038 case T_MNEM_rors
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7042 inst
.instruction
|= inst
.operands
[0].reg
;
7043 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7047 switch (inst
.instruction
)
7049 case T_MNEM_asrs
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7050 case T_MNEM_lsls
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7051 case T_MNEM_lsrs
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7054 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7055 inst
.instruction
|= inst
.operands
[0].reg
;
7056 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7062 constraint (inst
.operands
[0].reg
> 7
7063 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
7064 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7066 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
7068 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
7069 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
7070 _("source1 and dest must be same register"));
7072 switch (inst
.instruction
)
7074 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7075 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7076 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7077 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7081 inst
.instruction
|= inst
.operands
[0].reg
;
7082 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7086 switch (inst
.instruction
)
7088 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7089 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7090 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7091 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
7094 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7095 inst
.instruction
|= inst
.operands
[0].reg
;
7096 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7104 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7105 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7106 inst
.instruction
|= inst
.operands
[2].reg
;
7112 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7113 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7114 _("expression too complex"));
7115 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7116 inst
.instruction
|= (value
& 0xf000) >> 12;
7117 inst
.instruction
|= (value
& 0x0ff0);
7118 inst
.instruction
|= (value
& 0x000f) << 16;
7124 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7125 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7126 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7128 if (inst
.operands
[3].present
)
7130 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7131 _("expression too complex"));
7133 if (inst
.reloc
.exp
.X_add_number
!= 0)
7135 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7136 inst
.instruction
|= 0x00200000; /* sh bit */
7137 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7138 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7140 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7147 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7148 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7149 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7155 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7156 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7157 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7158 || inst
.operands
[2].negative
,
7159 _("instruction does not accept this addressing mode"));
7161 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7162 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7163 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7164 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
7170 if (!inst
.operands
[2].present
)
7171 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
7173 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7174 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7175 || inst
.operands
[0].reg
== inst
.operands
[3].reg
7176 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
7179 inst
.instruction
|= inst
.operands
[0].reg
;
7180 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7181 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7182 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7189 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7190 inst
.instruction
|= inst
.operands
[2].reg
;
7191 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
7197 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
7198 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7199 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
7201 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7202 inst
.instruction
|= inst
.operands
[0].reg
;
7203 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7205 else if (unified_syntax
)
7207 if (inst
.instruction
<= 0xffff)
7208 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7209 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7210 inst
.instruction
|= inst
.operands
[1].reg
;
7211 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
7215 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
7216 _("Thumb encoding does not support rotation"));
7217 constraint (1, BAD_HIREG
);
7224 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7230 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7231 inst
.instruction
|= inst
.operands
[1].imm
;
7232 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7234 if (inst
.operands
[3].present
)
7236 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7237 _("expression too complex"));
7238 if (inst
.reloc
.exp
.X_add_number
!= 0)
7240 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7241 inst
.instruction
|= 0x00200000; /* sh bit */
7243 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7244 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7246 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7253 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7254 inst
.instruction
|= inst
.operands
[1].imm
;
7255 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7258 /* Overall per-instruction processing. */
7260 /* We need to be able to fix up arbitrary expressions in some statements.
7261 This is so that we can handle symbols that are an arbitrary distance from
7262 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7263 which returns part of an address in a form which will be valid for
7264 a data instruction. We do this by pushing the expression into a symbol
7265 in the expr_section, and creating a fix for that. */
7268 fix_new_arm (fragS
* frag
,
7283 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
7287 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
7292 /* Mark whether the fix is to a THUMB instruction, or an ARM
7294 new_fix
->tc_fix_data
= thumb_mode
;
7298 output_inst (const char * str
)
7304 as_bad ("%s -- `%s'", inst
.error
, str
);
7310 to
= frag_more (inst
.size
);
7312 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
7314 assert (inst
.size
== (2 * THUMB_SIZE
));
7315 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
7316 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
7318 else if (inst
.size
> INSN_SIZE
)
7320 assert (inst
.size
== (2 * INSN_SIZE
));
7321 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
7322 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
7325 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
7327 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7328 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
7329 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
7333 dwarf2_emit_insn (inst
.size
);
7337 /* Tag values used in struct asm_opcode's tag field. */
7340 OT_unconditional
, /* Instruction cannot be conditionalized.
7341 The ARM condition field is still 0xE. */
7342 OT_unconditionalF
, /* Instruction cannot be conditionalized
7343 and carries 0xF in its ARM condition field. */
7344 OT_csuffix
, /* Instruction takes a conditional suffix. */
7345 OT_cinfix3
, /* Instruction takes a conditional infix,
7346 beginning at character index 3. (In
7347 unified mode, it becomes a suffix.) */
7348 OT_csuf_or_in3
, /* Instruction takes either a conditional
7349 suffix or an infix at character index 3.
7350 (In unified mode, a suffix only. */
7351 OT_odd_infix_unc
, /* This is the unconditional variant of an
7352 instruction that takes a conditional infix
7353 at an unusual position. In unified mode,
7354 this variant will accept a suffix. */
7355 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
7356 are the conditional variants of instructions that
7357 take conditional infixes in unusual positions.
7358 The infix appears at character index
7359 (tag - OT_odd_infix_0). These are not accepted
7363 /* Subroutine of md_assemble, responsible for looking up the primary
7364 opcode from the mnemonic the user wrote. STR points to the
7365 beginning of the mnemonic.
7367 This is not simply a hash table lookup, because of conditional
7368 variants. Most instructions have conditional variants, which are
7369 expressed with a _conditional affix_ to the mnemonic. If we were
7370 to encode each conditional variant as a literal string in the opcode
7371 table, it would have approximately 20,000 entries.
7373 Most mnemonics take this affix as a suffix, and in unified syntax,
7374 'most' is upgraded to 'all'. However, in the divided syntax, some
7375 instructions take the affix as an infix, notably the s-variants of
7376 the arithmetic instructions. Of those instructions, all but six
7377 have the infix appear after the third character of the mnemonic.
7379 Accordingly, the algorithm for looking up primary opcodes given
7382 1. Look up the identifier in the opcode table.
7383 If we find a match, go to step U.
7385 2. Look up the last two characters of the identifier in the
7386 conditions table. If we find a match, look up the first N-2
7387 characters of the identifier in the opcode table. If we
7388 find a match, go to step CE.
7390 3. Look up the fourth and fifth characters of the identifier in
7391 the conditions table. If we find a match, extract those
7392 characters from the identifier, and look up the remaining
7393 characters in the opcode table. If we find a match, go
7398 U. Examine the tag field of the opcode structure, in case this is
7399 one of the six instructions with its conditional infix in an
7400 unusual place. If it is, the tag tells us where to find the
7401 infix; look it up in the conditions table and set inst.cond
7402 accordingly. Otherwise, this is an unconditional instruction.
7403 Again set inst.cond accordingly. Return the opcode structure.
7405 CE. Examine the tag field to make sure this is an instruction that
7406 should receive a conditional suffix. If it is not, fail.
7407 Otherwise, set inst.cond from the suffix we already looked up,
7408 and return the opcode structure.
7410 CM. Examine the tag field to make sure this is an instruction that
7411 should receive a conditional infix after the third character.
7412 If it is not, fail. Otherwise, undo the edits to the current
7413 line of input and proceed as for case CE. */
7415 static const struct asm_opcode
*
7416 opcode_lookup (char **str
)
7420 const struct asm_opcode
*opcode
;
7421 const struct asm_cond
*cond
;
7423 /* Scan up to the end of the mnemonic, which must end in white space,
7424 '.' (in unified mode only), or end of string. */
7425 for (base
= end
= *str
; *end
!= '\0'; end
++)
7426 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
7432 /* Handle a possible width suffix. */
7435 if (end
[1] == 'w' && (end
[2] == ' ' || end
[2] == '\0'))
7437 else if (end
[1] == 'n' && (end
[2] == ' ' || end
[2] == '\0'))
7447 /* Look for unaffixed or special-case affixed mnemonic. */
7448 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
7452 if (opcode
->tag
< OT_odd_infix_0
)
7454 inst
.cond
= COND_ALWAYS
;
7459 as_warn (_("conditional infixes are deprecated in unified syntax"));
7460 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
7461 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7464 inst
.cond
= cond
->value
;
7468 /* Cannot have a conditional suffix on a mnemonic of less than two
7473 /* Look for suffixed mnemonic. */
7475 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7476 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
7480 switch (opcode
->tag
)
7483 case OT_odd_infix_unc
:
7484 if (!unified_syntax
)
7486 /* else fall through */
7489 case OT_csuf_or_in3
:
7490 inst
.cond
= cond
->value
;
7493 case OT_unconditional
:
7494 case OT_unconditionalF
:
7495 /* delayed diagnostic */
7496 inst
.error
= BAD_COND
;
7497 inst
.cond
= COND_ALWAYS
;
7505 /* Cannot have a usual-position infix on a mnemonic of less than
7506 six characters (five would be a suffix). */
7510 /* Look for infixed mnemonic in the usual position. */
7512 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
7516 memcpy (save
, affix
, 2);
7517 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
7518 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
7519 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
7520 memcpy (affix
, save
, 2);
7522 if (opcode
&& (opcode
->tag
== OT_cinfix3
|| opcode
->tag
== OT_csuf_or_in3
))
7526 as_warn (_("conditional infixes are deprecated in unified syntax"));
7528 inst
.cond
= cond
->value
;
7536 md_assemble (char *str
)
7539 const struct asm_opcode
* opcode
;
7541 /* Align the previous label if needed. */
7542 if (last_label_seen
!= NULL
)
7544 symbol_set_frag (last_label_seen
, frag_now
);
7545 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7546 S_SET_SEGMENT (last_label_seen
, now_seg
);
7549 memset (&inst
, '\0', sizeof (inst
));
7550 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7552 opcode
= opcode_lookup (&p
);
7555 /* It wasn't an instruction, but it might be a register alias of
7556 the form alias .req reg. */
7557 if (!create_register_alias (str
, p
))
7558 as_bad (_("bad instruction `%s'"), str
);
7565 /* Check that this instruction is supported for this CPU. */
7566 if (thumb_mode
== 1 && (opcode
->tvariant
& cpu_variant
) == 0)
7568 as_bad (_("selected processor does not support `%s'"), str
);
7571 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
7572 && opcode
->tencode
!= do_t_branch
)
7574 as_bad (_("Thumb does not support conditional execution"));
7578 mapping_state (MAP_THUMB
);
7579 inst
.instruction
= opcode
->tvalue
;
7581 if (!parse_operands (p
, opcode
->operands
))
7586 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
7587 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
7588 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
7590 as_bad (_("cannot honor width suffix -- `%s'"), str
);
7597 /* Check that this instruction is supported for this CPU. */
7598 if ((opcode
->avariant
& cpu_variant
) == 0)
7600 as_bad (_("selected processor does not support `%s'"), str
);
7605 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
7609 mapping_state (MAP_ARM
);
7610 inst
.instruction
= opcode
->avalue
;
7611 if (opcode
->tag
== OT_unconditionalF
)
7612 inst
.instruction
|= 0xF << 28;
7614 inst
.instruction
|= inst
.cond
<< 28;
7615 inst
.size
= INSN_SIZE
;
7616 if (!parse_operands (p
, opcode
->operands
))
7622 /* Various frobbings of labels and their addresses. */
7625 arm_start_line_hook (void)
7627 last_label_seen
= NULL
;
7631 arm_frob_label (symbolS
* sym
)
7633 last_label_seen
= sym
;
7635 ARM_SET_THUMB (sym
, thumb_mode
);
7637 #if defined OBJ_COFF || defined OBJ_ELF
7638 ARM_SET_INTERWORK (sym
, support_interwork
);
7641 /* Note - do not allow local symbols (.Lxxx) to be labeled
7642 as Thumb functions. This is because these labels, whilst
7643 they exist inside Thumb code, are not the entry points for
7644 possible ARM->Thumb calls. Also, these labels can be used
7645 as part of a computed goto or switch statement. eg gcc
7646 can generate code that looks like this:
7658 The first instruction loads the address of the jump table.
7659 The second instruction converts a table index into a byte offset.
7660 The third instruction gets the jump address out of the table.
7661 The fourth instruction performs the jump.
7663 If the address stored at .Laaa is that of a symbol which has the
7664 Thumb_Func bit set, then the linker will arrange for this address
7665 to have the bottom bit set, which in turn would mean that the
7666 address computation performed by the third instruction would end
7667 up with the bottom bit set. Since the ARM is capable of unaligned
7668 word loads, the instruction would then load the incorrect address
7669 out of the jump table, and chaos would ensue. */
7670 if (label_is_thumb_function_name
7671 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
7672 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
7674 /* When the address of a Thumb function is taken the bottom
7675 bit of that address should be set. This will allow
7676 interworking between Arm and Thumb functions to work
7679 THUMB_SET_FUNC (sym
, 1);
7681 label_is_thumb_function_name
= FALSE
;
7686 arm_data_in_code (void)
7688 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
7690 *input_line_pointer
= '/';
7691 input_line_pointer
+= 5;
7692 *input_line_pointer
= 0;
7700 arm_canonicalize_symbol_name (char * name
)
7704 if (thumb_mode
&& (len
= strlen (name
)) > 5
7705 && streq (name
+ len
- 5, "/data"))
7706 *(name
+ len
- 5) = 0;
7711 /* Table of all register names defined by default. The user can
7712 define additional names with .req. Note that all register names
7713 should appear in both upper and lowercase variants. Some registers
7714 also have mixed-case names. */
7716 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7717 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7718 #define REGSET(p,t) \
7719 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7720 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7721 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7722 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7724 static const struct reg_entry reg_names
[] =
7726 /* ARM integer registers. */
7727 REGSET(r
, RN
), REGSET(R
, RN
),
7729 /* ATPCS synonyms. */
7730 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
7731 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
7732 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
7734 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
7735 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
7736 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
7738 /* Well-known aliases. */
7739 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
7740 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
7742 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
7743 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
7745 /* Coprocessor numbers. */
7746 REGSET(p
, CP
), REGSET(P
, CP
),
7748 /* Coprocessor register numbers. The "cr" variants are for backward
7750 REGSET(c
, CN
), REGSET(C
, CN
),
7751 REGSET(cr
, CN
), REGSET(CR
, CN
),
7753 /* FPA registers. */
7754 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
7755 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
7757 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
7758 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
7760 /* VFP SP registers. */
7762 REGNUM(s
,16,VFS
), REGNUM(s
,17,VFS
), REGNUM(s
,18,VFS
), REGNUM(s
,19,VFS
),
7763 REGNUM(s
,20,VFS
), REGNUM(s
,21,VFS
), REGNUM(s
,22,VFS
), REGNUM(s
,23,VFS
),
7764 REGNUM(s
,24,VFS
), REGNUM(s
,25,VFS
), REGNUM(s
,26,VFS
), REGNUM(s
,27,VFS
),
7765 REGNUM(s
,28,VFS
), REGNUM(s
,29,VFS
), REGNUM(s
,30,VFS
), REGNUM(s
,31,VFS
),
7768 REGNUM(S
,16,VFS
), REGNUM(S
,17,VFS
), REGNUM(S
,18,VFS
), REGNUM(S
,19,VFS
),
7769 REGNUM(S
,20,VFS
), REGNUM(S
,21,VFS
), REGNUM(S
,22,VFS
), REGNUM(S
,23,VFS
),
7770 REGNUM(S
,24,VFS
), REGNUM(S
,25,VFS
), REGNUM(S
,26,VFS
), REGNUM(S
,27,VFS
),
7771 REGNUM(S
,28,VFS
), REGNUM(S
,29,VFS
), REGNUM(S
,30,VFS
), REGNUM(S
,31,VFS
),
7773 /* VFP DP Registers. */
7774 REGSET(d
,VFD
), REGSET(D
,VFS
),
7776 /* VFP control registers. */
7777 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
7778 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
7780 /* Maverick DSP coprocessor registers. */
7781 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
7782 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
7784 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
7785 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
7786 REGDEF(dspsc
,0,DSPSC
),
7788 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
7789 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
7790 REGDEF(DSPSC
,0,DSPSC
),
7792 /* iWMMXt data registers - p0, c0-15. */
7793 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
7795 /* iWMMXt control registers - p1, c0-3. */
7796 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
7797 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
7798 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
7799 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
7801 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
7802 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
7803 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
7804 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
7805 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
7807 /* XScale accumulator registers. */
7808 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
7814 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
7815 within psr_required_here. */
7816 static const struct asm_psr psrs
[] =
7818 /* Backward compatibility notation. Note that "all" is no longer
7819 truly all possible PSR bits. */
7820 {"all", PSR_c
| PSR_f
},
7824 /* Individual flags. */
7829 /* Combinations of flags. */
7830 {"fs", PSR_f
| PSR_s
},
7831 {"fx", PSR_f
| PSR_x
},
7832 {"fc", PSR_f
| PSR_c
},
7833 {"sf", PSR_s
| PSR_f
},
7834 {"sx", PSR_s
| PSR_x
},
7835 {"sc", PSR_s
| PSR_c
},
7836 {"xf", PSR_x
| PSR_f
},
7837 {"xs", PSR_x
| PSR_s
},
7838 {"xc", PSR_x
| PSR_c
},
7839 {"cf", PSR_c
| PSR_f
},
7840 {"cs", PSR_c
| PSR_s
},
7841 {"cx", PSR_c
| PSR_x
},
7842 {"fsx", PSR_f
| PSR_s
| PSR_x
},
7843 {"fsc", PSR_f
| PSR_s
| PSR_c
},
7844 {"fxs", PSR_f
| PSR_x
| PSR_s
},
7845 {"fxc", PSR_f
| PSR_x
| PSR_c
},
7846 {"fcs", PSR_f
| PSR_c
| PSR_s
},
7847 {"fcx", PSR_f
| PSR_c
| PSR_x
},
7848 {"sfx", PSR_s
| PSR_f
| PSR_x
},
7849 {"sfc", PSR_s
| PSR_f
| PSR_c
},
7850 {"sxf", PSR_s
| PSR_x
| PSR_f
},
7851 {"sxc", PSR_s
| PSR_x
| PSR_c
},
7852 {"scf", PSR_s
| PSR_c
| PSR_f
},
7853 {"scx", PSR_s
| PSR_c
| PSR_x
},
7854 {"xfs", PSR_x
| PSR_f
| PSR_s
},
7855 {"xfc", PSR_x
| PSR_f
| PSR_c
},
7856 {"xsf", PSR_x
| PSR_s
| PSR_f
},
7857 {"xsc", PSR_x
| PSR_s
| PSR_c
},
7858 {"xcf", PSR_x
| PSR_c
| PSR_f
},
7859 {"xcs", PSR_x
| PSR_c
| PSR_s
},
7860 {"cfs", PSR_c
| PSR_f
| PSR_s
},
7861 {"cfx", PSR_c
| PSR_f
| PSR_x
},
7862 {"csf", PSR_c
| PSR_s
| PSR_f
},
7863 {"csx", PSR_c
| PSR_s
| PSR_x
},
7864 {"cxf", PSR_c
| PSR_x
| PSR_f
},
7865 {"cxs", PSR_c
| PSR_x
| PSR_s
},
7866 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
7867 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
7868 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
7869 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
7870 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
7871 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
7872 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
7873 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
7874 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
7875 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
7876 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
7877 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
7878 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
7879 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
7880 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
7881 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
7882 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
7883 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
7884 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
7885 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
7886 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
7887 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
7888 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
7889 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
7892 /* Table of all shift-in-operand names. */
7893 static const struct asm_shift_name shift_names
[] =
7895 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
7896 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
7897 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
7898 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
7899 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
7900 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
7903 /* Table of all explicit relocation names. */
7905 static struct reloc_entry reloc_names
[] =
7907 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
7908 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
7909 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
7910 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
7911 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
7912 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
7913 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
7914 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
7915 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
7916 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
7917 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
7921 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
7922 static const struct asm_cond conds
[] =
7926 {"cs", 0x2}, {"hs", 0x2},
7927 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
7941 /* Table of ARM-format instructions. */
7943 /* Macros for gluing together operand strings. N.B. In all cases
7944 other than OPS0, the trailing OP_stop comes from default
7945 zero-initialization of the unspecified elements of the array. */
7946 #define OPS0() { OP_stop, }
7947 #define OPS1(a) { OP_##a, }
7948 #define OPS2(a,b) { OP_##a,OP_##b, }
7949 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
7950 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
7951 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
7952 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
7954 /* These macros abstract out the exact format of the mnemonic table and
7955 save some repeated characters. */
7957 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
7958 #define TxCE(mnem, op, top, nops, ops, ae, te) \
7959 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
7960 THUMB_VARIANT, do_##ae, do_##te }
7962 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
7963 a T_MNEM_xyz enumerator. */
7964 #define TCE(mnem, aop, top, nops, ops, ae, te) \
7965 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
7966 #define tCE(mnem, aop, top, nops, ops, ae, te) \
7967 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7969 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
7970 infix after the third character. */
7971 #define TxC3(mnem, op, top, nops, ops, ae, te) \
7972 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
7973 THUMB_VARIANT, do_##ae, do_##te }
7974 #define TC3(mnem, aop, top, nops, ops, ae, te) \
7975 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
7976 #define tC3(mnem, aop, top, nops, ops, ae, te) \
7977 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7979 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
7980 appear in the condition table. */
7981 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
7982 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
7983 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
7985 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
7986 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
7987 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
7988 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
7989 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
7990 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
7991 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
7992 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
7993 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
7994 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
7995 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
7996 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
7997 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
7998 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
7999 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8000 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8001 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8002 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8003 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8004 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8006 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8007 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8008 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8009 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8011 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8012 field is still 0xE. */
8013 #define TUE(mnem, op, top, nops, ops, ae, te) \
8014 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8015 THUMB_VARIANT, do_##ae, do_##te }
8017 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8018 condition code field. */
8019 #define TUF(mnem, op, top, nops, ops, ae, te) \
8020 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8021 THUMB_VARIANT, do_##ae, do_##te }
8023 /* ARM-only variants of all the above. */
8024 #define CE(mnem, op, nops, ops, ae) \
8025 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8027 #define C3(mnem, op, nops, ops, ae) \
8028 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8030 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8031 { #m1 #m2 #m3, OPS##nops ops, \
8032 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8033 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8035 #define CM(m1, m2, op, nops, ops, ae) \
8036 xCM_(m1, , m2, op, nops, ops, ae), \
8037 xCM_(m1, eq, m2, op, nops, ops, ae), \
8038 xCM_(m1, ne, m2, op, nops, ops, ae), \
8039 xCM_(m1, cs, m2, op, nops, ops, ae), \
8040 xCM_(m1, hs, m2, op, nops, ops, ae), \
8041 xCM_(m1, cc, m2, op, nops, ops, ae), \
8042 xCM_(m1, ul, m2, op, nops, ops, ae), \
8043 xCM_(m1, lo, m2, op, nops, ops, ae), \
8044 xCM_(m1, mi, m2, op, nops, ops, ae), \
8045 xCM_(m1, pl, m2, op, nops, ops, ae), \
8046 xCM_(m1, vs, m2, op, nops, ops, ae), \
8047 xCM_(m1, vc, m2, op, nops, ops, ae), \
8048 xCM_(m1, hi, m2, op, nops, ops, ae), \
8049 xCM_(m1, ls, m2, op, nops, ops, ae), \
8050 xCM_(m1, ge, m2, op, nops, ops, ae), \
8051 xCM_(m1, lt, m2, op, nops, ops, ae), \
8052 xCM_(m1, gt, m2, op, nops, ops, ae), \
8053 xCM_(m1, le, m2, op, nops, ops, ae), \
8054 xCM_(m1, al, m2, op, nops, ops, ae)
8056 #define UE(mnem, op, nops, ops, ae) \
8057 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8059 #define UF(mnem, op, nops, ops, ae) \
8060 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8064 /* Thumb-only, unconditional. */
8065 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8067 /* ARM-only, takes either a suffix or a position-3 infix
8068 (for an FPA corner case). */
8069 #define C3E(mnem, op, nops, ops, ae) \
8070 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8072 static const struct asm_opcode insns
[] =
8074 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8075 #define THUMB_VARIANT ARM_EXT_V4T
8076 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8077 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8078 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8079 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8080 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8081 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8082 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8083 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8084 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8085 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8086 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8087 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8088 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8089 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8090 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8091 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8093 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8094 for setting PSR flag bits. They are obsolete in V6 and do not
8095 have Thumb equivalents. */
8096 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8097 tC3(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8098 C3(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
8099 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8100 tC3(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8101 C3(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
8102 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8103 tC3(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8104 C3(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
8106 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8107 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8108 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8109 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8111 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8112 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8113 tCE(str
, 4000000, str
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8114 tC3(strb
, 4400000, strb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8116 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8117 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8118 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8119 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8121 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
8122 TCE(b
, a000000
, e000
, 1, (EXPr
), branch
, t_branch
),
8123 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), branch
, t_branch23
),
8126 TCE(adr
, 28f0000
, 000f
, 2, (RR
, EXP
), adr
, t_adr
),
8127 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
8128 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
8130 /* Thumb-compatibility pseudo ops. */
8131 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8132 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8133 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8134 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8135 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8136 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8137 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8138 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8139 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
8140 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
8141 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
8142 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
8144 #undef THUMB_VARIANT
8145 #define THUMB_VARIANT ARM_EXT_V6
8146 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
8148 /* V1 instructions with no Thumb analogue prior to V6T2. */
8149 #undef THUMB_VARIANT
8150 #define THUMB_VARIANT ARM_EXT_V6T2
8151 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8152 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8153 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8154 TC3(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8155 C3(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
8157 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8158 TC3(ldrbt
, 4700000, f8300e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8159 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8160 TC3(strbt
, 4600000, f8200e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8162 TC3(stmdb
, 9000000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8163 TC3(stmfd
, 9000000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8165 TC3(ldmdb
, 9100000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8166 TC3(ldmea
, 9100000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8168 /* V1 instructions with no Thumb analogue at all. */
8169 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
8170 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
8172 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8173 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8174 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8175 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8176 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8177 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8178 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8179 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8182 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8183 #undef THUMB_VARIANT
8184 #define THUMB_VARIANT ARM_EXT_V4T
8185 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8186 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8188 #undef THUMB_VARIANT
8189 #define THUMB_VARIANT ARM_EXT_V6T2
8190 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
8191 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
8193 /* Generic coprocessor instructions. */
8194 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8195 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8196 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8197 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8198 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8199 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8200 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8203 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8204 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8205 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8208 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8209 TCE(mrs
, 10f0000
, f3ef8000
, 2, (RR
, PSR
), mrs
, t_mrs
),
8210 TCE(msr
, 120f000
, f3808000
, 2, (PSR
, RR_EXi
), msr
, t_msr
),
8213 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8214 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8215 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8216 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8217 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8218 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8219 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8220 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8221 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8224 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8225 #undef THUMB_VARIANT
8226 #define THUMB_VARIANT ARM_EXT_V4T
8227 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8228 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8229 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8230 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8231 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8232 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8235 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8236 /* ARM Architecture 4T. */
8237 /* Note: bx (and blx) are required on V5, even if the processor does
8238 not support Thumb. */
8239 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
8242 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8243 #undef THUMB_VARIANT
8244 #define THUMB_VARIANT ARM_EXT_V5T
8245 /* Note: blx has 2 variants; the .value coded here is for
8246 BLX(2). Only this variant has conditional execution. */
8247 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
8248 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
8250 #undef THUMB_VARIANT
8251 #define THUMB_VARIANT ARM_EXT_V6T2
8252 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
8253 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8254 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8255 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8256 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8257 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8258 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8259 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8262 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8263 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8264 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8265 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8266 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8268 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8269 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8271 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8272 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8273 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8274 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8276 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8277 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8278 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8279 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8281 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8282 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8284 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8285 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8286 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8287 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8290 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8291 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
8292 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8293 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8295 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8296 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8299 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8300 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
8303 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8304 #undef THUMB_VARIANT
8305 #define THUMB_VARIANT ARM_EXT_V6
8306 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8307 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8308 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8309 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8310 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8311 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8312 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8313 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8314 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8315 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
8317 #undef THUMB_VARIANT
8318 #define THUMB_VARIANT ARM_EXT_V6T2
8319 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, imm0
),
8320 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
8321 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8322 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8323 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
8324 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
8325 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8326 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8327 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8328 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8329 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8330 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8331 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8332 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8333 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8334 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8335 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8336 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8337 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8338 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8339 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8340 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8341 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8342 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8343 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8344 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8345 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8346 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8347 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8348 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8349 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8350 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8351 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8352 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8353 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8354 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8355 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8356 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8357 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8358 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8359 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8360 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8361 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
8362 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
8363 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
8364 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
8365 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
8366 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
8367 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
8368 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
8369 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8370 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8371 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8372 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8373 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8374 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8375 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
8376 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8377 TCE(sel
, 68000b0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8378 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8379 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8380 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8381 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8382 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8383 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8384 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8385 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
8386 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8387 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8388 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8389 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8390 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8391 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8392 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8393 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8394 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8395 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8396 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
8397 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
8398 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
8399 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
8400 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
8401 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
8402 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
8403 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
8404 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8405 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
8406 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
8407 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
8410 #define ARM_VARIANT ARM_EXT_V6K
8411 #undef THUMB_VARIANT
8412 #define THUMB_VARIANT ARM_EXT_V6K
8413 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
8414 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
8415 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
8416 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
8418 #undef THUMB_VARIANT
8419 #define THUMB_VARIANT ARM_EXT_V6T2
8420 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
8421 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
8422 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
8423 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
8424 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
8425 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
8426 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
8429 #define ARM_VARIANT ARM_EXT_V6Z
8430 TCE(smi
, 1600070, f7f08000
, 1, (EXPi
), smi
, t_smi
),
8433 #define ARM_VARIANT ARM_EXT_V6T2
8434 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
8435 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
8436 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
8437 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
8439 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
8440 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
8441 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
8442 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
8444 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8445 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8446 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8447 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
8449 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
8450 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
8451 /* ARM does not really have an IT instruction. */
8452 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
8453 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
8454 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
8455 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
8456 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
8457 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
8458 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
8459 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
8460 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
8461 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
8462 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
8463 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
8464 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
8465 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
8466 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
8469 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8470 CE(wfs
, e200110
, 1, (RR
), rd
),
8471 CE(rfs
, e300110
, 1, (RR
), rd
),
8472 CE(wfc
, e400110
, 1, (RR
), rd
),
8473 CE(rfc
, e500110
, 1, (RR
), rd
),
8475 C3(ldfs
, c100100
, 2, (RF
, ADDR
), rd_cpaddr
),
8476 C3(ldfd
, c108100
, 2, (RF
, ADDR
), rd_cpaddr
),
8477 C3(ldfe
, c500100
, 2, (RF
, ADDR
), rd_cpaddr
),
8478 C3(ldfp
, c508100
, 2, (RF
, ADDR
), rd_cpaddr
),
8480 C3(stfs
, c000100
, 2, (RF
, ADDR
), rd_cpaddr
),
8481 C3(stfd
, c008100
, 2, (RF
, ADDR
), rd_cpaddr
),
8482 C3(stfe
, c400100
, 2, (RF
, ADDR
), rd_cpaddr
),
8483 C3(stfp
, c408100
, 2, (RF
, ADDR
), rd_cpaddr
),
8485 C3(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
8486 C3(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
8487 C3(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
8488 C3(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
8489 C3(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
8490 C3(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
8491 C3(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
8492 C3(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
8493 C3(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
8494 C3(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
8495 C3(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
8496 C3(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
8498 C3(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
8499 C3(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
8500 C3(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
8501 C3(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
8502 C3(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
8503 C3(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
8504 C3(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
8505 C3(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
8506 C3(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
8507 C3(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
8508 C3(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
8509 C3(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
8511 C3(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
8512 C3(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
8513 C3(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
8514 C3(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
8515 C3(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
8516 C3(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
8517 C3(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
8518 C3(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
8519 C3(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
8520 C3(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
8521 C3(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
8522 C3(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
8524 C3(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
8525 C3(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
8526 C3(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
8527 C3(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
8528 C3(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
8529 C3(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
8530 C3(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
8531 C3(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
8532 C3(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
8533 C3(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
8534 C3(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
8535 C3(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
8537 C3(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
8538 C3(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
8539 C3(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
8540 C3(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
8541 C3(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
8542 C3(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
8543 C3(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
8544 C3(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
8545 C3(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
8546 C3(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
8547 C3(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
8548 C3(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
8550 C3(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
8551 C3(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
8552 C3(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
8553 C3(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
8554 C3(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
8555 C3(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
8556 C3(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
8557 C3(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
8558 C3(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
8559 C3(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
8560 C3(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
8561 C3(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
8563 C3(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
8564 C3(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
8565 C3(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
8566 C3(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
8567 C3(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
8568 C3(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
8569 C3(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
8570 C3(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
8571 C3(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
8572 C3(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
8573 C3(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
8574 C3(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
8576 C3(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
8577 C3(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
8578 C3(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
8579 C3(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
8580 C3(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
8581 C3(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
8582 C3(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
8583 C3(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
8584 C3(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
8585 C3(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
8586 C3(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
8587 C3(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
8589 C3(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
8590 C3(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
8591 C3(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
8592 C3(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
8593 C3(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
8594 C3(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
8595 C3(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
8596 C3(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
8597 C3(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
8598 C3(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
8599 C3(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
8600 C3(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
8602 C3(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
8603 C3(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
8604 C3(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
8605 C3(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
8606 C3(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
8607 C3(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
8608 C3(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
8609 C3(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
8610 C3(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
8611 C3(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
8612 C3(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
8613 C3(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
8615 C3(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
8616 C3(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
8617 C3(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
8618 C3(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
8619 C3(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
8620 C3(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
8621 C3(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
8622 C3(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
8623 C3(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
8624 C3(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
8625 C3(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
8626 C3(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
8628 C3(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
8629 C3(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
8630 C3(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
8631 C3(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
8632 C3(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
8633 C3(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
8634 C3(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
8635 C3(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
8636 C3(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
8637 C3(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
8638 C3(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
8639 C3(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
8641 C3(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
8642 C3(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
8643 C3(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
8644 C3(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
8645 C3(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
8646 C3(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
8647 C3(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
8648 C3(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
8649 C3(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
8650 C3(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
8651 C3(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
8652 C3(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
8654 C3(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
8655 C3(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
8656 C3(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
8657 C3(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
8658 C3(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
8659 C3(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
8660 C3(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
8661 C3(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
8662 C3(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
8663 C3(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
8664 C3(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
8665 C3(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
8667 C3(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
8668 C3(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
8669 C3(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
8670 C3(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
8671 C3(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
8672 C3(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
8673 C3(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
8674 C3(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
8675 C3(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
8676 C3(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
8677 C3(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
8678 C3(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
8680 C3(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
8681 C3(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
8682 C3(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
8683 C3(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
8684 C3(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
8685 C3(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
8686 C3(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
8687 C3(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
8688 C3(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
8689 C3(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
8690 C3(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
8691 C3(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
8693 C3(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8694 C3(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8695 C3(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8696 C3(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8697 C3(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8698 C3(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8699 C3(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8700 C3(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8701 C3(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8702 C3(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8703 C3(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8704 C3(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8706 C3(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8707 C3(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8708 C3(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8709 C3(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8710 C3(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8711 C3(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8712 C3(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8713 C3(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8714 C3(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8715 C3(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8716 C3(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8717 C3(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8719 C3(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8720 C3(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8721 C3(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8722 C3(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8723 C3(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8724 C3(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8725 C3(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8726 C3(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8727 C3(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8728 C3(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8729 C3(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8730 C3(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8732 C3(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8733 C3(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8734 C3(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8735 C3(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8736 C3(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8737 C3(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8738 C3(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8739 C3(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8740 C3(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8741 C3(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8742 C3(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8743 C3(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8745 C3(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8746 C3(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8747 C3(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8748 C3(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8749 C3(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8750 C3(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8751 C3(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8752 C3(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8753 C3(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8754 C3(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8755 C3(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8756 C3(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8758 C3(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8759 C3(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8760 C3(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8761 C3(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8762 C3(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8763 C3(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8764 C3(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8765 C3(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8766 C3(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8767 C3(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8768 C3(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8769 C3(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8771 C3(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8772 C3(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8773 C3(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8774 C3(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8775 C3(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8776 C3(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8777 C3(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8778 C3(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8779 C3(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8780 C3(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8781 C3(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8782 C3(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8784 C3(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8785 C3(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8786 C3(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8787 C3(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8788 C3(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8789 C3(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8790 C3(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8791 C3(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8792 C3(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8793 C3(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8794 C3(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8795 C3(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8797 C3(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8798 C3(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8799 C3(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8800 C3(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8801 C3(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8802 C3(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8803 C3(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8804 C3(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8805 C3(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8806 C3(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8807 C3(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8808 C3(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8810 C3(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8811 C3(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8812 C3(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8813 C3(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8814 C3(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8815 C3(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8816 C3(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8817 C3(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8818 C3(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8819 C3(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8820 C3(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8821 C3(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8823 C3(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8824 C3(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8825 C3(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8826 C3(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8827 C3(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8828 C3(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8829 C3(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8830 C3(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8831 C3(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8832 C3(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8833 C3(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8834 C3(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8836 C3(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8837 C3(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8838 C3(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8839 C3(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8840 C3(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8841 C3(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8842 C3(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8843 C3(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8844 C3(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8845 C3(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8846 C3(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8847 C3(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8849 C3(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8850 C3(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8851 C3(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8852 C3(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8853 C3(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8854 C3(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8855 C3(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8856 C3(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8857 C3(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8858 C3(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8859 C3(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8860 C3(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
8862 CE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
8863 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
8864 CE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
8865 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
8867 C3(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
8868 C3(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
8869 C3(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
8870 C3(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
8871 C3(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
8872 C3(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
8873 C3(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
8874 C3(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
8875 C3(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
8876 C3(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
8877 C3(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
8878 C3(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
8880 /* The implementation of the FIX instruction is broken on some
8881 assemblers, in that it accepts a precision specifier as well as a
8882 rounding specifier, despite the fact that this is meaningless.
8883 To be more compatible, we accept it as well, though of course it
8884 does not set any bits. */
8885 CE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
8886 C3(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
8887 C3(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
8888 C3(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
8889 C3(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
8890 C3(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
8891 C3(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
8892 C3(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
8893 C3(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
8894 C3(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
8895 C3(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
8896 C3(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
8897 C3(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
8899 /* Instructions that were new with the real FPA, call them V2. */
8901 #define ARM_VARIANT FPU_FPA_EXT_V2
8902 CE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8903 C3(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8904 C3(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8905 CE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8906 C3(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8907 C3(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
8910 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
8911 /* Moves and type conversions. */
8912 CE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8913 CE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
8914 CE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
8915 CE(fmstat
, ef1fa10
, 0, (), noargs
),
8916 CE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8917 CE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8918 CE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8919 CE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8920 CE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8921 CE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8922 CE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
8923 CE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
8925 /* Memory operations. */
8926 CE(flds
, d100a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
8927 CE(fsts
, d000a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
8928 CE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
8929 CE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
8930 CE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
8931 CE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
8932 CE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
8933 CE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
8934 CE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
8935 CE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
8936 CE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
8937 CE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
8938 CE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
8939 CE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
8940 CE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
8941 CE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
8942 CE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
8943 CE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
8945 /* Monadic operations. */
8946 CE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8947 CE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8948 CE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8950 /* Dyadic operations. */
8951 CE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8952 CE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8953 CE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8954 CE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8955 CE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8956 CE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8957 CE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8958 CE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8959 CE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
8962 CE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8963 CE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
8964 CE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
8965 CE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
8968 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
8969 /* Moves and type conversions. */
8970 CE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), rd_rm
),
8971 CE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
8972 CE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
8973 CE(fmdhr
, e200b10
, 2, (RVD
, RR
), rn_rd
),
8974 CE(fmdlr
, e000b10
, 2, (RVD
, RR
), rn_rd
),
8975 CE(fmrdh
, e300b10
, 2, (RR
, RVD
), rd_rn
),
8976 CE(fmrdl
, e100b10
, 2, (RR
, RVD
), rd_rn
),
8977 CE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
8978 CE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
8979 CE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
8980 CE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
8981 CE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
8982 CE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
8984 /* Memory operations. */
8985 CE(fldd
, d100b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
8986 CE(fstd
, d000b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
8987 CE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
8988 CE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
8989 CE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
8990 CE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
8991 CE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
8992 CE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
8993 CE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
8994 CE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
8996 /* Monadic operations. */
8997 CE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), rd_rm
),
8998 CE(fnegd
, eb10b40
, 2, (RVD
, RVD
), rd_rm
),
8999 CE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), rd_rm
),
9001 /* Dyadic operations. */
9002 CE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9003 CE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9004 CE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9005 CE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9006 CE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9007 CE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9008 CE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9009 CE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9010 CE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9013 CE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), rd_rm
),
9014 CE(fcmpzd
, eb50b40
, 1, (RVD
), rd
),
9015 CE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), rd_rm
),
9016 CE(fcmpezd
, eb50bc0
, 1, (RVD
), rd
),
9019 #define ARM_VARIANT FPU_VFP_EXT_V2
9020 CE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
9021 CE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
9022 CE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), rm_rd_rn
),
9023 CE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), rd_rn_rm
),
9026 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9027 CE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9028 CE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9029 CE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9030 CE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9031 CE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9032 CE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9033 CE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
9034 CE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
9037 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9038 CE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
9039 CE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
9040 CE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
9041 CE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
9042 CE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
9043 CE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
9044 CE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
9045 CE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
9046 CE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
9047 CE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9048 CE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9049 CE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9050 CE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9051 CE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9052 CE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9053 CE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9054 CE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9055 CE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9056 CE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
9057 CE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
9058 CE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9059 CE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9060 CE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9061 CE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9062 CE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9063 CE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9064 CE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
9065 CE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
9066 CE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
9067 CE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
9068 CE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
9069 CE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
9070 CE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
9071 CE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
9072 CE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9073 CE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9074 CE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9075 CE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9076 CE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9077 CE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9078 CE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9079 CE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9080 CE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9081 CE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9082 CE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9083 CE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9084 CE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
9085 CE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9086 CE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9087 CE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9088 CE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9089 CE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9090 CE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9091 CE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9092 CE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9093 CE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9094 CE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9095 CE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9096 CE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9097 CE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9098 CE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9099 CE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9100 CE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9101 CE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9102 CE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9103 CE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9104 CE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9105 CE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9106 CE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9107 CE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9108 CE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9109 CE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9110 CE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9111 CE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9112 CE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9113 CE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9114 CE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9115 CE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9116 CE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9117 CE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9118 CE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9119 CE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9120 CE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9121 CE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9122 CE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9123 CE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9124 CE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9125 CE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9126 CE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
9127 CE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9128 CE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9129 CE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9130 CE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9131 CE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9132 CE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9133 CE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9134 CE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9135 CE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9136 CE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9137 CE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9138 CE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9139 CE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9140 CE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9141 CE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9142 CE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9143 CE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9144 CE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9145 CE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9146 CE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9147 CE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9148 CE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
9149 CE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9150 CE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9151 CE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9152 CE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9153 CE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9154 CE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9155 CE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9156 CE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9157 CE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9158 CE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9159 CE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9160 CE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9161 CE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9162 CE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9163 CE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9164 CE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9165 CE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9166 CE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9167 CE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9168 CE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9169 CE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9170 CE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9171 CE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9172 CE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9173 CE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9174 CE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9175 CE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9176 CE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9177 CE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9178 CE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9179 CE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9180 CE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9181 CE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9182 CE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9183 CE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9184 CE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9185 CE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9186 CE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9187 CE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9188 CE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9189 CE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9190 CE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9191 CE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9192 CE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9193 CE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9194 CE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9195 CE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9196 CE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9197 CE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9198 CE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9199 CE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
9202 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9203 CE(cfldrs
, c100400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9204 CE(cfldrd
, c500400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9205 CE(cfldr32
, c100500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9206 CE(cfldr64
, c500500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9207 CE(cfstrs
, c000400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9208 CE(cfstrd
, c400400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9209 CE(cfstr32
, c000500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9210 CE(cfstr64
, c400500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9211 CE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
9212 CE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
9213 CE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
9214 CE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
9215 CE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
9216 CE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
9217 CE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
9218 CE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
9219 CE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
9220 CE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
9221 CE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
9222 CE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
9223 CE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
9224 CE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
9225 CE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
9226 CE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
9227 CE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
9228 CE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
9229 CE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
9230 CE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
9231 CE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
9232 CE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
9233 CE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
9234 CE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
9235 CE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
9236 CE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
9237 CE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
9238 CE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
9239 CE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
9240 CE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
9241 CE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
9242 CE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
9243 CE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
9244 CE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
9245 CE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
9246 CE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
9247 CE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
9248 CE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
9249 CE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
9250 CE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
9251 CE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
9252 CE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
9253 CE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
9254 CE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
9255 CE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
9256 CE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
9257 CE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9258 CE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9259 CE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9260 CE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9261 CE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9262 CE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9263 CE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
9264 CE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
9265 CE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
9266 CE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
9267 CE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9268 CE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9269 CE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9270 CE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9271 CE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9272 CE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9273 CE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9274 CE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9275 CE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9276 CE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9277 CE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9278 CE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9281 #undef THUMB_VARIANT
9301 /* MD interface: bits in the object file. */
9303 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9304 for use in the a.out file, and stores them in the array pointed to by buf.
9305 This knows about the endian-ness of the target machine and does
9306 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9307 2 (short) and 4 (long) Floating numbers are put out as a series of
9308 LITTLENUMS (shorts, here at least). */
9311 md_number_to_chars (char * buf
, valueT val
, int n
)
9313 if (target_big_endian
)
9314 number_to_chars_bigendian (buf
, val
, n
);
9316 number_to_chars_littleendian (buf
, val
, n
);
9320 md_chars_to_number (char * buf
, int n
)
9323 unsigned char * where
= (unsigned char *) buf
;
9325 if (target_big_endian
)
9330 result
|= (*where
++ & 255);
9338 result
|= (where
[n
] & 255);
9345 /* MD interface: Sections. */
9348 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
9349 segT segtype ATTRIBUTE_UNUSED
)
9351 as_fatal (_("md_estimate_size_before_relax\n"));
9355 /* Round up a section size to the appropriate boundary. */
9358 md_section_align (segT segment ATTRIBUTE_UNUSED
,
9364 /* Round all sects to multiple of 4. */
9365 return (size
+ 3) & ~3;
9369 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9370 of an rs_align_code fragment. */
9373 arm_handle_align (fragS
* fragP
)
9375 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9376 static char const thumb_noop
[2] = { 0xc0, 0x46 };
9377 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9378 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
9380 int bytes
, fix
, noop_size
;
9384 if (fragP
->fr_type
!= rs_align_code
)
9387 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
9388 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
9391 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
9392 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
9394 if (fragP
->tc_frag_data
)
9396 if (target_big_endian
)
9397 noop
= thumb_bigend_noop
;
9400 noop_size
= sizeof (thumb_noop
);
9404 if (target_big_endian
)
9405 noop
= arm_bigend_noop
;
9408 noop_size
= sizeof (arm_noop
);
9411 if (bytes
& (noop_size
- 1))
9413 fix
= bytes
& (noop_size
- 1);
9419 while (bytes
>= noop_size
)
9421 memcpy (p
, noop
, noop_size
);
9427 fragP
->fr_fix
+= fix
;
9428 fragP
->fr_var
= noop_size
;
9431 /* Called from md_do_align. Used to create an alignment
9432 frag in a code section. */
9435 arm_frag_align_code (int n
, int max
)
9439 /* We assume that there will never be a requirement
9440 to support alignments greater than 32 bytes. */
9441 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
9442 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9444 p
= frag_var (rs_align_code
,
9445 MAX_MEM_FOR_RS_ALIGN_CODE
,
9447 (relax_substateT
) max
,
9454 /* Perform target specific initialisation of a frag. */
9457 arm_init_frag (fragS
* fragP
)
9459 /* Record whether this frag is in an ARM or a THUMB area. */
9460 fragP
->tc_frag_data
= thumb_mode
;
9464 /* When we change sections we need to issue a new mapping symbol. */
9467 arm_elf_change_section (void)
9470 segment_info_type
*seginfo
;
9472 /* Link an unlinked unwind index table section to the .text section. */
9473 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
9474 && elf_linked_to_section (now_seg
) == NULL
)
9475 elf_linked_to_section (now_seg
) = text_section
;
9477 if (!SEG_NORMAL (now_seg
))
9480 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
9482 /* We can ignore sections that only contain debug info. */
9483 if ((flags
& SEC_ALLOC
) == 0)
9486 seginfo
= seg_info (now_seg
);
9487 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
9488 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
9492 arm_elf_section_type (const char * str
, size_t len
)
9494 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
9495 return SHT_ARM_EXIDX
;
9500 /* Code to deal with unwinding tables. */
9502 static void add_unwind_adjustsp (offsetT
);
9504 /* Cenerate and deferred unwind frame offset. */
9507 flush_pending_unwind (void)
9511 offset
= unwind
.pending_offset
;
9512 unwind
.pending_offset
= 0;
9514 add_unwind_adjustsp (offset
);
9517 /* Add an opcode to this list for this function. Two-byte opcodes should
9518 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9522 add_unwind_opcode (valueT op
, int length
)
9524 /* Add any deferred stack adjustment. */
9525 if (unwind
.pending_offset
)
9526 flush_pending_unwind ();
9528 unwind
.sp_restored
= 0;
9530 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
9532 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
9534 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
9535 unwind
.opcode_alloc
);
9537 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
9542 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
9544 unwind
.opcode_count
++;
9548 /* Add unwind opcodes to adjust the stack pointer. */
9551 add_unwind_adjustsp (offsetT offset
)
9557 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9562 /* Long form: 0xb2, uleb128. */
9563 /* This might not fit in a word so add the individual bytes,
9564 remembering the list is built in reverse order. */
9565 o
= (valueT
) ((offset
- 0x204) >> 2);
9567 add_unwind_opcode (0, 1);
9569 /* Calculate the uleb128 encoding of the offset. */
9573 bytes
[n
] = o
& 0x7f;
9581 add_unwind_opcode (bytes
[n
- 1], 1);
9582 add_unwind_opcode (0xb2, 1);
9584 else if (offset
> 0x100)
9586 /* Two short opcodes. */
9587 add_unwind_opcode (0x3f, 1);
9588 op
= (offset
- 0x104) >> 2;
9589 add_unwind_opcode (op
, 1);
9591 else if (offset
> 0)
9594 op
= (offset
- 4) >> 2;
9595 add_unwind_opcode (op
, 1);
9597 else if (offset
< 0)
9600 while (offset
> 0x100)
9602 add_unwind_opcode (0x7f, 1);
9605 op
= ((offset
- 4) >> 2) | 0x40;
9606 add_unwind_opcode (op
, 1);
9610 /* Finish the list of unwind opcodes for this function. */
9612 finish_unwind_opcodes (void)
9618 /* Adjust sp as neccessary. */
9619 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
9620 flush_pending_unwind ();
9622 /* After restoring sp from the frame pointer. */
9623 op
= 0x90 | unwind
.fp_reg
;
9624 add_unwind_opcode (op
, 1);
9627 flush_pending_unwind ();
9631 /* Start an exception table entry. If idx is nonzero this is an index table
9635 start_unwind_section (const segT text_seg
, int idx
)
9637 const char * text_name
;
9638 const char * prefix
;
9639 const char * prefix_once
;
9640 const char * group_name
;
9644 size_t sec_name_len
;
9651 prefix
= ELF_STRING_ARM_unwind
;
9652 prefix_once
= ELF_STRING_ARM_unwind_once
;
9653 type
= SHT_ARM_EXIDX
;
9657 prefix
= ELF_STRING_ARM_unwind_info
;
9658 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
9659 type
= SHT_PROGBITS
;
9662 text_name
= segment_name (text_seg
);
9663 if (streq (text_name
, ".text"))
9666 if (strncmp (text_name
, ".gnu.linkonce.t.",
9667 strlen (".gnu.linkonce.t.")) == 0)
9669 prefix
= prefix_once
;
9670 text_name
+= strlen (".gnu.linkonce.t.");
9673 prefix_len
= strlen (prefix
);
9674 text_len
= strlen (text_name
);
9675 sec_name_len
= prefix_len
+ text_len
;
9676 sec_name
= xmalloc (sec_name_len
+ 1);
9677 memcpy (sec_name
, prefix
, prefix_len
);
9678 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
9679 sec_name
[prefix_len
+ text_len
] = '\0';
9685 /* Handle COMDAT group. */
9686 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
9688 group_name
= elf_group_name (text_seg
);
9689 if (group_name
== NULL
)
9691 as_bad ("Group section `%s' has no group signature",
9692 segment_name (text_seg
));
9693 ignore_rest_of_line ();
9700 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
9702 /* Set the setion link for index tables. */
9704 elf_linked_to_section (now_seg
) = text_seg
;
9708 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9709 personality routine data. Returns zero, or the index table value for
9710 and inline entry. */
9713 create_unwind_entry (int have_data
)
9718 /* The current word of data. */
9720 /* The number of bytes left in this word. */
9723 finish_unwind_opcodes ();
9725 /* Remember the current text section. */
9726 unwind
.saved_seg
= now_seg
;
9727 unwind
.saved_subseg
= now_subseg
;
9729 start_unwind_section (now_seg
, 0);
9731 if (unwind
.personality_routine
== NULL
)
9733 if (unwind
.personality_index
== -2)
9736 as_bad (_("handerdata in cantunwind frame"));
9737 return 1; /* EXIDX_CANTUNWIND. */
9740 /* Use a default personality routine if none is specified. */
9741 if (unwind
.personality_index
== -1)
9743 if (unwind
.opcode_count
> 3)
9744 unwind
.personality_index
= 1;
9746 unwind
.personality_index
= 0;
9749 /* Space for the personality routine entry. */
9750 if (unwind
.personality_index
== 0)
9752 if (unwind
.opcode_count
> 3)
9753 as_bad (_("too many unwind opcodes for personality routine 0"));
9757 /* All the data is inline in the index table. */
9760 while (unwind
.opcode_count
> 0)
9762 unwind
.opcode_count
--;
9763 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
9767 /* Pad with "finish" opcodes. */
9769 data
= (data
<< 8) | 0xb0;
9776 /* We get two opcodes "free" in the first word. */
9777 size
= unwind
.opcode_count
- 2;
9780 /* An extra byte is required for the opcode count. */
9781 size
= unwind
.opcode_count
+ 1;
9783 size
= (size
+ 3) >> 2;
9785 as_bad (_("too many unwind opcodes"));
9787 frag_align (2, 0, 0);
9788 record_alignment (now_seg
, 2);
9789 unwind
.table_entry
= expr_build_dot ();
9791 /* Allocate the table entry. */
9792 ptr
= frag_more ((size
<< 2) + 4);
9793 where
= frag_now_fix () - ((size
<< 2) + 4);
9795 switch (unwind
.personality_index
)
9798 /* ??? Should this be a PLT generating relocation? */
9799 /* Custom personality routine. */
9800 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
9801 BFD_RELOC_ARM_PREL31
);
9806 /* Set the first byte to the number of additional words. */
9811 /* ABI defined personality routines. */
9813 /* Three opcodes bytes are packed into the first word. */
9820 /* The size and first two opcode bytes go in the first word. */
9821 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
9826 /* Should never happen. */
9830 /* Pack the opcodes into words (MSB first), reversing the list at the same
9832 while (unwind
.opcode_count
> 0)
9836 md_number_to_chars (ptr
, data
, 4);
9841 unwind
.opcode_count
--;
9843 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
9846 /* Finish off the last word. */
9849 /* Pad with "finish" opcodes. */
9851 data
= (data
<< 8) | 0xb0;
9853 md_number_to_chars (ptr
, data
, 4);
9858 /* Add an empty descriptor if there is no user-specified data. */
9859 ptr
= frag_more (4);
9860 md_number_to_chars (ptr
, 0, 4);
9866 /* Convert REGNAME to a DWARF-2 register number. */
9869 tc_arm_regname_to_dw2regnum (const char *regname
)
9871 int reg
= arm_reg_parse ((char **) ®name
, REG_TYPE_RN
);
9879 /* Initialize the DWARF-2 unwind information for this procedure. */
9882 tc_arm_frame_initial_instructions (void)
9884 cfi_add_CFA_def_cfa (REG_SP
, 0);
9886 #endif /* OBJ_ELF */
9889 /* MD interface: Symbol and relocation handling. */
9891 /* Return the address within the segment that a PC-relative fixup is
9892 relative to. For ARM, PC-relative fixups applied to instructions
9893 are generally relative to the location of the fixup plus 8 bytes.
9894 Thumb branches are offset by 4, and Thumb loads relative to PC
9895 require special handling. */
9898 md_pcrel_from_section (fixS
* fixP
, segT seg
)
9900 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9902 /* If this is pc-relative and we are going to emit a relocation
9903 then we just want to put out any pipeline compensation that the linker
9904 will need. Otherwise we want to use the calculated base. */
9906 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
9907 || arm_force_relocation (fixP
)))
9910 switch (fixP
->fx_r_type
)
9912 /* PC relative addressing on the Thumb is slightly odd as the
9913 bottom two bits of the PC are forced to zero for the
9914 calculation. This happens *after* application of the
9915 pipeline offset. However, Thumb adrl already adjusts for
9916 this, so we need not do it again. */
9917 case BFD_RELOC_ARM_THUMB_ADD
:
9920 case BFD_RELOC_ARM_THUMB_OFFSET
:
9921 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
9922 return (base
+ 4) & ~3;
9924 /* Thumb branches are simply offset by +4. */
9925 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
9926 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
9927 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
9928 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
9929 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
9930 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
9931 case BFD_RELOC_THUMB_PCREL_BLX
:
9934 /* ARM mode branches are offset by +8. However, the Windows CE
9935 loader expects the relocation not to take this into account. */
9936 case BFD_RELOC_ARM_PCREL_BRANCH
:
9937 case BFD_RELOC_ARM_PCREL_BLX
:
9938 case BFD_RELOC_ARM_PLT32
:
9945 /* ARM mode loads relative to PC are also offset by +8. Unlike
9946 branches, the Windows CE loader *does* expect the relocation
9947 to take this into account. */
9948 case BFD_RELOC_ARM_OFFSET_IMM
:
9949 case BFD_RELOC_ARM_OFFSET_IMM8
:
9950 case BFD_RELOC_ARM_HWLITERAL
:
9951 case BFD_RELOC_ARM_LITERAL
:
9952 case BFD_RELOC_ARM_CP_OFF_IMM
:
9956 /* Other PC-relative relocations are un-offset. */
9962 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
9963 Otherwise we have no need to default values of symbols. */
9966 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
9969 if (name
[0] == '_' && name
[1] == 'G'
9970 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
9974 if (symbol_find (name
))
9975 as_bad ("GOT already in the symbol table");
9977 GOT_symbol
= symbol_new (name
, undefined_section
,
9978 (valueT
) 0, & zero_address_frag
);
9988 /* Subroutine of md_apply_fix. Check to see if an immediate can be
9989 computed as two separate immediate values, added together. We
9990 already know that this value cannot be computed by just one ARM
9994 validate_immediate_twopart (unsigned int val
,
9995 unsigned int * highpart
)
10000 for (i
= 0; i
< 32; i
+= 2)
10001 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
10007 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
10009 else if (a
& 0xff0000)
10011 if (a
& 0xff000000)
10013 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
10017 assert (a
& 0xff000000);
10018 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
10021 return (a
& 0xff) | (i
<< 7);
10028 validate_offset_imm (unsigned int val
, int hwse
)
10030 if ((hwse
&& val
> 255) || val
> 4095)
10035 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10036 negative immediate constant by altering the instruction. A bit of
10041 by inverting the second operand, and
10044 by negating the second operand. */
10047 negate_data_op (unsigned long * instruction
,
10048 unsigned long value
)
10051 unsigned long negated
, inverted
;
10053 negated
= encode_arm_immediate (-value
);
10054 inverted
= encode_arm_immediate (~value
);
10056 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
10059 /* First negates. */
10060 case OPCODE_SUB
: /* ADD <-> SUB */
10061 new_inst
= OPCODE_ADD
;
10066 new_inst
= OPCODE_SUB
;
10070 case OPCODE_CMP
: /* CMP <-> CMN */
10071 new_inst
= OPCODE_CMN
;
10076 new_inst
= OPCODE_CMP
;
10080 /* Now Inverted ops. */
10081 case OPCODE_MOV
: /* MOV <-> MVN */
10082 new_inst
= OPCODE_MVN
;
10087 new_inst
= OPCODE_MOV
;
10091 case OPCODE_AND
: /* AND <-> BIC */
10092 new_inst
= OPCODE_BIC
;
10097 new_inst
= OPCODE_AND
;
10101 case OPCODE_ADC
: /* ADC <-> SBC */
10102 new_inst
= OPCODE_SBC
;
10107 new_inst
= OPCODE_ADC
;
10111 /* We cannot do anything. */
10116 if (value
== (unsigned) FAIL
)
10119 *instruction
&= OPCODE_MASK
;
10120 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
10125 md_apply_fix (fixS
* fixP
,
10129 offsetT value
= * valP
;
10131 unsigned int newimm
;
10132 unsigned long temp
;
10134 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10136 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
10138 /* Note whether this will delete the relocation. */
10139 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
10142 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10143 consistency with the behavior on 32-bit hosts. Remember value
10145 value
&= 0xffffffff;
10146 value
^= 0x80000000;
10147 value
-= 0x80000000;
10150 fixP
->fx_addnumber
= value
;
10152 /* Same treatment for fixP->fx_offset. */
10153 fixP
->fx_offset
&= 0xffffffff;
10154 fixP
->fx_offset
^= 0x80000000;
10155 fixP
->fx_offset
-= 0x80000000;
10157 switch (fixP
->fx_r_type
)
10159 case BFD_RELOC_NONE
:
10160 /* This will need to go in the object file. */
10164 case BFD_RELOC_ARM_IMMEDIATE
:
10165 /* We claim that this fixup has been processed here,
10166 even if in fact we generate an error because we do
10167 not have a reloc for it, so tc_gen_reloc will reject it. */
10171 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10174 _("undefined symbol %s used as an immediate value"),
10175 S_GET_NAME (fixP
->fx_addsy
));
10179 newimm
= encode_arm_immediate (value
);
10180 temp
= md_chars_to_number (buf
, INSN_SIZE
);
10182 /* If the instruction will fail, see if we can fix things up by
10183 changing the opcode. */
10184 if (newimm
== (unsigned int) FAIL
10185 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
10187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10188 _("invalid constant (%lx) after fixup"),
10189 (unsigned long) value
);
10193 newimm
|= (temp
& 0xfffff000);
10194 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
10197 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
10199 unsigned int highpart
= 0;
10200 unsigned int newinsn
= 0xe1a00000; /* nop. */
10202 newimm
= encode_arm_immediate (value
);
10203 temp
= md_chars_to_number (buf
, INSN_SIZE
);
10205 /* If the instruction will fail, see if we can fix things up by
10206 changing the opcode. */
10207 if (newimm
== (unsigned int) FAIL
10208 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
10210 /* No ? OK - try using two ADD instructions to generate
10212 newimm
= validate_immediate_twopart (value
, & highpart
);
10214 /* Yes - then make sure that the second instruction is
10216 if (newimm
!= (unsigned int) FAIL
)
10218 /* Still No ? Try using a negated value. */
10219 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
10220 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
10221 /* Otherwise - give up. */
10224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10225 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10230 /* Replace the first operand in the 2nd instruction (which
10231 is the PC) with the destination register. We have
10232 already added in the PC in the first instruction and we
10233 do not want to do it again. */
10234 newinsn
&= ~ 0xf0000;
10235 newinsn
|= ((newinsn
& 0x0f000) << 4);
10238 newimm
|= (temp
& 0xfffff000);
10239 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
10241 highpart
|= (newinsn
& 0xfffff000);
10242 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
10246 case BFD_RELOC_ARM_OFFSET_IMM
:
10247 case BFD_RELOC_ARM_LITERAL
:
10253 if (validate_offset_imm (value
, 0) == FAIL
)
10255 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
10256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10257 _("invalid literal constant: pool needs to be closer"));
10259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10260 _("bad immediate value for offset (%ld)"),
10265 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10266 newval
&= 0xff7ff000;
10267 newval
|= value
| (sign
? INDEX_UP
: 0);
10268 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10271 case BFD_RELOC_ARM_OFFSET_IMM8
:
10272 case BFD_RELOC_ARM_HWLITERAL
:
10278 if (validate_offset_imm (value
, 1) == FAIL
)
10280 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
10281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10282 _("invalid literal constant: pool needs to be closer"));
10284 as_bad (_("bad immediate value for half-word offset (%ld)"),
10289 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10290 newval
&= 0xff7ff0f0;
10291 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
10292 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10295 case BFD_RELOC_ARM_T32_OFFSET_U8
:
10296 if (value
< 0 || value
> 1020 || value
% 4 != 0)
10297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10298 _("bad immediate value for offset (%ld)"), (long) value
);
10301 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
10303 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
10306 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
10307 /* This is a complicated relocation used for all varieties of Thumb32
10308 load/store instruction with immediate offset:
10310 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10311 *4, optional writeback(W)
10312 (doubleword load/store)
10314 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10315 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10316 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10317 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10318 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10320 Uppercase letters indicate bits that are already encoded at
10321 this point. Lowercase letters are our problem. For the
10322 second block of instructions, the secondary opcode nybble
10323 (bits 8..11) is present, and bit 23 is zero, even if this is
10324 a PC-relative operation. */
10325 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10327 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
10329 if ((newval
& 0xf0000000) == 0xe0000000)
10331 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10333 newval
|= (1 << 23);
10336 if (value
% 4 != 0)
10338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10339 _("offset not a multiple of 4"));
10345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10346 _("offset out of range"));
10351 else if ((newval
& 0x000f0000) == 0x000f0000)
10353 /* PC-relative, 12-bit offset. */
10355 newval
|= (1 << 23);
10358 if (value
>= 0xfff)
10360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10361 _("offset out of range"));
10366 else if ((newval
& 0x00000100) == 0x00000100)
10368 /* Writeback: 8-bit, +/- offset. */
10370 newval
|= (1 << 9);
10375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10376 _("offset out of range"));
10381 else if ((newval
& 0x00000f00) == 0x00000e00)
10383 /* T-instruction: positive 8-bit offset. */
10384 if (value
< 0 || value
>= 0xff)
10386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10387 _("offset out of range"));
10395 /* Positive 12-bit or negative 8-bit offset. */
10399 newval
|= (1 << 23);
10409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10410 _("offset out of range"));
10417 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
10418 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
10421 case BFD_RELOC_ARM_SHIFT_IMM
:
10422 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10423 if (((unsigned long) value
) > 32
10425 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
10427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10428 _("shift expression is too large"));
10433 /* Shifts of zero must be done as lsl. */
10435 else if (value
== 32)
10437 newval
&= 0xfffff07f;
10438 newval
|= (value
& 0x1f) << 7;
10439 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10442 case BFD_RELOC_ARM_T32_IMMEDIATE
:
10443 /* We claim that this fixup has been processed here,
10444 even if in fact we generate an error because we do
10445 not have a reloc for it, so tc_gen_reloc will reject it. */
10449 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10452 _("undefined symbol %s used as an immediate value"),
10453 S_GET_NAME (fixP
->fx_addsy
));
10457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10459 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
10461 newimm
= encode_thumb32_immediate (value
);
10463 /* FUTURE: Implement analogue of negate_data_op for T32. */
10464 if (newimm
== (unsigned int)FAIL
)
10466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10467 _("invalid constant (%lx) after fixup"),
10468 (unsigned long) value
);
10472 newval
|= (newimm
& 0x800) << 15;
10473 newval
|= (newimm
& 0x700) << 4;
10474 newval
|= (newimm
& 0x0ff);
10476 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
10477 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
10480 case BFD_RELOC_ARM_SMI
:
10481 if (((unsigned long) value
) > 0xffff)
10482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10483 _("invalid smi expression"));
10484 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10485 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
10486 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10489 case BFD_RELOC_ARM_SWI
:
10490 if (fixP
->tc_fix_data
!= 0)
10492 if (((unsigned long) value
) > 0xff)
10493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10494 _("invalid swi expression"));
10495 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10497 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10501 if (((unsigned long) value
) > 0x00ffffff)
10502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10503 _("invalid swi expression"));
10504 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10506 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10510 case BFD_RELOC_ARM_MULTI
:
10511 if (((unsigned long) value
) > 0xffff)
10512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10513 _("invalid expression in load/store multiple"));
10514 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
10515 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10518 case BFD_RELOC_ARM_PCREL_BRANCH
:
10520 case BFD_RELOC_ARM_PLT32
:
10523 /* We are going to store value (shifted right by two) in the
10524 instruction, in a 24 bit, signed field. Bits 0 and 1 must be
10525 clear, and bits 26 through 32 either all clear or all set. */
10526 if (value
& 0x00000003)
10527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10528 _("misaligned branch destination"));
10529 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
10530 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
10531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10532 _("branch out of range"));
10534 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10536 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10537 newval
|= (value
>> 2) & 0x00ffffff;
10538 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10542 case BFD_RELOC_ARM_PCREL_BLX
:
10543 /* BLX allows bit 1 to be set in the branch destination, since
10544 it targets a Thumb instruction which is only required to be
10545 aligned modulo 2. Other constraints are as for B/BL. */
10546 if (value
& 0x00000001)
10547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10548 _("misaligned BLX destination"));
10549 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
10550 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
10551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10552 _("branch out of range"));
10554 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10557 hbit
= (value
>> 1) & 1;
10558 value
= (value
>> 2) & 0x00ffffff;
10560 newval
= md_chars_to_number (buf
, INSN_SIZE
);
10561 newval
|= value
| hbit
<< 24;
10562 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10566 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
10567 /* CZB can only branch forward. */
10569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10570 _("branch out of range"));
10572 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10574 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10575 newval
|= ((value
& 0x2e) << 2) | ((value
& 0x40) << 3);
10576 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10580 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
10581 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
10582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10583 _("branch out of range"));
10585 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10587 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10588 newval
|= (value
& 0x1ff) >> 1;
10589 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10593 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
10594 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
10595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10596 _("branch out of range"));
10598 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10600 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10601 newval
|= (value
& 0xfff) >> 1;
10602 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10606 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
10607 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
10608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10609 _("conditional branch out of range"));
10611 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10614 addressT S
, J1
, J2
, lo
, hi
;
10616 S
= (value
& 0x00100000) >> 20;
10617 J2
= (value
& 0x00080000) >> 19;
10618 J1
= (value
& 0x00040000) >> 18;
10619 hi
= (value
& 0x0003f000) >> 12;
10620 lo
= (value
& 0x00000ffe) >> 1;
10622 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10623 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10624 newval
|= (S
<< 10) | hi
;
10625 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
10626 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10627 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10631 case BFD_RELOC_THUMB_PCREL_BLX
:
10632 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
10633 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
10634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10635 _("branch out of range"));
10637 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
10638 /* For a BLX instruction, make sure that the relocation is rounded up
10639 to a word boundary. This follows the semantics of the instruction
10640 which specifies that bit 1 of the target address will come from bit
10641 1 of the base address. */
10642 value
= (value
+ 1) & ~ 1;
10644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10648 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10649 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10650 newval
|= (value
& 0x7fffff) >> 12;
10651 newval2
|= (value
& 0xfff) >> 1;
10652 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10653 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10657 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
10658 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
10659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10660 _("branch out of range"));
10662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10665 addressT S
, I1
, I2
, lo
, hi
;
10667 S
= (value
& 0x01000000) >> 24;
10668 I1
= (value
& 0x00800000) >> 23;
10669 I2
= (value
& 0x00400000) >> 22;
10670 hi
= (value
& 0x003ff000) >> 12;
10671 lo
= (value
& 0x00000ffe) >> 1;
10676 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10677 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
10678 newval
|= (S
<< 10) | hi
;
10679 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
10680 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10681 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
10686 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10687 md_number_to_chars (buf
, value
, 1);
10691 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10692 md_number_to_chars (buf
, value
, 2);
10696 case BFD_RELOC_ARM_TLS_GD32
:
10697 case BFD_RELOC_ARM_TLS_LE32
:
10698 case BFD_RELOC_ARM_TLS_IE32
:
10699 case BFD_RELOC_ARM_TLS_LDM32
:
10700 case BFD_RELOC_ARM_TLS_LDO32
:
10701 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10704 case BFD_RELOC_ARM_GOT32
:
10705 case BFD_RELOC_ARM_GOTOFF
:
10706 case BFD_RELOC_ARM_TARGET2
:
10707 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10708 md_number_to_chars (buf
, 0, 4);
10712 case BFD_RELOC_RVA
:
10714 case BFD_RELOC_ARM_TARGET1
:
10715 case BFD_RELOC_ARM_ROSEGREL32
:
10716 case BFD_RELOC_ARM_SBREL32
:
10717 case BFD_RELOC_32_PCREL
:
10718 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10719 md_number_to_chars (buf
, value
, 4);
10723 case BFD_RELOC_ARM_PREL31
:
10724 if (fixP
->fx_done
|| !seg
->use_rela_p
)
10726 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
10727 if ((value
^ (value
>> 1)) & 0x40000000)
10729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10730 _("rel31 relocation overflow"));
10732 newval
|= value
& 0x7fffffff;
10733 md_number_to_chars (buf
, newval
, 4);
10738 case BFD_RELOC_ARM_CP_OFF_IMM
:
10739 if (value
< -1023 || value
> 1023 || (value
& 3))
10740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10741 _("co-processor offset out of range"));
10746 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
10747 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
10749 newval
&= ~WRITE_BACK
;
10750 md_number_to_chars (buf
, newval
, INSN_SIZE
);
10753 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
10754 if (value
< -255 || value
> 255)
10755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10756 _("co-processor offset out of range"));
10757 goto cp_off_common
;
10759 case BFD_RELOC_ARM_THUMB_OFFSET
:
10760 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10761 /* Exactly what ranges, and where the offset is inserted depends
10762 on the type of instruction, we can establish this from the
10764 switch (newval
>> 12)
10766 case 4: /* PC load. */
10767 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
10768 forced to zero for these loads; md_pcrel_from has already
10769 compensated for this. */
10771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10772 _("invalid offset, target not word aligned (0x%08lX)"),
10773 (((unsigned int) fixP
->fx_frag
->fr_address
10774 + (unsigned int) fixP
->fx_where
) & ~3) + value
);
10776 if (value
& ~0x3fc)
10777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10778 _("invalid offset, value too big (0x%08lX)"),
10781 newval
|= value
>> 2;
10784 case 9: /* SP load/store. */
10785 if (value
& ~0x3fc)
10786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10787 _("invalid offset, value too big (0x%08lX)"),
10789 newval
|= value
>> 2;
10792 case 6: /* Word load/store. */
10794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10795 _("invalid offset, value too big (0x%08lX)"),
10797 newval
|= value
<< 4; /* 6 - 2. */
10800 case 7: /* Byte load/store. */
10802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10803 _("invalid offset, value too big (0x%08lX)"),
10805 newval
|= value
<< 6;
10808 case 8: /* Halfword load/store. */
10810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10811 _("invalid offset, value too big (0x%08lX)"),
10813 newval
|= value
<< 5; /* 6 - 1. */
10817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10818 "Unable to process relocation for thumb opcode: %lx",
10819 (unsigned long) newval
);
10822 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10825 case BFD_RELOC_ARM_THUMB_ADD
:
10826 /* This is a complicated relocation, since we use it for all of
10827 the following immediate relocations:
10831 9bit ADD/SUB SP word-aligned
10832 10bit ADD PC/SP word-aligned
10834 The type of instruction being processed is encoded in the
10841 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10843 int rd
= (newval
>> 4) & 0xf;
10844 int rs
= newval
& 0xf;
10845 int subtract
= !!(newval
& 0x8000);
10847 /* Check for HI regs, only very restricted cases allowed:
10848 Adjusting SP, and using PC or SP to get an address. */
10849 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
10850 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
10851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10852 _("invalid Hi register with immediate"));
10854 /* If value is negative, choose the opposite instruction. */
10858 subtract
= !subtract
;
10860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10861 _("immediate value out of range"));
10866 if (value
& ~0x1fc)
10867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10868 _("invalid immediate for stack address calculation"));
10869 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
10870 newval
|= value
>> 2;
10872 else if (rs
== REG_PC
|| rs
== REG_SP
)
10874 if (subtract
|| value
& ~0x3fc)
10875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10876 _("invalid immediate for address calculation (value = 0x%08lX)"),
10877 (unsigned long) value
);
10878 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
10880 newval
|= value
>> 2;
10885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10886 _("immediate value out of range"));
10887 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
10888 newval
|= (rd
<< 8) | value
;
10893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10894 _("immediate value out of range"));
10895 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
10896 newval
|= rd
| (rs
<< 3) | (value
<< 6);
10899 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10902 case BFD_RELOC_ARM_THUMB_IMM
:
10903 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
10904 if (value
< 0 || value
> 255)
10905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10906 _("invalid immediate: %ld is too large"),
10909 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10912 case BFD_RELOC_ARM_THUMB_SHIFT
:
10913 /* 5bit shift value (0..32). LSL cannot take 32. */
10914 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
10915 temp
= newval
& 0xf800;
10916 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
10917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10918 _("invalid shift value: %ld"), (long) value
);
10919 /* Shifts of zero must be encoded as LSL. */
10921 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
10922 /* Shifts of 32 are encoded as zero. */
10923 else if (value
== 32)
10925 newval
|= value
<< 6;
10926 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
10929 case BFD_RELOC_VTABLE_INHERIT
:
10930 case BFD_RELOC_VTABLE_ENTRY
:
10934 case BFD_RELOC_UNUSED
:
10936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10937 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
10941 /* Translate internal representation of relocation info to BFD target
10945 tc_gen_reloc (asection
* section ATTRIBUTE_UNUSED
,
10949 bfd_reloc_code_real_type code
;
10951 reloc
= xmalloc (sizeof (arelent
));
10953 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
10954 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10955 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10957 if (fixp
->fx_pcrel
)
10958 fixp
->fx_offset
= reloc
->address
;
10959 reloc
->addend
= fixp
->fx_offset
;
10961 switch (fixp
->fx_r_type
)
10964 if (fixp
->fx_pcrel
)
10966 code
= BFD_RELOC_8_PCREL
;
10971 if (fixp
->fx_pcrel
)
10973 code
= BFD_RELOC_16_PCREL
;
10978 if (fixp
->fx_pcrel
)
10980 code
= BFD_RELOC_32_PCREL
;
10984 case BFD_RELOC_NONE
:
10985 case BFD_RELOC_ARM_PCREL_BRANCH
:
10986 case BFD_RELOC_ARM_PCREL_BLX
:
10987 case BFD_RELOC_RVA
:
10988 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
10989 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
10990 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
10991 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
10992 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
10993 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
10994 case BFD_RELOC_THUMB_PCREL_BLX
:
10995 case BFD_RELOC_VTABLE_ENTRY
:
10996 case BFD_RELOC_VTABLE_INHERIT
:
10997 code
= fixp
->fx_r_type
;
11000 case BFD_RELOC_ARM_LITERAL
:
11001 case BFD_RELOC_ARM_HWLITERAL
:
11002 /* If this is called then the a literal has
11003 been referenced across a section boundary. */
11004 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11005 _("literal referenced across section boundary"));
11009 case BFD_RELOC_ARM_GOT32
:
11010 case BFD_RELOC_ARM_GOTOFF
:
11011 case BFD_RELOC_ARM_PLT32
:
11012 case BFD_RELOC_ARM_TARGET1
:
11013 case BFD_RELOC_ARM_ROSEGREL32
:
11014 case BFD_RELOC_ARM_SBREL32
:
11015 case BFD_RELOC_ARM_PREL31
:
11016 case BFD_RELOC_ARM_TARGET2
:
11017 case BFD_RELOC_ARM_TLS_LE32
:
11018 case BFD_RELOC_ARM_TLS_LDO32
:
11019 code
= fixp
->fx_r_type
;
11022 case BFD_RELOC_ARM_TLS_GD32
:
11023 case BFD_RELOC_ARM_TLS_IE32
:
11024 case BFD_RELOC_ARM_TLS_LDM32
:
11025 /* BFD will include the symbol's address in the addend.
11026 But we don't want that, so subtract it out again here. */
11027 if (!S_IS_COMMON (fixp
->fx_addsy
))
11028 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
11029 code
= fixp
->fx_r_type
;
11033 case BFD_RELOC_ARM_IMMEDIATE
:
11034 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11035 _("internal relocation (type: IMMEDIATE) not fixed up"));
11038 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
11039 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11040 _("ADRL used for a symbol not defined in the same file"));
11043 case BFD_RELOC_ARM_OFFSET_IMM
:
11044 if (fixp
->fx_addsy
!= NULL
11045 && !S_IS_DEFINED (fixp
->fx_addsy
)
11046 && S_IS_LOCAL (fixp
->fx_addsy
))
11048 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11049 _("undefined local label `%s'"),
11050 S_GET_NAME (fixp
->fx_addsy
));
11054 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11055 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11062 switch (fixp
->fx_r_type
)
11064 case BFD_RELOC_NONE
: type
= "NONE"; break;
11065 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
11066 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
11067 case BFD_RELOC_ARM_SMI
: type
= "SMI"; break;
11068 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
11069 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
11070 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
11071 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
11072 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
11073 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
11074 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
11075 default: type
= _("<unknown>"); break;
11077 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11078 _("cannot represent %s relocation in this object file format"),
11085 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
11087 && fixp
->fx_addsy
== GOT_symbol
)
11089 code
= BFD_RELOC_ARM_GOTPC
;
11090 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
11094 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11096 if (reloc
->howto
== NULL
)
11098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11099 _("cannot represent %s relocation in this object file format"),
11100 bfd_get_reloc_code_name (code
));
11104 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11105 vtable entry to be used in the relocation's section offset. */
11106 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11107 reloc
->address
= fixp
->fx_offset
;
11112 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11115 cons_fix_new_arm (fragS
* frag
,
11120 bfd_reloc_code_real_type type
;
11124 FIXME: @@ Should look at CPU word size. */
11128 type
= BFD_RELOC_8
;
11131 type
= BFD_RELOC_16
;
11135 type
= BFD_RELOC_32
;
11138 type
= BFD_RELOC_64
;
11142 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
11145 #if defined OBJ_COFF || defined OBJ_ELF
11147 arm_validate_fix (fixS
* fixP
)
11149 /* If the destination of the branch is a defined symbol which does not have
11150 the THUMB_FUNC attribute, then we must be calling a function which has
11151 the (interfacearm) attribute. We look for the Thumb entry point to that
11152 function and change the branch to refer to that function instead. */
11153 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
11154 && fixP
->fx_addsy
!= NULL
11155 && S_IS_DEFINED (fixP
->fx_addsy
)
11156 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
11158 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
11164 arm_force_relocation (struct fix
* fixp
)
11166 #if defined (OBJ_COFF) && defined (TE_PE)
11167 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
11171 /* Resolve these relocations even if the symbol is extern or weak. */
11172 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
11173 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
11174 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
11177 return generic_force_reloc (fixp
);
11181 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11182 local labels from being added to the output symbol table when they
11183 are used with the ADRL pseudo op. The ADRL relocation should always
11184 be resolved before the binbary is emitted, so it is safe to say that
11185 it is adjustable. */
11188 arm_fix_adjustable (fixS
* fixP
)
11190 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
11197 /* Relocations against Thumb function names must be left unadjusted,
11198 so that the linker can use this information to correctly set the
11199 bottom bit of their addresses. The MIPS version of this function
11200 also prevents relocations that are mips-16 specific, but I do not
11201 know why it does this.
11204 There is one other problem that ought to be addressed here, but
11205 which currently is not: Taking the address of a label (rather
11206 than a function) and then later jumping to that address. Such
11207 addresses also ought to have their bottom bit set (assuming that
11208 they reside in Thumb code), but at the moment they will not. */
11211 arm_fix_adjustable (fixS
* fixP
)
11213 if (fixP
->fx_addsy
== NULL
)
11216 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
11217 && fixP
->fx_subsy
== NULL
)
11220 /* We need the symbol name for the VTABLE entries. */
11221 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11222 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11225 /* Don't allow symbols to be discarded on GOT related relocs. */
11226 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
11227 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
11228 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
11229 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
11230 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
11231 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
11232 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
11233 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
11234 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
11241 elf32_arm_target_format (void)
11244 return (target_big_endian
11245 ? "elf32-bigarm-symbian"
11246 : "elf32-littlearm-symbian");
11247 #elif defined (TE_VXWORKS)
11248 return (target_big_endian
11249 ? "elf32-bigarm-vxworks"
11250 : "elf32-littlearm-vxworks");
11252 if (target_big_endian
)
11253 return "elf32-bigarm";
11255 return "elf32-littlearm";
11260 armelf_frob_symbol (symbolS
* symp
,
11263 elf_frob_symbol (symp
, puntp
);
11267 /* MD interface: Finalization. */
11269 /* A good place to do this, although this was probably not intended
11270 for this kind of use. We need to dump the literal pool before
11271 references are made to a null symbol pointer. */
11276 literal_pool
* pool
;
11278 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
11280 /* Put it at the end of the relevent section. */
11281 subseg_set (pool
->section
, pool
->sub_section
);
11283 arm_elf_change_section ();
11289 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11293 arm_adjust_symtab (void)
11298 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
11300 if (ARM_IS_THUMB (sym
))
11302 if (THUMB_IS_FUNC (sym
))
11304 /* Mark the symbol as a Thumb function. */
11305 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
11306 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
11307 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
11309 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
11310 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
11312 as_bad (_("%s: unexpected function type: %d"),
11313 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
11315 else switch (S_GET_STORAGE_CLASS (sym
))
11318 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
11321 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
11324 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
11332 if (ARM_IS_INTERWORK (sym
))
11333 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
11340 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
11342 if (ARM_IS_THUMB (sym
))
11344 elf_symbol_type
* elf_sym
;
11346 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
11347 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
11349 if (! bfd_is_arm_mapping_symbol_name (elf_sym
->symbol
.name
))
11351 /* If it's a .thumb_func, declare it as so,
11352 otherwise tag label as .code 16. */
11353 if (THUMB_IS_FUNC (sym
))
11354 elf_sym
->internal_elf_sym
.st_info
=
11355 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
11357 elf_sym
->internal_elf_sym
.st_info
=
11358 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
11365 /* MD interface: Initialization. */
11368 set_constant_flonums (void)
11372 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
11373 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
11383 if ( (arm_ops_hsh
= hash_new ()) == NULL
11384 || (arm_cond_hsh
= hash_new ()) == NULL
11385 || (arm_shift_hsh
= hash_new ()) == NULL
11386 || (arm_psr_hsh
= hash_new ()) == NULL
11387 || (arm_reg_hsh
= hash_new ()) == NULL
11388 || (arm_reloc_hsh
= hash_new ()) == NULL
)
11389 as_fatal (_("virtual memory exhausted"));
11391 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
11392 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
11393 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
11394 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
11395 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
11396 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
11397 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
11398 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
11399 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
11400 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
11402 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
11403 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
11406 set_constant_flonums ();
11408 /* Set the cpu variant based on the command-line options. We prefer
11409 -mcpu= over -march= if both are set (as for GCC); and we prefer
11410 -mfpu= over any other way of setting the floating point unit.
11411 Use of legacy options with new options are faulted. */
11412 if (legacy_cpu
!= -1)
11414 if (mcpu_cpu_opt
!= -1 || march_cpu_opt
!= -1)
11415 as_bad (_("use of old and new-style options to set CPU type"));
11417 mcpu_cpu_opt
= legacy_cpu
;
11419 else if (mcpu_cpu_opt
== -1)
11420 mcpu_cpu_opt
= march_cpu_opt
;
11422 if (legacy_fpu
!= -1)
11424 if (mfpu_opt
!= -1)
11425 as_bad (_("use of old and new-style options to set FPU type"));
11427 mfpu_opt
= legacy_fpu
;
11429 else if (mfpu_opt
== -1)
11431 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11432 /* Some environments specify a default FPU. If they don't, infer it
11433 from the processor. */
11434 if (mcpu_fpu_opt
!= -1)
11435 mfpu_opt
= mcpu_fpu_opt
;
11437 mfpu_opt
= march_fpu_opt
;
11439 mfpu_opt
= FPU_DEFAULT
;
11443 if (mfpu_opt
== -1)
11445 if (mcpu_cpu_opt
== -1)
11446 mfpu_opt
= FPU_DEFAULT
;
11447 else if (mcpu_cpu_opt
& ARM_EXT_V5
)
11448 mfpu_opt
= FPU_ARCH_VFP_V2
;
11450 mfpu_opt
= FPU_ARCH_FPA
;
11453 if (mcpu_cpu_opt
== -1)
11454 mcpu_cpu_opt
= CPU_DEFAULT
;
11456 cpu_variant
= mcpu_cpu_opt
| mfpu_opt
;
11458 #if defined OBJ_COFF || defined OBJ_ELF
11460 unsigned int flags
= 0;
11462 #if defined OBJ_ELF
11463 flags
= meabi_flags
;
11465 switch (meabi_flags
)
11467 case EF_ARM_EABI_UNKNOWN
:
11469 /* Set the flags in the private structure. */
11470 if (uses_apcs_26
) flags
|= F_APCS26
;
11471 if (support_interwork
) flags
|= F_INTERWORK
;
11472 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
11473 if (pic_code
) flags
|= F_PIC
;
11474 if ((cpu_variant
& FPU_ANY
) == FPU_NONE
11475 || (cpu_variant
& FPU_ANY
) == FPU_ARCH_VFP
) /* VFP layout only. */
11476 flags
|= F_SOFT_FLOAT
;
11478 switch (mfloat_abi_opt
)
11480 case ARM_FLOAT_ABI_SOFT
:
11481 case ARM_FLOAT_ABI_SOFTFP
:
11482 flags
|= F_SOFT_FLOAT
;
11485 case ARM_FLOAT_ABI_HARD
:
11486 if (flags
& F_SOFT_FLOAT
)
11487 as_bad (_("hard-float conflicts with specified fpu"));
11491 /* Using VFP conventions (even if soft-float). */
11492 if (cpu_variant
& FPU_VFP_EXT_NONE
)
11493 flags
|= F_VFP_FLOAT
;
11495 #if defined OBJ_ELF
11496 if (cpu_variant
& FPU_ARCH_MAVERICK
)
11497 flags
|= EF_ARM_MAVERICK_FLOAT
;
11500 case EF_ARM_EABI_VER4
:
11501 /* No additional flags to set. */
11508 bfd_set_private_flags (stdoutput
, flags
);
11510 /* We have run out flags in the COFF header to encode the
11511 status of ATPCS support, so instead we create a dummy,
11512 empty, debug section called .arm.atpcs. */
11517 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
11521 bfd_set_section_flags
11522 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
11523 bfd_set_section_size (stdoutput
, sec
, 0);
11524 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
11530 /* Record the CPU type as well. */
11531 switch (cpu_variant
& ARM_CPU_MASK
)
11534 mach
= bfd_mach_arm_2
;
11537 case ARM_3
: /* Also ARM_250. */
11538 mach
= bfd_mach_arm_2a
;
11541 case ARM_6
: /* Also ARM_7. */
11542 mach
= bfd_mach_arm_3
;
11546 mach
= bfd_mach_arm_unknown
;
11550 /* Catch special cases. */
11551 if (cpu_variant
& ARM_CEXT_IWMMXT
)
11552 mach
= bfd_mach_arm_iWMMXt
;
11553 else if (cpu_variant
& ARM_CEXT_XSCALE
)
11554 mach
= bfd_mach_arm_XScale
;
11555 else if (cpu_variant
& ARM_CEXT_MAVERICK
)
11556 mach
= bfd_mach_arm_ep9312
;
11557 else if (cpu_variant
& ARM_EXT_V5E
)
11558 mach
= bfd_mach_arm_5TE
;
11559 else if (cpu_variant
& ARM_EXT_V5
)
11561 if (cpu_variant
& ARM_EXT_V4T
)
11562 mach
= bfd_mach_arm_5T
;
11564 mach
= bfd_mach_arm_5
;
11566 else if (cpu_variant
& ARM_EXT_V4
)
11568 if (cpu_variant
& ARM_EXT_V4T
)
11569 mach
= bfd_mach_arm_4T
;
11571 mach
= bfd_mach_arm_4
;
11573 else if (cpu_variant
& ARM_EXT_V3M
)
11574 mach
= bfd_mach_arm_3M
;
11576 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
11579 /* Command line processing. */
11582 Invocation line includes a switch not recognized by the base assembler.
11583 See if it's a processor-specific option.
11585 This routine is somewhat complicated by the need for backwards
11586 compatibility (since older releases of gcc can't be changed).
11587 The new options try to make the interface as compatible as
11590 New options (supported) are:
11592 -mcpu=<cpu name> Assemble for selected processor
11593 -march=<architecture name> Assemble for selected architecture
11594 -mfpu=<fpu architecture> Assemble for selected FPU.
11595 -EB/-mbig-endian Big-endian
11596 -EL/-mlittle-endian Little-endian
11597 -k Generate PIC code
11598 -mthumb Start in Thumb mode
11599 -mthumb-interwork Code supports ARM/Thumb interworking
11601 For now we will also provide support for:
11603 -mapcs-32 32-bit Program counter
11604 -mapcs-26 26-bit Program counter
11605 -macps-float Floats passed in FP registers
11606 -mapcs-reentrant Reentrant code
11608 (sometime these will probably be replaced with -mapcs=<list of options>
11609 and -matpcs=<list of options>)
11611 The remaining options are only supported for back-wards compatibility.
11612 Cpu variants, the arm part is optional:
11613 -m[arm]1 Currently not supported.
11614 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11615 -m[arm]3 Arm 3 processor
11616 -m[arm]6[xx], Arm 6 processors
11617 -m[arm]7[xx][t][[d]m] Arm 7 processors
11618 -m[arm]8[10] Arm 8 processors
11619 -m[arm]9[20][tdmi] Arm 9 processors
11620 -mstrongarm[110[0]] StrongARM processors
11621 -mxscale XScale processors
11622 -m[arm]v[2345[t[e]]] Arm architectures
11623 -mall All (except the ARM1)
11625 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11626 -mfpe-old (No float load/store multiples)
11627 -mvfpxd VFP Single precision
11629 -mno-fpu Disable all floating point instructions
11631 The following CPU names are recognized:
11632 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11633 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11634 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11635 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11636 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11637 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11638 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11642 const char * md_shortopts
= "m:k";
11644 #ifdef ARM_BI_ENDIAN
11645 #define OPTION_EB (OPTION_MD_BASE + 0)
11646 #define OPTION_EL (OPTION_MD_BASE + 1)
11648 #if TARGET_BYTES_BIG_ENDIAN
11649 #define OPTION_EB (OPTION_MD_BASE + 0)
11651 #define OPTION_EL (OPTION_MD_BASE + 1)
11655 struct option md_longopts
[] =
11658 {"EB", no_argument
, NULL
, OPTION_EB
},
11661 {"EL", no_argument
, NULL
, OPTION_EL
},
11663 {NULL
, no_argument
, NULL
, 0}
11666 size_t md_longopts_size
= sizeof (md_longopts
);
11668 struct arm_option_table
11670 char *option
; /* Option name to match. */
11671 char *help
; /* Help information. */
11672 int *var
; /* Variable to change. */
11673 int value
; /* What to change it to. */
11674 char *deprecated
; /* If non-null, print this message. */
11677 struct arm_option_table arm_opts
[] =
11679 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
11680 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
11681 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11682 &support_interwork
, 1, NULL
},
11683 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
11684 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
11685 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
11687 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
11688 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
11689 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
11690 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
11693 /* These are recognized by the assembler, but have no affect on code. */
11694 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
11695 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
11697 /* DON'T add any new processors to this list -- we want the whole list
11698 to go away... Add them to the processors table instead. */
11699 {"marm1", NULL
, &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
11700 {"m1", NULL
, &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
11701 {"marm2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
11702 {"m2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
11703 {"marm250", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
11704 {"m250", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
11705 {"marm3", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
11706 {"m3", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
11707 {"marm6", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
11708 {"m6", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
11709 {"marm600", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
11710 {"m600", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
11711 {"marm610", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
11712 {"m610", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
11713 {"marm620", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
11714 {"m620", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
11715 {"marm7", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
11716 {"m7", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
11717 {"marm70", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
11718 {"m70", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
11719 {"marm700", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
11720 {"m700", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
11721 {"marm700i", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
11722 {"m700i", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
11723 {"marm710", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
11724 {"m710", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
11725 {"marm710c", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
11726 {"m710c", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
11727 {"marm720", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
11728 {"m720", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
11729 {"marm7d", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
11730 {"m7d", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
11731 {"marm7di", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
11732 {"m7di", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
11733 {"marm7m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
11734 {"m7m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
11735 {"marm7dm", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
11736 {"m7dm", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
11737 {"marm7dmi", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
11738 {"m7dmi", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
11739 {"marm7100", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
11740 {"m7100", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
11741 {"marm7500", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
11742 {"m7500", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
11743 {"marm7500fe", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
11744 {"m7500fe", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
11745 {"marm7t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11746 {"m7t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11747 {"marm7tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11748 {"m7tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
11749 {"marm710t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
11750 {"m710t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
11751 {"marm720t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
11752 {"m720t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
11753 {"marm740t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
11754 {"m740t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
11755 {"marm8", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
11756 {"m8", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
11757 {"marm810", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
11758 {"m810", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
11759 {"marm9", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
11760 {"m9", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
11761 {"marm9tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
11762 {"m9tdmi", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
11763 {"marm920", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
11764 {"m920", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
11765 {"marm940", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
11766 {"m940", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
11767 {"mstrongarm", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
11768 {"mstrongarm110", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11769 N_("use -mcpu=strongarm110")},
11770 {"mstrongarm1100", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11771 N_("use -mcpu=strongarm1100")},
11772 {"mstrongarm1110", NULL
, &legacy_cpu
, ARM_ARCH_V4
,
11773 N_("use -mcpu=strongarm1110")},
11774 {"mxscale", NULL
, &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
11775 {"miwmmxt", NULL
, &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
11776 {"mall", NULL
, &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
11778 /* Architecture variants -- don't add any more to this list either. */
11779 {"mv2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
11780 {"marmv2", NULL
, &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
11781 {"mv2a", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
11782 {"marmv2a", NULL
, &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
11783 {"mv3", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
11784 {"marmv3", NULL
, &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
11785 {"mv3m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
11786 {"marmv3m", NULL
, &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
11787 {"mv4", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
11788 {"marmv4", NULL
, &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
11789 {"mv4t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
11790 {"marmv4t", NULL
, &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
11791 {"mv5", NULL
, &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
11792 {"marmv5", NULL
, &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
11793 {"mv5t", NULL
, &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
11794 {"marmv5t", NULL
, &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
11795 {"mv5e", NULL
, &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
11796 {"marmv5e", NULL
, &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
11798 /* Floating point variants -- don't add any more to this list either. */
11799 {"mfpe-old", NULL
, &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
11800 {"mfpa10", NULL
, &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
11801 {"mfpa11", NULL
, &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
11802 {"mno-fpu", NULL
, &legacy_fpu
, 0,
11803 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
11805 {NULL
, NULL
, NULL
, 0, NULL
}
11808 struct arm_cpu_option_table
11812 /* For some CPUs we assume an FPU unless the user explicitly sets
11817 /* This list should, at a minimum, contain all the cpu names
11818 recognized by GCC. */
11819 static struct arm_cpu_option_table arm_cpus
[] =
11821 {"all", ARM_ANY
, FPU_ARCH_FPA
},
11822 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
11823 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
11824 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
11825 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
11826 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11827 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11828 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11829 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11830 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11831 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11832 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
11833 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11834 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
11835 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11836 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
11837 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11838 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11839 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11840 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11841 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11842 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11843 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11844 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11845 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11846 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11847 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11848 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11849 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11850 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11851 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11852 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11853 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11854 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11855 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11856 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11857 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11858 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11859 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11860 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11861 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11862 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11863 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11864 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11865 /* For V5 or later processors we default to using VFP; but the user
11866 should really set the FPU type explicitly. */
11867 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
11868 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11869 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
11870 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
11871 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
11872 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
11873 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11874 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
},
11875 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11876 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
},
11877 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11878 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11879 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
},
11880 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
},
11881 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
11882 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
},
11883 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
},
11884 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
},
11885 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
},
11886 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
},
11887 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
},
11888 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
},
11889 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
},
11890 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
},
11891 /* ??? XSCALE is really an architecture. */
11892 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
},
11893 /* ??? iwmmxt is not a processor. */
11894 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
},
11895 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
},
11897 {"ep9312", ARM_ARCH_V4T
| ARM_CEXT_MAVERICK
, FPU_ARCH_MAVERICK
},
11901 struct arm_arch_option_table
11908 /* This list should, at a minimum, contain all the architecture names
11909 recognized by GCC. */
11910 static struct arm_arch_option_table arm_archs
[] =
11912 {"all", ARM_ANY
, FPU_ARCH_FPA
},
11913 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
11914 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
11915 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
11916 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
11917 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
11918 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
11919 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
11920 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
11921 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
11922 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
11923 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
11924 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
11925 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
11926 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
11927 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
11928 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
11929 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
11930 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
11931 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
11932 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
11933 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
11934 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
11935 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
11936 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
11937 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
11938 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
11939 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
11943 /* ISA extensions in the co-processor space. */
11944 struct arm_option_value_table
11950 static struct arm_option_value_table arm_extensions
[] =
11952 {"maverick", ARM_CEXT_MAVERICK
},
11953 {"xscale", ARM_CEXT_XSCALE
},
11954 {"iwmmxt", ARM_CEXT_IWMMXT
},
11958 /* This list should, at a minimum, contain all the fpu names
11959 recognized by GCC. */
11960 static struct arm_option_value_table arm_fpus
[] =
11962 {"softfpa", FPU_NONE
},
11963 {"fpe", FPU_ARCH_FPE
},
11964 {"fpe2", FPU_ARCH_FPE
},
11965 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
11966 {"fpa", FPU_ARCH_FPA
},
11967 {"fpa10", FPU_ARCH_FPA
},
11968 {"fpa11", FPU_ARCH_FPA
},
11969 {"arm7500fe", FPU_ARCH_FPA
},
11970 {"softvfp", FPU_ARCH_VFP
},
11971 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
11972 {"vfp", FPU_ARCH_VFP_V2
},
11973 {"vfp9", FPU_ARCH_VFP_V2
},
11974 {"vfp10", FPU_ARCH_VFP_V2
},
11975 {"vfp10-r0", FPU_ARCH_VFP_V1
},
11976 {"vfpxd", FPU_ARCH_VFP_V1xD
},
11977 {"arm1020t", FPU_ARCH_VFP_V1
},
11978 {"arm1020e", FPU_ARCH_VFP_V2
},
11979 {"arm1136jfs", FPU_ARCH_VFP_V2
},
11980 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
11981 {"maverick", FPU_ARCH_MAVERICK
},
11985 static struct arm_option_value_table arm_float_abis
[] =
11987 {"hard", ARM_FLOAT_ABI_HARD
},
11988 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
11989 {"soft", ARM_FLOAT_ABI_SOFT
},
11994 /* We only know how to output GNU and ver 4 (AAELF) formats. */
11995 static struct arm_option_value_table arm_eabis
[] =
11997 {"gnu", EF_ARM_EABI_UNKNOWN
},
11998 {"4", EF_ARM_EABI_VER4
},
12003 struct arm_long_option_table
12005 char * option
; /* Substring to match. */
12006 char * help
; /* Help information. */
12007 int (* func
) (char * subopt
); /* Function to decode sub-option. */
12008 char * deprecated
; /* If non-null, print this message. */
12012 arm_parse_extension (char * str
, int * opt_p
)
12014 while (str
!= NULL
&& *str
!= 0)
12016 struct arm_option_value_table
* opt
;
12022 as_bad (_("invalid architectural extension"));
12027 ext
= strchr (str
, '+');
12030 optlen
= ext
- str
;
12032 optlen
= strlen (str
);
12036 as_bad (_("missing architectural extension"));
12040 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
12041 if (strncmp (opt
->name
, str
, optlen
) == 0)
12043 *opt_p
|= opt
->value
;
12047 if (opt
->name
== NULL
)
12049 as_bad (_("unknown architectural extnsion `%s'"), str
);
12060 arm_parse_cpu (char * str
)
12062 struct arm_cpu_option_table
* opt
;
12063 char * ext
= strchr (str
, '+');
12067 optlen
= ext
- str
;
12069 optlen
= strlen (str
);
12073 as_bad (_("missing cpu name `%s'"), str
);
12077 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
12078 if (strncmp (opt
->name
, str
, optlen
) == 0)
12080 mcpu_cpu_opt
= opt
->value
;
12081 mcpu_fpu_opt
= opt
->default_fpu
;
12084 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
12089 as_bad (_("unknown cpu `%s'"), str
);
12094 arm_parse_arch (char * str
)
12096 struct arm_arch_option_table
*opt
;
12097 char *ext
= strchr (str
, '+');
12101 optlen
= ext
- str
;
12103 optlen
= strlen (str
);
12107 as_bad (_("missing architecture name `%s'"), str
);
12112 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
12113 if (streq (opt
->name
, str
))
12115 march_cpu_opt
= opt
->value
;
12116 march_fpu_opt
= opt
->default_fpu
;
12119 return arm_parse_extension (ext
, &march_cpu_opt
);
12124 as_bad (_("unknown architecture `%s'\n"), str
);
12129 arm_parse_fpu (char * str
)
12131 struct arm_option_value_table
* opt
;
12133 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
12134 if (streq (opt
->name
, str
))
12136 mfpu_opt
= opt
->value
;
12140 as_bad (_("unknown floating point format `%s'\n"), str
);
12145 arm_parse_float_abi (char * str
)
12147 struct arm_option_value_table
* opt
;
12149 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
12150 if (streq (opt
->name
, str
))
12152 mfloat_abi_opt
= opt
->value
;
12156 as_bad (_("unknown floating point abi `%s'\n"), str
);
12162 arm_parse_eabi (char * str
)
12164 struct arm_option_value_table
*opt
;
12166 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
12167 if (streq (opt
->name
, str
))
12169 meabi_flags
= opt
->value
;
12172 as_bad (_("unknown EABI `%s'\n"), str
);
12177 struct arm_long_option_table arm_long_opts
[] =
12179 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12180 arm_parse_cpu
, NULL
},
12181 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12182 arm_parse_arch
, NULL
},
12183 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12184 arm_parse_fpu
, NULL
},
12185 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12186 arm_parse_float_abi
, NULL
},
12188 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12189 arm_parse_eabi
, NULL
},
12191 {NULL
, NULL
, 0, NULL
}
12195 md_parse_option (int c
, char * arg
)
12197 struct arm_option_table
*opt
;
12198 struct arm_long_option_table
*lopt
;
12204 target_big_endian
= 1;
12210 target_big_endian
= 0;
12215 /* Listing option. Just ignore these, we don't support additional
12220 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
12222 if (c
== opt
->option
[0]
12223 && ((arg
== NULL
&& opt
->option
[1] == 0)
12224 || streq (arg
, opt
->option
+ 1)))
12226 #if WARN_DEPRECATED
12227 /* If the option is deprecated, tell the user. */
12228 if (opt
->deprecated
!= NULL
)
12229 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
12230 arg
? arg
: "", _(opt
->deprecated
));
12233 if (opt
->var
!= NULL
)
12234 *opt
->var
= opt
->value
;
12240 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
12242 /* These options are expected to have an argument. */
12243 if (c
== lopt
->option
[0]
12245 && strncmp (arg
, lopt
->option
+ 1,
12246 strlen (lopt
->option
+ 1)) == 0)
12248 #if WARN_DEPRECATED
12249 /* If the option is deprecated, tell the user. */
12250 if (lopt
->deprecated
!= NULL
)
12251 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
12252 _(lopt
->deprecated
));
12255 /* Call the sup-option parser. */
12256 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
12267 md_show_usage (FILE * fp
)
12269 struct arm_option_table
*opt
;
12270 struct arm_long_option_table
*lopt
;
12272 fprintf (fp
, _(" ARM-specific assembler options:\n"));
12274 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
12275 if (opt
->help
!= NULL
)
12276 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
12278 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
12279 if (lopt
->help
!= NULL
)
12280 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
12284 -EB assemble code for a big-endian cpu\n"));
12289 -EL assemble code for a little-endian cpu\n"));