1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6927 /* New operands for Armv8.1-M Mainline. */
6928 OP_LR
, /* ARM LR register */
6929 OP_RRe
, /* ARM register, only even numbered. */
6930 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6931 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6933 OP_REGLST
, /* ARM register list */
6934 OP_CLRMLST
, /* CLRM register list */
6935 OP_VRSLST
, /* VFP single-precision register list */
6936 OP_VRDLST
, /* VFP double-precision register list */
6937 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6938 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6939 OP_NSTRLST
, /* Neon element/structure list */
6940 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6941 OP_MSTRLST2
, /* MVE vector list with two elements. */
6942 OP_MSTRLST4
, /* MVE vector list with four elements. */
6944 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6945 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6946 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6947 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6949 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6950 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6954 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6955 scalar, or ARM register. */
6956 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6957 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6958 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6959 OP_VMOV
, /* Neon VMOV operands. */
6960 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6961 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6963 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6964 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6965 OP_VLDR
, /* VLDR operand. */
6967 OP_I0
, /* immediate zero */
6968 OP_I7
, /* immediate value 0 .. 7 */
6969 OP_I15
, /* 0 .. 15 */
6970 OP_I16
, /* 1 .. 16 */
6971 OP_I16z
, /* 0 .. 16 */
6972 OP_I31
, /* 0 .. 31 */
6973 OP_I31w
, /* 0 .. 31, optional trailing ! */
6974 OP_I32
, /* 1 .. 32 */
6975 OP_I32z
, /* 0 .. 32 */
6976 OP_I63
, /* 0 .. 63 */
6977 OP_I63s
, /* -64 .. 63 */
6978 OP_I64
, /* 1 .. 64 */
6979 OP_I64z
, /* 0 .. 64 */
6980 OP_I255
, /* 0 .. 255 */
6982 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6983 OP_I7b
, /* 0 .. 7 */
6984 OP_I15b
, /* 0 .. 15 */
6985 OP_I31b
, /* 0 .. 31 */
6987 OP_SH
, /* shifter operand */
6988 OP_SHG
, /* shifter operand with possible group relocation */
6989 OP_ADDR
, /* Memory address expression (any mode) */
6990 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6991 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6992 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6993 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6994 OP_EXP
, /* arbitrary expression */
6995 OP_EXPi
, /* same, with optional immediate prefix */
6996 OP_EXPr
, /* same, with optional relocation suffix */
6997 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6998 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6999 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7000 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7002 OP_CPSF
, /* CPS flags */
7003 OP_ENDI
, /* Endianness specifier */
7004 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7005 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7006 OP_COND
, /* conditional code */
7007 OP_TB
, /* Table branch. */
7009 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7011 OP_RRnpc_I0
, /* ARM register or literal 0 */
7012 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7013 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7014 OP_RF_IF
, /* FPA register or immediate */
7015 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7016 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7018 /* Optional operands. */
7019 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7020 OP_oI31b
, /* 0 .. 31 */
7021 OP_oI32b
, /* 1 .. 32 */
7022 OP_oI32z
, /* 0 .. 32 */
7023 OP_oIffffb
, /* 0 .. 65535 */
7024 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7026 OP_oRR
, /* ARM register */
7027 OP_oLR
, /* ARM LR register */
7028 OP_oRRnpc
, /* ARM register, not the PC */
7029 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7030 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7031 OP_oRND
, /* Optional Neon double precision register */
7032 OP_oRNQ
, /* Optional Neon quad precision register */
7033 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7034 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7035 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7036 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7038 OP_oSHll
, /* LSL immediate */
7039 OP_oSHar
, /* ASR immediate */
7040 OP_oSHllar
, /* LSL or ASR immediate */
7041 OP_oROR
, /* ROR 0/8/16/24 */
7042 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7044 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7046 /* Some pre-defined mixed (ARM/THUMB) operands. */
7047 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7048 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7049 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7051 OP_FIRST_OPTIONAL
= OP_oI7b
7054 /* Generic instruction operand parser. This does no encoding and no
7055 semantic validation; it merely squirrels values away in the inst
7056 structure. Returns SUCCESS or FAIL depending on whether the
7057 specified grammar matched. */
7059 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7061 unsigned const int *upat
= pattern
;
7062 char *backtrack_pos
= 0;
7063 const char *backtrack_error
= 0;
7064 int i
, val
= 0, backtrack_index
= 0;
7065 enum arm_reg_type rtype
;
7066 parse_operand_result result
;
7067 unsigned int op_parse_code
;
7068 bfd_boolean partial_match
;
7070 #define po_char_or_fail(chr) \
7073 if (skip_past_char (&str, chr) == FAIL) \
7078 #define po_reg_or_fail(regtype) \
7081 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7082 & inst.operands[i].vectype); \
7085 first_error (_(reg_expected_msgs[regtype])); \
7088 inst.operands[i].reg = val; \
7089 inst.operands[i].isreg = 1; \
7090 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7091 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7092 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7093 || rtype == REG_TYPE_VFD \
7094 || rtype == REG_TYPE_NQ); \
7095 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7099 #define po_reg_or_goto(regtype, label) \
7102 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7103 & inst.operands[i].vectype); \
7107 inst.operands[i].reg = val; \
7108 inst.operands[i].isreg = 1; \
7109 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7110 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7111 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7112 || rtype == REG_TYPE_VFD \
7113 || rtype == REG_TYPE_NQ); \
7114 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7118 #define po_imm_or_fail(min, max, popt) \
7121 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7123 inst.operands[i].imm = val; \
7127 #define po_scalar_or_goto(elsz, label, reg_type) \
7130 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7134 inst.operands[i].reg = val; \
7135 inst.operands[i].isscalar = 1; \
7139 #define po_misc_or_fail(expr) \
7147 #define po_misc_or_fail_no_backtrack(expr) \
7151 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7152 backtrack_pos = 0; \
7153 if (result != PARSE_OPERAND_SUCCESS) \
7158 #define po_barrier_or_imm(str) \
7161 val = parse_barrier (&str); \
7162 if (val == FAIL && ! ISALPHA (*str)) \
7165 /* ISB can only take SY as an option. */ \
7166 || ((inst.instruction & 0xf0) == 0x60 \
7169 inst.error = _("invalid barrier type"); \
7170 backtrack_pos = 0; \
7176 skip_whitespace (str
);
7178 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7180 op_parse_code
= upat
[i
];
7181 if (op_parse_code
>= 1<<16)
7182 op_parse_code
= thumb
? (op_parse_code
>> 16)
7183 : (op_parse_code
& ((1<<16)-1));
7185 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7187 /* Remember where we are in case we need to backtrack. */
7188 backtrack_pos
= str
;
7189 backtrack_error
= inst
.error
;
7190 backtrack_index
= i
;
7193 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7194 po_char_or_fail (',');
7196 switch (op_parse_code
)
7208 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7209 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7210 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7211 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7212 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7213 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7216 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7220 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7223 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7225 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7227 /* Also accept generic coprocessor regs for unknown registers. */
7229 po_reg_or_fail (REG_TYPE_CN
);
7231 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7232 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7233 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7234 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7235 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7236 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7237 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7238 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7239 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7240 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7243 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7246 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7247 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7249 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7254 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7258 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7260 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7263 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7265 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7268 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7270 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7275 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7278 po_reg_or_fail (REG_TYPE_NSDQ
);
7282 po_reg_or_fail (REG_TYPE_MQ
);
7284 /* Neon scalar. Using an element size of 8 means that some invalid
7285 scalars are accepted here, so deal with those in later code. */
7286 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7290 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7293 po_imm_or_fail (0, 0, TRUE
);
7298 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7302 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7307 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7310 if (parse_ifimm_zero (&str
))
7311 inst
.operands
[i
].imm
= 0;
7315 = _("only floating point zero is allowed as immediate value");
7323 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7326 po_reg_or_fail (REG_TYPE_RN
);
7330 case OP_RNSDQ_RNSC_MQ_RR
:
7331 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7334 case OP_RNSDQ_RNSC_MQ
:
7335 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7340 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7344 po_reg_or_fail (REG_TYPE_NSDQ
);
7351 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7354 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7357 po_reg_or_fail (REG_TYPE_NSD
);
7361 case OP_RNDQMQ_RNSC
:
7362 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7367 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7370 po_reg_or_fail (REG_TYPE_NDQ
);
7376 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7379 po_reg_or_fail (REG_TYPE_VFD
);
7384 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7385 not careful then bad things might happen. */
7386 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7389 case OP_RNDQMQ_Ibig
:
7390 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7395 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7398 /* There's a possibility of getting a 64-bit immediate here, so
7399 we need special handling. */
7400 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7403 inst
.error
= _("immediate value is out of range");
7411 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7414 po_imm_or_fail (0, 63, TRUE
);
7419 po_char_or_fail ('[');
7420 po_reg_or_fail (REG_TYPE_RN
);
7421 po_char_or_fail (']');
7427 po_reg_or_fail (REG_TYPE_RN
);
7428 if (skip_past_char (&str
, '!') == SUCCESS
)
7429 inst
.operands
[i
].writeback
= 1;
7433 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7434 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7435 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7436 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7437 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7438 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7439 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7440 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7441 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7442 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7443 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7444 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7446 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7448 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7449 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7451 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7452 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7453 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7454 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7456 /* Immediate variants */
7458 po_char_or_fail ('{');
7459 po_imm_or_fail (0, 255, TRUE
);
7460 po_char_or_fail ('}');
7464 /* The expression parser chokes on a trailing !, so we have
7465 to find it first and zap it. */
7468 while (*s
&& *s
!= ',')
7473 inst
.operands
[i
].writeback
= 1;
7475 po_imm_or_fail (0, 31, TRUE
);
7483 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7488 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7493 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7495 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7497 val
= parse_reloc (&str
);
7500 inst
.error
= _("unrecognized relocation suffix");
7503 else if (val
!= BFD_RELOC_UNUSED
)
7505 inst
.operands
[i
].imm
= val
;
7506 inst
.operands
[i
].hasreloc
= 1;
7512 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7514 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7516 inst
.operands
[i
].hasreloc
= 1;
7518 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7520 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7521 inst
.operands
[i
].hasreloc
= 0;
7525 /* Operand for MOVW or MOVT. */
7527 po_misc_or_fail (parse_half (&str
));
7530 /* Register or expression. */
7531 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7532 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7534 /* Register or immediate. */
7535 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7536 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7538 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7540 if (!is_immediate_prefix (*str
))
7543 val
= parse_fpa_immediate (&str
);
7546 /* FPA immediates are encoded as registers 8-15.
7547 parse_fpa_immediate has already applied the offset. */
7548 inst
.operands
[i
].reg
= val
;
7549 inst
.operands
[i
].isreg
= 1;
7552 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7553 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7555 /* Two kinds of register. */
7558 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7560 || (rege
->type
!= REG_TYPE_MMXWR
7561 && rege
->type
!= REG_TYPE_MMXWC
7562 && rege
->type
!= REG_TYPE_MMXWCG
))
7564 inst
.error
= _("iWMMXt data or control register expected");
7567 inst
.operands
[i
].reg
= rege
->number
;
7568 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7574 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7576 || (rege
->type
!= REG_TYPE_MMXWC
7577 && rege
->type
!= REG_TYPE_MMXWCG
))
7579 inst
.error
= _("iWMMXt control register expected");
7582 inst
.operands
[i
].reg
= rege
->number
;
7583 inst
.operands
[i
].isreg
= 1;
7588 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7589 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7590 case OP_oROR
: val
= parse_ror (&str
); break;
7592 case OP_COND
: val
= parse_cond (&str
); break;
7593 case OP_oBARRIER_I15
:
7594 po_barrier_or_imm (str
); break;
7596 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7602 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7603 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7605 inst
.error
= _("Banked registers are not available with this "
7611 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7615 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7618 val
= parse_sys_vldr_vstr (&str
);
7622 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7625 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7627 if (strncasecmp (str
, "APSR_", 5) == 0)
7634 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7635 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7636 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7637 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7638 default: found
= 16;
7642 inst
.operands
[i
].isvec
= 1;
7643 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7644 inst
.operands
[i
].reg
= REG_PC
;
7651 po_misc_or_fail (parse_tb (&str
));
7654 /* Register lists. */
7656 val
= parse_reg_list (&str
, REGLIST_RN
);
7659 inst
.operands
[i
].writeback
= 1;
7665 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7669 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7674 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7679 /* Allow Q registers too. */
7680 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7681 REGLIST_NEON_D
, &partial_match
);
7685 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7686 REGLIST_VFP_S
, &partial_match
);
7687 inst
.operands
[i
].issingle
= 1;
7692 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7693 REGLIST_VFP_D_VPR
, &partial_match
);
7694 if (val
== FAIL
&& !partial_match
)
7697 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7698 REGLIST_VFP_S_VPR
, &partial_match
);
7699 inst
.operands
[i
].issingle
= 1;
7704 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7705 REGLIST_NEON_D
, &partial_match
);
7710 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7711 1, &inst
.operands
[i
].vectype
);
7712 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7716 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7717 0, &inst
.operands
[i
].vectype
);
7720 /* Addressing modes */
7722 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7726 po_misc_or_fail (parse_address (&str
, i
));
7730 po_misc_or_fail_no_backtrack (
7731 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7735 po_misc_or_fail_no_backtrack (
7736 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7740 po_misc_or_fail_no_backtrack (
7741 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7745 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7749 po_misc_or_fail_no_backtrack (
7750 parse_shifter_operand_group_reloc (&str
, i
));
7754 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7758 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7762 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7767 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7770 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7773 po_reg_or_fail (REG_TYPE_ZR
);
7777 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7780 /* Various value-based sanity checks and shared operations. We
7781 do not signal immediate failures for the register constraints;
7782 this allows a syntax error to take precedence. */
7783 switch (op_parse_code
)
7791 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7792 inst
.error
= BAD_PC
;
7797 if (inst
.operands
[i
].isreg
)
7799 if (inst
.operands
[i
].reg
== REG_PC
)
7800 inst
.error
= BAD_PC
;
7801 else if (inst
.operands
[i
].reg
== REG_SP
7802 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7803 relaxed since ARMv8-A. */
7804 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7807 inst
.error
= BAD_SP
;
7813 if (inst
.operands
[i
].isreg
7814 && inst
.operands
[i
].reg
== REG_PC
7815 && (inst
.operands
[i
].writeback
|| thumb
))
7816 inst
.error
= BAD_PC
;
7821 if (inst
.operands
[i
].isreg
)
7831 case OP_oBARRIER_I15
:
7844 inst
.operands
[i
].imm
= val
;
7849 if (inst
.operands
[i
].reg
!= REG_LR
)
7850 inst
.error
= _("operand must be LR register");
7855 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7856 inst
.error
= BAD_PC
;
7860 if (inst
.operands
[i
].isreg
7861 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7862 inst
.error
= BAD_ODD
;
7866 if (inst
.operands
[i
].isreg
)
7868 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7869 inst
.error
= BAD_EVEN
;
7870 else if (inst
.operands
[i
].reg
== REG_SP
)
7871 as_tsktsk (MVE_BAD_SP
);
7872 else if (inst
.operands
[i
].reg
== REG_PC
)
7873 inst
.error
= BAD_PC
;
7881 /* If we get here, this operand was successfully parsed. */
7882 inst
.operands
[i
].present
= 1;
7886 inst
.error
= BAD_ARGS
;
7891 /* The parse routine should already have set inst.error, but set a
7892 default here just in case. */
7894 inst
.error
= BAD_SYNTAX
;
7898 /* Do not backtrack over a trailing optional argument that
7899 absorbed some text. We will only fail again, with the
7900 'garbage following instruction' error message, which is
7901 probably less helpful than the current one. */
7902 if (backtrack_index
== i
&& backtrack_pos
!= str
7903 && upat
[i
+1] == OP_stop
)
7906 inst
.error
= BAD_SYNTAX
;
7910 /* Try again, skipping the optional argument at backtrack_pos. */
7911 str
= backtrack_pos
;
7912 inst
.error
= backtrack_error
;
7913 inst
.operands
[backtrack_index
].present
= 0;
7914 i
= backtrack_index
;
7918 /* Check that we have parsed all the arguments. */
7919 if (*str
!= '\0' && !inst
.error
)
7920 inst
.error
= _("garbage following instruction");
7922 return inst
.error
? FAIL
: SUCCESS
;
7925 #undef po_char_or_fail
7926 #undef po_reg_or_fail
7927 #undef po_reg_or_goto
7928 #undef po_imm_or_fail
7929 #undef po_scalar_or_fail
7930 #undef po_barrier_or_imm
7932 /* Shorthand macro for instruction encoding functions issuing errors. */
7933 #define constraint(expr, err) \
7944 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7945 instructions are unpredictable if these registers are used. This
7946 is the BadReg predicate in ARM's Thumb-2 documentation.
7948 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7949 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7950 #define reject_bad_reg(reg) \
7952 if (reg == REG_PC) \
7954 inst.error = BAD_PC; \
7957 else if (reg == REG_SP \
7958 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7960 inst.error = BAD_SP; \
7965 /* If REG is R13 (the stack pointer), warn that its use is
7967 #define warn_deprecated_sp(reg) \
7969 if (warn_on_deprecated && reg == REG_SP) \
7970 as_tsktsk (_("use of r13 is deprecated")); \
7973 /* Functions for operand encoding. ARM, then Thumb. */
7975 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7977 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7979 The only binary encoding difference is the Coprocessor number. Coprocessor
7980 9 is used for half-precision calculations or conversions. The format of the
7981 instruction is the same as the equivalent Coprocessor 10 instruction that
7982 exists for Single-Precision operation. */
7985 do_scalar_fp16_v82_encode (void)
7987 if (inst
.cond
< COND_ALWAYS
)
7988 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7989 " the behaviour is UNPREDICTABLE"));
7990 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7993 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7994 mark_feature_used (&arm_ext_fp16
);
7997 /* If VAL can be encoded in the immediate field of an ARM instruction,
7998 return the encoded form. Otherwise, return FAIL. */
8001 encode_arm_immediate (unsigned int val
)
8008 for (i
= 2; i
< 32; i
+= 2)
8009 if ((a
= rotate_left (val
, i
)) <= 0xff)
8010 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8015 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8016 return the encoded form. Otherwise, return FAIL. */
8018 encode_thumb32_immediate (unsigned int val
)
8025 for (i
= 1; i
<= 24; i
++)
8028 if ((val
& ~(0xff << i
)) == 0)
8029 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8033 if (val
== ((a
<< 16) | a
))
8035 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8039 if (val
== ((a
<< 16) | a
))
8040 return 0x200 | (a
>> 8);
8044 /* Encode a VFP SP or DP register number into inst.instruction. */
8047 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8049 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8052 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8055 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8058 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8063 first_error (_("D register out of range for selected VFP version"));
8071 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8075 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8079 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8083 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8087 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8091 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8099 /* Encode a <shift> in an ARM-format instruction. The immediate,
8100 if any, is handled by md_apply_fix. */
8102 encode_arm_shift (int i
)
8104 /* register-shifted register. */
8105 if (inst
.operands
[i
].immisreg
)
8108 for (op_index
= 0; op_index
<= i
; ++op_index
)
8110 /* Check the operand only when it's presented. In pre-UAL syntax,
8111 if the destination register is the same as the first operand, two
8112 register form of the instruction can be used. */
8113 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8114 && inst
.operands
[op_index
].reg
== REG_PC
)
8115 as_warn (UNPRED_REG ("r15"));
8118 if (inst
.operands
[i
].imm
== REG_PC
)
8119 as_warn (UNPRED_REG ("r15"));
8122 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8123 inst
.instruction
|= SHIFT_ROR
<< 5;
8126 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8127 if (inst
.operands
[i
].immisreg
)
8129 inst
.instruction
|= SHIFT_BY_REG
;
8130 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8133 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8138 encode_arm_shifter_operand (int i
)
8140 if (inst
.operands
[i
].isreg
)
8142 inst
.instruction
|= inst
.operands
[i
].reg
;
8143 encode_arm_shift (i
);
8147 inst
.instruction
|= INST_IMMEDIATE
;
8148 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8149 inst
.instruction
|= inst
.operands
[i
].imm
;
8153 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8155 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8158 Generate an error if the operand is not a register. */
8159 constraint (!inst
.operands
[i
].isreg
,
8160 _("Instruction does not support =N addresses"));
8162 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8164 if (inst
.operands
[i
].preind
)
8168 inst
.error
= _("instruction does not accept preindexed addressing");
8171 inst
.instruction
|= PRE_INDEX
;
8172 if (inst
.operands
[i
].writeback
)
8173 inst
.instruction
|= WRITE_BACK
;
8176 else if (inst
.operands
[i
].postind
)
8178 gas_assert (inst
.operands
[i
].writeback
);
8180 inst
.instruction
|= WRITE_BACK
;
8182 else /* unindexed - only for coprocessor */
8184 inst
.error
= _("instruction does not accept unindexed addressing");
8188 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8189 && (((inst
.instruction
& 0x000f0000) >> 16)
8190 == ((inst
.instruction
& 0x0000f000) >> 12)))
8191 as_warn ((inst
.instruction
& LOAD_BIT
)
8192 ? _("destination register same as write-back base")
8193 : _("source register same as write-back base"));
8196 /* inst.operands[i] was set up by parse_address. Encode it into an
8197 ARM-format mode 2 load or store instruction. If is_t is true,
8198 reject forms that cannot be used with a T instruction (i.e. not
8201 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8203 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8205 encode_arm_addr_mode_common (i
, is_t
);
8207 if (inst
.operands
[i
].immisreg
)
8209 constraint ((inst
.operands
[i
].imm
== REG_PC
8210 || (is_pc
&& inst
.operands
[i
].writeback
)),
8212 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8213 inst
.instruction
|= inst
.operands
[i
].imm
;
8214 if (!inst
.operands
[i
].negative
)
8215 inst
.instruction
|= INDEX_UP
;
8216 if (inst
.operands
[i
].shifted
)
8218 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8219 inst
.instruction
|= SHIFT_ROR
<< 5;
8222 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8223 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8227 else /* immediate offset in inst.relocs[0] */
8229 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8231 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8233 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8234 cannot use PC in addressing.
8235 PC cannot be used in writeback addressing, either. */
8236 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8239 /* Use of PC in str is deprecated for ARMv7. */
8240 if (warn_on_deprecated
8242 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8243 as_tsktsk (_("use of PC in this instruction is deprecated"));
8246 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8248 /* Prefer + for zero encoded value. */
8249 if (!inst
.operands
[i
].negative
)
8250 inst
.instruction
|= INDEX_UP
;
8251 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8256 /* inst.operands[i] was set up by parse_address. Encode it into an
8257 ARM-format mode 3 load or store instruction. Reject forms that
8258 cannot be used with such instructions. If is_t is true, reject
8259 forms that cannot be used with a T instruction (i.e. not
8262 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8264 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8266 inst
.error
= _("instruction does not accept scaled register index");
8270 encode_arm_addr_mode_common (i
, is_t
);
8272 if (inst
.operands
[i
].immisreg
)
8274 constraint ((inst
.operands
[i
].imm
== REG_PC
8275 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8277 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8279 inst
.instruction
|= inst
.operands
[i
].imm
;
8280 if (!inst
.operands
[i
].negative
)
8281 inst
.instruction
|= INDEX_UP
;
8283 else /* immediate offset in inst.relocs[0] */
8285 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8286 && inst
.operands
[i
].writeback
),
8288 inst
.instruction
|= HWOFFSET_IMM
;
8289 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8291 /* Prefer + for zero encoded value. */
8292 if (!inst
.operands
[i
].negative
)
8293 inst
.instruction
|= INDEX_UP
;
8295 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8300 /* Write immediate bits [7:0] to the following locations:
8302 |28/24|23 19|18 16|15 4|3 0|
8303 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8305 This function is used by VMOV/VMVN/VORR/VBIC. */
8308 neon_write_immbits (unsigned immbits
)
8310 inst
.instruction
|= immbits
& 0xf;
8311 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8312 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8315 /* Invert low-order SIZE bits of XHI:XLO. */
8318 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8320 unsigned immlo
= xlo
? *xlo
: 0;
8321 unsigned immhi
= xhi
? *xhi
: 0;
8326 immlo
= (~immlo
) & 0xff;
8330 immlo
= (~immlo
) & 0xffff;
8334 immhi
= (~immhi
) & 0xffffffff;
8338 immlo
= (~immlo
) & 0xffffffff;
8352 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8356 neon_bits_same_in_bytes (unsigned imm
)
8358 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8359 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8360 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8361 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8364 /* For immediate of above form, return 0bABCD. */
8367 neon_squash_bits (unsigned imm
)
8369 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8370 | ((imm
& 0x01000000) >> 21);
8373 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8376 neon_qfloat_bits (unsigned imm
)
8378 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8381 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8382 the instruction. *OP is passed as the initial value of the op field, and
8383 may be set to a different value depending on the constant (i.e.
8384 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8385 MVN). If the immediate looks like a repeated pattern then also
8386 try smaller element sizes. */
8389 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8390 unsigned *immbits
, int *op
, int size
,
8391 enum neon_el_type type
)
8393 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8395 if (type
== NT_float
&& !float_p
)
8398 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8400 if (size
!= 32 || *op
== 1)
8402 *immbits
= neon_qfloat_bits (immlo
);
8408 if (neon_bits_same_in_bytes (immhi
)
8409 && neon_bits_same_in_bytes (immlo
))
8413 *immbits
= (neon_squash_bits (immhi
) << 4)
8414 | neon_squash_bits (immlo
);
8425 if (immlo
== (immlo
& 0x000000ff))
8430 else if (immlo
== (immlo
& 0x0000ff00))
8432 *immbits
= immlo
>> 8;
8435 else if (immlo
== (immlo
& 0x00ff0000))
8437 *immbits
= immlo
>> 16;
8440 else if (immlo
== (immlo
& 0xff000000))
8442 *immbits
= immlo
>> 24;
8445 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8447 *immbits
= (immlo
>> 8) & 0xff;
8450 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8452 *immbits
= (immlo
>> 16) & 0xff;
8456 if ((immlo
& 0xffff) != (immlo
>> 16))
8463 if (immlo
== (immlo
& 0x000000ff))
8468 else if (immlo
== (immlo
& 0x0000ff00))
8470 *immbits
= immlo
>> 8;
8474 if ((immlo
& 0xff) != (immlo
>> 8))
8479 if (immlo
== (immlo
& 0x000000ff))
8481 /* Don't allow MVN with 8-bit immediate. */
8491 #if defined BFD_HOST_64_BIT
8492 /* Returns TRUE if double precision value V may be cast
8493 to single precision without loss of accuracy. */
8496 is_double_a_single (bfd_int64_t v
)
8498 int exp
= (int)((v
>> 52) & 0x7FF);
8499 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8501 return (exp
== 0 || exp
== 0x7FF
8502 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8503 && (mantissa
& 0x1FFFFFFFl
) == 0;
8506 /* Returns a double precision value casted to single precision
8507 (ignoring the least significant bits in exponent and mantissa). */
8510 double_to_single (bfd_int64_t v
)
8512 int sign
= (int) ((v
>> 63) & 1l);
8513 int exp
= (int) ((v
>> 52) & 0x7FF);
8514 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8520 exp
= exp
- 1023 + 127;
8529 /* No denormalized numbers. */
8535 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8537 #endif /* BFD_HOST_64_BIT */
8546 static void do_vfp_nsyn_opcode (const char *);
8548 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8549 Determine whether it can be performed with a move instruction; if
8550 it can, convert inst.instruction to that move instruction and
8551 return TRUE; if it can't, convert inst.instruction to a literal-pool
8552 load and return FALSE. If this is not a valid thing to do in the
8553 current context, set inst.error and return TRUE.
8555 inst.operands[i] describes the destination register. */
8558 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8561 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8562 bfd_boolean arm_p
= (t
== CONST_ARM
);
8565 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8569 if ((inst
.instruction
& tbit
) == 0)
8571 inst
.error
= _("invalid pseudo operation");
8575 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8576 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8577 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8579 inst
.error
= _("constant expression expected");
8583 if (inst
.relocs
[0].exp
.X_op
== O_constant
8584 || inst
.relocs
[0].exp
.X_op
== O_big
)
8586 #if defined BFD_HOST_64_BIT
8591 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8593 LITTLENUM_TYPE w
[X_PRECISION
];
8596 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8598 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8600 /* FIXME: Should we check words w[2..5] ? */
8605 #if defined BFD_HOST_64_BIT
8607 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8608 << LITTLENUM_NUMBER_OF_BITS
)
8609 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8610 << LITTLENUM_NUMBER_OF_BITS
)
8611 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8612 << LITTLENUM_NUMBER_OF_BITS
)
8613 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8615 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8616 | (l
[0] & LITTLENUM_MASK
);
8620 v
= inst
.relocs
[0].exp
.X_add_number
;
8622 if (!inst
.operands
[i
].issingle
)
8626 /* LDR should not use lead in a flag-setting instruction being
8627 chosen so we do not check whether movs can be used. */
8629 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8630 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8631 && inst
.operands
[i
].reg
!= 13
8632 && inst
.operands
[i
].reg
!= 15)
8634 /* Check if on thumb2 it can be done with a mov.w, mvn or
8635 movw instruction. */
8636 unsigned int newimm
;
8637 bfd_boolean isNegated
;
8639 newimm
= encode_thumb32_immediate (v
);
8640 if (newimm
!= (unsigned int) FAIL
)
8644 newimm
= encode_thumb32_immediate (~v
);
8645 if (newimm
!= (unsigned int) FAIL
)
8649 /* The number can be loaded with a mov.w or mvn
8651 if (newimm
!= (unsigned int) FAIL
8652 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8654 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8655 | (inst
.operands
[i
].reg
<< 8));
8656 /* Change to MOVN. */
8657 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8658 inst
.instruction
|= (newimm
& 0x800) << 15;
8659 inst
.instruction
|= (newimm
& 0x700) << 4;
8660 inst
.instruction
|= (newimm
& 0x0ff);
8663 /* The number can be loaded with a movw instruction. */
8664 else if ((v
& ~0xFFFF) == 0
8665 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8667 int imm
= v
& 0xFFFF;
8669 inst
.instruction
= 0xf2400000; /* MOVW. */
8670 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8671 inst
.instruction
|= (imm
& 0xf000) << 4;
8672 inst
.instruction
|= (imm
& 0x0800) << 15;
8673 inst
.instruction
|= (imm
& 0x0700) << 4;
8674 inst
.instruction
|= (imm
& 0x00ff);
8681 int value
= encode_arm_immediate (v
);
8685 /* This can be done with a mov instruction. */
8686 inst
.instruction
&= LITERAL_MASK
;
8687 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8688 inst
.instruction
|= value
& 0xfff;
8692 value
= encode_arm_immediate (~ v
);
8695 /* This can be done with a mvn instruction. */
8696 inst
.instruction
&= LITERAL_MASK
;
8697 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8698 inst
.instruction
|= value
& 0xfff;
8702 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8705 unsigned immbits
= 0;
8706 unsigned immlo
= inst
.operands
[1].imm
;
8707 unsigned immhi
= inst
.operands
[1].regisimm
8708 ? inst
.operands
[1].reg
8709 : inst
.relocs
[0].exp
.X_unsigned
8711 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8712 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8713 &op
, 64, NT_invtype
);
8717 neon_invert_size (&immlo
, &immhi
, 64);
8719 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8720 &op
, 64, NT_invtype
);
8725 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8731 /* Fill other bits in vmov encoding for both thumb and arm. */
8733 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8735 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8736 neon_write_immbits (immbits
);
8744 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8745 if (inst
.operands
[i
].issingle
8746 && is_quarter_float (inst
.operands
[1].imm
)
8747 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8749 inst
.operands
[1].imm
=
8750 neon_qfloat_bits (v
);
8751 do_vfp_nsyn_opcode ("fconsts");
8755 /* If our host does not support a 64-bit type then we cannot perform
8756 the following optimization. This mean that there will be a
8757 discrepancy between the output produced by an assembler built for
8758 a 32-bit-only host and the output produced from a 64-bit host, but
8759 this cannot be helped. */
8760 #if defined BFD_HOST_64_BIT
8761 else if (!inst
.operands
[1].issingle
8762 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8764 if (is_double_a_single (v
)
8765 && is_quarter_float (double_to_single (v
)))
8767 inst
.operands
[1].imm
=
8768 neon_qfloat_bits (double_to_single (v
));
8769 do_vfp_nsyn_opcode ("fconstd");
8777 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8778 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8781 inst
.operands
[1].reg
= REG_PC
;
8782 inst
.operands
[1].isreg
= 1;
8783 inst
.operands
[1].preind
= 1;
8784 inst
.relocs
[0].pc_rel
= 1;
8785 inst
.relocs
[0].type
= (thumb_p
8786 ? BFD_RELOC_ARM_THUMB_OFFSET
8788 ? BFD_RELOC_ARM_HWLITERAL
8789 : BFD_RELOC_ARM_LITERAL
));
8793 /* inst.operands[i] was set up by parse_address. Encode it into an
8794 ARM-format instruction. Reject all forms which cannot be encoded
8795 into a coprocessor load/store instruction. If wb_ok is false,
8796 reject use of writeback; if unind_ok is false, reject use of
8797 unindexed addressing. If reloc_override is not 0, use it instead
8798 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8799 (in which case it is preserved). */
8802 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8804 if (!inst
.operands
[i
].isreg
)
8807 if (! inst
.operands
[0].isvec
)
8809 inst
.error
= _("invalid co-processor operand");
8812 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8816 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8818 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8820 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8822 gas_assert (!inst
.operands
[i
].writeback
);
8825 inst
.error
= _("instruction does not support unindexed addressing");
8828 inst
.instruction
|= inst
.operands
[i
].imm
;
8829 inst
.instruction
|= INDEX_UP
;
8833 if (inst
.operands
[i
].preind
)
8834 inst
.instruction
|= PRE_INDEX
;
8836 if (inst
.operands
[i
].writeback
)
8838 if (inst
.operands
[i
].reg
== REG_PC
)
8840 inst
.error
= _("pc may not be used with write-back");
8845 inst
.error
= _("instruction does not support writeback");
8848 inst
.instruction
|= WRITE_BACK
;
8852 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8853 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8854 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8855 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8858 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8860 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8863 /* Prefer + for zero encoded value. */
8864 if (!inst
.operands
[i
].negative
)
8865 inst
.instruction
|= INDEX_UP
;
8870 /* Functions for instruction encoding, sorted by sub-architecture.
8871 First some generics; their names are taken from the conventional
8872 bit positions for register arguments in ARM format instructions. */
8882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8895 inst
.instruction
|= inst
.operands
[1].reg
;
8901 inst
.instruction
|= inst
.operands
[0].reg
;
8902 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8909 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8916 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8927 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8929 if (ARM_CPU_IS_ANY (cpu_variant
))
8931 as_tsktsk ("%s", msg
);
8934 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8946 unsigned Rn
= inst
.operands
[2].reg
;
8947 /* Enforce restrictions on SWP instruction. */
8948 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8950 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8951 _("Rn must not overlap other operands"));
8953 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8955 if (!check_obsolete (&arm_ext_v8
,
8956 _("swp{b} use is obsoleted for ARMv8 and later"))
8957 && warn_on_deprecated
8958 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8959 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8963 inst
.instruction
|= inst
.operands
[1].reg
;
8964 inst
.instruction
|= Rn
<< 16;
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8971 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8972 inst
.instruction
|= inst
.operands
[2].reg
;
8978 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8979 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8980 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8981 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8983 inst
.instruction
|= inst
.operands
[0].reg
;
8984 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8985 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8991 inst
.instruction
|= inst
.operands
[0].imm
;
8997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8998 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9001 /* ARM instructions, in alphabetical order by function name (except
9002 that wrapper functions appear immediately after the function they
9005 /* This is a pseudo-op of the form "adr rd, label" to be converted
9006 into a relative address of the form "add rd, pc, #label-.-8". */
9011 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9013 /* Frag hacking will turn this into a sub instruction if the offset turns
9014 out to be negative. */
9015 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9016 inst
.relocs
[0].pc_rel
= 1;
9017 inst
.relocs
[0].exp
.X_add_number
-= 8;
9019 if (support_interwork
9020 && inst
.relocs
[0].exp
.X_op
== O_symbol
9021 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9022 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9023 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9024 inst
.relocs
[0].exp
.X_add_number
|= 1;
9027 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9028 into a relative address of the form:
9029 add rd, pc, #low(label-.-8)"
9030 add rd, rd, #high(label-.-8)" */
9035 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9037 /* Frag hacking will turn this into a sub instruction if the offset turns
9038 out to be negative. */
9039 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9040 inst
.relocs
[0].pc_rel
= 1;
9041 inst
.size
= INSN_SIZE
* 2;
9042 inst
.relocs
[0].exp
.X_add_number
-= 8;
9044 if (support_interwork
9045 && inst
.relocs
[0].exp
.X_op
== O_symbol
9046 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9047 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9048 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9049 inst
.relocs
[0].exp
.X_add_number
|= 1;
9055 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9056 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9058 if (!inst
.operands
[1].present
)
9059 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9062 encode_arm_shifter_operand (2);
9068 if (inst
.operands
[0].present
)
9069 inst
.instruction
|= inst
.operands
[0].imm
;
9071 inst
.instruction
|= 0xf;
9077 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9078 constraint (msb
> 32, _("bit-field extends past end of register"));
9079 /* The instruction encoding stores the LSB and MSB,
9080 not the LSB and width. */
9081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9082 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9083 inst
.instruction
|= (msb
- 1) << 16;
9091 /* #0 in second position is alternative syntax for bfc, which is
9092 the same instruction but with REG_PC in the Rm field. */
9093 if (!inst
.operands
[1].isreg
)
9094 inst
.operands
[1].reg
= REG_PC
;
9096 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9097 constraint (msb
> 32, _("bit-field extends past end of register"));
9098 /* The instruction encoding stores the LSB and MSB,
9099 not the LSB and width. */
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].reg
;
9102 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9103 inst
.instruction
|= (msb
- 1) << 16;
9109 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9110 _("bit-field extends past end of register"));
9111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9112 inst
.instruction
|= inst
.operands
[1].reg
;
9113 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9114 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9117 /* ARM V5 breakpoint instruction (argument parse)
9118 BKPT <16 bit unsigned immediate>
9119 Instruction is not conditional.
9120 The bit pattern given in insns[] has the COND_ALWAYS condition,
9121 and it is an error if the caller tried to override that. */
9126 /* Top 12 of 16 bits to bits 19:8. */
9127 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9129 /* Bottom 4 of 16 bits to bits 3:0. */
9130 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9134 encode_branch (int default_reloc
)
9136 if (inst
.operands
[0].hasreloc
)
9138 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9139 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9140 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9141 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9142 ? BFD_RELOC_ARM_PLT32
9143 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9146 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9147 inst
.relocs
[0].pc_rel
= 1;
9154 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9155 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9158 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9165 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9167 if (inst
.cond
== COND_ALWAYS
)
9168 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9170 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9174 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9177 /* ARM V5 branch-link-exchange instruction (argument parse)
9178 BLX <target_addr> ie BLX(1)
9179 BLX{<condition>} <Rm> ie BLX(2)
9180 Unfortunately, there are two different opcodes for this mnemonic.
9181 So, the insns[].value is not used, and the code here zaps values
9182 into inst.instruction.
9183 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9188 if (inst
.operands
[0].isreg
)
9190 /* Arg is a register; the opcode provided by insns[] is correct.
9191 It is not illegal to do "blx pc", just useless. */
9192 if (inst
.operands
[0].reg
== REG_PC
)
9193 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9195 inst
.instruction
|= inst
.operands
[0].reg
;
9199 /* Arg is an address; this instruction cannot be executed
9200 conditionally, and the opcode must be adjusted.
9201 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9202 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9203 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9204 inst
.instruction
= 0xfa000000;
9205 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9212 bfd_boolean want_reloc
;
9214 if (inst
.operands
[0].reg
== REG_PC
)
9215 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9217 inst
.instruction
|= inst
.operands
[0].reg
;
9218 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9219 it is for ARMv4t or earlier. */
9220 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9221 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9222 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9226 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9231 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9235 /* ARM v5TEJ. Jump to Jazelle code. */
9240 if (inst
.operands
[0].reg
== REG_PC
)
9241 as_tsktsk (_("use of r15 in bxj is not really useful"));
9243 inst
.instruction
|= inst
.operands
[0].reg
;
9246 /* Co-processor data operation:
9247 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9248 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9252 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9253 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9254 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9255 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9256 inst
.instruction
|= inst
.operands
[4].reg
;
9257 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9263 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9264 encode_arm_shifter_operand (1);
9267 /* Transfer between coprocessor and ARM registers.
9268 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9273 No special properties. */
9275 struct deprecated_coproc_regs_s
9282 arm_feature_set deprecated
;
9283 arm_feature_set obsoleted
;
9284 const char *dep_msg
;
9285 const char *obs_msg
;
9288 #define DEPR_ACCESS_V8 \
9289 N_("This coprocessor register access is deprecated in ARMv8")
9291 /* Table of all deprecated coprocessor registers. */
9292 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9294 {15, 0, 7, 10, 5, /* CP15DMB. */
9295 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9296 DEPR_ACCESS_V8
, NULL
},
9297 {15, 0, 7, 10, 4, /* CP15DSB. */
9298 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9299 DEPR_ACCESS_V8
, NULL
},
9300 {15, 0, 7, 5, 4, /* CP15ISB. */
9301 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9302 DEPR_ACCESS_V8
, NULL
},
9303 {14, 6, 1, 0, 0, /* TEEHBR. */
9304 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9305 DEPR_ACCESS_V8
, NULL
},
9306 {14, 6, 0, 0, 0, /* TEECR. */
9307 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9308 DEPR_ACCESS_V8
, NULL
},
9311 #undef DEPR_ACCESS_V8
9313 static const size_t deprecated_coproc_reg_count
=
9314 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9322 Rd
= inst
.operands
[2].reg
;
9325 if (inst
.instruction
== 0xee000010
9326 || inst
.instruction
== 0xfe000010)
9328 reject_bad_reg (Rd
);
9329 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9331 constraint (Rd
== REG_SP
, BAD_SP
);
9336 if (inst
.instruction
== 0xe000010)
9337 constraint (Rd
== REG_PC
, BAD_PC
);
9340 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9342 const struct deprecated_coproc_regs_s
*r
=
9343 deprecated_coproc_regs
+ i
;
9345 if (inst
.operands
[0].reg
== r
->cp
9346 && inst
.operands
[1].imm
== r
->opc1
9347 && inst
.operands
[3].reg
== r
->crn
9348 && inst
.operands
[4].reg
== r
->crm
9349 && inst
.operands
[5].imm
== r
->opc2
)
9351 if (! ARM_CPU_IS_ANY (cpu_variant
)
9352 && warn_on_deprecated
9353 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9354 as_tsktsk ("%s", r
->dep_msg
);
9358 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9359 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9360 inst
.instruction
|= Rd
<< 12;
9361 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9362 inst
.instruction
|= inst
.operands
[4].reg
;
9363 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9366 /* Transfer between coprocessor register and pair of ARM registers.
9367 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9372 Two XScale instructions are special cases of these:
9374 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9375 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9377 Result unpredictable if Rd or Rn is R15. */
9384 Rd
= inst
.operands
[2].reg
;
9385 Rn
= inst
.operands
[3].reg
;
9389 reject_bad_reg (Rd
);
9390 reject_bad_reg (Rn
);
9394 constraint (Rd
== REG_PC
, BAD_PC
);
9395 constraint (Rn
== REG_PC
, BAD_PC
);
9398 /* Only check the MRRC{2} variants. */
9399 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9401 /* If Rd == Rn, error that the operation is
9402 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9403 constraint (Rd
== Rn
, BAD_OVERLAP
);
9406 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9407 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9408 inst
.instruction
|= Rd
<< 12;
9409 inst
.instruction
|= Rn
<< 16;
9410 inst
.instruction
|= inst
.operands
[4].reg
;
9416 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9417 if (inst
.operands
[1].present
)
9419 inst
.instruction
|= CPSI_MMOD
;
9420 inst
.instruction
|= inst
.operands
[1].imm
;
9427 inst
.instruction
|= inst
.operands
[0].imm
;
9433 unsigned Rd
, Rn
, Rm
;
9435 Rd
= inst
.operands
[0].reg
;
9436 Rn
= (inst
.operands
[1].present
9437 ? inst
.operands
[1].reg
: Rd
);
9438 Rm
= inst
.operands
[2].reg
;
9440 constraint ((Rd
== REG_PC
), BAD_PC
);
9441 constraint ((Rn
== REG_PC
), BAD_PC
);
9442 constraint ((Rm
== REG_PC
), BAD_PC
);
9444 inst
.instruction
|= Rd
<< 16;
9445 inst
.instruction
|= Rn
<< 0;
9446 inst
.instruction
|= Rm
<< 8;
9452 /* There is no IT instruction in ARM mode. We
9453 process it to do the validation as if in
9454 thumb mode, just in case the code gets
9455 assembled for thumb using the unified syntax. */
9460 set_pred_insn_type (IT_INSN
);
9461 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9462 now_pred
.cc
= inst
.operands
[0].imm
;
9466 /* If there is only one register in the register list,
9467 then return its register number. Otherwise return -1. */
9469 only_one_reg_in_list (int range
)
9471 int i
= ffs (range
) - 1;
9472 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9476 encode_ldmstm(int from_push_pop_mnem
)
9478 int base_reg
= inst
.operands
[0].reg
;
9479 int range
= inst
.operands
[1].imm
;
9482 inst
.instruction
|= base_reg
<< 16;
9483 inst
.instruction
|= range
;
9485 if (inst
.operands
[1].writeback
)
9486 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9488 if (inst
.operands
[0].writeback
)
9490 inst
.instruction
|= WRITE_BACK
;
9491 /* Check for unpredictable uses of writeback. */
9492 if (inst
.instruction
& LOAD_BIT
)
9494 /* Not allowed in LDM type 2. */
9495 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9496 && ((range
& (1 << REG_PC
)) == 0))
9497 as_warn (_("writeback of base register is UNPREDICTABLE"));
9498 /* Only allowed if base reg not in list for other types. */
9499 else if (range
& (1 << base_reg
))
9500 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9504 /* Not allowed for type 2. */
9505 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9506 as_warn (_("writeback of base register is UNPREDICTABLE"));
9507 /* Only allowed if base reg not in list, or first in list. */
9508 else if ((range
& (1 << base_reg
))
9509 && (range
& ((1 << base_reg
) - 1)))
9510 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9514 /* If PUSH/POP has only one register, then use the A2 encoding. */
9515 one_reg
= only_one_reg_in_list (range
);
9516 if (from_push_pop_mnem
&& one_reg
>= 0)
9518 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9520 if (is_push
&& one_reg
== 13 /* SP */)
9521 /* PR 22483: The A2 encoding cannot be used when
9522 pushing the stack pointer as this is UNPREDICTABLE. */
9525 inst
.instruction
&= A_COND_MASK
;
9526 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9527 inst
.instruction
|= one_reg
<< 12;
9534 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9537 /* ARMv5TE load-consecutive (argument parse)
9546 constraint (inst
.operands
[0].reg
% 2 != 0,
9547 _("first transfer register must be even"));
9548 constraint (inst
.operands
[1].present
9549 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9550 _("can only transfer two consecutive registers"));
9551 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9552 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9554 if (!inst
.operands
[1].present
)
9555 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9557 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9558 register and the first register written; we have to diagnose
9559 overlap between the base and the second register written here. */
9561 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9562 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9563 as_warn (_("base register written back, and overlaps "
9564 "second transfer register"));
9566 if (!(inst
.instruction
& V4_STR_BIT
))
9568 /* For an index-register load, the index register must not overlap the
9569 destination (even if not write-back). */
9570 if (inst
.operands
[2].immisreg
9571 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9572 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9573 as_warn (_("index register overlaps transfer register"));
9575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9576 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9582 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9583 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9584 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9585 || inst
.operands
[1].negative
9586 /* This can arise if the programmer has written
9588 or if they have mistakenly used a register name as the last
9591 It is very difficult to distinguish between these two cases
9592 because "rX" might actually be a label. ie the register
9593 name has been occluded by a symbol of the same name. So we
9594 just generate a general 'bad addressing mode' type error
9595 message and leave it up to the programmer to discover the
9596 true cause and fix their mistake. */
9597 || (inst
.operands
[1].reg
== REG_PC
),
9600 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9601 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9602 _("offset must be zero in ARM encoding"));
9604 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9608 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9614 constraint (inst
.operands
[0].reg
% 2 != 0,
9615 _("even register required"));
9616 constraint (inst
.operands
[1].present
9617 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9618 _("can only load two consecutive registers"));
9619 /* If op 1 were present and equal to PC, this function wouldn't
9620 have been called in the first place. */
9621 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9624 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9627 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9628 which is not a multiple of four is UNPREDICTABLE. */
9630 check_ldr_r15_aligned (void)
9632 constraint (!(inst
.operands
[1].immisreg
)
9633 && (inst
.operands
[0].reg
== REG_PC
9634 && inst
.operands
[1].reg
== REG_PC
9635 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9636 _("ldr to register 15 must be 4-byte aligned"));
9642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9643 if (!inst
.operands
[1].isreg
)
9644 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9646 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9647 check_ldr_r15_aligned ();
9653 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9655 if (inst
.operands
[1].preind
)
9657 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9658 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9659 _("this instruction requires a post-indexed address"));
9661 inst
.operands
[1].preind
= 0;
9662 inst
.operands
[1].postind
= 1;
9663 inst
.operands
[1].writeback
= 1;
9665 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9666 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9669 /* Halfword and signed-byte load/store operations. */
9674 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9676 if (!inst
.operands
[1].isreg
)
9677 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9679 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9685 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9687 if (inst
.operands
[1].preind
)
9689 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9690 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9691 _("this instruction requires a post-indexed address"));
9693 inst
.operands
[1].preind
= 0;
9694 inst
.operands
[1].postind
= 1;
9695 inst
.operands
[1].writeback
= 1;
9697 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9698 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9701 /* Co-processor register load/store.
9702 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9706 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9707 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9708 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9714 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9715 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9716 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9717 && !(inst
.instruction
& 0x00400000))
9718 as_tsktsk (_("Rd and Rm should be different in mla"));
9720 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9721 inst
.instruction
|= inst
.operands
[1].reg
;
9722 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9723 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9729 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9730 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9733 encode_arm_shifter_operand (1);
9736 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9743 top
= (inst
.instruction
& 0x00400000) != 0;
9744 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9745 _(":lower16: not allowed in this instruction"));
9746 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9747 _(":upper16: not allowed in this instruction"));
9748 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9749 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9751 imm
= inst
.relocs
[0].exp
.X_add_number
;
9752 /* The value is in two pieces: 0:11, 16:19. */
9753 inst
.instruction
|= (imm
& 0x00000fff);
9754 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9759 do_vfp_nsyn_mrs (void)
9761 if (inst
.operands
[0].isvec
)
9763 if (inst
.operands
[1].reg
!= 1)
9764 first_error (_("operand 1 must be FPSCR"));
9765 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9766 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9767 do_vfp_nsyn_opcode ("fmstat");
9769 else if (inst
.operands
[1].isvec
)
9770 do_vfp_nsyn_opcode ("fmrx");
9778 do_vfp_nsyn_msr (void)
9780 if (inst
.operands
[0].isvec
)
9781 do_vfp_nsyn_opcode ("fmxr");
9791 unsigned Rt
= inst
.operands
[0].reg
;
9793 if (thumb_mode
&& Rt
== REG_SP
)
9795 inst
.error
= BAD_SP
;
9799 /* MVFR2 is only valid at ARMv8-A. */
9800 if (inst
.operands
[1].reg
== 5)
9801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9804 /* APSR_ sets isvec. All other refs to PC are illegal. */
9805 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9807 inst
.error
= BAD_PC
;
9811 /* If we get through parsing the register name, we just insert the number
9812 generated into the instruction without further validation. */
9813 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9814 inst
.instruction
|= (Rt
<< 12);
9820 unsigned Rt
= inst
.operands
[1].reg
;
9823 reject_bad_reg (Rt
);
9824 else if (Rt
== REG_PC
)
9826 inst
.error
= BAD_PC
;
9830 /* MVFR2 is only valid for ARMv8-A. */
9831 if (inst
.operands
[0].reg
== 5)
9832 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9835 /* If we get through parsing the register name, we just insert the number
9836 generated into the instruction without further validation. */
9837 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9838 inst
.instruction
|= (Rt
<< 12);
9846 if (do_vfp_nsyn_mrs () == SUCCESS
)
9849 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9852 if (inst
.operands
[1].isreg
)
9854 br
= inst
.operands
[1].reg
;
9855 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9856 as_bad (_("bad register for mrs"));
9860 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9861 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9863 _("'APSR', 'CPSR' or 'SPSR' expected"));
9864 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9867 inst
.instruction
|= br
;
9870 /* Two possible forms:
9871 "{C|S}PSR_<field>, Rm",
9872 "{C|S}PSR_f, #expression". */
9877 if (do_vfp_nsyn_msr () == SUCCESS
)
9880 inst
.instruction
|= inst
.operands
[0].imm
;
9881 if (inst
.operands
[1].isreg
)
9882 inst
.instruction
|= inst
.operands
[1].reg
;
9885 inst
.instruction
|= INST_IMMEDIATE
;
9886 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9887 inst
.relocs
[0].pc_rel
= 0;
9894 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9896 if (!inst
.operands
[2].present
)
9897 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9898 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9899 inst
.instruction
|= inst
.operands
[1].reg
;
9900 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9902 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9903 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9904 as_tsktsk (_("Rd and Rm should be different in mul"));
9907 /* Long Multiply Parser
9908 UMULL RdLo, RdHi, Rm, Rs
9909 SMULL RdLo, RdHi, Rm, Rs
9910 UMLAL RdLo, RdHi, Rm, Rs
9911 SMLAL RdLo, RdHi, Rm, Rs. */
9916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9918 inst
.instruction
|= inst
.operands
[2].reg
;
9919 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9921 /* rdhi and rdlo must be different. */
9922 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9923 as_tsktsk (_("rdhi and rdlo must be different"));
9925 /* rdhi, rdlo and rm must all be different before armv6. */
9926 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9927 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9928 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9929 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9935 if (inst
.operands
[0].present
9936 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9938 /* Architectural NOP hints are CPSR sets with no bits selected. */
9939 inst
.instruction
&= 0xf0000000;
9940 inst
.instruction
|= 0x0320f000;
9941 if (inst
.operands
[0].present
)
9942 inst
.instruction
|= inst
.operands
[0].imm
;
9946 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9947 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9948 Condition defaults to COND_ALWAYS.
9949 Error if Rd, Rn or Rm are R15. */
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9956 inst
.instruction
|= inst
.operands
[2].reg
;
9957 if (inst
.operands
[3].present
)
9958 encode_arm_shift (3);
9961 /* ARM V6 PKHTB (Argument Parse). */
9966 if (!inst
.operands
[3].present
)
9968 /* If the shift specifier is omitted, turn the instruction
9969 into pkhbt rd, rm, rn. */
9970 inst
.instruction
&= 0xfff00010;
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9972 inst
.instruction
|= inst
.operands
[1].reg
;
9973 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9978 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9979 inst
.instruction
|= inst
.operands
[2].reg
;
9980 encode_arm_shift (3);
9984 /* ARMv5TE: Preload-Cache
9985 MP Extensions: Preload for write
9989 Syntactically, like LDR with B=1, W=0, L=1. */
9994 constraint (!inst
.operands
[0].isreg
,
9995 _("'[' expected after PLD mnemonic"));
9996 constraint (inst
.operands
[0].postind
,
9997 _("post-indexed expression used in preload instruction"));
9998 constraint (inst
.operands
[0].writeback
,
9999 _("writeback used in preload instruction"));
10000 constraint (!inst
.operands
[0].preind
,
10001 _("unindexed addressing used in preload instruction"));
10002 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10005 /* ARMv7: PLI <addr_mode> */
10009 constraint (!inst
.operands
[0].isreg
,
10010 _("'[' expected after PLI mnemonic"));
10011 constraint (inst
.operands
[0].postind
,
10012 _("post-indexed expression used in preload instruction"));
10013 constraint (inst
.operands
[0].writeback
,
10014 _("writeback used in preload instruction"));
10015 constraint (!inst
.operands
[0].preind
,
10016 _("unindexed addressing used in preload instruction"));
10017 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10018 inst
.instruction
&= ~PRE_INDEX
;
10024 constraint (inst
.operands
[0].writeback
,
10025 _("push/pop do not support {reglist}^"));
10026 inst
.operands
[1] = inst
.operands
[0];
10027 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10028 inst
.operands
[0].isreg
= 1;
10029 inst
.operands
[0].writeback
= 1;
10030 inst
.operands
[0].reg
= REG_SP
;
10031 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10034 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10035 word at the specified address and the following word
10037 Unconditionally executed.
10038 Error if Rn is R15. */
10043 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10044 if (inst
.operands
[0].writeback
)
10045 inst
.instruction
|= WRITE_BACK
;
10048 /* ARM V6 ssat (argument parse). */
10053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10055 inst
.instruction
|= inst
.operands
[2].reg
;
10057 if (inst
.operands
[3].present
)
10058 encode_arm_shift (3);
10061 /* ARM V6 usat (argument parse). */
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10067 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10068 inst
.instruction
|= inst
.operands
[2].reg
;
10070 if (inst
.operands
[3].present
)
10071 encode_arm_shift (3);
10074 /* ARM V6 ssat16 (argument parse). */
10079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10080 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10081 inst
.instruction
|= inst
.operands
[2].reg
;
10087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10088 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10089 inst
.instruction
|= inst
.operands
[2].reg
;
10092 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10093 preserving the other bits.
10095 setend <endian_specifier>, where <endian_specifier> is either
10101 if (warn_on_deprecated
10102 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10103 as_tsktsk (_("setend use is deprecated for ARMv8"));
10105 if (inst
.operands
[0].imm
)
10106 inst
.instruction
|= 0x200;
10112 unsigned int Rm
= (inst
.operands
[1].present
10113 ? inst
.operands
[1].reg
10114 : inst
.operands
[0].reg
);
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= Rm
;
10118 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10120 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10121 inst
.instruction
|= SHIFT_BY_REG
;
10122 /* PR 12854: Error on extraneous shifts. */
10123 constraint (inst
.operands
[2].shifted
,
10124 _("extraneous shift as part of operand to shift insn"));
10127 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10133 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10134 inst
.relocs
[0].pc_rel
= 0;
10140 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10141 inst
.relocs
[0].pc_rel
= 0;
10147 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10148 inst
.relocs
[0].pc_rel
= 0;
10154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10155 _("selected processor does not support SETPAN instruction"));
10157 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10164 _("selected processor does not support SETPAN instruction"));
10166 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10169 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10170 SMLAxy{cond} Rd,Rm,Rs,Rn
10171 SMLAWy{cond} Rd,Rm,Rs,Rn
10172 Error if any register is R15. */
10177 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10178 inst
.instruction
|= inst
.operands
[1].reg
;
10179 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10180 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10183 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10184 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10185 Error if any register is R15.
10186 Warning if Rdlo == Rdhi. */
10191 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10192 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10193 inst
.instruction
|= inst
.operands
[2].reg
;
10194 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10196 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10197 as_tsktsk (_("rdhi and rdlo must be different"));
10200 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10201 SMULxy{cond} Rd,Rm,Rs
10202 Error if any register is R15. */
10207 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10208 inst
.instruction
|= inst
.operands
[1].reg
;
10209 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10212 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10213 the same for both ARM and Thumb-2. */
10220 if (inst
.operands
[0].present
)
10222 reg
= inst
.operands
[0].reg
;
10223 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10228 inst
.instruction
|= reg
<< 16;
10229 inst
.instruction
|= inst
.operands
[1].imm
;
10230 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10231 inst
.instruction
|= WRITE_BACK
;
10234 /* ARM V6 strex (argument parse). */
10239 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10240 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10241 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10242 || inst
.operands
[2].negative
10243 /* See comment in do_ldrex(). */
10244 || (inst
.operands
[2].reg
== REG_PC
),
10247 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10248 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10250 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10251 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10252 _("offset must be zero in ARM encoding"));
10254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10255 inst
.instruction
|= inst
.operands
[1].reg
;
10256 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10257 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10261 do_t_strexbh (void)
10263 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10264 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10265 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10266 || inst
.operands
[2].negative
,
10269 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10270 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10278 constraint (inst
.operands
[1].reg
% 2 != 0,
10279 _("even register required"));
10280 constraint (inst
.operands
[2].present
10281 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10282 _("can only store two consecutive registers"));
10283 /* If op 2 were present and equal to PC, this function wouldn't
10284 have been called in the first place. */
10285 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10287 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10288 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10289 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10293 inst
.instruction
|= inst
.operands
[1].reg
;
10294 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10301 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10302 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10310 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10311 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10316 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10317 extends it to 32-bits, and adds the result to a value in another
10318 register. You can specify a rotation by 0, 8, 16, or 24 bits
10319 before extracting the 16-bit value.
10320 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10321 Condition defaults to COND_ALWAYS.
10322 Error if any register uses R15. */
10327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10328 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10329 inst
.instruction
|= inst
.operands
[2].reg
;
10330 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10335 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10336 Condition defaults to COND_ALWAYS.
10337 Error if any register uses R15. */
10342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10343 inst
.instruction
|= inst
.operands
[1].reg
;
10344 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10347 /* VFP instructions. In a logical order: SP variant first, monad
10348 before dyad, arithmetic then move then load/store. */
10351 do_vfp_sp_monadic (void)
10353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10354 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10357 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10358 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10362 do_vfp_sp_dyadic (void)
10364 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10365 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10366 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10370 do_vfp_sp_compare_z (void)
10372 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10376 do_vfp_dp_sp_cvt (void)
10378 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10379 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10383 do_vfp_sp_dp_cvt (void)
10385 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10386 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10390 do_vfp_reg_from_sp (void)
10392 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10393 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10397 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10401 do_vfp_reg2_from_sp2 (void)
10403 constraint (inst
.operands
[2].imm
!= 2,
10404 _("only two consecutive VFP SP registers allowed here"));
10405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10406 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10407 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10411 do_vfp_sp_from_reg (void)
10413 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10414 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10417 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10418 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10422 do_vfp_sp2_from_reg2 (void)
10424 constraint (inst
.operands
[0].imm
!= 2,
10425 _("only two consecutive VFP SP registers allowed here"));
10426 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10427 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10428 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10432 do_vfp_sp_ldst (void)
10434 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10435 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10439 do_vfp_dp_ldst (void)
10441 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10442 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10447 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10449 if (inst
.operands
[0].writeback
)
10450 inst
.instruction
|= WRITE_BACK
;
10452 constraint (ldstm_type
!= VFP_LDSTMIA
,
10453 _("this addressing mode requires base-register writeback"));
10454 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10455 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10456 inst
.instruction
|= inst
.operands
[1].imm
;
10460 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10464 if (inst
.operands
[0].writeback
)
10465 inst
.instruction
|= WRITE_BACK
;
10467 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10468 _("this addressing mode requires base-register writeback"));
10470 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10471 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10473 count
= inst
.operands
[1].imm
<< 1;
10474 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10477 inst
.instruction
|= count
;
10481 do_vfp_sp_ldstmia (void)
10483 vfp_sp_ldstm (VFP_LDSTMIA
);
10487 do_vfp_sp_ldstmdb (void)
10489 vfp_sp_ldstm (VFP_LDSTMDB
);
10493 do_vfp_dp_ldstmia (void)
10495 vfp_dp_ldstm (VFP_LDSTMIA
);
10499 do_vfp_dp_ldstmdb (void)
10501 vfp_dp_ldstm (VFP_LDSTMDB
);
10505 do_vfp_xp_ldstmia (void)
10507 vfp_dp_ldstm (VFP_LDSTMIAX
);
10511 do_vfp_xp_ldstmdb (void)
10513 vfp_dp_ldstm (VFP_LDSTMDBX
);
10517 do_vfp_dp_rd_rm (void)
10519 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10520 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10523 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10524 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10528 do_vfp_dp_rn_rd (void)
10530 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10531 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10535 do_vfp_dp_rd_rn (void)
10537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10538 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10542 do_vfp_dp_rd_rn_rm (void)
10544 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10545 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10549 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10550 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10554 do_vfp_dp_rd (void)
10556 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10560 do_vfp_dp_rm_rd_rn (void)
10562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10563 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10566 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10567 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10568 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10571 /* VFPv3 instructions. */
10573 do_vfp_sp_const (void)
10575 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10576 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10577 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10581 do_vfp_dp_const (void)
10583 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10584 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10585 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10589 vfp_conv (int srcsize
)
10591 int immbits
= srcsize
- inst
.operands
[1].imm
;
10593 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10595 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10596 i.e. immbits must be in range 0 - 16. */
10597 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10600 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10602 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10603 i.e. immbits must be in range 0 - 31. */
10604 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10608 inst
.instruction
|= (immbits
& 1) << 5;
10609 inst
.instruction
|= (immbits
>> 1);
10613 do_vfp_sp_conv_16 (void)
10615 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10620 do_vfp_dp_conv_16 (void)
10622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10627 do_vfp_sp_conv_32 (void)
10629 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10634 do_vfp_dp_conv_32 (void)
10636 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10640 /* FPA instructions. Also in a logical order. */
10645 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10646 inst
.instruction
|= inst
.operands
[1].reg
;
10650 do_fpa_ldmstm (void)
10652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10653 switch (inst
.operands
[1].imm
)
10655 case 1: inst
.instruction
|= CP_T_X
; break;
10656 case 2: inst
.instruction
|= CP_T_Y
; break;
10657 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10662 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10664 /* The instruction specified "ea" or "fd", so we can only accept
10665 [Rn]{!}. The instruction does not really support stacking or
10666 unstacking, so we have to emulate these by setting appropriate
10667 bits and offsets. */
10668 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10669 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10670 _("this instruction does not support indexing"));
10672 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10673 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10675 if (!(inst
.instruction
& INDEX_UP
))
10676 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10678 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10680 inst
.operands
[2].preind
= 0;
10681 inst
.operands
[2].postind
= 1;
10685 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10688 /* iWMMXt instructions: strictly in alphabetical order. */
10691 do_iwmmxt_tandorc (void)
10693 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10697 do_iwmmxt_textrc (void)
10699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10700 inst
.instruction
|= inst
.operands
[1].imm
;
10704 do_iwmmxt_textrm (void)
10706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10707 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10708 inst
.instruction
|= inst
.operands
[2].imm
;
10712 do_iwmmxt_tinsr (void)
10714 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10715 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10716 inst
.instruction
|= inst
.operands
[2].imm
;
10720 do_iwmmxt_tmia (void)
10722 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10723 inst
.instruction
|= inst
.operands
[1].reg
;
10724 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10728 do_iwmmxt_waligni (void)
10730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10732 inst
.instruction
|= inst
.operands
[2].reg
;
10733 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10737 do_iwmmxt_wmerge (void)
10739 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10740 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10741 inst
.instruction
|= inst
.operands
[2].reg
;
10742 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10746 do_iwmmxt_wmov (void)
10748 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10750 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10751 inst
.instruction
|= inst
.operands
[1].reg
;
10755 do_iwmmxt_wldstbh (void)
10758 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10760 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10762 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10763 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10767 do_iwmmxt_wldstw (void)
10769 /* RIWR_RIWC clears .isreg for a control register. */
10770 if (!inst
.operands
[0].isreg
)
10772 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10773 inst
.instruction
|= 0xf0000000;
10776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10777 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10781 do_iwmmxt_wldstd (void)
10783 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10784 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10785 && inst
.operands
[1].immisreg
)
10787 inst
.instruction
&= ~0x1a000ff;
10788 inst
.instruction
|= (0xfU
<< 28);
10789 if (inst
.operands
[1].preind
)
10790 inst
.instruction
|= PRE_INDEX
;
10791 if (!inst
.operands
[1].negative
)
10792 inst
.instruction
|= INDEX_UP
;
10793 if (inst
.operands
[1].writeback
)
10794 inst
.instruction
|= WRITE_BACK
;
10795 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10796 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10797 inst
.instruction
|= inst
.operands
[1].imm
;
10800 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10804 do_iwmmxt_wshufh (void)
10806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10807 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10808 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10809 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10813 do_iwmmxt_wzero (void)
10815 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10816 inst
.instruction
|= inst
.operands
[0].reg
;
10817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10818 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10822 do_iwmmxt_wrwrwr_or_imm5 (void)
10824 if (inst
.operands
[2].isreg
)
10827 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10828 _("immediate operand requires iWMMXt2"));
10830 if (inst
.operands
[2].imm
== 0)
10832 switch ((inst
.instruction
>> 20) & 0xf)
10838 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10839 inst
.operands
[2].imm
= 16;
10840 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10846 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10847 inst
.operands
[2].imm
= 32;
10848 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10855 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10857 wrn
= (inst
.instruction
>> 16) & 0xf;
10858 inst
.instruction
&= 0xff0fff0f;
10859 inst
.instruction
|= wrn
;
10860 /* Bail out here; the instruction is now assembled. */
10865 /* Map 32 -> 0, etc. */
10866 inst
.operands
[2].imm
&= 0x1f;
10867 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10871 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10872 operations first, then control, shift, and load/store. */
10874 /* Insns like "foo X,Y,Z". */
10877 do_mav_triple (void)
10879 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10880 inst
.instruction
|= inst
.operands
[1].reg
;
10881 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10884 /* Insns like "foo W,X,Y,Z".
10885 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10890 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10891 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10892 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10893 inst
.instruction
|= inst
.operands
[3].reg
;
10896 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10898 do_mav_dspsc (void)
10900 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10903 /* Maverick shift immediate instructions.
10904 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10905 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10908 do_mav_shift (void)
10910 int imm
= inst
.operands
[2].imm
;
10912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10913 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10915 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10916 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10917 Bit 4 should be 0. */
10918 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10920 inst
.instruction
|= imm
;
10923 /* XScale instructions. Also sorted arithmetic before move. */
10925 /* Xscale multiply-accumulate (argument parse)
10928 MIAxycc acc0,Rm,Rs. */
10933 inst
.instruction
|= inst
.operands
[1].reg
;
10934 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10937 /* Xscale move-accumulator-register (argument parse)
10939 MARcc acc0,RdLo,RdHi. */
10944 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10945 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10948 /* Xscale move-register-accumulator (argument parse)
10950 MRAcc RdLo,RdHi,acc0. */
10955 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10960 /* Encoding functions relevant only to Thumb. */
10962 /* inst.operands[i] is a shifted-register operand; encode
10963 it into inst.instruction in the format used by Thumb32. */
10966 encode_thumb32_shifted_operand (int i
)
10968 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10969 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10971 constraint (inst
.operands
[i
].immisreg
,
10972 _("shift by register not allowed in thumb mode"));
10973 inst
.instruction
|= inst
.operands
[i
].reg
;
10974 if (shift
== SHIFT_RRX
)
10975 inst
.instruction
|= SHIFT_ROR
<< 4;
10978 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10979 _("expression too complex"));
10981 constraint (value
> 32
10982 || (value
== 32 && (shift
== SHIFT_LSL
10983 || shift
== SHIFT_ROR
)),
10984 _("shift expression is too large"));
10988 else if (value
== 32)
10991 inst
.instruction
|= shift
<< 4;
10992 inst
.instruction
|= (value
& 0x1c) << 10;
10993 inst
.instruction
|= (value
& 0x03) << 6;
10998 /* inst.operands[i] was set up by parse_address. Encode it into a
10999 Thumb32 format load or store instruction. Reject forms that cannot
11000 be used with such instructions. If is_t is true, reject forms that
11001 cannot be used with a T instruction; if is_d is true, reject forms
11002 that cannot be used with a D instruction. If it is a store insn,
11003 reject PC in Rn. */
11006 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11008 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11010 constraint (!inst
.operands
[i
].isreg
,
11011 _("Instruction does not support =N addresses"));
11013 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11014 if (inst
.operands
[i
].immisreg
)
11016 constraint (is_pc
, BAD_PC_ADDRESSING
);
11017 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11018 constraint (inst
.operands
[i
].negative
,
11019 _("Thumb does not support negative register indexing"));
11020 constraint (inst
.operands
[i
].postind
,
11021 _("Thumb does not support register post-indexing"));
11022 constraint (inst
.operands
[i
].writeback
,
11023 _("Thumb does not support register indexing with writeback"));
11024 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11025 _("Thumb supports only LSL in shifted register indexing"));
11027 inst
.instruction
|= inst
.operands
[i
].imm
;
11028 if (inst
.operands
[i
].shifted
)
11030 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11031 _("expression too complex"));
11032 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11033 || inst
.relocs
[0].exp
.X_add_number
> 3,
11034 _("shift out of range"));
11035 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11037 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11039 else if (inst
.operands
[i
].preind
)
11041 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11042 constraint (is_t
&& inst
.operands
[i
].writeback
,
11043 _("cannot use writeback with this instruction"));
11044 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11045 BAD_PC_ADDRESSING
);
11049 inst
.instruction
|= 0x01000000;
11050 if (inst
.operands
[i
].writeback
)
11051 inst
.instruction
|= 0x00200000;
11055 inst
.instruction
|= 0x00000c00;
11056 if (inst
.operands
[i
].writeback
)
11057 inst
.instruction
|= 0x00000100;
11059 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11061 else if (inst
.operands
[i
].postind
)
11063 gas_assert (inst
.operands
[i
].writeback
);
11064 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11065 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11068 inst
.instruction
|= 0x00200000;
11070 inst
.instruction
|= 0x00000900;
11071 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11073 else /* unindexed - only for coprocessor */
11074 inst
.error
= _("instruction does not accept unindexed addressing");
11077 /* Table of Thumb instructions which exist in both 16- and 32-bit
11078 encodings (the latter only in post-V6T2 cores). The index is the
11079 value used in the insns table below. When there is more than one
11080 possible 16-bit encoding for the instruction, this table always
11082 Also contains several pseudo-instructions used during relaxation. */
11083 #define T16_32_TAB \
11084 X(_adc, 4140, eb400000), \
11085 X(_adcs, 4140, eb500000), \
11086 X(_add, 1c00, eb000000), \
11087 X(_adds, 1c00, eb100000), \
11088 X(_addi, 0000, f1000000), \
11089 X(_addis, 0000, f1100000), \
11090 X(_add_pc,000f, f20f0000), \
11091 X(_add_sp,000d, f10d0000), \
11092 X(_adr, 000f, f20f0000), \
11093 X(_and, 4000, ea000000), \
11094 X(_ands, 4000, ea100000), \
11095 X(_asr, 1000, fa40f000), \
11096 X(_asrs, 1000, fa50f000), \
11097 X(_b, e000, f000b000), \
11098 X(_bcond, d000, f0008000), \
11099 X(_bf, 0000, f040e001), \
11100 X(_bfcsel,0000, f000e001), \
11101 X(_bfx, 0000, f060e001), \
11102 X(_bfl, 0000, f000c001), \
11103 X(_bflx, 0000, f070e001), \
11104 X(_bic, 4380, ea200000), \
11105 X(_bics, 4380, ea300000), \
11106 X(_cmn, 42c0, eb100f00), \
11107 X(_cmp, 2800, ebb00f00), \
11108 X(_cpsie, b660, f3af8400), \
11109 X(_cpsid, b670, f3af8600), \
11110 X(_cpy, 4600, ea4f0000), \
11111 X(_dec_sp,80dd, f1ad0d00), \
11112 X(_dls, 0000, f040e001), \
11113 X(_eor, 4040, ea800000), \
11114 X(_eors, 4040, ea900000), \
11115 X(_inc_sp,00dd, f10d0d00), \
11116 X(_ldmia, c800, e8900000), \
11117 X(_ldr, 6800, f8500000), \
11118 X(_ldrb, 7800, f8100000), \
11119 X(_ldrh, 8800, f8300000), \
11120 X(_ldrsb, 5600, f9100000), \
11121 X(_ldrsh, 5e00, f9300000), \
11122 X(_ldr_pc,4800, f85f0000), \
11123 X(_ldr_pc2,4800, f85f0000), \
11124 X(_ldr_sp,9800, f85d0000), \
11125 X(_le, 0000, f00fc001), \
11126 X(_lsl, 0000, fa00f000), \
11127 X(_lsls, 0000, fa10f000), \
11128 X(_lsr, 0800, fa20f000), \
11129 X(_lsrs, 0800, fa30f000), \
11130 X(_mov, 2000, ea4f0000), \
11131 X(_movs, 2000, ea5f0000), \
11132 X(_mul, 4340, fb00f000), \
11133 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11134 X(_mvn, 43c0, ea6f0000), \
11135 X(_mvns, 43c0, ea7f0000), \
11136 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11137 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11138 X(_orr, 4300, ea400000), \
11139 X(_orrs, 4300, ea500000), \
11140 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11141 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11142 X(_rev, ba00, fa90f080), \
11143 X(_rev16, ba40, fa90f090), \
11144 X(_revsh, bac0, fa90f0b0), \
11145 X(_ror, 41c0, fa60f000), \
11146 X(_rors, 41c0, fa70f000), \
11147 X(_sbc, 4180, eb600000), \
11148 X(_sbcs, 4180, eb700000), \
11149 X(_stmia, c000, e8800000), \
11150 X(_str, 6000, f8400000), \
11151 X(_strb, 7000, f8000000), \
11152 X(_strh, 8000, f8200000), \
11153 X(_str_sp,9000, f84d0000), \
11154 X(_sub, 1e00, eba00000), \
11155 X(_subs, 1e00, ebb00000), \
11156 X(_subi, 8000, f1a00000), \
11157 X(_subis, 8000, f1b00000), \
11158 X(_sxtb, b240, fa4ff080), \
11159 X(_sxth, b200, fa0ff080), \
11160 X(_tst, 4200, ea100f00), \
11161 X(_uxtb, b2c0, fa5ff080), \
11162 X(_uxth, b280, fa1ff080), \
11163 X(_nop, bf00, f3af8000), \
11164 X(_yield, bf10, f3af8001), \
11165 X(_wfe, bf20, f3af8002), \
11166 X(_wfi, bf30, f3af8003), \
11167 X(_wls, 0000, f040c001), \
11168 X(_sev, bf40, f3af8004), \
11169 X(_sevl, bf50, f3af8005), \
11170 X(_udf, de00, f7f0a000)
11172 /* To catch errors in encoding functions, the codes are all offset by
11173 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11174 as 16-bit instructions. */
11175 #define X(a,b,c) T_MNEM##a
11176 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11179 #define X(a,b,c) 0x##b
11180 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11181 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11184 #define X(a,b,c) 0x##c
11185 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11186 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11187 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11191 /* Thumb instruction encoders, in alphabetical order. */
11193 /* ADDW or SUBW. */
11196 do_t_add_sub_w (void)
11200 Rd
= inst
.operands
[0].reg
;
11201 Rn
= inst
.operands
[1].reg
;
11203 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11204 is the SP-{plus,minus}-immediate form of the instruction. */
11206 constraint (Rd
== REG_PC
, BAD_PC
);
11208 reject_bad_reg (Rd
);
11210 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11211 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11214 /* Parse an add or subtract instruction. We get here with inst.instruction
11215 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11218 do_t_add_sub (void)
11222 Rd
= inst
.operands
[0].reg
;
11223 Rs
= (inst
.operands
[1].present
11224 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11225 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11228 set_pred_insn_type_last ();
11230 if (unified_syntax
)
11233 bfd_boolean narrow
;
11236 flags
= (inst
.instruction
== T_MNEM_adds
11237 || inst
.instruction
== T_MNEM_subs
);
11239 narrow
= !in_pred_block ();
11241 narrow
= in_pred_block ();
11242 if (!inst
.operands
[2].isreg
)
11246 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11247 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11249 add
= (inst
.instruction
== T_MNEM_add
11250 || inst
.instruction
== T_MNEM_adds
);
11252 if (inst
.size_req
!= 4)
11254 /* Attempt to use a narrow opcode, with relaxation if
11256 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11257 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11258 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11259 opcode
= T_MNEM_add_sp
;
11260 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11261 opcode
= T_MNEM_add_pc
;
11262 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11265 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11267 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11271 inst
.instruction
= THUMB_OP16(opcode
);
11272 inst
.instruction
|= (Rd
<< 4) | Rs
;
11273 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11274 || (inst
.relocs
[0].type
11275 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11277 if (inst
.size_req
== 2)
11278 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11280 inst
.relax
= opcode
;
11284 constraint (inst
.size_req
== 2, BAD_HIREG
);
11286 if (inst
.size_req
== 4
11287 || (inst
.size_req
!= 2 && !opcode
))
11289 constraint ((inst
.relocs
[0].type
11290 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11291 && (inst
.relocs
[0].type
11292 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11293 THUMB1_RELOC_ONLY
);
11296 constraint (add
, BAD_PC
);
11297 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11298 _("only SUBS PC, LR, #const allowed"));
11299 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11300 _("expression too complex"));
11301 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11302 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11303 _("immediate value out of range"));
11304 inst
.instruction
= T2_SUBS_PC_LR
11305 | inst
.relocs
[0].exp
.X_add_number
;
11306 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11309 else if (Rs
== REG_PC
)
11311 /* Always use addw/subw. */
11312 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11313 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11317 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11318 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11321 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11323 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11325 inst
.instruction
|= Rd
<< 8;
11326 inst
.instruction
|= Rs
<< 16;
11331 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11332 unsigned int shift
= inst
.operands
[2].shift_kind
;
11334 Rn
= inst
.operands
[2].reg
;
11335 /* See if we can do this with a 16-bit instruction. */
11336 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11338 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11343 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11344 || inst
.instruction
== T_MNEM_add
)
11346 : T_OPCODE_SUB_R3
);
11347 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11351 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11353 /* Thumb-1 cores (except v6-M) require at least one high
11354 register in a narrow non flag setting add. */
11355 if (Rd
> 7 || Rn
> 7
11356 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11357 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11364 inst
.instruction
= T_OPCODE_ADD_HI
;
11365 inst
.instruction
|= (Rd
& 8) << 4;
11366 inst
.instruction
|= (Rd
& 7);
11367 inst
.instruction
|= Rn
<< 3;
11373 constraint (Rd
== REG_PC
, BAD_PC
);
11374 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11375 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11376 constraint (Rs
== REG_PC
, BAD_PC
);
11377 reject_bad_reg (Rn
);
11379 /* If we get here, it can't be done in 16 bits. */
11380 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11381 _("shift must be constant"));
11382 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11383 inst
.instruction
|= Rd
<< 8;
11384 inst
.instruction
|= Rs
<< 16;
11385 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11386 _("shift value over 3 not allowed in thumb mode"));
11387 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11388 _("only LSL shift allowed in thumb mode"));
11389 encode_thumb32_shifted_operand (2);
11394 constraint (inst
.instruction
== T_MNEM_adds
11395 || inst
.instruction
== T_MNEM_subs
,
11398 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11400 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11401 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11404 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11405 ? 0x0000 : 0x8000);
11406 inst
.instruction
|= (Rd
<< 4) | Rs
;
11407 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11411 Rn
= inst
.operands
[2].reg
;
11412 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11414 /* We now have Rd, Rs, and Rn set to registers. */
11415 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11417 /* Can't do this for SUB. */
11418 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11419 inst
.instruction
= T_OPCODE_ADD_HI
;
11420 inst
.instruction
|= (Rd
& 8) << 4;
11421 inst
.instruction
|= (Rd
& 7);
11423 inst
.instruction
|= Rn
<< 3;
11425 inst
.instruction
|= Rs
<< 3;
11427 constraint (1, _("dest must overlap one source register"));
11431 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11432 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11433 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11443 Rd
= inst
.operands
[0].reg
;
11444 reject_bad_reg (Rd
);
11446 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11448 /* Defer to section relaxation. */
11449 inst
.relax
= inst
.instruction
;
11450 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11451 inst
.instruction
|= Rd
<< 4;
11453 else if (unified_syntax
&& inst
.size_req
!= 2)
11455 /* Generate a 32-bit opcode. */
11456 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11457 inst
.instruction
|= Rd
<< 8;
11458 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11459 inst
.relocs
[0].pc_rel
= 1;
11463 /* Generate a 16-bit opcode. */
11464 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11465 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11466 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11467 inst
.relocs
[0].pc_rel
= 1;
11468 inst
.instruction
|= Rd
<< 4;
11471 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11472 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11473 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11474 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11475 inst
.relocs
[0].exp
.X_add_number
+= 1;
11478 /* Arithmetic instructions for which there is just one 16-bit
11479 instruction encoding, and it allows only two low registers.
11480 For maximal compatibility with ARM syntax, we allow three register
11481 operands even when Thumb-32 instructions are not available, as long
11482 as the first two are identical. For instance, both "sbc r0,r1" and
11483 "sbc r0,r0,r1" are allowed. */
11489 Rd
= inst
.operands
[0].reg
;
11490 Rs
= (inst
.operands
[1].present
11491 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11492 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11493 Rn
= inst
.operands
[2].reg
;
11495 reject_bad_reg (Rd
);
11496 reject_bad_reg (Rs
);
11497 if (inst
.operands
[2].isreg
)
11498 reject_bad_reg (Rn
);
11500 if (unified_syntax
)
11502 if (!inst
.operands
[2].isreg
)
11504 /* For an immediate, we always generate a 32-bit opcode;
11505 section relaxation will shrink it later if possible. */
11506 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11507 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11508 inst
.instruction
|= Rd
<< 8;
11509 inst
.instruction
|= Rs
<< 16;
11510 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11514 bfd_boolean narrow
;
11516 /* See if we can do this with a 16-bit instruction. */
11517 if (THUMB_SETS_FLAGS (inst
.instruction
))
11518 narrow
= !in_pred_block ();
11520 narrow
= in_pred_block ();
11522 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11524 if (inst
.operands
[2].shifted
)
11526 if (inst
.size_req
== 4)
11532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11533 inst
.instruction
|= Rd
;
11534 inst
.instruction
|= Rn
<< 3;
11538 /* If we get here, it can't be done in 16 bits. */
11539 constraint (inst
.operands
[2].shifted
11540 && inst
.operands
[2].immisreg
,
11541 _("shift must be constant"));
11542 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11543 inst
.instruction
|= Rd
<< 8;
11544 inst
.instruction
|= Rs
<< 16;
11545 encode_thumb32_shifted_operand (2);
11550 /* On its face this is a lie - the instruction does set the
11551 flags. However, the only supported mnemonic in this mode
11552 says it doesn't. */
11553 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11555 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11556 _("unshifted register required"));
11557 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11558 constraint (Rd
!= Rs
,
11559 _("dest and source1 must be the same register"));
11561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11562 inst
.instruction
|= Rd
;
11563 inst
.instruction
|= Rn
<< 3;
11567 /* Similarly, but for instructions where the arithmetic operation is
11568 commutative, so we can allow either of them to be different from
11569 the destination operand in a 16-bit instruction. For instance, all
11570 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11577 Rd
= inst
.operands
[0].reg
;
11578 Rs
= (inst
.operands
[1].present
11579 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11580 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11581 Rn
= inst
.operands
[2].reg
;
11583 reject_bad_reg (Rd
);
11584 reject_bad_reg (Rs
);
11585 if (inst
.operands
[2].isreg
)
11586 reject_bad_reg (Rn
);
11588 if (unified_syntax
)
11590 if (!inst
.operands
[2].isreg
)
11592 /* For an immediate, we always generate a 32-bit opcode;
11593 section relaxation will shrink it later if possible. */
11594 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11595 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11596 inst
.instruction
|= Rd
<< 8;
11597 inst
.instruction
|= Rs
<< 16;
11598 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11602 bfd_boolean narrow
;
11604 /* See if we can do this with a 16-bit instruction. */
11605 if (THUMB_SETS_FLAGS (inst
.instruction
))
11606 narrow
= !in_pred_block ();
11608 narrow
= in_pred_block ();
11610 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11612 if (inst
.operands
[2].shifted
)
11614 if (inst
.size_req
== 4)
11621 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11622 inst
.instruction
|= Rd
;
11623 inst
.instruction
|= Rn
<< 3;
11628 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11629 inst
.instruction
|= Rd
;
11630 inst
.instruction
|= Rs
<< 3;
11635 /* If we get here, it can't be done in 16 bits. */
11636 constraint (inst
.operands
[2].shifted
11637 && inst
.operands
[2].immisreg
,
11638 _("shift must be constant"));
11639 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11640 inst
.instruction
|= Rd
<< 8;
11641 inst
.instruction
|= Rs
<< 16;
11642 encode_thumb32_shifted_operand (2);
11647 /* On its face this is a lie - the instruction does set the
11648 flags. However, the only supported mnemonic in this mode
11649 says it doesn't. */
11650 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11652 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11653 _("unshifted register required"));
11654 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11656 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11657 inst
.instruction
|= Rd
;
11660 inst
.instruction
|= Rn
<< 3;
11662 inst
.instruction
|= Rs
<< 3;
11664 constraint (1, _("dest must overlap one source register"));
11672 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11673 constraint (msb
> 32, _("bit-field extends past end of register"));
11674 /* The instruction encoding stores the LSB and MSB,
11675 not the LSB and width. */
11676 Rd
= inst
.operands
[0].reg
;
11677 reject_bad_reg (Rd
);
11678 inst
.instruction
|= Rd
<< 8;
11679 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11680 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11681 inst
.instruction
|= msb
- 1;
11690 Rd
= inst
.operands
[0].reg
;
11691 reject_bad_reg (Rd
);
11693 /* #0 in second position is alternative syntax for bfc, which is
11694 the same instruction but with REG_PC in the Rm field. */
11695 if (!inst
.operands
[1].isreg
)
11699 Rn
= inst
.operands
[1].reg
;
11700 reject_bad_reg (Rn
);
11703 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11704 constraint (msb
> 32, _("bit-field extends past end of register"));
11705 /* The instruction encoding stores the LSB and MSB,
11706 not the LSB and width. */
11707 inst
.instruction
|= Rd
<< 8;
11708 inst
.instruction
|= Rn
<< 16;
11709 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11710 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11711 inst
.instruction
|= msb
- 1;
11719 Rd
= inst
.operands
[0].reg
;
11720 Rn
= inst
.operands
[1].reg
;
11722 reject_bad_reg (Rd
);
11723 reject_bad_reg (Rn
);
11725 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11726 _("bit-field extends past end of register"));
11727 inst
.instruction
|= Rd
<< 8;
11728 inst
.instruction
|= Rn
<< 16;
11729 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11730 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11731 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11734 /* ARM V5 Thumb BLX (argument parse)
11735 BLX <target_addr> which is BLX(1)
11736 BLX <Rm> which is BLX(2)
11737 Unfortunately, there are two different opcodes for this mnemonic.
11738 So, the insns[].value is not used, and the code here zaps values
11739 into inst.instruction.
11741 ??? How to take advantage of the additional two bits of displacement
11742 available in Thumb32 mode? Need new relocation? */
11747 set_pred_insn_type_last ();
11749 if (inst
.operands
[0].isreg
)
11751 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11752 /* We have a register, so this is BLX(2). */
11753 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11757 /* No register. This must be BLX(1). */
11758 inst
.instruction
= 0xf000e800;
11759 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11768 bfd_reloc_code_real_type reloc
;
11771 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11773 if (in_pred_block ())
11775 /* Conditional branches inside IT blocks are encoded as unconditional
11777 cond
= COND_ALWAYS
;
11782 if (cond
!= COND_ALWAYS
)
11783 opcode
= T_MNEM_bcond
;
11785 opcode
= inst
.instruction
;
11788 && (inst
.size_req
== 4
11789 || (inst
.size_req
!= 2
11790 && (inst
.operands
[0].hasreloc
11791 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11793 inst
.instruction
= THUMB_OP32(opcode
);
11794 if (cond
== COND_ALWAYS
)
11795 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11799 _("selected architecture does not support "
11800 "wide conditional branch instruction"));
11802 gas_assert (cond
!= 0xF);
11803 inst
.instruction
|= cond
<< 22;
11804 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11809 inst
.instruction
= THUMB_OP16(opcode
);
11810 if (cond
== COND_ALWAYS
)
11811 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11814 inst
.instruction
|= cond
<< 8;
11815 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11817 /* Allow section relaxation. */
11818 if (unified_syntax
&& inst
.size_req
!= 2)
11819 inst
.relax
= opcode
;
11821 inst
.relocs
[0].type
= reloc
;
11822 inst
.relocs
[0].pc_rel
= 1;
11825 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11826 between the two is the maximum immediate allowed - which is passed in
11829 do_t_bkpt_hlt1 (int range
)
11831 constraint (inst
.cond
!= COND_ALWAYS
,
11832 _("instruction is always unconditional"));
11833 if (inst
.operands
[0].present
)
11835 constraint (inst
.operands
[0].imm
> range
,
11836 _("immediate value out of range"));
11837 inst
.instruction
|= inst
.operands
[0].imm
;
11840 set_pred_insn_type (NEUTRAL_IT_INSN
);
11846 do_t_bkpt_hlt1 (63);
11852 do_t_bkpt_hlt1 (255);
11856 do_t_branch23 (void)
11858 set_pred_insn_type_last ();
11859 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11861 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11862 this file. We used to simply ignore the PLT reloc type here --
11863 the branch encoding is now needed to deal with TLSCALL relocs.
11864 So if we see a PLT reloc now, put it back to how it used to be to
11865 keep the preexisting behaviour. */
11866 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11867 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11869 #if defined(OBJ_COFF)
11870 /* If the destination of the branch is a defined symbol which does not have
11871 the THUMB_FUNC attribute, then we must be calling a function which has
11872 the (interfacearm) attribute. We look for the Thumb entry point to that
11873 function and change the branch to refer to that function instead. */
11874 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11875 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11876 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11877 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11878 inst
.relocs
[0].exp
.X_add_symbol
11879 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11886 set_pred_insn_type_last ();
11887 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11888 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11889 should cause the alignment to be checked once it is known. This is
11890 because BX PC only works if the instruction is word aligned. */
11898 set_pred_insn_type_last ();
11899 Rm
= inst
.operands
[0].reg
;
11900 reject_bad_reg (Rm
);
11901 inst
.instruction
|= Rm
<< 16;
11910 Rd
= inst
.operands
[0].reg
;
11911 Rm
= inst
.operands
[1].reg
;
11913 reject_bad_reg (Rd
);
11914 reject_bad_reg (Rm
);
11916 inst
.instruction
|= Rd
<< 8;
11917 inst
.instruction
|= Rm
<< 16;
11918 inst
.instruction
|= Rm
;
11924 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11930 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11931 inst
.instruction
|= inst
.operands
[0].imm
;
11937 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11939 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11940 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11942 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11943 inst
.instruction
= 0xf3af8000;
11944 inst
.instruction
|= imod
<< 9;
11945 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11946 if (inst
.operands
[1].present
)
11947 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11951 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11952 && (inst
.operands
[0].imm
& 4),
11953 _("selected processor does not support 'A' form "
11954 "of this instruction"));
11955 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11956 _("Thumb does not support the 2-argument "
11957 "form of this instruction"));
11958 inst
.instruction
|= inst
.operands
[0].imm
;
11962 /* THUMB CPY instruction (argument parse). */
11967 if (inst
.size_req
== 4)
11969 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11970 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11971 inst
.instruction
|= inst
.operands
[1].reg
;
11975 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11976 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11977 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11984 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11985 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11986 inst
.instruction
|= inst
.operands
[0].reg
;
11987 inst
.relocs
[0].pc_rel
= 1;
11988 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11994 inst
.instruction
|= inst
.operands
[0].imm
;
12000 unsigned Rd
, Rn
, Rm
;
12002 Rd
= inst
.operands
[0].reg
;
12003 Rn
= (inst
.operands
[1].present
12004 ? inst
.operands
[1].reg
: Rd
);
12005 Rm
= inst
.operands
[2].reg
;
12007 reject_bad_reg (Rd
);
12008 reject_bad_reg (Rn
);
12009 reject_bad_reg (Rm
);
12011 inst
.instruction
|= Rd
<< 8;
12012 inst
.instruction
|= Rn
<< 16;
12013 inst
.instruction
|= Rm
;
12019 if (unified_syntax
&& inst
.size_req
== 4)
12020 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12022 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12028 unsigned int cond
= inst
.operands
[0].imm
;
12030 set_pred_insn_type (IT_INSN
);
12031 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12032 now_pred
.cc
= cond
;
12033 now_pred
.warn_deprecated
= FALSE
;
12034 now_pred
.type
= SCALAR_PRED
;
12036 /* If the condition is a negative condition, invert the mask. */
12037 if ((cond
& 0x1) == 0x0)
12039 unsigned int mask
= inst
.instruction
& 0x000f;
12041 if ((mask
& 0x7) == 0)
12043 /* No conversion needed. */
12044 now_pred
.block_length
= 1;
12046 else if ((mask
& 0x3) == 0)
12049 now_pred
.block_length
= 2;
12051 else if ((mask
& 0x1) == 0)
12054 now_pred
.block_length
= 3;
12059 now_pred
.block_length
= 4;
12062 inst
.instruction
&= 0xfff0;
12063 inst
.instruction
|= mask
;
12066 inst
.instruction
|= cond
<< 4;
12069 /* Helper function used for both push/pop and ldm/stm. */
12071 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12072 bfd_boolean writeback
)
12074 bfd_boolean load
, store
;
12076 gas_assert (base
!= -1 || !do_io
);
12077 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12078 store
= do_io
&& !load
;
12080 if (mask
& (1 << 13))
12081 inst
.error
= _("SP not allowed in register list");
12083 if (do_io
&& (mask
& (1 << base
)) != 0
12085 inst
.error
= _("having the base register in the register list when "
12086 "using write back is UNPREDICTABLE");
12090 if (mask
& (1 << 15))
12092 if (mask
& (1 << 14))
12093 inst
.error
= _("LR and PC should not both be in register list");
12095 set_pred_insn_type_last ();
12100 if (mask
& (1 << 15))
12101 inst
.error
= _("PC not allowed in register list");
12104 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12106 /* Single register transfers implemented as str/ldr. */
12109 if (inst
.instruction
& (1 << 23))
12110 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12112 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12116 if (inst
.instruction
& (1 << 23))
12117 inst
.instruction
= 0x00800000; /* ia -> [base] */
12119 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12122 inst
.instruction
|= 0xf8400000;
12124 inst
.instruction
|= 0x00100000;
12126 mask
= ffs (mask
) - 1;
12129 else if (writeback
)
12130 inst
.instruction
|= WRITE_BACK
;
12132 inst
.instruction
|= mask
;
12134 inst
.instruction
|= base
<< 16;
12140 /* This really doesn't seem worth it. */
12141 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12142 _("expression too complex"));
12143 constraint (inst
.operands
[1].writeback
,
12144 _("Thumb load/store multiple does not support {reglist}^"));
12146 if (unified_syntax
)
12148 bfd_boolean narrow
;
12152 /* See if we can use a 16-bit instruction. */
12153 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12154 && inst
.size_req
!= 4
12155 && !(inst
.operands
[1].imm
& ~0xff))
12157 mask
= 1 << inst
.operands
[0].reg
;
12159 if (inst
.operands
[0].reg
<= 7)
12161 if (inst
.instruction
== T_MNEM_stmia
12162 ? inst
.operands
[0].writeback
12163 : (inst
.operands
[0].writeback
12164 == !(inst
.operands
[1].imm
& mask
)))
12166 if (inst
.instruction
== T_MNEM_stmia
12167 && (inst
.operands
[1].imm
& mask
)
12168 && (inst
.operands
[1].imm
& (mask
- 1)))
12169 as_warn (_("value stored for r%d is UNKNOWN"),
12170 inst
.operands
[0].reg
);
12172 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12173 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12174 inst
.instruction
|= inst
.operands
[1].imm
;
12177 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12179 /* This means 1 register in reg list one of 3 situations:
12180 1. Instruction is stmia, but without writeback.
12181 2. lmdia without writeback, but with Rn not in
12183 3. ldmia with writeback, but with Rn in reglist.
12184 Case 3 is UNPREDICTABLE behaviour, so we handle
12185 case 1 and 2 which can be converted into a 16-bit
12186 str or ldr. The SP cases are handled below. */
12187 unsigned long opcode
;
12188 /* First, record an error for Case 3. */
12189 if (inst
.operands
[1].imm
& mask
12190 && inst
.operands
[0].writeback
)
12192 _("having the base register in the register list when "
12193 "using write back is UNPREDICTABLE");
12195 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12197 inst
.instruction
= THUMB_OP16 (opcode
);
12198 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12199 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12203 else if (inst
.operands
[0] .reg
== REG_SP
)
12205 if (inst
.operands
[0].writeback
)
12208 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12209 ? T_MNEM_push
: T_MNEM_pop
);
12210 inst
.instruction
|= inst
.operands
[1].imm
;
12213 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12216 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12217 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12218 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12226 if (inst
.instruction
< 0xffff)
12227 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12229 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12230 inst
.operands
[1].imm
,
12231 inst
.operands
[0].writeback
);
12236 constraint (inst
.operands
[0].reg
> 7
12237 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12238 constraint (inst
.instruction
!= T_MNEM_ldmia
12239 && inst
.instruction
!= T_MNEM_stmia
,
12240 _("Thumb-2 instruction only valid in unified syntax"));
12241 if (inst
.instruction
== T_MNEM_stmia
)
12243 if (!inst
.operands
[0].writeback
)
12244 as_warn (_("this instruction will write back the base register"));
12245 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12246 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12247 as_warn (_("value stored for r%d is UNKNOWN"),
12248 inst
.operands
[0].reg
);
12252 if (!inst
.operands
[0].writeback
12253 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12254 as_warn (_("this instruction will write back the base register"));
12255 else if (inst
.operands
[0].writeback
12256 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12257 as_warn (_("this instruction will not write back the base register"));
12260 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12261 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12262 inst
.instruction
|= inst
.operands
[1].imm
;
12269 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12270 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12271 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12272 || inst
.operands
[1].negative
,
12275 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12278 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12279 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12285 if (!inst
.operands
[1].present
)
12287 constraint (inst
.operands
[0].reg
== REG_LR
,
12288 _("r14 not allowed as first register "
12289 "when second register is omitted"));
12290 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12292 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12296 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12297 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12303 unsigned long opcode
;
12306 if (inst
.operands
[0].isreg
12307 && !inst
.operands
[0].preind
12308 && inst
.operands
[0].reg
== REG_PC
)
12309 set_pred_insn_type_last ();
12311 opcode
= inst
.instruction
;
12312 if (unified_syntax
)
12314 if (!inst
.operands
[1].isreg
)
12316 if (opcode
<= 0xffff)
12317 inst
.instruction
= THUMB_OP32 (opcode
);
12318 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12321 if (inst
.operands
[1].isreg
12322 && !inst
.operands
[1].writeback
12323 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12324 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12325 && opcode
<= 0xffff
12326 && inst
.size_req
!= 4)
12328 /* Insn may have a 16-bit form. */
12329 Rn
= inst
.operands
[1].reg
;
12330 if (inst
.operands
[1].immisreg
)
12332 inst
.instruction
= THUMB_OP16 (opcode
);
12334 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12336 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12337 reject_bad_reg (inst
.operands
[1].imm
);
12339 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12340 && opcode
!= T_MNEM_ldrsb
)
12341 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12342 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12349 if (inst
.relocs
[0].pc_rel
)
12350 opcode
= T_MNEM_ldr_pc2
;
12352 opcode
= T_MNEM_ldr_pc
;
12356 if (opcode
== T_MNEM_ldr
)
12357 opcode
= T_MNEM_ldr_sp
;
12359 opcode
= T_MNEM_str_sp
;
12361 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12365 inst
.instruction
= inst
.operands
[0].reg
;
12366 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12368 inst
.instruction
|= THUMB_OP16 (opcode
);
12369 if (inst
.size_req
== 2)
12370 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12372 inst
.relax
= opcode
;
12376 /* Definitely a 32-bit variant. */
12378 /* Warning for Erratum 752419. */
12379 if (opcode
== T_MNEM_ldr
12380 && inst
.operands
[0].reg
== REG_SP
12381 && inst
.operands
[1].writeback
== 1
12382 && !inst
.operands
[1].immisreg
)
12384 if (no_cpu_selected ()
12385 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12386 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12387 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12388 as_warn (_("This instruction may be unpredictable "
12389 "if executed on M-profile cores "
12390 "with interrupts enabled."));
12393 /* Do some validations regarding addressing modes. */
12394 if (inst
.operands
[1].immisreg
)
12395 reject_bad_reg (inst
.operands
[1].imm
);
12397 constraint (inst
.operands
[1].writeback
== 1
12398 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12401 inst
.instruction
= THUMB_OP32 (opcode
);
12402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12403 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12404 check_ldr_r15_aligned ();
12408 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12410 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12412 /* Only [Rn,Rm] is acceptable. */
12413 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12414 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12415 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12416 || inst
.operands
[1].negative
,
12417 _("Thumb does not support this addressing mode"));
12418 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12422 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12423 if (!inst
.operands
[1].isreg
)
12424 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12427 constraint (!inst
.operands
[1].preind
12428 || inst
.operands
[1].shifted
12429 || inst
.operands
[1].writeback
,
12430 _("Thumb does not support this addressing mode"));
12431 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12433 constraint (inst
.instruction
& 0x0600,
12434 _("byte or halfword not valid for base register"));
12435 constraint (inst
.operands
[1].reg
== REG_PC
12436 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12437 _("r15 based store not allowed"));
12438 constraint (inst
.operands
[1].immisreg
,
12439 _("invalid base register for register offset"));
12441 if (inst
.operands
[1].reg
== REG_PC
)
12442 inst
.instruction
= T_OPCODE_LDR_PC
;
12443 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12444 inst
.instruction
= T_OPCODE_LDR_SP
;
12446 inst
.instruction
= T_OPCODE_STR_SP
;
12448 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12449 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12453 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12454 if (!inst
.operands
[1].immisreg
)
12456 /* Immediate offset. */
12457 inst
.instruction
|= inst
.operands
[0].reg
;
12458 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12459 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12463 /* Register offset. */
12464 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12465 constraint (inst
.operands
[1].negative
,
12466 _("Thumb does not support this addressing mode"));
12469 switch (inst
.instruction
)
12471 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12472 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12473 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12474 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12475 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12476 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12477 case 0x5600 /* ldrsb */:
12478 case 0x5e00 /* ldrsh */: break;
12482 inst
.instruction
|= inst
.operands
[0].reg
;
12483 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12484 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12490 if (!inst
.operands
[1].present
)
12492 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12493 constraint (inst
.operands
[0].reg
== REG_LR
,
12494 _("r14 not allowed here"));
12495 constraint (inst
.operands
[0].reg
== REG_R12
,
12496 _("r12 not allowed here"));
12499 if (inst
.operands
[2].writeback
12500 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12501 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12502 as_warn (_("base register written back, and overlaps "
12503 "one of transfer registers"));
12505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12506 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12507 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12514 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12520 unsigned Rd
, Rn
, Rm
, Ra
;
12522 Rd
= inst
.operands
[0].reg
;
12523 Rn
= inst
.operands
[1].reg
;
12524 Rm
= inst
.operands
[2].reg
;
12525 Ra
= inst
.operands
[3].reg
;
12527 reject_bad_reg (Rd
);
12528 reject_bad_reg (Rn
);
12529 reject_bad_reg (Rm
);
12530 reject_bad_reg (Ra
);
12532 inst
.instruction
|= Rd
<< 8;
12533 inst
.instruction
|= Rn
<< 16;
12534 inst
.instruction
|= Rm
;
12535 inst
.instruction
|= Ra
<< 12;
12541 unsigned RdLo
, RdHi
, Rn
, Rm
;
12543 RdLo
= inst
.operands
[0].reg
;
12544 RdHi
= inst
.operands
[1].reg
;
12545 Rn
= inst
.operands
[2].reg
;
12546 Rm
= inst
.operands
[3].reg
;
12548 reject_bad_reg (RdLo
);
12549 reject_bad_reg (RdHi
);
12550 reject_bad_reg (Rn
);
12551 reject_bad_reg (Rm
);
12553 inst
.instruction
|= RdLo
<< 12;
12554 inst
.instruction
|= RdHi
<< 8;
12555 inst
.instruction
|= Rn
<< 16;
12556 inst
.instruction
|= Rm
;
12560 do_t_mov_cmp (void)
12564 Rn
= inst
.operands
[0].reg
;
12565 Rm
= inst
.operands
[1].reg
;
12568 set_pred_insn_type_last ();
12570 if (unified_syntax
)
12572 int r0off
= (inst
.instruction
== T_MNEM_mov
12573 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12574 unsigned long opcode
;
12575 bfd_boolean narrow
;
12576 bfd_boolean low_regs
;
12578 low_regs
= (Rn
<= 7 && Rm
<= 7);
12579 opcode
= inst
.instruction
;
12580 if (in_pred_block ())
12581 narrow
= opcode
!= T_MNEM_movs
;
12583 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12584 if (inst
.size_req
== 4
12585 || inst
.operands
[1].shifted
)
12588 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12589 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12590 && !inst
.operands
[1].shifted
12594 inst
.instruction
= T2_SUBS_PC_LR
;
12598 if (opcode
== T_MNEM_cmp
)
12600 constraint (Rn
== REG_PC
, BAD_PC
);
12603 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12605 warn_deprecated_sp (Rm
);
12606 /* R15 was documented as a valid choice for Rm in ARMv6,
12607 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12608 tools reject R15, so we do too. */
12609 constraint (Rm
== REG_PC
, BAD_PC
);
12612 reject_bad_reg (Rm
);
12614 else if (opcode
== T_MNEM_mov
12615 || opcode
== T_MNEM_movs
)
12617 if (inst
.operands
[1].isreg
)
12619 if (opcode
== T_MNEM_movs
)
12621 reject_bad_reg (Rn
);
12622 reject_bad_reg (Rm
);
12626 /* This is mov.n. */
12627 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12628 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12630 as_tsktsk (_("Use of r%u as a source register is "
12631 "deprecated when r%u is the destination "
12632 "register."), Rm
, Rn
);
12637 /* This is mov.w. */
12638 constraint (Rn
== REG_PC
, BAD_PC
);
12639 constraint (Rm
== REG_PC
, BAD_PC
);
12640 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12641 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12645 reject_bad_reg (Rn
);
12648 if (!inst
.operands
[1].isreg
)
12650 /* Immediate operand. */
12651 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12653 if (low_regs
&& narrow
)
12655 inst
.instruction
= THUMB_OP16 (opcode
);
12656 inst
.instruction
|= Rn
<< 8;
12657 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12658 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12660 if (inst
.size_req
== 2)
12661 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12663 inst
.relax
= opcode
;
12668 constraint ((inst
.relocs
[0].type
12669 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12670 && (inst
.relocs
[0].type
12671 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12672 THUMB1_RELOC_ONLY
);
12674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12675 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12676 inst
.instruction
|= Rn
<< r0off
;
12677 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12680 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12681 && (inst
.instruction
== T_MNEM_mov
12682 || inst
.instruction
== T_MNEM_movs
))
12684 /* Register shifts are encoded as separate shift instructions. */
12685 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12687 if (in_pred_block ())
12692 if (inst
.size_req
== 4)
12695 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12701 switch (inst
.operands
[1].shift_kind
)
12704 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12707 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12710 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12713 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12719 inst
.instruction
= opcode
;
12722 inst
.instruction
|= Rn
;
12723 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12728 inst
.instruction
|= CONDS_BIT
;
12730 inst
.instruction
|= Rn
<< 8;
12731 inst
.instruction
|= Rm
<< 16;
12732 inst
.instruction
|= inst
.operands
[1].imm
;
12737 /* Some mov with immediate shift have narrow variants.
12738 Register shifts are handled above. */
12739 if (low_regs
&& inst
.operands
[1].shifted
12740 && (inst
.instruction
== T_MNEM_mov
12741 || inst
.instruction
== T_MNEM_movs
))
12743 if (in_pred_block ())
12744 narrow
= (inst
.instruction
== T_MNEM_mov
);
12746 narrow
= (inst
.instruction
== T_MNEM_movs
);
12751 switch (inst
.operands
[1].shift_kind
)
12753 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12754 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12755 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12756 default: narrow
= FALSE
; break;
12762 inst
.instruction
|= Rn
;
12763 inst
.instruction
|= Rm
<< 3;
12764 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12768 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12769 inst
.instruction
|= Rn
<< r0off
;
12770 encode_thumb32_shifted_operand (1);
12774 switch (inst
.instruction
)
12777 /* In v4t or v5t a move of two lowregs produces unpredictable
12778 results. Don't allow this. */
12781 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12782 "MOV Rd, Rs with two low registers is not "
12783 "permitted on this architecture");
12784 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12788 inst
.instruction
= T_OPCODE_MOV_HR
;
12789 inst
.instruction
|= (Rn
& 0x8) << 4;
12790 inst
.instruction
|= (Rn
& 0x7);
12791 inst
.instruction
|= Rm
<< 3;
12795 /* We know we have low registers at this point.
12796 Generate LSLS Rd, Rs, #0. */
12797 inst
.instruction
= T_OPCODE_LSL_I
;
12798 inst
.instruction
|= Rn
;
12799 inst
.instruction
|= Rm
<< 3;
12805 inst
.instruction
= T_OPCODE_CMP_LR
;
12806 inst
.instruction
|= Rn
;
12807 inst
.instruction
|= Rm
<< 3;
12811 inst
.instruction
= T_OPCODE_CMP_HR
;
12812 inst
.instruction
|= (Rn
& 0x8) << 4;
12813 inst
.instruction
|= (Rn
& 0x7);
12814 inst
.instruction
|= Rm
<< 3;
12821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12823 /* PR 10443: Do not silently ignore shifted operands. */
12824 constraint (inst
.operands
[1].shifted
,
12825 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12827 if (inst
.operands
[1].isreg
)
12829 if (Rn
< 8 && Rm
< 8)
12831 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12832 since a MOV instruction produces unpredictable results. */
12833 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12834 inst
.instruction
= T_OPCODE_ADD_I3
;
12836 inst
.instruction
= T_OPCODE_CMP_LR
;
12838 inst
.instruction
|= Rn
;
12839 inst
.instruction
|= Rm
<< 3;
12843 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12844 inst
.instruction
= T_OPCODE_MOV_HR
;
12846 inst
.instruction
= T_OPCODE_CMP_HR
;
12852 constraint (Rn
> 7,
12853 _("only lo regs allowed with immediate"));
12854 inst
.instruction
|= Rn
<< 8;
12855 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12866 top
= (inst
.instruction
& 0x00800000) != 0;
12867 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12869 constraint (top
, _(":lower16: not allowed in this instruction"));
12870 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12872 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12874 constraint (!top
, _(":upper16: not allowed in this instruction"));
12875 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12878 Rd
= inst
.operands
[0].reg
;
12879 reject_bad_reg (Rd
);
12881 inst
.instruction
|= Rd
<< 8;
12882 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12884 imm
= inst
.relocs
[0].exp
.X_add_number
;
12885 inst
.instruction
|= (imm
& 0xf000) << 4;
12886 inst
.instruction
|= (imm
& 0x0800) << 15;
12887 inst
.instruction
|= (imm
& 0x0700) << 4;
12888 inst
.instruction
|= (imm
& 0x00ff);
12893 do_t_mvn_tst (void)
12897 Rn
= inst
.operands
[0].reg
;
12898 Rm
= inst
.operands
[1].reg
;
12900 if (inst
.instruction
== T_MNEM_cmp
12901 || inst
.instruction
== T_MNEM_cmn
)
12902 constraint (Rn
== REG_PC
, BAD_PC
);
12904 reject_bad_reg (Rn
);
12905 reject_bad_reg (Rm
);
12907 if (unified_syntax
)
12909 int r0off
= (inst
.instruction
== T_MNEM_mvn
12910 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12911 bfd_boolean narrow
;
12913 if (inst
.size_req
== 4
12914 || inst
.instruction
> 0xffff
12915 || inst
.operands
[1].shifted
12916 || Rn
> 7 || Rm
> 7)
12918 else if (inst
.instruction
== T_MNEM_cmn
12919 || inst
.instruction
== T_MNEM_tst
)
12921 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12922 narrow
= !in_pred_block ();
12924 narrow
= in_pred_block ();
12926 if (!inst
.operands
[1].isreg
)
12928 /* For an immediate, we always generate a 32-bit opcode;
12929 section relaxation will shrink it later if possible. */
12930 if (inst
.instruction
< 0xffff)
12931 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12932 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12933 inst
.instruction
|= Rn
<< r0off
;
12934 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12938 /* See if we can do this with a 16-bit instruction. */
12941 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12942 inst
.instruction
|= Rn
;
12943 inst
.instruction
|= Rm
<< 3;
12947 constraint (inst
.operands
[1].shifted
12948 && inst
.operands
[1].immisreg
,
12949 _("shift must be constant"));
12950 if (inst
.instruction
< 0xffff)
12951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12952 inst
.instruction
|= Rn
<< r0off
;
12953 encode_thumb32_shifted_operand (1);
12959 constraint (inst
.instruction
> 0xffff
12960 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12961 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12962 _("unshifted register required"));
12963 constraint (Rn
> 7 || Rm
> 7,
12966 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12967 inst
.instruction
|= Rn
;
12968 inst
.instruction
|= Rm
<< 3;
12977 if (do_vfp_nsyn_mrs () == SUCCESS
)
12980 Rd
= inst
.operands
[0].reg
;
12981 reject_bad_reg (Rd
);
12982 inst
.instruction
|= Rd
<< 8;
12984 if (inst
.operands
[1].isreg
)
12986 unsigned br
= inst
.operands
[1].reg
;
12987 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12988 as_bad (_("bad register for mrs"));
12990 inst
.instruction
|= br
& (0xf << 16);
12991 inst
.instruction
|= (br
& 0x300) >> 4;
12992 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12996 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12998 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13000 /* PR gas/12698: The constraint is only applied for m_profile.
13001 If the user has specified -march=all, we want to ignore it as
13002 we are building for any CPU type, including non-m variants. */
13003 bfd_boolean m_profile
=
13004 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13005 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13006 "not support requested special purpose register"));
13009 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13011 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13012 _("'APSR', 'CPSR' or 'SPSR' expected"));
13014 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13015 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13016 inst
.instruction
|= 0xf0000;
13026 if (do_vfp_nsyn_msr () == SUCCESS
)
13029 constraint (!inst
.operands
[1].isreg
,
13030 _("Thumb encoding does not support an immediate here"));
13032 if (inst
.operands
[0].isreg
)
13033 flags
= (int)(inst
.operands
[0].reg
);
13035 flags
= inst
.operands
[0].imm
;
13037 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13039 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13041 /* PR gas/12698: The constraint is only applied for m_profile.
13042 If the user has specified -march=all, we want to ignore it as
13043 we are building for any CPU type, including non-m variants. */
13044 bfd_boolean m_profile
=
13045 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13046 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13047 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13048 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13049 && bits
!= PSR_f
)) && m_profile
,
13050 _("selected processor does not support requested special "
13051 "purpose register"));
13054 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13055 "requested special purpose register"));
13057 Rn
= inst
.operands
[1].reg
;
13058 reject_bad_reg (Rn
);
13060 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13061 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13062 inst
.instruction
|= (flags
& 0x300) >> 4;
13063 inst
.instruction
|= (flags
& 0xff);
13064 inst
.instruction
|= Rn
<< 16;
13070 bfd_boolean narrow
;
13071 unsigned Rd
, Rn
, Rm
;
13073 if (!inst
.operands
[2].present
)
13074 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13076 Rd
= inst
.operands
[0].reg
;
13077 Rn
= inst
.operands
[1].reg
;
13078 Rm
= inst
.operands
[2].reg
;
13080 if (unified_syntax
)
13082 if (inst
.size_req
== 4
13088 else if (inst
.instruction
== T_MNEM_muls
)
13089 narrow
= !in_pred_block ();
13091 narrow
= in_pred_block ();
13095 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13096 constraint (Rn
> 7 || Rm
> 7,
13103 /* 16-bit MULS/Conditional MUL. */
13104 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13105 inst
.instruction
|= Rd
;
13108 inst
.instruction
|= Rm
<< 3;
13110 inst
.instruction
|= Rn
<< 3;
13112 constraint (1, _("dest must overlap one source register"));
13116 constraint (inst
.instruction
!= T_MNEM_mul
,
13117 _("Thumb-2 MUL must not set flags"));
13119 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13120 inst
.instruction
|= Rd
<< 8;
13121 inst
.instruction
|= Rn
<< 16;
13122 inst
.instruction
|= Rm
<< 0;
13124 reject_bad_reg (Rd
);
13125 reject_bad_reg (Rn
);
13126 reject_bad_reg (Rm
);
13133 unsigned RdLo
, RdHi
, Rn
, Rm
;
13135 RdLo
= inst
.operands
[0].reg
;
13136 RdHi
= inst
.operands
[1].reg
;
13137 Rn
= inst
.operands
[2].reg
;
13138 Rm
= inst
.operands
[3].reg
;
13140 reject_bad_reg (RdLo
);
13141 reject_bad_reg (RdHi
);
13142 reject_bad_reg (Rn
);
13143 reject_bad_reg (Rm
);
13145 inst
.instruction
|= RdLo
<< 12;
13146 inst
.instruction
|= RdHi
<< 8;
13147 inst
.instruction
|= Rn
<< 16;
13148 inst
.instruction
|= Rm
;
13151 as_tsktsk (_("rdhi and rdlo must be different"));
13157 set_pred_insn_type (NEUTRAL_IT_INSN
);
13159 if (unified_syntax
)
13161 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13163 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13164 inst
.instruction
|= inst
.operands
[0].imm
;
13168 /* PR9722: Check for Thumb2 availability before
13169 generating a thumb2 nop instruction. */
13170 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13172 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13173 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13176 inst
.instruction
= 0x46c0;
13181 constraint (inst
.operands
[0].present
,
13182 _("Thumb does not support NOP with hints"));
13183 inst
.instruction
= 0x46c0;
13190 if (unified_syntax
)
13192 bfd_boolean narrow
;
13194 if (THUMB_SETS_FLAGS (inst
.instruction
))
13195 narrow
= !in_pred_block ();
13197 narrow
= in_pred_block ();
13198 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13200 if (inst
.size_req
== 4)
13205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13206 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13212 inst
.instruction
|= inst
.operands
[0].reg
;
13213 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13218 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13220 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13222 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13223 inst
.instruction
|= inst
.operands
[0].reg
;
13224 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13233 Rd
= inst
.operands
[0].reg
;
13234 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13236 reject_bad_reg (Rd
);
13237 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13238 reject_bad_reg (Rn
);
13240 inst
.instruction
|= Rd
<< 8;
13241 inst
.instruction
|= Rn
<< 16;
13243 if (!inst
.operands
[2].isreg
)
13245 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13246 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13252 Rm
= inst
.operands
[2].reg
;
13253 reject_bad_reg (Rm
);
13255 constraint (inst
.operands
[2].shifted
13256 && inst
.operands
[2].immisreg
,
13257 _("shift must be constant"));
13258 encode_thumb32_shifted_operand (2);
13265 unsigned Rd
, Rn
, Rm
;
13267 Rd
= inst
.operands
[0].reg
;
13268 Rn
= inst
.operands
[1].reg
;
13269 Rm
= inst
.operands
[2].reg
;
13271 reject_bad_reg (Rd
);
13272 reject_bad_reg (Rn
);
13273 reject_bad_reg (Rm
);
13275 inst
.instruction
|= Rd
<< 8;
13276 inst
.instruction
|= Rn
<< 16;
13277 inst
.instruction
|= Rm
;
13278 if (inst
.operands
[3].present
)
13280 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13281 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13282 _("expression too complex"));
13283 inst
.instruction
|= (val
& 0x1c) << 10;
13284 inst
.instruction
|= (val
& 0x03) << 6;
13291 if (!inst
.operands
[3].present
)
13295 inst
.instruction
&= ~0x00000020;
13297 /* PR 10168. Swap the Rm and Rn registers. */
13298 Rtmp
= inst
.operands
[1].reg
;
13299 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13300 inst
.operands
[2].reg
= Rtmp
;
13308 if (inst
.operands
[0].immisreg
)
13309 reject_bad_reg (inst
.operands
[0].imm
);
13311 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13315 do_t_push_pop (void)
13319 constraint (inst
.operands
[0].writeback
,
13320 _("push/pop do not support {reglist}^"));
13321 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13322 _("expression too complex"));
13324 mask
= inst
.operands
[0].imm
;
13325 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13326 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13327 else if (inst
.size_req
!= 4
13328 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13329 ? REG_LR
: REG_PC
)))
13331 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13332 inst
.instruction
|= THUMB_PP_PC_LR
;
13333 inst
.instruction
|= mask
& 0xff;
13335 else if (unified_syntax
)
13337 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13338 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13342 inst
.error
= _("invalid register list to push/pop instruction");
13350 if (unified_syntax
)
13351 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13354 inst
.error
= _("invalid register list to push/pop instruction");
13360 do_t_vscclrm (void)
13362 if (inst
.operands
[0].issingle
)
13364 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13365 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13366 inst
.instruction
|= inst
.operands
[0].imm
;
13370 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13371 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13372 inst
.instruction
|= 1 << 8;
13373 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13382 Rd
= inst
.operands
[0].reg
;
13383 Rm
= inst
.operands
[1].reg
;
13385 reject_bad_reg (Rd
);
13386 reject_bad_reg (Rm
);
13388 inst
.instruction
|= Rd
<< 8;
13389 inst
.instruction
|= Rm
<< 16;
13390 inst
.instruction
|= Rm
;
13398 Rd
= inst
.operands
[0].reg
;
13399 Rm
= inst
.operands
[1].reg
;
13401 reject_bad_reg (Rd
);
13402 reject_bad_reg (Rm
);
13404 if (Rd
<= 7 && Rm
<= 7
13405 && inst
.size_req
!= 4)
13407 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13408 inst
.instruction
|= Rd
;
13409 inst
.instruction
|= Rm
<< 3;
13411 else if (unified_syntax
)
13413 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13414 inst
.instruction
|= Rd
<< 8;
13415 inst
.instruction
|= Rm
<< 16;
13416 inst
.instruction
|= Rm
;
13419 inst
.error
= BAD_HIREG
;
13427 Rd
= inst
.operands
[0].reg
;
13428 Rm
= inst
.operands
[1].reg
;
13430 reject_bad_reg (Rd
);
13431 reject_bad_reg (Rm
);
13433 inst
.instruction
|= Rd
<< 8;
13434 inst
.instruction
|= Rm
;
13442 Rd
= inst
.operands
[0].reg
;
13443 Rs
= (inst
.operands
[1].present
13444 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13445 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13447 reject_bad_reg (Rd
);
13448 reject_bad_reg (Rs
);
13449 if (inst
.operands
[2].isreg
)
13450 reject_bad_reg (inst
.operands
[2].reg
);
13452 inst
.instruction
|= Rd
<< 8;
13453 inst
.instruction
|= Rs
<< 16;
13454 if (!inst
.operands
[2].isreg
)
13456 bfd_boolean narrow
;
13458 if ((inst
.instruction
& 0x00100000) != 0)
13459 narrow
= !in_pred_block ();
13461 narrow
= in_pred_block ();
13463 if (Rd
> 7 || Rs
> 7)
13466 if (inst
.size_req
== 4 || !unified_syntax
)
13469 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13470 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13473 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13474 relaxation, but it doesn't seem worth the hassle. */
13477 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13478 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13479 inst
.instruction
|= Rs
<< 3;
13480 inst
.instruction
|= Rd
;
13484 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13485 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13489 encode_thumb32_shifted_operand (2);
13495 if (warn_on_deprecated
13496 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13497 as_tsktsk (_("setend use is deprecated for ARMv8"));
13499 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13500 if (inst
.operands
[0].imm
)
13501 inst
.instruction
|= 0x8;
13507 if (!inst
.operands
[1].present
)
13508 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13510 if (unified_syntax
)
13512 bfd_boolean narrow
;
13515 switch (inst
.instruction
)
13518 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13520 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13522 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13524 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13528 if (THUMB_SETS_FLAGS (inst
.instruction
))
13529 narrow
= !in_pred_block ();
13531 narrow
= in_pred_block ();
13532 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13534 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13536 if (inst
.operands
[2].isreg
13537 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13538 || inst
.operands
[2].reg
> 7))
13540 if (inst
.size_req
== 4)
13543 reject_bad_reg (inst
.operands
[0].reg
);
13544 reject_bad_reg (inst
.operands
[1].reg
);
13548 if (inst
.operands
[2].isreg
)
13550 reject_bad_reg (inst
.operands
[2].reg
);
13551 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13552 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13553 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13554 inst
.instruction
|= inst
.operands
[2].reg
;
13556 /* PR 12854: Error on extraneous shifts. */
13557 constraint (inst
.operands
[2].shifted
,
13558 _("extraneous shift as part of operand to shift insn"));
13562 inst
.operands
[1].shifted
= 1;
13563 inst
.operands
[1].shift_kind
= shift_kind
;
13564 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13565 ? T_MNEM_movs
: T_MNEM_mov
);
13566 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13567 encode_thumb32_shifted_operand (1);
13568 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13569 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13574 if (inst
.operands
[2].isreg
)
13576 switch (shift_kind
)
13578 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13579 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13580 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13581 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13585 inst
.instruction
|= inst
.operands
[0].reg
;
13586 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13588 /* PR 12854: Error on extraneous shifts. */
13589 constraint (inst
.operands
[2].shifted
,
13590 _("extraneous shift as part of operand to shift insn"));
13594 switch (shift_kind
)
13596 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13597 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13598 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13601 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13602 inst
.instruction
|= inst
.operands
[0].reg
;
13603 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13609 constraint (inst
.operands
[0].reg
> 7
13610 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13611 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13613 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13615 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13616 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13617 _("source1 and dest must be same register"));
13619 switch (inst
.instruction
)
13621 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13622 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13623 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13624 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13628 inst
.instruction
|= inst
.operands
[0].reg
;
13629 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13631 /* PR 12854: Error on extraneous shifts. */
13632 constraint (inst
.operands
[2].shifted
,
13633 _("extraneous shift as part of operand to shift insn"));
13637 switch (inst
.instruction
)
13639 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13640 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13641 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13642 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13645 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13646 inst
.instruction
|= inst
.operands
[0].reg
;
13647 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13655 unsigned Rd
, Rn
, Rm
;
13657 Rd
= inst
.operands
[0].reg
;
13658 Rn
= inst
.operands
[1].reg
;
13659 Rm
= inst
.operands
[2].reg
;
13661 reject_bad_reg (Rd
);
13662 reject_bad_reg (Rn
);
13663 reject_bad_reg (Rm
);
13665 inst
.instruction
|= Rd
<< 8;
13666 inst
.instruction
|= Rn
<< 16;
13667 inst
.instruction
|= Rm
;
13673 unsigned Rd
, Rn
, Rm
;
13675 Rd
= inst
.operands
[0].reg
;
13676 Rm
= inst
.operands
[1].reg
;
13677 Rn
= inst
.operands
[2].reg
;
13679 reject_bad_reg (Rd
);
13680 reject_bad_reg (Rn
);
13681 reject_bad_reg (Rm
);
13683 inst
.instruction
|= Rd
<< 8;
13684 inst
.instruction
|= Rn
<< 16;
13685 inst
.instruction
|= Rm
;
13691 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13692 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13693 _("SMC is not permitted on this architecture"));
13694 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13695 _("expression too complex"));
13696 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13697 inst
.instruction
|= (value
& 0xf000) >> 12;
13698 inst
.instruction
|= (value
& 0x0ff0);
13699 inst
.instruction
|= (value
& 0x000f) << 16;
13700 /* PR gas/15623: SMC instructions must be last in an IT block. */
13701 set_pred_insn_type_last ();
13707 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13709 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13710 inst
.instruction
|= (value
& 0x0fff);
13711 inst
.instruction
|= (value
& 0xf000) << 4;
13715 do_t_ssat_usat (int bias
)
13719 Rd
= inst
.operands
[0].reg
;
13720 Rn
= inst
.operands
[2].reg
;
13722 reject_bad_reg (Rd
);
13723 reject_bad_reg (Rn
);
13725 inst
.instruction
|= Rd
<< 8;
13726 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13727 inst
.instruction
|= Rn
<< 16;
13729 if (inst
.operands
[3].present
)
13731 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13733 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13735 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13736 _("expression too complex"));
13738 if (shift_amount
!= 0)
13740 constraint (shift_amount
> 31,
13741 _("shift expression is too large"));
13743 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13744 inst
.instruction
|= 0x00200000; /* sh bit. */
13746 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13747 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13755 do_t_ssat_usat (1);
13763 Rd
= inst
.operands
[0].reg
;
13764 Rn
= inst
.operands
[2].reg
;
13766 reject_bad_reg (Rd
);
13767 reject_bad_reg (Rn
);
13769 inst
.instruction
|= Rd
<< 8;
13770 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13771 inst
.instruction
|= Rn
<< 16;
13777 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13778 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13779 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13780 || inst
.operands
[2].negative
,
13783 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13785 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13786 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13787 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13788 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13794 if (!inst
.operands
[2].present
)
13795 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13797 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13798 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13799 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13802 inst
.instruction
|= inst
.operands
[0].reg
;
13803 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13804 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13805 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13811 unsigned Rd
, Rn
, Rm
;
13813 Rd
= inst
.operands
[0].reg
;
13814 Rn
= inst
.operands
[1].reg
;
13815 Rm
= inst
.operands
[2].reg
;
13817 reject_bad_reg (Rd
);
13818 reject_bad_reg (Rn
);
13819 reject_bad_reg (Rm
);
13821 inst
.instruction
|= Rd
<< 8;
13822 inst
.instruction
|= Rn
<< 16;
13823 inst
.instruction
|= Rm
;
13824 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13832 Rd
= inst
.operands
[0].reg
;
13833 Rm
= inst
.operands
[1].reg
;
13835 reject_bad_reg (Rd
);
13836 reject_bad_reg (Rm
);
13838 if (inst
.instruction
<= 0xffff
13839 && inst
.size_req
!= 4
13840 && Rd
<= 7 && Rm
<= 7
13841 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13843 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13844 inst
.instruction
|= Rd
;
13845 inst
.instruction
|= Rm
<< 3;
13847 else if (unified_syntax
)
13849 if (inst
.instruction
<= 0xffff)
13850 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13851 inst
.instruction
|= Rd
<< 8;
13852 inst
.instruction
|= Rm
;
13853 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13857 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13858 _("Thumb encoding does not support rotation"));
13859 constraint (1, BAD_HIREG
);
13866 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13875 half
= (inst
.instruction
& 0x10) != 0;
13876 set_pred_insn_type_last ();
13877 constraint (inst
.operands
[0].immisreg
,
13878 _("instruction requires register index"));
13880 Rn
= inst
.operands
[0].reg
;
13881 Rm
= inst
.operands
[0].imm
;
13883 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13884 constraint (Rn
== REG_SP
, BAD_SP
);
13885 reject_bad_reg (Rm
);
13887 constraint (!half
&& inst
.operands
[0].shifted
,
13888 _("instruction does not allow shifted index"));
13889 inst
.instruction
|= (Rn
<< 16) | Rm
;
13895 if (!inst
.operands
[0].present
)
13896 inst
.operands
[0].imm
= 0;
13898 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13900 constraint (inst
.size_req
== 2,
13901 _("immediate value out of range"));
13902 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13903 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13904 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13908 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13909 inst
.instruction
|= inst
.operands
[0].imm
;
13912 set_pred_insn_type (NEUTRAL_IT_INSN
);
13919 do_t_ssat_usat (0);
13927 Rd
= inst
.operands
[0].reg
;
13928 Rn
= inst
.operands
[2].reg
;
13930 reject_bad_reg (Rd
);
13931 reject_bad_reg (Rn
);
13933 inst
.instruction
|= Rd
<< 8;
13934 inst
.instruction
|= inst
.operands
[1].imm
;
13935 inst
.instruction
|= Rn
<< 16;
13938 /* Checking the range of the branch offset (VAL) with NBITS bits
13939 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13941 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13943 gas_assert (nbits
> 0 && nbits
<= 32);
13946 int cmp
= (1 << (nbits
- 1));
13947 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13952 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13958 /* For branches in Armv8.1-M Mainline. */
13960 do_t_branch_future (void)
13962 unsigned long insn
= inst
.instruction
;
13964 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13965 if (inst
.operands
[0].hasreloc
== 0)
13967 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13968 as_bad (BAD_BRANCH_OFF
);
13970 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13974 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13975 inst
.relocs
[0].pc_rel
= 1;
13981 if (inst
.operands
[1].hasreloc
== 0)
13983 int val
= inst
.operands
[1].imm
;
13984 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13985 as_bad (BAD_BRANCH_OFF
);
13987 int immA
= (val
& 0x0001f000) >> 12;
13988 int immB
= (val
& 0x00000ffc) >> 2;
13989 int immC
= (val
& 0x00000002) >> 1;
13990 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13994 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13995 inst
.relocs
[1].pc_rel
= 1;
14000 if (inst
.operands
[1].hasreloc
== 0)
14002 int val
= inst
.operands
[1].imm
;
14003 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14004 as_bad (BAD_BRANCH_OFF
);
14006 int immA
= (val
& 0x0007f000) >> 12;
14007 int immB
= (val
& 0x00000ffc) >> 2;
14008 int immC
= (val
& 0x00000002) >> 1;
14009 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14013 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14014 inst
.relocs
[1].pc_rel
= 1;
14018 case T_MNEM_bfcsel
:
14020 if (inst
.operands
[1].hasreloc
== 0)
14022 int val
= inst
.operands
[1].imm
;
14023 int immA
= (val
& 0x00001000) >> 12;
14024 int immB
= (val
& 0x00000ffc) >> 2;
14025 int immC
= (val
& 0x00000002) >> 1;
14026 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14030 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14031 inst
.relocs
[1].pc_rel
= 1;
14035 if (inst
.operands
[2].hasreloc
== 0)
14037 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14038 int val2
= inst
.operands
[2].imm
;
14039 int val0
= inst
.operands
[0].imm
& 0x1f;
14040 int diff
= val2
- val0
;
14042 inst
.instruction
|= 1 << 17; /* T bit. */
14043 else if (diff
!= 2)
14044 as_bad (_("out of range label-relative fixup value"));
14048 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14049 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14050 inst
.relocs
[2].pc_rel
= 1;
14054 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14055 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14060 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14067 /* Helper function for do_t_loloop to handle relocations. */
14069 v8_1_loop_reloc (int is_le
)
14071 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14073 int value
= inst
.relocs
[0].exp
.X_add_number
;
14074 value
= (is_le
) ? -value
: value
;
14076 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14077 as_bad (BAD_BRANCH_OFF
);
14081 immh
= (value
& 0x00000ffc) >> 2;
14082 imml
= (value
& 0x00000002) >> 1;
14084 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14088 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14089 inst
.relocs
[0].pc_rel
= 1;
14093 /* To handle the Scalar Low Overhead Loop instructions
14094 in Armv8.1-M Mainline. */
14098 unsigned long insn
= inst
.instruction
;
14100 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14101 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14107 if (!inst
.operands
[0].present
)
14108 inst
.instruction
|= 1 << 21;
14110 v8_1_loop_reloc (TRUE
);
14114 v8_1_loop_reloc (FALSE
);
14115 /* Fall through. */
14117 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14118 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14125 /* MVE instruction encoder helpers. */
14126 #define M_MNEM_vabav 0xee800f01
14127 #define M_MNEM_vmladav 0xeef00e00
14128 #define M_MNEM_vmladava 0xeef00e20
14129 #define M_MNEM_vmladavx 0xeef01e00
14130 #define M_MNEM_vmladavax 0xeef01e20
14131 #define M_MNEM_vmlsdav 0xeef00e01
14132 #define M_MNEM_vmlsdava 0xeef00e21
14133 #define M_MNEM_vmlsdavx 0xeef01e01
14134 #define M_MNEM_vmlsdavax 0xeef01e21
14135 #define M_MNEM_vmullt 0xee011e00
14136 #define M_MNEM_vmullb 0xee010e00
14137 #define M_MNEM_vst20 0xfc801e00
14138 #define M_MNEM_vst21 0xfc801e20
14139 #define M_MNEM_vst40 0xfc801e01
14140 #define M_MNEM_vst41 0xfc801e21
14141 #define M_MNEM_vst42 0xfc801e41
14142 #define M_MNEM_vst43 0xfc801e61
14143 #define M_MNEM_vld20 0xfc901e00
14144 #define M_MNEM_vld21 0xfc901e20
14145 #define M_MNEM_vld40 0xfc901e01
14146 #define M_MNEM_vld41 0xfc901e21
14147 #define M_MNEM_vld42 0xfc901e41
14148 #define M_MNEM_vld43 0xfc901e61
14149 #define M_MNEM_vstrb 0xec000e00
14150 #define M_MNEM_vstrh 0xec000e10
14151 #define M_MNEM_vstrw 0xec000e40
14152 #define M_MNEM_vstrd 0xec000e50
14153 #define M_MNEM_vldrb 0xec100e00
14154 #define M_MNEM_vldrh 0xec100e10
14155 #define M_MNEM_vldrw 0xec100e40
14156 #define M_MNEM_vldrd 0xec100e50
14157 #define M_MNEM_vmovlt 0xeea01f40
14158 #define M_MNEM_vmovlb 0xeea00f40
14159 #define M_MNEM_vmovnt 0xfe311e81
14160 #define M_MNEM_vmovnb 0xfe310e81
14161 #define M_MNEM_vadc 0xee300f00
14162 #define M_MNEM_vadci 0xee301f00
14163 #define M_MNEM_vbrsr 0xfe011e60
14164 #define M_MNEM_vaddlv 0xee890f00
14165 #define M_MNEM_vaddlva 0xee890f20
14166 #define M_MNEM_vaddv 0xeef10f00
14167 #define M_MNEM_vaddva 0xeef10f20
14168 #define M_MNEM_vddup 0xee011f6e
14169 #define M_MNEM_vdwdup 0xee011f60
14170 #define M_MNEM_vidup 0xee010f6e
14171 #define M_MNEM_viwdup 0xee010f60
14172 #define M_MNEM_vmaxv 0xeee20f00
14173 #define M_MNEM_vmaxav 0xeee00f00
14174 #define M_MNEM_vminv 0xeee20f80
14175 #define M_MNEM_vminav 0xeee00f80
14176 #define M_MNEM_vmlaldav 0xee800e00
14177 #define M_MNEM_vmlaldava 0xee800e20
14178 #define M_MNEM_vmlaldavx 0xee801e00
14179 #define M_MNEM_vmlaldavax 0xee801e20
14180 #define M_MNEM_vmlsldav 0xee800e01
14181 #define M_MNEM_vmlsldava 0xee800e21
14182 #define M_MNEM_vmlsldavx 0xee801e01
14183 #define M_MNEM_vmlsldavax 0xee801e21
14184 #define M_MNEM_vrmlaldavhx 0xee801f00
14185 #define M_MNEM_vrmlaldavhax 0xee801f20
14186 #define M_MNEM_vrmlsldavh 0xfe800e01
14187 #define M_MNEM_vrmlsldavha 0xfe800e21
14188 #define M_MNEM_vrmlsldavhx 0xfe801e01
14189 #define M_MNEM_vrmlsldavhax 0xfe801e21
14191 /* Neon instruction encoder helpers. */
14193 /* Encodings for the different types for various Neon opcodes. */
14195 /* An "invalid" code for the following tables. */
14198 struct neon_tab_entry
14201 unsigned float_or_poly
;
14202 unsigned scalar_or_imm
;
14205 /* Map overloaded Neon opcodes to their respective encodings. */
14206 #define NEON_ENC_TAB \
14207 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14208 X(vabdl, 0x0800700, N_INV, N_INV), \
14209 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14210 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14211 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14212 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14213 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14214 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14215 X(vaddl, 0x0800000, N_INV, N_INV), \
14216 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14217 X(vsubl, 0x0800200, N_INV, N_INV), \
14218 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14219 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14220 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14221 /* Register variants of the following two instructions are encoded as
14222 vcge / vcgt with the operands reversed. */ \
14223 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14224 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14225 X(vfma, N_INV, 0x0000c10, N_INV), \
14226 X(vfms, N_INV, 0x0200c10, N_INV), \
14227 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14228 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14229 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14230 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14231 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14232 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14233 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14234 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14235 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14236 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14237 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14238 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14239 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14240 X(vshl, 0x0000400, N_INV, 0x0800510), \
14241 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14242 X(vand, 0x0000110, N_INV, 0x0800030), \
14243 X(vbic, 0x0100110, N_INV, 0x0800030), \
14244 X(veor, 0x1000110, N_INV, N_INV), \
14245 X(vorn, 0x0300110, N_INV, 0x0800010), \
14246 X(vorr, 0x0200110, N_INV, 0x0800010), \
14247 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14248 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14249 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14250 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14251 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14252 X(vst1, 0x0000000, 0x0800000, N_INV), \
14253 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14254 X(vst2, 0x0000100, 0x0800100, N_INV), \
14255 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14256 X(vst3, 0x0000200, 0x0800200, N_INV), \
14257 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14258 X(vst4, 0x0000300, 0x0800300, N_INV), \
14259 X(vmovn, 0x1b20200, N_INV, N_INV), \
14260 X(vtrn, 0x1b20080, N_INV, N_INV), \
14261 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14262 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14263 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14264 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14265 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14266 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14267 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14268 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14269 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14270 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14271 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14272 X(vseleq, 0xe000a00, N_INV, N_INV), \
14273 X(vselvs, 0xe100a00, N_INV, N_INV), \
14274 X(vselge, 0xe200a00, N_INV, N_INV), \
14275 X(vselgt, 0xe300a00, N_INV, N_INV), \
14276 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14277 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14278 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14279 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14280 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14281 X(aes, 0x3b00300, N_INV, N_INV), \
14282 X(sha3op, 0x2000c00, N_INV, N_INV), \
14283 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14284 X(sha2op, 0x3ba0380, N_INV, N_INV)
14288 #define X(OPC,I,F,S) N_MNEM_##OPC
14293 static const struct neon_tab_entry neon_enc_tab
[] =
14295 #define X(OPC,I,F,S) { (I), (F), (S) }
14300 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14301 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14302 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14303 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14304 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14305 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14306 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14307 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14308 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14309 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14310 #define NEON_ENC_SINGLE_(X) \
14311 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14312 #define NEON_ENC_DOUBLE_(X) \
14313 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14314 #define NEON_ENC_FPV8_(X) \
14315 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14317 #define NEON_ENCODE(type, inst) \
14320 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14321 inst.is_neon = 1; \
14325 #define check_neon_suffixes \
14328 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14330 as_bad (_("invalid neon suffix for non neon instruction")); \
14336 /* Define shapes for instruction operands. The following mnemonic characters
14337 are used in this table:
14339 F - VFP S<n> register
14340 D - Neon D<n> register
14341 Q - Neon Q<n> register
14345 L - D<n> register list
14347 This table is used to generate various data:
14348 - enumerations of the form NS_DDR to be used as arguments to
14350 - a table classifying shapes into single, double, quad, mixed.
14351 - a table used to drive neon_select_shape. */
14353 #define NEON_SHAPE_DEF \
14354 X(4, (R, R, Q, Q), QUAD), \
14355 X(4, (Q, R, R, I), QUAD), \
14356 X(4, (R, R, S, S), QUAD), \
14357 X(4, (S, S, R, R), QUAD), \
14358 X(3, (Q, R, I), QUAD), \
14359 X(3, (I, Q, Q), QUAD), \
14360 X(3, (I, Q, R), QUAD), \
14361 X(3, (R, Q, Q), QUAD), \
14362 X(3, (D, D, D), DOUBLE), \
14363 X(3, (Q, Q, Q), QUAD), \
14364 X(3, (D, D, I), DOUBLE), \
14365 X(3, (Q, Q, I), QUAD), \
14366 X(3, (D, D, S), DOUBLE), \
14367 X(3, (Q, Q, S), QUAD), \
14368 X(3, (Q, Q, R), QUAD), \
14369 X(3, (R, R, Q), QUAD), \
14370 X(2, (R, Q), QUAD), \
14371 X(2, (D, D), DOUBLE), \
14372 X(2, (Q, Q), QUAD), \
14373 X(2, (D, S), DOUBLE), \
14374 X(2, (Q, S), QUAD), \
14375 X(2, (D, R), DOUBLE), \
14376 X(2, (Q, R), QUAD), \
14377 X(2, (D, I), DOUBLE), \
14378 X(2, (Q, I), QUAD), \
14379 X(3, (D, L, D), DOUBLE), \
14380 X(2, (D, Q), MIXED), \
14381 X(2, (Q, D), MIXED), \
14382 X(3, (D, Q, I), MIXED), \
14383 X(3, (Q, D, I), MIXED), \
14384 X(3, (Q, D, D), MIXED), \
14385 X(3, (D, Q, Q), MIXED), \
14386 X(3, (Q, Q, D), MIXED), \
14387 X(3, (Q, D, S), MIXED), \
14388 X(3, (D, Q, S), MIXED), \
14389 X(4, (D, D, D, I), DOUBLE), \
14390 X(4, (Q, Q, Q, I), QUAD), \
14391 X(4, (D, D, S, I), DOUBLE), \
14392 X(4, (Q, Q, S, I), QUAD), \
14393 X(2, (F, F), SINGLE), \
14394 X(3, (F, F, F), SINGLE), \
14395 X(2, (F, I), SINGLE), \
14396 X(2, (F, D), MIXED), \
14397 X(2, (D, F), MIXED), \
14398 X(3, (F, F, I), MIXED), \
14399 X(4, (R, R, F, F), SINGLE), \
14400 X(4, (F, F, R, R), SINGLE), \
14401 X(3, (D, R, R), DOUBLE), \
14402 X(3, (R, R, D), DOUBLE), \
14403 X(2, (S, R), SINGLE), \
14404 X(2, (R, S), SINGLE), \
14405 X(2, (F, R), SINGLE), \
14406 X(2, (R, F), SINGLE), \
14407 /* Half float shape supported so far. */\
14408 X (2, (H, D), MIXED), \
14409 X (2, (D, H), MIXED), \
14410 X (2, (H, F), MIXED), \
14411 X (2, (F, H), MIXED), \
14412 X (2, (H, H), HALF), \
14413 X (2, (H, R), HALF), \
14414 X (2, (R, H), HALF), \
14415 X (2, (H, I), HALF), \
14416 X (3, (H, H, H), HALF), \
14417 X (3, (H, F, I), MIXED), \
14418 X (3, (F, H, I), MIXED), \
14419 X (3, (D, H, H), MIXED), \
14420 X (3, (D, H, S), MIXED)
14422 #define S2(A,B) NS_##A##B
14423 #define S3(A,B,C) NS_##A##B##C
14424 #define S4(A,B,C,D) NS_##A##B##C##D
14426 #define X(N, L, C) S##N L
14439 enum neon_shape_class
14448 #define X(N, L, C) SC_##C
14450 static enum neon_shape_class neon_shape_class
[] =
14469 /* Register widths of above. */
14470 static unsigned neon_shape_el_size
[] =
14482 struct neon_shape_info
14485 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14488 #define S2(A,B) { SE_##A, SE_##B }
14489 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14490 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14492 #define X(N, L, C) { N, S##N L }
14494 static struct neon_shape_info neon_shape_tab
[] =
14504 /* Bit masks used in type checking given instructions.
14505 'N_EQK' means the type must be the same as (or based on in some way) the key
14506 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14507 set, various other bits can be set as well in order to modify the meaning of
14508 the type constraint. */
14510 enum neon_type_mask
14534 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14535 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14536 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14537 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14538 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14539 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14540 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14541 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14542 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14543 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14544 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14546 N_MAX_NONSPECIAL
= N_P64
14549 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14551 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14552 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14553 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14554 #define N_S_32 (N_S8 | N_S16 | N_S32)
14555 #define N_F_16_32 (N_F16 | N_F32)
14556 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14557 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14558 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14559 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14560 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14561 #define N_F_MVE (N_F16 | N_F32)
14562 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14564 /* Pass this as the first type argument to neon_check_type to ignore types
14566 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14568 /* Select a "shape" for the current instruction (describing register types or
14569 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14570 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14571 function of operand parsing, so this function doesn't need to be called.
14572 Shapes should be listed in order of decreasing length. */
14574 static enum neon_shape
14575 neon_select_shape (enum neon_shape shape
, ...)
14578 enum neon_shape first_shape
= shape
;
14580 /* Fix missing optional operands. FIXME: we don't know at this point how
14581 many arguments we should have, so this makes the assumption that we have
14582 > 1. This is true of all current Neon opcodes, I think, but may not be
14583 true in the future. */
14584 if (!inst
.operands
[1].present
)
14585 inst
.operands
[1] = inst
.operands
[0];
14587 va_start (ap
, shape
);
14589 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14594 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14596 if (!inst
.operands
[j
].present
)
14602 switch (neon_shape_tab
[shape
].el
[j
])
14604 /* If a .f16, .16, .u16, .s16 type specifier is given over
14605 a VFP single precision register operand, it's essentially
14606 means only half of the register is used.
14608 If the type specifier is given after the mnemonics, the
14609 information is stored in inst.vectype. If the type specifier
14610 is given after register operand, the information is stored
14611 in inst.operands[].vectype.
14613 When there is only one type specifier, and all the register
14614 operands are the same type of hardware register, the type
14615 specifier applies to all register operands.
14617 If no type specifier is given, the shape is inferred from
14618 operand information.
14621 vadd.f16 s0, s1, s2: NS_HHH
14622 vabs.f16 s0, s1: NS_HH
14623 vmov.f16 s0, r1: NS_HR
14624 vmov.f16 r0, s1: NS_RH
14625 vcvt.f16 r0, s1: NS_RH
14626 vcvt.f16.s32 s2, s2, #29: NS_HFI
14627 vcvt.f16.s32 s2, s2: NS_HF
14630 if (!(inst
.operands
[j
].isreg
14631 && inst
.operands
[j
].isvec
14632 && inst
.operands
[j
].issingle
14633 && !inst
.operands
[j
].isquad
14634 && ((inst
.vectype
.elems
== 1
14635 && inst
.vectype
.el
[0].size
== 16)
14636 || (inst
.vectype
.elems
> 1
14637 && inst
.vectype
.el
[j
].size
== 16)
14638 || (inst
.vectype
.elems
== 0
14639 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14640 && inst
.operands
[j
].vectype
.size
== 16))))
14645 if (!(inst
.operands
[j
].isreg
14646 && inst
.operands
[j
].isvec
14647 && inst
.operands
[j
].issingle
14648 && !inst
.operands
[j
].isquad
14649 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14650 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14651 || (inst
.vectype
.elems
== 0
14652 && (inst
.operands
[j
].vectype
.size
== 32
14653 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14658 if (!(inst
.operands
[j
].isreg
14659 && inst
.operands
[j
].isvec
14660 && !inst
.operands
[j
].isquad
14661 && !inst
.operands
[j
].issingle
))
14666 if (!(inst
.operands
[j
].isreg
14667 && !inst
.operands
[j
].isvec
))
14672 if (!(inst
.operands
[j
].isreg
14673 && inst
.operands
[j
].isvec
14674 && inst
.operands
[j
].isquad
14675 && !inst
.operands
[j
].issingle
))
14680 if (!(!inst
.operands
[j
].isreg
14681 && !inst
.operands
[j
].isscalar
))
14686 if (!(!inst
.operands
[j
].isreg
14687 && inst
.operands
[j
].isscalar
))
14697 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14698 /* We've matched all the entries in the shape table, and we don't
14699 have any left over operands which have not been matched. */
14705 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14706 first_error (_("invalid instruction shape"));
14711 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14712 means the Q bit should be set). */
14715 neon_quad (enum neon_shape shape
)
14717 return neon_shape_class
[shape
] == SC_QUAD
;
14721 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14724 /* Allow modification to be made to types which are constrained to be
14725 based on the key element, based on bits set alongside N_EQK. */
14726 if ((typebits
& N_EQK
) != 0)
14728 if ((typebits
& N_HLF
) != 0)
14730 else if ((typebits
& N_DBL
) != 0)
14732 if ((typebits
& N_SGN
) != 0)
14733 *g_type
= NT_signed
;
14734 else if ((typebits
& N_UNS
) != 0)
14735 *g_type
= NT_unsigned
;
14736 else if ((typebits
& N_INT
) != 0)
14737 *g_type
= NT_integer
;
14738 else if ((typebits
& N_FLT
) != 0)
14739 *g_type
= NT_float
;
14740 else if ((typebits
& N_SIZ
) != 0)
14741 *g_type
= NT_untyped
;
14745 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14746 operand type, i.e. the single type specified in a Neon instruction when it
14747 is the only one given. */
14749 static struct neon_type_el
14750 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14752 struct neon_type_el dest
= *key
;
14754 gas_assert ((thisarg
& N_EQK
) != 0);
14756 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14761 /* Convert Neon type and size into compact bitmask representation. */
14763 static enum neon_type_mask
14764 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14771 case 8: return N_8
;
14772 case 16: return N_16
;
14773 case 32: return N_32
;
14774 case 64: return N_64
;
14782 case 8: return N_I8
;
14783 case 16: return N_I16
;
14784 case 32: return N_I32
;
14785 case 64: return N_I64
;
14793 case 16: return N_F16
;
14794 case 32: return N_F32
;
14795 case 64: return N_F64
;
14803 case 8: return N_P8
;
14804 case 16: return N_P16
;
14805 case 64: return N_P64
;
14813 case 8: return N_S8
;
14814 case 16: return N_S16
;
14815 case 32: return N_S32
;
14816 case 64: return N_S64
;
14824 case 8: return N_U8
;
14825 case 16: return N_U16
;
14826 case 32: return N_U32
;
14827 case 64: return N_U64
;
14838 /* Convert compact Neon bitmask type representation to a type and size. Only
14839 handles the case where a single bit is set in the mask. */
14842 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14843 enum neon_type_mask mask
)
14845 if ((mask
& N_EQK
) != 0)
14848 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14850 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14852 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14854 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14859 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14861 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14862 *type
= NT_unsigned
;
14863 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14864 *type
= NT_integer
;
14865 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14866 *type
= NT_untyped
;
14867 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14869 else if ((mask
& (N_F_ALL
)) != 0)
14877 /* Modify a bitmask of allowed types. This is only needed for type
14881 modify_types_allowed (unsigned allowed
, unsigned mods
)
14884 enum neon_el_type type
;
14890 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14892 if (el_type_of_type_chk (&type
, &size
,
14893 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14895 neon_modify_type_size (mods
, &type
, &size
);
14896 destmask
|= type_chk_of_el_type (type
, size
);
14903 /* Check type and return type classification.
14904 The manual states (paraphrase): If one datatype is given, it indicates the
14906 - the second operand, if there is one
14907 - the operand, if there is no second operand
14908 - the result, if there are no operands.
14909 This isn't quite good enough though, so we use a concept of a "key" datatype
14910 which is set on a per-instruction basis, which is the one which matters when
14911 only one data type is written.
14912 Note: this function has side-effects (e.g. filling in missing operands). All
14913 Neon instructions should call it before performing bit encoding. */
14915 static struct neon_type_el
14916 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14919 unsigned i
, pass
, key_el
= 0;
14920 unsigned types
[NEON_MAX_TYPE_ELS
];
14921 enum neon_el_type k_type
= NT_invtype
;
14922 unsigned k_size
= -1u;
14923 struct neon_type_el badtype
= {NT_invtype
, -1};
14924 unsigned key_allowed
= 0;
14926 /* Optional registers in Neon instructions are always (not) in operand 1.
14927 Fill in the missing operand here, if it was omitted. */
14928 if (els
> 1 && !inst
.operands
[1].present
)
14929 inst
.operands
[1] = inst
.operands
[0];
14931 /* Suck up all the varargs. */
14933 for (i
= 0; i
< els
; i
++)
14935 unsigned thisarg
= va_arg (ap
, unsigned);
14936 if (thisarg
== N_IGNORE_TYPE
)
14941 types
[i
] = thisarg
;
14942 if ((thisarg
& N_KEY
) != 0)
14947 if (inst
.vectype
.elems
> 0)
14948 for (i
= 0; i
< els
; i
++)
14949 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14951 first_error (_("types specified in both the mnemonic and operands"));
14955 /* Duplicate inst.vectype elements here as necessary.
14956 FIXME: No idea if this is exactly the same as the ARM assembler,
14957 particularly when an insn takes one register and one non-register
14959 if (inst
.vectype
.elems
== 1 && els
> 1)
14962 inst
.vectype
.elems
= els
;
14963 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14964 for (j
= 0; j
< els
; j
++)
14966 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14969 else if (inst
.vectype
.elems
== 0 && els
> 0)
14972 /* No types were given after the mnemonic, so look for types specified
14973 after each operand. We allow some flexibility here; as long as the
14974 "key" operand has a type, we can infer the others. */
14975 for (j
= 0; j
< els
; j
++)
14976 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14977 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14979 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14981 for (j
= 0; j
< els
; j
++)
14982 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14983 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14988 first_error (_("operand types can't be inferred"));
14992 else if (inst
.vectype
.elems
!= els
)
14994 first_error (_("type specifier has the wrong number of parts"));
14998 for (pass
= 0; pass
< 2; pass
++)
15000 for (i
= 0; i
< els
; i
++)
15002 unsigned thisarg
= types
[i
];
15003 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15004 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15005 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15006 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15008 /* Decay more-specific signed & unsigned types to sign-insensitive
15009 integer types if sign-specific variants are unavailable. */
15010 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15011 && (types_allowed
& N_SU_ALL
) == 0)
15012 g_type
= NT_integer
;
15014 /* If only untyped args are allowed, decay any more specific types to
15015 them. Some instructions only care about signs for some element
15016 sizes, so handle that properly. */
15017 if (((types_allowed
& N_UNT
) == 0)
15018 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15019 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15020 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15021 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15022 g_type
= NT_untyped
;
15026 if ((thisarg
& N_KEY
) != 0)
15030 key_allowed
= thisarg
& ~N_KEY
;
15032 /* Check architecture constraint on FP16 extension. */
15034 && k_type
== NT_float
15035 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15037 inst
.error
= _(BAD_FP16
);
15044 if ((thisarg
& N_VFP
) != 0)
15046 enum neon_shape_el regshape
;
15047 unsigned regwidth
, match
;
15049 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15052 first_error (_("invalid instruction shape"));
15055 regshape
= neon_shape_tab
[ns
].el
[i
];
15056 regwidth
= neon_shape_el_size
[regshape
];
15058 /* In VFP mode, operands must match register widths. If we
15059 have a key operand, use its width, else use the width of
15060 the current operand. */
15066 /* FP16 will use a single precision register. */
15067 if (regwidth
== 32 && match
== 16)
15069 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15073 inst
.error
= _(BAD_FP16
);
15078 if (regwidth
!= match
)
15080 first_error (_("operand size must match register width"));
15085 if ((thisarg
& N_EQK
) == 0)
15087 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15089 if ((given_type
& types_allowed
) == 0)
15091 first_error (BAD_SIMD_TYPE
);
15097 enum neon_el_type mod_k_type
= k_type
;
15098 unsigned mod_k_size
= k_size
;
15099 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15100 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15102 first_error (_("inconsistent types in Neon instruction"));
15110 return inst
.vectype
.el
[key_el
];
15113 /* Neon-style VFP instruction forwarding. */
15115 /* Thumb VFP instructions have 0xE in the condition field. */
15118 do_vfp_cond_or_thumb (void)
15123 inst
.instruction
|= 0xe0000000;
15125 inst
.instruction
|= inst
.cond
<< 28;
15128 /* Look up and encode a simple mnemonic, for use as a helper function for the
15129 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15130 etc. It is assumed that operand parsing has already been done, and that the
15131 operands are in the form expected by the given opcode (this isn't necessarily
15132 the same as the form in which they were parsed, hence some massaging must
15133 take place before this function is called).
15134 Checks current arch version against that in the looked-up opcode. */
15137 do_vfp_nsyn_opcode (const char *opname
)
15139 const struct asm_opcode
*opcode
;
15141 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15146 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15147 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15154 inst
.instruction
= opcode
->tvalue
;
15155 opcode
->tencode ();
15159 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15160 opcode
->aencode ();
15165 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15167 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15169 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15172 do_vfp_nsyn_opcode ("fadds");
15174 do_vfp_nsyn_opcode ("fsubs");
15176 /* ARMv8.2 fp16 instruction. */
15178 do_scalar_fp16_v82_encode ();
15183 do_vfp_nsyn_opcode ("faddd");
15185 do_vfp_nsyn_opcode ("fsubd");
15189 /* Check operand types to see if this is a VFP instruction, and if so call
15193 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15195 enum neon_shape rs
;
15196 struct neon_type_el et
;
15201 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15202 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15206 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15207 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15208 N_F_ALL
| N_KEY
| N_VFP
);
15215 if (et
.type
!= NT_invtype
)
15226 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15228 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15230 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15233 do_vfp_nsyn_opcode ("fmacs");
15235 do_vfp_nsyn_opcode ("fnmacs");
15237 /* ARMv8.2 fp16 instruction. */
15239 do_scalar_fp16_v82_encode ();
15244 do_vfp_nsyn_opcode ("fmacd");
15246 do_vfp_nsyn_opcode ("fnmacd");
15251 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15253 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15255 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15258 do_vfp_nsyn_opcode ("ffmas");
15260 do_vfp_nsyn_opcode ("ffnmas");
15262 /* ARMv8.2 fp16 instruction. */
15264 do_scalar_fp16_v82_encode ();
15269 do_vfp_nsyn_opcode ("ffmad");
15271 do_vfp_nsyn_opcode ("ffnmad");
15276 do_vfp_nsyn_mul (enum neon_shape rs
)
15278 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15280 do_vfp_nsyn_opcode ("fmuls");
15282 /* ARMv8.2 fp16 instruction. */
15284 do_scalar_fp16_v82_encode ();
15287 do_vfp_nsyn_opcode ("fmuld");
15291 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15293 int is_neg
= (inst
.instruction
& 0x80) != 0;
15294 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15296 if (rs
== NS_FF
|| rs
== NS_HH
)
15299 do_vfp_nsyn_opcode ("fnegs");
15301 do_vfp_nsyn_opcode ("fabss");
15303 /* ARMv8.2 fp16 instruction. */
15305 do_scalar_fp16_v82_encode ();
15310 do_vfp_nsyn_opcode ("fnegd");
15312 do_vfp_nsyn_opcode ("fabsd");
15316 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15317 insns belong to Neon, and are handled elsewhere. */
15320 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15322 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15326 do_vfp_nsyn_opcode ("fldmdbs");
15328 do_vfp_nsyn_opcode ("fldmias");
15333 do_vfp_nsyn_opcode ("fstmdbs");
15335 do_vfp_nsyn_opcode ("fstmias");
15340 do_vfp_nsyn_sqrt (void)
15342 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15343 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15345 if (rs
== NS_FF
|| rs
== NS_HH
)
15347 do_vfp_nsyn_opcode ("fsqrts");
15349 /* ARMv8.2 fp16 instruction. */
15351 do_scalar_fp16_v82_encode ();
15354 do_vfp_nsyn_opcode ("fsqrtd");
15358 do_vfp_nsyn_div (void)
15360 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15361 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15362 N_F_ALL
| N_KEY
| N_VFP
);
15364 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15366 do_vfp_nsyn_opcode ("fdivs");
15368 /* ARMv8.2 fp16 instruction. */
15370 do_scalar_fp16_v82_encode ();
15373 do_vfp_nsyn_opcode ("fdivd");
15377 do_vfp_nsyn_nmul (void)
15379 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15380 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15381 N_F_ALL
| N_KEY
| N_VFP
);
15383 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15385 NEON_ENCODE (SINGLE
, inst
);
15386 do_vfp_sp_dyadic ();
15388 /* ARMv8.2 fp16 instruction. */
15390 do_scalar_fp16_v82_encode ();
15394 NEON_ENCODE (DOUBLE
, inst
);
15395 do_vfp_dp_rd_rn_rm ();
15397 do_vfp_cond_or_thumb ();
15401 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15405 neon_logbits (unsigned x
)
15407 return ffs (x
) - 4;
15410 #define LOW4(R) ((R) & 0xf)
15411 #define HI1(R) (((R) >> 4) & 1)
15414 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15419 first_error (BAD_EL_TYPE
);
15422 switch (inst
.operands
[0].imm
)
15425 first_error (_("invalid condition"));
15447 /* only accept eq and ne. */
15448 if (inst
.operands
[0].imm
> 1)
15450 first_error (_("invalid condition"));
15453 return inst
.operands
[0].imm
;
15455 if (inst
.operands
[0].imm
== 0x2)
15457 else if (inst
.operands
[0].imm
== 0x8)
15461 first_error (_("invalid condition"));
15465 switch (inst
.operands
[0].imm
)
15468 first_error (_("invalid condition"));
15484 /* Should be unreachable. */
15491 /* We are dealing with a vector predicated block. */
15492 if (inst
.operands
[0].present
)
15494 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15495 struct neon_type_el et
15496 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15499 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15501 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15503 if (et
.type
== NT_invtype
)
15506 if (et
.type
== NT_float
)
15508 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15510 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15511 inst
.instruction
|= (et
.size
== 16) << 28;
15512 inst
.instruction
|= 0x3 << 20;
15516 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15518 inst
.instruction
|= 1 << 28;
15519 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15522 if (inst
.operands
[2].isquad
)
15524 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15525 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15526 inst
.instruction
|= (fcond
& 0x2) >> 1;
15530 if (inst
.operands
[2].reg
== REG_SP
)
15531 as_tsktsk (MVE_BAD_SP
);
15532 inst
.instruction
|= 1 << 6;
15533 inst
.instruction
|= (fcond
& 0x2) << 4;
15534 inst
.instruction
|= inst
.operands
[2].reg
;
15536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15537 inst
.instruction
|= (fcond
& 0x4) << 10;
15538 inst
.instruction
|= (fcond
& 0x1) << 7;
15541 set_pred_insn_type (VPT_INSN
);
15543 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15544 | ((inst
.instruction
& 0xe000) >> 13);
15545 now_pred
.warn_deprecated
= FALSE
;
15546 now_pred
.type
= VECTOR_PRED
;
15553 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15554 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15555 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15556 if (!inst
.operands
[2].present
)
15557 first_error (_("MVE vector or ARM register expected"));
15558 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15560 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15561 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15562 && inst
.operands
[1].isquad
)
15564 inst
.instruction
= N_MNEM_vcmp
;
15568 if (inst
.cond
> COND_ALWAYS
)
15569 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15571 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15573 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15574 struct neon_type_el et
15575 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15578 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15579 && !inst
.operands
[2].iszr
, BAD_PC
);
15581 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15583 inst
.instruction
= 0xee010f00;
15584 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15585 inst
.instruction
|= (fcond
& 0x4) << 10;
15586 inst
.instruction
|= (fcond
& 0x1) << 7;
15587 if (et
.type
== NT_float
)
15589 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15591 inst
.instruction
|= (et
.size
== 16) << 28;
15592 inst
.instruction
|= 0x3 << 20;
15596 inst
.instruction
|= 1 << 28;
15597 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15599 if (inst
.operands
[2].isquad
)
15601 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15602 inst
.instruction
|= (fcond
& 0x2) >> 1;
15603 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15607 if (inst
.operands
[2].reg
== REG_SP
)
15608 as_tsktsk (MVE_BAD_SP
);
15609 inst
.instruction
|= 1 << 6;
15610 inst
.instruction
|= (fcond
& 0x2) << 4;
15611 inst
.instruction
|= inst
.operands
[2].reg
;
15619 do_mve_vmaxa_vmina (void)
15621 if (inst
.cond
> COND_ALWAYS
)
15622 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15624 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15626 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15627 struct neon_type_el et
15628 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15631 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15632 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15633 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15634 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15639 do_mve_vfmas (void)
15641 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15642 struct neon_type_el et
15643 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15645 if (inst
.cond
> COND_ALWAYS
)
15646 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15648 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15650 if (inst
.operands
[2].reg
== REG_SP
)
15651 as_tsktsk (MVE_BAD_SP
);
15652 else if (inst
.operands
[2].reg
== REG_PC
)
15653 as_tsktsk (MVE_BAD_PC
);
15655 inst
.instruction
|= (et
.size
== 16) << 28;
15656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15658 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15659 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15660 inst
.instruction
|= inst
.operands
[2].reg
;
15665 do_mve_viddup (void)
15667 if (inst
.cond
> COND_ALWAYS
)
15668 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15670 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15672 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15673 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15674 _("immediate must be either 1, 2, 4 or 8"));
15676 enum neon_shape rs
;
15677 struct neon_type_el et
;
15679 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15681 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15682 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15687 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15688 if (inst
.operands
[2].reg
== REG_SP
)
15689 as_tsktsk (MVE_BAD_SP
);
15690 else if (inst
.operands
[2].reg
== REG_PC
)
15691 first_error (BAD_PC
);
15693 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15694 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15695 Rm
= inst
.operands
[2].reg
>> 1;
15697 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15698 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15699 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15700 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15701 inst
.instruction
|= (imm
> 2) << 7;
15702 inst
.instruction
|= Rm
<< 1;
15703 inst
.instruction
|= (imm
== 2 || imm
== 8);
15708 do_mve_vmlas (void)
15710 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15711 struct neon_type_el et
15712 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15714 if (inst
.operands
[2].reg
== REG_PC
)
15715 as_tsktsk (MVE_BAD_PC
);
15716 else if (inst
.operands
[2].reg
== REG_SP
)
15717 as_tsktsk (MVE_BAD_SP
);
15719 if (inst
.cond
> COND_ALWAYS
)
15720 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15722 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15724 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15725 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15726 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15727 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15729 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15730 inst
.instruction
|= inst
.operands
[2].reg
;
15735 do_mve_vmaxnma_vminnma (void)
15737 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15738 struct neon_type_el et
15739 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15741 if (inst
.cond
> COND_ALWAYS
)
15742 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15744 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15746 inst
.instruction
|= (et
.size
== 16) << 28;
15747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15748 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15750 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15755 do_mve_vcmul (void)
15757 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15758 struct neon_type_el et
15759 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15761 if (inst
.cond
> COND_ALWAYS
)
15762 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15764 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15766 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15767 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15768 _("immediate out of range"));
15770 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15771 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15772 as_tsktsk (BAD_MVE_SRCDEST
);
15774 inst
.instruction
|= (et
.size
== 32) << 28;
15775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15777 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15778 inst
.instruction
|= (rot
> 90) << 12;
15779 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15780 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15781 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15782 inst
.instruction
|= (rot
== 90 || rot
== 270);
15787 do_vfp_nsyn_cmp (void)
15789 enum neon_shape rs
;
15790 if (!inst
.operands
[0].isreg
)
15797 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15802 if (inst
.operands
[1].isreg
)
15804 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15805 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15807 if (rs
== NS_FF
|| rs
== NS_HH
)
15809 NEON_ENCODE (SINGLE
, inst
);
15810 do_vfp_sp_monadic ();
15814 NEON_ENCODE (DOUBLE
, inst
);
15815 do_vfp_dp_rd_rm ();
15820 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15821 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15823 switch (inst
.instruction
& 0x0fffffff)
15826 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15829 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15835 if (rs
== NS_FI
|| rs
== NS_HI
)
15837 NEON_ENCODE (SINGLE
, inst
);
15838 do_vfp_sp_compare_z ();
15842 NEON_ENCODE (DOUBLE
, inst
);
15846 do_vfp_cond_or_thumb ();
15848 /* ARMv8.2 fp16 instruction. */
15849 if (rs
== NS_HI
|| rs
== NS_HH
)
15850 do_scalar_fp16_v82_encode ();
15854 nsyn_insert_sp (void)
15856 inst
.operands
[1] = inst
.operands
[0];
15857 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15858 inst
.operands
[0].reg
= REG_SP
;
15859 inst
.operands
[0].isreg
= 1;
15860 inst
.operands
[0].writeback
= 1;
15861 inst
.operands
[0].present
= 1;
15865 do_vfp_nsyn_push (void)
15869 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15870 _("register list must contain at least 1 and at most 16 "
15873 if (inst
.operands
[1].issingle
)
15874 do_vfp_nsyn_opcode ("fstmdbs");
15876 do_vfp_nsyn_opcode ("fstmdbd");
15880 do_vfp_nsyn_pop (void)
15884 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15885 _("register list must contain at least 1 and at most 16 "
15888 if (inst
.operands
[1].issingle
)
15889 do_vfp_nsyn_opcode ("fldmias");
15891 do_vfp_nsyn_opcode ("fldmiad");
15894 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15895 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15898 neon_dp_fixup (struct arm_it
* insn
)
15900 unsigned int i
= insn
->instruction
;
15905 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15916 insn
->instruction
= i
;
15920 mve_encode_qqr (int size
, int U
, int fp
)
15922 if (inst
.operands
[2].reg
== REG_SP
)
15923 as_tsktsk (MVE_BAD_SP
);
15924 else if (inst
.operands
[2].reg
== REG_PC
)
15925 as_tsktsk (MVE_BAD_PC
);
15930 if (((unsigned)inst
.instruction
) == 0xd00)
15931 inst
.instruction
= 0xee300f40;
15933 else if (((unsigned)inst
.instruction
) == 0x200d00)
15934 inst
.instruction
= 0xee301f40;
15936 else if (((unsigned)inst
.instruction
) == 0x1000d10)
15937 inst
.instruction
= 0xee310e60;
15939 /* Setting size which is 1 for F16 and 0 for F32. */
15940 inst
.instruction
|= (size
== 16) << 28;
15945 if (((unsigned)inst
.instruction
) == 0x800)
15946 inst
.instruction
= 0xee010f40;
15948 else if (((unsigned)inst
.instruction
) == 0x1000800)
15949 inst
.instruction
= 0xee011f40;
15951 else if (((unsigned)inst
.instruction
) == 0)
15952 inst
.instruction
= 0xee000f40;
15954 else if (((unsigned)inst
.instruction
) == 0x200)
15955 inst
.instruction
= 0xee001f40;
15957 else if (((unsigned)inst
.instruction
) == 0x900)
15958 inst
.instruction
= 0xee010e40;
15960 else if (((unsigned)inst
.instruction
) == 0x910)
15961 inst
.instruction
= 0xee011e60;
15963 else if (((unsigned)inst
.instruction
) == 0x10)
15964 inst
.instruction
= 0xee000f60;
15966 else if (((unsigned)inst
.instruction
) == 0x210)
15967 inst
.instruction
= 0xee001f60;
15970 inst
.instruction
|= U
<< 28;
15972 /* Setting bits for size. */
15973 inst
.instruction
|= neon_logbits (size
) << 20;
15975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15976 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15978 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15979 inst
.instruction
|= inst
.operands
[2].reg
;
15984 mve_encode_rqq (unsigned bit28
, unsigned size
)
15986 inst
.instruction
|= bit28
<< 28;
15987 inst
.instruction
|= neon_logbits (size
) << 20;
15988 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15990 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15991 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15992 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15997 mve_encode_qqq (int ubit
, int size
)
16000 inst
.instruction
|= (ubit
!= 0) << 28;
16001 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16002 inst
.instruction
|= neon_logbits (size
) << 20;
16003 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16004 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16005 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16006 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16007 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16013 mve_encode_rq (unsigned bit28
, unsigned size
)
16015 inst
.instruction
|= bit28
<< 28;
16016 inst
.instruction
|= neon_logbits (size
) << 18;
16017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16018 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16023 mve_encode_rrqq (unsigned U
, unsigned size
)
16025 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16027 inst
.instruction
|= U
<< 28;
16028 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16029 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16030 inst
.instruction
|= (size
== 32) << 16;
16031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16032 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16033 inst
.instruction
|= inst
.operands
[3].reg
;
16037 /* Encode insns with bit pattern:
16039 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16040 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16042 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16043 different meaning for some instruction. */
16046 neon_three_same (int isquad
, int ubit
, int size
)
16048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16049 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16050 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16051 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16052 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16053 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16054 inst
.instruction
|= (isquad
!= 0) << 6;
16055 inst
.instruction
|= (ubit
!= 0) << 24;
16057 inst
.instruction
|= neon_logbits (size
) << 20;
16059 neon_dp_fixup (&inst
);
16062 /* Encode instructions of the form:
16064 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16065 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16067 Don't write size if SIZE == -1. */
16070 neon_two_same (int qbit
, int ubit
, int size
)
16072 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16073 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16074 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16075 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16076 inst
.instruction
|= (qbit
!= 0) << 6;
16077 inst
.instruction
|= (ubit
!= 0) << 24;
16080 inst
.instruction
|= neon_logbits (size
) << 18;
16082 neon_dp_fixup (&inst
);
16085 enum vfp_or_neon_is_neon_bits
16088 NEON_CHECK_ARCH
= 2,
16089 NEON_CHECK_ARCH8
= 4
16092 /* Call this function if an instruction which may have belonged to the VFP or
16093 Neon instruction sets, but turned out to be a Neon instruction (due to the
16094 operand types involved, etc.). We have to check and/or fix-up a couple of
16097 - Make sure the user hasn't attempted to make a Neon instruction
16099 - Alter the value in the condition code field if necessary.
16100 - Make sure that the arch supports Neon instructions.
16102 Which of these operations take place depends on bits from enum
16103 vfp_or_neon_is_neon_bits.
16105 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16106 current instruction's condition is COND_ALWAYS, the condition field is
16107 changed to inst.uncond_value. This is necessary because instructions shared
16108 between VFP and Neon may be conditional for the VFP variants only, and the
16109 unconditional Neon version must have, e.g., 0xF in the condition field. */
16112 vfp_or_neon_is_neon (unsigned check
)
16114 /* Conditions are always legal in Thumb mode (IT blocks). */
16115 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16117 if (inst
.cond
!= COND_ALWAYS
)
16119 first_error (_(BAD_COND
));
16122 if (inst
.uncond_value
!= -1)
16123 inst
.instruction
|= inst
.uncond_value
<< 28;
16127 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16128 || ((check
& NEON_CHECK_ARCH8
)
16129 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16131 first_error (_(BAD_FPU
));
16139 check_simd_pred_availability (int fp
, unsigned check
)
16141 if (inst
.cond
> COND_ALWAYS
)
16143 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16145 inst
.error
= BAD_FPU
;
16148 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16150 else if (inst
.cond
< COND_ALWAYS
)
16152 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16153 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16154 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16159 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16160 && vfp_or_neon_is_neon (check
) == FAIL
)
16163 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16164 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16169 /* Neon instruction encoders, in approximate order of appearance. */
16172 do_neon_dyadic_i_su (void)
16174 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16177 enum neon_shape rs
;
16178 struct neon_type_el et
;
16179 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16180 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16182 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16184 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16188 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16190 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16194 do_neon_dyadic_i64_su (void)
16196 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16198 enum neon_shape rs
;
16199 struct neon_type_el et
;
16200 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16202 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16203 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16207 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16208 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16211 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16213 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16217 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16220 unsigned size
= et
.size
>> 3;
16221 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16222 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16223 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16224 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16225 inst
.instruction
|= (isquad
!= 0) << 6;
16226 inst
.instruction
|= immbits
<< 16;
16227 inst
.instruction
|= (size
>> 3) << 7;
16228 inst
.instruction
|= (size
& 0x7) << 19;
16230 inst
.instruction
|= (uval
!= 0) << 24;
16232 neon_dp_fixup (&inst
);
16236 do_neon_shl_imm (void)
16238 if (!inst
.operands
[2].isreg
)
16240 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16241 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16242 int imm
= inst
.operands
[2].imm
;
16244 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16245 _("immediate out of range for shift"));
16246 NEON_ENCODE (IMMED
, inst
);
16247 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16251 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16252 struct neon_type_el et
= neon_check_type (3, rs
,
16253 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16256 /* VSHL/VQSHL 3-register variants have syntax such as:
16258 whereas other 3-register operations encoded by neon_three_same have
16261 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
16263 tmp
= inst
.operands
[2].reg
;
16264 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16265 inst
.operands
[1].reg
= tmp
;
16266 NEON_ENCODE (INTEGER
, inst
);
16267 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16272 do_neon_qshl_imm (void)
16274 if (!inst
.operands
[2].isreg
)
16276 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16277 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16278 int imm
= inst
.operands
[2].imm
;
16280 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16281 _("immediate out of range for shift"));
16282 NEON_ENCODE (IMMED
, inst
);
16283 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16287 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16288 struct neon_type_el et
= neon_check_type (3, rs
,
16289 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16292 /* See note in do_neon_shl_imm. */
16293 tmp
= inst
.operands
[2].reg
;
16294 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16295 inst
.operands
[1].reg
= tmp
;
16296 NEON_ENCODE (INTEGER
, inst
);
16297 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16302 do_neon_rshl (void)
16304 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16305 struct neon_type_el et
= neon_check_type (3, rs
,
16306 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16309 tmp
= inst
.operands
[2].reg
;
16310 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16311 inst
.operands
[1].reg
= tmp
;
16312 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16316 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16318 /* Handle .I8 pseudo-instructions. */
16321 /* Unfortunately, this will make everything apart from zero out-of-range.
16322 FIXME is this the intended semantics? There doesn't seem much point in
16323 accepting .I8 if so. */
16324 immediate
|= immediate
<< 8;
16330 if (immediate
== (immediate
& 0x000000ff))
16332 *immbits
= immediate
;
16335 else if (immediate
== (immediate
& 0x0000ff00))
16337 *immbits
= immediate
>> 8;
16340 else if (immediate
== (immediate
& 0x00ff0000))
16342 *immbits
= immediate
>> 16;
16345 else if (immediate
== (immediate
& 0xff000000))
16347 *immbits
= immediate
>> 24;
16350 if ((immediate
& 0xffff) != (immediate
>> 16))
16351 goto bad_immediate
;
16352 immediate
&= 0xffff;
16355 if (immediate
== (immediate
& 0x000000ff))
16357 *immbits
= immediate
;
16360 else if (immediate
== (immediate
& 0x0000ff00))
16362 *immbits
= immediate
>> 8;
16367 first_error (_("immediate value out of range"));
16372 do_neon_logic (void)
16374 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16376 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16378 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16381 else if (rs
!= NS_QQQ
16382 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16383 first_error (BAD_FPU
);
16385 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16386 /* U bit and size field were set as part of the bitmask. */
16387 NEON_ENCODE (INTEGER
, inst
);
16388 neon_three_same (neon_quad (rs
), 0, -1);
16392 const int three_ops_form
= (inst
.operands
[2].present
16393 && !inst
.operands
[2].isreg
);
16394 const int immoperand
= (three_ops_form
? 2 : 1);
16395 enum neon_shape rs
= (three_ops_form
16396 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16397 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16398 /* Because neon_select_shape makes the second operand a copy of the first
16399 if the second operand is not present. */
16401 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16404 else if (rs
!= NS_QQI
16405 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16406 first_error (BAD_FPU
);
16408 struct neon_type_el et
;
16409 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16410 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16412 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16415 if (et
.type
== NT_invtype
)
16417 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16422 if (three_ops_form
)
16423 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16424 _("first and second operands shall be the same register"));
16426 NEON_ENCODE (IMMED
, inst
);
16428 immbits
= inst
.operands
[immoperand
].imm
;
16431 /* .i64 is a pseudo-op, so the immediate must be a repeating
16433 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16434 inst
.operands
[immoperand
].reg
: 0))
16436 /* Set immbits to an invalid constant. */
16437 immbits
= 0xdeadbeef;
16444 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16448 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16452 /* Pseudo-instruction for VBIC. */
16453 neon_invert_size (&immbits
, 0, et
.size
);
16454 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16458 /* Pseudo-instruction for VORR. */
16459 neon_invert_size (&immbits
, 0, et
.size
);
16460 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16470 inst
.instruction
|= neon_quad (rs
) << 6;
16471 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16472 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16473 inst
.instruction
|= cmode
<< 8;
16474 neon_write_immbits (immbits
);
16476 neon_dp_fixup (&inst
);
16481 do_neon_bitfield (void)
16483 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16484 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16485 neon_three_same (neon_quad (rs
), 0, -1);
16489 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16492 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16493 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16495 if (et
.type
== NT_float
)
16497 NEON_ENCODE (FLOAT
, inst
);
16499 mve_encode_qqr (et
.size
, 0, 1);
16501 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16505 NEON_ENCODE (INTEGER
, inst
);
16507 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16509 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16515 do_neon_dyadic_if_su_d (void)
16517 /* This version only allow D registers, but that constraint is enforced during
16518 operand parsing so we don't need to do anything extra here. */
16519 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16523 do_neon_dyadic_if_i_d (void)
16525 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16526 affected if we specify unsigned args. */
16527 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16531 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16533 constraint (size
< 32, BAD_ADDR_MODE
);
16534 constraint (size
!= elsize
, BAD_EL_TYPE
);
16535 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16536 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16537 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16538 _("destination register and offset register may not be the"
16541 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16548 constraint ((imm
% (size
/ 8) != 0)
16549 || imm
> (0x7f << neon_logbits (size
)),
16550 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16551 " range of +/-[0,508]")
16552 : _("immediate must be a multiple of 8 in the"
16553 " range of +/-[0,1016]"));
16554 inst
.instruction
|= 0x11 << 24;
16555 inst
.instruction
|= add
<< 23;
16556 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16557 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16558 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16559 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16560 inst
.instruction
|= 1 << 12;
16561 inst
.instruction
|= (size
== 64) << 8;
16562 inst
.instruction
&= 0xffffff00;
16563 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16564 inst
.instruction
|= imm
>> neon_logbits (size
);
16568 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16570 unsigned os
= inst
.operands
[1].imm
>> 5;
16571 constraint (os
!= 0 && size
== 8,
16572 _("can not shift offsets when accessing less than half-word"));
16573 constraint (os
&& os
!= neon_logbits (size
),
16574 _("shift immediate must be 1, 2 or 3 for half-word, word"
16575 " or double-word accesses respectively"));
16576 if (inst
.operands
[1].reg
== REG_PC
)
16577 as_tsktsk (MVE_BAD_PC
);
16582 constraint (elsize
>= 64, BAD_EL_TYPE
);
16585 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16589 constraint (elsize
!= size
, BAD_EL_TYPE
);
16594 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16598 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16599 _("destination register and offset register may not be"
16601 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16603 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16604 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16605 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16609 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16612 inst
.instruction
|= 1 << 23;
16613 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16615 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16616 inst
.instruction
|= neon_logbits (elsize
) << 7;
16617 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16618 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16619 inst
.instruction
|= !!os
;
16623 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16625 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16627 constraint (size
>= 64, BAD_ADDR_MODE
);
16631 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16634 constraint (elsize
!= size
, BAD_EL_TYPE
);
16641 constraint (elsize
!= size
&& type
!= NT_unsigned
16642 && type
!= NT_signed
, BAD_EL_TYPE
);
16646 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16649 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16657 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16662 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16665 constraint (1, _("immediate must be a multiple of 2 in the"
16666 " range of +/-[0,254]"));
16669 constraint (1, _("immediate must be a multiple of 4 in the"
16670 " range of +/-[0,508]"));
16675 if (size
!= elsize
)
16677 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16678 constraint (inst
.operands
[0].reg
> 14,
16679 _("MVE vector register in the range [Q0..Q7] expected"));
16680 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16681 inst
.instruction
|= (size
== 16) << 19;
16682 inst
.instruction
|= neon_logbits (elsize
) << 7;
16686 if (inst
.operands
[1].reg
== REG_PC
)
16687 as_tsktsk (MVE_BAD_PC
);
16688 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16689 as_tsktsk (MVE_BAD_SP
);
16690 inst
.instruction
|= 1 << 12;
16691 inst
.instruction
|= neon_logbits (size
) << 7;
16693 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16694 inst
.instruction
|= add
<< 23;
16695 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16696 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16697 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16698 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16699 inst
.instruction
&= 0xffffff80;
16700 inst
.instruction
|= imm
>> neon_logbits (size
);
16705 do_mve_vstr_vldr (void)
16710 if (inst
.cond
> COND_ALWAYS
)
16711 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16713 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16715 switch (inst
.instruction
)
16722 /* fall through. */
16728 /* fall through. */
16734 /* fall through. */
16740 /* fall through. */
16745 unsigned elsize
= inst
.vectype
.el
[0].size
;
16747 if (inst
.operands
[1].isquad
)
16749 /* We are dealing with [Q, imm]{!} cases. */
16750 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16754 if (inst
.operands
[1].immisreg
== 2)
16756 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16757 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16759 else if (!inst
.operands
[1].immisreg
)
16761 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16762 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16765 constraint (1, BAD_ADDR_MODE
);
16772 do_mve_vst_vld (void)
16774 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16777 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16778 || inst
.relocs
[0].exp
.X_add_number
!= 0
16779 || inst
.operands
[1].immisreg
!= 0,
16781 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16782 if (inst
.operands
[1].reg
== REG_PC
)
16783 as_tsktsk (MVE_BAD_PC
);
16784 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16785 as_tsktsk (MVE_BAD_SP
);
16788 /* These instructions are one of the "exceptions" mentioned in
16789 handle_pred_state. They are MVE instructions that are not VPT compatible
16790 and do not accept a VPT code, thus appending such a code is a syntax
16792 if (inst
.cond
> COND_ALWAYS
)
16793 first_error (BAD_SYNTAX
);
16794 /* If we append a scalar condition code we can set this to
16795 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16796 else if (inst
.cond
< COND_ALWAYS
)
16797 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16799 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16801 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16802 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16804 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16805 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16810 do_mve_vaddlv (void)
16812 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
16813 struct neon_type_el et
16814 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
16816 if (et
.type
== NT_invtype
)
16817 first_error (BAD_EL_TYPE
);
16819 if (inst
.cond
> COND_ALWAYS
)
16820 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16822 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16824 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16826 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16827 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
16828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16829 inst
.instruction
|= inst
.operands
[2].reg
;
16834 do_neon_dyadic_if_su (void)
16836 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16837 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16840 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
16841 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
16842 && et
.type
== NT_float
16843 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
16845 if (check_simd_pred_availability (et
.type
== NT_float
,
16846 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16849 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16853 do_neon_addsub_if_i (void)
16855 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16856 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16859 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16860 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16861 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16863 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16864 /* If we are parsing Q registers and the element types match MVE, which NEON
16865 also supports, then we must check whether this is an instruction that can
16866 be used by both MVE/NEON. This distinction can be made based on whether
16867 they are predicated or not. */
16868 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16870 if (check_simd_pred_availability (et
.type
== NT_float
,
16871 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16876 /* If they are either in a D register or are using an unsupported. */
16878 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16882 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16883 affected if we specify unsigned args. */
16884 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16887 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16889 V<op> A,B (A is operand 0, B is operand 2)
16894 so handle that case specially. */
16897 neon_exchange_operands (void)
16899 if (inst
.operands
[1].present
)
16901 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16903 /* Swap operands[1] and operands[2]. */
16904 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16905 inst
.operands
[1] = inst
.operands
[2];
16906 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16911 inst
.operands
[1] = inst
.operands
[2];
16912 inst
.operands
[2] = inst
.operands
[0];
16917 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16919 if (inst
.operands
[2].isreg
)
16922 neon_exchange_operands ();
16923 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16927 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16928 struct neon_type_el et
= neon_check_type (2, rs
,
16929 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16931 NEON_ENCODE (IMMED
, inst
);
16932 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16933 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16934 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16935 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16936 inst
.instruction
|= neon_quad (rs
) << 6;
16937 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16938 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16940 neon_dp_fixup (&inst
);
16947 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16951 do_neon_cmp_inv (void)
16953 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16959 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16962 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16963 scalars, which are encoded in 5 bits, M : Rm.
16964 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16965 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16968 Dot Product instructions are similar to multiply instructions except elsize
16969 should always be 32.
16971 This function translates SCALAR, which is GAS's internal encoding of indexed
16972 scalar register, to raw encoding. There is also register and index range
16973 check based on ELSIZE. */
16976 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16978 unsigned regno
= NEON_SCALAR_REG (scalar
);
16979 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16984 if (regno
> 7 || elno
> 3)
16986 return regno
| (elno
<< 3);
16989 if (regno
> 15 || elno
> 1)
16991 return regno
| (elno
<< 4);
16995 first_error (_("scalar out of range for multiply instruction"));
17001 /* Encode multiply / multiply-accumulate scalar instructions. */
17004 neon_mul_mac (struct neon_type_el et
, int ubit
)
17008 /* Give a more helpful error message if we have an invalid type. */
17009 if (et
.type
== NT_invtype
)
17012 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17013 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17014 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17015 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17016 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17017 inst
.instruction
|= LOW4 (scalar
);
17018 inst
.instruction
|= HI1 (scalar
) << 5;
17019 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17020 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17021 inst
.instruction
|= (ubit
!= 0) << 24;
17023 neon_dp_fixup (&inst
);
17027 do_neon_mac_maybe_scalar (void)
17029 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17032 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17035 if (inst
.operands
[2].isscalar
)
17037 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17038 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17039 struct neon_type_el et
= neon_check_type (3, rs
,
17040 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17041 NEON_ENCODE (SCALAR
, inst
);
17042 neon_mul_mac (et
, neon_quad (rs
));
17044 else if (!inst
.operands
[2].isvec
)
17046 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17048 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17049 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17051 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17055 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17056 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17057 affected if we specify unsigned args. */
17058 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17063 do_neon_fmac (void)
17065 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17066 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17069 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17072 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17074 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17075 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17080 if (inst
.operands
[2].reg
== REG_SP
)
17081 as_tsktsk (MVE_BAD_SP
);
17082 else if (inst
.operands
[2].reg
== REG_PC
)
17083 as_tsktsk (MVE_BAD_PC
);
17085 inst
.instruction
= 0xee310e40;
17086 inst
.instruction
|= (et
.size
== 16) << 28;
17087 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17088 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17090 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17091 inst
.instruction
|= inst
.operands
[2].reg
;
17098 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17101 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17107 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17108 struct neon_type_el et
= neon_check_type (3, rs
,
17109 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17110 neon_three_same (neon_quad (rs
), 0, et
.size
);
17113 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17114 same types as the MAC equivalents. The polynomial type for this instruction
17115 is encoded the same as the integer type. */
17120 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17123 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17126 if (inst
.operands
[2].isscalar
)
17128 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17129 do_neon_mac_maybe_scalar ();
17133 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17135 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17136 struct neon_type_el et
17137 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17138 if (et
.type
== NT_float
)
17139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17142 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17146 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17147 neon_dyadic_misc (NT_poly
,
17148 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17154 do_neon_qdmulh (void)
17156 if (inst
.operands
[2].isscalar
)
17158 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17159 struct neon_type_el et
= neon_check_type (3, rs
,
17160 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17161 NEON_ENCODE (SCALAR
, inst
);
17162 neon_mul_mac (et
, neon_quad (rs
));
17166 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17167 struct neon_type_el et
= neon_check_type (3, rs
,
17168 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17169 NEON_ENCODE (INTEGER
, inst
);
17170 /* The U bit (rounding) comes from bit mask. */
17171 neon_three_same (neon_quad (rs
), 0, et
.size
);
17176 do_mve_vaddv (void)
17178 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17179 struct neon_type_el et
17180 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17182 if (et
.type
== NT_invtype
)
17183 first_error (BAD_EL_TYPE
);
17185 if (inst
.cond
> COND_ALWAYS
)
17186 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17188 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17190 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17192 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17196 do_mve_vhcadd (void)
17198 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17199 struct neon_type_el et
17200 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17202 if (inst
.cond
> COND_ALWAYS
)
17203 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17205 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17207 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17208 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17210 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17211 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17212 "operand makes instruction UNPREDICTABLE"));
17214 mve_encode_qqq (0, et
.size
);
17215 inst
.instruction
|= (rot
== 270) << 12;
17222 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17223 struct neon_type_el et
17224 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17226 if (et
.type
== NT_invtype
)
17227 first_error (BAD_EL_TYPE
);
17229 if (inst
.cond
> COND_ALWAYS
)
17230 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17232 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17234 mve_encode_qqq (0, 64);
17238 do_mve_vbrsr (void)
17240 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17241 struct neon_type_el et
17242 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17244 if (inst
.cond
> COND_ALWAYS
)
17245 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17247 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17249 mve_encode_qqr (et
.size
, 0, 0);
17255 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17257 if (inst
.cond
> COND_ALWAYS
)
17258 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17260 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17262 mve_encode_qqq (1, 64);
17266 do_mve_vmulh (void)
17268 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17269 struct neon_type_el et
17270 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17272 if (inst
.cond
> COND_ALWAYS
)
17273 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17275 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17277 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17281 do_mve_vmull (void)
17284 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17285 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17286 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17287 && inst
.cond
== COND_ALWAYS
17288 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17293 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17294 N_SUF_32
| N_F64
| N_P8
17295 | N_P16
| N_I_MVE
| N_KEY
);
17296 if (((et
.type
== NT_poly
) && et
.size
== 8
17297 && ARM_CPU_IS_ANY (cpu_variant
))
17298 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17305 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17306 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17307 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17309 /* We are dealing with MVE's vmullt. */
17311 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17312 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17313 as_tsktsk (BAD_MVE_SRCDEST
);
17315 if (inst
.cond
> COND_ALWAYS
)
17316 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17318 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17320 if (et
.type
== NT_poly
)
17321 mve_encode_qqq (neon_logbits (et
.size
), 64);
17323 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17328 inst
.instruction
= N_MNEM_vmul
;
17331 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17336 do_mve_vabav (void)
17338 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17343 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17346 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17347 | N_S16
| N_S32
| N_U8
| N_U16
17350 if (inst
.cond
> COND_ALWAYS
)
17351 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17353 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17355 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17359 do_mve_vmladav (void)
17361 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17362 struct neon_type_el et
= neon_check_type (3, rs
,
17363 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17365 if (et
.type
== NT_unsigned
17366 && (inst
.instruction
== M_MNEM_vmladavx
17367 || inst
.instruction
== M_MNEM_vmladavax
17368 || inst
.instruction
== M_MNEM_vmlsdav
17369 || inst
.instruction
== M_MNEM_vmlsdava
17370 || inst
.instruction
== M_MNEM_vmlsdavx
17371 || inst
.instruction
== M_MNEM_vmlsdavax
))
17372 first_error (BAD_SIMD_TYPE
);
17374 constraint (inst
.operands
[2].reg
> 14,
17375 _("MVE vector register in the range [Q0..Q7] expected"));
17377 if (inst
.cond
> COND_ALWAYS
)
17378 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17380 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17382 if (inst
.instruction
== M_MNEM_vmlsdav
17383 || inst
.instruction
== M_MNEM_vmlsdava
17384 || inst
.instruction
== M_MNEM_vmlsdavx
17385 || inst
.instruction
== M_MNEM_vmlsdavax
)
17386 inst
.instruction
|= (et
.size
== 8) << 28;
17388 inst
.instruction
|= (et
.size
== 8) << 8;
17390 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17391 inst
.instruction
|= (et
.size
== 32) << 16;
17395 do_mve_vmlaldav (void)
17397 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17398 struct neon_type_el et
17399 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17400 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17402 if (et
.type
== NT_unsigned
17403 && (inst
.instruction
== M_MNEM_vmlsldav
17404 || inst
.instruction
== M_MNEM_vmlsldava
17405 || inst
.instruction
== M_MNEM_vmlsldavx
17406 || inst
.instruction
== M_MNEM_vmlsldavax
))
17407 first_error (BAD_SIMD_TYPE
);
17409 if (inst
.cond
> COND_ALWAYS
)
17410 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17412 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17414 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17418 do_mve_vrmlaldavh (void)
17420 struct neon_type_el et
;
17421 if (inst
.instruction
== M_MNEM_vrmlsldavh
17422 || inst
.instruction
== M_MNEM_vrmlsldavha
17423 || inst
.instruction
== M_MNEM_vrmlsldavhx
17424 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17426 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17427 if (inst
.operands
[1].reg
== REG_SP
)
17428 as_tsktsk (MVE_BAD_SP
);
17432 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17433 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17434 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17436 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17437 N_U32
| N_S32
| N_KEY
);
17438 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17439 with vmax/min instructions, making the use of SP in assembly really
17440 nonsensical, so instead of issuing a warning like we do for other uses
17441 of SP for the odd register operand we error out. */
17442 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17445 /* Make sure we still check the second operand is an odd one and that PC is
17446 disallowed. This because we are parsing for any GPR operand, to be able
17447 to distinguish between giving a warning or an error for SP as described
17449 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17450 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17452 if (inst
.cond
> COND_ALWAYS
)
17453 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17455 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17457 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17462 do_mve_vmaxnmv (void)
17464 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17465 struct neon_type_el et
17466 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17468 if (inst
.cond
> COND_ALWAYS
)
17469 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17471 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17473 if (inst
.operands
[0].reg
== REG_SP
)
17474 as_tsktsk (MVE_BAD_SP
);
17475 else if (inst
.operands
[0].reg
== REG_PC
)
17476 as_tsktsk (MVE_BAD_PC
);
17478 mve_encode_rq (et
.size
== 16, 64);
17482 do_mve_vmaxv (void)
17484 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17485 struct neon_type_el et
;
17487 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17488 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17490 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17492 if (inst
.cond
> COND_ALWAYS
)
17493 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17495 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17497 if (inst
.operands
[0].reg
== REG_SP
)
17498 as_tsktsk (MVE_BAD_SP
);
17499 else if (inst
.operands
[0].reg
== REG_PC
)
17500 as_tsktsk (MVE_BAD_PC
);
17502 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17507 do_neon_qrdmlah (void)
17509 /* Check we're on the correct architecture. */
17510 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17512 _("instruction form not available on this architecture.");
17513 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17515 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17516 record_feature_use (&fpu_neon_ext_v8_1
);
17519 if (inst
.operands
[2].isscalar
)
17521 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17522 struct neon_type_el et
= neon_check_type (3, rs
,
17523 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17524 NEON_ENCODE (SCALAR
, inst
);
17525 neon_mul_mac (et
, neon_quad (rs
));
17529 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17530 struct neon_type_el et
= neon_check_type (3, rs
,
17531 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17532 NEON_ENCODE (INTEGER
, inst
);
17533 /* The U bit (rounding) comes from bit mask. */
17534 neon_three_same (neon_quad (rs
), 0, et
.size
);
17539 do_neon_fcmp_absolute (void)
17541 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17542 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17543 N_F_16_32
| N_KEY
);
17544 /* Size field comes from bit mask. */
17545 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17549 do_neon_fcmp_absolute_inv (void)
17551 neon_exchange_operands ();
17552 do_neon_fcmp_absolute ();
17556 do_neon_step (void)
17558 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17559 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17560 N_F_16_32
| N_KEY
);
17561 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17565 do_neon_abs_neg (void)
17567 enum neon_shape rs
;
17568 struct neon_type_el et
;
17570 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
17573 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17574 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
17576 if (check_simd_pred_availability (et
.type
== NT_float
,
17577 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17584 inst
.instruction
|= neon_quad (rs
) << 6;
17585 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17586 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17588 neon_dp_fixup (&inst
);
17594 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17595 struct neon_type_el et
= neon_check_type (2, rs
,
17596 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17597 int imm
= inst
.operands
[2].imm
;
17598 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17599 _("immediate out of range for insert"));
17600 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17606 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17607 struct neon_type_el et
= neon_check_type (2, rs
,
17608 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17609 int imm
= inst
.operands
[2].imm
;
17610 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17611 _("immediate out of range for insert"));
17612 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
17616 do_neon_qshlu_imm (void)
17618 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17619 struct neon_type_el et
= neon_check_type (2, rs
,
17620 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
17621 int imm
= inst
.operands
[2].imm
;
17622 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17623 _("immediate out of range for shift"));
17624 /* Only encodes the 'U present' variant of the instruction.
17625 In this case, signed types have OP (bit 8) set to 0.
17626 Unsigned types have OP set to 1. */
17627 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
17628 /* The rest of the bits are the same as other immediate shifts. */
17629 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17633 do_neon_qmovn (void)
17635 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17636 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17637 /* Saturating move where operands can be signed or unsigned, and the
17638 destination has the same signedness. */
17639 NEON_ENCODE (INTEGER
, inst
);
17640 if (et
.type
== NT_unsigned
)
17641 inst
.instruction
|= 0xc0;
17643 inst
.instruction
|= 0x80;
17644 neon_two_same (0, 1, et
.size
/ 2);
17648 do_neon_qmovun (void)
17650 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17651 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17652 /* Saturating move with unsigned results. Operands must be signed. */
17653 NEON_ENCODE (INTEGER
, inst
);
17654 neon_two_same (0, 1, et
.size
/ 2);
17658 do_neon_rshift_sat_narrow (void)
17660 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17661 or unsigned. If operands are unsigned, results must also be unsigned. */
17662 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17663 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17664 int imm
= inst
.operands
[2].imm
;
17665 /* This gets the bounds check, size encoding and immediate bits calculation
17669 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17670 VQMOVN.I<size> <Dd>, <Qm>. */
17673 inst
.operands
[2].present
= 0;
17674 inst
.instruction
= N_MNEM_vqmovn
;
17679 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17680 _("immediate out of range"));
17681 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17685 do_neon_rshift_sat_narrow_u (void)
17687 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17688 or unsigned. If operands are unsigned, results must also be unsigned. */
17689 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17690 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17691 int imm
= inst
.operands
[2].imm
;
17692 /* This gets the bounds check, size encoding and immediate bits calculation
17696 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17697 VQMOVUN.I<size> <Dd>, <Qm>. */
17700 inst
.operands
[2].present
= 0;
17701 inst
.instruction
= N_MNEM_vqmovun
;
17706 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17707 _("immediate out of range"));
17708 /* FIXME: The manual is kind of unclear about what value U should have in
17709 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17711 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
17715 do_neon_movn (void)
17717 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17718 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17719 NEON_ENCODE (INTEGER
, inst
);
17720 neon_two_same (0, 1, et
.size
/ 2);
17724 do_neon_rshift_narrow (void)
17726 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17727 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17728 int imm
= inst
.operands
[2].imm
;
17729 /* This gets the bounds check, size encoding and immediate bits calculation
17733 /* If immediate is zero then we are a pseudo-instruction for
17734 VMOVN.I<size> <Dd>, <Qm> */
17737 inst
.operands
[2].present
= 0;
17738 inst
.instruction
= N_MNEM_vmovn
;
17743 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17744 _("immediate out of range for narrowing operation"));
17745 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
17749 do_neon_shll (void)
17751 /* FIXME: Type checking when lengthening. */
17752 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
17753 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
17754 unsigned imm
= inst
.operands
[2].imm
;
17756 if (imm
== et
.size
)
17758 /* Maximum shift variant. */
17759 NEON_ENCODE (INTEGER
, inst
);
17760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17764 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17766 neon_dp_fixup (&inst
);
17770 /* A more-specific type check for non-max versions. */
17771 et
= neon_check_type (2, NS_QDI
,
17772 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17773 NEON_ENCODE (IMMED
, inst
);
17774 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
17778 /* Check the various types for the VCVT instruction, and return which version
17779 the current instruction is. */
17781 #define CVT_FLAVOUR_VAR \
17782 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17783 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17784 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17785 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17786 /* Half-precision conversions. */ \
17787 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17788 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17789 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17790 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17791 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17792 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17793 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17794 Compared with single/double precision variants, only the co-processor \
17795 field is different, so the encoding flow is reused here. */ \
17796 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17797 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17798 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17799 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17800 /* VFP instructions. */ \
17801 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17802 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17803 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17804 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17805 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17806 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17807 /* VFP instructions with bitshift. */ \
17808 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17809 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17810 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17811 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17812 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17813 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17814 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17815 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17817 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17818 neon_cvt_flavour_##C,
17820 /* The different types of conversions we can do. */
17821 enum neon_cvt_flavour
17824 neon_cvt_flavour_invalid
,
17825 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
17830 static enum neon_cvt_flavour
17831 get_neon_cvt_flavour (enum neon_shape rs
)
17833 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17834 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17835 if (et.type != NT_invtype) \
17837 inst.error = NULL; \
17838 return (neon_cvt_flavour_##C); \
17841 struct neon_type_el et
;
17842 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
17843 || rs
== NS_FF
) ? N_VFP
: 0;
17844 /* The instruction versions which take an immediate take one register
17845 argument, which is extended to the width of the full register. Thus the
17846 "source" and "destination" registers must have the same width. Hack that
17847 here by making the size equal to the key (wider, in this case) operand. */
17848 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
17852 return neon_cvt_flavour_invalid
;
17867 /* Neon-syntax VFP conversions. */
17870 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
17872 const char *opname
= 0;
17874 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
17875 || rs
== NS_FHI
|| rs
== NS_HFI
)
17877 /* Conversions with immediate bitshift. */
17878 const char *enc
[] =
17880 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17886 if (flavour
< (int) ARRAY_SIZE (enc
))
17888 opname
= enc
[flavour
];
17889 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17890 _("operands 0 and 1 must be the same register"));
17891 inst
.operands
[1] = inst
.operands
[2];
17892 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17897 /* Conversions without bitshift. */
17898 const char *enc
[] =
17900 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17906 if (flavour
< (int) ARRAY_SIZE (enc
))
17907 opname
= enc
[flavour
];
17911 do_vfp_nsyn_opcode (opname
);
17913 /* ARMv8.2 fp16 VCVT instruction. */
17914 if (flavour
== neon_cvt_flavour_s32_f16
17915 || flavour
== neon_cvt_flavour_u32_f16
17916 || flavour
== neon_cvt_flavour_f16_u32
17917 || flavour
== neon_cvt_flavour_f16_s32
)
17918 do_scalar_fp16_v82_encode ();
17922 do_vfp_nsyn_cvtz (void)
17924 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17925 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17926 const char *enc
[] =
17928 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17934 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17935 do_vfp_nsyn_opcode (enc
[flavour
]);
17939 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17940 enum neon_cvt_mode mode
)
17945 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17946 D register operands. */
17947 if (flavour
== neon_cvt_flavour_s32_f64
17948 || flavour
== neon_cvt_flavour_u32_f64
)
17949 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17952 if (flavour
== neon_cvt_flavour_s32_f16
17953 || flavour
== neon_cvt_flavour_u32_f16
)
17954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17957 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17961 case neon_cvt_flavour_s32_f64
:
17965 case neon_cvt_flavour_s32_f32
:
17969 case neon_cvt_flavour_s32_f16
:
17973 case neon_cvt_flavour_u32_f64
:
17977 case neon_cvt_flavour_u32_f32
:
17981 case neon_cvt_flavour_u32_f16
:
17986 first_error (_("invalid instruction shape"));
17992 case neon_cvt_mode_a
: rm
= 0; break;
17993 case neon_cvt_mode_n
: rm
= 1; break;
17994 case neon_cvt_mode_p
: rm
= 2; break;
17995 case neon_cvt_mode_m
: rm
= 3; break;
17996 default: first_error (_("invalid rounding mode")); return;
17999 NEON_ENCODE (FPV8
, inst
);
18000 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18001 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18002 inst
.instruction
|= sz
<< 8;
18004 /* ARMv8.2 fp16 VCVT instruction. */
18005 if (flavour
== neon_cvt_flavour_s32_f16
18006 ||flavour
== neon_cvt_flavour_u32_f16
)
18007 do_scalar_fp16_v82_encode ();
18008 inst
.instruction
|= op
<< 7;
18009 inst
.instruction
|= rm
<< 16;
18010 inst
.instruction
|= 0xf0000000;
18011 inst
.is_neon
= TRUE
;
18015 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18017 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18018 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18019 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18021 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18023 if (flavour
== neon_cvt_flavour_invalid
)
18026 /* PR11109: Handle round-to-zero for VCVT conversions. */
18027 if (mode
== neon_cvt_mode_z
18028 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18029 && (flavour
== neon_cvt_flavour_s16_f16
18030 || flavour
== neon_cvt_flavour_u16_f16
18031 || flavour
== neon_cvt_flavour_s32_f32
18032 || flavour
== neon_cvt_flavour_u32_f32
18033 || flavour
== neon_cvt_flavour_s32_f64
18034 || flavour
== neon_cvt_flavour_u32_f64
)
18035 && (rs
== NS_FD
|| rs
== NS_FF
))
18037 do_vfp_nsyn_cvtz ();
18041 /* ARMv8.2 fp16 VCVT conversions. */
18042 if (mode
== neon_cvt_mode_z
18043 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18044 && (flavour
== neon_cvt_flavour_s32_f16
18045 || flavour
== neon_cvt_flavour_u32_f16
)
18048 do_vfp_nsyn_cvtz ();
18049 do_scalar_fp16_v82_encode ();
18053 /* VFP rather than Neon conversions. */
18054 if (flavour
>= neon_cvt_flavour_first_fp
)
18056 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18057 do_vfp_nsyn_cvt (rs
, flavour
);
18059 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18067 if (mode
== neon_cvt_mode_z
18068 && (flavour
== neon_cvt_flavour_f16_s16
18069 || flavour
== neon_cvt_flavour_f16_u16
18070 || flavour
== neon_cvt_flavour_s16_f16
18071 || flavour
== neon_cvt_flavour_u16_f16
18072 || flavour
== neon_cvt_flavour_f32_u32
18073 || flavour
== neon_cvt_flavour_f32_s32
18074 || flavour
== neon_cvt_flavour_s32_f32
18075 || flavour
== neon_cvt_flavour_u32_f32
))
18077 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18080 else if (mode
== neon_cvt_mode_n
)
18082 /* We are dealing with vcvt with the 'ne' condition. */
18084 inst
.instruction
= N_MNEM_vcvt
;
18085 do_neon_cvt_1 (neon_cvt_mode_z
);
18088 /* fall through. */
18092 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18093 0x0000100, 0x1000100, 0x0, 0x1000000};
18095 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18096 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18099 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18101 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18102 _("immediate value out of range"));
18105 case neon_cvt_flavour_f16_s16
:
18106 case neon_cvt_flavour_f16_u16
:
18107 case neon_cvt_flavour_s16_f16
:
18108 case neon_cvt_flavour_u16_f16
:
18109 constraint (inst
.operands
[2].imm
> 16,
18110 _("immediate value out of range"));
18112 case neon_cvt_flavour_f32_u32
:
18113 case neon_cvt_flavour_f32_s32
:
18114 case neon_cvt_flavour_s32_f32
:
18115 case neon_cvt_flavour_u32_f32
:
18116 constraint (inst
.operands
[2].imm
> 32,
18117 _("immediate value out of range"));
18120 inst
.error
= BAD_FPU
;
18125 /* Fixed-point conversion with #0 immediate is encoded as an
18126 integer conversion. */
18127 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18129 NEON_ENCODE (IMMED
, inst
);
18130 if (flavour
!= neon_cvt_flavour_invalid
)
18131 inst
.instruction
|= enctab
[flavour
];
18132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18136 inst
.instruction
|= neon_quad (rs
) << 6;
18137 inst
.instruction
|= 1 << 21;
18138 if (flavour
< neon_cvt_flavour_s16_f16
)
18140 inst
.instruction
|= 1 << 21;
18141 immbits
= 32 - inst
.operands
[2].imm
;
18142 inst
.instruction
|= immbits
<< 16;
18146 inst
.instruction
|= 3 << 20;
18147 immbits
= 16 - inst
.operands
[2].imm
;
18148 inst
.instruction
|= immbits
<< 16;
18149 inst
.instruction
&= ~(1 << 9);
18152 neon_dp_fixup (&inst
);
18157 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18158 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18159 && (flavour
== neon_cvt_flavour_s16_f16
18160 || flavour
== neon_cvt_flavour_u16_f16
18161 || flavour
== neon_cvt_flavour_s32_f32
18162 || flavour
== neon_cvt_flavour_u32_f32
))
18164 if (check_simd_pred_availability (1,
18165 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18168 else if (mode
== neon_cvt_mode_z
18169 && (flavour
== neon_cvt_flavour_f16_s16
18170 || flavour
== neon_cvt_flavour_f16_u16
18171 || flavour
== neon_cvt_flavour_s16_f16
18172 || flavour
== neon_cvt_flavour_u16_f16
18173 || flavour
== neon_cvt_flavour_f32_u32
18174 || flavour
== neon_cvt_flavour_f32_s32
18175 || flavour
== neon_cvt_flavour_s32_f32
18176 || flavour
== neon_cvt_flavour_u32_f32
))
18178 if (check_simd_pred_availability (1,
18179 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18182 /* fall through. */
18184 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18187 NEON_ENCODE (FLOAT
, inst
);
18188 if (check_simd_pred_availability (1,
18189 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18192 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18195 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18196 inst
.instruction
|= neon_quad (rs
) << 6;
18197 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18198 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18199 inst
.instruction
|= mode
<< 8;
18200 if (flavour
== neon_cvt_flavour_u16_f16
18201 || flavour
== neon_cvt_flavour_s16_f16
)
18202 /* Mask off the original size bits and reencode them. */
18203 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18206 inst
.instruction
|= 0xfc000000;
18208 inst
.instruction
|= 0xf0000000;
18214 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18215 0x100, 0x180, 0x0, 0x080};
18217 NEON_ENCODE (INTEGER
, inst
);
18219 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18221 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18225 if (flavour
!= neon_cvt_flavour_invalid
)
18226 inst
.instruction
|= enctab
[flavour
];
18228 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18230 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18231 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18232 inst
.instruction
|= neon_quad (rs
) << 6;
18233 if (flavour
>= neon_cvt_flavour_s16_f16
18234 && flavour
<= neon_cvt_flavour_f16_u16
)
18235 /* Half precision. */
18236 inst
.instruction
|= 1 << 18;
18238 inst
.instruction
|= 2 << 18;
18240 neon_dp_fixup (&inst
);
18245 /* Half-precision conversions for Advanced SIMD -- neon. */
18248 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18252 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18254 as_bad (_("operand size must match register width"));
18259 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18261 as_bad (_("operand size must match register width"));
18266 inst
.instruction
= 0x3b60600;
18268 inst
.instruction
= 0x3b60700;
18270 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18271 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18272 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18273 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18274 neon_dp_fixup (&inst
);
18278 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18279 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18280 do_vfp_nsyn_cvt (rs
, flavour
);
18282 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18287 do_neon_cvtr (void)
18289 do_neon_cvt_1 (neon_cvt_mode_x
);
18295 do_neon_cvt_1 (neon_cvt_mode_z
);
18299 do_neon_cvta (void)
18301 do_neon_cvt_1 (neon_cvt_mode_a
);
18305 do_neon_cvtn (void)
18307 do_neon_cvt_1 (neon_cvt_mode_n
);
18311 do_neon_cvtp (void)
18313 do_neon_cvt_1 (neon_cvt_mode_p
);
18317 do_neon_cvtm (void)
18319 do_neon_cvt_1 (neon_cvt_mode_m
);
18323 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18326 mark_feature_used (&fpu_vfp_ext_armv8
);
18328 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18329 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18330 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18331 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18332 inst
.instruction
|= to
? 0x10000 : 0;
18333 inst
.instruction
|= t
? 0x80 : 0;
18334 inst
.instruction
|= is_double
? 0x100 : 0;
18335 do_vfp_cond_or_thumb ();
18339 do_neon_cvttb_1 (bfd_boolean t
)
18341 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18342 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18346 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18348 int single_to_half
= 0;
18349 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
18352 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18354 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18355 && (flavour
== neon_cvt_flavour_u16_f16
18356 || flavour
== neon_cvt_flavour_s16_f16
18357 || flavour
== neon_cvt_flavour_f16_s16
18358 || flavour
== neon_cvt_flavour_f16_u16
18359 || flavour
== neon_cvt_flavour_u32_f32
18360 || flavour
== neon_cvt_flavour_s32_f32
18361 || flavour
== neon_cvt_flavour_f32_s32
18362 || flavour
== neon_cvt_flavour_f32_u32
))
18365 inst
.instruction
= N_MNEM_vcvt
;
18366 set_pred_insn_type (INSIDE_VPT_INSN
);
18367 do_neon_cvt_1 (neon_cvt_mode_z
);
18370 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18371 single_to_half
= 1;
18372 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18374 first_error (BAD_FPU
);
18378 inst
.instruction
= 0xee3f0e01;
18379 inst
.instruction
|= single_to_half
<< 28;
18380 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18381 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18382 inst
.instruction
|= t
<< 12;
18383 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18387 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18390 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18392 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18395 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18397 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18399 /* The VCVTB and VCVTT instructions with D-register operands
18400 don't work for SP only targets. */
18401 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18405 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18407 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18409 /* The VCVTB and VCVTT instructions with D-register operands
18410 don't work for SP only targets. */
18411 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18415 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18422 do_neon_cvtb (void)
18424 do_neon_cvttb_1 (FALSE
);
18429 do_neon_cvtt (void)
18431 do_neon_cvttb_1 (TRUE
);
18435 neon_move_immediate (void)
18437 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18438 struct neon_type_el et
= neon_check_type (2, rs
,
18439 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18440 unsigned immlo
, immhi
= 0, immbits
;
18441 int op
, cmode
, float_p
;
18443 constraint (et
.type
== NT_invtype
,
18444 _("operand size must be specified for immediate VMOV"));
18446 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18447 op
= (inst
.instruction
& (1 << 5)) != 0;
18449 immlo
= inst
.operands
[1].imm
;
18450 if (inst
.operands
[1].regisimm
)
18451 immhi
= inst
.operands
[1].reg
;
18453 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18454 _("immediate has bits set outside the operand size"));
18456 float_p
= inst
.operands
[1].immisfloat
;
18458 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18459 et
.size
, et
.type
)) == FAIL
)
18461 /* Invert relevant bits only. */
18462 neon_invert_size (&immlo
, &immhi
, et
.size
);
18463 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18464 with one or the other; those cases are caught by
18465 neon_cmode_for_move_imm. */
18467 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18468 &op
, et
.size
, et
.type
)) == FAIL
)
18470 first_error (_("immediate out of range"));
18475 inst
.instruction
&= ~(1 << 5);
18476 inst
.instruction
|= op
<< 5;
18478 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18479 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18480 inst
.instruction
|= neon_quad (rs
) << 6;
18481 inst
.instruction
|= cmode
<< 8;
18483 neon_write_immbits (immbits
);
18489 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18492 if (inst
.operands
[1].isreg
)
18494 enum neon_shape rs
;
18495 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18496 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
18498 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18500 NEON_ENCODE (INTEGER
, inst
);
18501 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18502 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18503 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18504 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18505 inst
.instruction
|= neon_quad (rs
) << 6;
18509 NEON_ENCODE (IMMED
, inst
);
18510 neon_move_immediate ();
18513 neon_dp_fixup (&inst
);
18515 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18517 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
18518 constraint ((inst
.instruction
& 0xd00) == 0xd00,
18519 _("immediate value out of range"));
18523 /* Encode instructions of form:
18525 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18526 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18529 neon_mixed_length (struct neon_type_el et
, unsigned size
)
18531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18535 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18536 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18537 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
18538 inst
.instruction
|= neon_logbits (size
) << 20;
18540 neon_dp_fixup (&inst
);
18544 do_neon_dyadic_long (void)
18546 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
18549 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
18552 NEON_ENCODE (INTEGER
, inst
);
18553 /* FIXME: Type checking for lengthening op. */
18554 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18555 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18556 neon_mixed_length (et
, et
.size
);
18558 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18559 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
18561 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18562 in an IT block with le/lt conditions. */
18564 if (inst
.cond
== 0xf)
18566 else if (inst
.cond
== 0x10)
18569 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18571 if (inst
.instruction
== N_MNEM_vaddl
)
18573 inst
.instruction
= N_MNEM_vadd
;
18574 do_neon_addsub_if_i ();
18576 else if (inst
.instruction
== N_MNEM_vsubl
)
18578 inst
.instruction
= N_MNEM_vsub
;
18579 do_neon_addsub_if_i ();
18581 else if (inst
.instruction
== N_MNEM_vabdl
)
18583 inst
.instruction
= N_MNEM_vabd
;
18584 do_neon_dyadic_if_su ();
18588 first_error (BAD_FPU
);
18592 do_neon_abal (void)
18594 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18595 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18596 neon_mixed_length (et
, et
.size
);
18600 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
18602 if (inst
.operands
[2].isscalar
)
18604 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
18605 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
18606 NEON_ENCODE (SCALAR
, inst
);
18607 neon_mul_mac (et
, et
.type
== NT_unsigned
);
18611 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18612 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
18613 NEON_ENCODE (INTEGER
, inst
);
18614 neon_mixed_length (et
, et
.size
);
18619 do_neon_mac_maybe_scalar_long (void)
18621 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
18624 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18625 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18628 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
18630 unsigned regno
= NEON_SCALAR_REG (scalar
);
18631 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
18635 if (regno
> 7 || elno
> 3)
18638 return ((regno
& 0x7)
18639 | ((elno
& 0x1) << 3)
18640 | (((elno
>> 1) & 0x1) << 5));
18644 if (regno
> 15 || elno
> 1)
18647 return (((regno
& 0x1) << 5)
18648 | ((regno
>> 1) & 0x7)
18649 | ((elno
& 0x1) << 3));
18653 first_error (_("scalar out of range for multiply instruction"));
18658 do_neon_fmac_maybe_scalar_long (int subtype
)
18660 enum neon_shape rs
;
18662 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18663 field (bits[21:20]) has different meaning. For scalar index variant, it's
18664 used to differentiate add and subtract, otherwise it's with fixed value
18668 if (inst
.cond
!= COND_ALWAYS
)
18669 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18670 "behaviour is UNPREDICTABLE"));
18672 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18675 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18678 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18679 be a scalar index register. */
18680 if (inst
.operands
[2].isscalar
)
18682 high8
= 0xfe000000;
18685 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18689 high8
= 0xfc000000;
18692 inst
.instruction
|= (0x1 << 23);
18693 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
18696 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
18698 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18699 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18700 so we simply pass -1 as size. */
18701 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
18702 neon_three_same (quad_p
, 0, size
);
18704 /* Undo neon_dp_fixup. Redo the high eight bits. */
18705 inst
.instruction
&= 0x00ffffff;
18706 inst
.instruction
|= high8
;
18708 #define LOW1(R) ((R) & 0x1)
18709 #define HI4(R) (((R) >> 1) & 0xf)
18710 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18711 whether the instruction is in Q form and whether Vm is a scalar indexed
18713 if (inst
.operands
[2].isscalar
)
18716 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
18717 inst
.instruction
&= 0xffffffd0;
18718 inst
.instruction
|= rm
;
18722 /* Redo Rn as well. */
18723 inst
.instruction
&= 0xfff0ff7f;
18724 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18725 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18730 /* Redo Rn and Rm. */
18731 inst
.instruction
&= 0xfff0ff50;
18732 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18733 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18734 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
18735 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
18740 do_neon_vfmal (void)
18742 return do_neon_fmac_maybe_scalar_long (0);
18746 do_neon_vfmsl (void)
18748 return do_neon_fmac_maybe_scalar_long (1);
18752 do_neon_dyadic_wide (void)
18754 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
18755 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18756 neon_mixed_length (et
, et
.size
);
18760 do_neon_dyadic_narrow (void)
18762 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18763 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
18764 /* Operand sign is unimportant, and the U bit is part of the opcode,
18765 so force the operand type to integer. */
18766 et
.type
= NT_integer
;
18767 neon_mixed_length (et
, et
.size
/ 2);
18771 do_neon_mul_sat_scalar_long (void)
18773 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
18777 do_neon_vmull (void)
18779 if (inst
.operands
[2].isscalar
)
18780 do_neon_mac_maybe_scalar_long ();
18783 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18784 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
18786 if (et
.type
== NT_poly
)
18787 NEON_ENCODE (POLY
, inst
);
18789 NEON_ENCODE (INTEGER
, inst
);
18791 /* For polynomial encoding the U bit must be zero, and the size must
18792 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18793 obviously, as 0b10). */
18796 /* Check we're on the correct architecture. */
18797 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
18799 _("Instruction form not available on this architecture.");
18804 neon_mixed_length (et
, et
.size
);
18811 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18812 struct neon_type_el et
= neon_check_type (3, rs
,
18813 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18814 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
18816 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
18817 _("shift out of range"));
18818 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18819 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18820 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18821 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18822 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18823 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18824 inst
.instruction
|= neon_quad (rs
) << 6;
18825 inst
.instruction
|= imm
<< 8;
18827 neon_dp_fixup (&inst
);
18833 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18834 struct neon_type_el et
= neon_check_type (2, rs
,
18835 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18836 unsigned op
= (inst
.instruction
>> 7) & 3;
18837 /* N (width of reversed regions) is encoded as part of the bitmask. We
18838 extract it here to check the elements to be reversed are smaller.
18839 Otherwise we'd get a reserved instruction. */
18840 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
18841 gas_assert (elsize
!= 0);
18842 constraint (et
.size
>= elsize
,
18843 _("elements must be smaller than reversal region"));
18844 neon_two_same (neon_quad (rs
), 1, et
.size
);
18850 if (inst
.operands
[1].isscalar
)
18852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
18854 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
18855 struct neon_type_el et
= neon_check_type (2, rs
,
18856 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18857 unsigned sizebits
= et
.size
>> 3;
18858 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18859 int logsize
= neon_logbits (et
.size
);
18860 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
18862 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
18865 NEON_ENCODE (SCALAR
, inst
);
18866 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18867 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18868 inst
.instruction
|= LOW4 (dm
);
18869 inst
.instruction
|= HI1 (dm
) << 5;
18870 inst
.instruction
|= neon_quad (rs
) << 6;
18871 inst
.instruction
|= x
<< 17;
18872 inst
.instruction
|= sizebits
<< 16;
18874 neon_dp_fixup (&inst
);
18878 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
18879 struct neon_type_el et
= neon_check_type (2, rs
,
18880 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18883 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
))
18887 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
18890 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18892 if (inst
.operands
[1].reg
== REG_SP
)
18893 as_tsktsk (MVE_BAD_SP
);
18894 else if (inst
.operands
[1].reg
== REG_PC
)
18895 as_tsktsk (MVE_BAD_PC
);
18898 /* Duplicate ARM register to lanes of vector. */
18899 NEON_ENCODE (ARMREG
, inst
);
18902 case 8: inst
.instruction
|= 0x400000; break;
18903 case 16: inst
.instruction
|= 0x000020; break;
18904 case 32: inst
.instruction
|= 0x000000; break;
18907 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18908 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18909 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18910 inst
.instruction
|= neon_quad (rs
) << 21;
18911 /* The encoding for this instruction is identical for the ARM and Thumb
18912 variants, except for the condition field. */
18913 do_vfp_cond_or_thumb ();
18918 do_mve_mov (int toQ
)
18920 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18922 if (inst
.cond
> COND_ALWAYS
)
18923 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18925 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18934 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18935 _("Index one must be [2,3] and index two must be two less than"
18937 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18938 _("General purpose registers may not be the same"));
18939 constraint (inst
.operands
[Rt
].reg
== REG_SP
18940 || inst
.operands
[Rt2
].reg
== REG_SP
,
18942 constraint (inst
.operands
[Rt
].reg
== REG_PC
18943 || inst
.operands
[Rt2
].reg
== REG_PC
,
18946 inst
.instruction
= 0xec000f00;
18947 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18948 inst
.instruction
|= !!toQ
<< 20;
18949 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18950 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18951 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18952 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18958 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18961 if (inst
.cond
> COND_ALWAYS
)
18962 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18964 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18966 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18970 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18971 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18972 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18973 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18978 /* VMOV has particularly many variations. It can be one of:
18979 0. VMOV<c><q> <Qd>, <Qm>
18980 1. VMOV<c><q> <Dd>, <Dm>
18981 (Register operations, which are VORR with Rm = Rn.)
18982 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18983 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18985 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18986 (ARM register to scalar.)
18987 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18988 (Two ARM registers to vector.)
18989 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18990 (Scalar to ARM register.)
18991 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18992 (Vector to two ARM registers.)
18993 8. VMOV.F32 <Sd>, <Sm>
18994 9. VMOV.F64 <Dd>, <Dm>
18995 (VFP register moves.)
18996 10. VMOV.F32 <Sd>, #imm
18997 11. VMOV.F64 <Dd>, #imm
18998 (VFP float immediate load.)
18999 12. VMOV <Rd>, <Sm>
19000 (VFP single to ARM reg.)
19001 13. VMOV <Sd>, <Rm>
19002 (ARM reg to VFP single.)
19003 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19004 (Two ARM regs to two VFP singles.)
19005 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19006 (Two VFP singles to two ARM regs.)
19007 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19008 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19009 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19010 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19012 These cases can be disambiguated using neon_select_shape, except cases 1/9
19013 and 3/11 which depend on the operand type too.
19015 All the encoded bits are hardcoded by this function.
19017 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19018 Cases 5, 7 may be used with VFPv2 and above.
19020 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19021 can specify a type where it doesn't make sense to, and is ignored). */
19026 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19027 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19028 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19029 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19031 struct neon_type_el et
;
19032 const char *ldconst
= 0;
19036 case NS_DD
: /* case 1/9. */
19037 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19038 /* It is not an error here if no type is given. */
19040 if (et
.type
== NT_float
&& et
.size
== 64)
19042 do_vfp_nsyn_opcode ("fcpyd");
19045 /* fall through. */
19047 case NS_QQ
: /* case 0/1. */
19049 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19051 /* The architecture manual I have doesn't explicitly state which
19052 value the U bit should have for register->register moves, but
19053 the equivalent VORR instruction has U = 0, so do that. */
19054 inst
.instruction
= 0x0200110;
19055 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19056 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19057 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19058 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19061 inst
.instruction
|= neon_quad (rs
) << 6;
19063 neon_dp_fixup (&inst
);
19067 case NS_DI
: /* case 3/11. */
19068 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19070 if (et
.type
== NT_float
&& et
.size
== 64)
19072 /* case 11 (fconstd). */
19073 ldconst
= "fconstd";
19074 goto encode_fconstd
;
19076 /* fall through. */
19078 case NS_QI
: /* case 2/3. */
19079 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19081 inst
.instruction
= 0x0800010;
19082 neon_move_immediate ();
19083 neon_dp_fixup (&inst
);
19086 case NS_SR
: /* case 4. */
19088 unsigned bcdebits
= 0;
19090 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19091 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19093 /* .<size> is optional here, defaulting to .32. */
19094 if (inst
.vectype
.elems
== 0
19095 && inst
.operands
[0].vectype
.type
== NT_invtype
19096 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19098 inst
.vectype
.el
[0].type
= NT_untyped
;
19099 inst
.vectype
.el
[0].size
= 32;
19100 inst
.vectype
.elems
= 1;
19103 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19104 logsize
= neon_logbits (et
.size
);
19108 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19109 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19114 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19115 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19119 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19121 if (inst
.operands
[1].reg
== REG_SP
)
19122 as_tsktsk (MVE_BAD_SP
);
19123 else if (inst
.operands
[1].reg
== REG_PC
)
19124 as_tsktsk (MVE_BAD_PC
);
19126 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19128 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19129 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19134 case 8: bcdebits
= 0x8; break;
19135 case 16: bcdebits
= 0x1; break;
19136 case 32: bcdebits
= 0x0; break;
19140 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19142 inst
.instruction
= 0xe000b10;
19143 do_vfp_cond_or_thumb ();
19144 inst
.instruction
|= LOW4 (dn
) << 16;
19145 inst
.instruction
|= HI1 (dn
) << 7;
19146 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19147 inst
.instruction
|= (bcdebits
& 3) << 5;
19148 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19149 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19153 case NS_DRR
: /* case 5 (fmdrr). */
19154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19155 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19158 inst
.instruction
= 0xc400b10;
19159 do_vfp_cond_or_thumb ();
19160 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19161 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19162 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19163 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19166 case NS_RS
: /* case 6. */
19169 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19170 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19171 unsigned abcdebits
= 0;
19173 /* .<dt> is optional here, defaulting to .32. */
19174 if (inst
.vectype
.elems
== 0
19175 && inst
.operands
[0].vectype
.type
== NT_invtype
19176 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19178 inst
.vectype
.el
[0].type
= NT_untyped
;
19179 inst
.vectype
.el
[0].size
= 32;
19180 inst
.vectype
.elems
= 1;
19183 et
= neon_check_type (2, NS_NULL
,
19184 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19185 logsize
= neon_logbits (et
.size
);
19189 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19190 && vfp_or_neon_is_neon (NEON_CHECK_CC
19191 | NEON_CHECK_ARCH
) == FAIL
)
19196 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19197 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19201 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19203 if (inst
.operands
[0].reg
== REG_SP
)
19204 as_tsktsk (MVE_BAD_SP
);
19205 else if (inst
.operands
[0].reg
== REG_PC
)
19206 as_tsktsk (MVE_BAD_PC
);
19209 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19211 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19212 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19216 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19217 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19218 case 32: abcdebits
= 0x00; break;
19222 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19223 inst
.instruction
= 0xe100b10;
19224 do_vfp_cond_or_thumb ();
19225 inst
.instruction
|= LOW4 (dn
) << 16;
19226 inst
.instruction
|= HI1 (dn
) << 7;
19227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19228 inst
.instruction
|= (abcdebits
& 3) << 5;
19229 inst
.instruction
|= (abcdebits
>> 2) << 21;
19230 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19234 case NS_RRD
: /* case 7 (fmrrd). */
19235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19236 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19239 inst
.instruction
= 0xc500b10;
19240 do_vfp_cond_or_thumb ();
19241 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19242 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19243 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19244 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19247 case NS_FF
: /* case 8 (fcpys). */
19248 do_vfp_nsyn_opcode ("fcpys");
19252 case NS_FI
: /* case 10 (fconsts). */
19253 ldconst
= "fconsts";
19255 if (!inst
.operands
[1].immisfloat
)
19258 /* Immediate has to fit in 8 bits so float is enough. */
19259 float imm
= (float) inst
.operands
[1].imm
;
19260 memcpy (&new_imm
, &imm
, sizeof (float));
19261 /* But the assembly may have been written to provide an integer
19262 bit pattern that equates to a float, so check that the
19263 conversion has worked. */
19264 if (is_quarter_float (new_imm
))
19266 if (is_quarter_float (inst
.operands
[1].imm
))
19267 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19269 inst
.operands
[1].imm
= new_imm
;
19270 inst
.operands
[1].immisfloat
= 1;
19274 if (is_quarter_float (inst
.operands
[1].imm
))
19276 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19277 do_vfp_nsyn_opcode (ldconst
);
19279 /* ARMv8.2 fp16 vmov.f16 instruction. */
19281 do_scalar_fp16_v82_encode ();
19284 first_error (_("immediate out of range"));
19288 case NS_RF
: /* case 12 (fmrs). */
19289 do_vfp_nsyn_opcode ("fmrs");
19290 /* ARMv8.2 fp16 vmov.f16 instruction. */
19292 do_scalar_fp16_v82_encode ();
19296 case NS_FR
: /* case 13 (fmsr). */
19297 do_vfp_nsyn_opcode ("fmsr");
19298 /* ARMv8.2 fp16 vmov.f16 instruction. */
19300 do_scalar_fp16_v82_encode ();
19310 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19311 (one of which is a list), but we have parsed four. Do some fiddling to
19312 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19314 case NS_RRFF
: /* case 14 (fmrrs). */
19315 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19316 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19318 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19319 _("VFP registers must be adjacent"));
19320 inst
.operands
[2].imm
= 2;
19321 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19322 do_vfp_nsyn_opcode ("fmrrs");
19325 case NS_FFRR
: /* case 15 (fmsrr). */
19326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19327 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19329 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19330 _("VFP registers must be adjacent"));
19331 inst
.operands
[1] = inst
.operands
[2];
19332 inst
.operands
[2] = inst
.operands
[3];
19333 inst
.operands
[0].imm
= 2;
19334 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19335 do_vfp_nsyn_opcode ("fmsrr");
19339 /* neon_select_shape has determined that the instruction
19340 shape is wrong and has already set the error message. */
19351 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19352 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19353 && !inst
.operands
[2].present
))
19355 inst
.instruction
= 0;
19358 set_pred_insn_type (INSIDE_IT_INSN
);
19363 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19366 if (inst
.cond
!= COND_ALWAYS
)
19367 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19369 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19370 | N_S16
| N_U16
| N_KEY
);
19372 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19374 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19375 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19376 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19377 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19382 do_neon_rshift_round_imm (void)
19384 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19385 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19386 int imm
= inst
.operands
[2].imm
;
19388 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19391 inst
.operands
[2].present
= 0;
19396 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19397 _("immediate out of range for shift"));
19398 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19403 do_neon_movhf (void)
19405 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19406 constraint (rs
!= NS_HH
, _("invalid suffix"));
19408 if (inst
.cond
!= COND_ALWAYS
)
19412 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19413 " the behaviour is UNPREDICTABLE"));
19417 inst
.error
= BAD_COND
;
19422 do_vfp_sp_monadic ();
19425 inst
.instruction
|= 0xf0000000;
19429 do_neon_movl (void)
19431 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19432 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19433 unsigned sizebits
= et
.size
>> 3;
19434 inst
.instruction
|= sizebits
<< 19;
19435 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19441 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19442 struct neon_type_el et
= neon_check_type (2, rs
,
19443 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19444 NEON_ENCODE (INTEGER
, inst
);
19445 neon_two_same (neon_quad (rs
), 1, et
.size
);
19449 do_neon_zip_uzp (void)
19451 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19452 struct neon_type_el et
= neon_check_type (2, rs
,
19453 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19454 if (rs
== NS_DD
&& et
.size
== 32)
19456 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
19457 inst
.instruction
= N_MNEM_vtrn
;
19461 neon_two_same (neon_quad (rs
), 1, et
.size
);
19465 do_neon_sat_abs_neg (void)
19467 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19470 enum neon_shape rs
;
19471 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19472 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19474 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19475 struct neon_type_el et
= neon_check_type (2, rs
,
19476 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19477 neon_two_same (neon_quad (rs
), 1, et
.size
);
19481 do_neon_pair_long (void)
19483 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19484 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
19485 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
19486 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
19487 neon_two_same (neon_quad (rs
), 1, et
.size
);
19491 do_neon_recip_est (void)
19493 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19494 struct neon_type_el et
= neon_check_type (2, rs
,
19495 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
19496 inst
.instruction
|= (et
.type
== NT_float
) << 8;
19497 neon_two_same (neon_quad (rs
), 1, et
.size
);
19503 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19506 enum neon_shape rs
;
19507 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19508 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19510 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19512 struct neon_type_el et
= neon_check_type (2, rs
,
19513 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19514 neon_two_same (neon_quad (rs
), 1, et
.size
);
19520 if (check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19523 enum neon_shape rs
;
19524 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19525 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19527 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19529 struct neon_type_el et
= neon_check_type (2, rs
,
19530 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
19531 neon_two_same (neon_quad (rs
), 1, et
.size
);
19537 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19538 struct neon_type_el et
= neon_check_type (2, rs
,
19539 N_EQK
| N_INT
, N_8
| N_KEY
);
19540 neon_two_same (neon_quad (rs
), 1, et
.size
);
19546 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19547 neon_two_same (neon_quad (rs
), 1, -1);
19551 do_neon_tbl_tbx (void)
19553 unsigned listlenbits
;
19554 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
19556 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
19558 first_error (_("bad list length for table lookup"));
19562 listlenbits
= inst
.operands
[1].imm
- 1;
19563 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19564 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19565 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19566 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19567 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19568 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19569 inst
.instruction
|= listlenbits
<< 8;
19571 neon_dp_fixup (&inst
);
19575 do_neon_ldm_stm (void)
19577 /* P, U and L bits are part of bitmask. */
19578 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
19579 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
19581 if (inst
.operands
[1].issingle
)
19583 do_vfp_nsyn_ldm_stm (is_dbmode
);
19587 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
19588 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19590 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
19591 _("register list must contain at least 1 and at most 16 "
19594 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
19595 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
19596 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19597 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
19599 inst
.instruction
|= offsetbits
;
19601 do_vfp_cond_or_thumb ();
19605 do_neon_ldr_str (void)
19607 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
19609 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19610 And is UNPREDICTABLE in thumb mode. */
19612 && inst
.operands
[1].reg
== REG_PC
19613 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
19616 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19617 else if (warn_on_deprecated
)
19618 as_tsktsk (_("Use of PC here is deprecated"));
19621 if (inst
.operands
[0].issingle
)
19624 do_vfp_nsyn_opcode ("flds");
19626 do_vfp_nsyn_opcode ("fsts");
19628 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19629 if (inst
.vectype
.el
[0].size
== 16)
19630 do_scalar_fp16_v82_encode ();
19635 do_vfp_nsyn_opcode ("fldd");
19637 do_vfp_nsyn_opcode ("fstd");
19642 do_t_vldr_vstr_sysreg (void)
19644 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
19645 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
19647 /* Use of PC is UNPREDICTABLE. */
19648 if (inst
.operands
[1].reg
== REG_PC
)
19649 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19651 if (inst
.operands
[1].immisreg
)
19652 inst
.error
= _("instruction does not accept register index");
19654 if (!inst
.operands
[1].isreg
)
19655 inst
.error
= _("instruction does not accept PC-relative addressing");
19657 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
19658 inst
.error
= _("immediate value out of range");
19660 inst
.instruction
= 0xec000f80;
19662 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
19663 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
19664 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
19665 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
19669 do_vldr_vstr (void)
19671 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
19673 /* VLDR/VSTR (System Register). */
19676 if (!mark_feature_used (&arm_ext_v8_1m_main
))
19677 as_bad (_("Instruction not permitted on this architecture"));
19679 do_t_vldr_vstr_sysreg ();
19684 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
19685 as_bad (_("Instruction not permitted on this architecture"));
19686 do_neon_ldr_str ();
19690 /* "interleave" version also handles non-interleaving register VLD1/VST1
19694 do_neon_ld_st_interleave (void)
19696 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
19697 N_8
| N_16
| N_32
| N_64
);
19698 unsigned alignbits
= 0;
19700 /* The bits in this table go:
19701 0: register stride of one (0) or two (1)
19702 1,2: register list length, minus one (1, 2, 3, 4).
19703 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19704 We use -1 for invalid entries. */
19705 const int typetable
[] =
19707 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19708 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19709 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19710 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19714 if (et
.type
== NT_invtype
)
19717 if (inst
.operands
[1].immisalign
)
19718 switch (inst
.operands
[1].imm
>> 8)
19720 case 64: alignbits
= 1; break;
19722 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
19723 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19724 goto bad_alignment
;
19728 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19729 goto bad_alignment
;
19734 first_error (_("bad alignment"));
19738 inst
.instruction
|= alignbits
<< 4;
19739 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19741 /* Bits [4:6] of the immediate in a list specifier encode register stride
19742 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19743 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19744 up the right value for "type" in a table based on this value and the given
19745 list style, then stick it back. */
19746 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
19747 | (((inst
.instruction
>> 8) & 3) << 3);
19749 typebits
= typetable
[idx
];
19751 constraint (typebits
== -1, _("bad list type for instruction"));
19752 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
19755 inst
.instruction
&= ~0xf00;
19756 inst
.instruction
|= typebits
<< 8;
19759 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19760 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19761 otherwise. The variable arguments are a list of pairs of legal (size, align)
19762 values, terminated with -1. */
19765 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
19768 int result
= FAIL
, thissize
, thisalign
;
19770 if (!inst
.operands
[1].immisalign
)
19776 va_start (ap
, do_alignment
);
19780 thissize
= va_arg (ap
, int);
19781 if (thissize
== -1)
19783 thisalign
= va_arg (ap
, int);
19785 if (size
== thissize
&& align
== thisalign
)
19788 while (result
!= SUCCESS
);
19792 if (result
== SUCCESS
)
19795 first_error (_("unsupported alignment for instruction"));
19801 do_neon_ld_st_lane (void)
19803 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19804 int align_good
, do_alignment
= 0;
19805 int logsize
= neon_logbits (et
.size
);
19806 int align
= inst
.operands
[1].imm
>> 8;
19807 int n
= (inst
.instruction
>> 8) & 3;
19808 int max_el
= 64 / et
.size
;
19810 if (et
.type
== NT_invtype
)
19813 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
19814 _("bad list length"));
19815 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
19816 _("scalar index out of range"));
19817 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
19819 _("stride of 2 unavailable when element size is 8"));
19823 case 0: /* VLD1 / VST1. */
19824 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
19826 if (align_good
== FAIL
)
19830 unsigned alignbits
= 0;
19833 case 16: alignbits
= 0x1; break;
19834 case 32: alignbits
= 0x3; break;
19837 inst
.instruction
|= alignbits
<< 4;
19841 case 1: /* VLD2 / VST2. */
19842 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
19843 16, 32, 32, 64, -1);
19844 if (align_good
== FAIL
)
19847 inst
.instruction
|= 1 << 4;
19850 case 2: /* VLD3 / VST3. */
19851 constraint (inst
.operands
[1].immisalign
,
19852 _("can't use alignment with this instruction"));
19855 case 3: /* VLD4 / VST4. */
19856 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19857 16, 64, 32, 64, 32, 128, -1);
19858 if (align_good
== FAIL
)
19862 unsigned alignbits
= 0;
19865 case 8: alignbits
= 0x1; break;
19866 case 16: alignbits
= 0x1; break;
19867 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
19870 inst
.instruction
|= alignbits
<< 4;
19877 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19878 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19879 inst
.instruction
|= 1 << (4 + logsize
);
19881 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
19882 inst
.instruction
|= logsize
<< 10;
19885 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19888 do_neon_ld_dup (void)
19890 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19891 int align_good
, do_alignment
= 0;
19893 if (et
.type
== NT_invtype
)
19896 switch ((inst
.instruction
>> 8) & 3)
19898 case 0: /* VLD1. */
19899 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
19900 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19901 &do_alignment
, 16, 16, 32, 32, -1);
19902 if (align_good
== FAIL
)
19904 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
19907 case 2: inst
.instruction
|= 1 << 5; break;
19908 default: first_error (_("bad list length")); return;
19910 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19913 case 1: /* VLD2. */
19914 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19915 &do_alignment
, 8, 16, 16, 32, 32, 64,
19917 if (align_good
== FAIL
)
19919 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
19920 _("bad list length"));
19921 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19922 inst
.instruction
|= 1 << 5;
19923 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19926 case 2: /* VLD3. */
19927 constraint (inst
.operands
[1].immisalign
,
19928 _("can't use alignment with this instruction"));
19929 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
19930 _("bad list length"));
19931 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19932 inst
.instruction
|= 1 << 5;
19933 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19936 case 3: /* VLD4. */
19938 int align
= inst
.operands
[1].imm
>> 8;
19939 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19940 16, 64, 32, 64, 32, 128, -1);
19941 if (align_good
== FAIL
)
19943 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19944 _("bad list length"));
19945 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19946 inst
.instruction
|= 1 << 5;
19947 if (et
.size
== 32 && align
== 128)
19948 inst
.instruction
|= 0x3 << 6;
19950 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19957 inst
.instruction
|= do_alignment
<< 4;
19960 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19961 apart from bits [11:4]. */
19964 do_neon_ldx_stx (void)
19966 if (inst
.operands
[1].isreg
)
19967 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19969 switch (NEON_LANE (inst
.operands
[0].imm
))
19971 case NEON_INTERLEAVE_LANES
:
19972 NEON_ENCODE (INTERLV
, inst
);
19973 do_neon_ld_st_interleave ();
19976 case NEON_ALL_LANES
:
19977 NEON_ENCODE (DUP
, inst
);
19978 if (inst
.instruction
== N_INV
)
19980 first_error ("only loads support such operands");
19987 NEON_ENCODE (LANE
, inst
);
19988 do_neon_ld_st_lane ();
19991 /* L bit comes from bit mask. */
19992 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19993 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19994 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19996 if (inst
.operands
[1].postind
)
19998 int postreg
= inst
.operands
[1].imm
& 0xf;
19999 constraint (!inst
.operands
[1].immisreg
,
20000 _("post-index must be a register"));
20001 constraint (postreg
== 0xd || postreg
== 0xf,
20002 _("bad register for post-index"));
20003 inst
.instruction
|= postreg
;
20007 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20008 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20009 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20012 if (inst
.operands
[1].writeback
)
20014 inst
.instruction
|= 0xd;
20017 inst
.instruction
|= 0xf;
20021 inst
.instruction
|= 0xf9000000;
20023 inst
.instruction
|= 0xf4000000;
20028 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20030 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20031 D register operands. */
20032 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20036 NEON_ENCODE (FPV8
, inst
);
20038 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20040 do_vfp_sp_dyadic ();
20042 /* ARMv8.2 fp16 instruction. */
20044 do_scalar_fp16_v82_encode ();
20047 do_vfp_dp_rd_rn_rm ();
20050 inst
.instruction
|= 0x100;
20052 inst
.instruction
|= 0xf0000000;
20058 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20060 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20061 first_error (_("invalid instruction shape"));
20067 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20068 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20070 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20073 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20076 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20080 do_vrint_1 (enum neon_cvt_mode mode
)
20082 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20083 struct neon_type_el et
;
20088 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20089 D register operands. */
20090 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20094 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20096 if (et
.type
!= NT_invtype
)
20098 /* VFP encodings. */
20099 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20100 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20101 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20103 NEON_ENCODE (FPV8
, inst
);
20104 if (rs
== NS_FF
|| rs
== NS_HH
)
20105 do_vfp_sp_monadic ();
20107 do_vfp_dp_rd_rm ();
20111 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20112 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20113 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20114 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20115 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20116 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20117 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20121 inst
.instruction
|= (rs
== NS_DD
) << 8;
20122 do_vfp_cond_or_thumb ();
20124 /* ARMv8.2 fp16 vrint instruction. */
20126 do_scalar_fp16_v82_encode ();
20130 /* Neon encodings (or something broken...). */
20132 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20134 if (et
.type
== NT_invtype
)
20137 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20138 NEON_ENCODE (FLOAT
, inst
);
20140 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
20143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20147 inst
.instruction
|= neon_quad (rs
) << 6;
20148 /* Mask off the original size bits and reencode them. */
20149 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20150 | neon_logbits (et
.size
) << 18);
20154 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20155 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20156 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20157 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20158 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20159 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20160 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20165 inst
.instruction
|= 0xfc000000;
20167 inst
.instruction
|= 0xf0000000;
20174 do_vrint_1 (neon_cvt_mode_x
);
20180 do_vrint_1 (neon_cvt_mode_z
);
20186 do_vrint_1 (neon_cvt_mode_r
);
20192 do_vrint_1 (neon_cvt_mode_a
);
20198 do_vrint_1 (neon_cvt_mode_n
);
20204 do_vrint_1 (neon_cvt_mode_p
);
20210 do_vrint_1 (neon_cvt_mode_m
);
20214 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20216 unsigned regno
= NEON_SCALAR_REG (opnd
);
20217 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20219 if (elsize
== 16 && elno
< 2 && regno
< 16)
20220 return regno
| (elno
<< 4);
20221 else if (elsize
== 32 && elno
== 0)
20224 first_error (_("scalar out of range"));
20231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20232 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20233 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20234 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20235 _("expression too complex"));
20236 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20237 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20238 _("immediate out of range"));
20241 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20244 if (inst
.operands
[2].isscalar
)
20246 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20247 first_error (_("invalid instruction shape"));
20248 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20249 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20250 N_KEY
| N_F16
| N_F32
).size
;
20251 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20253 inst
.instruction
= 0xfe000800;
20254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20255 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20258 inst
.instruction
|= LOW4 (m
);
20259 inst
.instruction
|= HI1 (m
) << 5;
20260 inst
.instruction
|= neon_quad (rs
) << 6;
20261 inst
.instruction
|= rot
<< 20;
20262 inst
.instruction
|= (size
== 32) << 23;
20266 enum neon_shape rs
;
20267 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20268 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20270 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20272 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20273 N_KEY
| N_F16
| N_F32
).size
;
20274 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20275 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20276 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20277 as_tsktsk (BAD_MVE_SRCDEST
);
20279 neon_three_same (neon_quad (rs
), 0, -1);
20280 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20281 inst
.instruction
|= 0xfc200800;
20282 inst
.instruction
|= rot
<< 23;
20283 inst
.instruction
|= (size
== 32) << 20;
20290 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20291 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20292 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20293 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20294 _("expression too complex"));
20296 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20297 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20298 enum neon_shape rs
;
20299 struct neon_type_el et
;
20300 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20302 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20303 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20307 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20308 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20310 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20311 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20312 "operand makes instruction UNPREDICTABLE"));
20315 if (et
.type
== NT_invtype
)
20318 if (check_simd_pred_availability (et
.type
== NT_float
, NEON_CHECK_ARCH8
20322 if (et
.type
== NT_float
)
20324 neon_three_same (neon_quad (rs
), 0, -1);
20325 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20326 inst
.instruction
|= 0xfc800800;
20327 inst
.instruction
|= (rot
== 270) << 24;
20328 inst
.instruction
|= (et
.size
== 32) << 20;
20332 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20333 inst
.instruction
= 0xfe000f00;
20334 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20335 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20336 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20337 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20338 inst
.instruction
|= (rot
== 270) << 12;
20339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20340 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20341 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20346 /* Dot Product instructions encoding support. */
20349 do_neon_dotproduct (int unsigned_p
)
20351 enum neon_shape rs
;
20352 unsigned scalar_oprd2
= 0;
20355 if (inst
.cond
!= COND_ALWAYS
)
20356 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20357 "is UNPREDICTABLE"));
20359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20362 /* Dot Product instructions are in three-same D/Q register format or the third
20363 operand can be a scalar index register. */
20364 if (inst
.operands
[2].isscalar
)
20366 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20367 high8
= 0xfe000000;
20368 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20372 high8
= 0xfc000000;
20373 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20377 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20379 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20381 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20382 Product instruction, so we pass 0 as the "ubit" parameter. And the
20383 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20384 neon_three_same (neon_quad (rs
), 0, 32);
20386 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20387 different NEON three-same encoding. */
20388 inst
.instruction
&= 0x00ffffff;
20389 inst
.instruction
|= high8
;
20390 /* Encode 'U' bit which indicates signedness. */
20391 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20392 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20393 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20394 the instruction encoding. */
20395 if (inst
.operands
[2].isscalar
)
20397 inst
.instruction
&= 0xffffffd0;
20398 inst
.instruction
|= LOW4 (scalar_oprd2
);
20399 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20403 /* Dot Product instructions for signed integer. */
20406 do_neon_dotproduct_s (void)
20408 return do_neon_dotproduct (0);
20411 /* Dot Product instructions for unsigned integer. */
20414 do_neon_dotproduct_u (void)
20416 return do_neon_dotproduct (1);
20419 /* Crypto v1 instructions. */
20421 do_crypto_2op_1 (unsigned elttype
, int op
)
20423 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20425 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20431 NEON_ENCODE (INTEGER
, inst
);
20432 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20437 inst
.instruction
|= op
<< 6;
20440 inst
.instruction
|= 0xfc000000;
20442 inst
.instruction
|= 0xf0000000;
20446 do_crypto_3op_1 (int u
, int op
)
20448 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20450 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
20451 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
20456 NEON_ENCODE (INTEGER
, inst
);
20457 neon_three_same (1, u
, 8 << op
);
20463 do_crypto_2op_1 (N_8
, 0);
20469 do_crypto_2op_1 (N_8
, 1);
20475 do_crypto_2op_1 (N_8
, 2);
20481 do_crypto_2op_1 (N_8
, 3);
20487 do_crypto_3op_1 (0, 0);
20493 do_crypto_3op_1 (0, 1);
20499 do_crypto_3op_1 (0, 2);
20505 do_crypto_3op_1 (0, 3);
20511 do_crypto_3op_1 (1, 0);
20517 do_crypto_3op_1 (1, 1);
20521 do_sha256su1 (void)
20523 do_crypto_3op_1 (1, 2);
20529 do_crypto_2op_1 (N_32
, -1);
20535 do_crypto_2op_1 (N_32
, 0);
20539 do_sha256su0 (void)
20541 do_crypto_2op_1 (N_32
, 1);
20545 do_crc32_1 (unsigned int poly
, unsigned int sz
)
20547 unsigned int Rd
= inst
.operands
[0].reg
;
20548 unsigned int Rn
= inst
.operands
[1].reg
;
20549 unsigned int Rm
= inst
.operands
[2].reg
;
20551 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20552 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
20553 inst
.instruction
|= LOW4 (Rn
) << 16;
20554 inst
.instruction
|= LOW4 (Rm
);
20555 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
20556 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
20558 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
20559 as_warn (UNPRED_REG ("r15"));
20601 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20603 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
20604 do_vfp_sp_dp_cvt ();
20605 do_vfp_cond_or_thumb ();
20609 /* Overall per-instruction processing. */
20611 /* We need to be able to fix up arbitrary expressions in some statements.
20612 This is so that we can handle symbols that are an arbitrary distance from
20613 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20614 which returns part of an address in a form which will be valid for
20615 a data instruction. We do this by pushing the expression into a symbol
20616 in the expr_section, and creating a fix for that. */
20619 fix_new_arm (fragS
* frag
,
20633 /* Create an absolute valued symbol, so we have something to
20634 refer to in the object file. Unfortunately for us, gas's
20635 generic expression parsing will already have folded out
20636 any use of .set foo/.type foo %function that may have
20637 been used to set type information of the target location,
20638 that's being specified symbolically. We have to presume
20639 the user knows what they are doing. */
20643 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
20645 symbol
= symbol_find_or_make (name
);
20646 S_SET_SEGMENT (symbol
, absolute_section
);
20647 symbol_set_frag (symbol
, &zero_address_frag
);
20648 S_SET_VALUE (symbol
, exp
->X_add_number
);
20649 exp
->X_op
= O_symbol
;
20650 exp
->X_add_symbol
= symbol
;
20651 exp
->X_add_number
= 0;
20657 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
20658 (enum bfd_reloc_code_real
) reloc
);
20662 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
20663 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
20667 /* Mark whether the fix is to a THUMB instruction, or an ARM
20669 new_fix
->tc_fix_data
= thumb_mode
;
20672 /* Create a frg for an instruction requiring relaxation. */
20674 output_relax_insn (void)
20680 /* The size of the instruction is unknown, so tie the debug info to the
20681 start of the instruction. */
20682 dwarf2_emit_insn (0);
20684 switch (inst
.relocs
[0].exp
.X_op
)
20687 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
20688 offset
= inst
.relocs
[0].exp
.X_add_number
;
20692 offset
= inst
.relocs
[0].exp
.X_add_number
;
20695 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
20699 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
20700 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
20701 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
20704 /* Write a 32-bit thumb instruction to buf. */
20706 put_thumb32_insn (char * buf
, unsigned long insn
)
20708 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
20709 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
20713 output_inst (const char * str
)
20719 as_bad ("%s -- `%s'", inst
.error
, str
);
20724 output_relax_insn ();
20727 if (inst
.size
== 0)
20730 to
= frag_more (inst
.size
);
20731 /* PR 9814: Record the thumb mode into the current frag so that we know
20732 what type of NOP padding to use, if necessary. We override any previous
20733 setting so that if the mode has changed then the NOPS that we use will
20734 match the encoding of the last instruction in the frag. */
20735 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20737 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
20739 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
20740 put_thumb32_insn (to
, inst
.instruction
);
20742 else if (inst
.size
> INSN_SIZE
)
20744 gas_assert (inst
.size
== (2 * INSN_SIZE
));
20745 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
20746 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
20749 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
20752 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20754 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
20755 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
20756 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
20757 inst
.relocs
[r
].type
);
20760 dwarf2_emit_insn (inst
.size
);
20764 output_it_inst (int cond
, int mask
, char * to
)
20766 unsigned long instruction
= 0xbf00;
20769 instruction
|= mask
;
20770 instruction
|= cond
<< 4;
20774 to
= frag_more (2);
20776 dwarf2_emit_insn (2);
20780 md_number_to_chars (to
, instruction
, 2);
20785 /* Tag values used in struct asm_opcode's tag field. */
20788 OT_unconditional
, /* Instruction cannot be conditionalized.
20789 The ARM condition field is still 0xE. */
20790 OT_unconditionalF
, /* Instruction cannot be conditionalized
20791 and carries 0xF in its ARM condition field. */
20792 OT_csuffix
, /* Instruction takes a conditional suffix. */
20793 OT_csuffixF
, /* Some forms of the instruction take a scalar
20794 conditional suffix, others place 0xF where the
20795 condition field would be, others take a vector
20796 conditional suffix. */
20797 OT_cinfix3
, /* Instruction takes a conditional infix,
20798 beginning at character index 3. (In
20799 unified mode, it becomes a suffix.) */
20800 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
20801 tsts, cmps, cmns, and teqs. */
20802 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
20803 character index 3, even in unified mode. Used for
20804 legacy instructions where suffix and infix forms
20805 may be ambiguous. */
20806 OT_csuf_or_in3
, /* Instruction takes either a conditional
20807 suffix or an infix at character index 3. */
20808 OT_odd_infix_unc
, /* This is the unconditional variant of an
20809 instruction that takes a conditional infix
20810 at an unusual position. In unified mode,
20811 this variant will accept a suffix. */
20812 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
20813 are the conditional variants of instructions that
20814 take conditional infixes in unusual positions.
20815 The infix appears at character index
20816 (tag - OT_odd_infix_0). These are not accepted
20817 in unified mode. */
20820 /* Subroutine of md_assemble, responsible for looking up the primary
20821 opcode from the mnemonic the user wrote. STR points to the
20822 beginning of the mnemonic.
20824 This is not simply a hash table lookup, because of conditional
20825 variants. Most instructions have conditional variants, which are
20826 expressed with a _conditional affix_ to the mnemonic. If we were
20827 to encode each conditional variant as a literal string in the opcode
20828 table, it would have approximately 20,000 entries.
20830 Most mnemonics take this affix as a suffix, and in unified syntax,
20831 'most' is upgraded to 'all'. However, in the divided syntax, some
20832 instructions take the affix as an infix, notably the s-variants of
20833 the arithmetic instructions. Of those instructions, all but six
20834 have the infix appear after the third character of the mnemonic.
20836 Accordingly, the algorithm for looking up primary opcodes given
20839 1. Look up the identifier in the opcode table.
20840 If we find a match, go to step U.
20842 2. Look up the last two characters of the identifier in the
20843 conditions table. If we find a match, look up the first N-2
20844 characters of the identifier in the opcode table. If we
20845 find a match, go to step CE.
20847 3. Look up the fourth and fifth characters of the identifier in
20848 the conditions table. If we find a match, extract those
20849 characters from the identifier, and look up the remaining
20850 characters in the opcode table. If we find a match, go
20855 U. Examine the tag field of the opcode structure, in case this is
20856 one of the six instructions with its conditional infix in an
20857 unusual place. If it is, the tag tells us where to find the
20858 infix; look it up in the conditions table and set inst.cond
20859 accordingly. Otherwise, this is an unconditional instruction.
20860 Again set inst.cond accordingly. Return the opcode structure.
20862 CE. Examine the tag field to make sure this is an instruction that
20863 should receive a conditional suffix. If it is not, fail.
20864 Otherwise, set inst.cond from the suffix we already looked up,
20865 and return the opcode structure.
20867 CM. Examine the tag field to make sure this is an instruction that
20868 should receive a conditional infix after the third character.
20869 If it is not, fail. Otherwise, undo the edits to the current
20870 line of input and proceed as for case CE. */
20872 static const struct asm_opcode
*
20873 opcode_lookup (char **str
)
20877 const struct asm_opcode
*opcode
;
20878 const struct asm_cond
*cond
;
20881 /* Scan up to the end of the mnemonic, which must end in white space,
20882 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20883 for (base
= end
= *str
; *end
!= '\0'; end
++)
20884 if (*end
== ' ' || *end
== '.')
20890 /* Handle a possible width suffix and/or Neon type suffix. */
20895 /* The .w and .n suffixes are only valid if the unified syntax is in
20897 if (unified_syntax
&& end
[1] == 'w')
20899 else if (unified_syntax
&& end
[1] == 'n')
20904 inst
.vectype
.elems
= 0;
20906 *str
= end
+ offset
;
20908 if (end
[offset
] == '.')
20910 /* See if we have a Neon type suffix (possible in either unified or
20911 non-unified ARM syntax mode). */
20912 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
20915 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
20921 /* Look for unaffixed or special-case affixed mnemonic. */
20922 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20927 if (opcode
->tag
< OT_odd_infix_0
)
20929 inst
.cond
= COND_ALWAYS
;
20933 if (warn_on_deprecated
&& unified_syntax
)
20934 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20935 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
20936 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20939 inst
.cond
= cond
->value
;
20942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20944 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20946 if (end
- base
< 2)
20949 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
20950 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20952 /* If this opcode can not be vector predicated then don't accept it with a
20953 vector predication code. */
20954 if (opcode
&& !opcode
->mayBeVecPred
)
20957 if (!opcode
|| !cond
)
20959 /* Cannot have a conditional suffix on a mnemonic of less than two
20961 if (end
- base
< 3)
20964 /* Look for suffixed mnemonic. */
20966 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20967 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20971 if (opcode
&& cond
)
20974 switch (opcode
->tag
)
20976 case OT_cinfix3_legacy
:
20977 /* Ignore conditional suffixes matched on infix only mnemonics. */
20981 case OT_cinfix3_deprecated
:
20982 case OT_odd_infix_unc
:
20983 if (!unified_syntax
)
20985 /* Fall through. */
20989 case OT_csuf_or_in3
:
20990 inst
.cond
= cond
->value
;
20993 case OT_unconditional
:
20994 case OT_unconditionalF
:
20996 inst
.cond
= cond
->value
;
20999 /* Delayed diagnostic. */
21000 inst
.error
= BAD_COND
;
21001 inst
.cond
= COND_ALWAYS
;
21010 /* Cannot have a usual-position infix on a mnemonic of less than
21011 six characters (five would be a suffix). */
21012 if (end
- base
< 6)
21015 /* Look for infixed mnemonic in the usual position. */
21017 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21021 memcpy (save
, affix
, 2);
21022 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21023 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21025 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21026 memcpy (affix
, save
, 2);
21029 && (opcode
->tag
== OT_cinfix3
21030 || opcode
->tag
== OT_cinfix3_deprecated
21031 || opcode
->tag
== OT_csuf_or_in3
21032 || opcode
->tag
== OT_cinfix3_legacy
))
21035 if (warn_on_deprecated
&& unified_syntax
21036 && (opcode
->tag
== OT_cinfix3
21037 || opcode
->tag
== OT_cinfix3_deprecated
))
21038 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21040 inst
.cond
= cond
->value
;
21047 /* This function generates an initial IT instruction, leaving its block
21048 virtually open for the new instructions. Eventually,
21049 the mask will be updated by now_pred_add_mask () each time
21050 a new instruction needs to be included in the IT block.
21051 Finally, the block is closed with close_automatic_it_block ().
21052 The block closure can be requested either from md_assemble (),
21053 a tencode (), or due to a label hook. */
21056 new_automatic_it_block (int cond
)
21058 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21059 now_pred
.mask
= 0x18;
21060 now_pred
.cc
= cond
;
21061 now_pred
.block_length
= 1;
21062 mapping_state (MAP_THUMB
);
21063 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21064 now_pred
.warn_deprecated
= FALSE
;
21065 now_pred
.insn_cond
= TRUE
;
21068 /* Close an automatic IT block.
21069 See comments in new_automatic_it_block (). */
21072 close_automatic_it_block (void)
21074 now_pred
.mask
= 0x10;
21075 now_pred
.block_length
= 0;
21078 /* Update the mask of the current automatically-generated IT
21079 instruction. See comments in new_automatic_it_block (). */
21082 now_pred_add_mask (int cond
)
21084 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21085 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21086 | ((bitvalue) << (nbit)))
21087 const int resulting_bit
= (cond
& 1);
21089 now_pred
.mask
&= 0xf;
21090 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21092 (5 - now_pred
.block_length
));
21093 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21095 ((5 - now_pred
.block_length
) - 1));
21096 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21099 #undef SET_BIT_VALUE
21102 /* The IT blocks handling machinery is accessed through the these functions:
21103 it_fsm_pre_encode () from md_assemble ()
21104 set_pred_insn_type () optional, from the tencode functions
21105 set_pred_insn_type_last () ditto
21106 in_pred_block () ditto
21107 it_fsm_post_encode () from md_assemble ()
21108 force_automatic_it_block_close () from label handling functions
21111 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21112 initializing the IT insn type with a generic initial value depending
21113 on the inst.condition.
21114 2) During the tencode function, two things may happen:
21115 a) The tencode function overrides the IT insn type by
21116 calling either set_pred_insn_type (type) or
21117 set_pred_insn_type_last ().
21118 b) The tencode function queries the IT block state by
21119 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21121 Both set_pred_insn_type and in_pred_block run the internal FSM state
21122 handling function (handle_pred_state), because: a) setting the IT insn
21123 type may incur in an invalid state (exiting the function),
21124 and b) querying the state requires the FSM to be updated.
21125 Specifically we want to avoid creating an IT block for conditional
21126 branches, so it_fsm_pre_encode is actually a guess and we can't
21127 determine whether an IT block is required until the tencode () routine
21128 has decided what type of instruction this actually it.
21129 Because of this, if set_pred_insn_type and in_pred_block have to be
21130 used, set_pred_insn_type has to be called first.
21132 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21133 that determines the insn IT type depending on the inst.cond code.
21134 When a tencode () routine encodes an instruction that can be
21135 either outside an IT block, or, in the case of being inside, has to be
21136 the last one, set_pred_insn_type_last () will determine the proper
21137 IT instruction type based on the inst.cond code. Otherwise,
21138 set_pred_insn_type can be called for overriding that logic or
21139 for covering other cases.
21141 Calling handle_pred_state () may not transition the IT block state to
21142 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21143 still queried. Instead, if the FSM determines that the state should
21144 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21145 after the tencode () function: that's what it_fsm_post_encode () does.
21147 Since in_pred_block () calls the state handling function to get an
21148 updated state, an error may occur (due to invalid insns combination).
21149 In that case, inst.error is set.
21150 Therefore, inst.error has to be checked after the execution of
21151 the tencode () routine.
21153 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21154 any pending state change (if any) that didn't take place in
21155 handle_pred_state () as explained above. */
21158 it_fsm_pre_encode (void)
21160 if (inst
.cond
!= COND_ALWAYS
)
21161 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21163 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21165 now_pred
.state_handled
= 0;
21168 /* IT state FSM handling function. */
21169 /* MVE instructions and non-MVE instructions are handled differently because of
21170 the introduction of VPT blocks.
21171 Specifications say that any non-MVE instruction inside a VPT block is
21172 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21173 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21174 few exceptions we have MVE_UNPREDICABLE_INSN.
21175 The error messages provided depending on the different combinations possible
21176 are described in the cases below:
21177 For 'most' MVE instructions:
21178 1) In an IT block, with an IT code: syntax error
21179 2) In an IT block, with a VPT code: error: must be in a VPT block
21180 3) In an IT block, with no code: warning: UNPREDICTABLE
21181 4) In a VPT block, with an IT code: syntax error
21182 5) In a VPT block, with a VPT code: OK!
21183 6) In a VPT block, with no code: error: missing code
21184 7) Outside a pred block, with an IT code: error: syntax error
21185 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21186 9) Outside a pred block, with no code: OK!
21187 For non-MVE instructions:
21188 10) In an IT block, with an IT code: OK!
21189 11) In an IT block, with a VPT code: syntax error
21190 12) In an IT block, with no code: error: missing code
21191 13) In a VPT block, with an IT code: error: should be in an IT block
21192 14) In a VPT block, with a VPT code: syntax error
21193 15) In a VPT block, with no code: UNPREDICTABLE
21194 16) Outside a pred block, with an IT code: error: should be in an IT block
21195 17) Outside a pred block, with a VPT code: syntax error
21196 18) Outside a pred block, with no code: OK!
21201 handle_pred_state (void)
21203 now_pred
.state_handled
= 1;
21204 now_pred
.insn_cond
= FALSE
;
21206 switch (now_pred
.state
)
21208 case OUTSIDE_PRED_BLOCK
:
21209 switch (inst
.pred_insn_type
)
21211 case MVE_UNPREDICABLE_INSN
:
21212 case MVE_OUTSIDE_PRED_INSN
:
21213 if (inst
.cond
< COND_ALWAYS
)
21215 /* Case 7: Outside a pred block, with an IT code: error: syntax
21217 inst
.error
= BAD_SYNTAX
;
21220 /* Case 9: Outside a pred block, with no code: OK! */
21222 case OUTSIDE_PRED_INSN
:
21223 if (inst
.cond
> COND_ALWAYS
)
21225 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21227 inst
.error
= BAD_SYNTAX
;
21230 /* Case 18: Outside a pred block, with no code: OK! */
21233 case INSIDE_VPT_INSN
:
21234 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21236 inst
.error
= BAD_OUT_VPT
;
21239 case INSIDE_IT_INSN
:
21240 case INSIDE_IT_LAST_INSN
:
21241 if (inst
.cond
< COND_ALWAYS
)
21243 /* Case 16: Outside a pred block, with an IT code: error: should
21244 be in an IT block. */
21245 if (thumb_mode
== 0)
21248 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21249 as_tsktsk (_("Warning: conditional outside an IT block"\
21254 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21255 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21257 /* Automatically generate the IT instruction. */
21258 new_automatic_it_block (inst
.cond
);
21259 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21260 close_automatic_it_block ();
21264 inst
.error
= BAD_OUT_IT
;
21270 else if (inst
.cond
> COND_ALWAYS
)
21272 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21274 inst
.error
= BAD_SYNTAX
;
21279 case IF_INSIDE_IT_LAST_INSN
:
21280 case NEUTRAL_IT_INSN
:
21284 if (inst
.cond
!= COND_ALWAYS
)
21285 first_error (BAD_SYNTAX
);
21286 now_pred
.state
= MANUAL_PRED_BLOCK
;
21287 now_pred
.block_length
= 0;
21288 now_pred
.type
= VECTOR_PRED
;
21292 now_pred
.state
= MANUAL_PRED_BLOCK
;
21293 now_pred
.block_length
= 0;
21294 now_pred
.type
= SCALAR_PRED
;
21299 case AUTOMATIC_PRED_BLOCK
:
21300 /* Three things may happen now:
21301 a) We should increment current it block size;
21302 b) We should close current it block (closing insn or 4 insns);
21303 c) We should close current it block and start a new one (due
21304 to incompatible conditions or
21305 4 insns-length block reached). */
21307 switch (inst
.pred_insn_type
)
21309 case INSIDE_VPT_INSN
:
21311 case MVE_UNPREDICABLE_INSN
:
21312 case MVE_OUTSIDE_PRED_INSN
:
21314 case OUTSIDE_PRED_INSN
:
21315 /* The closure of the block shall happen immediately,
21316 so any in_pred_block () call reports the block as closed. */
21317 force_automatic_it_block_close ();
21320 case INSIDE_IT_INSN
:
21321 case INSIDE_IT_LAST_INSN
:
21322 case IF_INSIDE_IT_LAST_INSN
:
21323 now_pred
.block_length
++;
21325 if (now_pred
.block_length
> 4
21326 || !now_pred_compatible (inst
.cond
))
21328 force_automatic_it_block_close ();
21329 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21330 new_automatic_it_block (inst
.cond
);
21334 now_pred
.insn_cond
= TRUE
;
21335 now_pred_add_mask (inst
.cond
);
21338 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21339 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21340 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21341 close_automatic_it_block ();
21344 case NEUTRAL_IT_INSN
:
21345 now_pred
.block_length
++;
21346 now_pred
.insn_cond
= TRUE
;
21348 if (now_pred
.block_length
> 4)
21349 force_automatic_it_block_close ();
21351 now_pred_add_mask (now_pred
.cc
& 1);
21355 close_automatic_it_block ();
21356 now_pred
.state
= MANUAL_PRED_BLOCK
;
21361 case MANUAL_PRED_BLOCK
:
21364 if (now_pred
.type
== SCALAR_PRED
)
21366 /* Check conditional suffixes. */
21367 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21368 now_pred
.mask
<<= 1;
21369 now_pred
.mask
&= 0x1f;
21370 is_last
= (now_pred
.mask
== 0x10);
21374 now_pred
.cc
^= (now_pred
.mask
>> 4);
21375 cond
= now_pred
.cc
+ 0xf;
21376 now_pred
.mask
<<= 1;
21377 now_pred
.mask
&= 0x1f;
21378 is_last
= now_pred
.mask
== 0x10;
21380 now_pred
.insn_cond
= TRUE
;
21382 switch (inst
.pred_insn_type
)
21384 case OUTSIDE_PRED_INSN
:
21385 if (now_pred
.type
== SCALAR_PRED
)
21387 if (inst
.cond
== COND_ALWAYS
)
21389 /* Case 12: In an IT block, with no code: error: missing
21391 inst
.error
= BAD_NOT_IT
;
21394 else if (inst
.cond
> COND_ALWAYS
)
21396 /* Case 11: In an IT block, with a VPT code: syntax error.
21398 inst
.error
= BAD_SYNTAX
;
21401 else if (thumb_mode
)
21403 /* This is for some special cases where a non-MVE
21404 instruction is not allowed in an IT block, such as cbz,
21405 but are put into one with a condition code.
21406 You could argue this should be a syntax error, but we
21407 gave the 'not allowed in IT block' diagnostic in the
21408 past so we will keep doing so. */
21409 inst
.error
= BAD_NOT_IT
;
21416 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21417 as_tsktsk (MVE_NOT_VPT
);
21420 case MVE_OUTSIDE_PRED_INSN
:
21421 if (now_pred
.type
== SCALAR_PRED
)
21423 if (inst
.cond
== COND_ALWAYS
)
21425 /* Case 3: In an IT block, with no code: warning:
21427 as_tsktsk (MVE_NOT_IT
);
21430 else if (inst
.cond
< COND_ALWAYS
)
21432 /* Case 1: In an IT block, with an IT code: syntax error.
21434 inst
.error
= BAD_SYNTAX
;
21442 if (inst
.cond
< COND_ALWAYS
)
21444 /* Case 4: In a VPT block, with an IT code: syntax error.
21446 inst
.error
= BAD_SYNTAX
;
21449 else if (inst
.cond
== COND_ALWAYS
)
21451 /* Case 6: In a VPT block, with no code: error: missing
21453 inst
.error
= BAD_NOT_VPT
;
21461 case MVE_UNPREDICABLE_INSN
:
21462 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
21464 case INSIDE_IT_INSN
:
21465 if (inst
.cond
> COND_ALWAYS
)
21467 /* Case 11: In an IT block, with a VPT code: syntax error. */
21468 /* Case 14: In a VPT block, with a VPT code: syntax error. */
21469 inst
.error
= BAD_SYNTAX
;
21472 else if (now_pred
.type
== SCALAR_PRED
)
21474 /* Case 10: In an IT block, with an IT code: OK! */
21475 if (cond
!= inst
.cond
)
21477 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
21484 /* Case 13: In a VPT block, with an IT code: error: should be
21486 inst
.error
= BAD_OUT_IT
;
21491 case INSIDE_VPT_INSN
:
21492 if (now_pred
.type
== SCALAR_PRED
)
21494 /* Case 2: In an IT block, with a VPT code: error: must be in a
21496 inst
.error
= BAD_OUT_VPT
;
21499 /* Case 5: In a VPT block, with a VPT code: OK! */
21500 else if (cond
!= inst
.cond
)
21502 inst
.error
= BAD_VPT_COND
;
21506 case INSIDE_IT_LAST_INSN
:
21507 case IF_INSIDE_IT_LAST_INSN
:
21508 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
21510 /* Case 4: In a VPT block, with an IT code: syntax error. */
21511 /* Case 11: In an IT block, with a VPT code: syntax error. */
21512 inst
.error
= BAD_SYNTAX
;
21515 else if (cond
!= inst
.cond
)
21517 inst
.error
= BAD_IT_COND
;
21522 inst
.error
= BAD_BRANCH
;
21527 case NEUTRAL_IT_INSN
:
21528 /* The BKPT instruction is unconditional even in a IT or VPT
21533 if (now_pred
.type
== SCALAR_PRED
)
21535 inst
.error
= BAD_IT_IT
;
21538 /* fall through. */
21540 if (inst
.cond
== COND_ALWAYS
)
21542 /* Executing a VPT/VPST instruction inside an IT block or a
21543 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21545 if (now_pred
.type
== SCALAR_PRED
)
21546 as_tsktsk (MVE_NOT_IT
);
21548 as_tsktsk (MVE_NOT_VPT
);
21553 /* VPT/VPST do not accept condition codes. */
21554 inst
.error
= BAD_SYNTAX
;
21565 struct depr_insn_mask
21567 unsigned long pattern
;
21568 unsigned long mask
;
21569 const char* description
;
21572 /* List of 16-bit instruction patterns deprecated in an IT block in
21574 static const struct depr_insn_mask depr_it_insns
[] = {
21575 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21576 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21577 { 0xa000, 0xb800, N_("ADR") },
21578 { 0x4800, 0xf800, N_("Literal loads") },
21579 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21580 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21581 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21582 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21583 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21588 it_fsm_post_encode (void)
21592 if (!now_pred
.state_handled
)
21593 handle_pred_state ();
21595 if (now_pred
.insn_cond
21596 && !now_pred
.warn_deprecated
21597 && warn_on_deprecated
21598 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
21599 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
21601 if (inst
.instruction
>= 0x10000)
21603 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21604 "performance deprecated in ARMv8-A and ARMv8-R"));
21605 now_pred
.warn_deprecated
= TRUE
;
21609 const struct depr_insn_mask
*p
= depr_it_insns
;
21611 while (p
->mask
!= 0)
21613 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
21615 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21616 "instructions of the following class are "
21617 "performance deprecated in ARMv8-A and "
21618 "ARMv8-R: %s"), p
->description
);
21619 now_pred
.warn_deprecated
= TRUE
;
21627 if (now_pred
.block_length
> 1)
21629 as_tsktsk (_("IT blocks containing more than one conditional "
21630 "instruction are performance deprecated in ARMv8-A and "
21632 now_pred
.warn_deprecated
= TRUE
;
21636 is_last
= (now_pred
.mask
== 0x10);
21639 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21645 force_automatic_it_block_close (void)
21647 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
21649 close_automatic_it_block ();
21650 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21656 in_pred_block (void)
21658 if (!now_pred
.state_handled
)
21659 handle_pred_state ();
21661 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
21664 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21665 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21666 here, hence the "known" in the function name. */
21669 known_t32_only_insn (const struct asm_opcode
*opcode
)
21671 /* Original Thumb-1 wide instruction. */
21672 if (opcode
->tencode
== do_t_blx
21673 || opcode
->tencode
== do_t_branch23
21674 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
21675 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
21678 /* Wide-only instruction added to ARMv8-M Baseline. */
21679 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
21680 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
21681 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
21682 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
21688 /* Whether wide instruction variant can be used if available for a valid OPCODE
21692 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
21694 if (known_t32_only_insn (opcode
))
21697 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21698 of variant T3 of B.W is checked in do_t_branch. */
21699 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21700 && opcode
->tencode
== do_t_branch
)
21703 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21704 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21705 && opcode
->tencode
== do_t_mov_cmp
21706 /* Make sure CMP instruction is not affected. */
21707 && opcode
->aencode
== do_mov
)
21710 /* Wide instruction variants of all instructions with narrow *and* wide
21711 variants become available with ARMv6t2. Other opcodes are either
21712 narrow-only or wide-only and are thus available if OPCODE is valid. */
21713 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
21716 /* OPCODE with narrow only instruction variant or wide variant not
21722 md_assemble (char *str
)
21725 const struct asm_opcode
* opcode
;
21727 /* Align the previous label if needed. */
21728 if (last_label_seen
!= NULL
)
21730 symbol_set_frag (last_label_seen
, frag_now
);
21731 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
21732 S_SET_SEGMENT (last_label_seen
, now_seg
);
21735 memset (&inst
, '\0', sizeof (inst
));
21737 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21738 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
21740 opcode
= opcode_lookup (&p
);
21743 /* It wasn't an instruction, but it might be a register alias of
21744 the form alias .req reg, or a Neon .dn/.qn directive. */
21745 if (! create_register_alias (str
, p
)
21746 && ! create_neon_reg_alias (str
, p
))
21747 as_bad (_("bad instruction `%s'"), str
);
21752 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
21753 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21755 /* The value which unconditional instructions should have in place of the
21756 condition field. */
21757 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
21761 arm_feature_set variant
;
21763 variant
= cpu_variant
;
21764 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21765 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
21766 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
21767 /* Check that this instruction is supported for this CPU. */
21768 if (!opcode
->tvariant
21769 || (thumb_mode
== 1
21770 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
21772 if (opcode
->tencode
== do_t_swi
)
21773 as_bad (_("SVC is not permitted on this architecture"));
21775 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
21778 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
21779 && opcode
->tencode
!= do_t_branch
)
21781 as_bad (_("Thumb does not support conditional execution"));
21785 /* Two things are addressed here:
21786 1) Implicit require narrow instructions on Thumb-1.
21787 This avoids relaxation accidentally introducing Thumb-2
21789 2) Reject wide instructions in non Thumb-2 cores.
21791 Only instructions with narrow and wide variants need to be handled
21792 but selecting all non wide-only instructions is easier. */
21793 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
21794 && !t32_insn_ok (variant
, opcode
))
21796 if (inst
.size_req
== 0)
21798 else if (inst
.size_req
== 4)
21800 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
21801 as_bad (_("selected processor does not support 32bit wide "
21802 "variant of instruction `%s'"), str
);
21804 as_bad (_("selected processor does not support `%s' in "
21805 "Thumb-2 mode"), str
);
21810 inst
.instruction
= opcode
->tvalue
;
21812 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
21814 /* Prepare the pred_insn_type for those encodings that don't set
21816 it_fsm_pre_encode ();
21818 opcode
->tencode ();
21820 it_fsm_post_encode ();
21823 if (!(inst
.error
|| inst
.relax
))
21825 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
21826 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
21827 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
21829 as_bad (_("cannot honor width suffix -- `%s'"), str
);
21834 /* Something has gone badly wrong if we try to relax a fixed size
21836 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
21838 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21839 *opcode
->tvariant
);
21840 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21841 set those bits when Thumb-2 32-bit instructions are seen. The impact
21842 of relaxable instructions will be considered later after we finish all
21844 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
21845 variant
= arm_arch_none
;
21847 variant
= cpu_variant
;
21848 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
21849 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21852 check_neon_suffixes
;
21856 mapping_state (MAP_THUMB
);
21859 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21863 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21864 is_bx
= (opcode
->aencode
== do_bx
);
21866 /* Check that this instruction is supported for this CPU. */
21867 if (!(is_bx
&& fix_v4bx
)
21868 && !(opcode
->avariant
&&
21869 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
21871 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
21876 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
21880 inst
.instruction
= opcode
->avalue
;
21881 if (opcode
->tag
== OT_unconditionalF
)
21882 inst
.instruction
|= 0xFU
<< 28;
21884 inst
.instruction
|= inst
.cond
<< 28;
21885 inst
.size
= INSN_SIZE
;
21886 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
21888 it_fsm_pre_encode ();
21889 opcode
->aencode ();
21890 it_fsm_post_encode ();
21892 /* Arm mode bx is marked as both v4T and v5 because it's still required
21893 on a hypothetical non-thumb v5 core. */
21895 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
21897 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
21898 *opcode
->avariant
);
21900 check_neon_suffixes
;
21904 mapping_state (MAP_ARM
);
21909 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21917 check_pred_blocks_finished (void)
21922 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
21923 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
21924 == MANUAL_PRED_BLOCK
)
21926 if (now_pred
.type
== SCALAR_PRED
)
21927 as_warn (_("section '%s' finished with an open IT block."),
21930 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21934 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
21936 if (now_pred
.type
== SCALAR_PRED
)
21937 as_warn (_("file finished with an open IT block."));
21939 as_warn (_("file finished with an open VPT/VPST block."));
21944 /* Various frobbings of labels and their addresses. */
21947 arm_start_line_hook (void)
21949 last_label_seen
= NULL
;
21953 arm_frob_label (symbolS
* sym
)
21955 last_label_seen
= sym
;
21957 ARM_SET_THUMB (sym
, thumb_mode
);
21959 #if defined OBJ_COFF || defined OBJ_ELF
21960 ARM_SET_INTERWORK (sym
, support_interwork
);
21963 force_automatic_it_block_close ();
21965 /* Note - do not allow local symbols (.Lxxx) to be labelled
21966 as Thumb functions. This is because these labels, whilst
21967 they exist inside Thumb code, are not the entry points for
21968 possible ARM->Thumb calls. Also, these labels can be used
21969 as part of a computed goto or switch statement. eg gcc
21970 can generate code that looks like this:
21972 ldr r2, [pc, .Laaa]
21982 The first instruction loads the address of the jump table.
21983 The second instruction converts a table index into a byte offset.
21984 The third instruction gets the jump address out of the table.
21985 The fourth instruction performs the jump.
21987 If the address stored at .Laaa is that of a symbol which has the
21988 Thumb_Func bit set, then the linker will arrange for this address
21989 to have the bottom bit set, which in turn would mean that the
21990 address computation performed by the third instruction would end
21991 up with the bottom bit set. Since the ARM is capable of unaligned
21992 word loads, the instruction would then load the incorrect address
21993 out of the jump table, and chaos would ensue. */
21994 if (label_is_thumb_function_name
21995 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21996 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21998 /* When the address of a Thumb function is taken the bottom
21999 bit of that address should be set. This will allow
22000 interworking between Arm and Thumb functions to work
22003 THUMB_SET_FUNC (sym
, 1);
22005 label_is_thumb_function_name
= FALSE
;
22008 dwarf2_emit_label (sym
);
22012 arm_data_in_code (void)
22014 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22016 *input_line_pointer
= '/';
22017 input_line_pointer
+= 5;
22018 *input_line_pointer
= 0;
22026 arm_canonicalize_symbol_name (char * name
)
22030 if (thumb_mode
&& (len
= strlen (name
)) > 5
22031 && streq (name
+ len
- 5, "/data"))
22032 *(name
+ len
- 5) = 0;
22037 /* Table of all register names defined by default. The user can
22038 define additional names with .req. Note that all register names
22039 should appear in both upper and lowercase variants. Some registers
22040 also have mixed-case names. */
22042 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22043 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22044 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22045 #define REGSET(p,t) \
22046 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22047 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22048 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22049 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22050 #define REGSETH(p,t) \
22051 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22052 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22053 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22054 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22055 #define REGSET2(p,t) \
22056 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22057 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22058 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22059 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22060 #define SPLRBANK(base,bank,t) \
22061 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22062 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22063 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22064 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22065 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22066 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22068 static const struct reg_entry reg_names
[] =
22070 /* ARM integer registers. */
22071 REGSET(r
, RN
), REGSET(R
, RN
),
22073 /* ATPCS synonyms. */
22074 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22075 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22076 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22078 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22079 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22080 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22082 /* Well-known aliases. */
22083 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22084 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22086 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22087 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22089 /* Defining the new Zero register from ARMv8.1-M. */
22093 /* Coprocessor numbers. */
22094 REGSET(p
, CP
), REGSET(P
, CP
),
22096 /* Coprocessor register numbers. The "cr" variants are for backward
22098 REGSET(c
, CN
), REGSET(C
, CN
),
22099 REGSET(cr
, CN
), REGSET(CR
, CN
),
22101 /* ARM banked registers. */
22102 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22103 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22104 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22105 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22106 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22107 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22108 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22110 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22111 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22112 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22113 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22114 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22115 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22116 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22117 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22119 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22120 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22121 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22122 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22123 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22124 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22125 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22126 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22127 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22129 /* FPA registers. */
22130 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22131 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22133 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22134 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22136 /* VFP SP registers. */
22137 REGSET(s
,VFS
), REGSET(S
,VFS
),
22138 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22140 /* VFP DP Registers. */
22141 REGSET(d
,VFD
), REGSET(D
,VFD
),
22142 /* Extra Neon DP registers. */
22143 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22145 /* Neon QP registers. */
22146 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22148 /* VFP control registers. */
22149 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22150 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22151 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22152 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22153 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22154 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22155 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22157 /* Maverick DSP coprocessor registers. */
22158 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22159 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22161 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22162 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22163 REGDEF(dspsc
,0,DSPSC
),
22165 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22166 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22167 REGDEF(DSPSC
,0,DSPSC
),
22169 /* iWMMXt data registers - p0, c0-15. */
22170 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22172 /* iWMMXt control registers - p1, c0-3. */
22173 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22174 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22175 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22176 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22178 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22179 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22180 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22181 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22182 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22184 /* XScale accumulator registers. */
22185 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22191 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22192 within psr_required_here. */
22193 static const struct asm_psr psrs
[] =
22195 /* Backward compatibility notation. Note that "all" is no longer
22196 truly all possible PSR bits. */
22197 {"all", PSR_c
| PSR_f
},
22201 /* Individual flags. */
22207 /* Combinations of flags. */
22208 {"fs", PSR_f
| PSR_s
},
22209 {"fx", PSR_f
| PSR_x
},
22210 {"fc", PSR_f
| PSR_c
},
22211 {"sf", PSR_s
| PSR_f
},
22212 {"sx", PSR_s
| PSR_x
},
22213 {"sc", PSR_s
| PSR_c
},
22214 {"xf", PSR_x
| PSR_f
},
22215 {"xs", PSR_x
| PSR_s
},
22216 {"xc", PSR_x
| PSR_c
},
22217 {"cf", PSR_c
| PSR_f
},
22218 {"cs", PSR_c
| PSR_s
},
22219 {"cx", PSR_c
| PSR_x
},
22220 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22221 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22222 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22223 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22224 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22225 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22226 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22227 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22228 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22229 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22230 {"scf", PSR_s
| PSR_c
| PSR_f
},
22231 {"scx", PSR_s
| PSR_c
| PSR_x
},
22232 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22233 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22234 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22235 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22236 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22237 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22238 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22239 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22240 {"csf", PSR_c
| PSR_s
| PSR_f
},
22241 {"csx", PSR_c
| PSR_s
| PSR_x
},
22242 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22243 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22244 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22245 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22246 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22247 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22248 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22249 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22250 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22251 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22252 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22253 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22254 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22255 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22256 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22257 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22258 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22259 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22260 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22261 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22262 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22263 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22264 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22265 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22266 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22267 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22270 /* Table of V7M psr names. */
22271 static const struct asm_psr v7m_psrs
[] =
22273 {"apsr", 0x0 }, {"APSR", 0x0 },
22274 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22275 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22276 {"psr", 0x3 }, {"PSR", 0x3 },
22277 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22278 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22279 {"epsr", 0x6 }, {"EPSR", 0x6 },
22280 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22281 {"msp", 0x8 }, {"MSP", 0x8 },
22282 {"psp", 0x9 }, {"PSP", 0x9 },
22283 {"msplim", 0xa }, {"MSPLIM", 0xa },
22284 {"psplim", 0xb }, {"PSPLIM", 0xb },
22285 {"primask", 0x10}, {"PRIMASK", 0x10},
22286 {"basepri", 0x11}, {"BASEPRI", 0x11},
22287 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22288 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22289 {"control", 0x14}, {"CONTROL", 0x14},
22290 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22291 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22292 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22293 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22294 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22295 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22296 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22297 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22298 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22301 /* Table of all shift-in-operand names. */
22302 static const struct asm_shift_name shift_names
[] =
22304 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22305 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22306 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22307 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22308 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22309 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22310 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22313 /* Table of all explicit relocation names. */
22315 static struct reloc_entry reloc_names
[] =
22317 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22318 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22319 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22320 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22321 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22322 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22323 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22324 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22325 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22326 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22327 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22328 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22329 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22330 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22331 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22332 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22333 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22334 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22335 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22336 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22337 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22338 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22339 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22340 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22341 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22342 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22343 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22347 /* Table of all conditional affixes. */
22348 static const struct asm_cond conds
[] =
22352 {"cs", 0x2}, {"hs", 0x2},
22353 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22366 static const struct asm_cond vconds
[] =
22372 #define UL_BARRIER(L,U,CODE,FEAT) \
22373 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22374 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22376 static struct asm_barrier_opt barrier_opt_names
[] =
22378 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22379 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22380 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22381 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22382 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22383 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22384 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22385 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22386 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22387 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22388 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22389 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22390 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22391 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22392 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22393 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22398 /* Table of ARM-format instructions. */
22400 /* Macros for gluing together operand strings. N.B. In all cases
22401 other than OPS0, the trailing OP_stop comes from default
22402 zero-initialization of the unspecified elements of the array. */
22403 #define OPS0() { OP_stop, }
22404 #define OPS1(a) { OP_##a, }
22405 #define OPS2(a,b) { OP_##a,OP_##b, }
22406 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22407 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22408 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22409 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22411 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22412 This is useful when mixing operands for ARM and THUMB, i.e. using the
22413 MIX_ARM_THUMB_OPERANDS macro.
22414 In order to use these macros, prefix the number of operands with _
22416 #define OPS_1(a) { a, }
22417 #define OPS_2(a,b) { a,b, }
22418 #define OPS_3(a,b,c) { a,b,c, }
22419 #define OPS_4(a,b,c,d) { a,b,c,d, }
22420 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22421 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22423 /* These macros abstract out the exact format of the mnemonic table and
22424 save some repeated characters. */
22426 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22427 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22428 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22429 THUMB_VARIANT, do_##ae, do_##te, 0 }
22431 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22432 a T_MNEM_xyz enumerator. */
22433 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22434 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22435 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22436 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22438 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22439 infix after the third character. */
22440 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22441 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22442 THUMB_VARIANT, do_##ae, do_##te, 0 }
22443 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22444 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22445 THUMB_VARIANT, do_##ae, do_##te, 0 }
22446 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22447 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22448 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22449 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
22450 #define tC3(mnem, aop, top, nops, ops, ae, te) \
22451 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22452 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
22453 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22455 /* Mnemonic that cannot be conditionalized. The ARM condition-code
22456 field is still 0xE. Many of the Thumb variants can be executed
22457 conditionally, so this is checked separately. */
22458 #define TUE(mnem, op, top, nops, ops, ae, te) \
22459 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22460 THUMB_VARIANT, do_##ae, do_##te, 0 }
22462 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
22463 Used by mnemonics that have very minimal differences in the encoding for
22464 ARM and Thumb variants and can be handled in a common function. */
22465 #define TUEc(mnem, op, top, nops, ops, en) \
22466 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
22467 THUMB_VARIANT, do_##en, do_##en, 0 }
22469 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
22470 condition code field. */
22471 #define TUF(mnem, op, top, nops, ops, ae, te) \
22472 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
22473 THUMB_VARIANT, do_##ae, do_##te, 0 }
22475 /* ARM-only variants of all the above. */
22476 #define CE(mnem, op, nops, ops, ae) \
22477 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22479 #define C3(mnem, op, nops, ops, ae) \
22480 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22482 /* Thumb-only variants of TCE and TUE. */
22483 #define ToC(mnem, top, nops, ops, te) \
22484 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22487 #define ToU(mnem, top, nops, ops, te) \
22488 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
22491 /* T_MNEM_xyz enumerator variants of ToC. */
22492 #define toC(mnem, top, nops, ops, te) \
22493 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
22496 /* T_MNEM_xyz enumerator variants of ToU. */
22497 #define toU(mnem, top, nops, ops, te) \
22498 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
22501 /* Legacy mnemonics that always have conditional infix after the third
22503 #define CL(mnem, op, nops, ops, ae) \
22504 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22505 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22507 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
22508 #define cCE(mnem, op, nops, ops, ae) \
22509 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22511 /* mov instructions that are shared between coprocessor and MVE. */
22512 #define mcCE(mnem, op, nops, ops, ae) \
22513 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22515 /* Legacy coprocessor instructions where conditional infix and conditional
22516 suffix are ambiguous. For consistency this includes all FPA instructions,
22517 not just the potentially ambiguous ones. */
22518 #define cCL(mnem, op, nops, ops, ae) \
22519 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22520 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22522 /* Coprocessor, takes either a suffix or a position-3 infix
22523 (for an FPA corner case). */
22524 #define C3E(mnem, op, nops, ops, ae) \
22525 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22526 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22528 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22529 { m1 #m2 m3, OPS##nops ops, \
22530 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22531 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22533 #define CM(m1, m2, op, nops, ops, ae) \
22534 xCM_ (m1, , m2, op, nops, ops, ae), \
22535 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22536 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22537 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22538 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22539 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22540 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22541 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22542 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22543 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22544 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22545 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22546 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22547 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22548 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22549 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22550 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22551 xCM_ (m1, le, m2, op, nops, ops, ae), \
22552 xCM_ (m1, al, m2, op, nops, ops, ae)
22554 #define UE(mnem, op, nops, ops, ae) \
22555 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22557 #define UF(mnem, op, nops, ops, ae) \
22558 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22560 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22561 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22562 use the same encoding function for each. */
22563 #define NUF(mnem, op, nops, ops, enc) \
22564 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22565 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22567 /* Neon data processing, version which indirects through neon_enc_tab for
22568 the various overloaded versions of opcodes. */
22569 #define nUF(mnem, op, nops, ops, enc) \
22570 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22571 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22573 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22575 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22576 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22577 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22579 #define NCE(mnem, op, nops, ops, enc) \
22580 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22582 #define NCEF(mnem, op, nops, ops, enc) \
22583 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22585 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22586 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22587 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22588 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22590 #define nCE(mnem, op, nops, ops, enc) \
22591 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22593 #define nCEF(mnem, op, nops, ops, enc) \
22594 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22597 #define mCEF(mnem, op, nops, ops, enc) \
22598 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22599 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22602 /* nCEF but for MVE predicated instructions. */
22603 #define mnCEF(mnem, op, nops, ops, enc) \
22604 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22606 /* nCE but for MVE predicated instructions. */
22607 #define mnCE(mnem, op, nops, ops, enc) \
22608 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22610 /* NUF but for potentially MVE predicated instructions. */
22611 #define MNUF(mnem, op, nops, ops, enc) \
22612 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22613 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22615 /* nUF but for potentially MVE predicated instructions. */
22616 #define mnUF(mnem, op, nops, ops, enc) \
22617 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22618 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22620 /* ToC but for potentially MVE predicated instructions. */
22621 #define mToC(mnem, top, nops, ops, te) \
22622 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22625 /* NCE but for MVE predicated instructions. */
22626 #define MNCE(mnem, op, nops, ops, enc) \
22627 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22629 /* NCEF but for MVE predicated instructions. */
22630 #define MNCEF(mnem, op, nops, ops, enc) \
22631 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22634 static const struct asm_opcode insns
[] =
22636 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22637 #define THUMB_VARIANT & arm_ext_v4t
22638 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22639 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22640 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22641 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22642 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22643 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22644 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22645 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22646 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22647 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22648 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22649 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22650 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22651 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22652 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22653 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22655 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22656 for setting PSR flag bits. They are obsolete in V6 and do not
22657 have Thumb equivalents. */
22658 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22659 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22660 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
22661 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22662 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22663 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
22664 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22665 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22666 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
22668 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
22669 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
22670 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22671 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22673 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
22674 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22675 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
22677 OP_ADDRGLDR
),ldst
, t_ldst
),
22678 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22680 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22681 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22682 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22683 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22684 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22685 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22687 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
22688 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
22691 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
22692 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
22693 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
22694 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
22696 /* Thumb-compatibility pseudo ops. */
22697 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22698 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22699 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22700 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22701 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22702 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22703 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22704 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22705 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
22706 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
22707 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
22708 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
22710 /* These may simplify to neg. */
22711 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22712 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22714 #undef THUMB_VARIANT
22715 #define THUMB_VARIANT & arm_ext_os
22717 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22718 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22720 #undef THUMB_VARIANT
22721 #define THUMB_VARIANT & arm_ext_v6
22723 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
22725 /* V1 instructions with no Thumb analogue prior to V6T2. */
22726 #undef THUMB_VARIANT
22727 #define THUMB_VARIANT & arm_ext_v6t2
22729 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22730 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22731 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
22733 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22734 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22735 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
22736 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22738 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22739 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22741 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22742 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22744 /* V1 instructions with no Thumb analogue at all. */
22745 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
22746 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
22748 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22749 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22750 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22751 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22752 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22753 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22754 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22755 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22758 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22759 #undef THUMB_VARIANT
22760 #define THUMB_VARIANT & arm_ext_v4t
22762 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22763 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22765 #undef THUMB_VARIANT
22766 #define THUMB_VARIANT & arm_ext_v6t2
22768 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22769 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
22771 /* Generic coprocessor instructions. */
22772 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22773 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22774 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22775 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22776 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22777 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22778 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22781 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22783 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22784 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22787 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22788 #undef THUMB_VARIANT
22789 #define THUMB_VARIANT & arm_ext_msr
22791 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
22792 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
22795 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22796 #undef THUMB_VARIANT
22797 #define THUMB_VARIANT & arm_ext_v6t2
22799 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22800 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22801 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22802 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22803 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22804 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22805 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22806 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22809 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22810 #undef THUMB_VARIANT
22811 #define THUMB_VARIANT & arm_ext_v4t
22813 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22814 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22815 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22816 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22817 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22818 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22821 #define ARM_VARIANT & arm_ext_v4t_5
22823 /* ARM Architecture 4T. */
22824 /* Note: bx (and blx) are required on V5, even if the processor does
22825 not support Thumb. */
22826 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
22829 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22830 #undef THUMB_VARIANT
22831 #define THUMB_VARIANT & arm_ext_v5t
22833 /* Note: blx has 2 variants; the .value coded here is for
22834 BLX(2). Only this variant has conditional execution. */
22835 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
22836 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
22838 #undef THUMB_VARIANT
22839 #define THUMB_VARIANT & arm_ext_v6t2
22841 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
22842 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22843 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22844 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22845 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22846 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22847 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22848 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22851 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22852 #undef THUMB_VARIANT
22853 #define THUMB_VARIANT & arm_ext_v5exp
22855 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22856 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22857 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22858 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22860 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22861 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22863 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22864 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22865 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22866 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22868 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22869 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22870 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22871 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22873 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22874 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22876 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22877 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22878 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22879 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22882 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22883 #undef THUMB_VARIANT
22884 #define THUMB_VARIANT & arm_ext_v6t2
22886 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
22887 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
22889 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
22890 ADDRGLDRS
), ldrd
, t_ldstd
),
22892 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22893 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22896 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22898 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
22901 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22902 #undef THUMB_VARIANT
22903 #define THUMB_VARIANT & arm_ext_v6
22905 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22906 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22907 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22908 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22909 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22910 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22911 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22912 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22913 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22914 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
22916 #undef THUMB_VARIANT
22917 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22919 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
22920 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22922 #undef THUMB_VARIANT
22923 #define THUMB_VARIANT & arm_ext_v6t2
22925 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22926 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22928 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
22929 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
22931 /* ARM V6 not included in V7M. */
22932 #undef THUMB_VARIANT
22933 #define THUMB_VARIANT & arm_ext_v6_notm
22934 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22935 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22936 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
22937 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
22938 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22939 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22940 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
22941 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22942 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
22943 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22944 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22945 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22946 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22947 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22948 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
22949 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
22950 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22951 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22952 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
22954 /* ARM V6 not included in V7M (eg. integer SIMD). */
22955 #undef THUMB_VARIANT
22956 #define THUMB_VARIANT & arm_ext_v6_dsp
22957 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
22958 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
22959 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22960 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22961 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22962 /* Old name for QASX. */
22963 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22964 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22965 /* Old name for QSAX. */
22966 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22967 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22968 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22969 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22970 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22971 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22972 /* Old name for SASX. */
22973 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22974 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22975 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22976 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22977 /* Old name for SHASX. */
22978 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22979 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22980 /* Old name for SHSAX. */
22981 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22982 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22983 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22984 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22985 /* Old name for SSAX. */
22986 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22987 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22988 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22989 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22990 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22991 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22992 /* Old name for UASX. */
22993 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22994 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22995 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22996 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22997 /* Old name for UHASX. */
22998 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22999 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23000 /* Old name for UHSAX. */
23001 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23002 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23003 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23004 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23005 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23006 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23007 /* Old name for UQASX. */
23008 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23009 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23010 /* Old name for UQSAX. */
23011 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23012 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23013 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23014 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23015 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23016 /* Old name for USAX. */
23017 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23018 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23019 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23020 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23021 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23022 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23023 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23024 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23025 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23026 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23027 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23028 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23029 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23030 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23031 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23032 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23033 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23034 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23035 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23036 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23037 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23038 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23039 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23040 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23041 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23042 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23043 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23044 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23045 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23046 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23047 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23048 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23049 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23050 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23053 #define ARM_VARIANT & arm_ext_v6k_v6t2
23054 #undef THUMB_VARIANT
23055 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23057 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23058 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23059 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23060 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23062 #undef THUMB_VARIANT
23063 #define THUMB_VARIANT & arm_ext_v6_notm
23064 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23066 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23067 RRnpcb
), strexd
, t_strexd
),
23069 #undef THUMB_VARIANT
23070 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23071 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23073 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23075 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23077 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23079 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23082 #define ARM_VARIANT & arm_ext_sec
23083 #undef THUMB_VARIANT
23084 #define THUMB_VARIANT & arm_ext_sec
23086 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23089 #define ARM_VARIANT & arm_ext_virt
23090 #undef THUMB_VARIANT
23091 #define THUMB_VARIANT & arm_ext_virt
23093 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23094 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23097 #define ARM_VARIANT & arm_ext_pan
23098 #undef THUMB_VARIANT
23099 #define THUMB_VARIANT & arm_ext_pan
23101 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23104 #define ARM_VARIANT & arm_ext_v6t2
23105 #undef THUMB_VARIANT
23106 #define THUMB_VARIANT & arm_ext_v6t2
23108 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23109 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23110 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23111 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23113 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23114 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23116 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23117 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23118 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23119 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23122 #define ARM_VARIANT & arm_ext_v3
23123 #undef THUMB_VARIANT
23124 #define THUMB_VARIANT & arm_ext_v6t2
23126 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23127 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23128 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23131 #define ARM_VARIANT & arm_ext_v6t2
23132 #undef THUMB_VARIANT
23133 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23134 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23135 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23137 /* Thumb-only instructions. */
23139 #define ARM_VARIANT NULL
23140 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23141 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23143 /* ARM does not really have an IT instruction, so always allow it.
23144 The opcode is copied from Thumb in order to allow warnings in
23145 -mimplicit-it=[never | arm] modes. */
23147 #define ARM_VARIANT & arm_ext_v1
23148 #undef THUMB_VARIANT
23149 #define THUMB_VARIANT & arm_ext_v6t2
23151 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23152 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23153 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23154 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23155 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23156 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23157 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23158 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23159 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23160 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23161 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23162 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23163 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23164 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23165 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23166 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23167 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23168 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23170 /* Thumb2 only instructions. */
23172 #define ARM_VARIANT NULL
23174 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23175 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23176 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23177 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23178 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23179 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23181 /* Hardware division instructions. */
23183 #define ARM_VARIANT & arm_ext_adiv
23184 #undef THUMB_VARIANT
23185 #define THUMB_VARIANT & arm_ext_div
23187 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23188 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23190 /* ARM V6M/V7 instructions. */
23192 #define ARM_VARIANT & arm_ext_barrier
23193 #undef THUMB_VARIANT
23194 #define THUMB_VARIANT & arm_ext_barrier
23196 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23197 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23198 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23200 /* ARM V7 instructions. */
23202 #define ARM_VARIANT & arm_ext_v7
23203 #undef THUMB_VARIANT
23204 #define THUMB_VARIANT & arm_ext_v7
23206 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23207 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23210 #define ARM_VARIANT & arm_ext_mp
23211 #undef THUMB_VARIANT
23212 #define THUMB_VARIANT & arm_ext_mp
23214 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23216 /* AArchv8 instructions. */
23218 #define ARM_VARIANT & arm_ext_v8
23220 /* Instructions shared between armv8-a and armv8-m. */
23221 #undef THUMB_VARIANT
23222 #define THUMB_VARIANT & arm_ext_atomics
23224 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23225 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23226 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23227 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23228 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23229 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23230 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23231 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23232 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23233 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23235 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23237 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23239 #undef THUMB_VARIANT
23240 #define THUMB_VARIANT & arm_ext_v8
23242 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23243 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23245 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23248 /* Defined in V8 but is in undefined encoding space for earlier
23249 architectures. However earlier architectures are required to treat
23250 this instuction as a semihosting trap as well. Hence while not explicitly
23251 defined as such, it is in fact correct to define the instruction for all
23253 #undef THUMB_VARIANT
23254 #define THUMB_VARIANT & arm_ext_v1
23256 #define ARM_VARIANT & arm_ext_v1
23257 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23259 /* ARMv8 T32 only. */
23261 #define ARM_VARIANT NULL
23262 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23263 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23264 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23266 /* FP for ARMv8. */
23268 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23269 #undef THUMB_VARIANT
23270 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23272 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23273 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23274 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23275 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23276 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23277 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
23278 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
23279 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
23280 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
23281 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
23282 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
23284 /* Crypto v1 extensions. */
23286 #define ARM_VARIANT & fpu_crypto_ext_armv8
23287 #undef THUMB_VARIANT
23288 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23290 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23291 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23292 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23293 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23294 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23295 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23296 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23297 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23298 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23299 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23300 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23301 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23302 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23303 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23306 #define ARM_VARIANT & crc_ext_armv8
23307 #undef THUMB_VARIANT
23308 #define THUMB_VARIANT & crc_ext_armv8
23309 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23310 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23311 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23312 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23313 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23314 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23316 /* ARMv8.2 RAS extension. */
23318 #define ARM_VARIANT & arm_ext_ras
23319 #undef THUMB_VARIANT
23320 #define THUMB_VARIANT & arm_ext_ras
23321 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23324 #define ARM_VARIANT & arm_ext_v8_3
23325 #undef THUMB_VARIANT
23326 #define THUMB_VARIANT & arm_ext_v8_3
23327 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23330 #define ARM_VARIANT & fpu_neon_ext_dotprod
23331 #undef THUMB_VARIANT
23332 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23333 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23334 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23337 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23338 #undef THUMB_VARIANT
23339 #define THUMB_VARIANT NULL
23341 cCE("wfs", e200110
, 1, (RR
), rd
),
23342 cCE("rfs", e300110
, 1, (RR
), rd
),
23343 cCE("wfc", e400110
, 1, (RR
), rd
),
23344 cCE("rfc", e500110
, 1, (RR
), rd
),
23346 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23347 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23348 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23349 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23351 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23352 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23353 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23354 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23356 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23357 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23358 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23359 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23360 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23361 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23362 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23363 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23364 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23365 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23366 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23367 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23369 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23370 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23371 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23372 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23373 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23374 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23375 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23376 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23377 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23378 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23379 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23380 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23382 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23383 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23384 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23385 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23386 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23387 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23388 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23389 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23390 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23391 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23392 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23393 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23395 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23396 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23397 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23398 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23399 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23400 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23401 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23402 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23403 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23404 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23405 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23406 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23408 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23409 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23410 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23411 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23412 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23413 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23414 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23415 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23416 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23417 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23418 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23419 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23421 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23422 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23423 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23424 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23425 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23426 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23427 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23428 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23429 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23430 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23431 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23432 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23434 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23435 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23436 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23437 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23438 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23439 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23440 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23441 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23442 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23443 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23444 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
23445 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
23447 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
23448 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
23449 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
23450 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
23451 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
23452 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
23453 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
23454 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
23455 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
23456 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
23457 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
23458 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
23460 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
23461 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
23462 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
23463 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
23464 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
23465 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
23466 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
23467 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
23468 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
23469 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
23470 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
23471 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
23473 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
23474 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
23475 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
23476 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
23477 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
23478 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
23479 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
23480 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
23481 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
23482 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
23483 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
23484 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
23486 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
23487 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
23488 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
23489 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
23490 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
23491 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
23492 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
23493 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
23494 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
23495 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
23496 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
23497 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
23499 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
23500 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
23501 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
23502 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
23503 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
23504 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
23505 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
23506 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
23507 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
23508 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
23509 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
23510 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
23512 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
23513 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
23514 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
23515 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
23516 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
23517 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
23518 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
23519 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
23520 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
23521 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
23522 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
23523 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
23525 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
23526 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
23527 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
23528 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
23529 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
23530 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
23531 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
23532 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
23533 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
23534 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
23535 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
23536 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
23538 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
23539 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
23540 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
23541 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
23542 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
23543 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
23544 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
23545 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
23546 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
23547 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
23548 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
23549 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
23551 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
23552 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
23553 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
23554 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
23555 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
23556 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
23557 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
23558 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
23559 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
23560 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
23561 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
23562 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
23564 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23565 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23566 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23567 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23568 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23569 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23570 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23571 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23572 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23573 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23574 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23575 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23577 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23578 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23579 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23580 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23581 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23582 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23583 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23584 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23585 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23586 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23587 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23588 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23590 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23591 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23592 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23593 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23594 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23595 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23596 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23597 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23598 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23599 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23600 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23601 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23603 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23604 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23605 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23606 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23607 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23608 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23609 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23610 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23611 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23612 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23613 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23614 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23616 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23617 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23618 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23619 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23620 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23621 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23622 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23623 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23624 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23625 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23626 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23627 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23629 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23630 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23631 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23632 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23633 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23634 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23635 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23636 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23637 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23638 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23639 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23640 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23642 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23643 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23644 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23645 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23646 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23647 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23648 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23649 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23650 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23651 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23652 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23653 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23655 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23656 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23657 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23658 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23659 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23660 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23661 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23662 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23663 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23664 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23665 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23666 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23668 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23669 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23670 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23671 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23672 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23673 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23674 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23675 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23676 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23677 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23678 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23679 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23681 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23682 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23683 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23684 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23685 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23686 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23687 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23688 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23689 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23690 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23691 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23692 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23694 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23695 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23696 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23697 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23698 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23699 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23700 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23701 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23702 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23703 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23704 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23705 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23707 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23708 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23709 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23710 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23711 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23712 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23713 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23714 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23715 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23716 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23717 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23718 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23720 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23721 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23722 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23723 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23724 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23725 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23726 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23727 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23728 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23729 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23730 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23731 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23733 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23734 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23735 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23736 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23738 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
23739 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
23740 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
23741 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
23742 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
23743 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
23744 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
23745 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
23746 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
23747 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
23748 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
23749 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
23751 /* The implementation of the FIX instruction is broken on some
23752 assemblers, in that it accepts a precision specifier as well as a
23753 rounding specifier, despite the fact that this is meaningless.
23754 To be more compatible, we accept it as well, though of course it
23755 does not set any bits. */
23756 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
23757 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
23758 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
23759 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
23760 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
23761 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
23762 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
23763 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
23764 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
23765 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
23766 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
23767 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
23768 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
23770 /* Instructions that were new with the real FPA, call them V2. */
23772 #define ARM_VARIANT & fpu_fpa_ext_v2
23774 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23775 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23776 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23777 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23778 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23779 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23782 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23784 /* Moves and type conversions. */
23785 cCE("fmstat", ef1fa10
, 0, (), noargs
),
23786 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
23787 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
23788 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23789 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23790 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23791 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23792 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23793 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23794 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
23795 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
23797 /* Memory operations. */
23798 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23799 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23800 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23801 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23802 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23803 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23804 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23805 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23806 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23807 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23808 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23809 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23810 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23811 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23812 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23813 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23814 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23815 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23817 /* Monadic operations. */
23818 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23819 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23820 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23822 /* Dyadic operations. */
23823 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23824 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23825 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23826 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23827 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23828 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23829 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23830 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23831 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23834 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23835 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
23836 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23837 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
23839 /* Double precision load/store are still present on single precision
23840 implementations. */
23841 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23842 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23843 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23844 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23845 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23846 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23847 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23848 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23849 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23850 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23853 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23855 /* Moves and type conversions. */
23856 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23857 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23858 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23859 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23860 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23861 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23862 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23863 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23864 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23865 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23866 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23867 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23869 /* Monadic operations. */
23870 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23871 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23872 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23874 /* Dyadic operations. */
23875 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23876 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23877 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23878 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23879 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23880 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23881 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23882 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23883 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23886 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23887 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
23888 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23889 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
23891 /* Instructions which may belong to either the Neon or VFP instruction sets.
23892 Individual encoder functions perform additional architecture checks. */
23894 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23895 #undef THUMB_VARIANT
23896 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23898 /* These mnemonics are unique to VFP. */
23899 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
23900 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
23901 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23902 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23903 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23904 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
23905 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
23906 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
23908 /* Mnemonics shared by Neon and VFP. */
23909 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23911 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23912 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23913 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23914 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23915 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23916 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23918 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
23919 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
23920 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
23921 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
23924 /* NOTE: All VMOV encoding is special-cased! */
23925 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
23927 #undef THUMB_VARIANT
23928 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23929 by different feature bits. Since we are setting the Thumb guard, we can
23930 require Thumb-1 which makes it a nop guard and set the right feature bit in
23931 do_vldr_vstr (). */
23932 #define THUMB_VARIANT & arm_ext_v4t
23933 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23934 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23937 #define ARM_VARIANT & arm_ext_fp16
23938 #undef THUMB_VARIANT
23939 #define THUMB_VARIANT & arm_ext_fp16
23940 /* New instructions added from v8.2, allowing the extraction and insertion of
23941 the upper 16 bits of a 32-bit vector register. */
23942 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
23943 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
23945 /* New backported fma/fms instructions optional in v8.2. */
23946 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
23947 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
23949 #undef THUMB_VARIANT
23950 #define THUMB_VARIANT & fpu_neon_ext_v1
23952 #define ARM_VARIANT & fpu_neon_ext_v1
23954 /* Data processing with three registers of the same length. */
23955 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23956 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
23957 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
23958 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23959 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23960 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23961 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23962 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23963 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23964 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23965 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23966 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23967 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23968 /* If not immediate, fall back to neon_dyadic_i64_su.
23969 shl_imm should accept I8 I16 I32 I64,
23970 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23971 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
23972 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
23973 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
23974 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
23975 /* Logic ops, types optional & ignored. */
23976 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23977 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23978 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23979 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23980 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23981 /* Bitfield ops, untyped. */
23982 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23983 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23984 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23985 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23986 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23987 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23988 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23989 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23990 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23991 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23992 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23993 back to neon_dyadic_if_su. */
23994 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23995 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23996 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23997 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23998 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23999 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24000 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24001 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24002 /* Comparison. Type I8 I16 I32 F32. */
24003 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24004 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24005 /* As above, D registers only. */
24006 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24007 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24008 /* Int and float variants, signedness unimportant. */
24009 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24010 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24011 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24012 /* Add/sub take types I8 I16 I32 I64 F32. */
24013 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24014 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24015 /* vtst takes sizes 8, 16, 32. */
24016 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24017 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24018 /* VMUL takes I8 I16 I32 F32 P8. */
24019 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24020 /* VQD{R}MULH takes S16 S32. */
24021 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
24022 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24023 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
24024 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24025 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24026 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24027 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24028 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24029 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24030 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24031 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24032 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24033 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24034 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24035 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24036 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24037 /* ARM v8.1 extension. */
24038 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24039 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24040 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24041 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24043 /* Two address, int/float. Types S8 S16 S32 F32. */
24044 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24045 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24047 /* Data processing with two registers and a shift amount. */
24048 /* Right shifts, and variants with rounding.
24049 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24050 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
24051 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24052 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
24053 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24054 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24055 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24056 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24057 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24058 /* Shift and insert. Sizes accepted 8 16 32 64. */
24059 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
24060 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24061 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
24062 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24063 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24064 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
24065 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24066 /* Right shift immediate, saturating & narrowing, with rounding variants.
24067 Types accepted S16 S32 S64 U16 U32 U64. */
24068 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24069 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24070 /* As above, unsigned. Types accepted S16 S32 S64. */
24071 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24072 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24073 /* Right shift narrowing. Types accepted I16 I32 I64. */
24074 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24075 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24076 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24077 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24078 /* CVT with optional immediate for fixed-point variant. */
24079 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24081 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24083 /* Data processing, three registers of different lengths. */
24084 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24085 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24086 /* If not scalar, fall back to neon_dyadic_long.
24087 Vector types as above, scalar types S16 S32 U16 U32. */
24088 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24089 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24090 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24091 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24092 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24093 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24094 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24095 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24096 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24097 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24098 /* Saturating doubling multiplies. Types S16 S32. */
24099 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24100 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24101 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24102 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24103 S16 S32 U16 U32. */
24104 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24106 /* Extract. Size 8. */
24107 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24108 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24110 /* Two registers, miscellaneous. */
24111 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24112 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
24113 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24114 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
24115 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24116 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
24117 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24118 /* Vector replicate. Sizes 8 16 32. */
24119 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24120 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24121 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24122 /* VMOVN. Types I16 I32 I64. */
24123 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24124 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24125 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24126 /* VQMOVUN. Types S16 S32 S64. */
24127 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24128 /* VZIP / VUZP. Sizes 8 16 32. */
24129 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24130 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24131 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24132 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24133 /* VQABS / VQNEG. Types S8 S16 S32. */
24134 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24135 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24136 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24137 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24138 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24139 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24140 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24141 /* Reciprocal estimates. Types U32 F16 F32. */
24142 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24143 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24144 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24145 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24146 /* VCLS. Types S8 S16 S32. */
24147 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24148 /* VCLZ. Types I8 I16 I32. */
24149 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24150 /* VCNT. Size 8. */
24151 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24152 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24153 /* Two address, untyped. */
24154 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24155 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24156 /* VTRN. Sizes 8 16 32. */
24157 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24158 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24160 /* Table lookup. Size 8. */
24161 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24162 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24164 #undef THUMB_VARIANT
24165 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24167 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24169 /* Neon element/structure load/store. */
24170 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24171 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24172 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24173 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24174 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24175 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24176 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24177 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24179 #undef THUMB_VARIANT
24180 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24182 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24183 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24184 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24185 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24186 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24187 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24188 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24189 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24190 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24191 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24193 #undef THUMB_VARIANT
24194 #define THUMB_VARIANT & fpu_vfp_ext_v3
24196 #define ARM_VARIANT & fpu_vfp_ext_v3
24198 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24199 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24200 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24201 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24202 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24203 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24204 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24205 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24206 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24209 #define ARM_VARIANT & fpu_vfp_ext_fma
24210 #undef THUMB_VARIANT
24211 #define THUMB_VARIANT & fpu_vfp_ext_fma
24212 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24213 VFP FMA variant; NEON and VFP FMA always includes the NEON
24214 FMA instructions. */
24215 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24216 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24218 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24219 the v form should always be used. */
24220 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24221 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24222 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24223 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24224 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24225 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24227 #undef THUMB_VARIANT
24229 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24231 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24232 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24233 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24234 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24235 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24236 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24237 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24238 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24241 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24243 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24244 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24245 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24246 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24247 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24248 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24249 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24250 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24251 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24252 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24253 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24254 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24255 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24256 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24257 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24258 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24259 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24260 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24261 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24262 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24263 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24264 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24265 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24266 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24267 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24268 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24269 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24270 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24271 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24272 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24273 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24274 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24275 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24276 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24277 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24278 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24279 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24280 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24281 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24282 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24283 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24284 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24285 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24286 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24287 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24288 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24289 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24290 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24291 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24292 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24293 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24294 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24295 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24296 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24297 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24298 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24299 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24300 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24301 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24302 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24303 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24304 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24305 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24306 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24307 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24308 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24309 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24310 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24311 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24312 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24313 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24314 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24315 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24316 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24317 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24318 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24319 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24320 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24321 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24322 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24323 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24324 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24325 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24326 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24327 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24328 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24329 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24330 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24331 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24332 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24333 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24334 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24335 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24336 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24337 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24338 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24339 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24340 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24341 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24342 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24343 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24344 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24345 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24346 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24347 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24348 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24349 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24350 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24351 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24352 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24353 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24354 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24355 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24356 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24357 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24358 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24359 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24360 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24361 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24362 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24363 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24364 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24365 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24366 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24367 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24368 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24369 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24370 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24371 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24372 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24373 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24374 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24375 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24376 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24377 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24378 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24379 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24380 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24381 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24382 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24383 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24384 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24385 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24386 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24387 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24388 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24389 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24390 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24391 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24392 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24393 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24394 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24395 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24396 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24397 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24398 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24399 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24400 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24401 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24402 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24403 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24404 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24407 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24409 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24410 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24411 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24412 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24413 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24414 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24415 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24416 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24417 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24418 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24419 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24420 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24421 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24422 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24423 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24424 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24425 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24426 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24427 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24428 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24429 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24430 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24431 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24432 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24433 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24434 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24435 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24436 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24437 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24438 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24439 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24440 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24441 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24442 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24443 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24444 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24445 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24446 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24447 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24448 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24449 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24450 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24451 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24452 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24453 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24454 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24455 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24456 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24457 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24458 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24459 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24460 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24461 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24462 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24463 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24464 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24465 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24468 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
24470 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24471 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24472 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24473 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24474 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
24475 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
24476 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
24477 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
24478 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
24479 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
24480 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
24481 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
24482 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
24483 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
24484 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
24485 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
24486 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
24487 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
24488 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
24489 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
24490 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
24491 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
24492 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
24493 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
24494 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
24495 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
24496 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
24497 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
24498 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
24499 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
24500 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
24501 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
24502 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
24503 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
24504 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
24505 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
24506 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
24507 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
24508 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
24509 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
24510 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
24511 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
24512 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
24513 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
24514 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
24515 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
24516 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
24517 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
24518 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
24519 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
24520 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
24521 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
24522 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
24523 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
24524 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24525 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24526 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24527 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24528 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24529 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24530 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
24531 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
24532 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
24533 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
24534 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24535 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24536 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24537 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24538 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24539 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24540 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24541 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24542 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24543 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24544 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24545 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24547 /* ARMv8.5-A instructions. */
24549 #define ARM_VARIANT & arm_ext_sb
24550 #undef THUMB_VARIANT
24551 #define THUMB_VARIANT & arm_ext_sb
24552 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
24555 #define ARM_VARIANT & arm_ext_predres
24556 #undef THUMB_VARIANT
24557 #define THUMB_VARIANT & arm_ext_predres
24558 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
24559 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
24560 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
24562 /* ARMv8-M instructions. */
24564 #define ARM_VARIANT NULL
24565 #undef THUMB_VARIANT
24566 #define THUMB_VARIANT & arm_ext_v8m
24567 ToU("sg", e97fe97f
, 0, (), noargs
),
24568 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
24569 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
24570 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
24571 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
24572 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
24573 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
24575 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24576 instructions behave as nop if no VFP is present. */
24577 #undef THUMB_VARIANT
24578 #define THUMB_VARIANT & arm_ext_v8m_main
24579 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
24580 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
24582 /* Armv8.1-M Mainline instructions. */
24583 #undef THUMB_VARIANT
24584 #define THUMB_VARIANT & arm_ext_v8_1m_main
24585 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
24586 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
24587 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24588 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
24589 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24591 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
24592 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
24593 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
24595 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
24596 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
24598 #undef THUMB_VARIANT
24599 #define THUMB_VARIANT & mve_ext
24601 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24602 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24603 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24604 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24605 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24606 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24607 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24608 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24609 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24610 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24611 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24612 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24613 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24614 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24615 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24617 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
24618 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
24619 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
24620 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
24621 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
24622 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
24623 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
24624 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
24625 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
24626 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
24627 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
24628 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
24629 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
24630 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
24631 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
24633 /* MVE and MVE FP only. */
24634 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
24635 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24636 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24637 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24638 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24639 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
24640 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
24641 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24642 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24643 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24644 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24645 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24646 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24647 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24648 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24649 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24650 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24652 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24653 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24654 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24655 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24656 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24657 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24658 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24659 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24660 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24661 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24662 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24663 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24664 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24665 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24666 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24667 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24668 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24669 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24670 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24671 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24673 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
24674 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
24675 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
24676 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24677 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24678 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
24679 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
24680 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
24681 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
24682 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
24683 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
24684 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
24685 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
24686 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
24687 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
24688 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
24689 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
24691 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24692 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24693 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24694 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24695 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24696 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24697 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24698 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24699 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24700 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
24701 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24702 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24703 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24704 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24705 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24706 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24707 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24708 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24709 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24710 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
24712 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
24713 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
24714 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
24716 #undef THUMB_VARIANT
24717 #define THUMB_VARIANT & mve_fp_ext
24718 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
24719 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
24720 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
24721 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
24722 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24723 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24724 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24725 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
24728 #define ARM_VARIANT & fpu_vfp_ext_v1
24729 #undef THUMB_VARIANT
24730 #define THUMB_VARIANT & arm_ext_v6t2
24731 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
24732 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
24734 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24737 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24739 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
24740 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
24741 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
24742 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24744 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
24745 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24746 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24748 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24749 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24751 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
24752 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
24754 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24755 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24758 #define ARM_VARIANT & fpu_vfp_ext_v2
24760 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
24761 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
24762 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
24763 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
24766 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24767 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
24768 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
24769 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
24770 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
24771 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
24772 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
24775 #define ARM_VARIANT & fpu_neon_ext_v1
24776 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24777 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
24778 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24779 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24780 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24781 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24782 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24783 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24784 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
24785 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
24786 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
24787 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
24788 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
24789 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
24790 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
24791 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24792 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24793 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
24794 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
24795 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
24796 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
24797 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
24800 #define ARM_VARIANT & arm_ext_v8_3
24801 #undef THUMB_VARIANT
24802 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24803 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
24804 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
24807 #undef THUMB_VARIANT
24839 /* MD interface: bits in the object file. */
24841 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24842 for use in the a.out file, and stores them in the array pointed to by buf.
24843 This knows about the endian-ness of the target machine and does
24844 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24845 2 (short) and 4 (long) Floating numbers are put out as a series of
24846 LITTLENUMS (shorts, here at least). */
24849 md_number_to_chars (char * buf
, valueT val
, int n
)
24851 if (target_big_endian
)
24852 number_to_chars_bigendian (buf
, val
, n
);
24854 number_to_chars_littleendian (buf
, val
, n
);
24858 md_chars_to_number (char * buf
, int n
)
24861 unsigned char * where
= (unsigned char *) buf
;
24863 if (target_big_endian
)
24868 result
|= (*where
++ & 255);
24876 result
|= (where
[n
] & 255);
24883 /* MD interface: Sections. */
24885 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24886 that an rs_machine_dependent frag may reach. */
24889 arm_frag_max_var (fragS
*fragp
)
24891 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24892 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24894 Note that we generate relaxable instructions even for cases that don't
24895 really need it, like an immediate that's a trivial constant. So we're
24896 overestimating the instruction size for some of those cases. Rather
24897 than putting more intelligence here, it would probably be better to
24898 avoid generating a relaxation frag in the first place when it can be
24899 determined up front that a short instruction will suffice. */
24901 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
24905 /* Estimate the size of a frag before relaxing. Assume everything fits in
24909 md_estimate_size_before_relax (fragS
* fragp
,
24910 segT segtype ATTRIBUTE_UNUSED
)
24916 /* Convert a machine dependent frag. */
24919 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
24921 unsigned long insn
;
24922 unsigned long old_op
;
24930 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24932 old_op
= bfd_get_16(abfd
, buf
);
24933 if (fragp
->fr_symbol
)
24935 exp
.X_op
= O_symbol
;
24936 exp
.X_add_symbol
= fragp
->fr_symbol
;
24940 exp
.X_op
= O_constant
;
24942 exp
.X_add_number
= fragp
->fr_offset
;
24943 opcode
= fragp
->fr_subtype
;
24946 case T_MNEM_ldr_pc
:
24947 case T_MNEM_ldr_pc2
:
24948 case T_MNEM_ldr_sp
:
24949 case T_MNEM_str_sp
:
24956 if (fragp
->fr_var
== 4)
24958 insn
= THUMB_OP32 (opcode
);
24959 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
24961 insn
|= (old_op
& 0x700) << 4;
24965 insn
|= (old_op
& 7) << 12;
24966 insn
|= (old_op
& 0x38) << 13;
24968 insn
|= 0x00000c00;
24969 put_thumb32_insn (buf
, insn
);
24970 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
24974 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
24976 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
24979 if (fragp
->fr_var
== 4)
24981 insn
= THUMB_OP32 (opcode
);
24982 insn
|= (old_op
& 0xf0) << 4;
24983 put_thumb32_insn (buf
, insn
);
24984 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
24988 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24989 exp
.X_add_number
-= 4;
24997 if (fragp
->fr_var
== 4)
24999 int r0off
= (opcode
== T_MNEM_mov
25000 || opcode
== T_MNEM_movs
) ? 0 : 8;
25001 insn
= THUMB_OP32 (opcode
);
25002 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25003 insn
|= (old_op
& 0x700) << r0off
;
25004 put_thumb32_insn (buf
, insn
);
25005 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25009 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25014 if (fragp
->fr_var
== 4)
25016 insn
= THUMB_OP32(opcode
);
25017 put_thumb32_insn (buf
, insn
);
25018 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25021 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25025 if (fragp
->fr_var
== 4)
25027 insn
= THUMB_OP32(opcode
);
25028 insn
|= (old_op
& 0xf00) << 14;
25029 put_thumb32_insn (buf
, insn
);
25030 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25033 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25036 case T_MNEM_add_sp
:
25037 case T_MNEM_add_pc
:
25038 case T_MNEM_inc_sp
:
25039 case T_MNEM_dec_sp
:
25040 if (fragp
->fr_var
== 4)
25042 /* ??? Choose between add and addw. */
25043 insn
= THUMB_OP32 (opcode
);
25044 insn
|= (old_op
& 0xf0) << 4;
25045 put_thumb32_insn (buf
, insn
);
25046 if (opcode
== T_MNEM_add_pc
)
25047 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25049 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25052 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25060 if (fragp
->fr_var
== 4)
25062 insn
= THUMB_OP32 (opcode
);
25063 insn
|= (old_op
& 0xf0) << 4;
25064 insn
|= (old_op
& 0xf) << 16;
25065 put_thumb32_insn (buf
, insn
);
25066 if (insn
& (1 << 20))
25067 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25069 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25072 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25078 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25079 (enum bfd_reloc_code_real
) reloc_type
);
25080 fixp
->fx_file
= fragp
->fr_file
;
25081 fixp
->fx_line
= fragp
->fr_line
;
25082 fragp
->fr_fix
+= fragp
->fr_var
;
25084 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25085 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25086 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25087 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25090 /* Return the size of a relaxable immediate operand instruction.
25091 SHIFT and SIZE specify the form of the allowable immediate. */
25093 relax_immediate (fragS
*fragp
, int size
, int shift
)
25099 /* ??? Should be able to do better than this. */
25100 if (fragp
->fr_symbol
)
25103 low
= (1 << shift
) - 1;
25104 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25105 offset
= fragp
->fr_offset
;
25106 /* Force misaligned offsets to 32-bit variant. */
25109 if (offset
& ~mask
)
25114 /* Get the address of a symbol during relaxation. */
25116 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25122 sym
= fragp
->fr_symbol
;
25123 sym_frag
= symbol_get_frag (sym
);
25124 know (S_GET_SEGMENT (sym
) != absolute_section
25125 || sym_frag
== &zero_address_frag
);
25126 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25128 /* If frag has yet to be reached on this pass, assume it will
25129 move by STRETCH just as we did. If this is not so, it will
25130 be because some frag between grows, and that will force
25134 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25138 /* Adjust stretch for any alignment frag. Note that if have
25139 been expanding the earlier code, the symbol may be
25140 defined in what appears to be an earlier frag. FIXME:
25141 This doesn't handle the fr_subtype field, which specifies
25142 a maximum number of bytes to skip when doing an
25144 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25146 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25149 stretch
= - ((- stretch
)
25150 & ~ ((1 << (int) f
->fr_offset
) - 1));
25152 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25164 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25167 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25172 /* Assume worst case for symbols not known to be in the same section. */
25173 if (fragp
->fr_symbol
== NULL
25174 || !S_IS_DEFINED (fragp
->fr_symbol
)
25175 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25176 || S_IS_WEAK (fragp
->fr_symbol
))
25179 val
= relaxed_symbol_addr (fragp
, stretch
);
25180 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25181 addr
= (addr
+ 4) & ~3;
25182 /* Force misaligned targets to 32-bit variant. */
25186 if (val
< 0 || val
> 1020)
25191 /* Return the size of a relaxable add/sub immediate instruction. */
25193 relax_addsub (fragS
*fragp
, asection
*sec
)
25198 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25199 op
= bfd_get_16(sec
->owner
, buf
);
25200 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25201 return relax_immediate (fragp
, 8, 0);
25203 return relax_immediate (fragp
, 3, 0);
25206 /* Return TRUE iff the definition of symbol S could be pre-empted
25207 (overridden) at link or load time. */
25209 symbol_preemptible (symbolS
*s
)
25211 /* Weak symbols can always be pre-empted. */
25215 /* Non-global symbols cannot be pre-empted. */
25216 if (! S_IS_EXTERNAL (s
))
25220 /* In ELF, a global symbol can be marked protected, or private. In that
25221 case it can't be pre-empted (other definitions in the same link unit
25222 would violate the ODR). */
25223 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25227 /* Other global symbols might be pre-empted. */
25231 /* Return the size of a relaxable branch instruction. BITS is the
25232 size of the offset field in the narrow instruction. */
25235 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25241 /* Assume worst case for symbols not known to be in the same section. */
25242 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25243 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25244 || S_IS_WEAK (fragp
->fr_symbol
))
25248 /* A branch to a function in ARM state will require interworking. */
25249 if (S_IS_DEFINED (fragp
->fr_symbol
)
25250 && ARM_IS_FUNC (fragp
->fr_symbol
))
25254 if (symbol_preemptible (fragp
->fr_symbol
))
25257 val
= relaxed_symbol_addr (fragp
, stretch
);
25258 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25261 /* Offset is a signed value *2 */
25263 if (val
>= limit
|| val
< -limit
)
25269 /* Relax a machine dependent frag. This returns the amount by which
25270 the current size of the frag should change. */
25273 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25278 oldsize
= fragp
->fr_var
;
25279 switch (fragp
->fr_subtype
)
25281 case T_MNEM_ldr_pc2
:
25282 newsize
= relax_adr (fragp
, sec
, stretch
);
25284 case T_MNEM_ldr_pc
:
25285 case T_MNEM_ldr_sp
:
25286 case T_MNEM_str_sp
:
25287 newsize
= relax_immediate (fragp
, 8, 2);
25291 newsize
= relax_immediate (fragp
, 5, 2);
25295 newsize
= relax_immediate (fragp
, 5, 1);
25299 newsize
= relax_immediate (fragp
, 5, 0);
25302 newsize
= relax_adr (fragp
, sec
, stretch
);
25308 newsize
= relax_immediate (fragp
, 8, 0);
25311 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25314 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25316 case T_MNEM_add_sp
:
25317 case T_MNEM_add_pc
:
25318 newsize
= relax_immediate (fragp
, 8, 2);
25320 case T_MNEM_inc_sp
:
25321 case T_MNEM_dec_sp
:
25322 newsize
= relax_immediate (fragp
, 7, 2);
25328 newsize
= relax_addsub (fragp
, sec
);
25334 fragp
->fr_var
= newsize
;
25335 /* Freeze wide instructions that are at or before the same location as
25336 in the previous pass. This avoids infinite loops.
25337 Don't freeze them unconditionally because targets may be artificially
25338 misaligned by the expansion of preceding frags. */
25339 if (stretch
<= 0 && newsize
> 2)
25341 md_convert_frag (sec
->owner
, sec
, fragp
);
25345 return newsize
- oldsize
;
25348 /* Round up a section size to the appropriate boundary. */
25351 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25357 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25358 of an rs_align_code fragment. */
25361 arm_handle_align (fragS
* fragP
)
25363 static unsigned char const arm_noop
[2][2][4] =
25366 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25367 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25370 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25371 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25374 static unsigned char const thumb_noop
[2][2][2] =
25377 {0xc0, 0x46}, /* LE */
25378 {0x46, 0xc0}, /* BE */
25381 {0x00, 0xbf}, /* LE */
25382 {0xbf, 0x00} /* BE */
25385 static unsigned char const wide_thumb_noop
[2][4] =
25386 { /* Wide Thumb-2 */
25387 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25388 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25391 unsigned bytes
, fix
, noop_size
;
25393 const unsigned char * noop
;
25394 const unsigned char *narrow_noop
= NULL
;
25399 if (fragP
->fr_type
!= rs_align_code
)
25402 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
25403 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
25406 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25407 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
25409 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
25411 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
25413 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25414 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
25416 narrow_noop
= thumb_noop
[1][target_big_endian
];
25417 noop
= wide_thumb_noop
[target_big_endian
];
25420 noop
= thumb_noop
[0][target_big_endian
];
25428 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
25429 ? selected_cpu
: arm_arch_none
,
25431 [target_big_endian
];
25438 fragP
->fr_var
= noop_size
;
25440 if (bytes
& (noop_size
- 1))
25442 fix
= bytes
& (noop_size
- 1);
25444 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
25446 memset (p
, 0, fix
);
25453 if (bytes
& noop_size
)
25455 /* Insert a narrow noop. */
25456 memcpy (p
, narrow_noop
, noop_size
);
25458 bytes
-= noop_size
;
25462 /* Use wide noops for the remainder */
25466 while (bytes
>= noop_size
)
25468 memcpy (p
, noop
, noop_size
);
25470 bytes
-= noop_size
;
25474 fragP
->fr_fix
+= fix
;
25477 /* Called from md_do_align. Used to create an alignment
25478 frag in a code section. */
25481 arm_frag_align_code (int n
, int max
)
25485 /* We assume that there will never be a requirement
25486 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
25487 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25492 _("alignments greater than %d bytes not supported in .text sections."),
25493 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
25494 as_fatal ("%s", err_msg
);
25497 p
= frag_var (rs_align_code
,
25498 MAX_MEM_FOR_RS_ALIGN_CODE
,
25500 (relax_substateT
) max
,
25507 /* Perform target specific initialisation of a frag.
25508 Note - despite the name this initialisation is not done when the frag
25509 is created, but only when its type is assigned. A frag can be created
25510 and used a long time before its type is set, so beware of assuming that
25511 this initialisation is performed first. */
25515 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
25517 /* Record whether this frag is in an ARM or a THUMB area. */
25518 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25521 #else /* OBJ_ELF is defined. */
25523 arm_init_frag (fragS
* fragP
, int max_chars
)
25525 bfd_boolean frag_thumb_mode
;
25527 /* If the current ARM vs THUMB mode has not already
25528 been recorded into this frag then do so now. */
25529 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
25530 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
25532 /* PR 21809: Do not set a mapping state for debug sections
25533 - it just confuses other tools. */
25534 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
25537 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
25539 /* Record a mapping symbol for alignment frags. We will delete this
25540 later if the alignment ends up empty. */
25541 switch (fragP
->fr_type
)
25544 case rs_align_test
:
25546 mapping_state_2 (MAP_DATA
, max_chars
);
25548 case rs_align_code
:
25549 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
25556 /* When we change sections we need to issue a new mapping symbol. */
25559 arm_elf_change_section (void)
25561 /* Link an unlinked unwind index table section to the .text section. */
25562 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
25563 && elf_linked_to_section (now_seg
) == NULL
)
25564 elf_linked_to_section (now_seg
) = text_section
;
25568 arm_elf_section_type (const char * str
, size_t len
)
25570 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
25571 return SHT_ARM_EXIDX
;
25576 /* Code to deal with unwinding tables. */
25578 static void add_unwind_adjustsp (offsetT
);
25580 /* Generate any deferred unwind frame offset. */
25583 flush_pending_unwind (void)
25587 offset
= unwind
.pending_offset
;
25588 unwind
.pending_offset
= 0;
25590 add_unwind_adjustsp (offset
);
25593 /* Add an opcode to this list for this function. Two-byte opcodes should
25594 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25598 add_unwind_opcode (valueT op
, int length
)
25600 /* Add any deferred stack adjustment. */
25601 if (unwind
.pending_offset
)
25602 flush_pending_unwind ();
25604 unwind
.sp_restored
= 0;
25606 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
25608 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
25609 if (unwind
.opcodes
)
25610 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
25611 unwind
.opcode_alloc
);
25613 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
25618 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
25620 unwind
.opcode_count
++;
25624 /* Add unwind opcodes to adjust the stack pointer. */
25627 add_unwind_adjustsp (offsetT offset
)
25631 if (offset
> 0x200)
25633 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
25638 /* Long form: 0xb2, uleb128. */
25639 /* This might not fit in a word so add the individual bytes,
25640 remembering the list is built in reverse order. */
25641 o
= (valueT
) ((offset
- 0x204) >> 2);
25643 add_unwind_opcode (0, 1);
25645 /* Calculate the uleb128 encoding of the offset. */
25649 bytes
[n
] = o
& 0x7f;
25655 /* Add the insn. */
25657 add_unwind_opcode (bytes
[n
- 1], 1);
25658 add_unwind_opcode (0xb2, 1);
25660 else if (offset
> 0x100)
25662 /* Two short opcodes. */
25663 add_unwind_opcode (0x3f, 1);
25664 op
= (offset
- 0x104) >> 2;
25665 add_unwind_opcode (op
, 1);
25667 else if (offset
> 0)
25669 /* Short opcode. */
25670 op
= (offset
- 4) >> 2;
25671 add_unwind_opcode (op
, 1);
25673 else if (offset
< 0)
25676 while (offset
> 0x100)
25678 add_unwind_opcode (0x7f, 1);
25681 op
= ((offset
- 4) >> 2) | 0x40;
25682 add_unwind_opcode (op
, 1);
25686 /* Finish the list of unwind opcodes for this function. */
25689 finish_unwind_opcodes (void)
25693 if (unwind
.fp_used
)
25695 /* Adjust sp as necessary. */
25696 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
25697 flush_pending_unwind ();
25699 /* After restoring sp from the frame pointer. */
25700 op
= 0x90 | unwind
.fp_reg
;
25701 add_unwind_opcode (op
, 1);
25704 flush_pending_unwind ();
25708 /* Start an exception table entry. If idx is nonzero this is an index table
25712 start_unwind_section (const segT text_seg
, int idx
)
25714 const char * text_name
;
25715 const char * prefix
;
25716 const char * prefix_once
;
25717 const char * group_name
;
25725 prefix
= ELF_STRING_ARM_unwind
;
25726 prefix_once
= ELF_STRING_ARM_unwind_once
;
25727 type
= SHT_ARM_EXIDX
;
25731 prefix
= ELF_STRING_ARM_unwind_info
;
25732 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
25733 type
= SHT_PROGBITS
;
25736 text_name
= segment_name (text_seg
);
25737 if (streq (text_name
, ".text"))
25740 if (strncmp (text_name
, ".gnu.linkonce.t.",
25741 strlen (".gnu.linkonce.t.")) == 0)
25743 prefix
= prefix_once
;
25744 text_name
+= strlen (".gnu.linkonce.t.");
25747 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
25753 /* Handle COMDAT group. */
25754 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
25756 group_name
= elf_group_name (text_seg
);
25757 if (group_name
== NULL
)
25759 as_bad (_("Group section `%s' has no group signature"),
25760 segment_name (text_seg
));
25761 ignore_rest_of_line ();
25764 flags
|= SHF_GROUP
;
25768 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
25771 /* Set the section link for index tables. */
25773 elf_linked_to_section (now_seg
) = text_seg
;
25777 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25778 personality routine data. Returns zero, or the index table value for
25779 an inline entry. */
25782 create_unwind_entry (int have_data
)
25787 /* The current word of data. */
25789 /* The number of bytes left in this word. */
25792 finish_unwind_opcodes ();
25794 /* Remember the current text section. */
25795 unwind
.saved_seg
= now_seg
;
25796 unwind
.saved_subseg
= now_subseg
;
25798 start_unwind_section (now_seg
, 0);
25800 if (unwind
.personality_routine
== NULL
)
25802 if (unwind
.personality_index
== -2)
25805 as_bad (_("handlerdata in cantunwind frame"));
25806 return 1; /* EXIDX_CANTUNWIND. */
25809 /* Use a default personality routine if none is specified. */
25810 if (unwind
.personality_index
== -1)
25812 if (unwind
.opcode_count
> 3)
25813 unwind
.personality_index
= 1;
25815 unwind
.personality_index
= 0;
25818 /* Space for the personality routine entry. */
25819 if (unwind
.personality_index
== 0)
25821 if (unwind
.opcode_count
> 3)
25822 as_bad (_("too many unwind opcodes for personality routine 0"));
25826 /* All the data is inline in the index table. */
25829 while (unwind
.opcode_count
> 0)
25831 unwind
.opcode_count
--;
25832 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25836 /* Pad with "finish" opcodes. */
25838 data
= (data
<< 8) | 0xb0;
25845 /* We get two opcodes "free" in the first word. */
25846 size
= unwind
.opcode_count
- 2;
25850 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25851 if (unwind
.personality_index
!= -1)
25853 as_bad (_("attempt to recreate an unwind entry"));
25857 /* An extra byte is required for the opcode count. */
25858 size
= unwind
.opcode_count
+ 1;
25861 size
= (size
+ 3) >> 2;
25863 as_bad (_("too many unwind opcodes"));
25865 frag_align (2, 0, 0);
25866 record_alignment (now_seg
, 2);
25867 unwind
.table_entry
= expr_build_dot ();
25869 /* Allocate the table entry. */
25870 ptr
= frag_more ((size
<< 2) + 4);
25871 /* PR 13449: Zero the table entries in case some of them are not used. */
25872 memset (ptr
, 0, (size
<< 2) + 4);
25873 where
= frag_now_fix () - ((size
<< 2) + 4);
25875 switch (unwind
.personality_index
)
25878 /* ??? Should this be a PLT generating relocation? */
25879 /* Custom personality routine. */
25880 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
25881 BFD_RELOC_ARM_PREL31
);
25886 /* Set the first byte to the number of additional words. */
25887 data
= size
> 0 ? size
- 1 : 0;
25891 /* ABI defined personality routines. */
25893 /* Three opcodes bytes are packed into the first word. */
25900 /* The size and first two opcode bytes go in the first word. */
25901 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
25906 /* Should never happen. */
25910 /* Pack the opcodes into words (MSB first), reversing the list at the same
25912 while (unwind
.opcode_count
> 0)
25916 md_number_to_chars (ptr
, data
, 4);
25921 unwind
.opcode_count
--;
25923 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25926 /* Finish off the last word. */
25929 /* Pad with "finish" opcodes. */
25931 data
= (data
<< 8) | 0xb0;
25933 md_number_to_chars (ptr
, data
, 4);
25938 /* Add an empty descriptor if there is no user-specified data. */
25939 ptr
= frag_more (4);
25940 md_number_to_chars (ptr
, 0, 4);
25947 /* Initialize the DWARF-2 unwind information for this procedure. */
25950 tc_arm_frame_initial_instructions (void)
25952 cfi_add_CFA_def_cfa (REG_SP
, 0);
25954 #endif /* OBJ_ELF */
25956 /* Convert REGNAME to a DWARF-2 register number. */
25959 tc_arm_regname_to_dw2regnum (char *regname
)
25961 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
25965 /* PR 16694: Allow VFP registers as well. */
25966 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
25970 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
25979 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
25983 exp
.X_op
= O_secrel
;
25984 exp
.X_add_symbol
= symbol
;
25985 exp
.X_add_number
= 0;
25986 emit_expr (&exp
, size
);
25990 /* MD interface: Symbol and relocation handling. */
25992 /* Return the address within the segment that a PC-relative fixup is
25993 relative to. For ARM, PC-relative fixups applied to instructions
25994 are generally relative to the location of the fixup plus 8 bytes.
25995 Thumb branches are offset by 4, and Thumb loads relative to PC
25996 require special handling. */
25999 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26001 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26003 /* If this is pc-relative and we are going to emit a relocation
26004 then we just want to put out any pipeline compensation that the linker
26005 will need. Otherwise we want to use the calculated base.
26006 For WinCE we skip the bias for externals as well, since this
26007 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26009 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26010 || (arm_force_relocation (fixP
)
26012 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26018 switch (fixP
->fx_r_type
)
26020 /* PC relative addressing on the Thumb is slightly odd as the
26021 bottom two bits of the PC are forced to zero for the
26022 calculation. This happens *after* application of the
26023 pipeline offset. However, Thumb adrl already adjusts for
26024 this, so we need not do it again. */
26025 case BFD_RELOC_ARM_THUMB_ADD
:
26028 case BFD_RELOC_ARM_THUMB_OFFSET
:
26029 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26030 case BFD_RELOC_ARM_T32_ADD_PC12
:
26031 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26032 return (base
+ 4) & ~3;
26034 /* Thumb branches are simply offset by +4. */
26035 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26036 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26037 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26038 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26039 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26040 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26041 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26042 case BFD_RELOC_ARM_THUMB_BF17
:
26043 case BFD_RELOC_ARM_THUMB_BF19
:
26044 case BFD_RELOC_ARM_THUMB_BF13
:
26045 case BFD_RELOC_ARM_THUMB_LOOP12
:
26048 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26050 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26051 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26052 && ARM_IS_FUNC (fixP
->fx_addsy
)
26053 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26054 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26057 /* BLX is like branches above, but forces the low two bits of PC to
26059 case BFD_RELOC_THUMB_PCREL_BLX
:
26061 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26062 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26063 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26064 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26065 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26066 return (base
+ 4) & ~3;
26068 /* ARM mode branches are offset by +8. However, the Windows CE
26069 loader expects the relocation not to take this into account. */
26070 case BFD_RELOC_ARM_PCREL_BLX
:
26072 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26073 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26074 && ARM_IS_FUNC (fixP
->fx_addsy
)
26075 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26076 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26079 case BFD_RELOC_ARM_PCREL_CALL
:
26081 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26082 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26083 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26084 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26085 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26088 case BFD_RELOC_ARM_PCREL_BRANCH
:
26089 case BFD_RELOC_ARM_PCREL_JUMP
:
26090 case BFD_RELOC_ARM_PLT32
:
26092 /* When handling fixups immediately, because we have already
26093 discovered the value of a symbol, or the address of the frag involved
26094 we must account for the offset by +8, as the OS loader will never see the reloc.
26095 see fixup_segment() in write.c
26096 The S_IS_EXTERNAL test handles the case of global symbols.
26097 Those need the calculated base, not just the pipe compensation the linker will need. */
26099 && fixP
->fx_addsy
!= NULL
26100 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26101 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26109 /* ARM mode loads relative to PC are also offset by +8. Unlike
26110 branches, the Windows CE loader *does* expect the relocation
26111 to take this into account. */
26112 case BFD_RELOC_ARM_OFFSET_IMM
:
26113 case BFD_RELOC_ARM_OFFSET_IMM8
:
26114 case BFD_RELOC_ARM_HWLITERAL
:
26115 case BFD_RELOC_ARM_LITERAL
:
26116 case BFD_RELOC_ARM_CP_OFF_IMM
:
26120 /* Other PC-relative relocations are un-offset. */
26126 static bfd_boolean flag_warn_syms
= TRUE
;
26129 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26131 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26132 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26133 does mean that the resulting code might be very confusing to the reader.
26134 Also this warning can be triggered if the user omits an operand before
26135 an immediate address, eg:
26139 GAS treats this as an assignment of the value of the symbol foo to a
26140 symbol LDR, and so (without this code) it will not issue any kind of
26141 warning or error message.
26143 Note - ARM instructions are case-insensitive but the strings in the hash
26144 table are all stored in lower case, so we must first ensure that name is
26146 if (flag_warn_syms
&& arm_ops_hsh
)
26148 char * nbuf
= strdup (name
);
26151 for (p
= nbuf
; *p
; p
++)
26153 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26155 static struct hash_control
* already_warned
= NULL
;
26157 if (already_warned
== NULL
)
26158 already_warned
= hash_new ();
26159 /* Only warn about the symbol once. To keep the code
26160 simple we let hash_insert do the lookup for us. */
26161 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26162 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26171 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26172 Otherwise we have no need to default values of symbols. */
26175 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26178 if (name
[0] == '_' && name
[1] == 'G'
26179 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26183 if (symbol_find (name
))
26184 as_bad (_("GOT already in the symbol table"));
26186 GOT_symbol
= symbol_new (name
, undefined_section
,
26187 (valueT
) 0, & zero_address_frag
);
26197 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26198 computed as two separate immediate values, added together. We
26199 already know that this value cannot be computed by just one ARM
26202 static unsigned int
26203 validate_immediate_twopart (unsigned int val
,
26204 unsigned int * highpart
)
26209 for (i
= 0; i
< 32; i
+= 2)
26210 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26216 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26218 else if (a
& 0xff0000)
26220 if (a
& 0xff000000)
26222 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26226 gas_assert (a
& 0xff000000);
26227 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26230 return (a
& 0xff) | (i
<< 7);
26237 validate_offset_imm (unsigned int val
, int hwse
)
26239 if ((hwse
&& val
> 255) || val
> 4095)
26244 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26245 negative immediate constant by altering the instruction. A bit of
26250 by inverting the second operand, and
26253 by negating the second operand. */
26256 negate_data_op (unsigned long * instruction
,
26257 unsigned long value
)
26260 unsigned long negated
, inverted
;
26262 negated
= encode_arm_immediate (-value
);
26263 inverted
= encode_arm_immediate (~value
);
26265 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26268 /* First negates. */
26269 case OPCODE_SUB
: /* ADD <-> SUB */
26270 new_inst
= OPCODE_ADD
;
26275 new_inst
= OPCODE_SUB
;
26279 case OPCODE_CMP
: /* CMP <-> CMN */
26280 new_inst
= OPCODE_CMN
;
26285 new_inst
= OPCODE_CMP
;
26289 /* Now Inverted ops. */
26290 case OPCODE_MOV
: /* MOV <-> MVN */
26291 new_inst
= OPCODE_MVN
;
26296 new_inst
= OPCODE_MOV
;
26300 case OPCODE_AND
: /* AND <-> BIC */
26301 new_inst
= OPCODE_BIC
;
26306 new_inst
= OPCODE_AND
;
26310 case OPCODE_ADC
: /* ADC <-> SBC */
26311 new_inst
= OPCODE_SBC
;
26316 new_inst
= OPCODE_ADC
;
26320 /* We cannot do anything. */
26325 if (value
== (unsigned) FAIL
)
26328 *instruction
&= OPCODE_MASK
;
26329 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26333 /* Like negate_data_op, but for Thumb-2. */
26335 static unsigned int
26336 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26340 unsigned int negated
, inverted
;
26342 negated
= encode_thumb32_immediate (-value
);
26343 inverted
= encode_thumb32_immediate (~value
);
26345 rd
= (*instruction
>> 8) & 0xf;
26346 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26349 /* ADD <-> SUB. Includes CMP <-> CMN. */
26350 case T2_OPCODE_SUB
:
26351 new_inst
= T2_OPCODE_ADD
;
26355 case T2_OPCODE_ADD
:
26356 new_inst
= T2_OPCODE_SUB
;
26360 /* ORR <-> ORN. Includes MOV <-> MVN. */
26361 case T2_OPCODE_ORR
:
26362 new_inst
= T2_OPCODE_ORN
;
26366 case T2_OPCODE_ORN
:
26367 new_inst
= T2_OPCODE_ORR
;
26371 /* AND <-> BIC. TST has no inverted equivalent. */
26372 case T2_OPCODE_AND
:
26373 new_inst
= T2_OPCODE_BIC
;
26380 case T2_OPCODE_BIC
:
26381 new_inst
= T2_OPCODE_AND
;
26386 case T2_OPCODE_ADC
:
26387 new_inst
= T2_OPCODE_SBC
;
26391 case T2_OPCODE_SBC
:
26392 new_inst
= T2_OPCODE_ADC
;
26396 /* We cannot do anything. */
26401 if (value
== (unsigned int)FAIL
)
26404 *instruction
&= T2_OPCODE_MASK
;
26405 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
26409 /* Read a 32-bit thumb instruction from buf. */
26411 static unsigned long
26412 get_thumb32_insn (char * buf
)
26414 unsigned long insn
;
26415 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
26416 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26421 /* We usually want to set the low bit on the address of thumb function
26422 symbols. In particular .word foo - . should have the low bit set.
26423 Generic code tries to fold the difference of two symbols to
26424 a constant. Prevent this and force a relocation when the first symbols
26425 is a thumb function. */
26428 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
26430 if (op
== O_subtract
26431 && l
->X_op
== O_symbol
26432 && r
->X_op
== O_symbol
26433 && THUMB_IS_FUNC (l
->X_add_symbol
))
26435 l
->X_op
= O_subtract
;
26436 l
->X_op_symbol
= r
->X_add_symbol
;
26437 l
->X_add_number
-= r
->X_add_number
;
26441 /* Process as normal. */
26445 /* Encode Thumb2 unconditional branches and calls. The encoding
26446 for the 2 are identical for the immediate values. */
26449 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
26451 #define T2I1I2MASK ((1 << 13) | (1 << 11))
26454 addressT S
, I1
, I2
, lo
, hi
;
26456 S
= (value
>> 24) & 0x01;
26457 I1
= (value
>> 23) & 0x01;
26458 I2
= (value
>> 22) & 0x01;
26459 hi
= (value
>> 12) & 0x3ff;
26460 lo
= (value
>> 1) & 0x7ff;
26461 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26462 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26463 newval
|= (S
<< 10) | hi
;
26464 newval2
&= ~T2I1I2MASK
;
26465 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
26466 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26467 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26471 md_apply_fix (fixS
* fixP
,
26475 offsetT value
= * valP
;
26477 unsigned int newimm
;
26478 unsigned long temp
;
26480 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
26482 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
26484 /* Note whether this will delete the relocation. */
26486 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
26489 /* On a 64-bit host, silently truncate 'value' to 32 bits for
26490 consistency with the behaviour on 32-bit hosts. Remember value
26492 value
&= 0xffffffff;
26493 value
^= 0x80000000;
26494 value
-= 0x80000000;
26497 fixP
->fx_addnumber
= value
;
26499 /* Same treatment for fixP->fx_offset. */
26500 fixP
->fx_offset
&= 0xffffffff;
26501 fixP
->fx_offset
^= 0x80000000;
26502 fixP
->fx_offset
-= 0x80000000;
26504 switch (fixP
->fx_r_type
)
26506 case BFD_RELOC_NONE
:
26507 /* This will need to go in the object file. */
26511 case BFD_RELOC_ARM_IMMEDIATE
:
26512 /* We claim that this fixup has been processed here,
26513 even if in fact we generate an error because we do
26514 not have a reloc for it, so tc_gen_reloc will reject it. */
26517 if (fixP
->fx_addsy
)
26519 const char *msg
= 0;
26521 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26522 msg
= _("undefined symbol %s used as an immediate value");
26523 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26524 msg
= _("symbol %s is in a different section");
26525 else if (S_IS_WEAK (fixP
->fx_addsy
))
26526 msg
= _("symbol %s is weak and may be overridden later");
26530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26531 msg
, S_GET_NAME (fixP
->fx_addsy
));
26536 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26538 /* If the offset is negative, we should use encoding A2 for ADR. */
26539 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
26540 newimm
= negate_data_op (&temp
, value
);
26543 newimm
= encode_arm_immediate (value
);
26545 /* If the instruction will fail, see if we can fix things up by
26546 changing the opcode. */
26547 if (newimm
== (unsigned int) FAIL
)
26548 newimm
= negate_data_op (&temp
, value
);
26549 /* MOV accepts both ARM modified immediate (A1 encoding) and
26550 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
26551 When disassembling, MOV is preferred when there is no encoding
26553 if (newimm
== (unsigned int) FAIL
26554 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
26555 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
26556 && !((temp
>> SBIT_SHIFT
) & 0x1)
26557 && value
>= 0 && value
<= 0xffff)
26559 /* Clear bits[23:20] to change encoding from A1 to A2. */
26560 temp
&= 0xff0fffff;
26561 /* Encoding high 4bits imm. Code below will encode the remaining
26563 temp
|= (value
& 0x0000f000) << 4;
26564 newimm
= value
& 0x00000fff;
26568 if (newimm
== (unsigned int) FAIL
)
26570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26571 _("invalid constant (%lx) after fixup"),
26572 (unsigned long) value
);
26576 newimm
|= (temp
& 0xfffff000);
26577 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26580 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
26582 unsigned int highpart
= 0;
26583 unsigned int newinsn
= 0xe1a00000; /* nop. */
26585 if (fixP
->fx_addsy
)
26587 const char *msg
= 0;
26589 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26590 msg
= _("undefined symbol %s used as an immediate value");
26591 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26592 msg
= _("symbol %s is in a different section");
26593 else if (S_IS_WEAK (fixP
->fx_addsy
))
26594 msg
= _("symbol %s is weak and may be overridden later");
26598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26599 msg
, S_GET_NAME (fixP
->fx_addsy
));
26604 newimm
= encode_arm_immediate (value
);
26605 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26607 /* If the instruction will fail, see if we can fix things up by
26608 changing the opcode. */
26609 if (newimm
== (unsigned int) FAIL
26610 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
26612 /* No ? OK - try using two ADD instructions to generate
26614 newimm
= validate_immediate_twopart (value
, & highpart
);
26616 /* Yes - then make sure that the second instruction is
26618 if (newimm
!= (unsigned int) FAIL
)
26620 /* Still No ? Try using a negated value. */
26621 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
26622 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
26623 /* Otherwise - give up. */
26626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26627 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
26632 /* Replace the first operand in the 2nd instruction (which
26633 is the PC) with the destination register. We have
26634 already added in the PC in the first instruction and we
26635 do not want to do it again. */
26636 newinsn
&= ~ 0xf0000;
26637 newinsn
|= ((newinsn
& 0x0f000) << 4);
26640 newimm
|= (temp
& 0xfffff000);
26641 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26643 highpart
|= (newinsn
& 0xfffff000);
26644 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
26648 case BFD_RELOC_ARM_OFFSET_IMM
:
26649 if (!fixP
->fx_done
&& seg
->use_rela_p
)
26651 /* Fall through. */
26653 case BFD_RELOC_ARM_LITERAL
:
26659 if (validate_offset_imm (value
, 0) == FAIL
)
26661 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
26662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26663 _("invalid literal constant: pool needs to be closer"));
26665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26666 _("bad immediate value for offset (%ld)"),
26671 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26673 newval
&= 0xfffff000;
26676 newval
&= 0xff7ff000;
26677 newval
|= value
| (sign
? INDEX_UP
: 0);
26679 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26682 case BFD_RELOC_ARM_OFFSET_IMM8
:
26683 case BFD_RELOC_ARM_HWLITERAL
:
26689 if (validate_offset_imm (value
, 1) == FAIL
)
26691 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
26692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26693 _("invalid literal constant: pool needs to be closer"));
26695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26696 _("bad immediate value for 8-bit offset (%ld)"),
26701 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26703 newval
&= 0xfffff0f0;
26706 newval
&= 0xff7ff0f0;
26707 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
26709 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26712 case BFD_RELOC_ARM_T32_OFFSET_U8
:
26713 if (value
< 0 || value
> 1020 || value
% 4 != 0)
26714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26715 _("bad immediate value for offset (%ld)"), (long) value
);
26718 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
26720 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
26723 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26724 /* This is a complicated relocation used for all varieties of Thumb32
26725 load/store instruction with immediate offset:
26727 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26728 *4, optional writeback(W)
26729 (doubleword load/store)
26731 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26732 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26733 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26734 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26735 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26737 Uppercase letters indicate bits that are already encoded at
26738 this point. Lowercase letters are our problem. For the
26739 second block of instructions, the secondary opcode nybble
26740 (bits 8..11) is present, and bit 23 is zero, even if this is
26741 a PC-relative operation. */
26742 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26744 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
26746 if ((newval
& 0xf0000000) == 0xe0000000)
26748 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26750 newval
|= (1 << 23);
26753 if (value
% 4 != 0)
26755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26756 _("offset not a multiple of 4"));
26762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26763 _("offset out of range"));
26768 else if ((newval
& 0x000f0000) == 0x000f0000)
26770 /* PC-relative, 12-bit offset. */
26772 newval
|= (1 << 23);
26777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26778 _("offset out of range"));
26783 else if ((newval
& 0x00000100) == 0x00000100)
26785 /* Writeback: 8-bit, +/- offset. */
26787 newval
|= (1 << 9);
26792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26793 _("offset out of range"));
26798 else if ((newval
& 0x00000f00) == 0x00000e00)
26800 /* T-instruction: positive 8-bit offset. */
26801 if (value
< 0 || value
> 0xff)
26803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26804 _("offset out of range"));
26812 /* Positive 12-bit or negative 8-bit offset. */
26816 newval
|= (1 << 23);
26826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26827 _("offset out of range"));
26834 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
26835 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
26838 case BFD_RELOC_ARM_SHIFT_IMM
:
26839 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26840 if (((unsigned long) value
) > 32
26842 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
26844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26845 _("shift expression is too large"));
26850 /* Shifts of zero must be done as lsl. */
26852 else if (value
== 32)
26854 newval
&= 0xfffff07f;
26855 newval
|= (value
& 0x1f) << 7;
26856 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26859 case BFD_RELOC_ARM_T32_IMMEDIATE
:
26860 case BFD_RELOC_ARM_T32_ADD_IMM
:
26861 case BFD_RELOC_ARM_T32_IMM12
:
26862 case BFD_RELOC_ARM_T32_ADD_PC12
:
26863 /* We claim that this fixup has been processed here,
26864 even if in fact we generate an error because we do
26865 not have a reloc for it, so tc_gen_reloc will reject it. */
26869 && ! S_IS_DEFINED (fixP
->fx_addsy
))
26871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26872 _("undefined symbol %s used as an immediate value"),
26873 S_GET_NAME (fixP
->fx_addsy
));
26877 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26879 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
26882 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26883 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26884 Thumb2 modified immediate encoding (T2). */
26885 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
26886 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26888 newimm
= encode_thumb32_immediate (value
);
26889 if (newimm
== (unsigned int) FAIL
)
26890 newimm
= thumb32_negate_data_op (&newval
, value
);
26892 if (newimm
== (unsigned int) FAIL
)
26894 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
26896 /* Turn add/sum into addw/subw. */
26897 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26898 newval
= (newval
& 0xfeffffff) | 0x02000000;
26899 /* No flat 12-bit imm encoding for addsw/subsw. */
26900 if ((newval
& 0x00100000) == 0)
26902 /* 12 bit immediate for addw/subw. */
26906 newval
^= 0x00a00000;
26909 newimm
= (unsigned int) FAIL
;
26916 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26917 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26918 disassembling, MOV is preferred when there is no encoding
26920 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
26921 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26922 but with the Rn field [19:16] set to 1111. */
26923 && (((newval
>> 16) & 0xf) == 0xf)
26924 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
26925 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
26926 && value
>= 0 && value
<= 0xffff)
26928 /* Toggle bit[25] to change encoding from T2 to T3. */
26930 /* Clear bits[19:16]. */
26931 newval
&= 0xfff0ffff;
26932 /* Encoding high 4bits imm. Code below will encode the
26933 remaining low 12bits. */
26934 newval
|= (value
& 0x0000f000) << 4;
26935 newimm
= value
& 0x00000fff;
26940 if (newimm
== (unsigned int)FAIL
)
26942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26943 _("invalid constant (%lx) after fixup"),
26944 (unsigned long) value
);
26948 newval
|= (newimm
& 0x800) << 15;
26949 newval
|= (newimm
& 0x700) << 4;
26950 newval
|= (newimm
& 0x0ff);
26952 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
26953 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
26956 case BFD_RELOC_ARM_SMC
:
26957 if (((unsigned long) value
) > 0xffff)
26958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26959 _("invalid smc expression"));
26960 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26961 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26962 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26965 case BFD_RELOC_ARM_HVC
:
26966 if (((unsigned long) value
) > 0xffff)
26967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26968 _("invalid hvc expression"));
26969 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26970 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26971 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26974 case BFD_RELOC_ARM_SWI
:
26975 if (fixP
->tc_fix_data
!= 0)
26977 if (((unsigned long) value
) > 0xff)
26978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26979 _("invalid swi expression"));
26980 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26982 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26986 if (((unsigned long) value
) > 0x00ffffff)
26987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26988 _("invalid swi expression"));
26989 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26991 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26995 case BFD_RELOC_ARM_MULTI
:
26996 if (((unsigned long) value
) > 0xffff)
26997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26998 _("invalid expression in load/store multiple"));
26999 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27000 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27004 case BFD_RELOC_ARM_PCREL_CALL
:
27006 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27008 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27009 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27010 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27011 /* Flip the bl to blx. This is a simple flip
27012 bit here because we generate PCREL_CALL for
27013 unconditional bls. */
27015 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27016 newval
= newval
| 0x10000000;
27017 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27023 goto arm_branch_common
;
27025 case BFD_RELOC_ARM_PCREL_JUMP
:
27026 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27028 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27029 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27030 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27032 /* This would map to a bl<cond>, b<cond>,
27033 b<always> to a Thumb function. We
27034 need to force a relocation for this particular
27036 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27039 /* Fall through. */
27041 case BFD_RELOC_ARM_PLT32
:
27043 case BFD_RELOC_ARM_PCREL_BRANCH
:
27045 goto arm_branch_common
;
27047 case BFD_RELOC_ARM_PCREL_BLX
:
27050 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27052 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27053 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27054 && ARM_IS_FUNC (fixP
->fx_addsy
))
27056 /* Flip the blx to a bl and warn. */
27057 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27058 newval
= 0xeb000000;
27059 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27060 _("blx to '%s' an ARM ISA state function changed to bl"),
27062 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27068 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27069 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27073 /* We are going to store value (shifted right by two) in the
27074 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27075 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27079 _("misaligned branch destination"));
27080 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27081 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27084 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27086 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27087 newval
|= (value
>> 2) & 0x00ffffff;
27088 /* Set the H bit on BLX instructions. */
27092 newval
|= 0x01000000;
27094 newval
&= ~0x01000000;
27096 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27100 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27101 /* CBZ can only branch forward. */
27103 /* Attempts to use CBZ to branch to the next instruction
27104 (which, strictly speaking, are prohibited) will be turned into
27107 FIXME: It may be better to remove the instruction completely and
27108 perform relaxation. */
27111 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27112 newval
= 0xbf00; /* NOP encoding T1 */
27113 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27120 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27122 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27123 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27124 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27129 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27130 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27133 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27135 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27136 newval
|= (value
& 0x1ff) >> 1;
27137 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27141 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27142 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27147 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27148 newval
|= (value
& 0xfff) >> 1;
27149 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27153 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27155 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27156 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27157 && ARM_IS_FUNC (fixP
->fx_addsy
)
27158 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27160 /* Force a relocation for a branch 20 bits wide. */
27163 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27165 _("conditional branch out of range"));
27167 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27170 addressT S
, J1
, J2
, lo
, hi
;
27172 S
= (value
& 0x00100000) >> 20;
27173 J2
= (value
& 0x00080000) >> 19;
27174 J1
= (value
& 0x00040000) >> 18;
27175 hi
= (value
& 0x0003f000) >> 12;
27176 lo
= (value
& 0x00000ffe) >> 1;
27178 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27179 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27180 newval
|= (S
<< 10) | hi
;
27181 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27182 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27183 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27187 case BFD_RELOC_THUMB_PCREL_BLX
:
27188 /* If there is a blx from a thumb state function to
27189 another thumb function flip this to a bl and warn
27193 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27194 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27195 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27197 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27198 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27199 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27201 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27202 newval
= newval
| 0x1000;
27203 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27204 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27209 goto thumb_bl_common
;
27211 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27212 /* A bl from Thumb state ISA to an internal ARM state function
27213 is converted to a blx. */
27215 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27216 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27217 && ARM_IS_FUNC (fixP
->fx_addsy
)
27218 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27220 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27221 newval
= newval
& ~0x1000;
27222 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27223 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27229 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27230 /* For a BLX instruction, make sure that the relocation is rounded up
27231 to a word boundary. This follows the semantics of the instruction
27232 which specifies that bit 1 of the target address will come from bit
27233 1 of the base address. */
27234 value
= (value
+ 3) & ~ 3;
27237 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27238 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27239 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27242 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27244 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27246 else if ((value
& ~0x1ffffff)
27247 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27249 _("Thumb2 branch out of range"));
27252 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27253 encode_thumb2_b_bl_offset (buf
, value
);
27257 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27258 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27261 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27262 encode_thumb2_b_bl_offset (buf
, value
);
27267 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27272 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27273 md_number_to_chars (buf
, value
, 2);
27277 case BFD_RELOC_ARM_TLS_CALL
:
27278 case BFD_RELOC_ARM_THM_TLS_CALL
:
27279 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27280 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27281 case BFD_RELOC_ARM_TLS_GOTDESC
:
27282 case BFD_RELOC_ARM_TLS_GD32
:
27283 case BFD_RELOC_ARM_TLS_LE32
:
27284 case BFD_RELOC_ARM_TLS_IE32
:
27285 case BFD_RELOC_ARM_TLS_LDM32
:
27286 case BFD_RELOC_ARM_TLS_LDO32
:
27287 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27290 /* Same handling as above, but with the arm_fdpic guard. */
27291 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27292 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27293 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27296 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27300 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27301 _("Relocation supported only in FDPIC mode"));
27305 case BFD_RELOC_ARM_GOT32
:
27306 case BFD_RELOC_ARM_GOTOFF
:
27309 case BFD_RELOC_ARM_GOT_PREL
:
27310 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27311 md_number_to_chars (buf
, value
, 4);
27314 case BFD_RELOC_ARM_TARGET2
:
27315 /* TARGET2 is not partial-inplace, so we need to write the
27316 addend here for REL targets, because it won't be written out
27317 during reloc processing later. */
27318 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27319 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27322 /* Relocations for FDPIC. */
27323 case BFD_RELOC_ARM_GOTFUNCDESC
:
27324 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27325 case BFD_RELOC_ARM_FUNCDESC
:
27328 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27329 md_number_to_chars (buf
, 0, 4);
27333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27334 _("Relocation supported only in FDPIC mode"));
27339 case BFD_RELOC_RVA
:
27341 case BFD_RELOC_ARM_TARGET1
:
27342 case BFD_RELOC_ARM_ROSEGREL32
:
27343 case BFD_RELOC_ARM_SBREL32
:
27344 case BFD_RELOC_32_PCREL
:
27346 case BFD_RELOC_32_SECREL
:
27348 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27350 /* For WinCE we only do this for pcrel fixups. */
27351 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27353 md_number_to_chars (buf
, value
, 4);
27357 case BFD_RELOC_ARM_PREL31
:
27358 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27360 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27361 if ((value
^ (value
>> 1)) & 0x40000000)
27363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27364 _("rel31 relocation overflow"));
27366 newval
|= value
& 0x7fffffff;
27367 md_number_to_chars (buf
, newval
, 4);
27372 case BFD_RELOC_ARM_CP_OFF_IMM
:
27373 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27374 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27375 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27376 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27378 newval
= get_thumb32_insn (buf
);
27379 if ((newval
& 0x0f200f00) == 0x0d000900)
27381 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27382 has permitted values that are multiples of 2, in the range 0
27384 if (value
< -510 || value
> 510 || (value
& 1))
27385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27386 _("co-processor offset out of range"));
27388 else if ((newval
& 0xfe001f80) == 0xec000f80)
27390 if (value
< -511 || value
> 512 || (value
& 3))
27391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27392 _("co-processor offset out of range"));
27394 else if (value
< -1023 || value
> 1023 || (value
& 3))
27395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27396 _("co-processor offset out of range"));
27401 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27402 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27403 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27405 newval
= get_thumb32_insn (buf
);
27408 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27409 newval
&= 0xffffff80;
27411 newval
&= 0xffffff00;
27415 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
27416 newval
&= 0xff7fff80;
27418 newval
&= 0xff7fff00;
27419 if ((newval
& 0x0f200f00) == 0x0d000900)
27421 /* This is a fp16 vstr/vldr.
27423 It requires the immediate offset in the instruction is shifted
27424 left by 1 to be a half-word offset.
27426 Here, left shift by 1 first, and later right shift by 2
27427 should get the right offset. */
27430 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
27432 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27433 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27434 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27436 put_thumb32_insn (buf
, newval
);
27439 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
27440 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
27441 if (value
< -255 || value
> 255)
27442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27443 _("co-processor offset out of range"));
27445 goto cp_off_common
;
27447 case BFD_RELOC_ARM_THUMB_OFFSET
:
27448 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27449 /* Exactly what ranges, and where the offset is inserted depends
27450 on the type of instruction, we can establish this from the
27452 switch (newval
>> 12)
27454 case 4: /* PC load. */
27455 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
27456 forced to zero for these loads; md_pcrel_from has already
27457 compensated for this. */
27459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27460 _("invalid offset, target not word aligned (0x%08lX)"),
27461 (((unsigned long) fixP
->fx_frag
->fr_address
27462 + (unsigned long) fixP
->fx_where
) & ~3)
27463 + (unsigned long) value
);
27465 if (value
& ~0x3fc)
27466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27467 _("invalid offset, value too big (0x%08lX)"),
27470 newval
|= value
>> 2;
27473 case 9: /* SP load/store. */
27474 if (value
& ~0x3fc)
27475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27476 _("invalid offset, value too big (0x%08lX)"),
27478 newval
|= value
>> 2;
27481 case 6: /* Word load/store. */
27483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27484 _("invalid offset, value too big (0x%08lX)"),
27486 newval
|= value
<< 4; /* 6 - 2. */
27489 case 7: /* Byte load/store. */
27491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27492 _("invalid offset, value too big (0x%08lX)"),
27494 newval
|= value
<< 6;
27497 case 8: /* Halfword load/store. */
27499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27500 _("invalid offset, value too big (0x%08lX)"),
27502 newval
|= value
<< 5; /* 6 - 1. */
27506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27507 "Unable to process relocation for thumb opcode: %lx",
27508 (unsigned long) newval
);
27511 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27514 case BFD_RELOC_ARM_THUMB_ADD
:
27515 /* This is a complicated relocation, since we use it for all of
27516 the following immediate relocations:
27520 9bit ADD/SUB SP word-aligned
27521 10bit ADD PC/SP word-aligned
27523 The type of instruction being processed is encoded in the
27530 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27532 int rd
= (newval
>> 4) & 0xf;
27533 int rs
= newval
& 0xf;
27534 int subtract
= !!(newval
& 0x8000);
27536 /* Check for HI regs, only very restricted cases allowed:
27537 Adjusting SP, and using PC or SP to get an address. */
27538 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
27539 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
27540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27541 _("invalid Hi register with immediate"));
27543 /* If value is negative, choose the opposite instruction. */
27547 subtract
= !subtract
;
27549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27550 _("immediate value out of range"));
27555 if (value
& ~0x1fc)
27556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27557 _("invalid immediate for stack address calculation"));
27558 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
27559 newval
|= value
>> 2;
27561 else if (rs
== REG_PC
|| rs
== REG_SP
)
27563 /* PR gas/18541. If the addition is for a defined symbol
27564 within range of an ADR instruction then accept it. */
27567 && fixP
->fx_addsy
!= NULL
)
27571 if (! S_IS_DEFINED (fixP
->fx_addsy
)
27572 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
27573 || S_IS_WEAK (fixP
->fx_addsy
))
27575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27576 _("address calculation needs a strongly defined nearby symbol"));
27580 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27582 /* Round up to the next 4-byte boundary. */
27587 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
27591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27592 _("symbol too far away"));
27602 if (subtract
|| value
& ~0x3fc)
27603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27604 _("invalid immediate for address calculation (value = 0x%08lX)"),
27605 (unsigned long) (subtract
? - value
: value
));
27606 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
27608 newval
|= value
>> 2;
27613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27614 _("immediate value out of range"));
27615 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
27616 newval
|= (rd
<< 8) | value
;
27621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27622 _("immediate value out of range"));
27623 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
27624 newval
|= rd
| (rs
<< 3) | (value
<< 6);
27627 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27630 case BFD_RELOC_ARM_THUMB_IMM
:
27631 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27632 if (value
< 0 || value
> 255)
27633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27634 _("invalid immediate: %ld is out of range"),
27637 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27640 case BFD_RELOC_ARM_THUMB_SHIFT
:
27641 /* 5bit shift value (0..32). LSL cannot take 32. */
27642 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
27643 temp
= newval
& 0xf800;
27644 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
27645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27646 _("invalid shift value: %ld"), (long) value
);
27647 /* Shifts of zero must be encoded as LSL. */
27649 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
27650 /* Shifts of 32 are encoded as zero. */
27651 else if (value
== 32)
27653 newval
|= value
<< 6;
27654 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27657 case BFD_RELOC_VTABLE_INHERIT
:
27658 case BFD_RELOC_VTABLE_ENTRY
:
27662 case BFD_RELOC_ARM_MOVW
:
27663 case BFD_RELOC_ARM_MOVT
:
27664 case BFD_RELOC_ARM_THUMB_MOVW
:
27665 case BFD_RELOC_ARM_THUMB_MOVT
:
27666 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27668 /* REL format relocations are limited to a 16-bit addend. */
27669 if (!fixP
->fx_done
)
27671 if (value
< -0x8000 || value
> 0x7fff)
27672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27673 _("offset out of range"));
27675 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27676 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27681 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27682 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27684 newval
= get_thumb32_insn (buf
);
27685 newval
&= 0xfbf08f00;
27686 newval
|= (value
& 0xf000) << 4;
27687 newval
|= (value
& 0x0800) << 15;
27688 newval
|= (value
& 0x0700) << 4;
27689 newval
|= (value
& 0x00ff);
27690 put_thumb32_insn (buf
, newval
);
27694 newval
= md_chars_to_number (buf
, 4);
27695 newval
&= 0xfff0f000;
27696 newval
|= value
& 0x0fff;
27697 newval
|= (value
& 0xf000) << 4;
27698 md_number_to_chars (buf
, newval
, 4);
27703 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27704 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27705 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27706 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27707 gas_assert (!fixP
->fx_done
);
27710 bfd_boolean is_mov
;
27711 bfd_vma encoded_addend
= value
;
27713 /* Check that addend can be encoded in instruction. */
27714 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
27715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27716 _("the offset 0x%08lX is not representable"),
27717 (unsigned long) encoded_addend
);
27719 /* Extract the instruction. */
27720 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
27721 is_mov
= (insn
& 0xf800) == 0x2000;
27726 if (!seg
->use_rela_p
)
27727 insn
|= encoded_addend
;
27733 /* Extract the instruction. */
27734 /* Encoding is the following
27739 /* The following conditions must be true :
27744 rd
= (insn
>> 4) & 0xf;
27746 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
27747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27748 _("Unable to process relocation for thumb opcode: %lx"),
27749 (unsigned long) insn
);
27751 /* Encode as ADD immediate8 thumb 1 code. */
27752 insn
= 0x3000 | (rd
<< 8);
27754 /* Place the encoded addend into the first 8 bits of the
27756 if (!seg
->use_rela_p
)
27757 insn
|= encoded_addend
;
27760 /* Update the instruction. */
27761 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
27765 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27766 case BFD_RELOC_ARM_ALU_PC_G0
:
27767 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27768 case BFD_RELOC_ARM_ALU_PC_G1
:
27769 case BFD_RELOC_ARM_ALU_PC_G2
:
27770 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27771 case BFD_RELOC_ARM_ALU_SB_G0
:
27772 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27773 case BFD_RELOC_ARM_ALU_SB_G1
:
27774 case BFD_RELOC_ARM_ALU_SB_G2
:
27775 gas_assert (!fixP
->fx_done
);
27776 if (!seg
->use_rela_p
)
27779 bfd_vma encoded_addend
;
27780 bfd_vma addend_abs
= llabs (value
);
27782 /* Check that the absolute value of the addend can be
27783 expressed as an 8-bit constant plus a rotation. */
27784 encoded_addend
= encode_arm_immediate (addend_abs
);
27785 if (encoded_addend
== (unsigned int) FAIL
)
27786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27787 _("the offset 0x%08lX is not representable"),
27788 (unsigned long) addend_abs
);
27790 /* Extract the instruction. */
27791 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27793 /* If the addend is positive, use an ADD instruction.
27794 Otherwise use a SUB. Take care not to destroy the S bit. */
27795 insn
&= 0xff1fffff;
27801 /* Place the encoded addend into the first 12 bits of the
27803 insn
&= 0xfffff000;
27804 insn
|= encoded_addend
;
27806 /* Update the instruction. */
27807 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27811 case BFD_RELOC_ARM_LDR_PC_G0
:
27812 case BFD_RELOC_ARM_LDR_PC_G1
:
27813 case BFD_RELOC_ARM_LDR_PC_G2
:
27814 case BFD_RELOC_ARM_LDR_SB_G0
:
27815 case BFD_RELOC_ARM_LDR_SB_G1
:
27816 case BFD_RELOC_ARM_LDR_SB_G2
:
27817 gas_assert (!fixP
->fx_done
);
27818 if (!seg
->use_rela_p
)
27821 bfd_vma addend_abs
= llabs (value
);
27823 /* Check that the absolute value of the addend can be
27824 encoded in 12 bits. */
27825 if (addend_abs
>= 0x1000)
27826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27827 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27828 (unsigned long) addend_abs
);
27830 /* Extract the instruction. */
27831 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27833 /* If the addend is negative, clear bit 23 of the instruction.
27834 Otherwise set it. */
27836 insn
&= ~(1 << 23);
27840 /* Place the absolute value of the addend into the first 12 bits
27841 of the instruction. */
27842 insn
&= 0xfffff000;
27843 insn
|= addend_abs
;
27845 /* Update the instruction. */
27846 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27850 case BFD_RELOC_ARM_LDRS_PC_G0
:
27851 case BFD_RELOC_ARM_LDRS_PC_G1
:
27852 case BFD_RELOC_ARM_LDRS_PC_G2
:
27853 case BFD_RELOC_ARM_LDRS_SB_G0
:
27854 case BFD_RELOC_ARM_LDRS_SB_G1
:
27855 case BFD_RELOC_ARM_LDRS_SB_G2
:
27856 gas_assert (!fixP
->fx_done
);
27857 if (!seg
->use_rela_p
)
27860 bfd_vma addend_abs
= llabs (value
);
27862 /* Check that the absolute value of the addend can be
27863 encoded in 8 bits. */
27864 if (addend_abs
>= 0x100)
27865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27866 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27867 (unsigned long) addend_abs
);
27869 /* Extract the instruction. */
27870 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27872 /* If the addend is negative, clear bit 23 of the instruction.
27873 Otherwise set it. */
27875 insn
&= ~(1 << 23);
27879 /* Place the first four bits of the absolute value of the addend
27880 into the first 4 bits of the instruction, and the remaining
27881 four into bits 8 .. 11. */
27882 insn
&= 0xfffff0f0;
27883 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
27885 /* Update the instruction. */
27886 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27890 case BFD_RELOC_ARM_LDC_PC_G0
:
27891 case BFD_RELOC_ARM_LDC_PC_G1
:
27892 case BFD_RELOC_ARM_LDC_PC_G2
:
27893 case BFD_RELOC_ARM_LDC_SB_G0
:
27894 case BFD_RELOC_ARM_LDC_SB_G1
:
27895 case BFD_RELOC_ARM_LDC_SB_G2
:
27896 gas_assert (!fixP
->fx_done
);
27897 if (!seg
->use_rela_p
)
27900 bfd_vma addend_abs
= llabs (value
);
27902 /* Check that the absolute value of the addend is a multiple of
27903 four and, when divided by four, fits in 8 bits. */
27904 if (addend_abs
& 0x3)
27905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27906 _("bad offset 0x%08lX (must be word-aligned)"),
27907 (unsigned long) addend_abs
);
27909 if ((addend_abs
>> 2) > 0xff)
27910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27911 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27912 (unsigned long) addend_abs
);
27914 /* Extract the instruction. */
27915 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27917 /* If the addend is negative, clear bit 23 of the instruction.
27918 Otherwise set it. */
27920 insn
&= ~(1 << 23);
27924 /* Place the addend (divided by four) into the first eight
27925 bits of the instruction. */
27926 insn
&= 0xfffffff0;
27927 insn
|= addend_abs
>> 2;
27929 /* Update the instruction. */
27930 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27934 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27936 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27937 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27938 && ARM_IS_FUNC (fixP
->fx_addsy
)
27939 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27941 /* Force a relocation for a branch 5 bits wide. */
27944 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
27945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27948 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27950 addressT boff
= value
>> 1;
27952 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27953 newval
|= (boff
<< 7);
27954 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27958 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27960 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27961 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27962 && ARM_IS_FUNC (fixP
->fx_addsy
)
27963 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27967 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
27968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27969 _("branch out of range"));
27971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27973 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27975 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
27976 addressT diff
= value
- boff
;
27980 newval
|= 1 << 1; /* T bit. */
27982 else if (diff
!= 2)
27984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27985 _("out of range label-relative fixup value"));
27987 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27991 case BFD_RELOC_ARM_THUMB_BF17
:
27993 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27994 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27995 && ARM_IS_FUNC (fixP
->fx_addsy
)
27996 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27998 /* Force a relocation for a branch 17 bits wide. */
28002 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28003 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28006 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28009 addressT immA
, immB
, immC
;
28011 immA
= (value
& 0x0001f000) >> 12;
28012 immB
= (value
& 0x00000ffc) >> 2;
28013 immC
= (value
& 0x00000002) >> 1;
28015 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28016 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28018 newval2
|= (immC
<< 11) | (immB
<< 1);
28019 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28020 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28024 case BFD_RELOC_ARM_THUMB_BF19
:
28026 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28027 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28028 && ARM_IS_FUNC (fixP
->fx_addsy
)
28029 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28031 /* Force a relocation for a branch 19 bits wide. */
28035 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28039 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28042 addressT immA
, immB
, immC
;
28044 immA
= (value
& 0x0007f000) >> 12;
28045 immB
= (value
& 0x00000ffc) >> 2;
28046 immC
= (value
& 0x00000002) >> 1;
28048 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28049 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28051 newval2
|= (immC
<< 11) | (immB
<< 1);
28052 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28053 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28057 case BFD_RELOC_ARM_THUMB_BF13
:
28059 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28060 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28061 && ARM_IS_FUNC (fixP
->fx_addsy
)
28062 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28064 /* Force a relocation for a branch 13 bits wide. */
28068 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28072 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28075 addressT immA
, immB
, immC
;
28077 immA
= (value
& 0x00001000) >> 12;
28078 immB
= (value
& 0x00000ffc) >> 2;
28079 immC
= (value
& 0x00000002) >> 1;
28081 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28082 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28084 newval2
|= (immC
<< 11) | (immB
<< 1);
28085 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28086 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28090 case BFD_RELOC_ARM_THUMB_LOOP12
:
28092 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28093 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28094 && ARM_IS_FUNC (fixP
->fx_addsy
)
28095 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28097 /* Force a relocation for a branch 12 bits wide. */
28101 bfd_vma insn
= get_thumb32_insn (buf
);
28102 /* le lr, <label> or le <label> */
28103 if (((insn
& 0xffffffff) == 0xf00fc001)
28104 || ((insn
& 0xffffffff) == 0xf02fc001))
28107 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28112 addressT imml
, immh
;
28114 immh
= (value
& 0x00000ffc) >> 2;
28115 imml
= (value
& 0x00000002) >> 1;
28117 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28118 newval
|= (imml
<< 11) | (immh
<< 1);
28119 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28123 case BFD_RELOC_ARM_V4BX
:
28124 /* This will need to go in the object file. */
28128 case BFD_RELOC_UNUSED
:
28130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28131 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28135 /* Translate internal representation of relocation info to BFD target
28139 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28142 bfd_reloc_code_real_type code
;
28144 reloc
= XNEW (arelent
);
28146 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28147 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28148 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28150 if (fixp
->fx_pcrel
)
28152 if (section
->use_rela_p
)
28153 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28155 fixp
->fx_offset
= reloc
->address
;
28157 reloc
->addend
= fixp
->fx_offset
;
28159 switch (fixp
->fx_r_type
)
28162 if (fixp
->fx_pcrel
)
28164 code
= BFD_RELOC_8_PCREL
;
28167 /* Fall through. */
28170 if (fixp
->fx_pcrel
)
28172 code
= BFD_RELOC_16_PCREL
;
28175 /* Fall through. */
28178 if (fixp
->fx_pcrel
)
28180 code
= BFD_RELOC_32_PCREL
;
28183 /* Fall through. */
28185 case BFD_RELOC_ARM_MOVW
:
28186 if (fixp
->fx_pcrel
)
28188 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28191 /* Fall through. */
28193 case BFD_RELOC_ARM_MOVT
:
28194 if (fixp
->fx_pcrel
)
28196 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28199 /* Fall through. */
28201 case BFD_RELOC_ARM_THUMB_MOVW
:
28202 if (fixp
->fx_pcrel
)
28204 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28207 /* Fall through. */
28209 case BFD_RELOC_ARM_THUMB_MOVT
:
28210 if (fixp
->fx_pcrel
)
28212 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28215 /* Fall through. */
28217 case BFD_RELOC_NONE
:
28218 case BFD_RELOC_ARM_PCREL_BRANCH
:
28219 case BFD_RELOC_ARM_PCREL_BLX
:
28220 case BFD_RELOC_RVA
:
28221 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28222 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28223 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28224 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28225 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28226 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28227 case BFD_RELOC_VTABLE_ENTRY
:
28228 case BFD_RELOC_VTABLE_INHERIT
:
28230 case BFD_RELOC_32_SECREL
:
28232 code
= fixp
->fx_r_type
;
28235 case BFD_RELOC_THUMB_PCREL_BLX
:
28237 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28238 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28241 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28244 case BFD_RELOC_ARM_LITERAL
:
28245 case BFD_RELOC_ARM_HWLITERAL
:
28246 /* If this is called then the a literal has
28247 been referenced across a section boundary. */
28248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28249 _("literal referenced across section boundary"));
28253 case BFD_RELOC_ARM_TLS_CALL
:
28254 case BFD_RELOC_ARM_THM_TLS_CALL
:
28255 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28256 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28257 case BFD_RELOC_ARM_GOT32
:
28258 case BFD_RELOC_ARM_GOTOFF
:
28259 case BFD_RELOC_ARM_GOT_PREL
:
28260 case BFD_RELOC_ARM_PLT32
:
28261 case BFD_RELOC_ARM_TARGET1
:
28262 case BFD_RELOC_ARM_ROSEGREL32
:
28263 case BFD_RELOC_ARM_SBREL32
:
28264 case BFD_RELOC_ARM_PREL31
:
28265 case BFD_RELOC_ARM_TARGET2
:
28266 case BFD_RELOC_ARM_TLS_LDO32
:
28267 case BFD_RELOC_ARM_PCREL_CALL
:
28268 case BFD_RELOC_ARM_PCREL_JUMP
:
28269 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28270 case BFD_RELOC_ARM_ALU_PC_G0
:
28271 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28272 case BFD_RELOC_ARM_ALU_PC_G1
:
28273 case BFD_RELOC_ARM_ALU_PC_G2
:
28274 case BFD_RELOC_ARM_LDR_PC_G0
:
28275 case BFD_RELOC_ARM_LDR_PC_G1
:
28276 case BFD_RELOC_ARM_LDR_PC_G2
:
28277 case BFD_RELOC_ARM_LDRS_PC_G0
:
28278 case BFD_RELOC_ARM_LDRS_PC_G1
:
28279 case BFD_RELOC_ARM_LDRS_PC_G2
:
28280 case BFD_RELOC_ARM_LDC_PC_G0
:
28281 case BFD_RELOC_ARM_LDC_PC_G1
:
28282 case BFD_RELOC_ARM_LDC_PC_G2
:
28283 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28284 case BFD_RELOC_ARM_ALU_SB_G0
:
28285 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28286 case BFD_RELOC_ARM_ALU_SB_G1
:
28287 case BFD_RELOC_ARM_ALU_SB_G2
:
28288 case BFD_RELOC_ARM_LDR_SB_G0
:
28289 case BFD_RELOC_ARM_LDR_SB_G1
:
28290 case BFD_RELOC_ARM_LDR_SB_G2
:
28291 case BFD_RELOC_ARM_LDRS_SB_G0
:
28292 case BFD_RELOC_ARM_LDRS_SB_G1
:
28293 case BFD_RELOC_ARM_LDRS_SB_G2
:
28294 case BFD_RELOC_ARM_LDC_SB_G0
:
28295 case BFD_RELOC_ARM_LDC_SB_G1
:
28296 case BFD_RELOC_ARM_LDC_SB_G2
:
28297 case BFD_RELOC_ARM_V4BX
:
28298 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28299 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28300 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28301 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28302 case BFD_RELOC_ARM_GOTFUNCDESC
:
28303 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28304 case BFD_RELOC_ARM_FUNCDESC
:
28305 case BFD_RELOC_ARM_THUMB_BF17
:
28306 case BFD_RELOC_ARM_THUMB_BF19
:
28307 case BFD_RELOC_ARM_THUMB_BF13
:
28308 code
= fixp
->fx_r_type
;
28311 case BFD_RELOC_ARM_TLS_GOTDESC
:
28312 case BFD_RELOC_ARM_TLS_GD32
:
28313 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28314 case BFD_RELOC_ARM_TLS_LE32
:
28315 case BFD_RELOC_ARM_TLS_IE32
:
28316 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28317 case BFD_RELOC_ARM_TLS_LDM32
:
28318 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28319 /* BFD will include the symbol's address in the addend.
28320 But we don't want that, so subtract it out again here. */
28321 if (!S_IS_COMMON (fixp
->fx_addsy
))
28322 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28323 code
= fixp
->fx_r_type
;
28327 case BFD_RELOC_ARM_IMMEDIATE
:
28328 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28329 _("internal relocation (type: IMMEDIATE) not fixed up"));
28332 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28333 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28334 _("ADRL used for a symbol not defined in the same file"));
28337 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28338 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28339 case BFD_RELOC_ARM_THUMB_LOOP12
:
28340 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28341 _("%s used for a symbol not defined in the same file"),
28342 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28345 case BFD_RELOC_ARM_OFFSET_IMM
:
28346 if (section
->use_rela_p
)
28348 code
= fixp
->fx_r_type
;
28352 if (fixp
->fx_addsy
!= NULL
28353 && !S_IS_DEFINED (fixp
->fx_addsy
)
28354 && S_IS_LOCAL (fixp
->fx_addsy
))
28356 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28357 _("undefined local label `%s'"),
28358 S_GET_NAME (fixp
->fx_addsy
));
28362 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28363 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28370 switch (fixp
->fx_r_type
)
28372 case BFD_RELOC_NONE
: type
= "NONE"; break;
28373 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28374 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28375 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28376 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28377 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28378 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28379 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28380 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28381 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28382 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28383 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28384 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28385 default: type
= _("<unknown>"); break;
28387 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28388 _("cannot represent %s relocation in this object file format"),
28395 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28397 && fixp
->fx_addsy
== GOT_symbol
)
28399 code
= BFD_RELOC_ARM_GOTPC
;
28400 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
28404 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
28406 if (reloc
->howto
== NULL
)
28408 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28409 _("cannot represent %s relocation in this object file format"),
28410 bfd_get_reloc_code_name (code
));
28414 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
28415 vtable entry to be used in the relocation's section offset. */
28416 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28417 reloc
->address
= fixp
->fx_offset
;
28422 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
28425 cons_fix_new_arm (fragS
* frag
,
28429 bfd_reloc_code_real_type reloc
)
28434 FIXME: @@ Should look at CPU word size. */
28438 reloc
= BFD_RELOC_8
;
28441 reloc
= BFD_RELOC_16
;
28445 reloc
= BFD_RELOC_32
;
28448 reloc
= BFD_RELOC_64
;
28453 if (exp
->X_op
== O_secrel
)
28455 exp
->X_op
= O_symbol
;
28456 reloc
= BFD_RELOC_32_SECREL
;
28460 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
28463 #if defined (OBJ_COFF)
28465 arm_validate_fix (fixS
* fixP
)
28467 /* If the destination of the branch is a defined symbol which does not have
28468 the THUMB_FUNC attribute, then we must be calling a function which has
28469 the (interfacearm) attribute. We look for the Thumb entry point to that
28470 function and change the branch to refer to that function instead. */
28471 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
28472 && fixP
->fx_addsy
!= NULL
28473 && S_IS_DEFINED (fixP
->fx_addsy
)
28474 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
28476 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
28483 arm_force_relocation (struct fix
* fixp
)
28485 #if defined (OBJ_COFF) && defined (TE_PE)
28486 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
28490 /* In case we have a call or a branch to a function in ARM ISA mode from
28491 a thumb function or vice-versa force the relocation. These relocations
28492 are cleared off for some cores that might have blx and simple transformations
28496 switch (fixp
->fx_r_type
)
28498 case BFD_RELOC_ARM_PCREL_JUMP
:
28499 case BFD_RELOC_ARM_PCREL_CALL
:
28500 case BFD_RELOC_THUMB_PCREL_BLX
:
28501 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
28505 case BFD_RELOC_ARM_PCREL_BLX
:
28506 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28507 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28508 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28509 if (ARM_IS_FUNC (fixp
->fx_addsy
))
28518 /* Resolve these relocations even if the symbol is extern or weak.
28519 Technically this is probably wrong due to symbol preemption.
28520 In practice these relocations do not have enough range to be useful
28521 at dynamic link time, and some code (e.g. in the Linux kernel)
28522 expects these references to be resolved. */
28523 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
28524 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
28525 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
28526 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
28527 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28528 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
28529 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
28530 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
28531 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28532 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
28533 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
28534 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
28535 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
28536 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
28539 /* Always leave these relocations for the linker. */
28540 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28541 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28542 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28545 /* Always generate relocations against function symbols. */
28546 if (fixp
->fx_r_type
== BFD_RELOC_32
28548 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
28551 return generic_force_reloc (fixp
);
28554 #if defined (OBJ_ELF) || defined (OBJ_COFF)
28555 /* Relocations against function names must be left unadjusted,
28556 so that the linker can use this information to generate interworking
28557 stubs. The MIPS version of this function
28558 also prevents relocations that are mips-16 specific, but I do not
28559 know why it does this.
28562 There is one other problem that ought to be addressed here, but
28563 which currently is not: Taking the address of a label (rather
28564 than a function) and then later jumping to that address. Such
28565 addresses also ought to have their bottom bit set (assuming that
28566 they reside in Thumb code), but at the moment they will not. */
28569 arm_fix_adjustable (fixS
* fixP
)
28571 if (fixP
->fx_addsy
== NULL
)
28574 /* Preserve relocations against symbols with function type. */
28575 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
28578 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
28579 && fixP
->fx_subsy
== NULL
)
28582 /* We need the symbol name for the VTABLE entries. */
28583 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
28584 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28587 /* Don't allow symbols to be discarded on GOT related relocs. */
28588 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
28589 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
28590 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
28591 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
28592 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
28593 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
28594 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
28595 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
28596 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
28597 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
28598 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
28599 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
28600 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
28601 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
28602 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
28603 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
28604 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
28607 /* Similarly for group relocations. */
28608 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28609 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28610 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28613 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28614 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
28615 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28616 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
28617 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
28618 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28619 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
28620 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
28621 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
28624 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28625 offsets, so keep these symbols. */
28626 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28627 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
28632 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
28636 elf32_arm_target_format (void)
28639 return (target_big_endian
28640 ? "elf32-bigarm-symbian"
28641 : "elf32-littlearm-symbian");
28642 #elif defined (TE_VXWORKS)
28643 return (target_big_endian
28644 ? "elf32-bigarm-vxworks"
28645 : "elf32-littlearm-vxworks");
28646 #elif defined (TE_NACL)
28647 return (target_big_endian
28648 ? "elf32-bigarm-nacl"
28649 : "elf32-littlearm-nacl");
28653 if (target_big_endian
)
28654 return "elf32-bigarm-fdpic";
28656 return "elf32-littlearm-fdpic";
28660 if (target_big_endian
)
28661 return "elf32-bigarm";
28663 return "elf32-littlearm";
28669 armelf_frob_symbol (symbolS
* symp
,
28672 elf_frob_symbol (symp
, puntp
);
28676 /* MD interface: Finalization. */
28681 literal_pool
* pool
;
28683 /* Ensure that all the predication blocks are properly closed. */
28684 check_pred_blocks_finished ();
28686 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
28688 /* Put it at the end of the relevant section. */
28689 subseg_set (pool
->section
, pool
->sub_section
);
28691 arm_elf_change_section ();
28698 /* Remove any excess mapping symbols generated for alignment frags in
28699 SEC. We may have created a mapping symbol before a zero byte
28700 alignment; remove it if there's a mapping symbol after the
28703 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
28704 void *dummy ATTRIBUTE_UNUSED
)
28706 segment_info_type
*seginfo
= seg_info (sec
);
28709 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
28712 for (fragp
= seginfo
->frchainP
->frch_root
;
28714 fragp
= fragp
->fr_next
)
28716 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
28717 fragS
*next
= fragp
->fr_next
;
28719 /* Variable-sized frags have been converted to fixed size by
28720 this point. But if this was variable-sized to start with,
28721 there will be a fixed-size frag after it. So don't handle
28723 if (sym
== NULL
|| next
== NULL
)
28726 if (S_GET_VALUE (sym
) < next
->fr_address
)
28727 /* Not at the end of this frag. */
28729 know (S_GET_VALUE (sym
) == next
->fr_address
);
28733 if (next
->tc_frag_data
.first_map
!= NULL
)
28735 /* Next frag starts with a mapping symbol. Discard this
28737 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28741 if (next
->fr_next
== NULL
)
28743 /* This mapping symbol is at the end of the section. Discard
28745 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
28746 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28750 /* As long as we have empty frags without any mapping symbols,
28752 /* If the next frag is non-empty and does not start with a
28753 mapping symbol, then this mapping symbol is required. */
28754 if (next
->fr_address
!= next
->fr_next
->fr_address
)
28757 next
= next
->fr_next
;
28759 while (next
!= NULL
);
28764 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28768 arm_adjust_symtab (void)
28773 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28775 if (ARM_IS_THUMB (sym
))
28777 if (THUMB_IS_FUNC (sym
))
28779 /* Mark the symbol as a Thumb function. */
28780 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
28781 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
28782 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
28784 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
28785 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
28787 as_bad (_("%s: unexpected function type: %d"),
28788 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
28790 else switch (S_GET_STORAGE_CLASS (sym
))
28793 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
28796 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
28799 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
28807 if (ARM_IS_INTERWORK (sym
))
28808 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
28815 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28817 if (ARM_IS_THUMB (sym
))
28819 elf_symbol_type
* elf_sym
;
28821 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
28822 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
28824 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
28825 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
28827 /* If it's a .thumb_func, declare it as so,
28828 otherwise tag label as .code 16. */
28829 if (THUMB_IS_FUNC (sym
))
28830 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
28831 ST_BRANCH_TO_THUMB
);
28832 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28833 elf_sym
->internal_elf_sym
.st_info
=
28834 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
28839 /* Remove any overlapping mapping symbols generated by alignment frags. */
28840 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
28841 /* Now do generic ELF adjustments. */
28842 elf_adjust_symtab ();
28846 /* MD interface: Initialization. */
28849 set_constant_flonums (void)
28853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
28854 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
28858 /* Auto-select Thumb mode if it's the only available instruction set for the
28859 given architecture. */
28862 autoselect_thumb_from_cpu_variant (void)
28864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
28865 opcode_select (16);
28874 if ( (arm_ops_hsh
= hash_new ()) == NULL
28875 || (arm_cond_hsh
= hash_new ()) == NULL
28876 || (arm_vcond_hsh
= hash_new ()) == NULL
28877 || (arm_shift_hsh
= hash_new ()) == NULL
28878 || (arm_psr_hsh
= hash_new ()) == NULL
28879 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
28880 || (arm_reg_hsh
= hash_new ()) == NULL
28881 || (arm_reloc_hsh
= hash_new ()) == NULL
28882 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
28883 as_fatal (_("virtual memory exhausted"));
28885 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
28886 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
28887 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
28888 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
28889 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
28890 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
28891 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
28892 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
28893 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
28894 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
28895 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
28896 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
28897 (void *) (v7m_psrs
+ i
));
28898 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
28899 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
28901 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
28903 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
28904 (void *) (barrier_opt_names
+ i
));
28906 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
28908 struct reloc_entry
* entry
= reloc_names
+ i
;
28910 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
28911 /* This makes encode_branch() use the EABI versions of this relocation. */
28912 entry
->reloc
= BFD_RELOC_UNUSED
;
28914 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
28918 set_constant_flonums ();
28920 /* Set the cpu variant based on the command-line options. We prefer
28921 -mcpu= over -march= if both are set (as for GCC); and we prefer
28922 -mfpu= over any other way of setting the floating point unit.
28923 Use of legacy options with new options are faulted. */
28926 if (mcpu_cpu_opt
|| march_cpu_opt
)
28927 as_bad (_("use of old and new-style options to set CPU type"));
28929 selected_arch
= *legacy_cpu
;
28931 else if (mcpu_cpu_opt
)
28933 selected_arch
= *mcpu_cpu_opt
;
28934 selected_ext
= *mcpu_ext_opt
;
28936 else if (march_cpu_opt
)
28938 selected_arch
= *march_cpu_opt
;
28939 selected_ext
= *march_ext_opt
;
28941 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28946 as_bad (_("use of old and new-style options to set FPU type"));
28948 selected_fpu
= *legacy_fpu
;
28951 selected_fpu
= *mfpu_opt
;
28954 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28955 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28956 /* Some environments specify a default FPU. If they don't, infer it
28957 from the processor. */
28959 selected_fpu
= *mcpu_fpu_opt
;
28960 else if (march_fpu_opt
)
28961 selected_fpu
= *march_fpu_opt
;
28963 selected_fpu
= fpu_default
;
28967 if (ARM_FEATURE_ZERO (selected_fpu
))
28969 if (!no_cpu_selected ())
28970 selected_fpu
= fpu_default
;
28972 selected_fpu
= fpu_arch_fpa
;
28976 if (ARM_FEATURE_ZERO (selected_arch
))
28978 selected_arch
= cpu_default
;
28979 selected_cpu
= selected_arch
;
28981 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28983 /* Autodection of feature mode: allow all features in cpu_variant but leave
28984 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28985 after all instruction have been processed and we can decide what CPU
28986 should be selected. */
28987 if (ARM_FEATURE_ZERO (selected_arch
))
28988 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28990 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28993 autoselect_thumb_from_cpu_variant ();
28995 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
28997 #if defined OBJ_COFF || defined OBJ_ELF
28999 unsigned int flags
= 0;
29001 #if defined OBJ_ELF
29002 flags
= meabi_flags
;
29004 switch (meabi_flags
)
29006 case EF_ARM_EABI_UNKNOWN
:
29008 /* Set the flags in the private structure. */
29009 if (uses_apcs_26
) flags
|= F_APCS26
;
29010 if (support_interwork
) flags
|= F_INTERWORK
;
29011 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29012 if (pic_code
) flags
|= F_PIC
;
29013 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29014 flags
|= F_SOFT_FLOAT
;
29016 switch (mfloat_abi_opt
)
29018 case ARM_FLOAT_ABI_SOFT
:
29019 case ARM_FLOAT_ABI_SOFTFP
:
29020 flags
|= F_SOFT_FLOAT
;
29023 case ARM_FLOAT_ABI_HARD
:
29024 if (flags
& F_SOFT_FLOAT
)
29025 as_bad (_("hard-float conflicts with specified fpu"));
29029 /* Using pure-endian doubles (even if soft-float). */
29030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29031 flags
|= F_VFP_FLOAT
;
29033 #if defined OBJ_ELF
29034 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29035 flags
|= EF_ARM_MAVERICK_FLOAT
;
29038 case EF_ARM_EABI_VER4
:
29039 case EF_ARM_EABI_VER5
:
29040 /* No additional flags to set. */
29047 bfd_set_private_flags (stdoutput
, flags
);
29049 /* We have run out flags in the COFF header to encode the
29050 status of ATPCS support, so instead we create a dummy,
29051 empty, debug section called .arm.atpcs. */
29056 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29060 bfd_set_section_flags
29061 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29062 bfd_set_section_size (stdoutput
, sec
, 0);
29063 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29069 /* Record the CPU type as well. */
29070 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29071 mach
= bfd_mach_arm_iWMMXt2
;
29072 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29073 mach
= bfd_mach_arm_iWMMXt
;
29074 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29075 mach
= bfd_mach_arm_XScale
;
29076 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29077 mach
= bfd_mach_arm_ep9312
;
29078 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29079 mach
= bfd_mach_arm_5TE
;
29080 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29082 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29083 mach
= bfd_mach_arm_5T
;
29085 mach
= bfd_mach_arm_5
;
29087 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29089 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29090 mach
= bfd_mach_arm_4T
;
29092 mach
= bfd_mach_arm_4
;
29094 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29095 mach
= bfd_mach_arm_3M
;
29096 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29097 mach
= bfd_mach_arm_3
;
29098 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29099 mach
= bfd_mach_arm_2a
;
29100 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29101 mach
= bfd_mach_arm_2
;
29103 mach
= bfd_mach_arm_unknown
;
29105 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29108 /* Command line processing. */
29111 Invocation line includes a switch not recognized by the base assembler.
29112 See if it's a processor-specific option.
29114 This routine is somewhat complicated by the need for backwards
29115 compatibility (since older releases of gcc can't be changed).
29116 The new options try to make the interface as compatible as
29119 New options (supported) are:
29121 -mcpu=<cpu name> Assemble for selected processor
29122 -march=<architecture name> Assemble for selected architecture
29123 -mfpu=<fpu architecture> Assemble for selected FPU.
29124 -EB/-mbig-endian Big-endian
29125 -EL/-mlittle-endian Little-endian
29126 -k Generate PIC code
29127 -mthumb Start in Thumb mode
29128 -mthumb-interwork Code supports ARM/Thumb interworking
29130 -m[no-]warn-deprecated Warn about deprecated features
29131 -m[no-]warn-syms Warn when symbols match instructions
29133 For now we will also provide support for:
29135 -mapcs-32 32-bit Program counter
29136 -mapcs-26 26-bit Program counter
29137 -macps-float Floats passed in FP registers
29138 -mapcs-reentrant Reentrant code
29140 (sometime these will probably be replaced with -mapcs=<list of options>
29141 and -matpcs=<list of options>)
29143 The remaining options are only supported for back-wards compatibility.
29144 Cpu variants, the arm part is optional:
29145 -m[arm]1 Currently not supported.
29146 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29147 -m[arm]3 Arm 3 processor
29148 -m[arm]6[xx], Arm 6 processors
29149 -m[arm]7[xx][t][[d]m] Arm 7 processors
29150 -m[arm]8[10] Arm 8 processors
29151 -m[arm]9[20][tdmi] Arm 9 processors
29152 -mstrongarm[110[0]] StrongARM processors
29153 -mxscale XScale processors
29154 -m[arm]v[2345[t[e]]] Arm architectures
29155 -mall All (except the ARM1)
29157 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29158 -mfpe-old (No float load/store multiples)
29159 -mvfpxd VFP Single precision
29161 -mno-fpu Disable all floating point instructions
29163 The following CPU names are recognized:
29164 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29165 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29166 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29167 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29168 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29169 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29170 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29174 const char * md_shortopts
= "m:k";
29176 #ifdef ARM_BI_ENDIAN
29177 #define OPTION_EB (OPTION_MD_BASE + 0)
29178 #define OPTION_EL (OPTION_MD_BASE + 1)
29180 #if TARGET_BYTES_BIG_ENDIAN
29181 #define OPTION_EB (OPTION_MD_BASE + 0)
29183 #define OPTION_EL (OPTION_MD_BASE + 1)
29186 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29187 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29189 struct option md_longopts
[] =
29192 {"EB", no_argument
, NULL
, OPTION_EB
},
29195 {"EL", no_argument
, NULL
, OPTION_EL
},
29197 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29199 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29201 {NULL
, no_argument
, NULL
, 0}
29204 size_t md_longopts_size
= sizeof (md_longopts
);
29206 struct arm_option_table
29208 const char * option
; /* Option name to match. */
29209 const char * help
; /* Help information. */
29210 int * var
; /* Variable to change. */
29211 int value
; /* What to change it to. */
29212 const char * deprecated
; /* If non-null, print this message. */
29215 struct arm_option_table arm_opts
[] =
29217 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29218 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29219 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29220 &support_interwork
, 1, NULL
},
29221 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29222 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29223 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29225 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29226 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29227 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29228 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29231 /* These are recognized by the assembler, but have no affect on code. */
29232 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29233 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29235 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29236 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29237 &warn_on_deprecated
, 0, NULL
},
29238 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29239 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29240 {NULL
, NULL
, NULL
, 0, NULL
}
29243 struct arm_legacy_option_table
29245 const char * option
; /* Option name to match. */
29246 const arm_feature_set
** var
; /* Variable to change. */
29247 const arm_feature_set value
; /* What to change it to. */
29248 const char * deprecated
; /* If non-null, print this message. */
29251 const struct arm_legacy_option_table arm_legacy_opts
[] =
29253 /* DON'T add any new processors to this list -- we want the whole list
29254 to go away... Add them to the processors table instead. */
29255 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29256 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29257 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29258 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29259 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29260 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29261 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29262 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29263 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29264 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29265 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29266 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29267 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29268 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29269 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29270 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29271 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29272 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29273 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29274 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29275 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29276 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29277 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29278 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29279 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29280 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29281 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29282 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29283 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29284 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29285 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29286 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29287 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29288 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29289 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29290 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29291 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29292 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29293 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29294 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29295 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29296 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29297 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29298 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29299 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29300 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29301 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29302 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29303 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29304 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29305 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29306 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29307 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29308 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29309 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29310 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29311 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29312 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29313 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29314 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29315 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29316 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29317 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29318 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29319 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29320 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29321 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29322 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29323 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29324 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29325 N_("use -mcpu=strongarm110")},
29326 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29327 N_("use -mcpu=strongarm1100")},
29328 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29329 N_("use -mcpu=strongarm1110")},
29330 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29331 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29332 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29334 /* Architecture variants -- don't add any more to this list either. */
29335 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29336 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29337 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29338 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29339 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29340 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29341 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29342 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29343 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29344 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29345 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29346 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29347 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29348 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29349 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29350 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29351 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29352 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29354 /* Floating point variants -- don't add any more to this list either. */
29355 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29356 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29357 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29358 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29359 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29361 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29364 struct arm_cpu_option_table
29368 const arm_feature_set value
;
29369 const arm_feature_set ext
;
29370 /* For some CPUs we assume an FPU unless the user explicitly sets
29372 const arm_feature_set default_fpu
;
29373 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29375 const char * canonical_name
;
29378 /* This list should, at a minimum, contain all the cpu names
29379 recognized by GCC. */
29380 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29382 static const struct arm_cpu_option_table arm_cpus
[] =
29384 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29387 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29390 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29393 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29396 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29399 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
29402 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
29405 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
29408 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
29411 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
29414 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
29417 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
29420 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
29423 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
29426 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
29429 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
29432 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
29435 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
29438 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
29441 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
29444 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
29447 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
29450 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
29453 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
29456 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
29459 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
29462 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
29465 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
29468 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
29471 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
29474 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
29477 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
29480 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
29483 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
29486 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
29489 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
29492 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
29495 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
29498 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
29501 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
29504 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
29507 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
29510 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
29513 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
29516 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
29519 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
29523 /* For V5 or later processors we default to using VFP; but the user
29524 should really set the FPU type explicitly. */
29525 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
29528 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
29531 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29534 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
29537 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
29540 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
29543 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
29546 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
29549 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
29552 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
29555 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
29558 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
29561 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
29564 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
29567 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
29570 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
29573 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
29576 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
29579 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
29582 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
29585 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
29588 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
29591 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
29594 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
29597 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
29600 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
29603 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
29606 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
29609 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
29612 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
29615 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
29618 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
29621 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
29624 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
29627 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
29630 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
29633 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
29634 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29636 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
29638 FPU_ARCH_NEON_VFP_V4
),
29639 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
29640 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29641 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29642 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
29643 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29644 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29645 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
29647 FPU_ARCH_NEON_VFP_V4
),
29648 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
29650 FPU_ARCH_NEON_VFP_V4
),
29651 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
29653 FPU_ARCH_NEON_VFP_V4
),
29654 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
29655 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29656 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29657 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
29658 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29659 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29660 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
29661 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29662 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29663 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
29664 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29665 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29666 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
29667 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29668 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29669 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
29670 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29671 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29672 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
29673 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29674 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29675 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
29676 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29677 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29678 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
29679 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29680 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29681 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
29682 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29683 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29684 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
29687 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
29689 FPU_ARCH_VFP_V3D16
),
29690 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
29691 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29693 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
29694 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29695 FPU_ARCH_VFP_V3D16
),
29696 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
29697 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29698 FPU_ARCH_VFP_V3D16
),
29699 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
29700 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29701 FPU_ARCH_NEON_VFP_ARMV8
),
29702 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
29703 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29705 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
29708 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
29711 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
29714 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
29717 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
29720 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
29723 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
29726 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
29727 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29728 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29729 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
29730 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29731 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29732 /* ??? XSCALE is really an architecture. */
29733 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
29737 /* ??? iwmmxt is not a processor. */
29738 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
29741 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
29744 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
29749 ARM_CPU_OPT ("ep9312", "ARM920T",
29750 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
29751 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
29753 /* Marvell processors. */
29754 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
29755 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29756 FPU_ARCH_VFP_V3D16
),
29757 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
29758 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29759 FPU_ARCH_NEON_VFP_V4
),
29761 /* APM X-Gene family. */
29762 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
29764 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29765 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
29766 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29767 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29769 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29773 struct arm_ext_table
29777 const arm_feature_set merge
;
29778 const arm_feature_set clear
;
29781 struct arm_arch_option_table
29785 const arm_feature_set value
;
29786 const arm_feature_set default_fpu
;
29787 const struct arm_ext_table
* ext_table
;
29790 /* Used to add support for +E and +noE extension. */
29791 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29792 /* Used to add support for a +E extension. */
29793 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29794 /* Used to add support for a +noE extension. */
29795 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29797 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29798 ~0 & ~FPU_ENDIAN_PURE)
29800 static const struct arm_ext_table armv5te_ext_table
[] =
29802 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
29803 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29806 static const struct arm_ext_table armv7_ext_table
[] =
29808 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29809 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29812 static const struct arm_ext_table armv7ve_ext_table
[] =
29814 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
29815 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
29816 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29817 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29818 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29819 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
29820 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29822 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
29823 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29825 /* Aliases for +simd. */
29826 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29828 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29829 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29830 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29832 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29835 static const struct arm_ext_table armv7a_ext_table
[] =
29837 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29838 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29839 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29840 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29841 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29842 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
29843 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29845 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
29846 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29848 /* Aliases for +simd. */
29849 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29850 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29852 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29853 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29855 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
29856 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
29857 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29860 static const struct arm_ext_table armv7r_ext_table
[] =
29862 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
29863 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
29864 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29865 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29866 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
29867 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29868 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29869 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
29870 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29873 static const struct arm_ext_table armv7em_ext_table
[] =
29875 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
29876 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29877 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
29878 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
29879 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29880 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
29881 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29884 static const struct arm_ext_table armv8a_ext_table
[] =
29886 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29887 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29888 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29889 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29891 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29892 should use the +simd option to turn on FP. */
29893 ARM_REMOVE ("fp", ALL_FP
),
29894 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29895 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29896 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29900 static const struct arm_ext_table armv81a_ext_table
[] =
29902 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29903 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29904 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29906 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29907 should use the +simd option to turn on FP. */
29908 ARM_REMOVE ("fp", ALL_FP
),
29909 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29910 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29911 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29914 static const struct arm_ext_table armv82a_ext_table
[] =
29916 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29917 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
29918 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
29919 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29920 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29921 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29923 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29924 should use the +simd option to turn on FP. */
29925 ARM_REMOVE ("fp", ALL_FP
),
29926 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29927 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29928 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29931 static const struct arm_ext_table armv84a_ext_table
[] =
29933 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29934 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29935 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29936 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29938 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29939 should use the +simd option to turn on FP. */
29940 ARM_REMOVE ("fp", ALL_FP
),
29941 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29942 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29943 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29946 static const struct arm_ext_table armv85a_ext_table
[] =
29948 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29949 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29950 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29951 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29953 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29954 should use the +simd option to turn on FP. */
29955 ARM_REMOVE ("fp", ALL_FP
),
29956 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29959 static const struct arm_ext_table armv8m_main_ext_table
[] =
29961 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29962 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29963 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
29964 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29965 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29968 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
29970 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29971 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29973 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29974 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
29977 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29978 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29979 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
29980 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
29982 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29983 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
29984 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29985 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29988 static const struct arm_ext_table armv8r_ext_table
[] =
29990 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29991 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29992 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29993 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29994 ARM_REMOVE ("fp", ALL_FP
),
29995 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
29996 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29999 /* This list should, at a minimum, contain all the architecture names
30000 recognized by GCC. */
30001 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30002 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30003 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30005 static const struct arm_arch_option_table arm_archs
[] =
30007 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30008 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30009 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30010 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30011 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30012 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30013 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30014 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30015 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30016 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30017 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30018 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30019 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30020 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30021 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30022 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30023 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30024 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30025 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30026 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30027 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30028 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30029 kept to preserve existing behaviour. */
30030 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30031 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30032 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30033 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30034 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30035 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30036 kept to preserve existing behaviour. */
30037 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30038 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30039 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30040 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30041 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30042 /* The official spelling of the ARMv7 profile variants is the dashed form.
30043 Accept the non-dashed form for compatibility with old toolchains. */
30044 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30045 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30046 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30047 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30048 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30049 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30050 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30051 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30052 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30053 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30055 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30057 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30058 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30059 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30060 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30061 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30062 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30063 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30064 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30065 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30066 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30067 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30069 #undef ARM_ARCH_OPT
30071 /* ISA extensions in the co-processor and main instruction set space. */
30073 struct arm_option_extension_value_table
30077 const arm_feature_set merge_value
;
30078 const arm_feature_set clear_value
;
30079 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30080 indicates that an extension is available for all architectures while
30081 ARM_ANY marks an empty entry. */
30082 const arm_feature_set allowed_archs
[2];
30085 /* The following table must be in alphabetical order with a NULL last entry. */
30087 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30088 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30090 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30091 use the context sensitive approach using arm_ext_table's. */
30092 static const struct arm_option_extension_value_table arm_extensions
[] =
30094 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30095 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30096 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30097 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30098 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30099 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30100 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30102 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30103 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30104 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30105 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30106 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30107 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30108 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30110 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30111 | ARM_EXT2_FP16_FML
),
30112 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30113 | ARM_EXT2_FP16_FML
),
30115 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30116 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30117 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30118 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30119 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30120 Thumb divide instruction. Due to this having the same name as the
30121 previous entry, this will be ignored when doing command-line parsing and
30122 only considered by build attribute selection code. */
30123 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30124 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30125 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30126 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30127 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30128 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30129 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30130 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30131 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30132 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30133 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30134 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30135 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30136 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30137 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30138 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30139 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30140 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30141 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30142 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30143 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30145 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30146 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30147 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30148 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30149 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30150 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30151 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30152 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30154 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30155 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30156 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30157 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30158 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30159 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30160 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30161 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30163 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30164 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30165 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30166 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30167 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30171 /* ISA floating-point and Advanced SIMD extensions. */
30172 struct arm_option_fpu_value_table
30175 const arm_feature_set value
;
30178 /* This list should, at a minimum, contain all the fpu names
30179 recognized by GCC. */
30180 static const struct arm_option_fpu_value_table arm_fpus
[] =
30182 {"softfpa", FPU_NONE
},
30183 {"fpe", FPU_ARCH_FPE
},
30184 {"fpe2", FPU_ARCH_FPE
},
30185 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30186 {"fpa", FPU_ARCH_FPA
},
30187 {"fpa10", FPU_ARCH_FPA
},
30188 {"fpa11", FPU_ARCH_FPA
},
30189 {"arm7500fe", FPU_ARCH_FPA
},
30190 {"softvfp", FPU_ARCH_VFP
},
30191 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30192 {"vfp", FPU_ARCH_VFP_V2
},
30193 {"vfp9", FPU_ARCH_VFP_V2
},
30194 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30195 {"vfp10", FPU_ARCH_VFP_V2
},
30196 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30197 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30198 {"vfpv2", FPU_ARCH_VFP_V2
},
30199 {"vfpv3", FPU_ARCH_VFP_V3
},
30200 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30201 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30202 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30203 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30204 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30205 {"arm1020t", FPU_ARCH_VFP_V1
},
30206 {"arm1020e", FPU_ARCH_VFP_V2
},
30207 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30208 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30209 {"maverick", FPU_ARCH_MAVERICK
},
30210 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30211 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30212 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30213 {"vfpv4", FPU_ARCH_VFP_V4
},
30214 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30215 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30216 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30217 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30218 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30219 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30220 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30221 {"crypto-neon-fp-armv8",
30222 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30223 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30224 {"crypto-neon-fp-armv8.1",
30225 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30226 {NULL
, ARM_ARCH_NONE
}
30229 struct arm_option_value_table
30235 static const struct arm_option_value_table arm_float_abis
[] =
30237 {"hard", ARM_FLOAT_ABI_HARD
},
30238 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30239 {"soft", ARM_FLOAT_ABI_SOFT
},
30244 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30245 static const struct arm_option_value_table arm_eabis
[] =
30247 {"gnu", EF_ARM_EABI_UNKNOWN
},
30248 {"4", EF_ARM_EABI_VER4
},
30249 {"5", EF_ARM_EABI_VER5
},
30254 struct arm_long_option_table
30256 const char * option
; /* Substring to match. */
30257 const char * help
; /* Help information. */
30258 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30259 const char * deprecated
; /* If non-null, print this message. */
30263 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30264 arm_feature_set
*ext_set
,
30265 const struct arm_ext_table
*ext_table
)
30267 /* We insist on extensions being specified in alphabetical order, and with
30268 extensions being added before being removed. We achieve this by having
30269 the global ARM_EXTENSIONS table in alphabetical order, and using the
30270 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30271 or removing it (0) and only allowing it to change in the order
30273 const struct arm_option_extension_value_table
* opt
= NULL
;
30274 const arm_feature_set arm_any
= ARM_ANY
;
30275 int adding_value
= -1;
30277 while (str
!= NULL
&& *str
!= 0)
30284 as_bad (_("invalid architectural extension"));
30289 ext
= strchr (str
, '+');
30294 len
= strlen (str
);
30296 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30298 if (adding_value
!= 0)
30301 opt
= arm_extensions
;
30309 if (adding_value
== -1)
30312 opt
= arm_extensions
;
30314 else if (adding_value
!= 1)
30316 as_bad (_("must specify extensions to add before specifying "
30317 "those to remove"));
30324 as_bad (_("missing architectural extension"));
30328 gas_assert (adding_value
!= -1);
30329 gas_assert (opt
!= NULL
);
30331 if (ext_table
!= NULL
)
30333 const struct arm_ext_table
* ext_opt
= ext_table
;
30334 bfd_boolean found
= FALSE
;
30335 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30336 if (ext_opt
->name_len
== len
30337 && strncmp (ext_opt
->name
, str
, len
) == 0)
30341 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30342 /* TODO: Option not supported. When we remove the
30343 legacy table this case should error out. */
30346 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30350 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30351 /* TODO: Option not supported. When we remove the
30352 legacy table this case should error out. */
30354 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30366 /* Scan over the options table trying to find an exact match. */
30367 for (; opt
->name
!= NULL
; opt
++)
30368 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30370 int i
, nb_allowed_archs
=
30371 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30372 /* Check we can apply the extension to this architecture. */
30373 for (i
= 0; i
< nb_allowed_archs
; i
++)
30376 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30378 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30381 if (i
== nb_allowed_archs
)
30383 as_bad (_("extension does not apply to the base architecture"));
30387 /* Add or remove the extension. */
30389 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30391 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30393 /* Allowing Thumb division instructions for ARMv7 in autodetection
30394 rely on this break so that duplicate extensions (extensions
30395 with the same name as a previous extension in the list) are not
30396 considered for command-line parsing. */
30400 if (opt
->name
== NULL
)
30402 /* Did we fail to find an extension because it wasn't specified in
30403 alphabetical order, or because it does not exist? */
30405 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30406 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30409 if (opt
->name
== NULL
)
30410 as_bad (_("unknown architectural extension `%s'"), str
);
30412 as_bad (_("architectural extensions must be specified in "
30413 "alphabetical order"));
30419 /* We should skip the extension we've just matched the next time
30431 arm_parse_cpu (const char *str
)
30433 const struct arm_cpu_option_table
*opt
;
30434 const char *ext
= strchr (str
, '+');
30440 len
= strlen (str
);
30444 as_bad (_("missing cpu name `%s'"), str
);
30448 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
30449 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30451 mcpu_cpu_opt
= &opt
->value
;
30452 if (mcpu_ext_opt
== NULL
)
30453 mcpu_ext_opt
= XNEW (arm_feature_set
);
30454 *mcpu_ext_opt
= opt
->ext
;
30455 mcpu_fpu_opt
= &opt
->default_fpu
;
30456 if (opt
->canonical_name
)
30458 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
30459 strcpy (selected_cpu_name
, opt
->canonical_name
);
30465 if (len
>= sizeof selected_cpu_name
)
30466 len
= (sizeof selected_cpu_name
) - 1;
30468 for (i
= 0; i
< len
; i
++)
30469 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30470 selected_cpu_name
[i
] = 0;
30474 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
30479 as_bad (_("unknown cpu `%s'"), str
);
30484 arm_parse_arch (const char *str
)
30486 const struct arm_arch_option_table
*opt
;
30487 const char *ext
= strchr (str
, '+');
30493 len
= strlen (str
);
30497 as_bad (_("missing architecture name `%s'"), str
);
30501 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
30502 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30504 march_cpu_opt
= &opt
->value
;
30505 if (march_ext_opt
== NULL
)
30506 march_ext_opt
= XNEW (arm_feature_set
);
30507 *march_ext_opt
= arm_arch_none
;
30508 march_fpu_opt
= &opt
->default_fpu
;
30509 strcpy (selected_cpu_name
, opt
->name
);
30512 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
30518 as_bad (_("unknown architecture `%s'\n"), str
);
30523 arm_parse_fpu (const char * str
)
30525 const struct arm_option_fpu_value_table
* opt
;
30527 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30528 if (streq (opt
->name
, str
))
30530 mfpu_opt
= &opt
->value
;
30534 as_bad (_("unknown floating point format `%s'\n"), str
);
30539 arm_parse_float_abi (const char * str
)
30541 const struct arm_option_value_table
* opt
;
30543 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
30544 if (streq (opt
->name
, str
))
30546 mfloat_abi_opt
= opt
->value
;
30550 as_bad (_("unknown floating point abi `%s'\n"), str
);
30556 arm_parse_eabi (const char * str
)
30558 const struct arm_option_value_table
*opt
;
30560 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
30561 if (streq (opt
->name
, str
))
30563 meabi_flags
= opt
->value
;
30566 as_bad (_("unknown EABI `%s'\n"), str
);
30572 arm_parse_it_mode (const char * str
)
30574 bfd_boolean ret
= TRUE
;
30576 if (streq ("arm", str
))
30577 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
30578 else if (streq ("thumb", str
))
30579 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
30580 else if (streq ("always", str
))
30581 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
30582 else if (streq ("never", str
))
30583 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
30586 as_bad (_("unknown implicit IT mode `%s', should be "\
30587 "arm, thumb, always, or never."), str
);
30595 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
30597 codecomposer_syntax
= TRUE
;
30598 arm_comment_chars
[0] = ';';
30599 arm_line_separator_chars
[0] = 0;
30603 struct arm_long_option_table arm_long_opts
[] =
30605 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30606 arm_parse_cpu
, NULL
},
30607 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30608 arm_parse_arch
, NULL
},
30609 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30610 arm_parse_fpu
, NULL
},
30611 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30612 arm_parse_float_abi
, NULL
},
30614 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30615 arm_parse_eabi
, NULL
},
30617 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30618 arm_parse_it_mode
, NULL
},
30619 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30620 arm_ccs_mode
, NULL
},
30621 {NULL
, NULL
, 0, NULL
}
30625 md_parse_option (int c
, const char * arg
)
30627 struct arm_option_table
*opt
;
30628 const struct arm_legacy_option_table
*fopt
;
30629 struct arm_long_option_table
*lopt
;
30635 target_big_endian
= 1;
30641 target_big_endian
= 0;
30645 case OPTION_FIX_V4BX
:
30653 #endif /* OBJ_ELF */
30656 /* Listing option. Just ignore these, we don't support additional
30661 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30663 if (c
== opt
->option
[0]
30664 && ((arg
== NULL
&& opt
->option
[1] == 0)
30665 || streq (arg
, opt
->option
+ 1)))
30667 /* If the option is deprecated, tell the user. */
30668 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
30669 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30670 arg
? arg
: "", _(opt
->deprecated
));
30672 if (opt
->var
!= NULL
)
30673 *opt
->var
= opt
->value
;
30679 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
30681 if (c
== fopt
->option
[0]
30682 && ((arg
== NULL
&& fopt
->option
[1] == 0)
30683 || streq (arg
, fopt
->option
+ 1)))
30685 /* If the option is deprecated, tell the user. */
30686 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
30687 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30688 arg
? arg
: "", _(fopt
->deprecated
));
30690 if (fopt
->var
!= NULL
)
30691 *fopt
->var
= &fopt
->value
;
30697 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30699 /* These options are expected to have an argument. */
30700 if (c
== lopt
->option
[0]
30702 && strncmp (arg
, lopt
->option
+ 1,
30703 strlen (lopt
->option
+ 1)) == 0)
30705 /* If the option is deprecated, tell the user. */
30706 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
30707 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
30708 _(lopt
->deprecated
));
30710 /* Call the sup-option parser. */
30711 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
30722 md_show_usage (FILE * fp
)
30724 struct arm_option_table
*opt
;
30725 struct arm_long_option_table
*lopt
;
30727 fprintf (fp
, _(" ARM-specific assembler options:\n"));
30729 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30730 if (opt
->help
!= NULL
)
30731 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
30733 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30734 if (lopt
->help
!= NULL
)
30735 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
30739 -EB assemble code for a big-endian cpu\n"));
30744 -EL assemble code for a little-endian cpu\n"));
30748 --fix-v4bx Allow BX in ARMv4 code\n"));
30752 --fdpic generate an FDPIC object file\n"));
30753 #endif /* OBJ_ELF */
30761 arm_feature_set flags
;
30762 } cpu_arch_ver_table
;
30764 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30765 chronologically for architectures, with an exception for ARMv6-M and
30766 ARMv6S-M due to legacy reasons. No new architecture should have a
30767 special case. This allows for build attribute selection results to be
30768 stable when new architectures are added. */
30769 static const cpu_arch_ver_table cpu_arch_ver
[] =
30771 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
30772 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
30773 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
30774 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
30775 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
30776 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
30777 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
30778 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
30779 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
30780 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
30781 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
30782 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
30783 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
30784 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
30785 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
30786 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
30787 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
30788 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
30789 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
30790 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
30791 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
30792 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
30793 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
30794 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
30796 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30797 always selected build attributes to match those of ARMv6-M
30798 (resp. ARMv6S-M). However, due to these architectures being a strict
30799 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30800 would be selected when fully respecting chronology of architectures.
30801 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30802 move them before ARMv7 architectures. */
30803 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
30804 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
30806 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
30807 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
30808 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
30809 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
30810 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
30811 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
30812 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
30813 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
30814 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
30815 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
30816 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
30817 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
30818 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
30819 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
30820 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
30821 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
30822 {-1, ARM_ARCH_NONE
}
30825 /* Set an attribute if it has not already been set by the user. */
30828 aeabi_set_attribute_int (int tag
, int value
)
30831 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30832 || !attributes_set_explicitly
[tag
])
30833 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
30837 aeabi_set_attribute_string (int tag
, const char *value
)
30840 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30841 || !attributes_set_explicitly
[tag
])
30842 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
30845 /* Return whether features in the *NEEDED feature set are available via
30846 extensions for the architecture whose feature set is *ARCH_FSET. */
30849 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
30850 const arm_feature_set
*needed
)
30852 int i
, nb_allowed_archs
;
30853 arm_feature_set ext_fset
;
30854 const struct arm_option_extension_value_table
*opt
;
30856 ext_fset
= arm_arch_none
;
30857 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30859 /* Extension does not provide any feature we need. */
30860 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
30864 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30865 for (i
= 0; i
< nb_allowed_archs
; i
++)
30868 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
30871 /* Extension is available, add it. */
30872 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
30873 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
30877 /* Can we enable all features in *needed? */
30878 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
30881 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30882 a given architecture feature set *ARCH_EXT_FSET including extension feature
30883 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30884 - if true, check for an exact match of the architecture modulo extensions;
30885 - otherwise, select build attribute value of the first superset
30886 architecture released so that results remains stable when new architectures
30888 For -march/-mcpu=all the build attribute value of the most featureful
30889 architecture is returned. Tag_CPU_arch_profile result is returned in
30893 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
30894 const arm_feature_set
*ext_fset
,
30895 char *profile
, int exact_match
)
30897 arm_feature_set arch_fset
;
30898 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
30900 /* Select most featureful architecture with all its extensions if building
30901 for -march=all as the feature sets used to set build attributes. */
30902 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
30904 /* Force revisiting of decision for each new architecture. */
30905 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30907 return TAG_CPU_ARCH_V8
;
30910 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
30912 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
30914 arm_feature_set known_arch_fset
;
30916 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
30919 /* Base architecture match user-specified architecture and
30920 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30921 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
30926 /* Base architecture match user-specified architecture only
30927 (eg. ARMv6-M in the same case as above). Record it in case we
30928 find a match with above condition. */
30929 else if (p_ver_ret
== NULL
30930 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
30936 /* Architecture has all features wanted. */
30937 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
30939 arm_feature_set added_fset
;
30941 /* Compute features added by this architecture over the one
30942 recorded in p_ver_ret. */
30943 if (p_ver_ret
!= NULL
)
30944 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
30946 /* First architecture that match incl. with extensions, or the
30947 only difference in features over the recorded match is
30948 features that were optional and are now mandatory. */
30949 if (p_ver_ret
== NULL
30950 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
30956 else if (p_ver_ret
== NULL
)
30958 arm_feature_set needed_ext_fset
;
30960 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
30962 /* Architecture has all features needed when using some
30963 extensions. Record it and continue searching in case there
30964 exist an architecture providing all needed features without
30965 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30967 if (have_ext_for_needed_feat_p (&known_arch_fset
,
30974 if (p_ver_ret
== NULL
)
30978 /* Tag_CPU_arch_profile. */
30979 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
30980 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
30981 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
30982 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
30984 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
30986 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
30990 return p_ver_ret
->val
;
30993 /* Set the public EABI object attributes. */
30996 aeabi_set_public_attributes (void)
30998 char profile
= '\0';
31001 int fp16_optional
= 0;
31002 int skip_exact_match
= 0;
31003 arm_feature_set flags
, flags_arch
, flags_ext
;
31005 /* Autodetection mode, choose the architecture based the instructions
31007 if (no_cpu_selected ())
31009 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31011 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31012 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31014 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31015 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31017 /* Code run during relaxation relies on selected_cpu being set. */
31018 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31019 flags_ext
= arm_arch_none
;
31020 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31021 selected_ext
= flags_ext
;
31022 selected_cpu
= flags
;
31024 /* Otherwise, choose the architecture based on the capabilities of the
31028 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31029 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31030 flags_ext
= selected_ext
;
31031 flags
= selected_cpu
;
31033 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31035 /* Allow the user to override the reported architecture. */
31036 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31038 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31039 flags_ext
= arm_arch_none
;
31042 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31044 /* When this function is run again after relaxation has happened there is no
31045 way to determine whether an architecture or CPU was specified by the user:
31046 - selected_cpu is set above for relaxation to work;
31047 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31048 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31049 Therefore, if not in -march=all case we first try an exact match and fall
31050 back to autodetection. */
31051 if (!skip_exact_match
)
31052 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31054 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31056 as_bad (_("no architecture contains all the instructions used\n"));
31058 /* Tag_CPU_name. */
31059 if (selected_cpu_name
[0])
31063 q
= selected_cpu_name
;
31064 if (strncmp (q
, "armv", 4) == 0)
31069 for (i
= 0; q
[i
]; i
++)
31070 q
[i
] = TOUPPER (q
[i
]);
31072 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31075 /* Tag_CPU_arch. */
31076 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31078 /* Tag_CPU_arch_profile. */
31079 if (profile
!= '\0')
31080 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31082 /* Tag_DSP_extension. */
31083 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31084 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31086 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31087 /* Tag_ARM_ISA_use. */
31088 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31089 || ARM_FEATURE_ZERO (flags_arch
))
31090 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31092 /* Tag_THUMB_ISA_use. */
31093 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31094 || ARM_FEATURE_ZERO (flags_arch
))
31098 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31099 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31101 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31105 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31108 /* Tag_VFP_arch. */
31109 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31110 aeabi_set_attribute_int (Tag_VFP_arch
,
31111 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31113 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31114 aeabi_set_attribute_int (Tag_VFP_arch
,
31115 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31117 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31120 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31122 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31124 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31127 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31128 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31129 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31130 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31131 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31133 /* Tag_ABI_HardFP_use. */
31134 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31135 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31136 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31138 /* Tag_WMMX_arch. */
31139 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31140 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31141 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31142 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31144 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31145 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31146 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31147 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31148 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31149 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31151 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31153 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31157 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31162 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31163 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31164 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31165 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31167 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31168 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31169 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31173 We set Tag_DIV_use to two when integer divide instructions have been used
31174 in ARM state, or when Thumb integer divide instructions have been used,
31175 but we have no architecture profile set, nor have we any ARM instructions.
31177 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31178 by the base architecture.
31180 For new architectures we will have to check these tests. */
31181 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31182 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31183 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31184 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31185 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31186 || (profile
== '\0'
31187 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31188 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31189 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31191 /* Tag_MP_extension_use. */
31192 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31193 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31195 /* Tag Virtualization_use. */
31196 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31198 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31201 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31204 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31205 finished and free extension feature bits which will not be used anymore. */
31208 arm_md_post_relax (void)
31210 aeabi_set_public_attributes ();
31211 XDELETE (mcpu_ext_opt
);
31212 mcpu_ext_opt
= NULL
;
31213 XDELETE (march_ext_opt
);
31214 march_ext_opt
= NULL
;
31217 /* Add the default contents for the .ARM.attributes section. */
31222 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31225 aeabi_set_public_attributes ();
31227 #endif /* OBJ_ELF */
31229 /* Parse a .cpu directive. */
31232 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31234 const struct arm_cpu_option_table
*opt
;
31238 name
= input_line_pointer
;
31239 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31240 input_line_pointer
++;
31241 saved_char
= *input_line_pointer
;
31242 *input_line_pointer
= 0;
31244 /* Skip the first "all" entry. */
31245 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31246 if (streq (opt
->name
, name
))
31248 selected_arch
= opt
->value
;
31249 selected_ext
= opt
->ext
;
31250 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31251 if (opt
->canonical_name
)
31252 strcpy (selected_cpu_name
, opt
->canonical_name
);
31256 for (i
= 0; opt
->name
[i
]; i
++)
31257 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31259 selected_cpu_name
[i
] = 0;
31261 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31263 *input_line_pointer
= saved_char
;
31264 demand_empty_rest_of_line ();
31267 as_bad (_("unknown cpu `%s'"), name
);
31268 *input_line_pointer
= saved_char
;
31269 ignore_rest_of_line ();
31272 /* Parse a .arch directive. */
31275 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31277 const struct arm_arch_option_table
*opt
;
31281 name
= input_line_pointer
;
31282 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31283 input_line_pointer
++;
31284 saved_char
= *input_line_pointer
;
31285 *input_line_pointer
= 0;
31287 /* Skip the first "all" entry. */
31288 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31289 if (streq (opt
->name
, name
))
31291 selected_arch
= opt
->value
;
31292 selected_ext
= arm_arch_none
;
31293 selected_cpu
= selected_arch
;
31294 strcpy (selected_cpu_name
, opt
->name
);
31295 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31296 *input_line_pointer
= saved_char
;
31297 demand_empty_rest_of_line ();
31301 as_bad (_("unknown architecture `%s'\n"), name
);
31302 *input_line_pointer
= saved_char
;
31303 ignore_rest_of_line ();
31306 /* Parse a .object_arch directive. */
31309 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31311 const struct arm_arch_option_table
*opt
;
31315 name
= input_line_pointer
;
31316 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31317 input_line_pointer
++;
31318 saved_char
= *input_line_pointer
;
31319 *input_line_pointer
= 0;
31321 /* Skip the first "all" entry. */
31322 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31323 if (streq (opt
->name
, name
))
31325 selected_object_arch
= opt
->value
;
31326 *input_line_pointer
= saved_char
;
31327 demand_empty_rest_of_line ();
31331 as_bad (_("unknown architecture `%s'\n"), name
);
31332 *input_line_pointer
= saved_char
;
31333 ignore_rest_of_line ();
31336 /* Parse a .arch_extension directive. */
31339 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31341 const struct arm_option_extension_value_table
*opt
;
31344 int adding_value
= 1;
31346 name
= input_line_pointer
;
31347 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31348 input_line_pointer
++;
31349 saved_char
= *input_line_pointer
;
31350 *input_line_pointer
= 0;
31352 if (strlen (name
) >= 2
31353 && strncmp (name
, "no", 2) == 0)
31359 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31360 if (streq (opt
->name
, name
))
31362 int i
, nb_allowed_archs
=
31363 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31364 for (i
= 0; i
< nb_allowed_archs
; i
++)
31367 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31369 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31373 if (i
== nb_allowed_archs
)
31375 as_bad (_("architectural extension `%s' is not allowed for the "
31376 "current base architecture"), name
);
31381 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31384 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31386 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31387 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31388 *input_line_pointer
= saved_char
;
31389 demand_empty_rest_of_line ();
31390 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31391 on this return so that duplicate extensions (extensions with the
31392 same name as a previous extension in the list) are not considered
31393 for command-line parsing. */
31397 if (opt
->name
== NULL
)
31398 as_bad (_("unknown architecture extension `%s'\n"), name
);
31400 *input_line_pointer
= saved_char
;
31401 ignore_rest_of_line ();
31404 /* Parse a .fpu directive. */
31407 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
31409 const struct arm_option_fpu_value_table
*opt
;
31413 name
= input_line_pointer
;
31414 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31415 input_line_pointer
++;
31416 saved_char
= *input_line_pointer
;
31417 *input_line_pointer
= 0;
31419 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31420 if (streq (opt
->name
, name
))
31422 selected_fpu
= opt
->value
;
31423 #ifndef CPU_DEFAULT
31424 if (no_cpu_selected ())
31425 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
31428 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31429 *input_line_pointer
= saved_char
;
31430 demand_empty_rest_of_line ();
31434 as_bad (_("unknown floating point format `%s'\n"), name
);
31435 *input_line_pointer
= saved_char
;
31436 ignore_rest_of_line ();
31439 /* Copy symbol information. */
31442 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
31444 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
31448 /* Given a symbolic attribute NAME, return the proper integer value.
31449 Returns -1 if the attribute is not known. */
31452 arm_convert_symbolic_attribute (const char *name
)
31454 static const struct
31459 attribute_table
[] =
31461 /* When you modify this table you should
31462 also modify the list in doc/c-arm.texi. */
31463 #define T(tag) {#tag, tag}
31464 T (Tag_CPU_raw_name
),
31467 T (Tag_CPU_arch_profile
),
31468 T (Tag_ARM_ISA_use
),
31469 T (Tag_THUMB_ISA_use
),
31473 T (Tag_Advanced_SIMD_arch
),
31474 T (Tag_PCS_config
),
31475 T (Tag_ABI_PCS_R9_use
),
31476 T (Tag_ABI_PCS_RW_data
),
31477 T (Tag_ABI_PCS_RO_data
),
31478 T (Tag_ABI_PCS_GOT_use
),
31479 T (Tag_ABI_PCS_wchar_t
),
31480 T (Tag_ABI_FP_rounding
),
31481 T (Tag_ABI_FP_denormal
),
31482 T (Tag_ABI_FP_exceptions
),
31483 T (Tag_ABI_FP_user_exceptions
),
31484 T (Tag_ABI_FP_number_model
),
31485 T (Tag_ABI_align_needed
),
31486 T (Tag_ABI_align8_needed
),
31487 T (Tag_ABI_align_preserved
),
31488 T (Tag_ABI_align8_preserved
),
31489 T (Tag_ABI_enum_size
),
31490 T (Tag_ABI_HardFP_use
),
31491 T (Tag_ABI_VFP_args
),
31492 T (Tag_ABI_WMMX_args
),
31493 T (Tag_ABI_optimization_goals
),
31494 T (Tag_ABI_FP_optimization_goals
),
31495 T (Tag_compatibility
),
31496 T (Tag_CPU_unaligned_access
),
31497 T (Tag_FP_HP_extension
),
31498 T (Tag_VFP_HP_extension
),
31499 T (Tag_ABI_FP_16bit_format
),
31500 T (Tag_MPextension_use
),
31502 T (Tag_nodefaults
),
31503 T (Tag_also_compatible_with
),
31504 T (Tag_conformance
),
31506 T (Tag_Virtualization_use
),
31507 T (Tag_DSP_extension
),
31509 /* We deliberately do not include Tag_MPextension_use_legacy. */
31517 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
31518 if (streq (name
, attribute_table
[i
].name
))
31519 return attribute_table
[i
].tag
;
31524 /* Apply sym value for relocations only in the case that they are for
31525 local symbols in the same segment as the fixup and you have the
31526 respective architectural feature for blx and simple switches. */
31529 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
31532 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
31533 /* PR 17444: If the local symbol is in a different section then a reloc
31534 will always be generated for it, so applying the symbol value now
31535 will result in a double offset being stored in the relocation. */
31536 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
31537 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
31539 switch (fixP
->fx_r_type
)
31541 case BFD_RELOC_ARM_PCREL_BLX
:
31542 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
31543 if (ARM_IS_FUNC (fixP
->fx_addsy
))
31547 case BFD_RELOC_ARM_PCREL_CALL
:
31548 case BFD_RELOC_THUMB_PCREL_BLX
:
31549 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
31560 #endif /* OBJ_ELF */