1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
369 static int mfloat_abi_opt
= -1;
370 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
372 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
373 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
375 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
376 /* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
379 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
380 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
381 static arm_feature_set selected_fpu
= FPU_NONE
;
382 /* Feature bits selected by the last .object_arch directive. */
383 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
384 /* Must be long enough to hold any of the names in arm_cpus. */
385 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
386 static char selected_cpu_name
[20];
388 extern FLONUM_TYPE generic_floating_point_number
;
390 /* Return if no cpu was selected on command-line. */
392 no_cpu_selected (void)
394 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
399 static int meabi_flags
= EABI_DEFAULT
;
401 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
404 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
409 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
414 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415 symbolS
* GOT_symbol
;
418 /* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
422 static int thumb_mode
= 0;
423 /* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426 #define MODE_RECORDED (1 << 4)
428 /* Specifies the intrinsic IT insn behavior mode. */
429 enum implicit_it_mode
431 IMPLICIT_IT_MODE_NEVER
= 0x00,
432 IMPLICIT_IT_MODE_ARM
= 0x01,
433 IMPLICIT_IT_MODE_THUMB
= 0x02,
434 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
436 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
438 /* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
450 Important differences from the old Thumb mode:
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
461 static bfd_boolean unified_syntax
= FALSE
;
463 /* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467 const char arm_symbol_chars
[] = "#[]{}";
483 enum neon_el_type type
;
487 #define NEON_MAX_TYPE_ELS 5
491 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
495 enum pred_instruction_type
501 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN
, /* The IT insn has been parsed. */
506 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
512 /* The maximum number of operands we need. */
513 #define ARM_IT_MAX_OPERANDS 6
514 #define ARM_IT_MAX_RELOCS 3
519 unsigned long instruction
;
521 unsigned int size_req
;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1u if nothing is
526 unsigned int uncond_value
;
527 struct neon_type vectype
;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
536 bfd_reloc_code_real_type type
;
539 } relocs
[ARM_IT_MAX_RELOCS
];
541 enum pred_instruction_type pred_insn_type
;
547 struct neon_type_el vectype
;
548 unsigned present
: 1; /* Operand present. */
549 unsigned isreg
: 1; /* Operand was a register. */
550 unsigned immisreg
: 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
556 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad
: 1; /* Operand is SIMD quad register. */
563 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
564 unsigned iszr
: 1; /* Operand is ZR register. */
565 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
566 unsigned writeback
: 1; /* Operand has trailing ! */
567 unsigned preind
: 1; /* Preindexed address. */
568 unsigned postind
: 1; /* Postindexed address. */
569 unsigned negative
: 1; /* Index register was negated. */
570 unsigned shifted
: 1; /* Shift applied to operation. */
571 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
572 } operands
[ARM_IT_MAX_OPERANDS
];
575 static struct arm_it inst
;
577 #define NUM_FLOAT_VALS 8
579 const char * fp_const
[] =
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
594 #define CP_T_X 0x00008000
595 #define CP_T_Y 0x00400000
597 #define CONDS_BIT 0x00100000
598 #define LOAD_BIT 0x00100000
600 #define DOUBLE_LOAD_FLAG 0x00000001
604 const char * template_name
;
608 #define COND_ALWAYS 0xE
612 const char * template_name
;
616 struct asm_barrier_opt
618 const char * template_name
;
620 const arm_feature_set arch
;
623 /* The bit that distinguishes CPSR and SPSR. */
624 #define SPSR_BIT (1 << 22)
626 /* The individual PSR flag bits. */
627 #define PSR_c (1 << 16)
628 #define PSR_x (1 << 17)
629 #define PSR_s (1 << 18)
630 #define PSR_f (1 << 19)
635 bfd_reloc_code_real_type reloc
;
640 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
641 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
646 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
649 /* Bits for DEFINED field in neon_typed_alias. */
650 #define NTA_HASTYPE 1
651 #define NTA_HASINDEX 2
653 struct neon_typed_alias
655 unsigned char defined
;
657 struct neon_type_el eltype
;
660 /* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
692 /* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
701 unsigned char builtin
;
702 struct neon_typed_alias
* neon
;
705 /* Diagnostics used when we don't get a register of the expected type. */
706 const char * const reg_expected_msgs
[] =
708 [REG_TYPE_RN
] = N_("ARM register expected"),
709 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN
] = N_("co-processor register expected"),
711 [REG_TYPE_FN
] = N_("FPA register expected"),
712 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
720 [REG_TYPE_VFC
] = N_("VFP system register expected"),
721 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 /* Some well known registers that we refer to directly elsewhere. */
741 /* ARM instructions take 4bytes in the object file, Thumb instructions
747 /* Basic string to match. */
748 const char * template_name
;
750 /* Parameters to instruction. */
751 unsigned int operands
[8];
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag
: 4;
756 /* Basic instruction code. */
759 /* Thumb-format instruction code. */
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set
* avariant
;
764 const arm_feature_set
* tvariant
;
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode
) (void);
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode
) (void);
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred
: 1;
776 /* Defines for various bits that we will want to toggle. */
777 #define INST_IMMEDIATE 0x02000000
778 #define OFFSET_REG 0x02000000
779 #define HWOFFSET_IMM 0x00400000
780 #define SHIFT_BY_REG 0x00000010
781 #define PRE_INDEX 0x01000000
782 #define INDEX_UP 0x00800000
783 #define WRITE_BACK 0x00200000
784 #define LDM_TYPE_2_OR_3 0x00400000
785 #define CPSI_MMOD 0x00020000
787 #define LITERAL_MASK 0xf000f000
788 #define OPCODE_MASK 0xfe1fffff
789 #define V4_STR_BIT 0x00000020
790 #define VLDR_VMOV_SAME 0x0040f000
792 #define T2_SUBS_PC_LR 0xf3de8f00
794 #define DATA_OP_SHIFT 21
795 #define SBIT_SHIFT 20
797 #define T2_OPCODE_MASK 0xfe1fffff
798 #define T2_DATA_OP_SHIFT 21
799 #define T2_SBIT_SHIFT 20
801 #define A_COND_MASK 0xf0000000
802 #define A_PUSH_POP_OP_MASK 0x0fff0000
804 /* Opcodes for pushing/poping registers to/from the stack. */
805 #define A1_OPCODE_PUSH 0x092d0000
806 #define A2_OPCODE_PUSH 0x052d0004
807 #define A2_OPCODE_POP 0x049d0004
809 /* Codes to distinguish the arithmetic instructions. */
820 #define OPCODE_CMP 10
821 #define OPCODE_CMN 11
822 #define OPCODE_ORR 12
823 #define OPCODE_MOV 13
824 #define OPCODE_BIC 14
825 #define OPCODE_MVN 15
827 #define T2_OPCODE_AND 0
828 #define T2_OPCODE_BIC 1
829 #define T2_OPCODE_ORR 2
830 #define T2_OPCODE_ORN 3
831 #define T2_OPCODE_EOR 4
832 #define T2_OPCODE_ADD 8
833 #define T2_OPCODE_ADC 10
834 #define T2_OPCODE_SBC 11
835 #define T2_OPCODE_SUB 13
836 #define T2_OPCODE_RSB 14
838 #define T_OPCODE_MUL 0x4340
839 #define T_OPCODE_TST 0x4200
840 #define T_OPCODE_CMN 0x42c0
841 #define T_OPCODE_NEG 0x4240
842 #define T_OPCODE_MVN 0x43c0
844 #define T_OPCODE_ADD_R3 0x1800
845 #define T_OPCODE_SUB_R3 0x1a00
846 #define T_OPCODE_ADD_HI 0x4400
847 #define T_OPCODE_ADD_ST 0xb000
848 #define T_OPCODE_SUB_ST 0xb080
849 #define T_OPCODE_ADD_SP 0xa800
850 #define T_OPCODE_ADD_PC 0xa000
851 #define T_OPCODE_ADD_I8 0x3000
852 #define T_OPCODE_SUB_I8 0x3800
853 #define T_OPCODE_ADD_I3 0x1c00
854 #define T_OPCODE_SUB_I3 0x1e00
856 #define T_OPCODE_ASR_R 0x4100
857 #define T_OPCODE_LSL_R 0x4080
858 #define T_OPCODE_LSR_R 0x40c0
859 #define T_OPCODE_ROR_R 0x41c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe000
891 #define THUMB_SIZE 2 /* Size of thumb instruction. */
892 #define THUMB_PP_PC_LR 0x0100
893 #define THUMB_LOAD_BIT 0x0800
894 #define THUMB2_LOAD_BIT 0x00100000
896 #define BAD_SYNTAX _("syntax error")
897 #define BAD_ARGS _("bad arguments to instruction")
898 #define BAD_SP _("r13 not allowed here")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_ODD _("Odd register not allowed here")
901 #define BAD_EVEN _("Even register not allowed here")
902 #define BAD_COND _("instruction cannot be conditional")
903 #define BAD_OVERLAP _("registers may not be the same")
904 #define BAD_HIREG _("lo register required")
905 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907 #define BAD_BRANCH _("branch must be last instruction in IT block")
908 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909 #define BAD_NO_VPT _("instruction not allowed in VPT block")
910 #define BAD_NOT_IT _("instruction not allowed in IT block")
911 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912 #define BAD_FPU _("selected FPU does not support instruction")
913 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914 #define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916 #define BAD_IT_COND _("incorrect condition in IT block")
917 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
919 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920 #define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922 #define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924 #define BAD_RANGE _("branch out of range")
925 #define BAD_FP16 _("selected processor does not support fp16 instruction")
926 #define BAD_BF16 _("selected processor does not support bf16 instruction")
927 #define BAD_CDE _("selected processor does not support cde instruction")
928 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
933 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
935 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
937 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
939 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940 #define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945 #define BAD_EL_TYPE _("bad element type for instruction")
946 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
948 static htab_t arm_ops_hsh
;
949 static htab_t arm_cond_hsh
;
950 static htab_t arm_vcond_hsh
;
951 static htab_t arm_shift_hsh
;
952 static htab_t arm_psr_hsh
;
953 static htab_t arm_v7m_psr_hsh
;
954 static htab_t arm_reg_hsh
;
955 static htab_t arm_reloc_hsh
;
956 static htab_t arm_barrier_opt_hsh
;
958 /* Stuff needed to resolve the label ambiguity
967 symbolS
* last_label_seen
;
968 static int label_is_thumb_function_name
= FALSE
;
970 /* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
973 #define MAX_LITERAL_POOL_SIZE 1024
974 typedef struct literal_pool
976 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
977 unsigned int next_free_entry
;
983 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
985 struct literal_pool
* next
;
986 unsigned int alignment
;
989 /* Pointer to a linked list of literal pools. */
990 literal_pool
* list_of_pools
= NULL
;
992 typedef enum asmfunc_states
995 WAITING_ASMFUNC_NAME
,
999 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1002 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1004 static struct current_pred now_pred
;
1008 now_pred_compatible (int cond
)
1010 return (cond
& ~1) == (now_pred
.cc
& ~1);
1014 conditional_insn (void)
1016 return inst
.cond
!= COND_ALWAYS
;
1019 static int in_pred_block (void);
1021 static int handle_pred_state (void);
1023 static void force_automatic_it_block_close (void);
1025 static void it_fsm_post_encode (void);
1027 #define set_pred_insn_type(type) \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1036 #define set_pred_insn_type_nonvoid(type, failret) \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1045 #define set_pred_insn_type_last() \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1055 /* Toggle value[pos]. */
1056 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1060 /* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062 char arm_comment_chars
[] = "@";
1064 /* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067 /* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070 /* Also note that comments like this one will always work. */
1071 const char line_comment_chars
[] = "#";
1073 char arm_line_separator_chars
[] = ";";
1075 /* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077 const char EXP_CHARS
[] = "eE";
1079 /* Chars that mean this number is a floating point constant. */
1080 /* As in 0f12.456 */
1081 /* or 0d1.2345e12 */
1083 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1085 /* Prefix characters that indicate the start of an immediate
1087 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1089 /* Separator character handling. */
1091 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1093 enum fp_16bit_format
1095 ARM_FP16_FORMAT_IEEE
= 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1097 ARM_FP16_FORMAT_DEFAULT
= 0x3
1100 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1104 skip_past_char (char ** str
, char c
)
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str
);
1118 #define skip_past_comma(str) skip_past_char (str, ',')
1120 /* Arithmetic expressions (possibly involving symbols). */
1122 /* Return TRUE if anything in the expression is a bignum. */
1125 walk_no_bignums (symbolS
* sp
)
1127 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1130 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 || (symbol_get_value_expression (sp
)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1140 static bfd_boolean in_my_get_expression
= FALSE
;
1142 /* Third argument to my_get_expression. */
1143 #define GE_NO_PREFIX 0
1144 #define GE_IMM_PREFIX 1
1145 #define GE_OPT_PREFIX 2
1146 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148 #define GE_OPT_PREFIX_BIG 3
1151 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1155 /* In unified syntax, all prefixes are optional. */
1157 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1160 switch (prefix_mode
)
1162 case GE_NO_PREFIX
: break;
1164 if (!is_immediate_prefix (**str
))
1166 inst
.error
= _("immediate expression requires a # prefix");
1172 case GE_OPT_PREFIX_BIG
:
1173 if (is_immediate_prefix (**str
))
1180 memset (ep
, 0, sizeof (expressionS
));
1182 save_in
= input_line_pointer
;
1183 input_line_pointer
= *str
;
1184 in_my_get_expression
= TRUE
;
1186 in_my_get_expression
= FALSE
;
1188 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str
= input_line_pointer
;
1192 input_line_pointer
= save_in
;
1193 if (inst
.error
== NULL
)
1194 inst
.error
= (ep
->X_op
== O_absent
1195 ? _("missing expression") :_("bad expression"));
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1203 && (ep
->X_op
== O_big
1204 || (ep
->X_add_symbol
1205 && (walk_no_bignums (ep
->X_add_symbol
)
1207 && walk_no_bignums (ep
->X_op_symbol
))))))
1209 inst
.error
= _("invalid constant");
1210 *str
= input_line_pointer
;
1211 input_line_pointer
= save_in
;
1215 *str
= input_line_pointer
;
1216 input_line_pointer
= save_in
;
1220 /* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1235 md_atof (int type
, char * litP
, int * sizeP
)
1238 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1254 FLONUM_TYPE generic_float
;
1256 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1259 input_line_pointer
= t
;
1261 return _("invalid floating point number");
1263 switch (generic_float
.sign
)
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1291 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1321 return _("Unrecognized or unsupported floating point constant");
1324 t
= atof_ieee (input_line_pointer
, type
, words
);
1326 input_line_pointer
= t
;
1327 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1329 if (target_big_endian
|| prec
== 1)
1330 for (i
= 0; i
< prec
; i
++)
1332 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1333 litP
+= sizeof (LITTLENUM_TYPE
);
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1336 for (i
= prec
- 1; i
>= 0; i
--)
1338 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1339 litP
+= sizeof (LITTLENUM_TYPE
);
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i
= 0; i
< prec
; i
+= 2)
1346 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1347 sizeof (LITTLENUM_TYPE
));
1348 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1349 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1350 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1356 /* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1360 md_operand (expressionS
* exp
)
1362 if (in_my_get_expression
)
1363 exp
->X_op
= O_illegal
;
1366 /* Immediate values. */
1369 /* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1374 immediate_for_directive (int *val
)
1377 exp
.X_op
= O_illegal
;
1379 if (is_immediate_prefix (*input_line_pointer
))
1381 input_line_pointer
++;
1385 if (exp
.X_op
!= O_constant
)
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1391 *val
= exp
.X_add_number
;
1396 /* Register parsing. */
1398 /* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1403 static struct reg_entry
*
1404 arm_reg_parse_multi (char **ccp
)
1408 struct reg_entry
*reg
;
1410 skip_whitespace (start
);
1412 #ifdef REGISTER_PREFIX
1413 if (*start
!= REGISTER_PREFIX
)
1417 #ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1423 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1428 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1430 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1440 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1441 enum arm_reg_type type
)
1443 /* Alternative syntaxes are accepted for a few register classes. */
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg
&& reg
->type
== REG_TYPE_CN
)
1456 /* For backward compatibility, a bare number is valid here. */
1458 unsigned long processor
= strtoul (start
, ccp
, 10);
1459 if (*ccp
!= start
&& processor
<= 15)
1464 case REG_TYPE_MMXWC
:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1478 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1482 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1485 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1492 if (reg
&& reg
->type
== type
)
1495 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1502 /* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1510 Can all be legally parsed by this function.
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1517 parse_neon_type (struct neon_type
*type
, char **str
)
1524 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1526 enum neon_el_type thistype
= NT_untyped
;
1527 unsigned thissize
= -1u;
1534 /* Just a size without an explicit type. */
1538 switch (TOLOWER (*ptr
))
1540 case 'i': thistype
= NT_integer
; break;
1541 case 'f': thistype
= NT_float
; break;
1542 case 'p': thistype
= NT_poly
; break;
1543 case 's': thistype
= NT_signed
; break;
1544 case 'u': thistype
= NT_unsigned
; break;
1546 thistype
= NT_float
;
1551 thistype
= NT_bfloat
;
1552 switch (TOLOWER (*(++ptr
)))
1556 thissize
= strtoul (ptr
, &ptr
, 10);
1559 as_bad (_("bad size %d in type specifier"), thissize
);
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1585 thissize
= strtoul (ptr
, &ptr
, 10);
1587 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1590 as_bad (_("bad size %d in type specifier"), thissize
);
1598 type
->el
[type
->elems
].type
= thistype
;
1599 type
->el
[type
->elems
].size
= thissize
;
1604 /* Empty/missing type is not a successful parse. */
1605 if (type
->elems
== 0)
1613 /* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1619 first_error (const char *err
)
1625 /* Parse a single type, e.g. ".s32", leading period included. */
1627 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1630 struct neon_type optype
;
1634 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1636 if (optype
.elems
== 1)
1637 *vectype
= optype
.el
[0];
1640 first_error (_("only one type should be specified for operand"));
1646 first_error (_("vector type expected"));
1658 /* Special meanings for indices (which have a range of 0-7), which will fit into
1661 #define NEON_ALL_LANES 15
1662 #define NEON_INTERLEAVE_LANES 14
1664 /* Record a use of the given feature. */
1666 record_feature_use (const arm_feature_set
*feature
)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1674 /* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1677 mark_feature_used (const arm_feature_set
*feature
)
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1682 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1683 && ARM_CPU_IS_ANY (cpu_variant
))
1685 first_error (BAD_MVE_AUTO
);
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1692 /* Add the appropriate architecture feature for the barrier option used.
1694 record_feature_use (feature
);
1699 /* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1705 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1706 enum arm_reg_type
*rtype
,
1707 struct neon_typed_alias
*typeinfo
)
1710 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1711 struct neon_typed_alias atype
;
1712 struct neon_type_el parsetype
;
1716 atype
.eltype
.type
= NT_invtype
;
1717 atype
.eltype
.size
= -1;
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1723 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type
== REG_TYPE_NDQ
1733 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1734 || (type
== REG_TYPE_VFSD
1735 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1736 || (type
== REG_TYPE_NSDQ
1737 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1738 || reg
->type
== REG_TYPE_NQ
))
1739 || (type
== REG_TYPE_NSD
1740 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1741 || (type
== REG_TYPE_MMXWC
1742 && (reg
->type
== REG_TYPE_MMXWCG
)))
1743 type
= (enum arm_reg_type
) reg
->type
;
1745 if (type
== REG_TYPE_MQ
)
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1750 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1753 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1755 first_error (_("expected MVE register [q0..q7]"));
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1761 && (type
== REG_TYPE_NQ
))
1765 if (type
!= reg
->type
)
1771 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1773 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1775 first_error (_("can't redefine type for operand"));
1778 atype
.defined
|= NTA_HASTYPE
;
1779 atype
.eltype
= parsetype
;
1782 if (skip_past_char (&str
, '[') == SUCCESS
)
1784 if (type
!= REG_TYPE_VFD
1785 && !(type
== REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1787 && !(type
== REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1791 first_error (_("only D and Q registers may be indexed"));
1793 first_error (_("only D registers may be indexed"));
1797 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1799 first_error (_("can't change index for operand"));
1803 atype
.defined
|= NTA_HASINDEX
;
1805 if (skip_past_char (&str
, ']') == SUCCESS
)
1806 atype
.index
= NEON_ALL_LANES
;
1811 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1813 if (exp
.X_op
!= O_constant
)
1815 first_error (_("constant expression required"));
1819 if (skip_past_char (&str
, ']') == FAIL
)
1822 atype
.index
= exp
.X_add_number
;
1837 /* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1845 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1846 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1848 struct neon_typed_alias atype
;
1850 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1855 /* Do not allow regname(... to parse as a register. */
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1862 first_error (_("register operand expected, but got scalar"));
1867 *vectype
= atype
.eltype
;
1874 #define NEON_SCALAR_REG(X) ((X) >> 4)
1875 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1877 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1882 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1883 arm_reg_type reg_type
)
1887 struct neon_typed_alias atype
;
1890 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1908 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1911 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1913 first_error (_("scalar must have an index"));
1916 else if (atype
.index
>= reg_size
/ elsize
)
1918 first_error (_("scalar index out of range"));
1923 *type
= atype
.eltype
;
1927 return reg
* 16 + atype
.index
;
1930 /* Types of registers in a list. */
1943 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1946 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1952 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1957 skip_whitespace (str
);
1970 const char apsr_str
[] = "apsr";
1971 int apsr_str_len
= strlen (apsr_str
);
1973 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1974 if (etype
== REGLIST_CLRM
)
1976 if (reg
== REG_SP
|| reg
== REG_PC
)
1978 else if (reg
== FAIL
1979 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1980 && !ISALPHA (*(str
+ apsr_str_len
)))
1983 str
+= apsr_str_len
;
1988 first_error (_("r0-r12, lr or APSR expected"));
1992 else /* etype == REGLIST_RN. */
1996 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2007 first_error (_("bad range in register list"));
2011 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2013 if (range
& (1 << i
))
2015 (_("Warning: duplicated register (r%d) in register list"),
2023 if (range
& (1 << reg
))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2026 else if (reg
<= cur_reg
)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2032 while (skip_past_comma (&str
) != FAIL
2033 || (in_range
= 1, *str
++ == '-'));
2036 if (skip_past_char (&str
, '}') == FAIL
)
2038 first_error (_("missing `}'"));
2042 else if (etype
== REGLIST_RN
)
2046 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2049 if (exp
.X_op
== O_constant
)
2051 if (exp
.X_add_number
2052 != (exp
.X_add_number
& 0x0000ffff))
2054 inst
.error
= _("invalid register mask");
2058 if ((range
& exp
.X_add_number
) != 0)
2060 int regno
= range
& exp
.X_add_number
;
2063 regno
= (1 << regno
) - 1;
2065 (_("Warning: duplicated register (r%d) in register list"),
2069 range
|= exp
.X_add_number
;
2073 if (inst
.relocs
[0].type
!= 0)
2075 inst
.error
= _("expression too complex");
2079 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2080 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2081 inst
.relocs
[0].pc_rel
= 0;
2085 if (*str
== '|' || *str
== '+')
2091 while (another_range
);
2097 /* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2113 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2114 bfd_boolean
*partial_match
)
2119 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2123 unsigned long mask
= 0;
2125 bfd_boolean vpr_seen
= FALSE
;
2126 bfd_boolean expect_vpr
=
2127 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2129 if (skip_past_char (&str
, '{') == FAIL
)
2131 inst
.error
= _("expecting {");
2138 case REGLIST_VFP_S_VPR
:
2139 regtype
= REG_TYPE_VFS
;
2144 case REGLIST_VFP_D_VPR
:
2145 regtype
= REG_TYPE_VFD
;
2148 case REGLIST_NEON_D
:
2149 regtype
= REG_TYPE_NDQ
;
2156 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2173 base_reg
= max_regs
;
2174 *partial_match
= FALSE
;
2178 unsigned int setmask
= 1, addregs
= 1;
2179 const char vpr_str
[] = "vpr";
2180 size_t vpr_str_len
= strlen (vpr_str
);
2182 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2186 if (new_base
== FAIL
2187 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2188 && !ISALPHA (*(str
+ vpr_str_len
))
2194 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2198 first_error (_("VPR expected last"));
2201 else if (new_base
== FAIL
)
2203 if (regtype
== REG_TYPE_VFS
)
2204 first_error (_("VFP single precision register or VPR "
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2212 else if (new_base
== FAIL
)
2214 first_error (_(reg_expected_msgs
[regtype
]));
2218 *partial_match
= TRUE
;
2222 if (new_base
>= max_regs
)
2224 first_error (_("register out of range in list"));
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype
== REG_TYPE_NQ
)
2235 if (new_base
< base_reg
)
2236 base_reg
= new_base
;
2238 if (mask
& (setmask
<< new_base
))
2240 first_error (_("invalid register list"));
2244 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2246 as_tsktsk (_("register list not in ascending order"));
2250 mask
|= setmask
<< new_base
;
2253 if (*str
== '-') /* We have the start of a range expression */
2259 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2262 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2266 if (high_range
>= max_regs
)
2268 first_error (_("register out of range in list"));
2272 if (regtype
== REG_TYPE_NQ
)
2273 high_range
= high_range
+ 1;
2275 if (high_range
<= new_base
)
2277 inst
.error
= _("register range not in ascending order");
2281 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2283 if (mask
& (setmask
<< new_base
))
2285 inst
.error
= _("invalid register list");
2289 mask
|= setmask
<< new_base
;
2294 while (skip_past_comma (&str
) != FAIL
);
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2304 if (expect_vpr
&& !vpr_seen
)
2306 first_error (_("VPR expected last"));
2310 /* Final test -- the registers must be consecutive. */
2312 for (i
= 0; i
< count
; i
++)
2314 if ((mask
& (1u << i
)) == 0)
2316 inst
.error
= _("non-contiguous register range");
2326 /* True if two alias types are the same. */
2329 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2337 if (a
->defined
!= b
->defined
)
2340 if ((a
->defined
& NTA_HASTYPE
) != 0
2341 && (a
->eltype
.type
!= b
->eltype
.type
2342 || a
->eltype
.size
!= b
->eltype
.size
))
2345 if ((a
->defined
& NTA_HASINDEX
) != 0
2346 && (a
->index
!= b
->index
))
2352 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2360 #define NEON_LANE(X) ((X) & 0xf)
2361 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2365 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2367 struct neon_type_el
*eltype
)
2374 int leading_brace
= 0;
2375 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2376 const char *const incr_error
= mve
? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error
= _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype
;
2380 firsttype
.defined
= 0;
2381 firsttype
.eltype
.type
= NT_invtype
;
2382 firsttype
.eltype
.size
= -1;
2383 firsttype
.index
= -1;
2385 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2390 struct neon_typed_alias atype
;
2392 rtype
= REG_TYPE_MQ
;
2393 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2397 first_error (_(reg_expected_msgs
[rtype
]));
2404 if (rtype
== REG_TYPE_NQ
)
2410 else if (reg_incr
== -1)
2412 reg_incr
= getreg
- base_reg
;
2413 if (reg_incr
< 1 || reg_incr
> 2)
2415 first_error (_(incr_error
));
2419 else if (getreg
!= base_reg
+ reg_incr
* count
)
2421 first_error (_(incr_error
));
2425 if (! neon_alias_types_same (&atype
, &firsttype
))
2427 first_error (_(type_error
));
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2435 struct neon_typed_alias htype
;
2436 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2438 lane
= NEON_INTERLEAVE_LANES
;
2439 else if (lane
!= NEON_INTERLEAVE_LANES
)
2441 first_error (_(type_error
));
2446 else if (reg_incr
!= 1)
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2452 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2455 first_error (_(reg_expected_msgs
[rtype
]));
2458 if (! neon_alias_types_same (&htype
, &firsttype
))
2460 first_error (_(type_error
));
2463 count
+= hireg
+ dregs
- getreg
;
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype
== REG_TYPE_NQ
)
2474 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2478 else if (lane
!= atype
.index
)
2480 first_error (_(type_error
));
2484 else if (lane
== -1)
2485 lane
= NEON_INTERLEAVE_LANES
;
2486 else if (lane
!= NEON_INTERLEAVE_LANES
)
2488 first_error (_(type_error
));
2493 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2495 /* No lane set by [x]. We must be interleaving structures. */
2497 lane
= NEON_INTERLEAVE_LANES
;
2500 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2501 || (count
> 1 && reg_incr
== -1))
2503 first_error (_("error parsing element/structure list"));
2507 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2509 first_error (_("expected }"));
2517 *eltype
= firsttype
.eltype
;
2522 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2525 /* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2532 parse_reloc (char **str
)
2534 struct reloc_entry
*r
;
2538 return BFD_RELOC_UNUSED
;
2543 while (*q
&& *q
!= ')' && *q
!= ',')
2548 if ((r
= (struct reloc_entry
*)
2549 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2556 /* Directives: register aliases. */
2558 static struct reg_entry
*
2559 insert_reg_alias (char *str
, unsigned number
, int type
)
2561 struct reg_entry
*new_reg
;
2564 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2566 if (new_reg
->builtin
)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2569 /* Only warn about a redefinition if it's not defined as the
2571 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2577 name
= xstrdup (str
);
2578 new_reg
= XNEW (struct reg_entry
);
2580 new_reg
->name
= name
;
2581 new_reg
->number
= number
;
2582 new_reg
->type
= type
;
2583 new_reg
->builtin
= FALSE
;
2584 new_reg
->neon
= NULL
;
2586 str_hash_insert (arm_reg_hsh
, name
, new_reg
, 0);
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
2887 = (struct reg_entry
*) str_hash_find (arm_reg_hsh
, name
);
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 str_hash_delete (arm_reg_hsh
, name
);
2900 free ((char *) reg
->name
);
2904 /* Also locate the all upper case and all lower case versions.
2905 Do not complain if we cannot find one or the other as it
2906 was probably deleted above. */
2908 nbuf
= strdup (name
);
2909 for (p
= nbuf
; *p
; p
++)
2911 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2914 str_hash_delete (arm_reg_hsh
, nbuf
);
2915 free ((char *) reg
->name
);
2920 for (p
= nbuf
; *p
; p
++)
2922 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2925 str_hash_delete (arm_reg_hsh
, nbuf
);
2926 free ((char *) reg
->name
);
2935 *input_line_pointer
= saved_char
;
2936 demand_empty_rest_of_line ();
2939 /* Directives: Instruction set selection. */
2942 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2943 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2944 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2945 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947 /* Create a new mapping symbol for the transition to STATE. */
2950 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2953 const char * symname
;
2960 type
= BSF_NO_FLAGS
;
2964 type
= BSF_NO_FLAGS
;
2968 type
= BSF_NO_FLAGS
;
2974 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2975 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2980 THUMB_SET_FUNC (symbolP
, 0);
2981 ARM_SET_THUMB (symbolP
, 0);
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 THUMB_SET_FUNC (symbolP
, 1);
2987 ARM_SET_THUMB (symbolP
, 1);
2988 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2996 /* Save the mapping symbols for future reference. Also check that
2997 we do not place two mapping symbols at the same offset within a
2998 frag. We'll handle overlap between frags in
2999 check_mapping_symbols.
3001 If .fill or other data filling directive generates zero sized data,
3002 the mapping symbol for the following code will have the same value
3003 as the one generated for the data filling directive. In this case,
3004 we replace the old symbol with the new one at the same address. */
3007 if (frag
->tc_frag_data
.first_map
!= NULL
)
3009 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3010 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3012 frag
->tc_frag_data
.first_map
= symbolP
;
3014 if (frag
->tc_frag_data
.last_map
!= NULL
)
3016 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3017 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3018 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3020 frag
->tc_frag_data
.last_map
= symbolP
;
3023 /* We must sometimes convert a region marked as code to data during
3024 code alignment, if an odd number of bytes have to be padded. The
3025 code mapping symbol is pushed to an aligned address. */
3028 insert_data_mapping_symbol (enum mstate state
,
3029 valueT value
, fragS
*frag
, offsetT bytes
)
3031 /* If there was already a mapping symbol, remove it. */
3032 if (frag
->tc_frag_data
.last_map
!= NULL
3033 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3035 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3039 know (frag
->tc_frag_data
.first_map
== symp
);
3040 frag
->tc_frag_data
.first_map
= NULL
;
3042 frag
->tc_frag_data
.last_map
= NULL
;
3043 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3046 make_mapping_symbol (MAP_DATA
, value
, frag
);
3047 make_mapping_symbol (state
, value
+ bytes
, frag
);
3050 static void mapping_state_2 (enum mstate state
, int max_chars
);
3052 /* Set the mapping state to STATE. Only call this when about to
3053 emit some STATE bytes to the file. */
3055 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057 mapping_state (enum mstate state
)
3059 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3068 All ARM instructions require 4-byte alignment.
3069 (Almost) all Thumb instructions require 2-byte alignment.
3071 When emitting instructions into any section, mark the section
3074 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3075 but themselves require 2-byte alignment; this applies to some
3076 PC- relative forms. However, these cases will involve implicit
3077 literal pool generation or an explicit .align >=2, both of
3078 which will cause the section to me marked with sufficient
3079 alignment. Thus, we don't handle those cases here. */
3080 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3082 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3083 /* This case will be evaluated later. */
3086 mapping_state_2 (state
, 0);
3089 /* Same as mapping_state, but MAX_CHARS bytes have already been
3090 allocated. Put the mapping symbol that far back. */
3093 mapping_state_2 (enum mstate state
, int max_chars
)
3095 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3097 if (!SEG_NORMAL (now_seg
))
3100 if (mapstate
== state
)
3101 /* The mapping symbol has already been emitted.
3102 There is nothing else to do. */
3105 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3106 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3108 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3109 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3112 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3115 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3116 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3120 #define mapping_state(x) ((void)0)
3121 #define mapping_state_2(x, y) ((void)0)
3124 /* Find the real, Thumb encoded start of a Thumb function. */
3128 find_real_start (symbolS
* symbolP
)
3131 const char * name
= S_GET_NAME (symbolP
);
3132 symbolS
* new_target
;
3134 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3135 #define STUB_NAME ".real_start_of"
3140 /* The compiler may generate BL instructions to local labels because
3141 it needs to perform a branch to a far away location. These labels
3142 do not have a corresponding ".real_start_of" label. We check
3143 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3144 the ".real_start_of" convention for nonlocal branches. */
3145 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3148 real_start
= concat (STUB_NAME
, name
, NULL
);
3149 new_target
= symbol_find (real_start
);
3152 if (new_target
== NULL
)
3154 as_warn (_("Failed to find real start of function: %s\n"), name
);
3155 new_target
= symbolP
;
3163 opcode_select (int width
)
3170 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3171 as_bad (_("selected processor does not support THUMB opcodes"));
3174 /* No need to force the alignment, since we will have been
3175 coming from ARM mode, which is word-aligned. */
3176 record_alignment (now_seg
, 1);
3183 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3184 as_bad (_("selected processor does not support ARM opcodes"));
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 1);
3196 as_bad (_("invalid instruction size selected (%d)"), width
);
3201 s_arm (int ignore ATTRIBUTE_UNUSED
)
3204 demand_empty_rest_of_line ();
3208 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 demand_empty_rest_of_line ();
3215 s_code (int unused ATTRIBUTE_UNUSED
)
3219 temp
= get_absolute_expression ();
3224 opcode_select (temp
);
3228 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3233 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3235 /* If we are not already in thumb mode go into it, EVEN if
3236 the target processor does not support thumb instructions.
3237 This is used by gcc/config/arm/lib1funcs.asm for example
3238 to compile interworking support functions even if the
3239 target processor should not support interworking. */
3243 record_alignment (now_seg
, 1);
3246 demand_empty_rest_of_line ();
3250 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3254 /* The following label is the name/address of the start of a Thumb function.
3255 We need to know this for the interworking support. */
3256 label_is_thumb_function_name
= TRUE
;
3259 /* Perform a .set directive, but also mark the alias as
3260 being a thumb function. */
3263 s_thumb_set (int equiv
)
3265 /* XXX the following is a duplicate of the code for s_set() in read.c
3266 We cannot just call that code as we need to get at the symbol that
3273 /* Especial apologies for the random logic:
3274 This just grew, and could be parsed much more simply!
3276 delim
= get_symbol_name (& name
);
3277 end_name
= input_line_pointer
;
3278 (void) restore_line_pointer (delim
);
3280 if (*input_line_pointer
!= ',')
3283 as_bad (_("expected comma after name \"%s\""), name
);
3285 ignore_rest_of_line ();
3289 input_line_pointer
++;
3292 if (name
[0] == '.' && name
[1] == '\0')
3294 /* XXX - this should not happen to .thumb_set. */
3298 if ((symbolP
= symbol_find (name
)) == NULL
3299 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3302 /* When doing symbol listings, play games with dummy fragments living
3303 outside the normal fragment chain to record the file and line info
3305 if (listing
& LISTING_SYMBOLS
)
3307 extern struct list_info_struct
* listing_tail
;
3308 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3310 memset (dummy_frag
, 0, sizeof (fragS
));
3311 dummy_frag
->fr_type
= rs_fill
;
3312 dummy_frag
->line
= listing_tail
;
3313 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3314 dummy_frag
->fr_symbol
= symbolP
;
3318 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3321 /* "set" symbols are local unless otherwise specified. */
3322 SF_SET_LOCAL (symbolP
);
3323 #endif /* OBJ_COFF */
3324 } /* Make a new symbol. */
3326 symbol_table_insert (symbolP
);
3331 && S_IS_DEFINED (symbolP
)
3332 && S_GET_SEGMENT (symbolP
) != reg_section
)
3333 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3335 pseudo_set (symbolP
);
3337 demand_empty_rest_of_line ();
3339 /* XXX Now we come to the Thumb specific bit of code. */
3341 THUMB_SET_FUNC (symbolP
, 1);
3342 ARM_SET_THUMB (symbolP
, 1);
3343 #if defined OBJ_ELF || defined OBJ_COFF
3344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3348 /* Directives: Mode selection. */
3350 /* .syntax [unified|divided] - choose the new unified syntax
3351 (same for Arm and Thumb encoding, modulo slight differences in what
3352 can be represented) or the old divergent syntax for each mode. */
3354 s_syntax (int unused ATTRIBUTE_UNUSED
)
3358 delim
= get_symbol_name (& name
);
3360 if (!strcasecmp (name
, "unified"))
3361 unified_syntax
= TRUE
;
3362 else if (!strcasecmp (name
, "divided"))
3363 unified_syntax
= FALSE
;
3366 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3369 (void) restore_line_pointer (delim
);
3370 demand_empty_rest_of_line ();
3373 /* Directives: sectioning and alignment. */
3376 s_bss (int ignore ATTRIBUTE_UNUSED
)
3378 /* We don't support putting frags in the BSS segment, we fake it by
3379 marking in_bss, then looking at s_skip for clues. */
3380 subseg_set (bss_section
, 0);
3381 demand_empty_rest_of_line ();
3383 #ifdef md_elf_section_change_hook
3384 md_elf_section_change_hook ();
3389 s_even (int ignore ATTRIBUTE_UNUSED
)
3391 /* Never make frag if expect extra pass. */
3393 frag_align (1, 0, 0);
3395 record_alignment (now_seg
, 1);
3397 demand_empty_rest_of_line ();
3400 /* Directives: CodeComposer Studio. */
3402 /* .ref (for CodeComposer Studio syntax only). */
3404 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3406 if (codecomposer_syntax
)
3407 ignore_rest_of_line ();
3409 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3412 /* If name is not NULL, then it is used for marking the beginning of a
3413 function, whereas if it is NULL then it means the function end. */
3415 asmfunc_debug (const char * name
)
3417 static const char * last_name
= NULL
;
3421 gas_assert (last_name
== NULL
);
3424 if (debug_type
== DEBUG_STABS
)
3425 stabs_generate_asm_func (name
, name
);
3429 gas_assert (last_name
!= NULL
);
3431 if (debug_type
== DEBUG_STABS
)
3432 stabs_generate_asm_endfunc (last_name
, last_name
);
3439 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3441 if (codecomposer_syntax
)
3443 switch (asmfunc_state
)
3445 case OUTSIDE_ASMFUNC
:
3446 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3449 case WAITING_ASMFUNC_NAME
:
3450 as_bad (_(".asmfunc repeated."));
3453 case WAITING_ENDASMFUNC
:
3454 as_bad (_(".asmfunc without function."));
3457 demand_empty_rest_of_line ();
3460 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3464 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3466 if (codecomposer_syntax
)
3468 switch (asmfunc_state
)
3470 case OUTSIDE_ASMFUNC
:
3471 as_bad (_(".endasmfunc without a .asmfunc."));
3474 case WAITING_ASMFUNC_NAME
:
3475 as_bad (_(".endasmfunc without function."));
3478 case WAITING_ENDASMFUNC
:
3479 asmfunc_state
= OUTSIDE_ASMFUNC
;
3480 asmfunc_debug (NULL
);
3483 demand_empty_rest_of_line ();
3486 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3490 s_ccs_def (int name
)
3492 if (codecomposer_syntax
)
3495 as_bad (_(".def pseudo-op only available with -mccs flag."));
3498 /* Directives: Literal pools. */
3500 static literal_pool
*
3501 find_literal_pool (void)
3503 literal_pool
* pool
;
3505 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3507 if (pool
->section
== now_seg
3508 && pool
->sub_section
== now_subseg
)
3515 static literal_pool
*
3516 find_or_make_literal_pool (void)
3518 /* Next literal pool ID number. */
3519 static unsigned int latest_pool_num
= 1;
3520 literal_pool
* pool
;
3522 pool
= find_literal_pool ();
3526 /* Create a new pool. */
3527 pool
= XNEW (literal_pool
);
3531 pool
->next_free_entry
= 0;
3532 pool
->section
= now_seg
;
3533 pool
->sub_section
= now_subseg
;
3534 pool
->next
= list_of_pools
;
3535 pool
->symbol
= NULL
;
3536 pool
->alignment
= 2;
3538 /* Add it to the list. */
3539 list_of_pools
= pool
;
3542 /* New pools, and emptied pools, will have a NULL symbol. */
3543 if (pool
->symbol
== NULL
)
3545 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3546 &zero_address_frag
, 0);
3547 pool
->id
= latest_pool_num
++;
3554 /* Add the literal in the global 'inst'
3555 structure to the relevant literal pool. */
3558 add_to_lit_pool (unsigned int nbytes
)
3560 #define PADDING_SLOT 0x1
3561 #define LIT_ENTRY_SIZE_MASK 0xFF
3562 literal_pool
* pool
;
3563 unsigned int entry
, pool_size
= 0;
3564 bfd_boolean padding_slot_p
= FALSE
;
3570 imm1
= inst
.operands
[1].imm
;
3571 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3572 : inst
.relocs
[0].exp
.X_unsigned
? 0
3573 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3574 if (target_big_endian
)
3577 imm2
= inst
.operands
[1].imm
;
3581 pool
= find_or_make_literal_pool ();
3583 /* Check if this literal value is already in the pool. */
3584 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3588 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3589 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
3591 == inst
.relocs
[0].exp
.X_add_number
)
3592 && (pool
->literals
[entry
].X_md
== nbytes
)
3593 && (pool
->literals
[entry
].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3598 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3599 && (pool
->literals
[entry
].X_add_number
3600 == inst
.relocs
[0].exp
.X_add_number
)
3601 && (pool
->literals
[entry
].X_add_symbol
3602 == inst
.relocs
[0].exp
.X_add_symbol
)
3603 && (pool
->literals
[entry
].X_op_symbol
3604 == inst
.relocs
[0].exp
.X_op_symbol
)
3605 && (pool
->literals
[entry
].X_md
== nbytes
))
3608 else if ((nbytes
== 8)
3609 && !(pool_size
& 0x7)
3610 && ((entry
+ 1) != pool
->next_free_entry
)
3611 && (pool
->literals
[entry
].X_op
== O_constant
)
3612 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3613 && (pool
->literals
[entry
].X_unsigned
3614 == inst
.relocs
[0].exp
.X_unsigned
)
3615 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3616 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3617 && (pool
->literals
[entry
+ 1].X_unsigned
3618 == inst
.relocs
[0].exp
.X_unsigned
))
3621 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3622 if (padding_slot_p
&& (nbytes
== 4))
3628 /* Do we need to create a new entry? */
3629 if (entry
== pool
->next_free_entry
)
3631 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3633 inst
.error
= _("literal pool overflow");
3639 /* For 8-byte entries, we align to an 8-byte boundary,
3640 and split it into two 4-byte entries, because on 32-bit
3641 host, 8-byte constants are treated as big num, thus
3642 saved in "generic_bignum" which will be overwritten
3643 by later assignments.
3645 We also need to make sure there is enough space for
3648 We also check to make sure the literal operand is a
3650 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3651 || inst
.relocs
[0].exp
.X_op
== O_big
))
3653 inst
.error
= _("invalid type for literal pool");
3656 else if (pool_size
& 0x7)
3658 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3660 inst
.error
= _("literal pool overflow");
3664 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3665 pool
->literals
[entry
].X_op
= O_constant
;
3666 pool
->literals
[entry
].X_add_number
= 0;
3667 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3668 pool
->next_free_entry
+= 1;
3671 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3673 inst
.error
= _("literal pool overflow");
3677 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3678 pool
->literals
[entry
].X_op
= O_constant
;
3679 pool
->literals
[entry
].X_add_number
= imm1
;
3680 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3681 pool
->literals
[entry
++].X_md
= 4;
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm2
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
].X_md
= 4;
3687 pool
->alignment
= 3;
3688 pool
->next_free_entry
+= 1;
3692 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3693 pool
->literals
[entry
].X_md
= 4;
3697 /* PR ld/12974: Record the location of the first source line to reference
3698 this entry in the literal pool. If it turns out during linking that the
3699 symbol does not exist we will be able to give an accurate line number for
3700 the (first use of the) missing reference. */
3701 if (debug_type
== DEBUG_DWARF2
)
3702 dwarf2_where (pool
->locs
+ entry
);
3704 pool
->next_free_entry
+= 1;
3706 else if (padding_slot_p
)
3708 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3709 pool
->literals
[entry
].X_md
= nbytes
;
3712 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3713 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3714 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3720 tc_start_label_without_colon (void)
3722 bfd_boolean ret
= TRUE
;
3724 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3726 const char *label
= input_line_pointer
;
3728 while (!is_end_of_line
[(int) label
[-1]])
3733 as_bad (_("Invalid label '%s'"), label
);
3737 asmfunc_debug (label
);
3739 asmfunc_state
= WAITING_ENDASMFUNC
;
3745 /* Can't use symbol_new here, so have to create a symbol and then at
3746 a later date assign it a value. That's what these functions do. */
3749 symbol_locate (symbolS
* symbolP
,
3750 const char * name
, /* It is copied, the caller can modify. */
3751 segT segment
, /* Segment identifier (SEG_<something>). */
3752 valueT valu
, /* Symbol value. */
3753 fragS
* frag
) /* Associated fragment. */
3756 char * preserved_copy_of_name
;
3758 name_length
= strlen (name
) + 1; /* +1 for \0. */
3759 obstack_grow (¬es
, name
, name_length
);
3760 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3762 #ifdef tc_canonicalize_symbol_name
3763 preserved_copy_of_name
=
3764 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3767 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3769 S_SET_SEGMENT (symbolP
, segment
);
3770 S_SET_VALUE (symbolP
, valu
);
3771 symbol_clear_list_pointers (symbolP
);
3773 symbol_set_frag (symbolP
, frag
);
3775 /* Link to end of symbol chain. */
3777 extern int symbol_table_frozen
;
3779 if (symbol_table_frozen
)
3783 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3785 obj_symbol_new_hook (symbolP
);
3787 #ifdef tc_symbol_new_hook
3788 tc_symbol_new_hook (symbolP
);
3792 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3793 #endif /* DEBUG_SYMS */
3797 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3800 literal_pool
* pool
;
3803 pool
= find_literal_pool ();
3805 || pool
->symbol
== NULL
3806 || pool
->next_free_entry
== 0)
3809 /* Align pool as you have word accesses.
3810 Only make a frag if we have to. */
3812 frag_align (pool
->alignment
, 0, 0);
3814 record_alignment (now_seg
, 2);
3817 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3818 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3820 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3822 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3823 (valueT
) frag_now_fix (), frag_now
);
3824 symbol_table_insert (pool
->symbol
);
3826 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3828 #if defined OBJ_COFF || defined OBJ_ELF
3829 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3832 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3835 if (debug_type
== DEBUG_DWARF2
)
3836 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3838 /* First output the expression in the instruction to the pool. */
3839 emit_expr (&(pool
->literals
[entry
]),
3840 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3843 /* Mark the pool as empty. */
3844 pool
->next_free_entry
= 0;
3845 pool
->symbol
= NULL
;
3849 /* Forward declarations for functions below, in the MD interface
3851 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3852 static valueT
create_unwind_entry (int);
3853 static void start_unwind_section (const segT
, int);
3854 static void add_unwind_opcode (valueT
, int);
3855 static void flush_pending_unwind (void);
3857 /* Directives: Data. */
3860 s_arm_elf_cons (int nbytes
)
3864 #ifdef md_flush_pending_output
3865 md_flush_pending_output ();
3868 if (is_it_end_of_statement ())
3870 demand_empty_rest_of_line ();
3874 #ifdef md_cons_align
3875 md_cons_align (nbytes
);
3878 mapping_state (MAP_DATA
);
3882 char *base
= input_line_pointer
;
3886 if (exp
.X_op
!= O_symbol
)
3887 emit_expr (&exp
, (unsigned int) nbytes
);
3890 char *before_reloc
= input_line_pointer
;
3891 reloc
= parse_reloc (&input_line_pointer
);
3894 as_bad (_("unrecognized relocation suffix"));
3895 ignore_rest_of_line ();
3898 else if (reloc
== BFD_RELOC_UNUSED
)
3899 emit_expr (&exp
, (unsigned int) nbytes
);
3902 reloc_howto_type
*howto
= (reloc_howto_type
*)
3903 bfd_reloc_type_lookup (stdoutput
,
3904 (bfd_reloc_code_real_type
) reloc
);
3905 int size
= bfd_get_reloc_size (howto
);
3907 if (reloc
== BFD_RELOC_ARM_PLT32
)
3909 as_bad (_("(plt) is only valid on branch targets"));
3910 reloc
= BFD_RELOC_UNUSED
;
3915 as_bad (ngettext ("%s relocations do not fit in %d byte",
3916 "%s relocations do not fit in %d bytes",
3918 howto
->name
, nbytes
);
3921 /* We've parsed an expression stopping at O_symbol.
3922 But there may be more expression left now that we
3923 have parsed the relocation marker. Parse it again.
3924 XXX Surely there is a cleaner way to do this. */
3925 char *p
= input_line_pointer
;
3927 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3929 memcpy (save_buf
, base
, input_line_pointer
- base
);
3930 memmove (base
+ (input_line_pointer
- before_reloc
),
3931 base
, before_reloc
- base
);
3933 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3935 memcpy (base
, save_buf
, p
- base
);
3937 offset
= nbytes
- size
;
3938 p
= frag_more (nbytes
);
3939 memset (p
, 0, nbytes
);
3940 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3941 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3947 while (*input_line_pointer
++ == ',');
3949 /* Put terminator back into stream. */
3950 input_line_pointer
--;
3951 demand_empty_rest_of_line ();
3954 /* Emit an expression containing a 32-bit thumb instruction.
3955 Implementation based on put_thumb32_insn. */
3958 emit_thumb32_expr (expressionS
* exp
)
3960 expressionS exp_high
= *exp
;
3962 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3963 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3964 exp
->X_add_number
&= 0xffff;
3965 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3968 /* Guess the instruction size based on the opcode. */
3971 thumb_insn_size (int opcode
)
3973 if ((unsigned int) opcode
< 0xe800u
)
3975 else if ((unsigned int) opcode
>= 0xe8000000u
)
3982 emit_insn (expressionS
*exp
, int nbytes
)
3986 if (exp
->X_op
== O_constant
)
3991 size
= thumb_insn_size (exp
->X_add_number
);
3995 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3997 as_bad (_(".inst.n operand too big. "\
3998 "Use .inst.w instead"));
4003 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4004 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4006 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4008 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4009 emit_thumb32_expr (exp
);
4011 emit_expr (exp
, (unsigned int) size
);
4013 it_fsm_post_encode ();
4017 as_bad (_("cannot determine Thumb instruction size. " \
4018 "Use .inst.n/.inst.w instead"));
4021 as_bad (_("constant expression required"));
4026 /* Like s_arm_elf_cons but do not use md_cons_align and
4027 set the mapping state to MAP_ARM/MAP_THUMB. */
4030 s_arm_elf_inst (int nbytes
)
4032 if (is_it_end_of_statement ())
4034 demand_empty_rest_of_line ();
4038 /* Calling mapping_state () here will not change ARM/THUMB,
4039 but will ensure not to be in DATA state. */
4042 mapping_state (MAP_THUMB
);
4047 as_bad (_("width suffixes are invalid in ARM mode"));
4048 ignore_rest_of_line ();
4054 mapping_state (MAP_ARM
);
4063 if (! emit_insn (& exp
, nbytes
))
4065 ignore_rest_of_line ();
4069 while (*input_line_pointer
++ == ',');
4071 /* Put terminator back into stream. */
4072 input_line_pointer
--;
4073 demand_empty_rest_of_line ();
4076 /* Parse a .rel31 directive. */
4079 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4086 if (*input_line_pointer
== '1')
4087 highbit
= 0x80000000;
4088 else if (*input_line_pointer
!= '0')
4089 as_bad (_("expected 0 or 1"));
4091 input_line_pointer
++;
4092 if (*input_line_pointer
!= ',')
4093 as_bad (_("missing comma"));
4094 input_line_pointer
++;
4096 #ifdef md_flush_pending_output
4097 md_flush_pending_output ();
4100 #ifdef md_cons_align
4104 mapping_state (MAP_DATA
);
4109 md_number_to_chars (p
, highbit
, 4);
4110 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4111 BFD_RELOC_ARM_PREL31
);
4113 demand_empty_rest_of_line ();
4116 /* Directives: AEABI stack-unwind tables. */
4118 /* Parse an unwind_fnstart directive. Simply records the current location. */
4121 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4123 demand_empty_rest_of_line ();
4124 if (unwind
.proc_start
)
4126 as_bad (_("duplicate .fnstart directive"));
4130 /* Mark the start of the function. */
4131 unwind
.proc_start
= expr_build_dot ();
4133 /* Reset the rest of the unwind info. */
4134 unwind
.opcode_count
= 0;
4135 unwind
.table_entry
= NULL
;
4136 unwind
.personality_routine
= NULL
;
4137 unwind
.personality_index
= -1;
4138 unwind
.frame_size
= 0;
4139 unwind
.fp_offset
= 0;
4140 unwind
.fp_reg
= REG_SP
;
4142 unwind
.sp_restored
= 0;
4146 /* Parse a handlerdata directive. Creates the exception handling table entry
4147 for the function. */
4150 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4152 demand_empty_rest_of_line ();
4153 if (!unwind
.proc_start
)
4154 as_bad (MISSING_FNSTART
);
4156 if (unwind
.table_entry
)
4157 as_bad (_("duplicate .handlerdata directive"));
4159 create_unwind_entry (1);
4162 /* Parse an unwind_fnend directive. Generates the index table entry. */
4165 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4170 unsigned int marked_pr_dependency
;
4172 demand_empty_rest_of_line ();
4174 if (!unwind
.proc_start
)
4176 as_bad (_(".fnend directive without .fnstart"));
4180 /* Add eh table entry. */
4181 if (unwind
.table_entry
== NULL
)
4182 val
= create_unwind_entry (0);
4186 /* Add index table entry. This is two words. */
4187 start_unwind_section (unwind
.saved_seg
, 1);
4188 frag_align (2, 0, 0);
4189 record_alignment (now_seg
, 2);
4191 ptr
= frag_more (8);
4193 where
= frag_now_fix () - 8;
4195 /* Self relative offset of the function start. */
4196 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4197 BFD_RELOC_ARM_PREL31
);
4199 /* Indicate dependency on EHABI-defined personality routines to the
4200 linker, if it hasn't been done already. */
4201 marked_pr_dependency
4202 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4203 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4204 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4206 static const char *const name
[] =
4208 "__aeabi_unwind_cpp_pr0",
4209 "__aeabi_unwind_cpp_pr1",
4210 "__aeabi_unwind_cpp_pr2"
4212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4214 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4215 |= 1 << unwind
.personality_index
;
4219 /* Inline exception table entry. */
4220 md_number_to_chars (ptr
+ 4, val
, 4);
4222 /* Self relative offset of the table entry. */
4223 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4224 BFD_RELOC_ARM_PREL31
);
4226 /* Restore the original section. */
4227 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4229 unwind
.proc_start
= NULL
;
4233 /* Parse an unwind_cantunwind directive. */
4236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4238 demand_empty_rest_of_line ();
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4243 as_bad (_("personality routine specified for cantunwind frame"));
4245 unwind
.personality_index
= -2;
4249 /* Parse a personalityindex directive. */
4252 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4256 if (!unwind
.proc_start
)
4257 as_bad (MISSING_FNSTART
);
4259 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4260 as_bad (_("duplicate .personalityindex directive"));
4264 if (exp
.X_op
!= O_constant
4265 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4267 as_bad (_("bad personality routine number"));
4268 ignore_rest_of_line ();
4272 unwind
.personality_index
= exp
.X_add_number
;
4274 demand_empty_rest_of_line ();
4278 /* Parse a personality directive. */
4281 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4285 if (!unwind
.proc_start
)
4286 as_bad (MISSING_FNSTART
);
4288 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4289 as_bad (_("duplicate .personality directive"));
4291 c
= get_symbol_name (& name
);
4292 p
= input_line_pointer
;
4294 ++ input_line_pointer
;
4295 unwind
.personality_routine
= symbol_find_or_make (name
);
4297 demand_empty_rest_of_line ();
4301 /* Parse a directive saving core registers. */
4304 s_arm_unwind_save_core (void)
4310 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4313 as_bad (_("expected register list"));
4314 ignore_rest_of_line ();
4318 demand_empty_rest_of_line ();
4320 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4321 into .unwind_save {..., sp...}. We aren't bothered about the value of
4322 ip because it is clobbered by calls. */
4323 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4324 && (range
& 0x3000) == 0x1000)
4326 unwind
.opcode_count
--;
4327 unwind
.sp_restored
= 0;
4328 range
= (range
| 0x2000) & ~0x1000;
4329 unwind
.pending_offset
= 0;
4335 /* See if we can use the short opcodes. These pop a block of up to 8
4336 registers starting with r4, plus maybe r14. */
4337 for (n
= 0; n
< 8; n
++)
4339 /* Break at the first non-saved register. */
4340 if ((range
& (1 << (n
+ 4))) == 0)
4343 /* See if there are any other bits set. */
4344 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4346 /* Use the long form. */
4347 op
= 0x8000 | ((range
>> 4) & 0xfff);
4348 add_unwind_opcode (op
, 2);
4352 /* Use the short form. */
4354 op
= 0xa8; /* Pop r14. */
4356 op
= 0xa0; /* Do not pop r14. */
4358 add_unwind_opcode (op
, 1);
4365 op
= 0xb100 | (range
& 0xf);
4366 add_unwind_opcode (op
, 2);
4369 /* Record the number of bytes pushed. */
4370 for (n
= 0; n
< 16; n
++)
4372 if (range
& (1 << n
))
4373 unwind
.frame_size
+= 4;
4378 /* Parse a directive saving FPA registers. */
4381 s_arm_unwind_save_fpa (int reg
)
4387 /* Get Number of registers to transfer. */
4388 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4391 exp
.X_op
= O_illegal
;
4393 if (exp
.X_op
!= O_constant
)
4395 as_bad (_("expected , <constant>"));
4396 ignore_rest_of_line ();
4400 num_regs
= exp
.X_add_number
;
4402 if (num_regs
< 1 || num_regs
> 4)
4404 as_bad (_("number of registers must be in the range [1:4]"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4414 op
= 0xb4 | (num_regs
- 1);
4415 add_unwind_opcode (op
, 1);
4420 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4421 add_unwind_opcode (op
, 2);
4423 unwind
.frame_size
+= num_regs
* 12;
4427 /* Parse a directive saving VFP registers for ARMv6 and above. */
4430 s_arm_unwind_save_vfp_armv6 (void)
4435 int num_vfpv3_regs
= 0;
4436 int num_regs_below_16
;
4437 bfd_boolean partial_match
;
4439 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4443 as_bad (_("expected register list"));
4444 ignore_rest_of_line ();
4448 demand_empty_rest_of_line ();
4450 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4451 than FSTMX/FLDMX-style ones). */
4453 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 num_vfpv3_regs
= count
;
4456 else if (start
+ count
> 16)
4457 num_vfpv3_regs
= start
+ count
- 16;
4459 if (num_vfpv3_regs
> 0)
4461 int start_offset
= start
> 16 ? start
- 16 : 0;
4462 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4463 add_unwind_opcode (op
, 2);
4466 /* Generate opcode for registers numbered in the range 0 .. 15. */
4467 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4468 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4469 if (num_regs_below_16
> 0)
4471 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4472 add_unwind_opcode (op
, 2);
4475 unwind
.frame_size
+= count
* 8;
4479 /* Parse a directive saving VFP registers for pre-ARMv6. */
4482 s_arm_unwind_save_vfp (void)
4487 bfd_boolean partial_match
;
4489 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4493 as_bad (_("expected register list"));
4494 ignore_rest_of_line ();
4498 demand_empty_rest_of_line ();
4503 op
= 0xb8 | (count
- 1);
4504 add_unwind_opcode (op
, 1);
4509 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4510 add_unwind_opcode (op
, 2);
4512 unwind
.frame_size
+= count
* 8 + 4;
4516 /* Parse a directive saving iWMMXt data registers. */
4519 s_arm_unwind_save_mmxwr (void)
4527 if (*input_line_pointer
== '{')
4528 input_line_pointer
++;
4532 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4536 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4541 as_tsktsk (_("register list not in ascending order"));
4544 if (*input_line_pointer
== '-')
4546 input_line_pointer
++;
4547 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4550 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4553 else if (reg
>= hi_reg
)
4555 as_bad (_("bad register range"));
4558 for (; reg
< hi_reg
; reg
++)
4562 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4564 skip_past_char (&input_line_pointer
, '}');
4566 demand_empty_rest_of_line ();
4568 /* Generate any deferred opcodes because we're going to be looking at
4570 flush_pending_unwind ();
4572 for (i
= 0; i
< 16; i
++)
4574 if (mask
& (1 << i
))
4575 unwind
.frame_size
+= 8;
4578 /* Attempt to combine with a previous opcode. We do this because gcc
4579 likes to output separate unwind directives for a single block of
4581 if (unwind
.opcode_count
> 0)
4583 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4584 if ((i
& 0xf8) == 0xc0)
4587 /* Only merge if the blocks are contiguous. */
4590 if ((mask
& 0xfe00) == (1 << 9))
4592 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4593 unwind
.opcode_count
--;
4596 else if (i
== 6 && unwind
.opcode_count
>= 2)
4598 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4602 op
= 0xffff << (reg
- 1);
4604 && ((mask
& op
) == (1u << (reg
- 1))))
4606 op
= (1 << (reg
+ i
+ 1)) - 1;
4607 op
&= ~((1 << reg
) - 1);
4609 unwind
.opcode_count
-= 2;
4616 /* We want to generate opcodes in the order the registers have been
4617 saved, ie. descending order. */
4618 for (reg
= 15; reg
>= -1; reg
--)
4620 /* Save registers in blocks. */
4622 || !(mask
& (1 << reg
)))
4624 /* We found an unsaved reg. Generate opcodes to save the
4631 op
= 0xc0 | (hi_reg
- 10);
4632 add_unwind_opcode (op
, 1);
4637 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4638 add_unwind_opcode (op
, 2);
4647 ignore_rest_of_line ();
4651 s_arm_unwind_save_mmxwcg (void)
4658 if (*input_line_pointer
== '{')
4659 input_line_pointer
++;
4661 skip_whitespace (input_line_pointer
);
4665 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4669 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4675 as_tsktsk (_("register list not in ascending order"));
4678 if (*input_line_pointer
== '-')
4680 input_line_pointer
++;
4681 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4687 else if (reg
>= hi_reg
)
4689 as_bad (_("bad register range"));
4692 for (; reg
< hi_reg
; reg
++)
4696 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4698 skip_past_char (&input_line_pointer
, '}');
4700 demand_empty_rest_of_line ();
4702 /* Generate any deferred opcodes because we're going to be looking at
4704 flush_pending_unwind ();
4706 for (reg
= 0; reg
< 16; reg
++)
4708 if (mask
& (1 << reg
))
4709 unwind
.frame_size
+= 4;
4712 add_unwind_opcode (op
, 2);
4715 ignore_rest_of_line ();
4719 /* Parse an unwind_save directive.
4720 If the argument is non-zero, this is a .vsave directive. */
4723 s_arm_unwind_save (int arch_v6
)
4726 struct reg_entry
*reg
;
4727 bfd_boolean had_brace
= FALSE
;
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 /* Figure out what sort of save we have. */
4733 peek
= input_line_pointer
;
4741 reg
= arm_reg_parse_multi (&peek
);
4745 as_bad (_("register expected"));
4746 ignore_rest_of_line ();
4755 as_bad (_("FPA .unwind_save does not take a register list"));
4756 ignore_rest_of_line ();
4759 input_line_pointer
= peek
;
4760 s_arm_unwind_save_fpa (reg
->number
);
4764 s_arm_unwind_save_core ();
4769 s_arm_unwind_save_vfp_armv6 ();
4771 s_arm_unwind_save_vfp ();
4774 case REG_TYPE_MMXWR
:
4775 s_arm_unwind_save_mmxwr ();
4778 case REG_TYPE_MMXWCG
:
4779 s_arm_unwind_save_mmxwcg ();
4783 as_bad (_(".unwind_save does not support this kind of register"));
4784 ignore_rest_of_line ();
4789 /* Parse an unwind_movsp directive. */
4792 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4798 if (!unwind
.proc_start
)
4799 as_bad (MISSING_FNSTART
);
4801 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4804 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4805 ignore_rest_of_line ();
4809 /* Optional constant. */
4810 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4812 if (immediate_for_directive (&offset
) == FAIL
)
4818 demand_empty_rest_of_line ();
4820 if (reg
== REG_SP
|| reg
== REG_PC
)
4822 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4826 if (unwind
.fp_reg
!= REG_SP
)
4827 as_bad (_("unexpected .unwind_movsp directive"));
4829 /* Generate opcode to restore the value. */
4831 add_unwind_opcode (op
, 1);
4833 /* Record the information for later. */
4834 unwind
.fp_reg
= reg
;
4835 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4836 unwind
.sp_restored
= 1;
4839 /* Parse an unwind_pad directive. */
4842 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4846 if (!unwind
.proc_start
)
4847 as_bad (MISSING_FNSTART
);
4849 if (immediate_for_directive (&offset
) == FAIL
)
4854 as_bad (_("stack increment must be multiple of 4"));
4855 ignore_rest_of_line ();
4859 /* Don't generate any opcodes, just record the details for later. */
4860 unwind
.frame_size
+= offset
;
4861 unwind
.pending_offset
+= offset
;
4863 demand_empty_rest_of_line ();
4866 /* Parse an unwind_setfp directive. */
4869 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4875 if (!unwind
.proc_start
)
4876 as_bad (MISSING_FNSTART
);
4878 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4879 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4882 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4886 as_bad (_("expected <reg>, <reg>"));
4887 ignore_rest_of_line ();
4891 /* Optional constant. */
4892 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4894 if (immediate_for_directive (&offset
) == FAIL
)
4900 demand_empty_rest_of_line ();
4902 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4904 as_bad (_("register must be either sp or set by a previous"
4905 "unwind_movsp directive"));
4909 /* Don't generate any opcodes, just record the information for later. */
4910 unwind
.fp_reg
= fp_reg
;
4912 if (sp_reg
== REG_SP
)
4913 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4915 unwind
.fp_offset
-= offset
;
4918 /* Parse an unwind_raw directive. */
4921 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4924 /* This is an arbitrary limit. */
4925 unsigned char op
[16];
4928 if (!unwind
.proc_start
)
4929 as_bad (MISSING_FNSTART
);
4932 if (exp
.X_op
== O_constant
4933 && skip_past_comma (&input_line_pointer
) != FAIL
)
4935 unwind
.frame_size
+= exp
.X_add_number
;
4939 exp
.X_op
= O_illegal
;
4941 if (exp
.X_op
!= O_constant
)
4943 as_bad (_("expected <offset>, <opcode>"));
4944 ignore_rest_of_line ();
4950 /* Parse the opcode. */
4955 as_bad (_("unwind opcode too long"));
4956 ignore_rest_of_line ();
4958 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4960 as_bad (_("invalid unwind opcode"));
4961 ignore_rest_of_line ();
4964 op
[count
++] = exp
.X_add_number
;
4966 /* Parse the next byte. */
4967 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4973 /* Add the opcode bytes in reverse order. */
4975 add_unwind_opcode (op
[count
], 1);
4977 demand_empty_rest_of_line ();
4981 /* Parse a .eabi_attribute directive. */
4984 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4986 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4988 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4989 attributes_set_explicitly
[tag
] = 1;
4992 /* Emit a tls fix for the symbol. */
4995 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4999 #ifdef md_flush_pending_output
5000 md_flush_pending_output ();
5003 #ifdef md_cons_align
5007 /* Since we're just labelling the code, there's no need to define a
5010 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5011 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5012 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5013 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5015 #endif /* OBJ_ELF */
5017 static void s_arm_arch (int);
5018 static void s_arm_object_arch (int);
5019 static void s_arm_cpu (int);
5020 static void s_arm_fpu (int);
5021 static void s_arm_arch_extension (int);
5026 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5033 if (exp
.X_op
== O_symbol
)
5034 exp
.X_op
= O_secrel
;
5036 emit_expr (&exp
, 4);
5038 while (*input_line_pointer
++ == ',');
5040 input_line_pointer
--;
5041 demand_empty_rest_of_line ();
5046 arm_is_largest_exponent_ok (int precision
)
5048 /* precision == 1 ensures that this will only return
5049 true for 16 bit floats. */
5050 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5054 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5058 enum fp_16bit_format new_format
;
5060 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5062 name
= input_line_pointer
;
5063 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5064 input_line_pointer
++;
5066 saved_char
= *input_line_pointer
;
5067 *input_line_pointer
= 0;
5069 if (strcasecmp (name
, "ieee") == 0)
5070 new_format
= ARM_FP16_FORMAT_IEEE
;
5071 else if (strcasecmp (name
, "alternative") == 0)
5072 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5075 as_bad (_("unrecognised float16 format \"%s\""), name
);
5079 /* Only set fp16_format if it is still the default (aka not already
5081 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5082 fp16_format
= new_format
;
5085 if (new_format
!= fp16_format
)
5086 as_warn (_("float16 format cannot be set more than once, ignoring."));
5090 *input_line_pointer
= saved_char
;
5091 ignore_rest_of_line ();
5094 /* This table describes all the machine specific pseudo-ops the assembler
5095 has to support. The fields are:
5096 pseudo-op name without dot
5097 function to call to execute this pseudo-op
5098 Integer arg to pass to the function. */
5100 const pseudo_typeS md_pseudo_table
[] =
5102 /* Never called because '.req' does not start a line. */
5103 { "req", s_req
, 0 },
5104 /* Following two are likewise never called. */
5107 { "unreq", s_unreq
, 0 },
5108 { "bss", s_bss
, 0 },
5109 { "align", s_align_ptwo
, 2 },
5110 { "arm", s_arm
, 0 },
5111 { "thumb", s_thumb
, 0 },
5112 { "code", s_code
, 0 },
5113 { "force_thumb", s_force_thumb
, 0 },
5114 { "thumb_func", s_thumb_func
, 0 },
5115 { "thumb_set", s_thumb_set
, 0 },
5116 { "even", s_even
, 0 },
5117 { "ltorg", s_ltorg
, 0 },
5118 { "pool", s_ltorg
, 0 },
5119 { "syntax", s_syntax
, 0 },
5120 { "cpu", s_arm_cpu
, 0 },
5121 { "arch", s_arm_arch
, 0 },
5122 { "object_arch", s_arm_object_arch
, 0 },
5123 { "fpu", s_arm_fpu
, 0 },
5124 { "arch_extension", s_arm_arch_extension
, 0 },
5126 { "word", s_arm_elf_cons
, 4 },
5127 { "long", s_arm_elf_cons
, 4 },
5128 { "inst.n", s_arm_elf_inst
, 2 },
5129 { "inst.w", s_arm_elf_inst
, 4 },
5130 { "inst", s_arm_elf_inst
, 0 },
5131 { "rel31", s_arm_rel31
, 0 },
5132 { "fnstart", s_arm_unwind_fnstart
, 0 },
5133 { "fnend", s_arm_unwind_fnend
, 0 },
5134 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5135 { "personality", s_arm_unwind_personality
, 0 },
5136 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5137 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5138 { "save", s_arm_unwind_save
, 0 },
5139 { "vsave", s_arm_unwind_save
, 1 },
5140 { "movsp", s_arm_unwind_movsp
, 0 },
5141 { "pad", s_arm_unwind_pad
, 0 },
5142 { "setfp", s_arm_unwind_setfp
, 0 },
5143 { "unwind_raw", s_arm_unwind_raw
, 0 },
5144 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5145 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5149 /* These are used for dwarf. */
5153 /* These are used for dwarf2. */
5154 { "file", dwarf2_directive_file
, 0 },
5155 { "loc", dwarf2_directive_loc
, 0 },
5156 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5158 { "extend", float_cons
, 'x' },
5159 { "ldouble", float_cons
, 'x' },
5160 { "packed", float_cons
, 'p' },
5161 { "bfloat16", float_cons
, 'b' },
5163 {"secrel32", pe_directive_secrel
, 0},
5166 /* These are for compatibility with CodeComposer Studio. */
5167 {"ref", s_ccs_ref
, 0},
5168 {"def", s_ccs_def
, 0},
5169 {"asmfunc", s_ccs_asmfunc
, 0},
5170 {"endasmfunc", s_ccs_endasmfunc
, 0},
5172 {"float16", float_cons
, 'h' },
5173 {"float16_format", set_fp16_format
, 0 },
5178 /* Parser functions used exclusively in instruction operands. */
5180 /* Generic immediate-value read function for use in insn parsing.
5181 STR points to the beginning of the immediate (the leading #);
5182 VAL receives the value; if the value is outside [MIN, MAX]
5183 issue an error. PREFIX_OPT is true if the immediate prefix is
5187 parse_immediate (char **str
, int *val
, int min
, int max
,
5188 bfd_boolean prefix_opt
)
5192 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5193 if (exp
.X_op
!= O_constant
)
5195 inst
.error
= _("constant expression required");
5199 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5201 inst
.error
= _("immediate value out of range");
5205 *val
= exp
.X_add_number
;
5209 /* Less-generic immediate-value read function with the possibility of loading a
5210 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5211 instructions. Puts the result directly in inst.operands[i]. */
5214 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5215 bfd_boolean allow_symbol_p
)
5218 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5221 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5223 if (exp_p
->X_op
== O_constant
)
5225 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5226 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5227 O_constant. We have to be careful not to break compilation for
5228 32-bit X_add_number, though. */
5229 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5231 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5232 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5234 inst
.operands
[i
].regisimm
= 1;
5237 else if (exp_p
->X_op
== O_big
5238 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5240 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5242 /* Bignums have their least significant bits in
5243 generic_bignum[0]. Make sure we put 32 bits in imm and
5244 32 bits in reg, in a (hopefully) portable way. */
5245 gas_assert (parts
!= 0);
5247 /* Make sure that the number is not too big.
5248 PR 11972: Bignums can now be sign-extended to the
5249 size of a .octa so check that the out of range bits
5250 are all zero or all one. */
5251 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5253 LITTLENUM_TYPE m
= -1;
5255 if (generic_bignum
[parts
* 2] != 0
5256 && generic_bignum
[parts
* 2] != m
)
5259 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5260 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5264 inst
.operands
[i
].imm
= 0;
5265 for (j
= 0; j
< parts
; j
++, idx
++)
5266 inst
.operands
[i
].imm
|= ((unsigned) generic_bignum
[idx
]
5267 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5268 inst
.operands
[i
].reg
= 0;
5269 for (j
= 0; j
< parts
; j
++, idx
++)
5270 inst
.operands
[i
].reg
|= ((unsigned) generic_bignum
[idx
]
5271 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5272 inst
.operands
[i
].regisimm
= 1;
5274 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5282 /* Returns the pseudo-register number of an FPA immediate constant,
5283 or FAIL if there isn't a valid constant here. */
5286 parse_fpa_immediate (char ** str
)
5288 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5294 /* First try and match exact strings, this is to guarantee
5295 that some formats will work even for cross assembly. */
5297 for (i
= 0; fp_const
[i
]; i
++)
5299 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5303 *str
+= strlen (fp_const
[i
]);
5304 if (is_end_of_line
[(unsigned char) **str
])
5310 /* Just because we didn't get a match doesn't mean that the constant
5311 isn't valid, just that it is in a format that we don't
5312 automatically recognize. Try parsing it with the standard
5313 expression routines. */
5315 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5317 /* Look for a raw floating point number. */
5318 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5319 && is_end_of_line
[(unsigned char) *save_in
])
5321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5323 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5325 if (words
[j
] != fp_values
[i
][j
])
5329 if (j
== MAX_LITTLENUMS
)
5337 /* Try and parse a more complex expression, this will probably fail
5338 unless the code uses a floating point prefix (eg "0f"). */
5339 save_in
= input_line_pointer
;
5340 input_line_pointer
= *str
;
5341 if (expression (&exp
) == absolute_section
5342 && exp
.X_op
== O_big
5343 && exp
.X_add_number
< 0)
5345 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 #define X_PRECISION 5
5348 #define E_PRECISION 15L
5349 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5351 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5353 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5355 if (words
[j
] != fp_values
[i
][j
])
5359 if (j
== MAX_LITTLENUMS
)
5361 *str
= input_line_pointer
;
5362 input_line_pointer
= save_in
;
5369 *str
= input_line_pointer
;
5370 input_line_pointer
= save_in
;
5371 inst
.error
= _("invalid FPA immediate expression");
5375 /* Returns 1 if a number has "quarter-precision" float format
5376 0baBbbbbbc defgh000 00000000 00000000. */
5379 is_quarter_float (unsigned imm
)
5381 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5382 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5386 /* Detect the presence of a floating point or integer zero constant,
5390 parse_ifimm_zero (char **in
)
5394 if (!is_immediate_prefix (**in
))
5396 /* In unified syntax, all prefixes are optional. */
5397 if (!unified_syntax
)
5403 /* Accept #0x0 as a synonym for #0. */
5404 if (strncmp (*in
, "0x", 2) == 0)
5407 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5412 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5413 &generic_floating_point_number
);
5416 && generic_floating_point_number
.sign
== '+'
5417 && (generic_floating_point_number
.low
5418 > generic_floating_point_number
.leader
))
5424 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5425 0baBbbbbbc defgh000 00000000 00000000.
5426 The zero and minus-zero cases need special handling, since they can't be
5427 encoded in the "quarter-precision" float format, but can nonetheless be
5428 loaded as integer constants. */
5431 parse_qfloat_immediate (char **ccp
, int *immed
)
5435 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5436 int found_fpchar
= 0;
5438 skip_past_char (&str
, '#');
5440 /* We must not accidentally parse an integer as a floating-point number. Make
5441 sure that the value we parse is not an integer by checking for special
5442 characters '.' or 'e'.
5443 FIXME: This is a horrible hack, but doing better is tricky because type
5444 information isn't in a very usable state at parse time. */
5446 skip_whitespace (fpnum
);
5448 if (strncmp (fpnum
, "0x", 2) == 0)
5452 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5453 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5463 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5465 unsigned fpword
= 0;
5468 /* Our FP word must be 32 bits (single-precision FP). */
5469 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5471 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5475 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5488 /* Shift operands. */
5491 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5494 struct asm_shift_name
5497 enum shift_kind kind
;
5500 /* Third argument to parse_shift. */
5501 enum parse_shift_mode
5503 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5504 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5505 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5506 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5507 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5508 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5511 /* Parse a <shift> specifier on an ARM data processing instruction.
5512 This has three forms:
5514 (LSL|LSR|ASL|ASR|ROR) Rs
5515 (LSL|LSR|ASL|ASR|ROR) #imm
5518 Note that ASL is assimilated to LSL in the instruction encoding, and
5519 RRX to ROR #0 (which cannot be written as such). */
5522 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5524 const struct asm_shift_name
*shift_name
;
5525 enum shift_kind shift
;
5530 for (p
= *str
; ISALPHA (*p
); p
++)
5535 inst
.error
= _("shift expression expected");
5540 = (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5543 if (shift_name
== NULL
)
5545 inst
.error
= _("shift expression expected");
5549 shift
= shift_name
->kind
;
5553 case NO_SHIFT_RESTRICT
:
5554 case SHIFT_IMMEDIATE
:
5555 if (shift
== SHIFT_UXTW
)
5557 inst
.error
= _("'UXTW' not allowed here");
5562 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5563 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5565 inst
.error
= _("'LSL' or 'ASR' required");
5570 case SHIFT_LSL_IMMEDIATE
:
5571 if (shift
!= SHIFT_LSL
)
5573 inst
.error
= _("'LSL' required");
5578 case SHIFT_ASR_IMMEDIATE
:
5579 if (shift
!= SHIFT_ASR
)
5581 inst
.error
= _("'ASR' required");
5585 case SHIFT_UXTW_IMMEDIATE
:
5586 if (shift
!= SHIFT_UXTW
)
5588 inst
.error
= _("'UXTW' required");
5596 if (shift
!= SHIFT_RRX
)
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p
);
5601 if (mode
== NO_SHIFT_RESTRICT
5602 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5604 inst
.operands
[i
].imm
= reg
;
5605 inst
.operands
[i
].immisreg
= 1;
5607 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5610 inst
.operands
[i
].shift_kind
= shift
;
5611 inst
.operands
[i
].shifted
= 1;
5616 /* Parse a <shifter_operand> for an ARM data processing instruction:
5619 #<immediate>, <rotate>
5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
5625 is deferred to md_apply_fix. */
5628 parse_shifter_operand (char **str
, int i
)
5633 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5635 inst
.operands
[i
].reg
= value
;
5636 inst
.operands
[i
].isreg
= 1;
5638 /* parse_shift will override this if appropriate */
5639 inst
.relocs
[0].exp
.X_op
= O_constant
;
5640 inst
.relocs
[0].exp
.X_add_number
= 0;
5642 if (skip_past_comma (str
) == FAIL
)
5645 /* Shift operation on register. */
5646 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5649 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5652 if (skip_past_comma (str
) == SUCCESS
)
5654 /* #x, y -- ie explicit rotation by Y. */
5655 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5658 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5660 inst
.error
= _("constant expression expected");
5664 value
= exp
.X_add_number
;
5665 if (value
< 0 || value
> 30 || value
% 2 != 0)
5667 inst
.error
= _("invalid rotation");
5670 if (inst
.relocs
[0].exp
.X_add_number
< 0
5671 || inst
.relocs
[0].exp
.X_add_number
> 255)
5673 inst
.error
= _("invalid constant");
5677 /* Encode as specified. */
5678 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5682 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5683 inst
.relocs
[0].pc_rel
= 0;
5687 /* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5694 struct group_reloc_table_entry
5705 /* Varieties of non-ALU group relocation. */
5713 static struct group_reloc_table_entry group_reloc_table
[] =
5714 { /* Program counter relative: */
5716 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5721 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5726 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5731 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5736 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5740 /* Section base relative */
5742 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5747 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5752 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5757 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5762 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5765 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5766 /* Absolute thumb alu relocations. */
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5788 /* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5796 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5799 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5801 int length
= strlen (group_reloc_table
[i
].name
);
5803 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5804 && (*str
)[length
] == ':')
5806 *out
= &group_reloc_table
[i
];
5807 *str
+= (length
+ 1);
5815 /* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5827 Everything else is as for parse_shifter_operand. */
5829 static parse_operand_result
5830 parse_shifter_operand_group_reloc (char **str
, int i
)
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5836 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5837 || (*str
)[0] == ':')
5839 struct group_reloc_table_entry
*entry
;
5841 if ((*str
)[0] == '#')
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5849 inst
.error
= _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5853 /* We now have the group relocation table entry corresponding to
5854 the name in the assembler source. Next, we parse the expression. */
5855 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5858 /* Record the relocation type (always the ALU variant here). */
5859 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5860 gas_assert (inst
.relocs
[0].type
!= 0);
5862 return PARSE_OPERAND_SUCCESS
;
5865 return parse_shifter_operand (str
, i
) == SUCCESS
5866 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5868 /* Never reached. */
5871 /* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875 static parse_operand_result
5876 parse_neon_alignment (char **str
, int i
)
5881 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5883 if (exp
.X_op
!= O_constant
)
5885 inst
.error
= _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL
;
5889 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5890 inst
.operands
[i
].immisalign
= 1;
5891 /* Alignments are not pre-indexes. */
5892 inst
.operands
[i
].preind
= 0;
5895 return PARSE_OPERAND_SUCCESS
;
5898 /* Parse all forms of an ARM address expression. Information is written
5899 to inst.operands[i] and/or inst.relocs[0].
5901 Preindexed addressing (.preind=1):
5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5906 .shift_kind=shift .relocs[0].exp=shift_imm
5908 These three may have a trailing ! which causes .writeback to be set also.
5910 Postindexed addressing (.postind=1, .writeback=1):
5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5915 .shift_kind=shift .relocs[0].exp=shift_imm
5917 Unindexed addressing (.preind=0, .postind=0):
5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5923 [Rn]{!} shorthand for [Rn,#0]{!}
5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5927 It is the caller's responsibility to check for addressing modes not
5928 supported by the instruction, and to set inst.relocs[0].type. */
5930 static parse_operand_result
5931 parse_address_main (char **str
, int i
, int group_relocations
,
5932 group_reloc_type group_type
)
5937 if (skip_past_char (&p
, '[') == FAIL
)
5939 if (group_type
== GROUP_MVE
5940 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5942 /* [r0-r15] expected as argument but receiving r0-r15 without
5944 inst
.error
= BAD_SYNTAX
;
5945 return PARSE_OPERAND_FAIL
;
5947 else if (skip_past_char (&p
, '=') == FAIL
)
5949 /* Bare address - translate to PC-relative offset. */
5950 inst
.relocs
[0].pc_rel
= 1;
5951 inst
.operands
[i
].reg
= REG_PC
;
5952 inst
.operands
[i
].isreg
= 1;
5953 inst
.operands
[i
].preind
= 1;
5955 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5956 return PARSE_OPERAND_FAIL
;
5958 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5959 /*allow_symbol_p=*/TRUE
))
5960 return PARSE_OPERAND_FAIL
;
5963 return PARSE_OPERAND_SUCCESS
;
5966 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5967 skip_whitespace (p
);
5969 if (group_type
== GROUP_MVE
)
5971 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5972 struct neon_type_el et
;
5973 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5975 inst
.operands
[i
].isquad
= 1;
5977 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5979 inst
.error
= BAD_ADDR_MODE
;
5980 return PARSE_OPERAND_FAIL
;
5983 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5985 if (group_type
== GROUP_MVE
)
5986 inst
.error
= BAD_ADDR_MODE
;
5988 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5989 return PARSE_OPERAND_FAIL
;
5991 inst
.operands
[i
].reg
= reg
;
5992 inst
.operands
[i
].isreg
= 1;
5994 if (skip_past_comma (&p
) == SUCCESS
)
5996 inst
.operands
[i
].preind
= 1;
5999 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6001 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6002 struct neon_type_el et
;
6003 if (group_type
== GROUP_MVE
6004 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6006 inst
.operands
[i
].immisreg
= 2;
6007 inst
.operands
[i
].imm
= reg
;
6009 if (skip_past_comma (&p
) == SUCCESS
)
6011 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6013 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6014 inst
.relocs
[0].exp
.X_add_number
= 0;
6017 return PARSE_OPERAND_FAIL
;
6020 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6022 inst
.operands
[i
].imm
= reg
;
6023 inst
.operands
[i
].immisreg
= 1;
6025 if (skip_past_comma (&p
) == SUCCESS
)
6026 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6027 return PARSE_OPERAND_FAIL
;
6029 else if (skip_past_char (&p
, ':') == SUCCESS
)
6031 /* FIXME: '@' should be used here, but it's filtered out by generic
6032 code before we get to see it here. This may be subject to
6034 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6036 if (result
!= PARSE_OPERAND_SUCCESS
)
6041 if (inst
.operands
[i
].negative
)
6043 inst
.operands
[i
].negative
= 0;
6047 if (group_relocations
6048 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6050 struct group_reloc_table_entry
*entry
;
6052 /* Skip over the #: or : sequence. */
6058 /* Try to parse a group relocation. Anything else is an
6060 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6062 inst
.error
= _("unknown group relocation");
6063 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6066 /* We now have the group relocation table entry corresponding to
6067 the name in the assembler source. Next, we parse the
6069 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6070 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6072 /* Record the relocation type. */
6077 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6082 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6087 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6094 if (inst
.relocs
[0].type
== 0)
6096 inst
.error
= _("this group relocation is not allowed on this instruction");
6097 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6104 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6105 return PARSE_OPERAND_FAIL
;
6106 /* If the offset is 0, find out if it's a +0 or -0. */
6107 if (inst
.relocs
[0].exp
.X_op
== O_constant
6108 && inst
.relocs
[0].exp
.X_add_number
== 0)
6110 skip_whitespace (q
);
6114 skip_whitespace (q
);
6117 inst
.operands
[i
].negative
= 1;
6122 else if (skip_past_char (&p
, ':') == SUCCESS
)
6124 /* FIXME: '@' should be used here, but it's filtered out by generic code
6125 before we get to see it here. This may be subject to change. */
6126 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6128 if (result
!= PARSE_OPERAND_SUCCESS
)
6132 if (skip_past_char (&p
, ']') == FAIL
)
6134 inst
.error
= _("']' expected");
6135 return PARSE_OPERAND_FAIL
;
6138 if (skip_past_char (&p
, '!') == SUCCESS
)
6139 inst
.operands
[i
].writeback
= 1;
6141 else if (skip_past_comma (&p
) == SUCCESS
)
6143 if (skip_past_char (&p
, '{') == SUCCESS
)
6145 /* [Rn], {expr} - unindexed, with option */
6146 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6147 0, 255, TRUE
) == FAIL
)
6148 return PARSE_OPERAND_FAIL
;
6150 if (skip_past_char (&p
, '}') == FAIL
)
6152 inst
.error
= _("'}' expected at end of 'option' field");
6153 return PARSE_OPERAND_FAIL
;
6155 if (inst
.operands
[i
].preind
)
6157 inst
.error
= _("cannot combine index with option");
6158 return PARSE_OPERAND_FAIL
;
6161 return PARSE_OPERAND_SUCCESS
;
6165 inst
.operands
[i
].postind
= 1;
6166 inst
.operands
[i
].writeback
= 1;
6168 if (inst
.operands
[i
].preind
)
6170 inst
.error
= _("cannot combine pre- and post-indexing");
6171 return PARSE_OPERAND_FAIL
;
6175 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6177 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6178 struct neon_type_el et
;
6179 if (group_type
== GROUP_MVE
6180 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6182 inst
.operands
[i
].immisreg
= 2;
6183 inst
.operands
[i
].imm
= reg
;
6185 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6187 /* We might be using the immediate for alignment already. If we
6188 are, OR the register number into the low-order bits. */
6189 if (inst
.operands
[i
].immisalign
)
6190 inst
.operands
[i
].imm
|= reg
;
6192 inst
.operands
[i
].imm
= reg
;
6193 inst
.operands
[i
].immisreg
= 1;
6195 if (skip_past_comma (&p
) == SUCCESS
)
6196 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6197 return PARSE_OPERAND_FAIL
;
6203 if (inst
.operands
[i
].negative
)
6205 inst
.operands
[i
].negative
= 0;
6208 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6209 return PARSE_OPERAND_FAIL
;
6210 /* If the offset is 0, find out if it's a +0 or -0. */
6211 if (inst
.relocs
[0].exp
.X_op
== O_constant
6212 && inst
.relocs
[0].exp
.X_add_number
== 0)
6214 skip_whitespace (q
);
6218 skip_whitespace (q
);
6221 inst
.operands
[i
].negative
= 1;
6227 /* If at this point neither .preind nor .postind is set, we have a
6228 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6229 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6231 inst
.operands
[i
].preind
= 1;
6232 inst
.relocs
[0].exp
.X_op
= O_constant
;
6233 inst
.relocs
[0].exp
.X_add_number
= 0;
6236 return PARSE_OPERAND_SUCCESS
;
6240 parse_address (char **str
, int i
)
6242 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6246 static parse_operand_result
6247 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6249 return parse_address_main (str
, i
, 1, type
);
6252 /* Parse an operand for a MOVW or MOVT instruction. */
6254 parse_half (char **str
)
6259 skip_past_char (&p
, '#');
6260 if (strncasecmp (p
, ":lower16:", 9) == 0)
6261 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6262 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6263 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6265 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6268 skip_whitespace (p
);
6271 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6274 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6276 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6278 inst
.error
= _("constant expression expected");
6281 if (inst
.relocs
[0].exp
.X_add_number
< 0
6282 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6284 inst
.error
= _("immediate value out of range");
6292 /* Miscellaneous. */
6294 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6295 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6297 parse_psr (char **str
, bfd_boolean lhs
)
6300 unsigned long psr_field
;
6301 const struct asm_psr
*psr
;
6303 bfd_boolean is_apsr
= FALSE
;
6304 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6306 /* PR gas/12698: If the user has specified -march=all then m_profile will
6307 be TRUE, but we want to ignore it in this case as we are building for any
6308 CPU type, including non-m variants. */
6309 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6312 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6313 feature for ease of use and backwards compatibility. */
6315 if (strncasecmp (p
, "SPSR", 4) == 0)
6318 goto unsupported_psr
;
6320 psr_field
= SPSR_BIT
;
6322 else if (strncasecmp (p
, "CPSR", 4) == 0)
6325 goto unsupported_psr
;
6329 else if (strncasecmp (p
, "APSR", 4) == 0)
6331 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6332 and ARMv7-R architecture CPUs. */
6341 while (ISALNUM (*p
) || *p
== '_');
6343 if (strncasecmp (start
, "iapsr", 5) == 0
6344 || strncasecmp (start
, "eapsr", 5) == 0
6345 || strncasecmp (start
, "xpsr", 4) == 0
6346 || strncasecmp (start
, "psr", 3) == 0)
6347 p
= start
+ strcspn (start
, "rR") + 1;
6349 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6355 /* If APSR is being written, a bitfield may be specified. Note that
6356 APSR itself is handled above. */
6357 if (psr
->field
<= 3)
6359 psr_field
= psr
->field
;
6365 /* M-profile MSR instructions have the mask field set to "10", except
6366 *PSR variants which modify APSR, which may use a different mask (and
6367 have been handled already). Do that by setting the PSR_f field
6369 return psr
->field
| (lhs
? PSR_f
: 0);
6372 goto unsupported_psr
;
6378 /* A suffix follows. */
6384 while (ISALNUM (*p
) || *p
== '_');
6388 /* APSR uses a notation for bits, rather than fields. */
6389 unsigned int nzcvq_bits
= 0;
6390 unsigned int g_bit
= 0;
6393 for (bit
= start
; bit
!= p
; bit
++)
6395 switch (TOLOWER (*bit
))
6398 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6402 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6406 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6410 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6414 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6418 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6422 inst
.error
= _("unexpected bit specified after APSR");
6427 if (nzcvq_bits
== 0x1f)
6432 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6434 inst
.error
= _("selected processor does not "
6435 "support DSP extension");
6442 if ((nzcvq_bits
& 0x20) != 0
6443 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6444 || (g_bit
& 0x2) != 0)
6446 inst
.error
= _("bad bitmask specified after APSR");
6452 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6457 psr_field
|= psr
->field
;
6463 goto error
; /* Garbage after "[CS]PSR". */
6465 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6466 is deprecated, but allow it anyway. */
6470 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6473 else if (!m_profile
)
6474 /* These bits are never right for M-profile devices: don't set them
6475 (only code paths which read/write APSR reach here). */
6476 psr_field
|= (PSR_c
| PSR_f
);
6482 inst
.error
= _("selected processor does not support requested special "
6483 "purpose register");
6487 inst
.error
= _("flag for {c}psr instruction expected");
6492 parse_sys_vldr_vstr (char **str
)
6501 {"FPSCR", 0x1, 0x0},
6502 {"FPSCR_nzcvqc", 0x2, 0x0},
6505 {"FPCXTNS", 0x6, 0x1},
6506 {"FPCXTS", 0x7, 0x1}
6508 char *op_end
= strchr (*str
, ',');
6509 size_t op_strlen
= op_end
- *str
;
6511 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6513 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6515 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6524 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6525 value suitable for splatting into the AIF field of the instruction. */
6528 parse_cps_flags (char **str
)
6537 case '\0': case ',':
6540 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6541 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6542 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6545 inst
.error
= _("unrecognized CPS flag");
6550 if (saw_a_flag
== 0)
6552 inst
.error
= _("missing CPS flags");
6560 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6561 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6564 parse_endian_specifier (char **str
)
6569 if (strncasecmp (s
, "BE", 2))
6571 else if (strncasecmp (s
, "LE", 2))
6575 inst
.error
= _("valid endian specifiers are be or le");
6579 if (ISALNUM (s
[2]) || s
[2] == '_')
6581 inst
.error
= _("valid endian specifiers are be or le");
6586 return little_endian
;
6589 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6590 value suitable for poking into the rotate field of an sxt or sxta
6591 instruction, or FAIL on error. */
6594 parse_ror (char **str
)
6599 if (strncasecmp (s
, "ROR", 3) == 0)
6603 inst
.error
= _("missing rotation field after comma");
6607 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6612 case 0: *str
= s
; return 0x0;
6613 case 8: *str
= s
; return 0x1;
6614 case 16: *str
= s
; return 0x2;
6615 case 24: *str
= s
; return 0x3;
6618 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6623 /* Parse a conditional code (from conds[] below). The value returned is in the
6624 range 0 .. 14, or FAIL. */
6626 parse_cond (char **str
)
6629 const struct asm_cond
*c
;
6631 /* Condition codes are always 2 characters, so matching up to
6632 3 characters is sufficient. */
6637 while (ISALPHA (*q
) && n
< 3)
6639 cond
[n
] = TOLOWER (*q
);
6644 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6647 inst
.error
= _("condition required");
6655 /* Parse an option for a barrier instruction. Returns the encoding for the
6658 parse_barrier (char **str
)
6661 const struct asm_barrier_opt
*o
;
6664 while (ISALPHA (*q
))
6667 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6672 if (!mark_feature_used (&o
->arch
))
6679 /* Parse the operands of a table branch instruction. Similar to a memory
6682 parse_tb (char **str
)
6687 if (skip_past_char (&p
, '[') == FAIL
)
6689 inst
.error
= _("'[' expected");
6693 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6695 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6698 inst
.operands
[0].reg
= reg
;
6700 if (skip_past_comma (&p
) == FAIL
)
6702 inst
.error
= _("',' expected");
6706 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6708 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6711 inst
.operands
[0].imm
= reg
;
6713 if (skip_past_comma (&p
) == SUCCESS
)
6715 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6717 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6719 inst
.error
= _("invalid shift");
6722 inst
.operands
[0].shifted
= 1;
6725 if (skip_past_char (&p
, ']') == FAIL
)
6727 inst
.error
= _("']' expected");
6734 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6735 information on the types the operands can take and how they are encoded.
6736 Up to four operands may be read; this function handles setting the
6737 ".present" field for each read operand itself.
6738 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6739 else returns FAIL. */
6742 parse_neon_mov (char **str
, int *which_operand
)
6744 int i
= *which_operand
, val
;
6745 enum arm_reg_type rtype
;
6747 struct neon_type_el optype
;
6749 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6751 /* Cases 17 or 19. */
6752 inst
.operands
[i
].reg
= val
;
6753 inst
.operands
[i
].isvec
= 1;
6754 inst
.operands
[i
].isscalar
= 2;
6755 inst
.operands
[i
].vectype
= optype
;
6756 inst
.operands
[i
++].present
= 1;
6758 if (skip_past_comma (&ptr
) == FAIL
)
6761 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6763 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6764 inst
.operands
[i
].reg
= val
;
6765 inst
.operands
[i
].isreg
= 1;
6766 inst
.operands
[i
].present
= 1;
6768 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6770 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6771 inst
.operands
[i
].reg
= val
;
6772 inst
.operands
[i
].isvec
= 1;
6773 inst
.operands
[i
].isscalar
= 2;
6774 inst
.operands
[i
].vectype
= optype
;
6775 inst
.operands
[i
++].present
= 1;
6777 if (skip_past_comma (&ptr
) == FAIL
)
6780 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6783 inst
.operands
[i
].reg
= val
;
6784 inst
.operands
[i
].isreg
= 1;
6785 inst
.operands
[i
++].present
= 1;
6787 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6793 inst
.operands
[i
].reg
= val
;
6794 inst
.operands
[i
].isreg
= 1;
6795 inst
.operands
[i
].present
= 1;
6799 first_error (_("expected ARM or MVE vector register"));
6803 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6805 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6806 inst
.operands
[i
].reg
= val
;
6807 inst
.operands
[i
].isscalar
= 1;
6808 inst
.operands
[i
].vectype
= optype
;
6809 inst
.operands
[i
++].present
= 1;
6811 if (skip_past_comma (&ptr
) == FAIL
)
6814 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6817 inst
.operands
[i
].reg
= val
;
6818 inst
.operands
[i
].isreg
= 1;
6819 inst
.operands
[i
].present
= 1;
6821 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6823 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6826 /* Cases 0, 1, 2, 3, 5 (D only). */
6827 if (skip_past_comma (&ptr
) == FAIL
)
6830 inst
.operands
[i
].reg
= val
;
6831 inst
.operands
[i
].isreg
= 1;
6832 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6833 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6834 inst
.operands
[i
].isvec
= 1;
6835 inst
.operands
[i
].vectype
= optype
;
6836 inst
.operands
[i
++].present
= 1;
6838 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6840 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6841 Case 13: VMOV <Sd>, <Rm> */
6842 inst
.operands
[i
].reg
= val
;
6843 inst
.operands
[i
].isreg
= 1;
6844 inst
.operands
[i
].present
= 1;
6846 if (rtype
== REG_TYPE_NQ
)
6848 first_error (_("can't use Neon quad register here"));
6851 else if (rtype
!= REG_TYPE_VFS
)
6854 if (skip_past_comma (&ptr
) == FAIL
)
6856 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6858 inst
.operands
[i
].reg
= val
;
6859 inst
.operands
[i
].isreg
= 1;
6860 inst
.operands
[i
].present
= 1;
6863 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6865 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6868 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6869 Case 1: VMOV<c><q> <Dd>, <Dm>
6870 Case 8: VMOV.F32 <Sd>, <Sm>
6871 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6873 inst
.operands
[i
].reg
= val
;
6874 inst
.operands
[i
].isreg
= 1;
6875 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6876 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6877 inst
.operands
[i
].isvec
= 1;
6878 inst
.operands
[i
].vectype
= optype
;
6879 inst
.operands
[i
].present
= 1;
6881 if (skip_past_comma (&ptr
) == SUCCESS
)
6886 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6889 inst
.operands
[i
].reg
= val
;
6890 inst
.operands
[i
].isreg
= 1;
6891 inst
.operands
[i
++].present
= 1;
6893 if (skip_past_comma (&ptr
) == FAIL
)
6896 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6899 inst
.operands
[i
].reg
= val
;
6900 inst
.operands
[i
].isreg
= 1;
6901 inst
.operands
[i
].present
= 1;
6904 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6905 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6906 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6907 Case 10: VMOV.F32 <Sd>, #<imm>
6908 Case 11: VMOV.F64 <Dd>, #<imm> */
6909 inst
.operands
[i
].immisfloat
= 1;
6910 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6912 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6913 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6917 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6921 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6923 /* Cases 6, 7, 16, 18. */
6924 inst
.operands
[i
].reg
= val
;
6925 inst
.operands
[i
].isreg
= 1;
6926 inst
.operands
[i
++].present
= 1;
6928 if (skip_past_comma (&ptr
) == FAIL
)
6931 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6933 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6934 inst
.operands
[i
].reg
= val
;
6935 inst
.operands
[i
].isscalar
= 2;
6936 inst
.operands
[i
].present
= 1;
6937 inst
.operands
[i
].vectype
= optype
;
6939 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6941 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6942 inst
.operands
[i
].reg
= val
;
6943 inst
.operands
[i
].isscalar
= 1;
6944 inst
.operands
[i
].present
= 1;
6945 inst
.operands
[i
].vectype
= optype
;
6947 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6949 inst
.operands
[i
].reg
= val
;
6950 inst
.operands
[i
].isreg
= 1;
6951 inst
.operands
[i
++].present
= 1;
6953 if (skip_past_comma (&ptr
) == FAIL
)
6956 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6959 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6961 inst
.operands
[i
].reg
= val
;
6962 inst
.operands
[i
].isreg
= 1;
6963 inst
.operands
[i
].isvec
= 1;
6964 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6965 inst
.operands
[i
].vectype
= optype
;
6966 inst
.operands
[i
].present
= 1;
6968 if (rtype
== REG_TYPE_VFS
)
6972 if (skip_past_comma (&ptr
) == FAIL
)
6974 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6977 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6980 inst
.operands
[i
].reg
= val
;
6981 inst
.operands
[i
].isreg
= 1;
6982 inst
.operands
[i
].isvec
= 1;
6983 inst
.operands
[i
].issingle
= 1;
6984 inst
.operands
[i
].vectype
= optype
;
6985 inst
.operands
[i
].present
= 1;
6990 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6993 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6994 inst
.operands
[i
].reg
= val
;
6995 inst
.operands
[i
].isvec
= 1;
6996 inst
.operands
[i
].isscalar
= 2;
6997 inst
.operands
[i
].vectype
= optype
;
6998 inst
.operands
[i
++].present
= 1;
7000 if (skip_past_comma (&ptr
) == FAIL
)
7003 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
7006 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7009 inst
.operands
[i
].reg
= val
;
7010 inst
.operands
[i
].isvec
= 1;
7011 inst
.operands
[i
].isscalar
= 2;
7012 inst
.operands
[i
].vectype
= optype
;
7013 inst
.operands
[i
].present
= 1;
7017 first_error (_("VFP single, double or MVE vector register"
7023 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7027 inst
.operands
[i
].reg
= val
;
7028 inst
.operands
[i
].isreg
= 1;
7029 inst
.operands
[i
].isvec
= 1;
7030 inst
.operands
[i
].issingle
= 1;
7031 inst
.operands
[i
].vectype
= optype
;
7032 inst
.operands
[i
].present
= 1;
7037 first_error (_("parse error"));
7041 /* Successfully parsed the operands. Update args. */
7047 first_error (_("expected comma"));
7051 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7055 /* Use this macro when the operand constraints are different
7056 for ARM and THUMB (e.g. ldrd). */
7057 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7058 ((arm_operand) | ((thumb_operand) << 16))
7060 /* Matcher codes for parse_operands. */
7061 enum operand_parse_code
7063 OP_stop
, /* end of line */
7065 OP_RR
, /* ARM register */
7066 OP_RRnpc
, /* ARM register, not r15 */
7067 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7068 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7069 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7070 optional trailing ! */
7071 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7072 OP_RCP
, /* Coprocessor number */
7073 OP_RCN
, /* Coprocessor register */
7074 OP_RF
, /* FPA register */
7075 OP_RVS
, /* VFP single precision register */
7076 OP_RVD
, /* VFP double precision register (0..15) */
7077 OP_RND
, /* Neon double precision register (0..31) */
7078 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7079 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7081 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7083 OP_RNQ
, /* Neon quad precision register */
7084 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7085 OP_RVSD
, /* VFP single or double precision register */
7086 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7087 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7088 OP_RNSD
, /* Neon single or double precision register */
7089 OP_RNDQ
, /* Neon double or quad precision register */
7090 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7091 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7092 OP_RNSDQ
, /* Neon single, double or quad precision register */
7093 OP_RNSC
, /* Neon scalar D[X] */
7094 OP_RVC
, /* VFP control register */
7095 OP_RMF
, /* Maverick F register */
7096 OP_RMD
, /* Maverick D register */
7097 OP_RMFX
, /* Maverick FX register */
7098 OP_RMDX
, /* Maverick DX register */
7099 OP_RMAX
, /* Maverick AX register */
7100 OP_RMDS
, /* Maverick DSPSC register */
7101 OP_RIWR
, /* iWMMXt wR register */
7102 OP_RIWC
, /* iWMMXt wC register */
7103 OP_RIWG
, /* iWMMXt wCG register */
7104 OP_RXA
, /* XScale accumulator register */
7106 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7107 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7109 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7111 OP_RMQ
, /* MVE vector register. */
7112 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7113 OP_RMQRR
, /* MVE vector or ARM register. */
7115 /* New operands for Armv8.1-M Mainline. */
7116 OP_LR
, /* ARM LR register */
7117 OP_RRe
, /* ARM register, only even numbered. */
7118 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7119 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7120 OP_RR_ZR
, /* ARM register or ZR but no PC */
7122 OP_REGLST
, /* ARM register list */
7123 OP_CLRMLST
, /* CLRM register list */
7124 OP_VRSLST
, /* VFP single-precision register list */
7125 OP_VRDLST
, /* VFP double-precision register list */
7126 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7127 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7128 OP_NSTRLST
, /* Neon element/structure list */
7129 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7130 OP_MSTRLST2
, /* MVE vector list with two elements. */
7131 OP_MSTRLST4
, /* MVE vector list with four elements. */
7133 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7134 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7135 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7136 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7138 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7139 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7140 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7141 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7143 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7144 scalar, or ARM register. */
7145 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7146 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7147 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7149 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7150 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7151 OP_VMOV
, /* Neon VMOV operands. */
7152 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7153 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7155 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7156 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7158 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7159 OP_VLDR
, /* VLDR operand. */
7161 OP_I0
, /* immediate zero */
7162 OP_I7
, /* immediate value 0 .. 7 */
7163 OP_I15
, /* 0 .. 15 */
7164 OP_I16
, /* 1 .. 16 */
7165 OP_I16z
, /* 0 .. 16 */
7166 OP_I31
, /* 0 .. 31 */
7167 OP_I31w
, /* 0 .. 31, optional trailing ! */
7168 OP_I32
, /* 1 .. 32 */
7169 OP_I32z
, /* 0 .. 32 */
7170 OP_I48_I64
, /* 48 or 64 */
7171 OP_I63
, /* 0 .. 63 */
7172 OP_I63s
, /* -64 .. 63 */
7173 OP_I64
, /* 1 .. 64 */
7174 OP_I64z
, /* 0 .. 64 */
7175 OP_I127
, /* 0 .. 127 */
7176 OP_I255
, /* 0 .. 255 */
7177 OP_I511
, /* 0 .. 511 */
7178 OP_I4095
, /* 0 .. 4095 */
7179 OP_I8191
, /* 0 .. 8191 */
7180 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7181 OP_I7b
, /* 0 .. 7 */
7182 OP_I15b
, /* 0 .. 15 */
7183 OP_I31b
, /* 0 .. 31 */
7185 OP_SH
, /* shifter operand */
7186 OP_SHG
, /* shifter operand with possible group relocation */
7187 OP_ADDR
, /* Memory address expression (any mode) */
7188 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7189 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7190 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7191 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7192 OP_EXP
, /* arbitrary expression */
7193 OP_EXPi
, /* same, with optional immediate prefix */
7194 OP_EXPr
, /* same, with optional relocation suffix */
7195 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7196 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7197 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7198 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7200 OP_CPSF
, /* CPS flags */
7201 OP_ENDI
, /* Endianness specifier */
7202 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7203 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7204 OP_COND
, /* conditional code */
7205 OP_TB
, /* Table branch. */
7207 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7209 OP_RRnpc_I0
, /* ARM register or literal 0 */
7210 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7211 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7212 OP_RF_IF
, /* FPA register or immediate */
7213 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7214 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7216 /* Optional operands. */
7217 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7218 OP_oI31b
, /* 0 .. 31 */
7219 OP_oI32b
, /* 1 .. 32 */
7220 OP_oI32z
, /* 0 .. 32 */
7221 OP_oIffffb
, /* 0 .. 65535 */
7222 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7224 OP_oRR
, /* ARM register */
7225 OP_oLR
, /* ARM LR register */
7226 OP_oRRnpc
, /* ARM register, not the PC */
7227 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7228 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7229 OP_oRND
, /* Optional Neon double precision register */
7230 OP_oRNQ
, /* Optional Neon quad precision register */
7231 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7232 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7233 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7234 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7236 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7238 OP_oSHll
, /* LSL immediate */
7239 OP_oSHar
, /* ASR immediate */
7240 OP_oSHllar
, /* LSL or ASR immediate */
7241 OP_oROR
, /* ROR 0/8/16/24 */
7242 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7244 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7246 /* Some pre-defined mixed (ARM/THUMB) operands. */
7247 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7248 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7249 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7251 OP_FIRST_OPTIONAL
= OP_oI7b
7254 /* Generic instruction operand parser. This does no encoding and no
7255 semantic validation; it merely squirrels values away in the inst
7256 structure. Returns SUCCESS or FAIL depending on whether the
7257 specified grammar matched. */
7259 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7261 unsigned const int *upat
= pattern
;
7262 char *backtrack_pos
= 0;
7263 const char *backtrack_error
= 0;
7264 int i
, val
= 0, backtrack_index
= 0;
7265 enum arm_reg_type rtype
;
7266 parse_operand_result result
;
7267 unsigned int op_parse_code
;
7268 bfd_boolean partial_match
;
7270 #define po_char_or_fail(chr) \
7273 if (skip_past_char (&str, chr) == FAIL) \
7278 #define po_reg_or_fail(regtype) \
7281 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7282 & inst.operands[i].vectype); \
7285 first_error (_(reg_expected_msgs[regtype])); \
7288 inst.operands[i].reg = val; \
7289 inst.operands[i].isreg = 1; \
7290 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7291 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7292 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7293 || rtype == REG_TYPE_VFD \
7294 || rtype == REG_TYPE_NQ); \
7295 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7299 #define po_reg_or_goto(regtype, label) \
7302 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7303 & inst.operands[i].vectype); \
7307 inst.operands[i].reg = val; \
7308 inst.operands[i].isreg = 1; \
7309 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7310 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7311 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7312 || rtype == REG_TYPE_VFD \
7313 || rtype == REG_TYPE_NQ); \
7314 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7318 #define po_imm_or_fail(min, max, popt) \
7321 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7323 inst.operands[i].imm = val; \
7327 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7331 my_get_expression (&exp, &str, popt); \
7332 if (exp.X_op != O_constant) \
7334 inst.error = _("constant expression required"); \
7337 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7339 inst.error = _("immediate value 48 or 64 expected"); \
7342 inst.operands[i].imm = exp.X_add_number; \
7346 #define po_scalar_or_goto(elsz, label, reg_type) \
7349 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7353 inst.operands[i].reg = val; \
7354 inst.operands[i].isscalar = 1; \
7358 #define po_misc_or_fail(expr) \
7366 #define po_misc_or_fail_no_backtrack(expr) \
7370 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7371 backtrack_pos = 0; \
7372 if (result != PARSE_OPERAND_SUCCESS) \
7377 #define po_barrier_or_imm(str) \
7380 val = parse_barrier (&str); \
7381 if (val == FAIL && ! ISALPHA (*str)) \
7384 /* ISB can only take SY as an option. */ \
7385 || ((inst.instruction & 0xf0) == 0x60 \
7388 inst.error = _("invalid barrier type"); \
7389 backtrack_pos = 0; \
7395 skip_whitespace (str
);
7397 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7399 op_parse_code
= upat
[i
];
7400 if (op_parse_code
>= 1<<16)
7401 op_parse_code
= thumb
? (op_parse_code
>> 16)
7402 : (op_parse_code
& ((1<<16)-1));
7404 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7406 /* Remember where we are in case we need to backtrack. */
7407 backtrack_pos
= str
;
7408 backtrack_error
= inst
.error
;
7409 backtrack_index
= i
;
7412 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7413 po_char_or_fail (',');
7415 switch (op_parse_code
)
7427 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7428 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7429 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7430 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7431 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7432 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7435 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7439 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7443 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7446 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7448 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7450 /* Also accept generic coprocessor regs for unknown registers. */
7452 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7454 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7455 existing register with a value of 0, this seems like the
7456 best way to parse P0. */
7458 if (strncasecmp (str
, "P0", 2) == 0)
7461 inst
.operands
[i
].isreg
= 1;
7462 inst
.operands
[i
].reg
= 13;
7467 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7468 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7469 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7470 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7471 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7472 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7473 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7474 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7475 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7476 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7479 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7482 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7483 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7485 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7490 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7494 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7496 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7499 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7501 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7505 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7508 po_reg_or_fail (REG_TYPE_MQ
);
7511 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7513 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7518 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7521 po_reg_or_fail (REG_TYPE_NSDQ
);
7525 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7529 po_reg_or_fail (REG_TYPE_MQ
);
7531 /* Neon scalar. Using an element size of 8 means that some invalid
7532 scalars are accepted here, so deal with those in later code. */
7533 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7537 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7540 po_imm_or_fail (0, 0, TRUE
);
7545 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7549 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7554 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7557 if (parse_ifimm_zero (&str
))
7558 inst
.operands
[i
].imm
= 0;
7562 = _("only floating point zero is allowed as immediate value");
7570 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7573 po_reg_or_fail (REG_TYPE_RN
);
7577 case OP_RNSDQ_RNSC_MQ_RR
:
7578 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7581 case OP_RNSDQ_RNSC_MQ
:
7582 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7587 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7591 po_reg_or_fail (REG_TYPE_NSDQ
);
7598 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7601 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7604 po_reg_or_fail (REG_TYPE_NSD
);
7608 case OP_RNDQMQ_RNSC_RR
:
7609 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7612 case OP_RNDQ_RNSC_RR
:
7613 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7615 case OP_RNDQMQ_RNSC
:
7616 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7621 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7624 po_reg_or_fail (REG_TYPE_NDQ
);
7630 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7633 po_reg_or_fail (REG_TYPE_VFD
);
7638 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7639 not careful then bad things might happen. */
7640 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7643 case OP_RNDQMQ_Ibig
:
7644 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7649 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7652 /* There's a possibility of getting a 64-bit immediate here, so
7653 we need special handling. */
7654 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7657 inst
.error
= _("immediate value is out of range");
7663 case OP_RNDQMQ_I63b_RR
:
7664 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7667 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7672 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7675 po_imm_or_fail (0, 63, TRUE
);
7680 po_char_or_fail ('[');
7681 po_reg_or_fail (REG_TYPE_RN
);
7682 po_char_or_fail (']');
7688 po_reg_or_fail (REG_TYPE_RN
);
7689 if (skip_past_char (&str
, '!') == SUCCESS
)
7690 inst
.operands
[i
].writeback
= 1;
7694 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7695 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7696 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7697 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7698 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7699 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7700 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7701 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7702 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7703 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7704 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7705 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7706 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7707 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7708 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7709 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7710 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7711 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7713 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7714 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7716 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7717 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7718 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7719 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7721 /* Immediate variants */
7723 po_char_or_fail ('{');
7724 po_imm_or_fail (0, 255, TRUE
);
7725 po_char_or_fail ('}');
7729 /* The expression parser chokes on a trailing !, so we have
7730 to find it first and zap it. */
7733 while (*s
&& *s
!= ',')
7738 inst
.operands
[i
].writeback
= 1;
7740 po_imm_or_fail (0, 31, TRUE
);
7748 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7753 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7758 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7760 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7762 val
= parse_reloc (&str
);
7765 inst
.error
= _("unrecognized relocation suffix");
7768 else if (val
!= BFD_RELOC_UNUSED
)
7770 inst
.operands
[i
].imm
= val
;
7771 inst
.operands
[i
].hasreloc
= 1;
7777 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7779 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7781 inst
.operands
[i
].hasreloc
= 1;
7783 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7785 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7786 inst
.operands
[i
].hasreloc
= 0;
7790 /* Operand for MOVW or MOVT. */
7792 po_misc_or_fail (parse_half (&str
));
7795 /* Register or expression. */
7796 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7797 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7799 /* Register or immediate. */
7800 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7801 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7803 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7804 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7806 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7808 if (!is_immediate_prefix (*str
))
7811 val
= parse_fpa_immediate (&str
);
7814 /* FPA immediates are encoded as registers 8-15.
7815 parse_fpa_immediate has already applied the offset. */
7816 inst
.operands
[i
].reg
= val
;
7817 inst
.operands
[i
].isreg
= 1;
7820 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7821 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7823 /* Two kinds of register. */
7826 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7828 || (rege
->type
!= REG_TYPE_MMXWR
7829 && rege
->type
!= REG_TYPE_MMXWC
7830 && rege
->type
!= REG_TYPE_MMXWCG
))
7832 inst
.error
= _("iWMMXt data or control register expected");
7835 inst
.operands
[i
].reg
= rege
->number
;
7836 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7842 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7844 || (rege
->type
!= REG_TYPE_MMXWC
7845 && rege
->type
!= REG_TYPE_MMXWCG
))
7847 inst
.error
= _("iWMMXt control register expected");
7850 inst
.operands
[i
].reg
= rege
->number
;
7851 inst
.operands
[i
].isreg
= 1;
7856 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7857 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7858 case OP_oROR
: val
= parse_ror (&str
); break;
7860 case OP_COND
: val
= parse_cond (&str
); break;
7861 case OP_oBARRIER_I15
:
7862 po_barrier_or_imm (str
); break;
7864 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7870 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7871 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7873 inst
.error
= _("Banked registers are not available with this "
7879 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7883 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7886 val
= parse_sys_vldr_vstr (&str
);
7890 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7893 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7895 if (strncasecmp (str
, "APSR_", 5) == 0)
7902 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7903 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7904 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7905 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7906 default: found
= 16;
7910 inst
.operands
[i
].isvec
= 1;
7911 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7912 inst
.operands
[i
].reg
= REG_PC
;
7919 po_misc_or_fail (parse_tb (&str
));
7922 /* Register lists. */
7924 val
= parse_reg_list (&str
, REGLIST_RN
);
7927 inst
.operands
[i
].writeback
= 1;
7933 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7937 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7942 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7947 /* Allow Q registers too. */
7948 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7949 REGLIST_NEON_D
, &partial_match
);
7953 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7954 REGLIST_VFP_S
, &partial_match
);
7955 inst
.operands
[i
].issingle
= 1;
7960 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7961 REGLIST_VFP_D_VPR
, &partial_match
);
7962 if (val
== FAIL
&& !partial_match
)
7965 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7966 REGLIST_VFP_S_VPR
, &partial_match
);
7967 inst
.operands
[i
].issingle
= 1;
7972 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7973 REGLIST_NEON_D
, &partial_match
);
7978 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7979 1, &inst
.operands
[i
].vectype
);
7980 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7984 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7985 0, &inst
.operands
[i
].vectype
);
7988 /* Addressing modes */
7990 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7994 po_misc_or_fail (parse_address (&str
, i
));
7998 po_misc_or_fail_no_backtrack (
7999 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
8003 po_misc_or_fail_no_backtrack (
8004 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
8008 po_misc_or_fail_no_backtrack (
8009 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8013 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8017 po_misc_or_fail_no_backtrack (
8018 parse_shifter_operand_group_reloc (&str
, i
));
8022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8026 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8030 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8035 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8040 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8043 po_reg_or_fail (REG_TYPE_ZR
);
8047 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8050 /* Various value-based sanity checks and shared operations. We
8051 do not signal immediate failures for the register constraints;
8052 this allows a syntax error to take precedence. */
8053 switch (op_parse_code
)
8061 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8062 inst
.error
= BAD_PC
;
8067 case OP_RRnpcsp_I32
:
8068 if (inst
.operands
[i
].isreg
)
8070 if (inst
.operands
[i
].reg
== REG_PC
)
8071 inst
.error
= BAD_PC
;
8072 else if (inst
.operands
[i
].reg
== REG_SP
8073 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8074 relaxed since ARMv8-A. */
8075 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8078 inst
.error
= BAD_SP
;
8084 if (inst
.operands
[i
].isreg
8085 && inst
.operands
[i
].reg
== REG_PC
8086 && (inst
.operands
[i
].writeback
|| thumb
))
8087 inst
.error
= BAD_PC
;
8092 if (inst
.operands
[i
].isreg
)
8102 case OP_oBARRIER_I15
:
8115 inst
.operands
[i
].imm
= val
;
8120 if (inst
.operands
[i
].reg
!= REG_LR
)
8121 inst
.error
= _("operand must be LR register");
8127 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8128 inst
.error
= BAD_PC
;
8132 if (inst
.operands
[i
].isreg
8133 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8134 inst
.error
= BAD_ODD
;
8138 if (inst
.operands
[i
].isreg
)
8140 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8141 inst
.error
= BAD_EVEN
;
8142 else if (inst
.operands
[i
].reg
== REG_SP
)
8143 as_tsktsk (MVE_BAD_SP
);
8144 else if (inst
.operands
[i
].reg
== REG_PC
)
8145 inst
.error
= BAD_PC
;
8153 /* If we get here, this operand was successfully parsed. */
8154 inst
.operands
[i
].present
= 1;
8158 inst
.error
= BAD_ARGS
;
8163 /* The parse routine should already have set inst.error, but set a
8164 default here just in case. */
8166 inst
.error
= BAD_SYNTAX
;
8170 /* Do not backtrack over a trailing optional argument that
8171 absorbed some text. We will only fail again, with the
8172 'garbage following instruction' error message, which is
8173 probably less helpful than the current one. */
8174 if (backtrack_index
== i
&& backtrack_pos
!= str
8175 && upat
[i
+1] == OP_stop
)
8178 inst
.error
= BAD_SYNTAX
;
8182 /* Try again, skipping the optional argument at backtrack_pos. */
8183 str
= backtrack_pos
;
8184 inst
.error
= backtrack_error
;
8185 inst
.operands
[backtrack_index
].present
= 0;
8186 i
= backtrack_index
;
8190 /* Check that we have parsed all the arguments. */
8191 if (*str
!= '\0' && !inst
.error
)
8192 inst
.error
= _("garbage following instruction");
8194 return inst
.error
? FAIL
: SUCCESS
;
8197 #undef po_char_or_fail
8198 #undef po_reg_or_fail
8199 #undef po_reg_or_goto
8200 #undef po_imm_or_fail
8201 #undef po_scalar_or_fail
8202 #undef po_barrier_or_imm
8204 /* Shorthand macro for instruction encoding functions issuing errors. */
8205 #define constraint(expr, err) \
8216 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8217 instructions are unpredictable if these registers are used. This
8218 is the BadReg predicate in ARM's Thumb-2 documentation.
8220 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8221 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8222 #define reject_bad_reg(reg) \
8224 if (reg == REG_PC) \
8226 inst.error = BAD_PC; \
8229 else if (reg == REG_SP \
8230 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8232 inst.error = BAD_SP; \
8237 /* If REG is R13 (the stack pointer), warn that its use is
8239 #define warn_deprecated_sp(reg) \
8241 if (warn_on_deprecated && reg == REG_SP) \
8242 as_tsktsk (_("use of r13 is deprecated")); \
8245 /* Functions for operand encoding. ARM, then Thumb. */
8247 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8249 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8251 The only binary encoding difference is the Coprocessor number. Coprocessor
8252 9 is used for half-precision calculations or conversions. The format of the
8253 instruction is the same as the equivalent Coprocessor 10 instruction that
8254 exists for Single-Precision operation. */
8257 do_scalar_fp16_v82_encode (void)
8259 if (inst
.cond
< COND_ALWAYS
)
8260 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8261 " the behaviour is UNPREDICTABLE"));
8262 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8265 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8266 mark_feature_used (&arm_ext_fp16
);
8269 /* If VAL can be encoded in the immediate field of an ARM instruction,
8270 return the encoded form. Otherwise, return FAIL. */
8273 encode_arm_immediate (unsigned int val
)
8280 for (i
= 2; i
< 32; i
+= 2)
8281 if ((a
= rotate_left (val
, i
)) <= 0xff)
8282 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8287 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8288 return the encoded form. Otherwise, return FAIL. */
8290 encode_thumb32_immediate (unsigned int val
)
8297 for (i
= 1; i
<= 24; i
++)
8300 if ((val
& ~(0xffU
<< i
)) == 0)
8301 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8305 if (val
== ((a
<< 16) | a
))
8307 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8311 if (val
== ((a
<< 16) | a
))
8312 return 0x200 | (a
>> 8);
8316 /* Encode a VFP SP or DP register number into inst.instruction. */
8319 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8321 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8324 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8327 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8330 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8335 first_error (_("D register out of range for selected VFP version"));
8343 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8347 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8351 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8355 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8359 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8363 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8371 /* Encode a <shift> in an ARM-format instruction. The immediate,
8372 if any, is handled by md_apply_fix. */
8374 encode_arm_shift (int i
)
8376 /* register-shifted register. */
8377 if (inst
.operands
[i
].immisreg
)
8380 for (op_index
= 0; op_index
<= i
; ++op_index
)
8382 /* Check the operand only when it's presented. In pre-UAL syntax,
8383 if the destination register is the same as the first operand, two
8384 register form of the instruction can be used. */
8385 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8386 && inst
.operands
[op_index
].reg
== REG_PC
)
8387 as_warn (UNPRED_REG ("r15"));
8390 if (inst
.operands
[i
].imm
== REG_PC
)
8391 as_warn (UNPRED_REG ("r15"));
8394 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8395 inst
.instruction
|= SHIFT_ROR
<< 5;
8398 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8399 if (inst
.operands
[i
].immisreg
)
8401 inst
.instruction
|= SHIFT_BY_REG
;
8402 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8405 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8410 encode_arm_shifter_operand (int i
)
8412 if (inst
.operands
[i
].isreg
)
8414 inst
.instruction
|= inst
.operands
[i
].reg
;
8415 encode_arm_shift (i
);
8419 inst
.instruction
|= INST_IMMEDIATE
;
8420 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8421 inst
.instruction
|= inst
.operands
[i
].imm
;
8425 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8427 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8430 Generate an error if the operand is not a register. */
8431 constraint (!inst
.operands
[i
].isreg
,
8432 _("Instruction does not support =N addresses"));
8434 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8436 if (inst
.operands
[i
].preind
)
8440 inst
.error
= _("instruction does not accept preindexed addressing");
8443 inst
.instruction
|= PRE_INDEX
;
8444 if (inst
.operands
[i
].writeback
)
8445 inst
.instruction
|= WRITE_BACK
;
8448 else if (inst
.operands
[i
].postind
)
8450 gas_assert (inst
.operands
[i
].writeback
);
8452 inst
.instruction
|= WRITE_BACK
;
8454 else /* unindexed - only for coprocessor */
8456 inst
.error
= _("instruction does not accept unindexed addressing");
8460 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8461 && (((inst
.instruction
& 0x000f0000) >> 16)
8462 == ((inst
.instruction
& 0x0000f000) >> 12)))
8463 as_warn ((inst
.instruction
& LOAD_BIT
)
8464 ? _("destination register same as write-back base")
8465 : _("source register same as write-back base"));
8468 /* inst.operands[i] was set up by parse_address. Encode it into an
8469 ARM-format mode 2 load or store instruction. If is_t is true,
8470 reject forms that cannot be used with a T instruction (i.e. not
8473 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8475 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8477 encode_arm_addr_mode_common (i
, is_t
);
8479 if (inst
.operands
[i
].immisreg
)
8481 constraint ((inst
.operands
[i
].imm
== REG_PC
8482 || (is_pc
&& inst
.operands
[i
].writeback
)),
8484 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8485 inst
.instruction
|= inst
.operands
[i
].imm
;
8486 if (!inst
.operands
[i
].negative
)
8487 inst
.instruction
|= INDEX_UP
;
8488 if (inst
.operands
[i
].shifted
)
8490 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8491 inst
.instruction
|= SHIFT_ROR
<< 5;
8494 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8495 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8499 else /* immediate offset in inst.relocs[0] */
8501 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8503 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8505 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8506 cannot use PC in addressing.
8507 PC cannot be used in writeback addressing, either. */
8508 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8511 /* Use of PC in str is deprecated for ARMv7. */
8512 if (warn_on_deprecated
8514 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8515 as_tsktsk (_("use of PC in this instruction is deprecated"));
8518 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8520 /* Prefer + for zero encoded value. */
8521 if (!inst
.operands
[i
].negative
)
8522 inst
.instruction
|= INDEX_UP
;
8523 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8528 /* inst.operands[i] was set up by parse_address. Encode it into an
8529 ARM-format mode 3 load or store instruction. Reject forms that
8530 cannot be used with such instructions. If is_t is true, reject
8531 forms that cannot be used with a T instruction (i.e. not
8534 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8536 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8538 inst
.error
= _("instruction does not accept scaled register index");
8542 encode_arm_addr_mode_common (i
, is_t
);
8544 if (inst
.operands
[i
].immisreg
)
8546 constraint ((inst
.operands
[i
].imm
== REG_PC
8547 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8549 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8551 inst
.instruction
|= inst
.operands
[i
].imm
;
8552 if (!inst
.operands
[i
].negative
)
8553 inst
.instruction
|= INDEX_UP
;
8555 else /* immediate offset in inst.relocs[0] */
8557 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8558 && inst
.operands
[i
].writeback
),
8560 inst
.instruction
|= HWOFFSET_IMM
;
8561 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8563 /* Prefer + for zero encoded value. */
8564 if (!inst
.operands
[i
].negative
)
8565 inst
.instruction
|= INDEX_UP
;
8567 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8572 /* Write immediate bits [7:0] to the following locations:
8574 |28/24|23 19|18 16|15 4|3 0|
8575 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8577 This function is used by VMOV/VMVN/VORR/VBIC. */
8580 neon_write_immbits (unsigned immbits
)
8582 inst
.instruction
|= immbits
& 0xf;
8583 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8584 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8587 /* Invert low-order SIZE bits of XHI:XLO. */
8590 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8592 unsigned immlo
= xlo
? *xlo
: 0;
8593 unsigned immhi
= xhi
? *xhi
: 0;
8598 immlo
= (~immlo
) & 0xff;
8602 immlo
= (~immlo
) & 0xffff;
8606 immhi
= (~immhi
) & 0xffffffff;
8610 immlo
= (~immlo
) & 0xffffffff;
8624 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8628 neon_bits_same_in_bytes (unsigned imm
)
8630 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8631 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8632 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8633 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8636 /* For immediate of above form, return 0bABCD. */
8639 neon_squash_bits (unsigned imm
)
8641 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8642 | ((imm
& 0x01000000) >> 21);
8645 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8648 neon_qfloat_bits (unsigned imm
)
8650 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8653 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8654 the instruction. *OP is passed as the initial value of the op field, and
8655 may be set to a different value depending on the constant (i.e.
8656 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8657 MVN). If the immediate looks like a repeated pattern then also
8658 try smaller element sizes. */
8661 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8662 unsigned *immbits
, int *op
, int size
,
8663 enum neon_el_type type
)
8665 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8667 if (type
== NT_float
&& !float_p
)
8670 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8672 if (size
!= 32 || *op
== 1)
8674 *immbits
= neon_qfloat_bits (immlo
);
8680 if (neon_bits_same_in_bytes (immhi
)
8681 && neon_bits_same_in_bytes (immlo
))
8685 *immbits
= (neon_squash_bits (immhi
) << 4)
8686 | neon_squash_bits (immlo
);
8697 if (immlo
== (immlo
& 0x000000ff))
8702 else if (immlo
== (immlo
& 0x0000ff00))
8704 *immbits
= immlo
>> 8;
8707 else if (immlo
== (immlo
& 0x00ff0000))
8709 *immbits
= immlo
>> 16;
8712 else if (immlo
== (immlo
& 0xff000000))
8714 *immbits
= immlo
>> 24;
8717 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8719 *immbits
= (immlo
>> 8) & 0xff;
8722 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8724 *immbits
= (immlo
>> 16) & 0xff;
8728 if ((immlo
& 0xffff) != (immlo
>> 16))
8735 if (immlo
== (immlo
& 0x000000ff))
8740 else if (immlo
== (immlo
& 0x0000ff00))
8742 *immbits
= immlo
>> 8;
8746 if ((immlo
& 0xff) != (immlo
>> 8))
8751 if (immlo
== (immlo
& 0x000000ff))
8753 /* Don't allow MVN with 8-bit immediate. */
8763 #if defined BFD_HOST_64_BIT
8764 /* Returns TRUE if double precision value V may be cast
8765 to single precision without loss of accuracy. */
8768 is_double_a_single (bfd_uint64_t v
)
8770 int exp
= (v
>> 52) & 0x7FF;
8771 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8773 return ((exp
== 0 || exp
== 0x7FF
8774 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8775 && (mantissa
& 0x1FFFFFFFL
) == 0);
8778 /* Returns a double precision value casted to single precision
8779 (ignoring the least significant bits in exponent and mantissa). */
8782 double_to_single (bfd_uint64_t v
)
8784 unsigned int sign
= (v
>> 63) & 1;
8785 int exp
= (v
>> 52) & 0x7FF;
8786 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8792 exp
= exp
- 1023 + 127;
8801 /* No denormalized numbers. */
8807 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8809 #endif /* BFD_HOST_64_BIT */
8818 static void do_vfp_nsyn_opcode (const char *);
8820 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8821 Determine whether it can be performed with a move instruction; if
8822 it can, convert inst.instruction to that move instruction and
8823 return TRUE; if it can't, convert inst.instruction to a literal-pool
8824 load and return FALSE. If this is not a valid thing to do in the
8825 current context, set inst.error and return TRUE.
8827 inst.operands[i] describes the destination register. */
8830 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8833 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8834 bfd_boolean arm_p
= (t
== CONST_ARM
);
8837 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8841 if ((inst
.instruction
& tbit
) == 0)
8843 inst
.error
= _("invalid pseudo operation");
8847 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8848 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8849 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8851 inst
.error
= _("constant expression expected");
8855 if (inst
.relocs
[0].exp
.X_op
== O_constant
8856 || inst
.relocs
[0].exp
.X_op
== O_big
)
8858 #if defined BFD_HOST_64_BIT
8863 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8865 LITTLENUM_TYPE w
[X_PRECISION
];
8868 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8870 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8872 /* FIXME: Should we check words w[2..5] ? */
8877 #if defined BFD_HOST_64_BIT
8878 v
= l
[3] & LITTLENUM_MASK
;
8879 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8880 v
|= l
[2] & LITTLENUM_MASK
;
8881 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8882 v
|= l
[1] & LITTLENUM_MASK
;
8883 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8884 v
|= l
[0] & LITTLENUM_MASK
;
8886 v
= l
[1] & LITTLENUM_MASK
;
8887 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8888 v
|= l
[0] & LITTLENUM_MASK
;
8892 v
= inst
.relocs
[0].exp
.X_add_number
;
8894 if (!inst
.operands
[i
].issingle
)
8898 /* LDR should not use lead in a flag-setting instruction being
8899 chosen so we do not check whether movs can be used. */
8901 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8902 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8903 && inst
.operands
[i
].reg
!= 13
8904 && inst
.operands
[i
].reg
!= 15)
8906 /* Check if on thumb2 it can be done with a mov.w, mvn or
8907 movw instruction. */
8908 unsigned int newimm
;
8909 bfd_boolean isNegated
= FALSE
;
8911 newimm
= encode_thumb32_immediate (v
);
8912 if (newimm
== (unsigned int) FAIL
)
8914 newimm
= encode_thumb32_immediate (~v
);
8918 /* The number can be loaded with a mov.w or mvn
8920 if (newimm
!= (unsigned int) FAIL
8921 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8923 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8924 | (inst
.operands
[i
].reg
<< 8));
8925 /* Change to MOVN. */
8926 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8927 inst
.instruction
|= (newimm
& 0x800) << 15;
8928 inst
.instruction
|= (newimm
& 0x700) << 4;
8929 inst
.instruction
|= (newimm
& 0x0ff);
8932 /* The number can be loaded with a movw instruction. */
8933 else if ((v
& ~0xFFFF) == 0
8934 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8936 int imm
= v
& 0xFFFF;
8938 inst
.instruction
= 0xf2400000; /* MOVW. */
8939 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8940 inst
.instruction
|= (imm
& 0xf000) << 4;
8941 inst
.instruction
|= (imm
& 0x0800) << 15;
8942 inst
.instruction
|= (imm
& 0x0700) << 4;
8943 inst
.instruction
|= (imm
& 0x00ff);
8944 /* In case this replacement is being done on Armv8-M
8945 Baseline we need to make sure to disable the
8946 instruction size check, as otherwise GAS will reject
8947 the use of this T32 instruction. */
8955 int value
= encode_arm_immediate (v
);
8959 /* This can be done with a mov instruction. */
8960 inst
.instruction
&= LITERAL_MASK
;
8961 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8962 inst
.instruction
|= value
& 0xfff;
8966 value
= encode_arm_immediate (~ v
);
8969 /* This can be done with a mvn instruction. */
8970 inst
.instruction
&= LITERAL_MASK
;
8971 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8972 inst
.instruction
|= value
& 0xfff;
8976 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8979 unsigned immbits
= 0;
8980 unsigned immlo
= inst
.operands
[1].imm
;
8981 unsigned immhi
= inst
.operands
[1].regisimm
8982 ? inst
.operands
[1].reg
8983 : inst
.relocs
[0].exp
.X_unsigned
8985 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8986 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8987 &op
, 64, NT_invtype
);
8991 neon_invert_size (&immlo
, &immhi
, 64);
8993 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8994 &op
, 64, NT_invtype
);
8999 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
9005 /* Fill other bits in vmov encoding for both thumb and arm. */
9007 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9009 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9010 neon_write_immbits (immbits
);
9018 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9019 if (inst
.operands
[i
].issingle
9020 && is_quarter_float (inst
.operands
[1].imm
)
9021 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9023 inst
.operands
[1].imm
=
9024 neon_qfloat_bits (v
);
9025 do_vfp_nsyn_opcode ("fconsts");
9029 /* If our host does not support a 64-bit type then we cannot perform
9030 the following optimization. This mean that there will be a
9031 discrepancy between the output produced by an assembler built for
9032 a 32-bit-only host and the output produced from a 64-bit host, but
9033 this cannot be helped. */
9034 #if defined BFD_HOST_64_BIT
9035 else if (!inst
.operands
[1].issingle
9036 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9038 if (is_double_a_single (v
)
9039 && is_quarter_float (double_to_single (v
)))
9041 inst
.operands
[1].imm
=
9042 neon_qfloat_bits (double_to_single (v
));
9043 do_vfp_nsyn_opcode ("fconstd");
9051 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9052 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9055 inst
.operands
[1].reg
= REG_PC
;
9056 inst
.operands
[1].isreg
= 1;
9057 inst
.operands
[1].preind
= 1;
9058 inst
.relocs
[0].pc_rel
= 1;
9059 inst
.relocs
[0].type
= (thumb_p
9060 ? BFD_RELOC_ARM_THUMB_OFFSET
9062 ? BFD_RELOC_ARM_HWLITERAL
9063 : BFD_RELOC_ARM_LITERAL
));
9067 /* inst.operands[i] was set up by parse_address. Encode it into an
9068 ARM-format instruction. Reject all forms which cannot be encoded
9069 into a coprocessor load/store instruction. If wb_ok is false,
9070 reject use of writeback; if unind_ok is false, reject use of
9071 unindexed addressing. If reloc_override is not 0, use it instead
9072 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9073 (in which case it is preserved). */
9076 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9078 if (!inst
.operands
[i
].isreg
)
9081 if (! inst
.operands
[0].isvec
)
9083 inst
.error
= _("invalid co-processor operand");
9086 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9090 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9092 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9094 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9096 gas_assert (!inst
.operands
[i
].writeback
);
9099 inst
.error
= _("instruction does not support unindexed addressing");
9102 inst
.instruction
|= inst
.operands
[i
].imm
;
9103 inst
.instruction
|= INDEX_UP
;
9107 if (inst
.operands
[i
].preind
)
9108 inst
.instruction
|= PRE_INDEX
;
9110 if (inst
.operands
[i
].writeback
)
9112 if (inst
.operands
[i
].reg
== REG_PC
)
9114 inst
.error
= _("pc may not be used with write-back");
9119 inst
.error
= _("instruction does not support writeback");
9122 inst
.instruction
|= WRITE_BACK
;
9126 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9127 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9128 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9129 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9132 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9134 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9137 /* Prefer + for zero encoded value. */
9138 if (!inst
.operands
[i
].negative
)
9139 inst
.instruction
|= INDEX_UP
;
9144 /* Functions for instruction encoding, sorted by sub-architecture.
9145 First some generics; their names are taken from the conventional
9146 bit positions for register arguments in ARM format instructions. */
9156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9162 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9168 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9169 inst
.instruction
|= inst
.operands
[1].reg
;
9175 inst
.instruction
|= inst
.operands
[0].reg
;
9176 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9182 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9183 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9189 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9190 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9196 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9197 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9201 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9203 if (ARM_CPU_IS_ANY (cpu_variant
))
9205 as_tsktsk ("%s", msg
);
9208 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9220 unsigned Rn
= inst
.operands
[2].reg
;
9221 /* Enforce restrictions on SWP instruction. */
9222 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9224 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9225 _("Rn must not overlap other operands"));
9227 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9229 if (!check_obsolete (&arm_ext_v8
,
9230 _("swp{b} use is obsoleted for ARMv8 and later"))
9231 && warn_on_deprecated
9232 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9233 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9237 inst
.instruction
|= inst
.operands
[1].reg
;
9238 inst
.instruction
|= Rn
<< 16;
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9246 inst
.instruction
|= inst
.operands
[2].reg
;
9252 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9253 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9254 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9255 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9257 inst
.instruction
|= inst
.operands
[0].reg
;
9258 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9259 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9265 inst
.instruction
|= inst
.operands
[0].imm
;
9271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9272 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9275 /* ARM instructions, in alphabetical order by function name (except
9276 that wrapper functions appear immediately after the function they
9279 /* This is a pseudo-op of the form "adr rd, label" to be converted
9280 into a relative address of the form "add rd, pc, #label-.-8". */
9285 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9287 /* Frag hacking will turn this into a sub instruction if the offset turns
9288 out to be negative. */
9289 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9290 inst
.relocs
[0].pc_rel
= 1;
9291 inst
.relocs
[0].exp
.X_add_number
-= 8;
9293 if (support_interwork
9294 && inst
.relocs
[0].exp
.X_op
== O_symbol
9295 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9296 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9297 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9298 inst
.relocs
[0].exp
.X_add_number
|= 1;
9301 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9302 into a relative address of the form:
9303 add rd, pc, #low(label-.-8)"
9304 add rd, rd, #high(label-.-8)" */
9309 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9311 /* Frag hacking will turn this into a sub instruction if the offset turns
9312 out to be negative. */
9313 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9314 inst
.relocs
[0].pc_rel
= 1;
9315 inst
.size
= INSN_SIZE
* 2;
9316 inst
.relocs
[0].exp
.X_add_number
-= 8;
9318 if (support_interwork
9319 && inst
.relocs
[0].exp
.X_op
== O_symbol
9320 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9321 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9322 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9323 inst
.relocs
[0].exp
.X_add_number
|= 1;
9329 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9330 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9332 if (!inst
.operands
[1].present
)
9333 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9335 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9336 encode_arm_shifter_operand (2);
9342 if (inst
.operands
[0].present
)
9343 inst
.instruction
|= inst
.operands
[0].imm
;
9345 inst
.instruction
|= 0xf;
9351 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9352 constraint (msb
> 32, _("bit-field extends past end of register"));
9353 /* The instruction encoding stores the LSB and MSB,
9354 not the LSB and width. */
9355 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9356 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9357 inst
.instruction
|= (msb
- 1) << 16;
9365 /* #0 in second position is alternative syntax for bfc, which is
9366 the same instruction but with REG_PC in the Rm field. */
9367 if (!inst
.operands
[1].isreg
)
9368 inst
.operands
[1].reg
= REG_PC
;
9370 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9371 constraint (msb
> 32, _("bit-field extends past end of register"));
9372 /* The instruction encoding stores the LSB and MSB,
9373 not the LSB and width. */
9374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9375 inst
.instruction
|= inst
.operands
[1].reg
;
9376 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9377 inst
.instruction
|= (msb
- 1) << 16;
9383 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9384 _("bit-field extends past end of register"));
9385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9386 inst
.instruction
|= inst
.operands
[1].reg
;
9387 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9388 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9391 /* ARM V5 breakpoint instruction (argument parse)
9392 BKPT <16 bit unsigned immediate>
9393 Instruction is not conditional.
9394 The bit pattern given in insns[] has the COND_ALWAYS condition,
9395 and it is an error if the caller tried to override that. */
9400 /* Top 12 of 16 bits to bits 19:8. */
9401 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9403 /* Bottom 4 of 16 bits to bits 3:0. */
9404 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9408 encode_branch (int default_reloc
)
9410 if (inst
.operands
[0].hasreloc
)
9412 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9413 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9414 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9415 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9416 ? BFD_RELOC_ARM_PLT32
9417 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9420 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9421 inst
.relocs
[0].pc_rel
= 1;
9428 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9429 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9432 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9439 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9441 if (inst
.cond
== COND_ALWAYS
)
9442 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9444 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9448 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9451 /* ARM V5 branch-link-exchange instruction (argument parse)
9452 BLX <target_addr> ie BLX(1)
9453 BLX{<condition>} <Rm> ie BLX(2)
9454 Unfortunately, there are two different opcodes for this mnemonic.
9455 So, the insns[].value is not used, and the code here zaps values
9456 into inst.instruction.
9457 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9462 if (inst
.operands
[0].isreg
)
9464 /* Arg is a register; the opcode provided by insns[] is correct.
9465 It is not illegal to do "blx pc", just useless. */
9466 if (inst
.operands
[0].reg
== REG_PC
)
9467 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9469 inst
.instruction
|= inst
.operands
[0].reg
;
9473 /* Arg is an address; this instruction cannot be executed
9474 conditionally, and the opcode must be adjusted.
9475 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9476 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9477 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9478 inst
.instruction
= 0xfa000000;
9479 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9486 bfd_boolean want_reloc
;
9488 if (inst
.operands
[0].reg
== REG_PC
)
9489 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9491 inst
.instruction
|= inst
.operands
[0].reg
;
9492 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9493 it is for ARMv4t or earlier. */
9494 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9495 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9496 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9500 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9505 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9509 /* ARM v5TEJ. Jump to Jazelle code. */
9514 if (inst
.operands
[0].reg
== REG_PC
)
9515 as_tsktsk (_("use of r15 in bxj is not really useful"));
9517 inst
.instruction
|= inst
.operands
[0].reg
;
9520 /* Co-processor data operation:
9521 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9522 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9526 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9527 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9528 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9529 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9530 inst
.instruction
|= inst
.operands
[4].reg
;
9531 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9537 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9538 encode_arm_shifter_operand (1);
9541 /* Transfer between coprocessor and ARM registers.
9542 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9547 No special properties. */
9549 struct deprecated_coproc_regs_s
9556 arm_feature_set deprecated
;
9557 arm_feature_set obsoleted
;
9558 const char *dep_msg
;
9559 const char *obs_msg
;
9562 #define DEPR_ACCESS_V8 \
9563 N_("This coprocessor register access is deprecated in ARMv8")
9565 /* Table of all deprecated coprocessor registers. */
9566 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9568 {15, 0, 7, 10, 5, /* CP15DMB. */
9569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9570 DEPR_ACCESS_V8
, NULL
},
9571 {15, 0, 7, 10, 4, /* CP15DSB. */
9572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9573 DEPR_ACCESS_V8
, NULL
},
9574 {15, 0, 7, 5, 4, /* CP15ISB. */
9575 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9576 DEPR_ACCESS_V8
, NULL
},
9577 {14, 6, 1, 0, 0, /* TEEHBR. */
9578 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9579 DEPR_ACCESS_V8
, NULL
},
9580 {14, 6, 0, 0, 0, /* TEECR. */
9581 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9582 DEPR_ACCESS_V8
, NULL
},
9585 #undef DEPR_ACCESS_V8
9587 static const size_t deprecated_coproc_reg_count
=
9588 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9596 Rd
= inst
.operands
[2].reg
;
9599 if (inst
.instruction
== 0xee000010
9600 || inst
.instruction
== 0xfe000010)
9602 reject_bad_reg (Rd
);
9603 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9605 constraint (Rd
== REG_SP
, BAD_SP
);
9610 if (inst
.instruction
== 0xe000010)
9611 constraint (Rd
== REG_PC
, BAD_PC
);
9614 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9616 const struct deprecated_coproc_regs_s
*r
=
9617 deprecated_coproc_regs
+ i
;
9619 if (inst
.operands
[0].reg
== r
->cp
9620 && inst
.operands
[1].imm
== r
->opc1
9621 && inst
.operands
[3].reg
== r
->crn
9622 && inst
.operands
[4].reg
== r
->crm
9623 && inst
.operands
[5].imm
== r
->opc2
)
9625 if (! ARM_CPU_IS_ANY (cpu_variant
)
9626 && warn_on_deprecated
9627 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9628 as_tsktsk ("%s", r
->dep_msg
);
9632 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9633 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9634 inst
.instruction
|= Rd
<< 12;
9635 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9636 inst
.instruction
|= inst
.operands
[4].reg
;
9637 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9640 /* Transfer between coprocessor register and pair of ARM registers.
9641 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9646 Two XScale instructions are special cases of these:
9648 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9649 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9651 Result unpredictable if Rd or Rn is R15. */
9658 Rd
= inst
.operands
[2].reg
;
9659 Rn
= inst
.operands
[3].reg
;
9663 reject_bad_reg (Rd
);
9664 reject_bad_reg (Rn
);
9668 constraint (Rd
== REG_PC
, BAD_PC
);
9669 constraint (Rn
== REG_PC
, BAD_PC
);
9672 /* Only check the MRRC{2} variants. */
9673 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9675 /* If Rd == Rn, error that the operation is
9676 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9677 constraint (Rd
== Rn
, BAD_OVERLAP
);
9680 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9681 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9682 inst
.instruction
|= Rd
<< 12;
9683 inst
.instruction
|= Rn
<< 16;
9684 inst
.instruction
|= inst
.operands
[4].reg
;
9690 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9691 if (inst
.operands
[1].present
)
9693 inst
.instruction
|= CPSI_MMOD
;
9694 inst
.instruction
|= inst
.operands
[1].imm
;
9701 inst
.instruction
|= inst
.operands
[0].imm
;
9707 unsigned Rd
, Rn
, Rm
;
9709 Rd
= inst
.operands
[0].reg
;
9710 Rn
= (inst
.operands
[1].present
9711 ? inst
.operands
[1].reg
: Rd
);
9712 Rm
= inst
.operands
[2].reg
;
9714 constraint ((Rd
== REG_PC
), BAD_PC
);
9715 constraint ((Rn
== REG_PC
), BAD_PC
);
9716 constraint ((Rm
== REG_PC
), BAD_PC
);
9718 inst
.instruction
|= Rd
<< 16;
9719 inst
.instruction
|= Rn
<< 0;
9720 inst
.instruction
|= Rm
<< 8;
9726 /* There is no IT instruction in ARM mode. We
9727 process it to do the validation as if in
9728 thumb mode, just in case the code gets
9729 assembled for thumb using the unified syntax. */
9734 set_pred_insn_type (IT_INSN
);
9735 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9736 now_pred
.cc
= inst
.operands
[0].imm
;
9740 /* If there is only one register in the register list,
9741 then return its register number. Otherwise return -1. */
9743 only_one_reg_in_list (int range
)
9745 int i
= ffs (range
) - 1;
9746 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9750 encode_ldmstm(int from_push_pop_mnem
)
9752 int base_reg
= inst
.operands
[0].reg
;
9753 int range
= inst
.operands
[1].imm
;
9756 inst
.instruction
|= base_reg
<< 16;
9757 inst
.instruction
|= range
;
9759 if (inst
.operands
[1].writeback
)
9760 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9762 if (inst
.operands
[0].writeback
)
9764 inst
.instruction
|= WRITE_BACK
;
9765 /* Check for unpredictable uses of writeback. */
9766 if (inst
.instruction
& LOAD_BIT
)
9768 /* Not allowed in LDM type 2. */
9769 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9770 && ((range
& (1 << REG_PC
)) == 0))
9771 as_warn (_("writeback of base register is UNPREDICTABLE"));
9772 /* Only allowed if base reg not in list for other types. */
9773 else if (range
& (1 << base_reg
))
9774 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9778 /* Not allowed for type 2. */
9779 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9780 as_warn (_("writeback of base register is UNPREDICTABLE"));
9781 /* Only allowed if base reg not in list, or first in list. */
9782 else if ((range
& (1 << base_reg
))
9783 && (range
& ((1 << base_reg
) - 1)))
9784 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9788 /* If PUSH/POP has only one register, then use the A2 encoding. */
9789 one_reg
= only_one_reg_in_list (range
);
9790 if (from_push_pop_mnem
&& one_reg
>= 0)
9792 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9794 if (is_push
&& one_reg
== 13 /* SP */)
9795 /* PR 22483: The A2 encoding cannot be used when
9796 pushing the stack pointer as this is UNPREDICTABLE. */
9799 inst
.instruction
&= A_COND_MASK
;
9800 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9801 inst
.instruction
|= one_reg
<< 12;
9808 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9811 /* ARMv5TE load-consecutive (argument parse)
9820 constraint (inst
.operands
[0].reg
% 2 != 0,
9821 _("first transfer register must be even"));
9822 constraint (inst
.operands
[1].present
9823 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9824 _("can only transfer two consecutive registers"));
9825 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9826 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9828 if (!inst
.operands
[1].present
)
9829 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9831 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9832 register and the first register written; we have to diagnose
9833 overlap between the base and the second register written here. */
9835 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9836 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9837 as_warn (_("base register written back, and overlaps "
9838 "second transfer register"));
9840 if (!(inst
.instruction
& V4_STR_BIT
))
9842 /* For an index-register load, the index register must not overlap the
9843 destination (even if not write-back). */
9844 if (inst
.operands
[2].immisreg
9845 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9846 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9847 as_warn (_("index register overlaps transfer register"));
9849 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9850 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9856 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9857 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9858 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9859 || inst
.operands
[1].negative
9860 /* This can arise if the programmer has written
9862 or if they have mistakenly used a register name as the last
9865 It is very difficult to distinguish between these two cases
9866 because "rX" might actually be a label. ie the register
9867 name has been occluded by a symbol of the same name. So we
9868 just generate a general 'bad addressing mode' type error
9869 message and leave it up to the programmer to discover the
9870 true cause and fix their mistake. */
9871 || (inst
.operands
[1].reg
== REG_PC
),
9874 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9875 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9876 _("offset must be zero in ARM encoding"));
9878 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9882 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9888 constraint (inst
.operands
[0].reg
% 2 != 0,
9889 _("even register required"));
9890 constraint (inst
.operands
[1].present
9891 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9892 _("can only load two consecutive registers"));
9893 /* If op 1 were present and equal to PC, this function wouldn't
9894 have been called in the first place. */
9895 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9898 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9901 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9902 which is not a multiple of four is UNPREDICTABLE. */
9904 check_ldr_r15_aligned (void)
9906 constraint (!(inst
.operands
[1].immisreg
)
9907 && (inst
.operands
[0].reg
== REG_PC
9908 && inst
.operands
[1].reg
== REG_PC
9909 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9910 _("ldr to register 15 must be 4-byte aligned"));
9916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9917 if (!inst
.operands
[1].isreg
)
9918 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9920 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9921 check_ldr_r15_aligned ();
9927 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9929 if (inst
.operands
[1].preind
)
9931 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9932 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9933 _("this instruction requires a post-indexed address"));
9935 inst
.operands
[1].preind
= 0;
9936 inst
.operands
[1].postind
= 1;
9937 inst
.operands
[1].writeback
= 1;
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9940 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9943 /* Halfword and signed-byte load/store operations. */
9948 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9950 if (!inst
.operands
[1].isreg
)
9951 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9953 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9959 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9961 if (inst
.operands
[1].preind
)
9963 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9964 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9965 _("this instruction requires a post-indexed address"));
9967 inst
.operands
[1].preind
= 0;
9968 inst
.operands
[1].postind
= 1;
9969 inst
.operands
[1].writeback
= 1;
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9972 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9975 /* Co-processor register load/store.
9976 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9980 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9981 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9982 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9988 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9989 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9990 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9991 && !(inst
.instruction
& 0x00400000))
9992 as_tsktsk (_("Rd and Rm should be different in mla"));
9994 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9995 inst
.instruction
|= inst
.operands
[1].reg
;
9996 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9997 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10003 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10004 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10005 THUMB1_RELOC_ONLY
);
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 encode_arm_shifter_operand (1);
10010 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10017 top
= (inst
.instruction
& 0x00400000) != 0;
10018 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10019 _(":lower16: not allowed in this instruction"));
10020 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10021 _(":upper16: not allowed in this instruction"));
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10023 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10025 imm
= inst
.relocs
[0].exp
.X_add_number
;
10026 /* The value is in two pieces: 0:11, 16:19. */
10027 inst
.instruction
|= (imm
& 0x00000fff);
10028 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10033 do_vfp_nsyn_mrs (void)
10035 if (inst
.operands
[0].isvec
)
10037 if (inst
.operands
[1].reg
!= 1)
10038 first_error (_("operand 1 must be FPSCR"));
10039 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10040 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10041 do_vfp_nsyn_opcode ("fmstat");
10043 else if (inst
.operands
[1].isvec
)
10044 do_vfp_nsyn_opcode ("fmrx");
10052 do_vfp_nsyn_msr (void)
10054 if (inst
.operands
[0].isvec
)
10055 do_vfp_nsyn_opcode ("fmxr");
10065 unsigned Rt
= inst
.operands
[0].reg
;
10067 if (thumb_mode
&& Rt
== REG_SP
)
10069 inst
.error
= BAD_SP
;
10073 switch (inst
.operands
[1].reg
)
10075 /* MVFR2 is only valid for Armv8-A. */
10077 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10081 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10082 case 1: /* fpscr. */
10083 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10084 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10088 case 14: /* fpcxt_ns. */
10089 case 15: /* fpcxt_s. */
10090 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10091 _("selected processor does not support instruction"));
10094 case 2: /* fpscr_nzcvqc. */
10095 case 12: /* vpr. */
10097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10098 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10099 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10100 _("selected processor does not support instruction"));
10101 if (inst
.operands
[0].reg
!= 2
10102 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10103 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10110 /* APSR_ sets isvec. All other refs to PC are illegal. */
10111 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10113 inst
.error
= BAD_PC
;
10117 /* If we get through parsing the register name, we just insert the number
10118 generated into the instruction without further validation. */
10119 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10120 inst
.instruction
|= (Rt
<< 12);
10126 unsigned Rt
= inst
.operands
[1].reg
;
10129 reject_bad_reg (Rt
);
10130 else if (Rt
== REG_PC
)
10132 inst
.error
= BAD_PC
;
10136 switch (inst
.operands
[0].reg
)
10138 /* MVFR2 is only valid for Armv8-A. */
10140 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10144 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10145 case 1: /* fpcr. */
10146 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10147 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10151 case 14: /* fpcxt_ns. */
10152 case 15: /* fpcxt_s. */
10153 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10154 _("selected processor does not support instruction"));
10157 case 2: /* fpscr_nzcvqc. */
10158 case 12: /* vpr. */
10160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10161 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10162 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10163 _("selected processor does not support instruction"));
10164 if (inst
.operands
[0].reg
!= 2
10165 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10166 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10173 /* If we get through parsing the register name, we just insert the number
10174 generated into the instruction without further validation. */
10175 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10176 inst
.instruction
|= (Rt
<< 12);
10184 if (do_vfp_nsyn_mrs () == SUCCESS
)
10187 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10188 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10190 if (inst
.operands
[1].isreg
)
10192 br
= inst
.operands
[1].reg
;
10193 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10194 as_bad (_("bad register for mrs"));
10198 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10199 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10201 _("'APSR', 'CPSR' or 'SPSR' expected"));
10202 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10205 inst
.instruction
|= br
;
10208 /* Two possible forms:
10209 "{C|S}PSR_<field>, Rm",
10210 "{C|S}PSR_f, #expression". */
10215 if (do_vfp_nsyn_msr () == SUCCESS
)
10218 inst
.instruction
|= inst
.operands
[0].imm
;
10219 if (inst
.operands
[1].isreg
)
10220 inst
.instruction
|= inst
.operands
[1].reg
;
10223 inst
.instruction
|= INST_IMMEDIATE
;
10224 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10225 inst
.relocs
[0].pc_rel
= 0;
10232 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10234 if (!inst
.operands
[2].present
)
10235 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10237 inst
.instruction
|= inst
.operands
[1].reg
;
10238 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10240 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10241 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10242 as_tsktsk (_("Rd and Rm should be different in mul"));
10245 /* Long Multiply Parser
10246 UMULL RdLo, RdHi, Rm, Rs
10247 SMULL RdLo, RdHi, Rm, Rs
10248 UMLAL RdLo, RdHi, Rm, Rs
10249 SMLAL RdLo, RdHi, Rm, Rs. */
10254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10255 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10256 inst
.instruction
|= inst
.operands
[2].reg
;
10257 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10259 /* rdhi and rdlo must be different. */
10260 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10261 as_tsktsk (_("rdhi and rdlo must be different"));
10263 /* rdhi, rdlo and rm must all be different before armv6. */
10264 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10265 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10266 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10267 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10273 if (inst
.operands
[0].present
10274 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10276 /* Architectural NOP hints are CPSR sets with no bits selected. */
10277 inst
.instruction
&= 0xf0000000;
10278 inst
.instruction
|= 0x0320f000;
10279 if (inst
.operands
[0].present
)
10280 inst
.instruction
|= inst
.operands
[0].imm
;
10284 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10285 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10286 Condition defaults to COND_ALWAYS.
10287 Error if Rd, Rn or Rm are R15. */
10292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10294 inst
.instruction
|= inst
.operands
[2].reg
;
10295 if (inst
.operands
[3].present
)
10296 encode_arm_shift (3);
10299 /* ARM V6 PKHTB (Argument Parse). */
10304 if (!inst
.operands
[3].present
)
10306 /* If the shift specifier is omitted, turn the instruction
10307 into pkhbt rd, rm, rn. */
10308 inst
.instruction
&= 0xfff00010;
10309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10310 inst
.instruction
|= inst
.operands
[1].reg
;
10311 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10316 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10317 inst
.instruction
|= inst
.operands
[2].reg
;
10318 encode_arm_shift (3);
10322 /* ARMv5TE: Preload-Cache
10323 MP Extensions: Preload for write
10327 Syntactically, like LDR with B=1, W=0, L=1. */
10332 constraint (!inst
.operands
[0].isreg
,
10333 _("'[' expected after PLD mnemonic"));
10334 constraint (inst
.operands
[0].postind
,
10335 _("post-indexed expression used in preload instruction"));
10336 constraint (inst
.operands
[0].writeback
,
10337 _("writeback used in preload instruction"));
10338 constraint (!inst
.operands
[0].preind
,
10339 _("unindexed addressing used in preload instruction"));
10340 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10343 /* ARMv7: PLI <addr_mode> */
10347 constraint (!inst
.operands
[0].isreg
,
10348 _("'[' expected after PLI mnemonic"));
10349 constraint (inst
.operands
[0].postind
,
10350 _("post-indexed expression used in preload instruction"));
10351 constraint (inst
.operands
[0].writeback
,
10352 _("writeback used in preload instruction"));
10353 constraint (!inst
.operands
[0].preind
,
10354 _("unindexed addressing used in preload instruction"));
10355 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10356 inst
.instruction
&= ~PRE_INDEX
;
10362 constraint (inst
.operands
[0].writeback
,
10363 _("push/pop do not support {reglist}^"));
10364 inst
.operands
[1] = inst
.operands
[0];
10365 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10366 inst
.operands
[0].isreg
= 1;
10367 inst
.operands
[0].writeback
= 1;
10368 inst
.operands
[0].reg
= REG_SP
;
10369 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10372 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10373 word at the specified address and the following word
10375 Unconditionally executed.
10376 Error if Rn is R15. */
10381 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10382 if (inst
.operands
[0].writeback
)
10383 inst
.instruction
|= WRITE_BACK
;
10386 /* ARM V6 ssat (argument parse). */
10391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10392 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10393 inst
.instruction
|= inst
.operands
[2].reg
;
10395 if (inst
.operands
[3].present
)
10396 encode_arm_shift (3);
10399 /* ARM V6 usat (argument parse). */
10404 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10405 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10406 inst
.instruction
|= inst
.operands
[2].reg
;
10408 if (inst
.operands
[3].present
)
10409 encode_arm_shift (3);
10412 /* ARM V6 ssat16 (argument parse). */
10417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10418 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10419 inst
.instruction
|= inst
.operands
[2].reg
;
10425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10426 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10427 inst
.instruction
|= inst
.operands
[2].reg
;
10430 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10431 preserving the other bits.
10433 setend <endian_specifier>, where <endian_specifier> is either
10439 if (warn_on_deprecated
10440 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10441 as_tsktsk (_("setend use is deprecated for ARMv8"));
10443 if (inst
.operands
[0].imm
)
10444 inst
.instruction
|= 0x200;
10450 unsigned int Rm
= (inst
.operands
[1].present
10451 ? inst
.operands
[1].reg
10452 : inst
.operands
[0].reg
);
10454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10455 inst
.instruction
|= Rm
;
10456 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10458 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10459 inst
.instruction
|= SHIFT_BY_REG
;
10460 /* PR 12854: Error on extraneous shifts. */
10461 constraint (inst
.operands
[2].shifted
,
10462 _("extraneous shift as part of operand to shift insn"));
10465 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10471 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10472 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10474 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10475 inst
.relocs
[0].pc_rel
= 0;
10481 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10482 inst
.relocs
[0].pc_rel
= 0;
10488 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10489 inst
.relocs
[0].pc_rel
= 0;
10495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10496 _("selected processor does not support SETPAN instruction"));
10498 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10504 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10505 _("selected processor does not support SETPAN instruction"));
10507 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10510 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10511 SMLAxy{cond} Rd,Rm,Rs,Rn
10512 SMLAWy{cond} Rd,Rm,Rs,Rn
10513 Error if any register is R15. */
10518 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10519 inst
.instruction
|= inst
.operands
[1].reg
;
10520 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10521 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10524 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10525 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10526 Error if any register is R15.
10527 Warning if Rdlo == Rdhi. */
10532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10533 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10534 inst
.instruction
|= inst
.operands
[2].reg
;
10535 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10537 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10538 as_tsktsk (_("rdhi and rdlo must be different"));
10541 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10542 SMULxy{cond} Rd,Rm,Rs
10543 Error if any register is R15. */
10548 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10549 inst
.instruction
|= inst
.operands
[1].reg
;
10550 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10553 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10554 the same for both ARM and Thumb-2. */
10561 if (inst
.operands
[0].present
)
10563 reg
= inst
.operands
[0].reg
;
10564 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10569 inst
.instruction
|= reg
<< 16;
10570 inst
.instruction
|= inst
.operands
[1].imm
;
10571 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10572 inst
.instruction
|= WRITE_BACK
;
10575 /* ARM V6 strex (argument parse). */
10580 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10581 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10582 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10583 || inst
.operands
[2].negative
10584 /* See comment in do_ldrex(). */
10585 || (inst
.operands
[2].reg
== REG_PC
),
10588 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10589 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10591 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10592 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10593 _("offset must be zero in ARM encoding"));
10595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10596 inst
.instruction
|= inst
.operands
[1].reg
;
10597 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10598 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10602 do_t_strexbh (void)
10604 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10605 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10606 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10607 || inst
.operands
[2].negative
,
10610 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10611 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10619 constraint (inst
.operands
[1].reg
% 2 != 0,
10620 _("even register required"));
10621 constraint (inst
.operands
[2].present
10622 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10623 _("can only store two consecutive registers"));
10624 /* If op 2 were present and equal to PC, this function wouldn't
10625 have been called in the first place. */
10626 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10628 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10629 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10630 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10634 inst
.instruction
|= inst
.operands
[1].reg
;
10635 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10642 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10643 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10651 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10652 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10657 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10658 extends it to 32-bits, and adds the result to a value in another
10659 register. You can specify a rotation by 0, 8, 16, or 24 bits
10660 before extracting the 16-bit value.
10661 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10662 Condition defaults to COND_ALWAYS.
10663 Error if any register uses R15. */
10668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10669 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10670 inst
.instruction
|= inst
.operands
[2].reg
;
10671 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10676 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10677 Condition defaults to COND_ALWAYS.
10678 Error if any register uses R15. */
10683 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10684 inst
.instruction
|= inst
.operands
[1].reg
;
10685 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10688 /* VFP instructions. In a logical order: SP variant first, monad
10689 before dyad, arithmetic then move then load/store. */
10692 do_vfp_sp_monadic (void)
10694 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10695 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10698 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10703 do_vfp_sp_dyadic (void)
10705 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10706 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10707 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10711 do_vfp_sp_compare_z (void)
10713 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10717 do_vfp_dp_sp_cvt (void)
10719 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10720 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10724 do_vfp_sp_dp_cvt (void)
10726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10727 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10731 do_vfp_reg_from_sp (void)
10733 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10734 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10738 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10742 do_vfp_reg2_from_sp2 (void)
10744 constraint (inst
.operands
[2].imm
!= 2,
10745 _("only two consecutive VFP SP registers allowed here"));
10746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10747 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10748 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10752 do_vfp_sp_from_reg (void)
10754 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10755 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10758 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10759 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10763 do_vfp_sp2_from_reg2 (void)
10765 constraint (inst
.operands
[0].imm
!= 2,
10766 _("only two consecutive VFP SP registers allowed here"));
10767 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10768 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10769 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10773 do_vfp_sp_ldst (void)
10775 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10776 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10780 do_vfp_dp_ldst (void)
10782 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10783 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10788 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10790 if (inst
.operands
[0].writeback
)
10791 inst
.instruction
|= WRITE_BACK
;
10793 constraint (ldstm_type
!= VFP_LDSTMIA
,
10794 _("this addressing mode requires base-register writeback"));
10795 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10796 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10797 inst
.instruction
|= inst
.operands
[1].imm
;
10801 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10805 if (inst
.operands
[0].writeback
)
10806 inst
.instruction
|= WRITE_BACK
;
10808 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10809 _("this addressing mode requires base-register writeback"));
10811 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10812 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10814 count
= inst
.operands
[1].imm
<< 1;
10815 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10818 inst
.instruction
|= count
;
10822 do_vfp_sp_ldstmia (void)
10824 vfp_sp_ldstm (VFP_LDSTMIA
);
10828 do_vfp_sp_ldstmdb (void)
10830 vfp_sp_ldstm (VFP_LDSTMDB
);
10834 do_vfp_dp_ldstmia (void)
10836 vfp_dp_ldstm (VFP_LDSTMIA
);
10840 do_vfp_dp_ldstmdb (void)
10842 vfp_dp_ldstm (VFP_LDSTMDB
);
10846 do_vfp_xp_ldstmia (void)
10848 vfp_dp_ldstm (VFP_LDSTMIAX
);
10852 do_vfp_xp_ldstmdb (void)
10854 vfp_dp_ldstm (VFP_LDSTMDBX
);
10858 do_vfp_dp_rd_rm (void)
10860 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10861 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10865 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10869 do_vfp_dp_rn_rd (void)
10871 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10872 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10876 do_vfp_dp_rd_rn (void)
10878 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10879 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10883 do_vfp_dp_rd_rn_rm (void)
10885 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10886 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10889 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10890 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10891 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10895 do_vfp_dp_rd (void)
10897 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10901 do_vfp_dp_rm_rd_rn (void)
10903 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10904 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10907 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10908 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10909 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10912 /* VFPv3 instructions. */
10914 do_vfp_sp_const (void)
10916 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10917 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10918 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10922 do_vfp_dp_const (void)
10924 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10925 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10926 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10930 vfp_conv (int srcsize
)
10932 int immbits
= srcsize
- inst
.operands
[1].imm
;
10934 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10936 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10937 i.e. immbits must be in range 0 - 16. */
10938 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10941 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10943 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10944 i.e. immbits must be in range 0 - 31. */
10945 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10949 inst
.instruction
|= (immbits
& 1) << 5;
10950 inst
.instruction
|= (immbits
>> 1);
10954 do_vfp_sp_conv_16 (void)
10956 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10961 do_vfp_dp_conv_16 (void)
10963 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10968 do_vfp_sp_conv_32 (void)
10970 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10975 do_vfp_dp_conv_32 (void)
10977 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10981 /* FPA instructions. Also in a logical order. */
10986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10987 inst
.instruction
|= inst
.operands
[1].reg
;
10991 do_fpa_ldmstm (void)
10993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10994 switch (inst
.operands
[1].imm
)
10996 case 1: inst
.instruction
|= CP_T_X
; break;
10997 case 2: inst
.instruction
|= CP_T_Y
; break;
10998 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
11003 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
11005 /* The instruction specified "ea" or "fd", so we can only accept
11006 [Rn]{!}. The instruction does not really support stacking or
11007 unstacking, so we have to emulate these by setting appropriate
11008 bits and offsets. */
11009 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11010 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11011 _("this instruction does not support indexing"));
11013 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11014 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11016 if (!(inst
.instruction
& INDEX_UP
))
11017 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11019 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11021 inst
.operands
[2].preind
= 0;
11022 inst
.operands
[2].postind
= 1;
11026 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11029 /* iWMMXt instructions: strictly in alphabetical order. */
11032 do_iwmmxt_tandorc (void)
11034 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11038 do_iwmmxt_textrc (void)
11040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11041 inst
.instruction
|= inst
.operands
[1].imm
;
11045 do_iwmmxt_textrm (void)
11047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11048 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11049 inst
.instruction
|= inst
.operands
[2].imm
;
11053 do_iwmmxt_tinsr (void)
11055 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11056 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11057 inst
.instruction
|= inst
.operands
[2].imm
;
11061 do_iwmmxt_tmia (void)
11063 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11064 inst
.instruction
|= inst
.operands
[1].reg
;
11065 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11069 do_iwmmxt_waligni (void)
11071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11072 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11073 inst
.instruction
|= inst
.operands
[2].reg
;
11074 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11078 do_iwmmxt_wmerge (void)
11080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11082 inst
.instruction
|= inst
.operands
[2].reg
;
11083 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11087 do_iwmmxt_wmov (void)
11089 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11091 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11092 inst
.instruction
|= inst
.operands
[1].reg
;
11096 do_iwmmxt_wldstbh (void)
11099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11101 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11103 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11104 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11108 do_iwmmxt_wldstw (void)
11110 /* RIWR_RIWC clears .isreg for a control register. */
11111 if (!inst
.operands
[0].isreg
)
11113 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11114 inst
.instruction
|= 0xf0000000;
11117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11118 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11122 do_iwmmxt_wldstd (void)
11124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11125 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11126 && inst
.operands
[1].immisreg
)
11128 inst
.instruction
&= ~0x1a000ff;
11129 inst
.instruction
|= (0xfU
<< 28);
11130 if (inst
.operands
[1].preind
)
11131 inst
.instruction
|= PRE_INDEX
;
11132 if (!inst
.operands
[1].negative
)
11133 inst
.instruction
|= INDEX_UP
;
11134 if (inst
.operands
[1].writeback
)
11135 inst
.instruction
|= WRITE_BACK
;
11136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11137 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11138 inst
.instruction
|= inst
.operands
[1].imm
;
11141 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11145 do_iwmmxt_wshufh (void)
11147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11148 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11149 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11150 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11154 do_iwmmxt_wzero (void)
11156 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11157 inst
.instruction
|= inst
.operands
[0].reg
;
11158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11159 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11163 do_iwmmxt_wrwrwr_or_imm5 (void)
11165 if (inst
.operands
[2].isreg
)
11168 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11169 _("immediate operand requires iWMMXt2"));
11171 if (inst
.operands
[2].imm
== 0)
11173 switch ((inst
.instruction
>> 20) & 0xf)
11179 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11180 inst
.operands
[2].imm
= 16;
11181 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11187 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11188 inst
.operands
[2].imm
= 32;
11189 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11196 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11198 wrn
= (inst
.instruction
>> 16) & 0xf;
11199 inst
.instruction
&= 0xff0fff0f;
11200 inst
.instruction
|= wrn
;
11201 /* Bail out here; the instruction is now assembled. */
11206 /* Map 32 -> 0, etc. */
11207 inst
.operands
[2].imm
&= 0x1f;
11208 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11212 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11213 operations first, then control, shift, and load/store. */
11215 /* Insns like "foo X,Y,Z". */
11218 do_mav_triple (void)
11220 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11221 inst
.instruction
|= inst
.operands
[1].reg
;
11222 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11225 /* Insns like "foo W,X,Y,Z".
11226 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11231 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11232 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11233 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11234 inst
.instruction
|= inst
.operands
[3].reg
;
11237 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11239 do_mav_dspsc (void)
11241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11244 /* Maverick shift immediate instructions.
11245 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11246 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11249 do_mav_shift (void)
11251 int imm
= inst
.operands
[2].imm
;
11253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11254 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11256 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11257 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11258 Bit 4 should be 0. */
11259 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11261 inst
.instruction
|= imm
;
11264 /* XScale instructions. Also sorted arithmetic before move. */
11266 /* Xscale multiply-accumulate (argument parse)
11269 MIAxycc acc0,Rm,Rs. */
11274 inst
.instruction
|= inst
.operands
[1].reg
;
11275 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11278 /* Xscale move-accumulator-register (argument parse)
11280 MARcc acc0,RdLo,RdHi. */
11285 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11289 /* Xscale move-register-accumulator (argument parse)
11291 MRAcc RdLo,RdHi,acc0. */
11296 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11301 /* Encoding functions relevant only to Thumb. */
11303 /* inst.operands[i] is a shifted-register operand; encode
11304 it into inst.instruction in the format used by Thumb32. */
11307 encode_thumb32_shifted_operand (int i
)
11309 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11310 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11312 constraint (inst
.operands
[i
].immisreg
,
11313 _("shift by register not allowed in thumb mode"));
11314 inst
.instruction
|= inst
.operands
[i
].reg
;
11315 if (shift
== SHIFT_RRX
)
11316 inst
.instruction
|= SHIFT_ROR
<< 4;
11319 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11320 _("expression too complex"));
11322 constraint (value
> 32
11323 || (value
== 32 && (shift
== SHIFT_LSL
11324 || shift
== SHIFT_ROR
)),
11325 _("shift expression is too large"));
11329 else if (value
== 32)
11332 inst
.instruction
|= shift
<< 4;
11333 inst
.instruction
|= (value
& 0x1c) << 10;
11334 inst
.instruction
|= (value
& 0x03) << 6;
11339 /* inst.operands[i] was set up by parse_address. Encode it into a
11340 Thumb32 format load or store instruction. Reject forms that cannot
11341 be used with such instructions. If is_t is true, reject forms that
11342 cannot be used with a T instruction; if is_d is true, reject forms
11343 that cannot be used with a D instruction. If it is a store insn,
11344 reject PC in Rn. */
11347 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11349 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11351 constraint (!inst
.operands
[i
].isreg
,
11352 _("Instruction does not support =N addresses"));
11354 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11355 if (inst
.operands
[i
].immisreg
)
11357 constraint (is_pc
, BAD_PC_ADDRESSING
);
11358 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11359 constraint (inst
.operands
[i
].negative
,
11360 _("Thumb does not support negative register indexing"));
11361 constraint (inst
.operands
[i
].postind
,
11362 _("Thumb does not support register post-indexing"));
11363 constraint (inst
.operands
[i
].writeback
,
11364 _("Thumb does not support register indexing with writeback"));
11365 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11366 _("Thumb supports only LSL in shifted register indexing"));
11368 inst
.instruction
|= inst
.operands
[i
].imm
;
11369 if (inst
.operands
[i
].shifted
)
11371 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11372 _("expression too complex"));
11373 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11374 || inst
.relocs
[0].exp
.X_add_number
> 3,
11375 _("shift out of range"));
11376 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11378 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11380 else if (inst
.operands
[i
].preind
)
11382 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11383 constraint (is_t
&& inst
.operands
[i
].writeback
,
11384 _("cannot use writeback with this instruction"));
11385 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11386 BAD_PC_ADDRESSING
);
11390 inst
.instruction
|= 0x01000000;
11391 if (inst
.operands
[i
].writeback
)
11392 inst
.instruction
|= 0x00200000;
11396 inst
.instruction
|= 0x00000c00;
11397 if (inst
.operands
[i
].writeback
)
11398 inst
.instruction
|= 0x00000100;
11400 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11402 else if (inst
.operands
[i
].postind
)
11404 gas_assert (inst
.operands
[i
].writeback
);
11405 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11406 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11409 inst
.instruction
|= 0x00200000;
11411 inst
.instruction
|= 0x00000900;
11412 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11414 else /* unindexed - only for coprocessor */
11415 inst
.error
= _("instruction does not accept unindexed addressing");
11418 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11419 encodings (the latter only in post-V6T2 cores). The index is the
11420 value used in the insns table below. When there is more than one
11421 possible 16-bit encoding for the instruction, this table always
11423 Also contains several pseudo-instructions used during relaxation. */
11424 #define T16_32_TAB \
11425 X(_adc, 4140, eb400000), \
11426 X(_adcs, 4140, eb500000), \
11427 X(_add, 1c00, eb000000), \
11428 X(_adds, 1c00, eb100000), \
11429 X(_addi, 0000, f1000000), \
11430 X(_addis, 0000, f1100000), \
11431 X(_add_pc,000f, f20f0000), \
11432 X(_add_sp,000d, f10d0000), \
11433 X(_adr, 000f, f20f0000), \
11434 X(_and, 4000, ea000000), \
11435 X(_ands, 4000, ea100000), \
11436 X(_asr, 1000, fa40f000), \
11437 X(_asrs, 1000, fa50f000), \
11438 X(_b, e000, f000b000), \
11439 X(_bcond, d000, f0008000), \
11440 X(_bf, 0000, f040e001), \
11441 X(_bfcsel,0000, f000e001), \
11442 X(_bfx, 0000, f060e001), \
11443 X(_bfl, 0000, f000c001), \
11444 X(_bflx, 0000, f070e001), \
11445 X(_bic, 4380, ea200000), \
11446 X(_bics, 4380, ea300000), \
11447 X(_cinc, 0000, ea509000), \
11448 X(_cinv, 0000, ea50a000), \
11449 X(_cmn, 42c0, eb100f00), \
11450 X(_cmp, 2800, ebb00f00), \
11451 X(_cneg, 0000, ea50b000), \
11452 X(_cpsie, b660, f3af8400), \
11453 X(_cpsid, b670, f3af8600), \
11454 X(_cpy, 4600, ea4f0000), \
11455 X(_csel, 0000, ea508000), \
11456 X(_cset, 0000, ea5f900f), \
11457 X(_csetm, 0000, ea5fa00f), \
11458 X(_csinc, 0000, ea509000), \
11459 X(_csinv, 0000, ea50a000), \
11460 X(_csneg, 0000, ea50b000), \
11461 X(_dec_sp,80dd, f1ad0d00), \
11462 X(_dls, 0000, f040e001), \
11463 X(_dlstp, 0000, f000e001), \
11464 X(_eor, 4040, ea800000), \
11465 X(_eors, 4040, ea900000), \
11466 X(_inc_sp,00dd, f10d0d00), \
11467 X(_lctp, 0000, f00fe001), \
11468 X(_ldmia, c800, e8900000), \
11469 X(_ldr, 6800, f8500000), \
11470 X(_ldrb, 7800, f8100000), \
11471 X(_ldrh, 8800, f8300000), \
11472 X(_ldrsb, 5600, f9100000), \
11473 X(_ldrsh, 5e00, f9300000), \
11474 X(_ldr_pc,4800, f85f0000), \
11475 X(_ldr_pc2,4800, f85f0000), \
11476 X(_ldr_sp,9800, f85d0000), \
11477 X(_le, 0000, f00fc001), \
11478 X(_letp, 0000, f01fc001), \
11479 X(_lsl, 0000, fa00f000), \
11480 X(_lsls, 0000, fa10f000), \
11481 X(_lsr, 0800, fa20f000), \
11482 X(_lsrs, 0800, fa30f000), \
11483 X(_mov, 2000, ea4f0000), \
11484 X(_movs, 2000, ea5f0000), \
11485 X(_mul, 4340, fb00f000), \
11486 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11487 X(_mvn, 43c0, ea6f0000), \
11488 X(_mvns, 43c0, ea7f0000), \
11489 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11490 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11491 X(_orr, 4300, ea400000), \
11492 X(_orrs, 4300, ea500000), \
11493 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11494 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11495 X(_rev, ba00, fa90f080), \
11496 X(_rev16, ba40, fa90f090), \
11497 X(_revsh, bac0, fa90f0b0), \
11498 X(_ror, 41c0, fa60f000), \
11499 X(_rors, 41c0, fa70f000), \
11500 X(_sbc, 4180, eb600000), \
11501 X(_sbcs, 4180, eb700000), \
11502 X(_stmia, c000, e8800000), \
11503 X(_str, 6000, f8400000), \
11504 X(_strb, 7000, f8000000), \
11505 X(_strh, 8000, f8200000), \
11506 X(_str_sp,9000, f84d0000), \
11507 X(_sub, 1e00, eba00000), \
11508 X(_subs, 1e00, ebb00000), \
11509 X(_subi, 8000, f1a00000), \
11510 X(_subis, 8000, f1b00000), \
11511 X(_sxtb, b240, fa4ff080), \
11512 X(_sxth, b200, fa0ff080), \
11513 X(_tst, 4200, ea100f00), \
11514 X(_uxtb, b2c0, fa5ff080), \
11515 X(_uxth, b280, fa1ff080), \
11516 X(_nop, bf00, f3af8000), \
11517 X(_yield, bf10, f3af8001), \
11518 X(_wfe, bf20, f3af8002), \
11519 X(_wfi, bf30, f3af8003), \
11520 X(_wls, 0000, f040c001), \
11521 X(_wlstp, 0000, f000c001), \
11522 X(_sev, bf40, f3af8004), \
11523 X(_sevl, bf50, f3af8005), \
11524 X(_udf, de00, f7f0a000)
11526 /* To catch errors in encoding functions, the codes are all offset by
11527 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11528 as 16-bit instructions. */
11529 #define X(a,b,c) T_MNEM##a
11530 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11533 #define X(a,b,c) 0x##b
11534 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11535 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11538 #define X(a,b,c) 0x##c
11539 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11540 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11541 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11545 /* Thumb instruction encoders, in alphabetical order. */
11547 /* ADDW or SUBW. */
11550 do_t_add_sub_w (void)
11554 Rd
= inst
.operands
[0].reg
;
11555 Rn
= inst
.operands
[1].reg
;
11557 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11558 is the SP-{plus,minus}-immediate form of the instruction. */
11560 constraint (Rd
== REG_PC
, BAD_PC
);
11562 reject_bad_reg (Rd
);
11564 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11565 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11568 /* Parse an add or subtract instruction. We get here with inst.instruction
11569 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11572 do_t_add_sub (void)
11576 Rd
= inst
.operands
[0].reg
;
11577 Rs
= (inst
.operands
[1].present
11578 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11579 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11582 set_pred_insn_type_last ();
11584 if (unified_syntax
)
11587 bfd_boolean narrow
;
11590 flags
= (inst
.instruction
== T_MNEM_adds
11591 || inst
.instruction
== T_MNEM_subs
);
11593 narrow
= !in_pred_block ();
11595 narrow
= in_pred_block ();
11596 if (!inst
.operands
[2].isreg
)
11600 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11601 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11603 add
= (inst
.instruction
== T_MNEM_add
11604 || inst
.instruction
== T_MNEM_adds
);
11606 if (inst
.size_req
!= 4)
11608 /* Attempt to use a narrow opcode, with relaxation if
11610 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11611 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11612 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11613 opcode
= T_MNEM_add_sp
;
11614 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11615 opcode
= T_MNEM_add_pc
;
11616 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11619 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11621 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11625 inst
.instruction
= THUMB_OP16(opcode
);
11626 inst
.instruction
|= (Rd
<< 4) | Rs
;
11627 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11628 || (inst
.relocs
[0].type
11629 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11631 if (inst
.size_req
== 2)
11632 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11634 inst
.relax
= opcode
;
11638 constraint (inst
.size_req
== 2, _("cannot honor width suffix"));
11640 if (inst
.size_req
== 4
11641 || (inst
.size_req
!= 2 && !opcode
))
11643 constraint ((inst
.relocs
[0].type
11644 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11645 && (inst
.relocs
[0].type
11646 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11647 THUMB1_RELOC_ONLY
);
11650 constraint (add
, BAD_PC
);
11651 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11652 _("only SUBS PC, LR, #const allowed"));
11653 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11654 _("expression too complex"));
11655 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11656 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11657 _("immediate value out of range"));
11658 inst
.instruction
= T2_SUBS_PC_LR
11659 | inst
.relocs
[0].exp
.X_add_number
;
11660 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11663 else if (Rs
== REG_PC
)
11665 /* Always use addw/subw. */
11666 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11667 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11671 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11672 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11675 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11677 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11679 inst
.instruction
|= Rd
<< 8;
11680 inst
.instruction
|= Rs
<< 16;
11685 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11686 unsigned int shift
= inst
.operands
[2].shift_kind
;
11688 Rn
= inst
.operands
[2].reg
;
11689 /* See if we can do this with a 16-bit instruction. */
11690 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11692 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11697 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11698 || inst
.instruction
== T_MNEM_add
)
11700 : T_OPCODE_SUB_R3
);
11701 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11705 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11707 /* Thumb-1 cores (except v6-M) require at least one high
11708 register in a narrow non flag setting add. */
11709 if (Rd
> 7 || Rn
> 7
11710 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11711 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11718 inst
.instruction
= T_OPCODE_ADD_HI
;
11719 inst
.instruction
|= (Rd
& 8) << 4;
11720 inst
.instruction
|= (Rd
& 7);
11721 inst
.instruction
|= Rn
<< 3;
11727 constraint (Rd
== REG_PC
, BAD_PC
);
11728 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11729 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11730 constraint (Rs
== REG_PC
, BAD_PC
);
11731 reject_bad_reg (Rn
);
11733 /* If we get here, it can't be done in 16 bits. */
11734 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11735 _("shift must be constant"));
11736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11737 inst
.instruction
|= Rd
<< 8;
11738 inst
.instruction
|= Rs
<< 16;
11739 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11740 _("shift value over 3 not allowed in thumb mode"));
11741 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11742 _("only LSL shift allowed in thumb mode"));
11743 encode_thumb32_shifted_operand (2);
11748 constraint (inst
.instruction
== T_MNEM_adds
11749 || inst
.instruction
== T_MNEM_subs
,
11752 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11754 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11755 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11758 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11759 ? 0x0000 : 0x8000);
11760 inst
.instruction
|= (Rd
<< 4) | Rs
;
11761 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11765 Rn
= inst
.operands
[2].reg
;
11766 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11768 /* We now have Rd, Rs, and Rn set to registers. */
11769 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11771 /* Can't do this for SUB. */
11772 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11773 inst
.instruction
= T_OPCODE_ADD_HI
;
11774 inst
.instruction
|= (Rd
& 8) << 4;
11775 inst
.instruction
|= (Rd
& 7);
11777 inst
.instruction
|= Rn
<< 3;
11779 inst
.instruction
|= Rs
<< 3;
11781 constraint (1, _("dest must overlap one source register"));
11785 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11786 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11787 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11797 Rd
= inst
.operands
[0].reg
;
11798 reject_bad_reg (Rd
);
11800 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11802 /* Defer to section relaxation. */
11803 inst
.relax
= inst
.instruction
;
11804 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11805 inst
.instruction
|= Rd
<< 4;
11807 else if (unified_syntax
&& inst
.size_req
!= 2)
11809 /* Generate a 32-bit opcode. */
11810 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11811 inst
.instruction
|= Rd
<< 8;
11812 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11813 inst
.relocs
[0].pc_rel
= 1;
11817 /* Generate a 16-bit opcode. */
11818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11819 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11820 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11821 inst
.relocs
[0].pc_rel
= 1;
11822 inst
.instruction
|= Rd
<< 4;
11825 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11826 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11827 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11828 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11829 inst
.relocs
[0].exp
.X_add_number
+= 1;
11832 /* Arithmetic instructions for which there is just one 16-bit
11833 instruction encoding, and it allows only two low registers.
11834 For maximal compatibility with ARM syntax, we allow three register
11835 operands even when Thumb-32 instructions are not available, as long
11836 as the first two are identical. For instance, both "sbc r0,r1" and
11837 "sbc r0,r0,r1" are allowed. */
11843 Rd
= inst
.operands
[0].reg
;
11844 Rs
= (inst
.operands
[1].present
11845 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11846 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11847 Rn
= inst
.operands
[2].reg
;
11849 reject_bad_reg (Rd
);
11850 reject_bad_reg (Rs
);
11851 if (inst
.operands
[2].isreg
)
11852 reject_bad_reg (Rn
);
11854 if (unified_syntax
)
11856 if (!inst
.operands
[2].isreg
)
11858 /* For an immediate, we always generate a 32-bit opcode;
11859 section relaxation will shrink it later if possible. */
11860 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11861 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11862 inst
.instruction
|= Rd
<< 8;
11863 inst
.instruction
|= Rs
<< 16;
11864 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11868 bfd_boolean narrow
;
11870 /* See if we can do this with a 16-bit instruction. */
11871 if (THUMB_SETS_FLAGS (inst
.instruction
))
11872 narrow
= !in_pred_block ();
11874 narrow
= in_pred_block ();
11876 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11878 if (inst
.operands
[2].shifted
)
11880 if (inst
.size_req
== 4)
11886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11887 inst
.instruction
|= Rd
;
11888 inst
.instruction
|= Rn
<< 3;
11892 /* If we get here, it can't be done in 16 bits. */
11893 constraint (inst
.operands
[2].shifted
11894 && inst
.operands
[2].immisreg
,
11895 _("shift must be constant"));
11896 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11897 inst
.instruction
|= Rd
<< 8;
11898 inst
.instruction
|= Rs
<< 16;
11899 encode_thumb32_shifted_operand (2);
11904 /* On its face this is a lie - the instruction does set the
11905 flags. However, the only supported mnemonic in this mode
11906 says it doesn't. */
11907 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11909 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11910 _("unshifted register required"));
11911 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11912 constraint (Rd
!= Rs
,
11913 _("dest and source1 must be the same register"));
11915 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11916 inst
.instruction
|= Rd
;
11917 inst
.instruction
|= Rn
<< 3;
11921 /* Similarly, but for instructions where the arithmetic operation is
11922 commutative, so we can allow either of them to be different from
11923 the destination operand in a 16-bit instruction. For instance, all
11924 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11931 Rd
= inst
.operands
[0].reg
;
11932 Rs
= (inst
.operands
[1].present
11933 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11934 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11935 Rn
= inst
.operands
[2].reg
;
11937 reject_bad_reg (Rd
);
11938 reject_bad_reg (Rs
);
11939 if (inst
.operands
[2].isreg
)
11940 reject_bad_reg (Rn
);
11942 if (unified_syntax
)
11944 if (!inst
.operands
[2].isreg
)
11946 /* For an immediate, we always generate a 32-bit opcode;
11947 section relaxation will shrink it later if possible. */
11948 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11949 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11950 inst
.instruction
|= Rd
<< 8;
11951 inst
.instruction
|= Rs
<< 16;
11952 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11956 bfd_boolean narrow
;
11958 /* See if we can do this with a 16-bit instruction. */
11959 if (THUMB_SETS_FLAGS (inst
.instruction
))
11960 narrow
= !in_pred_block ();
11962 narrow
= in_pred_block ();
11964 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11966 if (inst
.operands
[2].shifted
)
11968 if (inst
.size_req
== 4)
11975 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11976 inst
.instruction
|= Rd
;
11977 inst
.instruction
|= Rn
<< 3;
11982 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11983 inst
.instruction
|= Rd
;
11984 inst
.instruction
|= Rs
<< 3;
11989 /* If we get here, it can't be done in 16 bits. */
11990 constraint (inst
.operands
[2].shifted
11991 && inst
.operands
[2].immisreg
,
11992 _("shift must be constant"));
11993 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11994 inst
.instruction
|= Rd
<< 8;
11995 inst
.instruction
|= Rs
<< 16;
11996 encode_thumb32_shifted_operand (2);
12001 /* On its face this is a lie - the instruction does set the
12002 flags. However, the only supported mnemonic in this mode
12003 says it doesn't. */
12004 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12006 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
12007 _("unshifted register required"));
12008 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12010 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12011 inst
.instruction
|= Rd
;
12014 inst
.instruction
|= Rn
<< 3;
12016 inst
.instruction
|= Rs
<< 3;
12018 constraint (1, _("dest must overlap one source register"));
12026 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12027 constraint (msb
> 32, _("bit-field extends past end of register"));
12028 /* The instruction encoding stores the LSB and MSB,
12029 not the LSB and width. */
12030 Rd
= inst
.operands
[0].reg
;
12031 reject_bad_reg (Rd
);
12032 inst
.instruction
|= Rd
<< 8;
12033 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12034 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12035 inst
.instruction
|= msb
- 1;
12044 Rd
= inst
.operands
[0].reg
;
12045 reject_bad_reg (Rd
);
12047 /* #0 in second position is alternative syntax for bfc, which is
12048 the same instruction but with REG_PC in the Rm field. */
12049 if (!inst
.operands
[1].isreg
)
12053 Rn
= inst
.operands
[1].reg
;
12054 reject_bad_reg (Rn
);
12057 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12058 constraint (msb
> 32, _("bit-field extends past end of register"));
12059 /* The instruction encoding stores the LSB and MSB,
12060 not the LSB and width. */
12061 inst
.instruction
|= Rd
<< 8;
12062 inst
.instruction
|= Rn
<< 16;
12063 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12064 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12065 inst
.instruction
|= msb
- 1;
12073 Rd
= inst
.operands
[0].reg
;
12074 Rn
= inst
.operands
[1].reg
;
12076 reject_bad_reg (Rd
);
12077 reject_bad_reg (Rn
);
12079 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12080 _("bit-field extends past end of register"));
12081 inst
.instruction
|= Rd
<< 8;
12082 inst
.instruction
|= Rn
<< 16;
12083 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12084 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12085 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12088 /* ARM V5 Thumb BLX (argument parse)
12089 BLX <target_addr> which is BLX(1)
12090 BLX <Rm> which is BLX(2)
12091 Unfortunately, there are two different opcodes for this mnemonic.
12092 So, the insns[].value is not used, and the code here zaps values
12093 into inst.instruction.
12095 ??? How to take advantage of the additional two bits of displacement
12096 available in Thumb32 mode? Need new relocation? */
12101 set_pred_insn_type_last ();
12103 if (inst
.operands
[0].isreg
)
12105 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12106 /* We have a register, so this is BLX(2). */
12107 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12111 /* No register. This must be BLX(1). */
12112 inst
.instruction
= 0xf000e800;
12113 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12122 bfd_reloc_code_real_type reloc
;
12125 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12127 if (in_pred_block ())
12129 /* Conditional branches inside IT blocks are encoded as unconditional
12131 cond
= COND_ALWAYS
;
12136 if (cond
!= COND_ALWAYS
)
12137 opcode
= T_MNEM_bcond
;
12139 opcode
= inst
.instruction
;
12142 && (inst
.size_req
== 4
12143 || (inst
.size_req
!= 2
12144 && (inst
.operands
[0].hasreloc
12145 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12147 inst
.instruction
= THUMB_OP32(opcode
);
12148 if (cond
== COND_ALWAYS
)
12149 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12152 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12153 _("selected architecture does not support "
12154 "wide conditional branch instruction"));
12156 gas_assert (cond
!= 0xF);
12157 inst
.instruction
|= cond
<< 22;
12158 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12163 inst
.instruction
= THUMB_OP16(opcode
);
12164 if (cond
== COND_ALWAYS
)
12165 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12168 inst
.instruction
|= cond
<< 8;
12169 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12171 /* Allow section relaxation. */
12172 if (unified_syntax
&& inst
.size_req
!= 2)
12173 inst
.relax
= opcode
;
12175 inst
.relocs
[0].type
= reloc
;
12176 inst
.relocs
[0].pc_rel
= 1;
12179 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12180 between the two is the maximum immediate allowed - which is passed in
12183 do_t_bkpt_hlt1 (int range
)
12185 constraint (inst
.cond
!= COND_ALWAYS
,
12186 _("instruction is always unconditional"));
12187 if (inst
.operands
[0].present
)
12189 constraint (inst
.operands
[0].imm
> range
,
12190 _("immediate value out of range"));
12191 inst
.instruction
|= inst
.operands
[0].imm
;
12194 set_pred_insn_type (NEUTRAL_IT_INSN
);
12200 do_t_bkpt_hlt1 (63);
12206 do_t_bkpt_hlt1 (255);
12210 do_t_branch23 (void)
12212 set_pred_insn_type_last ();
12213 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12215 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12216 this file. We used to simply ignore the PLT reloc type here --
12217 the branch encoding is now needed to deal with TLSCALL relocs.
12218 So if we see a PLT reloc now, put it back to how it used to be to
12219 keep the preexisting behaviour. */
12220 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12221 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12223 #if defined(OBJ_COFF)
12224 /* If the destination of the branch is a defined symbol which does not have
12225 the THUMB_FUNC attribute, then we must be calling a function which has
12226 the (interfacearm) attribute. We look for the Thumb entry point to that
12227 function and change the branch to refer to that function instead. */
12228 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12229 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12230 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12231 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12232 inst
.relocs
[0].exp
.X_add_symbol
12233 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12240 set_pred_insn_type_last ();
12241 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12242 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12243 should cause the alignment to be checked once it is known. This is
12244 because BX PC only works if the instruction is word aligned. */
12252 set_pred_insn_type_last ();
12253 Rm
= inst
.operands
[0].reg
;
12254 reject_bad_reg (Rm
);
12255 inst
.instruction
|= Rm
<< 16;
12264 Rd
= inst
.operands
[0].reg
;
12265 Rm
= inst
.operands
[1].reg
;
12267 reject_bad_reg (Rd
);
12268 reject_bad_reg (Rm
);
12270 inst
.instruction
|= Rd
<< 8;
12271 inst
.instruction
|= Rm
<< 16;
12272 inst
.instruction
|= Rm
;
12275 /* For the Armv8.1-M conditional instructions. */
12279 unsigned Rd
, Rn
, Rm
;
12282 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12284 Rd
= inst
.operands
[0].reg
;
12285 switch (inst
.instruction
)
12291 Rn
= inst
.operands
[1].reg
;
12292 Rm
= inst
.operands
[2].reg
;
12293 cond
= inst
.operands
[3].imm
;
12294 constraint (Rn
== REG_SP
, BAD_SP
);
12295 constraint (Rm
== REG_SP
, BAD_SP
);
12301 Rn
= inst
.operands
[1].reg
;
12302 cond
= inst
.operands
[2].imm
;
12303 /* Invert the last bit to invert the cond. */
12304 cond
= TOGGLE_BIT (cond
, 0);
12305 constraint (Rn
== REG_SP
, BAD_SP
);
12311 cond
= inst
.operands
[1].imm
;
12312 /* Invert the last bit to invert the cond. */
12313 cond
= TOGGLE_BIT (cond
, 0);
12321 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12322 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12323 inst
.instruction
|= Rd
<< 8;
12324 inst
.instruction
|= Rn
<< 16;
12325 inst
.instruction
|= Rm
;
12326 inst
.instruction
|= cond
<< 4;
12332 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12338 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12339 inst
.instruction
|= inst
.operands
[0].imm
;
12345 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12347 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12348 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12350 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12351 inst
.instruction
= 0xf3af8000;
12352 inst
.instruction
|= imod
<< 9;
12353 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12354 if (inst
.operands
[1].present
)
12355 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12360 && (inst
.operands
[0].imm
& 4),
12361 _("selected processor does not support 'A' form "
12362 "of this instruction"));
12363 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12364 _("Thumb does not support the 2-argument "
12365 "form of this instruction"));
12366 inst
.instruction
|= inst
.operands
[0].imm
;
12370 /* THUMB CPY instruction (argument parse). */
12375 if (inst
.size_req
== 4)
12377 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12379 inst
.instruction
|= inst
.operands
[1].reg
;
12383 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12384 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12385 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12392 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12393 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12394 inst
.instruction
|= inst
.operands
[0].reg
;
12395 inst
.relocs
[0].pc_rel
= 1;
12396 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12402 inst
.instruction
|= inst
.operands
[0].imm
;
12408 unsigned Rd
, Rn
, Rm
;
12410 Rd
= inst
.operands
[0].reg
;
12411 Rn
= (inst
.operands
[1].present
12412 ? inst
.operands
[1].reg
: Rd
);
12413 Rm
= inst
.operands
[2].reg
;
12415 reject_bad_reg (Rd
);
12416 reject_bad_reg (Rn
);
12417 reject_bad_reg (Rm
);
12419 inst
.instruction
|= Rd
<< 8;
12420 inst
.instruction
|= Rn
<< 16;
12421 inst
.instruction
|= Rm
;
12427 if (unified_syntax
&& inst
.size_req
== 4)
12428 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12430 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12436 unsigned int cond
= inst
.operands
[0].imm
;
12438 set_pred_insn_type (IT_INSN
);
12439 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12440 now_pred
.cc
= cond
;
12441 now_pred
.warn_deprecated
= FALSE
;
12442 now_pred
.type
= SCALAR_PRED
;
12444 /* If the condition is a negative condition, invert the mask. */
12445 if ((cond
& 0x1) == 0x0)
12447 unsigned int mask
= inst
.instruction
& 0x000f;
12449 if ((mask
& 0x7) == 0)
12451 /* No conversion needed. */
12452 now_pred
.block_length
= 1;
12454 else if ((mask
& 0x3) == 0)
12457 now_pred
.block_length
= 2;
12459 else if ((mask
& 0x1) == 0)
12462 now_pred
.block_length
= 3;
12467 now_pred
.block_length
= 4;
12470 inst
.instruction
&= 0xfff0;
12471 inst
.instruction
|= mask
;
12474 inst
.instruction
|= cond
<< 4;
12477 /* Helper function used for both push/pop and ldm/stm. */
12479 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12480 bfd_boolean writeback
)
12482 bfd_boolean load
, store
;
12484 gas_assert (base
!= -1 || !do_io
);
12485 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12486 store
= do_io
&& !load
;
12488 if (mask
& (1 << 13))
12489 inst
.error
= _("SP not allowed in register list");
12491 if (do_io
&& (mask
& (1 << base
)) != 0
12493 inst
.error
= _("having the base register in the register list when "
12494 "using write back is UNPREDICTABLE");
12498 if (mask
& (1 << 15))
12500 if (mask
& (1 << 14))
12501 inst
.error
= _("LR and PC should not both be in register list");
12503 set_pred_insn_type_last ();
12508 if (mask
& (1 << 15))
12509 inst
.error
= _("PC not allowed in register list");
12512 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12514 /* Single register transfers implemented as str/ldr. */
12517 if (inst
.instruction
& (1 << 23))
12518 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12520 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12524 if (inst
.instruction
& (1 << 23))
12525 inst
.instruction
= 0x00800000; /* ia -> [base] */
12527 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12530 inst
.instruction
|= 0xf8400000;
12532 inst
.instruction
|= 0x00100000;
12534 mask
= ffs (mask
) - 1;
12537 else if (writeback
)
12538 inst
.instruction
|= WRITE_BACK
;
12540 inst
.instruction
|= mask
;
12542 inst
.instruction
|= base
<< 16;
12548 /* This really doesn't seem worth it. */
12549 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12550 _("expression too complex"));
12551 constraint (inst
.operands
[1].writeback
,
12552 _("Thumb load/store multiple does not support {reglist}^"));
12554 if (unified_syntax
)
12556 bfd_boolean narrow
;
12560 /* See if we can use a 16-bit instruction. */
12561 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12562 && inst
.size_req
!= 4
12563 && !(inst
.operands
[1].imm
& ~0xff))
12565 mask
= 1 << inst
.operands
[0].reg
;
12567 if (inst
.operands
[0].reg
<= 7)
12569 if (inst
.instruction
== T_MNEM_stmia
12570 ? inst
.operands
[0].writeback
12571 : (inst
.operands
[0].writeback
12572 == !(inst
.operands
[1].imm
& mask
)))
12574 if (inst
.instruction
== T_MNEM_stmia
12575 && (inst
.operands
[1].imm
& mask
)
12576 && (inst
.operands
[1].imm
& (mask
- 1)))
12577 as_warn (_("value stored for r%d is UNKNOWN"),
12578 inst
.operands
[0].reg
);
12580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12581 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12582 inst
.instruction
|= inst
.operands
[1].imm
;
12585 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12587 /* This means 1 register in reg list one of 3 situations:
12588 1. Instruction is stmia, but without writeback.
12589 2. lmdia without writeback, but with Rn not in
12591 3. ldmia with writeback, but with Rn in reglist.
12592 Case 3 is UNPREDICTABLE behaviour, so we handle
12593 case 1 and 2 which can be converted into a 16-bit
12594 str or ldr. The SP cases are handled below. */
12595 unsigned long opcode
;
12596 /* First, record an error for Case 3. */
12597 if (inst
.operands
[1].imm
& mask
12598 && inst
.operands
[0].writeback
)
12600 _("having the base register in the register list when "
12601 "using write back is UNPREDICTABLE");
12603 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12605 inst
.instruction
= THUMB_OP16 (opcode
);
12606 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12607 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12611 else if (inst
.operands
[0] .reg
== REG_SP
)
12613 if (inst
.operands
[0].writeback
)
12616 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12617 ? T_MNEM_push
: T_MNEM_pop
);
12618 inst
.instruction
|= inst
.operands
[1].imm
;
12621 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12624 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12625 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12626 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12634 if (inst
.instruction
< 0xffff)
12635 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12637 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12638 inst
.operands
[1].imm
,
12639 inst
.operands
[0].writeback
);
12644 constraint (inst
.operands
[0].reg
> 7
12645 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12646 constraint (inst
.instruction
!= T_MNEM_ldmia
12647 && inst
.instruction
!= T_MNEM_stmia
,
12648 _("Thumb-2 instruction only valid in unified syntax"));
12649 if (inst
.instruction
== T_MNEM_stmia
)
12651 if (!inst
.operands
[0].writeback
)
12652 as_warn (_("this instruction will write back the base register"));
12653 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12654 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12655 as_warn (_("value stored for r%d is UNKNOWN"),
12656 inst
.operands
[0].reg
);
12660 if (!inst
.operands
[0].writeback
12661 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12662 as_warn (_("this instruction will write back the base register"));
12663 else if (inst
.operands
[0].writeback
12664 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12665 as_warn (_("this instruction will not write back the base register"));
12668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12669 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12670 inst
.instruction
|= inst
.operands
[1].imm
;
12677 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12678 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12679 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12680 || inst
.operands
[1].negative
,
12683 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12686 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12687 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12693 if (!inst
.operands
[1].present
)
12695 constraint (inst
.operands
[0].reg
== REG_LR
,
12696 _("r14 not allowed as first register "
12697 "when second register is omitted"));
12698 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12700 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12703 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12704 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12705 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12711 unsigned long opcode
;
12714 if (inst
.operands
[0].isreg
12715 && !inst
.operands
[0].preind
12716 && inst
.operands
[0].reg
== REG_PC
)
12717 set_pred_insn_type_last ();
12719 opcode
= inst
.instruction
;
12720 if (unified_syntax
)
12722 if (!inst
.operands
[1].isreg
)
12724 if (opcode
<= 0xffff)
12725 inst
.instruction
= THUMB_OP32 (opcode
);
12726 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12729 if (inst
.operands
[1].isreg
12730 && !inst
.operands
[1].writeback
12731 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12732 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12733 && opcode
<= 0xffff
12734 && inst
.size_req
!= 4)
12736 /* Insn may have a 16-bit form. */
12737 Rn
= inst
.operands
[1].reg
;
12738 if (inst
.operands
[1].immisreg
)
12740 inst
.instruction
= THUMB_OP16 (opcode
);
12742 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12744 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12745 reject_bad_reg (inst
.operands
[1].imm
);
12747 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12748 && opcode
!= T_MNEM_ldrsb
)
12749 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12750 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12757 if (inst
.relocs
[0].pc_rel
)
12758 opcode
= T_MNEM_ldr_pc2
;
12760 opcode
= T_MNEM_ldr_pc
;
12764 if (opcode
== T_MNEM_ldr
)
12765 opcode
= T_MNEM_ldr_sp
;
12767 opcode
= T_MNEM_str_sp
;
12769 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12773 inst
.instruction
= inst
.operands
[0].reg
;
12774 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12776 inst
.instruction
|= THUMB_OP16 (opcode
);
12777 if (inst
.size_req
== 2)
12778 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12780 inst
.relax
= opcode
;
12784 /* Definitely a 32-bit variant. */
12786 /* Warning for Erratum 752419. */
12787 if (opcode
== T_MNEM_ldr
12788 && inst
.operands
[0].reg
== REG_SP
12789 && inst
.operands
[1].writeback
== 1
12790 && !inst
.operands
[1].immisreg
)
12792 if (no_cpu_selected ()
12793 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12794 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12795 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12796 as_warn (_("This instruction may be unpredictable "
12797 "if executed on M-profile cores "
12798 "with interrupts enabled."));
12801 /* Do some validations regarding addressing modes. */
12802 if (inst
.operands
[1].immisreg
)
12803 reject_bad_reg (inst
.operands
[1].imm
);
12805 constraint (inst
.operands
[1].writeback
== 1
12806 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12809 inst
.instruction
= THUMB_OP32 (opcode
);
12810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12811 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12812 check_ldr_r15_aligned ();
12816 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12818 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12820 /* Only [Rn,Rm] is acceptable. */
12821 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12822 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12823 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12824 || inst
.operands
[1].negative
,
12825 _("Thumb does not support this addressing mode"));
12826 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12831 if (!inst
.operands
[1].isreg
)
12832 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12835 constraint (!inst
.operands
[1].preind
12836 || inst
.operands
[1].shifted
12837 || inst
.operands
[1].writeback
,
12838 _("Thumb does not support this addressing mode"));
12839 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12841 constraint (inst
.instruction
& 0x0600,
12842 _("byte or halfword not valid for base register"));
12843 constraint (inst
.operands
[1].reg
== REG_PC
12844 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12845 _("r15 based store not allowed"));
12846 constraint (inst
.operands
[1].immisreg
,
12847 _("invalid base register for register offset"));
12849 if (inst
.operands
[1].reg
== REG_PC
)
12850 inst
.instruction
= T_OPCODE_LDR_PC
;
12851 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12852 inst
.instruction
= T_OPCODE_LDR_SP
;
12854 inst
.instruction
= T_OPCODE_STR_SP
;
12856 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12857 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12861 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12862 if (!inst
.operands
[1].immisreg
)
12864 /* Immediate offset. */
12865 inst
.instruction
|= inst
.operands
[0].reg
;
12866 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12867 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12871 /* Register offset. */
12872 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12873 constraint (inst
.operands
[1].negative
,
12874 _("Thumb does not support this addressing mode"));
12877 switch (inst
.instruction
)
12879 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12880 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12881 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12882 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12883 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12884 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12885 case 0x5600 /* ldrsb */:
12886 case 0x5e00 /* ldrsh */: break;
12890 inst
.instruction
|= inst
.operands
[0].reg
;
12891 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12892 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12898 if (!inst
.operands
[1].present
)
12900 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12901 constraint (inst
.operands
[0].reg
== REG_LR
,
12902 _("r14 not allowed here"));
12903 constraint (inst
.operands
[0].reg
== REG_R12
,
12904 _("r12 not allowed here"));
12907 if (inst
.operands
[2].writeback
12908 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12909 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12910 as_warn (_("base register written back, and overlaps "
12911 "one of transfer registers"));
12913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12914 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12915 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12922 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12928 unsigned Rd
, Rn
, Rm
, Ra
;
12930 Rd
= inst
.operands
[0].reg
;
12931 Rn
= inst
.operands
[1].reg
;
12932 Rm
= inst
.operands
[2].reg
;
12933 Ra
= inst
.operands
[3].reg
;
12935 reject_bad_reg (Rd
);
12936 reject_bad_reg (Rn
);
12937 reject_bad_reg (Rm
);
12938 reject_bad_reg (Ra
);
12940 inst
.instruction
|= Rd
<< 8;
12941 inst
.instruction
|= Rn
<< 16;
12942 inst
.instruction
|= Rm
;
12943 inst
.instruction
|= Ra
<< 12;
12949 unsigned RdLo
, RdHi
, Rn
, Rm
;
12951 RdLo
= inst
.operands
[0].reg
;
12952 RdHi
= inst
.operands
[1].reg
;
12953 Rn
= inst
.operands
[2].reg
;
12954 Rm
= inst
.operands
[3].reg
;
12956 reject_bad_reg (RdLo
);
12957 reject_bad_reg (RdHi
);
12958 reject_bad_reg (Rn
);
12959 reject_bad_reg (Rm
);
12961 inst
.instruction
|= RdLo
<< 12;
12962 inst
.instruction
|= RdHi
<< 8;
12963 inst
.instruction
|= Rn
<< 16;
12964 inst
.instruction
|= Rm
;
12968 do_t_mov_cmp (void)
12972 Rn
= inst
.operands
[0].reg
;
12973 Rm
= inst
.operands
[1].reg
;
12976 set_pred_insn_type_last ();
12978 if (unified_syntax
)
12980 int r0off
= (inst
.instruction
== T_MNEM_mov
12981 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12982 unsigned long opcode
;
12983 bfd_boolean narrow
;
12984 bfd_boolean low_regs
;
12986 low_regs
= (Rn
<= 7 && Rm
<= 7);
12987 opcode
= inst
.instruction
;
12988 if (in_pred_block ())
12989 narrow
= opcode
!= T_MNEM_movs
;
12991 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12992 if (inst
.size_req
== 4
12993 || inst
.operands
[1].shifted
)
12996 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12997 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12998 && !inst
.operands
[1].shifted
13002 inst
.instruction
= T2_SUBS_PC_LR
;
13006 if (opcode
== T_MNEM_cmp
)
13008 constraint (Rn
== REG_PC
, BAD_PC
);
13011 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13013 warn_deprecated_sp (Rm
);
13014 /* R15 was documented as a valid choice for Rm in ARMv6,
13015 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13016 tools reject R15, so we do too. */
13017 constraint (Rm
== REG_PC
, BAD_PC
);
13020 reject_bad_reg (Rm
);
13022 else if (opcode
== T_MNEM_mov
13023 || opcode
== T_MNEM_movs
)
13025 if (inst
.operands
[1].isreg
)
13027 if (opcode
== T_MNEM_movs
)
13029 reject_bad_reg (Rn
);
13030 reject_bad_reg (Rm
);
13034 /* This is mov.n. */
13035 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13036 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13038 as_tsktsk (_("Use of r%u as a source register is "
13039 "deprecated when r%u is the destination "
13040 "register."), Rm
, Rn
);
13045 /* This is mov.w. */
13046 constraint (Rn
== REG_PC
, BAD_PC
);
13047 constraint (Rm
== REG_PC
, BAD_PC
);
13048 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13049 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13053 reject_bad_reg (Rn
);
13056 if (!inst
.operands
[1].isreg
)
13058 /* Immediate operand. */
13059 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13061 if (low_regs
&& narrow
)
13063 inst
.instruction
= THUMB_OP16 (opcode
);
13064 inst
.instruction
|= Rn
<< 8;
13065 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13066 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13068 if (inst
.size_req
== 2)
13069 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13071 inst
.relax
= opcode
;
13076 constraint ((inst
.relocs
[0].type
13077 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13078 && (inst
.relocs
[0].type
13079 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13080 THUMB1_RELOC_ONLY
);
13082 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13083 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13084 inst
.instruction
|= Rn
<< r0off
;
13085 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13088 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13089 && (inst
.instruction
== T_MNEM_mov
13090 || inst
.instruction
== T_MNEM_movs
))
13092 /* Register shifts are encoded as separate shift instructions. */
13093 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13095 if (in_pred_block ())
13100 if (inst
.size_req
== 4)
13103 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13109 switch (inst
.operands
[1].shift_kind
)
13112 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13115 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13118 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13121 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13127 inst
.instruction
= opcode
;
13130 inst
.instruction
|= Rn
;
13131 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13136 inst
.instruction
|= CONDS_BIT
;
13138 inst
.instruction
|= Rn
<< 8;
13139 inst
.instruction
|= Rm
<< 16;
13140 inst
.instruction
|= inst
.operands
[1].imm
;
13145 /* Some mov with immediate shift have narrow variants.
13146 Register shifts are handled above. */
13147 if (low_regs
&& inst
.operands
[1].shifted
13148 && (inst
.instruction
== T_MNEM_mov
13149 || inst
.instruction
== T_MNEM_movs
))
13151 if (in_pred_block ())
13152 narrow
= (inst
.instruction
== T_MNEM_mov
);
13154 narrow
= (inst
.instruction
== T_MNEM_movs
);
13159 switch (inst
.operands
[1].shift_kind
)
13161 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13162 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13163 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13164 default: narrow
= FALSE
; break;
13170 inst
.instruction
|= Rn
;
13171 inst
.instruction
|= Rm
<< 3;
13172 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13176 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13177 inst
.instruction
|= Rn
<< r0off
;
13178 encode_thumb32_shifted_operand (1);
13182 switch (inst
.instruction
)
13185 /* In v4t or v5t a move of two lowregs produces unpredictable
13186 results. Don't allow this. */
13189 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13190 "MOV Rd, Rs with two low registers is not "
13191 "permitted on this architecture");
13192 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13196 inst
.instruction
= T_OPCODE_MOV_HR
;
13197 inst
.instruction
|= (Rn
& 0x8) << 4;
13198 inst
.instruction
|= (Rn
& 0x7);
13199 inst
.instruction
|= Rm
<< 3;
13203 /* We know we have low registers at this point.
13204 Generate LSLS Rd, Rs, #0. */
13205 inst
.instruction
= T_OPCODE_LSL_I
;
13206 inst
.instruction
|= Rn
;
13207 inst
.instruction
|= Rm
<< 3;
13213 inst
.instruction
= T_OPCODE_CMP_LR
;
13214 inst
.instruction
|= Rn
;
13215 inst
.instruction
|= Rm
<< 3;
13219 inst
.instruction
= T_OPCODE_CMP_HR
;
13220 inst
.instruction
|= (Rn
& 0x8) << 4;
13221 inst
.instruction
|= (Rn
& 0x7);
13222 inst
.instruction
|= Rm
<< 3;
13229 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13231 /* PR 10443: Do not silently ignore shifted operands. */
13232 constraint (inst
.operands
[1].shifted
,
13233 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13235 if (inst
.operands
[1].isreg
)
13237 if (Rn
< 8 && Rm
< 8)
13239 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13240 since a MOV instruction produces unpredictable results. */
13241 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13242 inst
.instruction
= T_OPCODE_ADD_I3
;
13244 inst
.instruction
= T_OPCODE_CMP_LR
;
13246 inst
.instruction
|= Rn
;
13247 inst
.instruction
|= Rm
<< 3;
13251 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13252 inst
.instruction
= T_OPCODE_MOV_HR
;
13254 inst
.instruction
= T_OPCODE_CMP_HR
;
13260 constraint (Rn
> 7,
13261 _("only lo regs allowed with immediate"));
13262 inst
.instruction
|= Rn
<< 8;
13263 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13274 top
= (inst
.instruction
& 0x00800000) != 0;
13275 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13277 constraint (top
, _(":lower16: not allowed in this instruction"));
13278 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13280 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13282 constraint (!top
, _(":upper16: not allowed in this instruction"));
13283 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13286 Rd
= inst
.operands
[0].reg
;
13287 reject_bad_reg (Rd
);
13289 inst
.instruction
|= Rd
<< 8;
13290 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13292 imm
= inst
.relocs
[0].exp
.X_add_number
;
13293 inst
.instruction
|= (imm
& 0xf000) << 4;
13294 inst
.instruction
|= (imm
& 0x0800) << 15;
13295 inst
.instruction
|= (imm
& 0x0700) << 4;
13296 inst
.instruction
|= (imm
& 0x00ff);
13301 do_t_mvn_tst (void)
13305 Rn
= inst
.operands
[0].reg
;
13306 Rm
= inst
.operands
[1].reg
;
13308 if (inst
.instruction
== T_MNEM_cmp
13309 || inst
.instruction
== T_MNEM_cmn
)
13310 constraint (Rn
== REG_PC
, BAD_PC
);
13312 reject_bad_reg (Rn
);
13313 reject_bad_reg (Rm
);
13315 if (unified_syntax
)
13317 int r0off
= (inst
.instruction
== T_MNEM_mvn
13318 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13319 bfd_boolean narrow
;
13321 if (inst
.size_req
== 4
13322 || inst
.instruction
> 0xffff
13323 || inst
.operands
[1].shifted
13324 || Rn
> 7 || Rm
> 7)
13326 else if (inst
.instruction
== T_MNEM_cmn
13327 || inst
.instruction
== T_MNEM_tst
)
13329 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13330 narrow
= !in_pred_block ();
13332 narrow
= in_pred_block ();
13334 if (!inst
.operands
[1].isreg
)
13336 /* For an immediate, we always generate a 32-bit opcode;
13337 section relaxation will shrink it later if possible. */
13338 if (inst
.instruction
< 0xffff)
13339 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13340 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13341 inst
.instruction
|= Rn
<< r0off
;
13342 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13346 /* See if we can do this with a 16-bit instruction. */
13349 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13350 inst
.instruction
|= Rn
;
13351 inst
.instruction
|= Rm
<< 3;
13355 constraint (inst
.operands
[1].shifted
13356 && inst
.operands
[1].immisreg
,
13357 _("shift must be constant"));
13358 if (inst
.instruction
< 0xffff)
13359 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13360 inst
.instruction
|= Rn
<< r0off
;
13361 encode_thumb32_shifted_operand (1);
13367 constraint (inst
.instruction
> 0xffff
13368 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13369 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13370 _("unshifted register required"));
13371 constraint (Rn
> 7 || Rm
> 7,
13374 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13375 inst
.instruction
|= Rn
;
13376 inst
.instruction
|= Rm
<< 3;
13385 if (do_vfp_nsyn_mrs () == SUCCESS
)
13388 Rd
= inst
.operands
[0].reg
;
13389 reject_bad_reg (Rd
);
13390 inst
.instruction
|= Rd
<< 8;
13392 if (inst
.operands
[1].isreg
)
13394 unsigned br
= inst
.operands
[1].reg
;
13395 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13396 as_bad (_("bad register for mrs"));
13398 inst
.instruction
|= br
& (0xf << 16);
13399 inst
.instruction
|= (br
& 0x300) >> 4;
13400 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13404 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13406 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13408 /* PR gas/12698: The constraint is only applied for m_profile.
13409 If the user has specified -march=all, we want to ignore it as
13410 we are building for any CPU type, including non-m variants. */
13411 bfd_boolean m_profile
=
13412 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13413 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13414 "not support requested special purpose register"));
13417 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13419 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13420 _("'APSR', 'CPSR' or 'SPSR' expected"));
13422 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13423 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13424 inst
.instruction
|= 0xf0000;
13434 if (do_vfp_nsyn_msr () == SUCCESS
)
13437 constraint (!inst
.operands
[1].isreg
,
13438 _("Thumb encoding does not support an immediate here"));
13440 if (inst
.operands
[0].isreg
)
13441 flags
= (int)(inst
.operands
[0].reg
);
13443 flags
= inst
.operands
[0].imm
;
13445 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13447 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13449 /* PR gas/12698: The constraint is only applied for m_profile.
13450 If the user has specified -march=all, we want to ignore it as
13451 we are building for any CPU type, including non-m variants. */
13452 bfd_boolean m_profile
=
13453 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13454 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13455 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13456 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13457 && bits
!= PSR_f
)) && m_profile
,
13458 _("selected processor does not support requested special "
13459 "purpose register"));
13462 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13463 "requested special purpose register"));
13465 Rn
= inst
.operands
[1].reg
;
13466 reject_bad_reg (Rn
);
13468 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13469 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13470 inst
.instruction
|= (flags
& 0x300) >> 4;
13471 inst
.instruction
|= (flags
& 0xff);
13472 inst
.instruction
|= Rn
<< 16;
13478 bfd_boolean narrow
;
13479 unsigned Rd
, Rn
, Rm
;
13481 if (!inst
.operands
[2].present
)
13482 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13484 Rd
= inst
.operands
[0].reg
;
13485 Rn
= inst
.operands
[1].reg
;
13486 Rm
= inst
.operands
[2].reg
;
13488 if (unified_syntax
)
13490 if (inst
.size_req
== 4
13496 else if (inst
.instruction
== T_MNEM_muls
)
13497 narrow
= !in_pred_block ();
13499 narrow
= in_pred_block ();
13503 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13504 constraint (Rn
> 7 || Rm
> 7,
13511 /* 16-bit MULS/Conditional MUL. */
13512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13513 inst
.instruction
|= Rd
;
13516 inst
.instruction
|= Rm
<< 3;
13518 inst
.instruction
|= Rn
<< 3;
13520 constraint (1, _("dest must overlap one source register"));
13524 constraint (inst
.instruction
!= T_MNEM_mul
,
13525 _("Thumb-2 MUL must not set flags"));
13527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13528 inst
.instruction
|= Rd
<< 8;
13529 inst
.instruction
|= Rn
<< 16;
13530 inst
.instruction
|= Rm
<< 0;
13532 reject_bad_reg (Rd
);
13533 reject_bad_reg (Rn
);
13534 reject_bad_reg (Rm
);
13541 unsigned RdLo
, RdHi
, Rn
, Rm
;
13543 RdLo
= inst
.operands
[0].reg
;
13544 RdHi
= inst
.operands
[1].reg
;
13545 Rn
= inst
.operands
[2].reg
;
13546 Rm
= inst
.operands
[3].reg
;
13548 reject_bad_reg (RdLo
);
13549 reject_bad_reg (RdHi
);
13550 reject_bad_reg (Rn
);
13551 reject_bad_reg (Rm
);
13553 inst
.instruction
|= RdLo
<< 12;
13554 inst
.instruction
|= RdHi
<< 8;
13555 inst
.instruction
|= Rn
<< 16;
13556 inst
.instruction
|= Rm
;
13559 as_tsktsk (_("rdhi and rdlo must be different"));
13565 set_pred_insn_type (NEUTRAL_IT_INSN
);
13567 if (unified_syntax
)
13569 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13571 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13572 inst
.instruction
|= inst
.operands
[0].imm
;
13576 /* PR9722: Check for Thumb2 availability before
13577 generating a thumb2 nop instruction. */
13578 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13581 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13584 inst
.instruction
= 0x46c0;
13589 constraint (inst
.operands
[0].present
,
13590 _("Thumb does not support NOP with hints"));
13591 inst
.instruction
= 0x46c0;
13598 if (unified_syntax
)
13600 bfd_boolean narrow
;
13602 if (THUMB_SETS_FLAGS (inst
.instruction
))
13603 narrow
= !in_pred_block ();
13605 narrow
= in_pred_block ();
13606 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13608 if (inst
.size_req
== 4)
13613 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13614 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13615 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13619 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13620 inst
.instruction
|= inst
.operands
[0].reg
;
13621 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13626 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13628 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13630 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13631 inst
.instruction
|= inst
.operands
[0].reg
;
13632 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13641 Rd
= inst
.operands
[0].reg
;
13642 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13644 reject_bad_reg (Rd
);
13645 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13646 reject_bad_reg (Rn
);
13648 inst
.instruction
|= Rd
<< 8;
13649 inst
.instruction
|= Rn
<< 16;
13651 if (!inst
.operands
[2].isreg
)
13653 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13654 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13660 Rm
= inst
.operands
[2].reg
;
13661 reject_bad_reg (Rm
);
13663 constraint (inst
.operands
[2].shifted
13664 && inst
.operands
[2].immisreg
,
13665 _("shift must be constant"));
13666 encode_thumb32_shifted_operand (2);
13673 unsigned Rd
, Rn
, Rm
;
13675 Rd
= inst
.operands
[0].reg
;
13676 Rn
= inst
.operands
[1].reg
;
13677 Rm
= inst
.operands
[2].reg
;
13679 reject_bad_reg (Rd
);
13680 reject_bad_reg (Rn
);
13681 reject_bad_reg (Rm
);
13683 inst
.instruction
|= Rd
<< 8;
13684 inst
.instruction
|= Rn
<< 16;
13685 inst
.instruction
|= Rm
;
13686 if (inst
.operands
[3].present
)
13688 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13689 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13690 _("expression too complex"));
13691 inst
.instruction
|= (val
& 0x1c) << 10;
13692 inst
.instruction
|= (val
& 0x03) << 6;
13699 if (!inst
.operands
[3].present
)
13703 inst
.instruction
&= ~0x00000020;
13705 /* PR 10168. Swap the Rm and Rn registers. */
13706 Rtmp
= inst
.operands
[1].reg
;
13707 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13708 inst
.operands
[2].reg
= Rtmp
;
13716 if (inst
.operands
[0].immisreg
)
13717 reject_bad_reg (inst
.operands
[0].imm
);
13719 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13723 do_t_push_pop (void)
13727 constraint (inst
.operands
[0].writeback
,
13728 _("push/pop do not support {reglist}^"));
13729 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13730 _("expression too complex"));
13732 mask
= inst
.operands
[0].imm
;
13733 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13734 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13735 else if (inst
.size_req
!= 4
13736 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13737 ? REG_LR
: REG_PC
)))
13739 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13740 inst
.instruction
|= THUMB_PP_PC_LR
;
13741 inst
.instruction
|= mask
& 0xff;
13743 else if (unified_syntax
)
13745 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13746 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13750 inst
.error
= _("invalid register list to push/pop instruction");
13758 if (unified_syntax
)
13759 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13762 inst
.error
= _("invalid register list to push/pop instruction");
13768 do_t_vscclrm (void)
13770 if (inst
.operands
[0].issingle
)
13772 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13773 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13774 inst
.instruction
|= inst
.operands
[0].imm
;
13778 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13779 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13780 inst
.instruction
|= 1 << 8;
13781 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13790 Rd
= inst
.operands
[0].reg
;
13791 Rm
= inst
.operands
[1].reg
;
13793 reject_bad_reg (Rd
);
13794 reject_bad_reg (Rm
);
13796 inst
.instruction
|= Rd
<< 8;
13797 inst
.instruction
|= Rm
<< 16;
13798 inst
.instruction
|= Rm
;
13806 Rd
= inst
.operands
[0].reg
;
13807 Rm
= inst
.operands
[1].reg
;
13809 reject_bad_reg (Rd
);
13810 reject_bad_reg (Rm
);
13812 if (Rd
<= 7 && Rm
<= 7
13813 && inst
.size_req
!= 4)
13815 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13816 inst
.instruction
|= Rd
;
13817 inst
.instruction
|= Rm
<< 3;
13819 else if (unified_syntax
)
13821 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13822 inst
.instruction
|= Rd
<< 8;
13823 inst
.instruction
|= Rm
<< 16;
13824 inst
.instruction
|= Rm
;
13827 inst
.error
= BAD_HIREG
;
13835 Rd
= inst
.operands
[0].reg
;
13836 Rm
= inst
.operands
[1].reg
;
13838 reject_bad_reg (Rd
);
13839 reject_bad_reg (Rm
);
13841 inst
.instruction
|= Rd
<< 8;
13842 inst
.instruction
|= Rm
;
13850 Rd
= inst
.operands
[0].reg
;
13851 Rs
= (inst
.operands
[1].present
13852 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13853 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13855 reject_bad_reg (Rd
);
13856 reject_bad_reg (Rs
);
13857 if (inst
.operands
[2].isreg
)
13858 reject_bad_reg (inst
.operands
[2].reg
);
13860 inst
.instruction
|= Rd
<< 8;
13861 inst
.instruction
|= Rs
<< 16;
13862 if (!inst
.operands
[2].isreg
)
13864 bfd_boolean narrow
;
13866 if ((inst
.instruction
& 0x00100000) != 0)
13867 narrow
= !in_pred_block ();
13869 narrow
= in_pred_block ();
13871 if (Rd
> 7 || Rs
> 7)
13874 if (inst
.size_req
== 4 || !unified_syntax
)
13877 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13878 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13881 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13882 relaxation, but it doesn't seem worth the hassle. */
13885 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13886 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13887 inst
.instruction
|= Rs
<< 3;
13888 inst
.instruction
|= Rd
;
13892 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13893 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13897 encode_thumb32_shifted_operand (2);
13903 if (warn_on_deprecated
13904 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13905 as_tsktsk (_("setend use is deprecated for ARMv8"));
13907 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13908 if (inst
.operands
[0].imm
)
13909 inst
.instruction
|= 0x8;
13915 if (!inst
.operands
[1].present
)
13916 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13918 if (unified_syntax
)
13920 bfd_boolean narrow
;
13923 switch (inst
.instruction
)
13926 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13928 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13930 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13932 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13936 if (THUMB_SETS_FLAGS (inst
.instruction
))
13937 narrow
= !in_pred_block ();
13939 narrow
= in_pred_block ();
13940 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13942 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13944 if (inst
.operands
[2].isreg
13945 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13946 || inst
.operands
[2].reg
> 7))
13948 if (inst
.size_req
== 4)
13951 reject_bad_reg (inst
.operands
[0].reg
);
13952 reject_bad_reg (inst
.operands
[1].reg
);
13956 if (inst
.operands
[2].isreg
)
13958 reject_bad_reg (inst
.operands
[2].reg
);
13959 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13960 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13961 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13962 inst
.instruction
|= inst
.operands
[2].reg
;
13964 /* PR 12854: Error on extraneous shifts. */
13965 constraint (inst
.operands
[2].shifted
,
13966 _("extraneous shift as part of operand to shift insn"));
13970 inst
.operands
[1].shifted
= 1;
13971 inst
.operands
[1].shift_kind
= shift_kind
;
13972 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13973 ? T_MNEM_movs
: T_MNEM_mov
);
13974 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13975 encode_thumb32_shifted_operand (1);
13976 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13977 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13982 if (inst
.operands
[2].isreg
)
13984 switch (shift_kind
)
13986 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13987 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13988 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13989 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13993 inst
.instruction
|= inst
.operands
[0].reg
;
13994 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13996 /* PR 12854: Error on extraneous shifts. */
13997 constraint (inst
.operands
[2].shifted
,
13998 _("extraneous shift as part of operand to shift insn"));
14002 switch (shift_kind
)
14004 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14005 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14006 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14009 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14010 inst
.instruction
|= inst
.operands
[0].reg
;
14011 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14017 constraint (inst
.operands
[0].reg
> 7
14018 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14019 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14021 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14023 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14024 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14025 _("source1 and dest must be same register"));
14027 switch (inst
.instruction
)
14029 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14030 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14031 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14032 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14036 inst
.instruction
|= inst
.operands
[0].reg
;
14037 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14039 /* PR 12854: Error on extraneous shifts. */
14040 constraint (inst
.operands
[2].shifted
,
14041 _("extraneous shift as part of operand to shift insn"));
14045 switch (inst
.instruction
)
14047 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14048 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14049 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14050 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14053 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14054 inst
.instruction
|= inst
.operands
[0].reg
;
14055 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14063 unsigned Rd
, Rn
, Rm
;
14065 Rd
= inst
.operands
[0].reg
;
14066 Rn
= inst
.operands
[1].reg
;
14067 Rm
= inst
.operands
[2].reg
;
14069 reject_bad_reg (Rd
);
14070 reject_bad_reg (Rn
);
14071 reject_bad_reg (Rm
);
14073 inst
.instruction
|= Rd
<< 8;
14074 inst
.instruction
|= Rn
<< 16;
14075 inst
.instruction
|= Rm
;
14081 unsigned Rd
, Rn
, Rm
;
14083 Rd
= inst
.operands
[0].reg
;
14084 Rm
= inst
.operands
[1].reg
;
14085 Rn
= inst
.operands
[2].reg
;
14087 reject_bad_reg (Rd
);
14088 reject_bad_reg (Rn
);
14089 reject_bad_reg (Rm
);
14091 inst
.instruction
|= Rd
<< 8;
14092 inst
.instruction
|= Rn
<< 16;
14093 inst
.instruction
|= Rm
;
14099 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14100 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14101 _("SMC is not permitted on this architecture"));
14102 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14103 _("expression too complex"));
14104 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14106 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14107 inst
.instruction
|= (value
& 0x000f) << 16;
14109 /* PR gas/15623: SMC instructions must be last in an IT block. */
14110 set_pred_insn_type_last ();
14116 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14118 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14119 inst
.instruction
|= (value
& 0x0fff);
14120 inst
.instruction
|= (value
& 0xf000) << 4;
14124 do_t_ssat_usat (int bias
)
14128 Rd
= inst
.operands
[0].reg
;
14129 Rn
= inst
.operands
[2].reg
;
14131 reject_bad_reg (Rd
);
14132 reject_bad_reg (Rn
);
14134 inst
.instruction
|= Rd
<< 8;
14135 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14136 inst
.instruction
|= Rn
<< 16;
14138 if (inst
.operands
[3].present
)
14140 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14142 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14144 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14145 _("expression too complex"));
14147 if (shift_amount
!= 0)
14149 constraint (shift_amount
> 31,
14150 _("shift expression is too large"));
14152 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14153 inst
.instruction
|= 0x00200000; /* sh bit. */
14155 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14156 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14164 do_t_ssat_usat (1);
14172 Rd
= inst
.operands
[0].reg
;
14173 Rn
= inst
.operands
[2].reg
;
14175 reject_bad_reg (Rd
);
14176 reject_bad_reg (Rn
);
14178 inst
.instruction
|= Rd
<< 8;
14179 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14180 inst
.instruction
|= Rn
<< 16;
14186 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14187 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14188 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14189 || inst
.operands
[2].negative
,
14192 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14194 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14195 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14196 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14197 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14203 if (!inst
.operands
[2].present
)
14204 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14206 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14207 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14208 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14211 inst
.instruction
|= inst
.operands
[0].reg
;
14212 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14213 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14214 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14220 unsigned Rd
, Rn
, Rm
;
14222 Rd
= inst
.operands
[0].reg
;
14223 Rn
= inst
.operands
[1].reg
;
14224 Rm
= inst
.operands
[2].reg
;
14226 reject_bad_reg (Rd
);
14227 reject_bad_reg (Rn
);
14228 reject_bad_reg (Rm
);
14230 inst
.instruction
|= Rd
<< 8;
14231 inst
.instruction
|= Rn
<< 16;
14232 inst
.instruction
|= Rm
;
14233 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14241 Rd
= inst
.operands
[0].reg
;
14242 Rm
= inst
.operands
[1].reg
;
14244 reject_bad_reg (Rd
);
14245 reject_bad_reg (Rm
);
14247 if (inst
.instruction
<= 0xffff
14248 && inst
.size_req
!= 4
14249 && Rd
<= 7 && Rm
<= 7
14250 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14252 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14253 inst
.instruction
|= Rd
;
14254 inst
.instruction
|= Rm
<< 3;
14256 else if (unified_syntax
)
14258 if (inst
.instruction
<= 0xffff)
14259 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14260 inst
.instruction
|= Rd
<< 8;
14261 inst
.instruction
|= Rm
;
14262 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14266 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14267 _("Thumb encoding does not support rotation"));
14268 constraint (1, BAD_HIREG
);
14275 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14284 half
= (inst
.instruction
& 0x10) != 0;
14285 set_pred_insn_type_last ();
14286 constraint (inst
.operands
[0].immisreg
,
14287 _("instruction requires register index"));
14289 Rn
= inst
.operands
[0].reg
;
14290 Rm
= inst
.operands
[0].imm
;
14292 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14293 constraint (Rn
== REG_SP
, BAD_SP
);
14294 reject_bad_reg (Rm
);
14296 constraint (!half
&& inst
.operands
[0].shifted
,
14297 _("instruction does not allow shifted index"));
14298 inst
.instruction
|= (Rn
<< 16) | Rm
;
14304 if (!inst
.operands
[0].present
)
14305 inst
.operands
[0].imm
= 0;
14307 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14309 constraint (inst
.size_req
== 2,
14310 _("immediate value out of range"));
14311 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14312 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14313 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14317 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14318 inst
.instruction
|= inst
.operands
[0].imm
;
14321 set_pred_insn_type (NEUTRAL_IT_INSN
);
14328 do_t_ssat_usat (0);
14336 Rd
= inst
.operands
[0].reg
;
14337 Rn
= inst
.operands
[2].reg
;
14339 reject_bad_reg (Rd
);
14340 reject_bad_reg (Rn
);
14342 inst
.instruction
|= Rd
<< 8;
14343 inst
.instruction
|= inst
.operands
[1].imm
;
14344 inst
.instruction
|= Rn
<< 16;
14347 /* Checking the range of the branch offset (VAL) with NBITS bits
14348 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14350 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14352 gas_assert (nbits
> 0 && nbits
<= 32);
14355 int cmp
= (1 << (nbits
- 1));
14356 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14361 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14367 /* For branches in Armv8.1-M Mainline. */
14369 do_t_branch_future (void)
14371 unsigned long insn
= inst
.instruction
;
14373 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14374 if (inst
.operands
[0].hasreloc
== 0)
14376 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14377 as_bad (BAD_BRANCH_OFF
);
14379 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14383 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14384 inst
.relocs
[0].pc_rel
= 1;
14390 if (inst
.operands
[1].hasreloc
== 0)
14392 int val
= inst
.operands
[1].imm
;
14393 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14394 as_bad (BAD_BRANCH_OFF
);
14396 int immA
= (val
& 0x0001f000) >> 12;
14397 int immB
= (val
& 0x00000ffc) >> 2;
14398 int immC
= (val
& 0x00000002) >> 1;
14399 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14403 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14404 inst
.relocs
[1].pc_rel
= 1;
14409 if (inst
.operands
[1].hasreloc
== 0)
14411 int val
= inst
.operands
[1].imm
;
14412 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14413 as_bad (BAD_BRANCH_OFF
);
14415 int immA
= (val
& 0x0007f000) >> 12;
14416 int immB
= (val
& 0x00000ffc) >> 2;
14417 int immC
= (val
& 0x00000002) >> 1;
14418 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14422 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14423 inst
.relocs
[1].pc_rel
= 1;
14427 case T_MNEM_bfcsel
:
14429 if (inst
.operands
[1].hasreloc
== 0)
14431 int val
= inst
.operands
[1].imm
;
14432 int immA
= (val
& 0x00001000) >> 12;
14433 int immB
= (val
& 0x00000ffc) >> 2;
14434 int immC
= (val
& 0x00000002) >> 1;
14435 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14439 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14440 inst
.relocs
[1].pc_rel
= 1;
14444 if (inst
.operands
[2].hasreloc
== 0)
14446 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14447 int val2
= inst
.operands
[2].imm
;
14448 int val0
= inst
.operands
[0].imm
& 0x1f;
14449 int diff
= val2
- val0
;
14451 inst
.instruction
|= 1 << 17; /* T bit. */
14452 else if (diff
!= 2)
14453 as_bad (_("out of range label-relative fixup value"));
14457 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14458 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14459 inst
.relocs
[2].pc_rel
= 1;
14463 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14464 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14469 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14476 /* Helper function for do_t_loloop to handle relocations. */
14478 v8_1_loop_reloc (int is_le
)
14480 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14482 int value
= inst
.relocs
[0].exp
.X_add_number
;
14483 value
= (is_le
) ? -value
: value
;
14485 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14486 as_bad (BAD_BRANCH_OFF
);
14490 immh
= (value
& 0x00000ffc) >> 2;
14491 imml
= (value
& 0x00000002) >> 1;
14493 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14497 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14498 inst
.relocs
[0].pc_rel
= 1;
14502 /* For shifts with four operands in MVE. */
14504 do_mve_scalar_shift1 (void)
14506 unsigned int value
= inst
.operands
[2].imm
;
14508 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14509 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14511 /* Setting the bit for saturation. */
14512 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14514 /* Assuming Rm is already checked not to be 11x1. */
14515 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14516 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14517 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14520 /* For shifts in MVE. */
14522 do_mve_scalar_shift (void)
14524 if (!inst
.operands
[2].present
)
14526 inst
.operands
[2] = inst
.operands
[1];
14527 inst
.operands
[1].reg
= 0xf;
14530 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14531 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14533 if (inst
.operands
[2].isreg
)
14535 /* Assuming Rm is already checked not to be 11x1. */
14536 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14537 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14538 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14542 /* Assuming imm is already checked as [1,32]. */
14543 unsigned int value
= inst
.operands
[2].imm
;
14544 inst
.instruction
|= (value
& 0x1c) << 10;
14545 inst
.instruction
|= (value
& 0x03) << 6;
14546 /* Change last 4 bits from 0xd to 0xf. */
14547 inst
.instruction
|= 0x2;
14551 /* MVE instruction encoder helpers. */
14552 #define M_MNEM_vabav 0xee800f01
14553 #define M_MNEM_vmladav 0xeef00e00
14554 #define M_MNEM_vmladava 0xeef00e20
14555 #define M_MNEM_vmladavx 0xeef01e00
14556 #define M_MNEM_vmladavax 0xeef01e20
14557 #define M_MNEM_vmlsdav 0xeef00e01
14558 #define M_MNEM_vmlsdava 0xeef00e21
14559 #define M_MNEM_vmlsdavx 0xeef01e01
14560 #define M_MNEM_vmlsdavax 0xeef01e21
14561 #define M_MNEM_vmullt 0xee011e00
14562 #define M_MNEM_vmullb 0xee010e00
14563 #define M_MNEM_vctp 0xf000e801
14564 #define M_MNEM_vst20 0xfc801e00
14565 #define M_MNEM_vst21 0xfc801e20
14566 #define M_MNEM_vst40 0xfc801e01
14567 #define M_MNEM_vst41 0xfc801e21
14568 #define M_MNEM_vst42 0xfc801e41
14569 #define M_MNEM_vst43 0xfc801e61
14570 #define M_MNEM_vld20 0xfc901e00
14571 #define M_MNEM_vld21 0xfc901e20
14572 #define M_MNEM_vld40 0xfc901e01
14573 #define M_MNEM_vld41 0xfc901e21
14574 #define M_MNEM_vld42 0xfc901e41
14575 #define M_MNEM_vld43 0xfc901e61
14576 #define M_MNEM_vstrb 0xec000e00
14577 #define M_MNEM_vstrh 0xec000e10
14578 #define M_MNEM_vstrw 0xec000e40
14579 #define M_MNEM_vstrd 0xec000e50
14580 #define M_MNEM_vldrb 0xec100e00
14581 #define M_MNEM_vldrh 0xec100e10
14582 #define M_MNEM_vldrw 0xec100e40
14583 #define M_MNEM_vldrd 0xec100e50
14584 #define M_MNEM_vmovlt 0xeea01f40
14585 #define M_MNEM_vmovlb 0xeea00f40
14586 #define M_MNEM_vmovnt 0xfe311e81
14587 #define M_MNEM_vmovnb 0xfe310e81
14588 #define M_MNEM_vadc 0xee300f00
14589 #define M_MNEM_vadci 0xee301f00
14590 #define M_MNEM_vbrsr 0xfe011e60
14591 #define M_MNEM_vaddlv 0xee890f00
14592 #define M_MNEM_vaddlva 0xee890f20
14593 #define M_MNEM_vaddv 0xeef10f00
14594 #define M_MNEM_vaddva 0xeef10f20
14595 #define M_MNEM_vddup 0xee011f6e
14596 #define M_MNEM_vdwdup 0xee011f60
14597 #define M_MNEM_vidup 0xee010f6e
14598 #define M_MNEM_viwdup 0xee010f60
14599 #define M_MNEM_vmaxv 0xeee20f00
14600 #define M_MNEM_vmaxav 0xeee00f00
14601 #define M_MNEM_vminv 0xeee20f80
14602 #define M_MNEM_vminav 0xeee00f80
14603 #define M_MNEM_vmlaldav 0xee800e00
14604 #define M_MNEM_vmlaldava 0xee800e20
14605 #define M_MNEM_vmlaldavx 0xee801e00
14606 #define M_MNEM_vmlaldavax 0xee801e20
14607 #define M_MNEM_vmlsldav 0xee800e01
14608 #define M_MNEM_vmlsldava 0xee800e21
14609 #define M_MNEM_vmlsldavx 0xee801e01
14610 #define M_MNEM_vmlsldavax 0xee801e21
14611 #define M_MNEM_vrmlaldavhx 0xee801f00
14612 #define M_MNEM_vrmlaldavhax 0xee801f20
14613 #define M_MNEM_vrmlsldavh 0xfe800e01
14614 #define M_MNEM_vrmlsldavha 0xfe800e21
14615 #define M_MNEM_vrmlsldavhx 0xfe801e01
14616 #define M_MNEM_vrmlsldavhax 0xfe801e21
14617 #define M_MNEM_vqmovnt 0xee331e01
14618 #define M_MNEM_vqmovnb 0xee330e01
14619 #define M_MNEM_vqmovunt 0xee311e81
14620 #define M_MNEM_vqmovunb 0xee310e81
14621 #define M_MNEM_vshrnt 0xee801fc1
14622 #define M_MNEM_vshrnb 0xee800fc1
14623 #define M_MNEM_vrshrnt 0xfe801fc1
14624 #define M_MNEM_vqshrnt 0xee801f40
14625 #define M_MNEM_vqshrnb 0xee800f40
14626 #define M_MNEM_vqshrunt 0xee801fc0
14627 #define M_MNEM_vqshrunb 0xee800fc0
14628 #define M_MNEM_vrshrnb 0xfe800fc1
14629 #define M_MNEM_vqrshrnt 0xee801f41
14630 #define M_MNEM_vqrshrnb 0xee800f41
14631 #define M_MNEM_vqrshrunt 0xfe801fc0
14632 #define M_MNEM_vqrshrunb 0xfe800fc0
14634 /* Bfloat16 instruction encoder helpers. */
14635 #define B_MNEM_vfmat 0xfc300850
14636 #define B_MNEM_vfmab 0xfc300810
14638 /* Neon instruction encoder helpers. */
14640 /* Encodings for the different types for various Neon opcodes. */
14642 /* An "invalid" code for the following tables. */
14645 struct neon_tab_entry
14648 unsigned float_or_poly
;
14649 unsigned scalar_or_imm
;
14652 /* Map overloaded Neon opcodes to their respective encodings. */
14653 #define NEON_ENC_TAB \
14654 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14655 X(vabdl, 0x0800700, N_INV, N_INV), \
14656 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14657 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14658 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14659 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14660 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14661 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14662 X(vaddl, 0x0800000, N_INV, N_INV), \
14663 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14664 X(vsubl, 0x0800200, N_INV, N_INV), \
14665 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14666 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14667 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14668 /* Register variants of the following two instructions are encoded as
14669 vcge / vcgt with the operands reversed. */ \
14670 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14671 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14672 X(vfma, N_INV, 0x0000c10, N_INV), \
14673 X(vfms, N_INV, 0x0200c10, N_INV), \
14674 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14675 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14676 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14677 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14678 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14679 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14680 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14681 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14682 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14683 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14684 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14685 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14686 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14687 X(vshl, 0x0000400, N_INV, 0x0800510), \
14688 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14689 X(vand, 0x0000110, N_INV, 0x0800030), \
14690 X(vbic, 0x0100110, N_INV, 0x0800030), \
14691 X(veor, 0x1000110, N_INV, N_INV), \
14692 X(vorn, 0x0300110, N_INV, 0x0800010), \
14693 X(vorr, 0x0200110, N_INV, 0x0800010), \
14694 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14695 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14696 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14697 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14698 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14699 X(vst1, 0x0000000, 0x0800000, N_INV), \
14700 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14701 X(vst2, 0x0000100, 0x0800100, N_INV), \
14702 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14703 X(vst3, 0x0000200, 0x0800200, N_INV), \
14704 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14705 X(vst4, 0x0000300, 0x0800300, N_INV), \
14706 X(vmovn, 0x1b20200, N_INV, N_INV), \
14707 X(vtrn, 0x1b20080, N_INV, N_INV), \
14708 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14709 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14710 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14711 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14712 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14713 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14714 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14715 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14716 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14717 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14718 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14719 X(vseleq, 0xe000a00, N_INV, N_INV), \
14720 X(vselvs, 0xe100a00, N_INV, N_INV), \
14721 X(vselge, 0xe200a00, N_INV, N_INV), \
14722 X(vselgt, 0xe300a00, N_INV, N_INV), \
14723 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14724 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14725 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14726 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14727 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14728 X(aes, 0x3b00300, N_INV, N_INV), \
14729 X(sha3op, 0x2000c00, N_INV, N_INV), \
14730 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14731 X(sha2op, 0x3ba0380, N_INV, N_INV)
14735 #define X(OPC,I,F,S) N_MNEM_##OPC
14740 static const struct neon_tab_entry neon_enc_tab
[] =
14742 #define X(OPC,I,F,S) { (I), (F), (S) }
14747 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14748 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14749 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14750 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14751 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14752 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14753 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14754 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14755 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14756 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14757 #define NEON_ENC_SINGLE_(X) \
14758 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14759 #define NEON_ENC_DOUBLE_(X) \
14760 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14761 #define NEON_ENC_FPV8_(X) \
14762 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14764 #define NEON_ENCODE(type, inst) \
14767 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14768 inst.is_neon = 1; \
14772 #define check_neon_suffixes \
14775 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14777 as_bad (_("invalid neon suffix for non neon instruction")); \
14783 /* Define shapes for instruction operands. The following mnemonic characters
14784 are used in this table:
14786 F - VFP S<n> register
14787 D - Neon D<n> register
14788 Q - Neon Q<n> register
14792 L - D<n> register list
14794 This table is used to generate various data:
14795 - enumerations of the form NS_DDR to be used as arguments to
14797 - a table classifying shapes into single, double, quad, mixed.
14798 - a table used to drive neon_select_shape. */
14800 #define NEON_SHAPE_DEF \
14801 X(4, (R, R, Q, Q), QUAD), \
14802 X(4, (Q, R, R, I), QUAD), \
14803 X(4, (R, R, S, S), QUAD), \
14804 X(4, (S, S, R, R), QUAD), \
14805 X(3, (Q, R, I), QUAD), \
14806 X(3, (I, Q, Q), QUAD), \
14807 X(3, (I, Q, R), QUAD), \
14808 X(3, (R, Q, Q), QUAD), \
14809 X(3, (D, D, D), DOUBLE), \
14810 X(3, (Q, Q, Q), QUAD), \
14811 X(3, (D, D, I), DOUBLE), \
14812 X(3, (Q, Q, I), QUAD), \
14813 X(3, (D, D, S), DOUBLE), \
14814 X(3, (Q, Q, S), QUAD), \
14815 X(3, (Q, Q, R), QUAD), \
14816 X(3, (R, R, Q), QUAD), \
14817 X(2, (R, Q), QUAD), \
14818 X(2, (D, D), DOUBLE), \
14819 X(2, (Q, Q), QUAD), \
14820 X(2, (D, S), DOUBLE), \
14821 X(2, (Q, S), QUAD), \
14822 X(2, (D, R), DOUBLE), \
14823 X(2, (Q, R), QUAD), \
14824 X(2, (D, I), DOUBLE), \
14825 X(2, (Q, I), QUAD), \
14826 X(3, (P, F, I), SINGLE), \
14827 X(3, (P, D, I), DOUBLE), \
14828 X(3, (P, Q, I), QUAD), \
14829 X(4, (P, F, F, I), SINGLE), \
14830 X(4, (P, D, D, I), DOUBLE), \
14831 X(4, (P, Q, Q, I), QUAD), \
14832 X(5, (P, F, F, F, I), SINGLE), \
14833 X(5, (P, D, D, D, I), DOUBLE), \
14834 X(5, (P, Q, Q, Q, I), QUAD), \
14835 X(3, (D, L, D), DOUBLE), \
14836 X(2, (D, Q), MIXED), \
14837 X(2, (Q, D), MIXED), \
14838 X(3, (D, Q, I), MIXED), \
14839 X(3, (Q, D, I), MIXED), \
14840 X(3, (Q, D, D), MIXED), \
14841 X(3, (D, Q, Q), MIXED), \
14842 X(3, (Q, Q, D), MIXED), \
14843 X(3, (Q, D, S), MIXED), \
14844 X(3, (D, Q, S), MIXED), \
14845 X(4, (D, D, D, I), DOUBLE), \
14846 X(4, (Q, Q, Q, I), QUAD), \
14847 X(4, (D, D, S, I), DOUBLE), \
14848 X(4, (Q, Q, S, I), QUAD), \
14849 X(2, (F, F), SINGLE), \
14850 X(3, (F, F, F), SINGLE), \
14851 X(2, (F, I), SINGLE), \
14852 X(2, (F, D), MIXED), \
14853 X(2, (D, F), MIXED), \
14854 X(3, (F, F, I), MIXED), \
14855 X(4, (R, R, F, F), SINGLE), \
14856 X(4, (F, F, R, R), SINGLE), \
14857 X(3, (D, R, R), DOUBLE), \
14858 X(3, (R, R, D), DOUBLE), \
14859 X(2, (S, R), SINGLE), \
14860 X(2, (R, S), SINGLE), \
14861 X(2, (F, R), SINGLE), \
14862 X(2, (R, F), SINGLE), \
14863 /* Used for MVE tail predicated loop instructions. */\
14864 X(2, (R, R), QUAD), \
14865 /* Half float shape supported so far. */\
14866 X (2, (H, D), MIXED), \
14867 X (2, (D, H), MIXED), \
14868 X (2, (H, F), MIXED), \
14869 X (2, (F, H), MIXED), \
14870 X (2, (H, H), HALF), \
14871 X (2, (H, R), HALF), \
14872 X (2, (R, H), HALF), \
14873 X (2, (H, I), HALF), \
14874 X (3, (H, H, H), HALF), \
14875 X (3, (H, F, I), MIXED), \
14876 X (3, (F, H, I), MIXED), \
14877 X (3, (D, H, H), MIXED), \
14878 X (3, (D, H, S), MIXED)
14880 #define S2(A,B) NS_##A##B
14881 #define S3(A,B,C) NS_##A##B##C
14882 #define S4(A,B,C,D) NS_##A##B##C##D
14883 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14885 #define X(N, L, C) S##N L
14899 enum neon_shape_class
14908 #define X(N, L, C) SC_##C
14910 static enum neon_shape_class neon_shape_class
[] =
14930 /* Register widths of above. */
14931 static unsigned neon_shape_el_size
[] =
14944 struct neon_shape_info
14947 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14950 #define S2(A,B) { SE_##A, SE_##B }
14951 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14952 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14953 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14955 #define X(N, L, C) { N, S##N L }
14957 static struct neon_shape_info neon_shape_tab
[] =
14968 /* Bit masks used in type checking given instructions.
14969 'N_EQK' means the type must be the same as (or based on in some way) the key
14970 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14971 set, various other bits can be set as well in order to modify the meaning of
14972 the type constraint. */
14974 enum neon_type_mask
14998 N_BF16
= 0x0400000,
14999 N_KEY
= 0x1000000, /* Key element (main type specifier). */
15000 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
15001 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
15002 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
15003 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
15004 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
15005 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15006 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15007 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15008 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15009 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15011 N_MAX_NONSPECIAL
= N_P64
15014 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15016 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15017 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15018 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15019 #define N_S_32 (N_S8 | N_S16 | N_S32)
15020 #define N_F_16_32 (N_F16 | N_F32)
15021 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15022 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15023 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15024 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15025 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15026 #define N_F_MVE (N_F16 | N_F32)
15027 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15029 /* Pass this as the first type argument to neon_check_type to ignore types
15031 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15033 /* Select a "shape" for the current instruction (describing register types or
15034 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15035 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15036 function of operand parsing, so this function doesn't need to be called.
15037 Shapes should be listed in order of decreasing length. */
15039 static enum neon_shape
15040 neon_select_shape (enum neon_shape shape
, ...)
15043 enum neon_shape first_shape
= shape
;
15045 /* Fix missing optional operands. FIXME: we don't know at this point how
15046 many arguments we should have, so this makes the assumption that we have
15047 > 1. This is true of all current Neon opcodes, I think, but may not be
15048 true in the future. */
15049 if (!inst
.operands
[1].present
)
15050 inst
.operands
[1] = inst
.operands
[0];
15052 va_start (ap
, shape
);
15054 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15059 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15061 if (!inst
.operands
[j
].present
)
15067 switch (neon_shape_tab
[shape
].el
[j
])
15069 /* If a .f16, .16, .u16, .s16 type specifier is given over
15070 a VFP single precision register operand, it's essentially
15071 means only half of the register is used.
15073 If the type specifier is given after the mnemonics, the
15074 information is stored in inst.vectype. If the type specifier
15075 is given after register operand, the information is stored
15076 in inst.operands[].vectype.
15078 When there is only one type specifier, and all the register
15079 operands are the same type of hardware register, the type
15080 specifier applies to all register operands.
15082 If no type specifier is given, the shape is inferred from
15083 operand information.
15086 vadd.f16 s0, s1, s2: NS_HHH
15087 vabs.f16 s0, s1: NS_HH
15088 vmov.f16 s0, r1: NS_HR
15089 vmov.f16 r0, s1: NS_RH
15090 vcvt.f16 r0, s1: NS_RH
15091 vcvt.f16.s32 s2, s2, #29: NS_HFI
15092 vcvt.f16.s32 s2, s2: NS_HF
15095 if (!(inst
.operands
[j
].isreg
15096 && inst
.operands
[j
].isvec
15097 && inst
.operands
[j
].issingle
15098 && !inst
.operands
[j
].isquad
15099 && ((inst
.vectype
.elems
== 1
15100 && inst
.vectype
.el
[0].size
== 16)
15101 || (inst
.vectype
.elems
> 1
15102 && inst
.vectype
.el
[j
].size
== 16)
15103 || (inst
.vectype
.elems
== 0
15104 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15105 && inst
.operands
[j
].vectype
.size
== 16))))
15110 if (!(inst
.operands
[j
].isreg
15111 && inst
.operands
[j
].isvec
15112 && inst
.operands
[j
].issingle
15113 && !inst
.operands
[j
].isquad
15114 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15115 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15116 || (inst
.vectype
.elems
== 0
15117 && (inst
.operands
[j
].vectype
.size
== 32
15118 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15123 if (!(inst
.operands
[j
].isreg
15124 && inst
.operands
[j
].isvec
15125 && !inst
.operands
[j
].isquad
15126 && !inst
.operands
[j
].issingle
))
15131 if (!(inst
.operands
[j
].isreg
15132 && !inst
.operands
[j
].isvec
))
15137 if (!(inst
.operands
[j
].isreg
15138 && inst
.operands
[j
].isvec
15139 && inst
.operands
[j
].isquad
15140 && !inst
.operands
[j
].issingle
))
15145 if (!(!inst
.operands
[j
].isreg
15146 && !inst
.operands
[j
].isscalar
))
15151 if (!(!inst
.operands
[j
].isreg
15152 && inst
.operands
[j
].isscalar
))
15163 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15164 /* We've matched all the entries in the shape table, and we don't
15165 have any left over operands which have not been matched. */
15171 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15172 first_error (_("invalid instruction shape"));
15177 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15178 means the Q bit should be set). */
15181 neon_quad (enum neon_shape shape
)
15183 return neon_shape_class
[shape
] == SC_QUAD
;
15187 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15190 /* Allow modification to be made to types which are constrained to be
15191 based on the key element, based on bits set alongside N_EQK. */
15192 if ((typebits
& N_EQK
) != 0)
15194 if ((typebits
& N_HLF
) != 0)
15196 else if ((typebits
& N_DBL
) != 0)
15198 if ((typebits
& N_SGN
) != 0)
15199 *g_type
= NT_signed
;
15200 else if ((typebits
& N_UNS
) != 0)
15201 *g_type
= NT_unsigned
;
15202 else if ((typebits
& N_INT
) != 0)
15203 *g_type
= NT_integer
;
15204 else if ((typebits
& N_FLT
) != 0)
15205 *g_type
= NT_float
;
15206 else if ((typebits
& N_SIZ
) != 0)
15207 *g_type
= NT_untyped
;
15211 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15212 operand type, i.e. the single type specified in a Neon instruction when it
15213 is the only one given. */
15215 static struct neon_type_el
15216 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15218 struct neon_type_el dest
= *key
;
15220 gas_assert ((thisarg
& N_EQK
) != 0);
15222 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15227 /* Convert Neon type and size into compact bitmask representation. */
15229 static enum neon_type_mask
15230 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15237 case 8: return N_8
;
15238 case 16: return N_16
;
15239 case 32: return N_32
;
15240 case 64: return N_64
;
15248 case 8: return N_I8
;
15249 case 16: return N_I16
;
15250 case 32: return N_I32
;
15251 case 64: return N_I64
;
15259 case 16: return N_F16
;
15260 case 32: return N_F32
;
15261 case 64: return N_F64
;
15269 case 8: return N_P8
;
15270 case 16: return N_P16
;
15271 case 64: return N_P64
;
15279 case 8: return N_S8
;
15280 case 16: return N_S16
;
15281 case 32: return N_S32
;
15282 case 64: return N_S64
;
15290 case 8: return N_U8
;
15291 case 16: return N_U16
;
15292 case 32: return N_U32
;
15293 case 64: return N_U64
;
15299 if (size
== 16) return N_BF16
;
15308 /* Convert compact Neon bitmask type representation to a type and size. Only
15309 handles the case where a single bit is set in the mask. */
15312 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15313 enum neon_type_mask mask
)
15315 if ((mask
& N_EQK
) != 0)
15318 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15320 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15323 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15325 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15330 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15332 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15333 *type
= NT_unsigned
;
15334 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15335 *type
= NT_integer
;
15336 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15337 *type
= NT_untyped
;
15338 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15340 else if ((mask
& (N_F_ALL
)) != 0)
15342 else if ((mask
& (N_BF16
)) != 0)
15350 /* Modify a bitmask of allowed types. This is only needed for type
15354 modify_types_allowed (unsigned allowed
, unsigned mods
)
15357 enum neon_el_type type
;
15363 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15365 if (el_type_of_type_chk (&type
, &size
,
15366 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15368 neon_modify_type_size (mods
, &type
, &size
);
15369 destmask
|= type_chk_of_el_type (type
, size
);
15376 /* Check type and return type classification.
15377 The manual states (paraphrase): If one datatype is given, it indicates the
15379 - the second operand, if there is one
15380 - the operand, if there is no second operand
15381 - the result, if there are no operands.
15382 This isn't quite good enough though, so we use a concept of a "key" datatype
15383 which is set on a per-instruction basis, which is the one which matters when
15384 only one data type is written.
15385 Note: this function has side-effects (e.g. filling in missing operands). All
15386 Neon instructions should call it before performing bit encoding. */
15388 static struct neon_type_el
15389 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15392 unsigned i
, pass
, key_el
= 0;
15393 unsigned types
[NEON_MAX_TYPE_ELS
];
15394 enum neon_el_type k_type
= NT_invtype
;
15395 unsigned k_size
= -1u;
15396 struct neon_type_el badtype
= {NT_invtype
, -1};
15397 unsigned key_allowed
= 0;
15399 /* Optional registers in Neon instructions are always (not) in operand 1.
15400 Fill in the missing operand here, if it was omitted. */
15401 if (els
> 1 && !inst
.operands
[1].present
)
15402 inst
.operands
[1] = inst
.operands
[0];
15404 /* Suck up all the varargs. */
15406 for (i
= 0; i
< els
; i
++)
15408 unsigned thisarg
= va_arg (ap
, unsigned);
15409 if (thisarg
== N_IGNORE_TYPE
)
15414 types
[i
] = thisarg
;
15415 if ((thisarg
& N_KEY
) != 0)
15420 if (inst
.vectype
.elems
> 0)
15421 for (i
= 0; i
< els
; i
++)
15422 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15424 first_error (_("types specified in both the mnemonic and operands"));
15428 /* Duplicate inst.vectype elements here as necessary.
15429 FIXME: No idea if this is exactly the same as the ARM assembler,
15430 particularly when an insn takes one register and one non-register
15432 if (inst
.vectype
.elems
== 1 && els
> 1)
15435 inst
.vectype
.elems
= els
;
15436 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15437 for (j
= 0; j
< els
; j
++)
15439 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15442 else if (inst
.vectype
.elems
== 0 && els
> 0)
15445 /* No types were given after the mnemonic, so look for types specified
15446 after each operand. We allow some flexibility here; as long as the
15447 "key" operand has a type, we can infer the others. */
15448 for (j
= 0; j
< els
; j
++)
15449 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15450 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15452 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15454 for (j
= 0; j
< els
; j
++)
15455 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15456 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15461 first_error (_("operand types can't be inferred"));
15465 else if (inst
.vectype
.elems
!= els
)
15467 first_error (_("type specifier has the wrong number of parts"));
15471 for (pass
= 0; pass
< 2; pass
++)
15473 for (i
= 0; i
< els
; i
++)
15475 unsigned thisarg
= types
[i
];
15476 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15477 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15478 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15479 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15481 /* Decay more-specific signed & unsigned types to sign-insensitive
15482 integer types if sign-specific variants are unavailable. */
15483 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15484 && (types_allowed
& N_SU_ALL
) == 0)
15485 g_type
= NT_integer
;
15487 /* If only untyped args are allowed, decay any more specific types to
15488 them. Some instructions only care about signs for some element
15489 sizes, so handle that properly. */
15490 if (((types_allowed
& N_UNT
) == 0)
15491 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15492 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15493 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15494 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15495 g_type
= NT_untyped
;
15499 if ((thisarg
& N_KEY
) != 0)
15503 key_allowed
= thisarg
& ~N_KEY
;
15505 /* Check architecture constraint on FP16 extension. */
15507 && k_type
== NT_float
15508 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15510 inst
.error
= _(BAD_FP16
);
15517 if ((thisarg
& N_VFP
) != 0)
15519 enum neon_shape_el regshape
;
15520 unsigned regwidth
, match
;
15522 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15525 first_error (_("invalid instruction shape"));
15528 regshape
= neon_shape_tab
[ns
].el
[i
];
15529 regwidth
= neon_shape_el_size
[regshape
];
15531 /* In VFP mode, operands must match register widths. If we
15532 have a key operand, use its width, else use the width of
15533 the current operand. */
15539 /* FP16 will use a single precision register. */
15540 if (regwidth
== 32 && match
== 16)
15542 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15546 inst
.error
= _(BAD_FP16
);
15551 if (regwidth
!= match
)
15553 first_error (_("operand size must match register width"));
15558 if ((thisarg
& N_EQK
) == 0)
15560 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15562 if ((given_type
& types_allowed
) == 0)
15564 first_error (BAD_SIMD_TYPE
);
15570 enum neon_el_type mod_k_type
= k_type
;
15571 unsigned mod_k_size
= k_size
;
15572 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15573 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15575 first_error (_("inconsistent types in Neon instruction"));
15583 return inst
.vectype
.el
[key_el
];
15586 /* Neon-style VFP instruction forwarding. */
15588 /* Thumb VFP instructions have 0xE in the condition field. */
15591 do_vfp_cond_or_thumb (void)
15596 inst
.instruction
|= 0xe0000000;
15598 inst
.instruction
|= inst
.cond
<< 28;
15601 /* Look up and encode a simple mnemonic, for use as a helper function for the
15602 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15603 etc. It is assumed that operand parsing has already been done, and that the
15604 operands are in the form expected by the given opcode (this isn't necessarily
15605 the same as the form in which they were parsed, hence some massaging must
15606 take place before this function is called).
15607 Checks current arch version against that in the looked-up opcode. */
15610 do_vfp_nsyn_opcode (const char *opname
)
15612 const struct asm_opcode
*opcode
;
15614 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15619 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15620 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15627 inst
.instruction
= opcode
->tvalue
;
15628 opcode
->tencode ();
15632 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15633 opcode
->aencode ();
15638 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15640 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15642 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15645 do_vfp_nsyn_opcode ("fadds");
15647 do_vfp_nsyn_opcode ("fsubs");
15649 /* ARMv8.2 fp16 instruction. */
15651 do_scalar_fp16_v82_encode ();
15656 do_vfp_nsyn_opcode ("faddd");
15658 do_vfp_nsyn_opcode ("fsubd");
15662 /* Check operand types to see if this is a VFP instruction, and if so call
15666 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15668 enum neon_shape rs
;
15669 struct neon_type_el et
;
15674 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15675 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15679 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15680 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15681 N_F_ALL
| N_KEY
| N_VFP
);
15688 if (et
.type
!= NT_invtype
)
15699 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15701 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15703 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15706 do_vfp_nsyn_opcode ("fmacs");
15708 do_vfp_nsyn_opcode ("fnmacs");
15710 /* ARMv8.2 fp16 instruction. */
15712 do_scalar_fp16_v82_encode ();
15717 do_vfp_nsyn_opcode ("fmacd");
15719 do_vfp_nsyn_opcode ("fnmacd");
15724 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15726 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15728 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15731 do_vfp_nsyn_opcode ("ffmas");
15733 do_vfp_nsyn_opcode ("ffnmas");
15735 /* ARMv8.2 fp16 instruction. */
15737 do_scalar_fp16_v82_encode ();
15742 do_vfp_nsyn_opcode ("ffmad");
15744 do_vfp_nsyn_opcode ("ffnmad");
15749 do_vfp_nsyn_mul (enum neon_shape rs
)
15751 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15753 do_vfp_nsyn_opcode ("fmuls");
15755 /* ARMv8.2 fp16 instruction. */
15757 do_scalar_fp16_v82_encode ();
15760 do_vfp_nsyn_opcode ("fmuld");
15764 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15766 int is_neg
= (inst
.instruction
& 0x80) != 0;
15767 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15769 if (rs
== NS_FF
|| rs
== NS_HH
)
15772 do_vfp_nsyn_opcode ("fnegs");
15774 do_vfp_nsyn_opcode ("fabss");
15776 /* ARMv8.2 fp16 instruction. */
15778 do_scalar_fp16_v82_encode ();
15783 do_vfp_nsyn_opcode ("fnegd");
15785 do_vfp_nsyn_opcode ("fabsd");
15789 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15790 insns belong to Neon, and are handled elsewhere. */
15793 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15795 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15799 do_vfp_nsyn_opcode ("fldmdbs");
15801 do_vfp_nsyn_opcode ("fldmias");
15806 do_vfp_nsyn_opcode ("fstmdbs");
15808 do_vfp_nsyn_opcode ("fstmias");
15813 do_vfp_nsyn_sqrt (void)
15815 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15816 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15818 if (rs
== NS_FF
|| rs
== NS_HH
)
15820 do_vfp_nsyn_opcode ("fsqrts");
15822 /* ARMv8.2 fp16 instruction. */
15824 do_scalar_fp16_v82_encode ();
15827 do_vfp_nsyn_opcode ("fsqrtd");
15831 do_vfp_nsyn_div (void)
15833 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15834 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15835 N_F_ALL
| N_KEY
| N_VFP
);
15837 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15839 do_vfp_nsyn_opcode ("fdivs");
15841 /* ARMv8.2 fp16 instruction. */
15843 do_scalar_fp16_v82_encode ();
15846 do_vfp_nsyn_opcode ("fdivd");
15850 do_vfp_nsyn_nmul (void)
15852 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15853 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15854 N_F_ALL
| N_KEY
| N_VFP
);
15856 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15858 NEON_ENCODE (SINGLE
, inst
);
15859 do_vfp_sp_dyadic ();
15861 /* ARMv8.2 fp16 instruction. */
15863 do_scalar_fp16_v82_encode ();
15867 NEON_ENCODE (DOUBLE
, inst
);
15868 do_vfp_dp_rd_rn_rm ();
15870 do_vfp_cond_or_thumb ();
15874 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15878 neon_logbits (unsigned x
)
15880 return ffs (x
) - 4;
15883 #define LOW4(R) ((R) & 0xf)
15884 #define HI1(R) (((R) >> 4) & 1)
15885 #define LOW1(R) ((R) & 0x1)
15886 #define HI4(R) (((R) >> 1) & 0xf)
15889 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15894 first_error (BAD_EL_TYPE
);
15897 switch (inst
.operands
[0].imm
)
15900 first_error (_("invalid condition"));
15922 /* only accept eq and ne. */
15923 if (inst
.operands
[0].imm
> 1)
15925 first_error (_("invalid condition"));
15928 return inst
.operands
[0].imm
;
15930 if (inst
.operands
[0].imm
== 0x2)
15932 else if (inst
.operands
[0].imm
== 0x8)
15936 first_error (_("invalid condition"));
15940 switch (inst
.operands
[0].imm
)
15943 first_error (_("invalid condition"));
15959 /* Should be unreachable. */
15963 /* For VCTP (create vector tail predicate) in MVE. */
15968 unsigned size
= 0x0;
15970 if (inst
.cond
> COND_ALWAYS
)
15971 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15973 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15975 /* This is a typical MVE instruction which has no type but have size 8, 16,
15976 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15977 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15978 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15979 dt
= inst
.vectype
.el
[0].size
;
15981 /* Setting this does not indicate an actual NEON instruction, but only
15982 indicates that the mnemonic accepts neon-style type suffixes. */
15996 first_error (_("Type is not allowed for this instruction"));
15998 inst
.instruction
|= size
<< 20;
15999 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16005 /* We are dealing with a vector predicated block. */
16006 if (inst
.operands
[0].present
)
16008 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16009 struct neon_type_el et
16010 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16013 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16015 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16017 if (et
.type
== NT_invtype
)
16020 if (et
.type
== NT_float
)
16022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16024 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16025 inst
.instruction
|= (et
.size
== 16) << 28;
16026 inst
.instruction
|= 0x3 << 20;
16030 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16032 inst
.instruction
|= 1 << 28;
16033 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16036 if (inst
.operands
[2].isquad
)
16038 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16039 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16040 inst
.instruction
|= (fcond
& 0x2) >> 1;
16044 if (inst
.operands
[2].reg
== REG_SP
)
16045 as_tsktsk (MVE_BAD_SP
);
16046 inst
.instruction
|= 1 << 6;
16047 inst
.instruction
|= (fcond
& 0x2) << 4;
16048 inst
.instruction
|= inst
.operands
[2].reg
;
16050 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16051 inst
.instruction
|= (fcond
& 0x4) << 10;
16052 inst
.instruction
|= (fcond
& 0x1) << 7;
16055 set_pred_insn_type (VPT_INSN
);
16057 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16058 | ((inst
.instruction
& 0xe000) >> 13);
16059 now_pred
.warn_deprecated
= FALSE
;
16060 now_pred
.type
= VECTOR_PRED
;
16067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16068 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16069 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16070 if (!inst
.operands
[2].present
)
16071 first_error (_("MVE vector or ARM register expected"));
16072 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16074 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16075 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16076 && inst
.operands
[1].isquad
)
16078 inst
.instruction
= N_MNEM_vcmp
;
16082 if (inst
.cond
> COND_ALWAYS
)
16083 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16085 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16087 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16088 struct neon_type_el et
16089 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16092 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16093 && !inst
.operands
[2].iszr
, BAD_PC
);
16095 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16097 inst
.instruction
= 0xee010f00;
16098 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16099 inst
.instruction
|= (fcond
& 0x4) << 10;
16100 inst
.instruction
|= (fcond
& 0x1) << 7;
16101 if (et
.type
== NT_float
)
16103 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16105 inst
.instruction
|= (et
.size
== 16) << 28;
16106 inst
.instruction
|= 0x3 << 20;
16110 inst
.instruction
|= 1 << 28;
16111 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16113 if (inst
.operands
[2].isquad
)
16115 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16116 inst
.instruction
|= (fcond
& 0x2) >> 1;
16117 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16121 if (inst
.operands
[2].reg
== REG_SP
)
16122 as_tsktsk (MVE_BAD_SP
);
16123 inst
.instruction
|= 1 << 6;
16124 inst
.instruction
|= (fcond
& 0x2) << 4;
16125 inst
.instruction
|= inst
.operands
[2].reg
;
16133 do_mve_vmaxa_vmina (void)
16135 if (inst
.cond
> COND_ALWAYS
)
16136 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16138 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16140 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16141 struct neon_type_el et
16142 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16145 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16147 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16153 do_mve_vfmas (void)
16155 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16156 struct neon_type_el et
16157 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16159 if (inst
.cond
> COND_ALWAYS
)
16160 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16162 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16164 if (inst
.operands
[2].reg
== REG_SP
)
16165 as_tsktsk (MVE_BAD_SP
);
16166 else if (inst
.operands
[2].reg
== REG_PC
)
16167 as_tsktsk (MVE_BAD_PC
);
16169 inst
.instruction
|= (et
.size
== 16) << 28;
16170 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16171 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16173 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16174 inst
.instruction
|= inst
.operands
[2].reg
;
16179 do_mve_viddup (void)
16181 if (inst
.cond
> COND_ALWAYS
)
16182 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16184 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16186 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16187 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16188 _("immediate must be either 1, 2, 4 or 8"));
16190 enum neon_shape rs
;
16191 struct neon_type_el et
;
16193 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16195 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16196 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16201 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16202 if (inst
.operands
[2].reg
== REG_SP
)
16203 as_tsktsk (MVE_BAD_SP
);
16204 else if (inst
.operands
[2].reg
== REG_PC
)
16205 first_error (BAD_PC
);
16207 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16208 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16209 Rm
= inst
.operands
[2].reg
>> 1;
16211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16212 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16213 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16214 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16215 inst
.instruction
|= (imm
> 2) << 7;
16216 inst
.instruction
|= Rm
<< 1;
16217 inst
.instruction
|= (imm
== 2 || imm
== 8);
16222 do_mve_vmlas (void)
16224 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16225 struct neon_type_el et
16226 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16228 if (inst
.operands
[2].reg
== REG_PC
)
16229 as_tsktsk (MVE_BAD_PC
);
16230 else if (inst
.operands
[2].reg
== REG_SP
)
16231 as_tsktsk (MVE_BAD_SP
);
16233 if (inst
.cond
> COND_ALWAYS
)
16234 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16236 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16238 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16240 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16242 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16243 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16244 inst
.instruction
|= inst
.operands
[2].reg
;
16249 do_mve_vshll (void)
16251 struct neon_type_el et
16252 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16254 if (inst
.cond
> COND_ALWAYS
)
16255 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16257 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16259 int imm
= inst
.operands
[2].imm
;
16260 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16261 _("immediate value out of range"));
16263 if ((unsigned)imm
== et
.size
)
16265 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16266 inst
.instruction
|= 0x110001;
16270 inst
.instruction
|= (et
.size
+ imm
) << 16;
16271 inst
.instruction
|= 0x800140;
16274 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16276 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16277 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16278 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16283 do_mve_vshlc (void)
16285 if (inst
.cond
> COND_ALWAYS
)
16286 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16288 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16290 if (inst
.operands
[1].reg
== REG_PC
)
16291 as_tsktsk (MVE_BAD_PC
);
16292 else if (inst
.operands
[1].reg
== REG_SP
)
16293 as_tsktsk (MVE_BAD_SP
);
16295 int imm
= inst
.operands
[2].imm
;
16296 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16298 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16299 inst
.instruction
|= (imm
& 0x1f) << 16;
16300 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16301 inst
.instruction
|= inst
.operands
[1].reg
;
16306 do_mve_vshrn (void)
16309 switch (inst
.instruction
)
16311 case M_MNEM_vshrnt
:
16312 case M_MNEM_vshrnb
:
16313 case M_MNEM_vrshrnt
:
16314 case M_MNEM_vrshrnb
:
16315 types
= N_I16
| N_I32
;
16317 case M_MNEM_vqshrnt
:
16318 case M_MNEM_vqshrnb
:
16319 case M_MNEM_vqrshrnt
:
16320 case M_MNEM_vqrshrnb
:
16321 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16323 case M_MNEM_vqshrunt
:
16324 case M_MNEM_vqshrunb
:
16325 case M_MNEM_vqrshrunt
:
16326 case M_MNEM_vqrshrunb
:
16327 types
= N_S16
| N_S32
;
16333 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16335 if (inst
.cond
> COND_ALWAYS
)
16336 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16338 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16340 unsigned Qd
= inst
.operands
[0].reg
;
16341 unsigned Qm
= inst
.operands
[1].reg
;
16342 unsigned imm
= inst
.operands
[2].imm
;
16343 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16345 ? _("immediate operand expected in the range [1,8]")
16346 : _("immediate operand expected in the range [1,16]"));
16348 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16349 inst
.instruction
|= HI1 (Qd
) << 22;
16350 inst
.instruction
|= (et
.size
- imm
) << 16;
16351 inst
.instruction
|= LOW4 (Qd
) << 12;
16352 inst
.instruction
|= HI1 (Qm
) << 5;
16353 inst
.instruction
|= LOW4 (Qm
);
16358 do_mve_vqmovn (void)
16360 struct neon_type_el et
;
16361 if (inst
.instruction
== M_MNEM_vqmovnt
16362 || inst
.instruction
== M_MNEM_vqmovnb
)
16363 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16364 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16366 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16368 if (inst
.cond
> COND_ALWAYS
)
16369 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16371 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16373 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16374 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16375 inst
.instruction
|= (et
.size
== 32) << 18;
16376 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16377 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16378 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16383 do_mve_vpsel (void)
16385 neon_select_shape (NS_QQQ
, NS_NULL
);
16387 if (inst
.cond
> COND_ALWAYS
)
16388 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16390 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16393 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16395 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16396 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16397 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16402 do_mve_vpnot (void)
16404 if (inst
.cond
> COND_ALWAYS
)
16405 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16407 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16411 do_mve_vmaxnma_vminnma (void)
16413 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16414 struct neon_type_el et
16415 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16417 if (inst
.cond
> COND_ALWAYS
)
16418 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16420 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16422 inst
.instruction
|= (et
.size
== 16) << 28;
16423 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16424 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16425 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16426 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16431 do_mve_vcmul (void)
16433 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16434 struct neon_type_el et
16435 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16437 if (inst
.cond
> COND_ALWAYS
)
16438 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16440 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16442 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16443 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16444 _("immediate out of range"));
16446 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16447 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16448 as_tsktsk (BAD_MVE_SRCDEST
);
16450 inst
.instruction
|= (et
.size
== 32) << 28;
16451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16452 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16453 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16454 inst
.instruction
|= (rot
> 90) << 12;
16455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16456 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16457 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16458 inst
.instruction
|= (rot
== 90 || rot
== 270);
16462 /* To handle the Low Overhead Loop instructions
16463 in Armv8.1-M Mainline and MVE. */
16467 unsigned long insn
= inst
.instruction
;
16469 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16471 if (insn
== T_MNEM_lctp
)
16474 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16476 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16478 struct neon_type_el et
16479 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16480 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16487 constraint (!inst
.operands
[0].present
,
16489 /* fall through. */
16492 if (!inst
.operands
[0].present
)
16493 inst
.instruction
|= 1 << 21;
16495 v8_1_loop_reloc (TRUE
);
16500 v8_1_loop_reloc (FALSE
);
16501 /* fall through. */
16504 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16506 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16507 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16508 else if (inst
.operands
[1].reg
== REG_PC
)
16509 as_tsktsk (MVE_BAD_PC
);
16510 if (inst
.operands
[1].reg
== REG_SP
)
16511 as_tsktsk (MVE_BAD_SP
);
16513 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16523 do_vfp_nsyn_cmp (void)
16525 enum neon_shape rs
;
16526 if (!inst
.operands
[0].isreg
)
16533 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16534 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16538 if (inst
.operands
[1].isreg
)
16540 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16541 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16543 if (rs
== NS_FF
|| rs
== NS_HH
)
16545 NEON_ENCODE (SINGLE
, inst
);
16546 do_vfp_sp_monadic ();
16550 NEON_ENCODE (DOUBLE
, inst
);
16551 do_vfp_dp_rd_rm ();
16556 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16557 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16559 switch (inst
.instruction
& 0x0fffffff)
16562 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16565 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16571 if (rs
== NS_FI
|| rs
== NS_HI
)
16573 NEON_ENCODE (SINGLE
, inst
);
16574 do_vfp_sp_compare_z ();
16578 NEON_ENCODE (DOUBLE
, inst
);
16582 do_vfp_cond_or_thumb ();
16584 /* ARMv8.2 fp16 instruction. */
16585 if (rs
== NS_HI
|| rs
== NS_HH
)
16586 do_scalar_fp16_v82_encode ();
16590 nsyn_insert_sp (void)
16592 inst
.operands
[1] = inst
.operands
[0];
16593 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16594 inst
.operands
[0].reg
= REG_SP
;
16595 inst
.operands
[0].isreg
= 1;
16596 inst
.operands
[0].writeback
= 1;
16597 inst
.operands
[0].present
= 1;
16600 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16601 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16604 neon_dp_fixup (struct arm_it
* insn
)
16606 unsigned int i
= insn
->instruction
;
16611 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16622 insn
->instruction
= i
;
16626 mve_encode_qqr (int size
, int U
, int fp
)
16628 if (inst
.operands
[2].reg
== REG_SP
)
16629 as_tsktsk (MVE_BAD_SP
);
16630 else if (inst
.operands
[2].reg
== REG_PC
)
16631 as_tsktsk (MVE_BAD_PC
);
16636 if (((unsigned)inst
.instruction
) == 0xd00)
16637 inst
.instruction
= 0xee300f40;
16639 else if (((unsigned)inst
.instruction
) == 0x200d00)
16640 inst
.instruction
= 0xee301f40;
16642 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16643 inst
.instruction
= 0xee310e60;
16645 /* Setting size which is 1 for F16 and 0 for F32. */
16646 inst
.instruction
|= (size
== 16) << 28;
16651 if (((unsigned)inst
.instruction
) == 0x800)
16652 inst
.instruction
= 0xee010f40;
16654 else if (((unsigned)inst
.instruction
) == 0x1000800)
16655 inst
.instruction
= 0xee011f40;
16657 else if (((unsigned)inst
.instruction
) == 0)
16658 inst
.instruction
= 0xee000f40;
16660 else if (((unsigned)inst
.instruction
) == 0x200)
16661 inst
.instruction
= 0xee001f40;
16663 else if (((unsigned)inst
.instruction
) == 0x900)
16664 inst
.instruction
= 0xee010e40;
16666 else if (((unsigned)inst
.instruction
) == 0x910)
16667 inst
.instruction
= 0xee011e60;
16669 else if (((unsigned)inst
.instruction
) == 0x10)
16670 inst
.instruction
= 0xee000f60;
16672 else if (((unsigned)inst
.instruction
) == 0x210)
16673 inst
.instruction
= 0xee001f60;
16675 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16676 inst
.instruction
= 0xee000e40;
16678 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16679 inst
.instruction
= 0xee010e60;
16681 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16682 inst
.instruction
= 0xfe010e60;
16685 inst
.instruction
|= U
<< 28;
16687 /* Setting bits for size. */
16688 inst
.instruction
|= neon_logbits (size
) << 20;
16690 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16691 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16694 inst
.instruction
|= inst
.operands
[2].reg
;
16699 mve_encode_rqq (unsigned bit28
, unsigned size
)
16701 inst
.instruction
|= bit28
<< 28;
16702 inst
.instruction
|= neon_logbits (size
) << 20;
16703 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16704 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16705 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16706 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16707 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16712 mve_encode_qqq (int ubit
, int size
)
16715 inst
.instruction
|= (ubit
!= 0) << 28;
16716 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16717 inst
.instruction
|= neon_logbits (size
) << 20;
16718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16719 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16720 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16721 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16722 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16728 mve_encode_rq (unsigned bit28
, unsigned size
)
16730 inst
.instruction
|= bit28
<< 28;
16731 inst
.instruction
|= neon_logbits (size
) << 18;
16732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16733 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16738 mve_encode_rrqq (unsigned U
, unsigned size
)
16740 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16742 inst
.instruction
|= U
<< 28;
16743 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16744 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16745 inst
.instruction
|= (size
== 32) << 16;
16746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16747 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16748 inst
.instruction
|= inst
.operands
[3].reg
;
16752 /* Helper function for neon_three_same handling the operands. */
16754 neon_three_args (int isquad
)
16756 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16757 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16758 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16759 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16760 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16761 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16762 inst
.instruction
|= (isquad
!= 0) << 6;
16766 /* Encode insns with bit pattern:
16768 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16769 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16771 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16772 different meaning for some instruction. */
16775 neon_three_same (int isquad
, int ubit
, int size
)
16777 neon_three_args (isquad
);
16778 inst
.instruction
|= (ubit
!= 0) << 24;
16780 inst
.instruction
|= neon_logbits (size
) << 20;
16782 neon_dp_fixup (&inst
);
16785 /* Encode instructions of the form:
16787 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16788 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16790 Don't write size if SIZE == -1. */
16793 neon_two_same (int qbit
, int ubit
, int size
)
16795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16799 inst
.instruction
|= (qbit
!= 0) << 6;
16800 inst
.instruction
|= (ubit
!= 0) << 24;
16803 inst
.instruction
|= neon_logbits (size
) << 18;
16805 neon_dp_fixup (&inst
);
16808 enum vfp_or_neon_is_neon_bits
16811 NEON_CHECK_ARCH
= 2,
16812 NEON_CHECK_ARCH8
= 4
16815 /* Call this function if an instruction which may have belonged to the VFP or
16816 Neon instruction sets, but turned out to be a Neon instruction (due to the
16817 operand types involved, etc.). We have to check and/or fix-up a couple of
16820 - Make sure the user hasn't attempted to make a Neon instruction
16822 - Alter the value in the condition code field if necessary.
16823 - Make sure that the arch supports Neon instructions.
16825 Which of these operations take place depends on bits from enum
16826 vfp_or_neon_is_neon_bits.
16828 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16829 current instruction's condition is COND_ALWAYS, the condition field is
16830 changed to inst.uncond_value. This is necessary because instructions shared
16831 between VFP and Neon may be conditional for the VFP variants only, and the
16832 unconditional Neon version must have, e.g., 0xF in the condition field. */
16835 vfp_or_neon_is_neon (unsigned check
)
16837 /* Conditions are always legal in Thumb mode (IT blocks). */
16838 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16840 if (inst
.cond
!= COND_ALWAYS
)
16842 first_error (_(BAD_COND
));
16845 if (inst
.uncond_value
!= -1u)
16846 inst
.instruction
|= inst
.uncond_value
<< 28;
16850 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16851 || ((check
& NEON_CHECK_ARCH8
)
16852 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16854 first_error (_(BAD_FPU
));
16862 /* Return TRUE if the SIMD instruction is available for the current
16863 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16864 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16865 vfp_or_neon_is_neon for the NEON specific checks. */
16868 check_simd_pred_availability (int fp
, unsigned check
)
16870 if (inst
.cond
> COND_ALWAYS
)
16872 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16874 inst
.error
= BAD_FPU
;
16877 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16879 else if (inst
.cond
< COND_ALWAYS
)
16881 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16882 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16883 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16888 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16889 && vfp_or_neon_is_neon (check
) == FAIL
)
16892 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16893 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16898 /* Neon instruction encoders, in approximate order of appearance. */
16901 do_neon_dyadic_i_su (void)
16903 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16906 enum neon_shape rs
;
16907 struct neon_type_el et
;
16908 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16909 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16911 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16913 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16917 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16919 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16923 do_neon_dyadic_i64_su (void)
16925 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16927 enum neon_shape rs
;
16928 struct neon_type_el et
;
16929 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16931 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16932 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16936 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16937 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16940 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16942 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16946 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16949 unsigned size
= et
.size
>> 3;
16950 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16951 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16952 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16953 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16954 inst
.instruction
|= (isquad
!= 0) << 6;
16955 inst
.instruction
|= immbits
<< 16;
16956 inst
.instruction
|= (size
>> 3) << 7;
16957 inst
.instruction
|= (size
& 0x7) << 19;
16959 inst
.instruction
|= (uval
!= 0) << 24;
16961 neon_dp_fixup (&inst
);
16967 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16970 if (!inst
.operands
[2].isreg
)
16972 enum neon_shape rs
;
16973 struct neon_type_el et
;
16974 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16976 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16977 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16981 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16982 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16984 int imm
= inst
.operands
[2].imm
;
16986 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16987 _("immediate out of range for shift"));
16988 NEON_ENCODE (IMMED
, inst
);
16989 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16993 enum neon_shape rs
;
16994 struct neon_type_el et
;
16995 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16997 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16998 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17002 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17003 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17009 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17010 _("invalid instruction shape"));
17011 if (inst
.operands
[2].reg
== REG_SP
)
17012 as_tsktsk (MVE_BAD_SP
);
17013 else if (inst
.operands
[2].reg
== REG_PC
)
17014 as_tsktsk (MVE_BAD_PC
);
17016 inst
.instruction
= 0xee311e60;
17017 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17018 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17019 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17020 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17021 inst
.instruction
|= inst
.operands
[2].reg
;
17028 /* VSHL/VQSHL 3-register variants have syntax such as:
17030 whereas other 3-register operations encoded by neon_three_same have
17033 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17034 operands[2].reg here. */
17035 tmp
= inst
.operands
[2].reg
;
17036 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17037 inst
.operands
[1].reg
= tmp
;
17038 NEON_ENCODE (INTEGER
, inst
);
17039 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17045 do_neon_qshl (void)
17047 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17050 if (!inst
.operands
[2].isreg
)
17052 enum neon_shape rs
;
17053 struct neon_type_el et
;
17054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17056 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17057 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17061 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17062 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17064 int imm
= inst
.operands
[2].imm
;
17066 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17067 _("immediate out of range for shift"));
17068 NEON_ENCODE (IMMED
, inst
);
17069 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17073 enum neon_shape rs
;
17074 struct neon_type_el et
;
17076 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17078 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17079 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17083 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17084 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17089 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17090 _("invalid instruction shape"));
17091 if (inst
.operands
[2].reg
== REG_SP
)
17092 as_tsktsk (MVE_BAD_SP
);
17093 else if (inst
.operands
[2].reg
== REG_PC
)
17094 as_tsktsk (MVE_BAD_PC
);
17096 inst
.instruction
= 0xee311ee0;
17097 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17098 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17099 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17100 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17101 inst
.instruction
|= inst
.operands
[2].reg
;
17108 /* See note in do_neon_shl. */
17109 tmp
= inst
.operands
[2].reg
;
17110 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17111 inst
.operands
[1].reg
= tmp
;
17112 NEON_ENCODE (INTEGER
, inst
);
17113 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17119 do_neon_rshl (void)
17121 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17124 enum neon_shape rs
;
17125 struct neon_type_el et
;
17126 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17128 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17129 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17133 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17134 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17141 if (inst
.operands
[2].reg
== REG_PC
)
17142 as_tsktsk (MVE_BAD_PC
);
17143 else if (inst
.operands
[2].reg
== REG_SP
)
17144 as_tsktsk (MVE_BAD_SP
);
17146 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17147 _("invalid instruction shape"));
17149 if (inst
.instruction
== 0x0000510)
17150 /* We are dealing with vqrshl. */
17151 inst
.instruction
= 0xee331ee0;
17153 /* We are dealing with vrshl. */
17154 inst
.instruction
= 0xee331e60;
17156 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17157 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17158 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17159 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17160 inst
.instruction
|= inst
.operands
[2].reg
;
17165 tmp
= inst
.operands
[2].reg
;
17166 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17167 inst
.operands
[1].reg
= tmp
;
17168 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17173 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17175 /* Handle .I8 pseudo-instructions. */
17178 /* Unfortunately, this will make everything apart from zero out-of-range.
17179 FIXME is this the intended semantics? There doesn't seem much point in
17180 accepting .I8 if so. */
17181 immediate
|= immediate
<< 8;
17187 if (immediate
== (immediate
& 0x000000ff))
17189 *immbits
= immediate
;
17192 else if (immediate
== (immediate
& 0x0000ff00))
17194 *immbits
= immediate
>> 8;
17197 else if (immediate
== (immediate
& 0x00ff0000))
17199 *immbits
= immediate
>> 16;
17202 else if (immediate
== (immediate
& 0xff000000))
17204 *immbits
= immediate
>> 24;
17207 if ((immediate
& 0xffff) != (immediate
>> 16))
17208 goto bad_immediate
;
17209 immediate
&= 0xffff;
17212 if (immediate
== (immediate
& 0x000000ff))
17214 *immbits
= immediate
;
17217 else if (immediate
== (immediate
& 0x0000ff00))
17219 *immbits
= immediate
>> 8;
17224 first_error (_("immediate value out of range"));
17229 do_neon_logic (void)
17231 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17233 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17235 && !check_simd_pred_availability (FALSE
,
17236 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17238 else if (rs
!= NS_QQQ
17239 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17240 first_error (BAD_FPU
);
17242 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17243 /* U bit and size field were set as part of the bitmask. */
17244 NEON_ENCODE (INTEGER
, inst
);
17245 neon_three_same (neon_quad (rs
), 0, -1);
17249 const int three_ops_form
= (inst
.operands
[2].present
17250 && !inst
.operands
[2].isreg
);
17251 const int immoperand
= (three_ops_form
? 2 : 1);
17252 enum neon_shape rs
= (three_ops_form
17253 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17254 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17255 /* Because neon_select_shape makes the second operand a copy of the first
17256 if the second operand is not present. */
17258 && !check_simd_pred_availability (FALSE
,
17259 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17261 else if (rs
!= NS_QQI
17262 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17263 first_error (BAD_FPU
);
17265 struct neon_type_el et
;
17266 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17267 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17269 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17272 if (et
.type
== NT_invtype
)
17274 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17279 if (three_ops_form
)
17280 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17281 _("first and second operands shall be the same register"));
17283 NEON_ENCODE (IMMED
, inst
);
17285 immbits
= inst
.operands
[immoperand
].imm
;
17288 /* .i64 is a pseudo-op, so the immediate must be a repeating
17290 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17291 inst
.operands
[immoperand
].reg
: 0))
17293 /* Set immbits to an invalid constant. */
17294 immbits
= 0xdeadbeef;
17301 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17305 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17309 /* Pseudo-instruction for VBIC. */
17310 neon_invert_size (&immbits
, 0, et
.size
);
17311 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17315 /* Pseudo-instruction for VORR. */
17316 neon_invert_size (&immbits
, 0, et
.size
);
17317 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17327 inst
.instruction
|= neon_quad (rs
) << 6;
17328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17330 inst
.instruction
|= cmode
<< 8;
17331 neon_write_immbits (immbits
);
17333 neon_dp_fixup (&inst
);
17338 do_neon_bitfield (void)
17340 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17341 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17342 neon_three_same (neon_quad (rs
), 0, -1);
17346 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17349 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17350 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17352 if (et
.type
== NT_float
)
17354 NEON_ENCODE (FLOAT
, inst
);
17356 mve_encode_qqr (et
.size
, 0, 1);
17358 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17362 NEON_ENCODE (INTEGER
, inst
);
17364 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17366 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17372 do_neon_dyadic_if_su_d (void)
17374 /* This version only allow D registers, but that constraint is enforced during
17375 operand parsing so we don't need to do anything extra here. */
17376 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17380 do_neon_dyadic_if_i_d (void)
17382 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17383 affected if we specify unsigned args. */
17384 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17388 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17390 constraint (size
< 32, BAD_ADDR_MODE
);
17391 constraint (size
!= elsize
, BAD_EL_TYPE
);
17392 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17393 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17394 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17395 _("destination register and offset register may not be the"
17398 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17405 constraint ((imm
% (size
/ 8) != 0)
17406 || imm
> (0x7f << neon_logbits (size
)),
17407 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17408 " range of +/-[0,508]")
17409 : _("immediate must be a multiple of 8 in the"
17410 " range of +/-[0,1016]"));
17411 inst
.instruction
|= 0x11 << 24;
17412 inst
.instruction
|= add
<< 23;
17413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17414 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17415 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17416 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17417 inst
.instruction
|= 1 << 12;
17418 inst
.instruction
|= (size
== 64) << 8;
17419 inst
.instruction
&= 0xffffff00;
17420 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17421 inst
.instruction
|= imm
>> neon_logbits (size
);
17425 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17427 unsigned os
= inst
.operands
[1].imm
>> 5;
17428 unsigned type
= inst
.vectype
.el
[0].type
;
17429 constraint (os
!= 0 && size
== 8,
17430 _("can not shift offsets when accessing less than half-word"));
17431 constraint (os
&& os
!= neon_logbits (size
),
17432 _("shift immediate must be 1, 2 or 3 for half-word, word"
17433 " or double-word accesses respectively"));
17434 if (inst
.operands
[1].reg
== REG_PC
)
17435 as_tsktsk (MVE_BAD_PC
);
17440 constraint (elsize
>= 64, BAD_EL_TYPE
);
17443 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17447 constraint (elsize
!= size
, BAD_EL_TYPE
);
17452 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17456 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17457 _("destination register and offset register may not be"
17459 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17460 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17462 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17466 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17469 inst
.instruction
|= 1 << 23;
17470 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17471 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17472 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17473 inst
.instruction
|= neon_logbits (elsize
) << 7;
17474 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17475 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17476 inst
.instruction
|= !!os
;
17480 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17482 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17484 constraint (size
>= 64, BAD_ADDR_MODE
);
17488 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17491 constraint (elsize
!= size
, BAD_EL_TYPE
);
17498 constraint (elsize
!= size
&& type
!= NT_unsigned
17499 && type
!= NT_signed
, BAD_EL_TYPE
);
17503 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17506 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17514 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17519 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17522 constraint (1, _("immediate must be a multiple of 2 in the"
17523 " range of +/-[0,254]"));
17526 constraint (1, _("immediate must be a multiple of 4 in the"
17527 " range of +/-[0,508]"));
17532 if (size
!= elsize
)
17534 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17535 constraint (inst
.operands
[0].reg
> 14,
17536 _("MVE vector register in the range [Q0..Q7] expected"));
17537 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17538 inst
.instruction
|= (size
== 16) << 19;
17539 inst
.instruction
|= neon_logbits (elsize
) << 7;
17543 if (inst
.operands
[1].reg
== REG_PC
)
17544 as_tsktsk (MVE_BAD_PC
);
17545 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17546 as_tsktsk (MVE_BAD_SP
);
17547 inst
.instruction
|= 1 << 12;
17548 inst
.instruction
|= neon_logbits (size
) << 7;
17550 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17551 inst
.instruction
|= add
<< 23;
17552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17553 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17554 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17555 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17556 inst
.instruction
&= 0xffffff80;
17557 inst
.instruction
|= imm
>> neon_logbits (size
);
17562 do_mve_vstr_vldr (void)
17567 if (inst
.cond
> COND_ALWAYS
)
17568 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17570 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17572 switch (inst
.instruction
)
17579 /* fall through. */
17585 /* fall through. */
17591 /* fall through. */
17597 /* fall through. */
17602 unsigned elsize
= inst
.vectype
.el
[0].size
;
17604 if (inst
.operands
[1].isquad
)
17606 /* We are dealing with [Q, imm]{!} cases. */
17607 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17611 if (inst
.operands
[1].immisreg
== 2)
17613 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17614 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17616 else if (!inst
.operands
[1].immisreg
)
17618 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17619 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17622 constraint (1, BAD_ADDR_MODE
);
17629 do_mve_vst_vld (void)
17631 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17634 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17635 || inst
.relocs
[0].exp
.X_add_number
!= 0
17636 || inst
.operands
[1].immisreg
!= 0,
17638 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17639 if (inst
.operands
[1].reg
== REG_PC
)
17640 as_tsktsk (MVE_BAD_PC
);
17641 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17642 as_tsktsk (MVE_BAD_SP
);
17645 /* These instructions are one of the "exceptions" mentioned in
17646 handle_pred_state. They are MVE instructions that are not VPT compatible
17647 and do not accept a VPT code, thus appending such a code is a syntax
17649 if (inst
.cond
> COND_ALWAYS
)
17650 first_error (BAD_SYNTAX
);
17651 /* If we append a scalar condition code we can set this to
17652 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17653 else if (inst
.cond
< COND_ALWAYS
)
17654 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17656 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17658 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17659 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17660 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17661 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17662 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17667 do_mve_vaddlv (void)
17669 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17670 struct neon_type_el et
17671 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17673 if (et
.type
== NT_invtype
)
17674 first_error (BAD_EL_TYPE
);
17676 if (inst
.cond
> COND_ALWAYS
)
17677 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17679 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17681 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17683 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17684 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17686 inst
.instruction
|= inst
.operands
[2].reg
;
17691 do_neon_dyadic_if_su (void)
17693 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17694 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17697 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17698 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17699 && et
.type
== NT_float
17700 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17702 if (!check_simd_pred_availability (et
.type
== NT_float
,
17703 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17706 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17710 do_neon_addsub_if_i (void)
17712 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17713 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17716 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17717 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17718 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17720 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17721 /* If we are parsing Q registers and the element types match MVE, which NEON
17722 also supports, then we must check whether this is an instruction that can
17723 be used by both MVE/NEON. This distinction can be made based on whether
17724 they are predicated or not. */
17725 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17727 if (!check_simd_pred_availability (et
.type
== NT_float
,
17728 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17733 /* If they are either in a D register or are using an unsupported. */
17735 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17739 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17740 affected if we specify unsigned args. */
17741 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17744 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17746 V<op> A,B (A is operand 0, B is operand 2)
17751 so handle that case specially. */
17754 neon_exchange_operands (void)
17756 if (inst
.operands
[1].present
)
17758 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17760 /* Swap operands[1] and operands[2]. */
17761 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17762 inst
.operands
[1] = inst
.operands
[2];
17763 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17768 inst
.operands
[1] = inst
.operands
[2];
17769 inst
.operands
[2] = inst
.operands
[0];
17774 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17776 if (inst
.operands
[2].isreg
)
17779 neon_exchange_operands ();
17780 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17784 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17785 struct neon_type_el et
= neon_check_type (2, rs
,
17786 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17788 NEON_ENCODE (IMMED
, inst
);
17789 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17790 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17791 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17792 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17793 inst
.instruction
|= neon_quad (rs
) << 6;
17794 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17795 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17797 neon_dp_fixup (&inst
);
17804 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17808 do_neon_cmp_inv (void)
17810 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17816 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17819 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17820 scalars, which are encoded in 5 bits, M : Rm.
17821 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17822 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17825 Dot Product instructions are similar to multiply instructions except elsize
17826 should always be 32.
17828 This function translates SCALAR, which is GAS's internal encoding of indexed
17829 scalar register, to raw encoding. There is also register and index range
17830 check based on ELSIZE. */
17833 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17835 unsigned regno
= NEON_SCALAR_REG (scalar
);
17836 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17841 if (regno
> 7 || elno
> 3)
17843 return regno
| (elno
<< 3);
17846 if (regno
> 15 || elno
> 1)
17848 return regno
| (elno
<< 4);
17852 first_error (_("scalar out of range for multiply instruction"));
17858 /* Encode multiply / multiply-accumulate scalar instructions. */
17861 neon_mul_mac (struct neon_type_el et
, int ubit
)
17865 /* Give a more helpful error message if we have an invalid type. */
17866 if (et
.type
== NT_invtype
)
17869 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17870 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17871 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17872 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17873 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17874 inst
.instruction
|= LOW4 (scalar
);
17875 inst
.instruction
|= HI1 (scalar
) << 5;
17876 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17877 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17878 inst
.instruction
|= (ubit
!= 0) << 24;
17880 neon_dp_fixup (&inst
);
17884 do_neon_mac_maybe_scalar (void)
17886 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17889 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17892 if (inst
.operands
[2].isscalar
)
17894 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17895 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17896 struct neon_type_el et
= neon_check_type (3, rs
,
17897 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17898 NEON_ENCODE (SCALAR
, inst
);
17899 neon_mul_mac (et
, neon_quad (rs
));
17901 else if (!inst
.operands
[2].isvec
)
17903 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17905 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17906 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17908 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17912 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17913 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17914 affected if we specify unsigned args. */
17915 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17920 do_bfloat_vfma (void)
17922 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17923 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17924 enum neon_shape rs
;
17927 if (inst
.instruction
!= B_MNEM_vfmab
)
17930 inst
.instruction
= B_MNEM_vfmat
;
17933 if (inst
.operands
[2].isscalar
)
17935 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17936 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17938 inst
.instruction
|= (1 << 25);
17939 int index
= inst
.operands
[2].reg
& 0xf;
17940 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17941 inst
.operands
[2].reg
>>= 4;
17942 constraint (!(inst
.operands
[2].reg
< 8),
17943 _("indexed register must be less than 8"));
17944 neon_three_args (t_bit
);
17945 inst
.instruction
|= ((index
& 1) << 3);
17946 inst
.instruction
|= ((index
& 2) << 4);
17950 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17951 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17952 neon_three_args (t_bit
);
17958 do_neon_fmac (void)
17960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17961 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17964 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17967 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17969 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17970 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17976 if (inst
.operands
[2].reg
== REG_SP
)
17977 as_tsktsk (MVE_BAD_SP
);
17978 else if (inst
.operands
[2].reg
== REG_PC
)
17979 as_tsktsk (MVE_BAD_PC
);
17981 inst
.instruction
= 0xee310e40;
17982 inst
.instruction
|= (et
.size
== 16) << 28;
17983 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17984 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17985 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17986 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17987 inst
.instruction
|= inst
.operands
[2].reg
;
17994 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17997 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
18003 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
18004 inst
.cond
== COND_ALWAYS
)
18006 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18007 inst
.instruction
= N_MNEM_vfma
;
18008 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18010 return do_neon_fmac();
18021 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18022 struct neon_type_el et
= neon_check_type (3, rs
,
18023 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18024 neon_three_same (neon_quad (rs
), 0, et
.size
);
18027 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18028 same types as the MAC equivalents. The polynomial type for this instruction
18029 is encoded the same as the integer type. */
18034 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18037 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18040 if (inst
.operands
[2].isscalar
)
18042 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18043 do_neon_mac_maybe_scalar ();
18047 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18049 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18050 struct neon_type_el et
18051 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18052 if (et
.type
== NT_float
)
18053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18056 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18060 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18061 neon_dyadic_misc (NT_poly
,
18062 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18068 do_neon_qdmulh (void)
18070 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18073 if (inst
.operands
[2].isscalar
)
18075 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18076 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18077 struct neon_type_el et
= neon_check_type (3, rs
,
18078 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18079 NEON_ENCODE (SCALAR
, inst
);
18080 neon_mul_mac (et
, neon_quad (rs
));
18084 enum neon_shape rs
;
18085 struct neon_type_el et
;
18086 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18088 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18089 et
= neon_check_type (3, rs
,
18090 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18094 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18095 et
= neon_check_type (3, rs
,
18096 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18099 NEON_ENCODE (INTEGER
, inst
);
18101 mve_encode_qqr (et
.size
, 0, 0);
18103 /* The U bit (rounding) comes from bit mask. */
18104 neon_three_same (neon_quad (rs
), 0, et
.size
);
18109 do_mve_vaddv (void)
18111 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18112 struct neon_type_el et
18113 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18115 if (et
.type
== NT_invtype
)
18116 first_error (BAD_EL_TYPE
);
18118 if (inst
.cond
> COND_ALWAYS
)
18119 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18121 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18123 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18125 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18129 do_mve_vhcadd (void)
18131 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18132 struct neon_type_el et
18133 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18135 if (inst
.cond
> COND_ALWAYS
)
18136 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18138 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18140 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18141 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18143 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18144 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18145 "operand makes instruction UNPREDICTABLE"));
18147 mve_encode_qqq (0, et
.size
);
18148 inst
.instruction
|= (rot
== 270) << 12;
18153 do_mve_vqdmull (void)
18155 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18156 struct neon_type_el et
18157 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18160 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18161 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18162 as_tsktsk (BAD_MVE_SRCDEST
);
18164 if (inst
.cond
> COND_ALWAYS
)
18165 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18167 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18171 mve_encode_qqq (et
.size
== 32, 64);
18172 inst
.instruction
|= 1;
18176 mve_encode_qqr (64, et
.size
== 32, 0);
18177 inst
.instruction
|= 0x3 << 5;
18184 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18185 struct neon_type_el et
18186 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18188 if (et
.type
== NT_invtype
)
18189 first_error (BAD_EL_TYPE
);
18191 if (inst
.cond
> COND_ALWAYS
)
18192 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18194 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18196 mve_encode_qqq (0, 64);
18200 do_mve_vbrsr (void)
18202 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18203 struct neon_type_el et
18204 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18206 if (inst
.cond
> COND_ALWAYS
)
18207 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18209 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18211 mve_encode_qqr (et
.size
, 0, 0);
18217 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18219 if (inst
.cond
> COND_ALWAYS
)
18220 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18222 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18224 mve_encode_qqq (1, 64);
18228 do_mve_vmulh (void)
18230 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18231 struct neon_type_el et
18232 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18234 if (inst
.cond
> COND_ALWAYS
)
18235 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18237 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18239 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18243 do_mve_vqdmlah (void)
18245 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18246 struct neon_type_el et
18247 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18249 if (inst
.cond
> COND_ALWAYS
)
18250 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18252 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18254 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18258 do_mve_vqdmladh (void)
18260 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18261 struct neon_type_el et
18262 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18264 if (inst
.cond
> COND_ALWAYS
)
18265 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18267 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18269 mve_encode_qqq (0, et
.size
);
18274 do_mve_vmull (void)
18277 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18278 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18279 if (inst
.cond
== COND_ALWAYS
18280 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18285 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18292 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18293 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18294 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18296 /* We are dealing with MVE's vmullt. */
18298 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18299 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18300 as_tsktsk (BAD_MVE_SRCDEST
);
18302 if (inst
.cond
> COND_ALWAYS
)
18303 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18305 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18307 if (et
.type
== NT_poly
)
18308 mve_encode_qqq (neon_logbits (et
.size
), 64);
18310 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18315 inst
.instruction
= N_MNEM_vmul
;
18318 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18323 do_mve_vabav (void)
18325 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18330 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18333 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18334 | N_S16
| N_S32
| N_U8
| N_U16
18337 if (inst
.cond
> COND_ALWAYS
)
18338 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18340 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18342 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18346 do_mve_vmladav (void)
18348 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18349 struct neon_type_el et
= neon_check_type (3, rs
,
18350 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18352 if (et
.type
== NT_unsigned
18353 && (inst
.instruction
== M_MNEM_vmladavx
18354 || inst
.instruction
== M_MNEM_vmladavax
18355 || inst
.instruction
== M_MNEM_vmlsdav
18356 || inst
.instruction
== M_MNEM_vmlsdava
18357 || inst
.instruction
== M_MNEM_vmlsdavx
18358 || inst
.instruction
== M_MNEM_vmlsdavax
))
18359 first_error (BAD_SIMD_TYPE
);
18361 constraint (inst
.operands
[2].reg
> 14,
18362 _("MVE vector register in the range [Q0..Q7] expected"));
18364 if (inst
.cond
> COND_ALWAYS
)
18365 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18367 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18369 if (inst
.instruction
== M_MNEM_vmlsdav
18370 || inst
.instruction
== M_MNEM_vmlsdava
18371 || inst
.instruction
== M_MNEM_vmlsdavx
18372 || inst
.instruction
== M_MNEM_vmlsdavax
)
18373 inst
.instruction
|= (et
.size
== 8) << 28;
18375 inst
.instruction
|= (et
.size
== 8) << 8;
18377 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18378 inst
.instruction
|= (et
.size
== 32) << 16;
18382 do_mve_vmlaldav (void)
18384 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18385 struct neon_type_el et
18386 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18387 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18389 if (et
.type
== NT_unsigned
18390 && (inst
.instruction
== M_MNEM_vmlsldav
18391 || inst
.instruction
== M_MNEM_vmlsldava
18392 || inst
.instruction
== M_MNEM_vmlsldavx
18393 || inst
.instruction
== M_MNEM_vmlsldavax
))
18394 first_error (BAD_SIMD_TYPE
);
18396 if (inst
.cond
> COND_ALWAYS
)
18397 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18399 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18401 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18405 do_mve_vrmlaldavh (void)
18407 struct neon_type_el et
;
18408 if (inst
.instruction
== M_MNEM_vrmlsldavh
18409 || inst
.instruction
== M_MNEM_vrmlsldavha
18410 || inst
.instruction
== M_MNEM_vrmlsldavhx
18411 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18413 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18414 if (inst
.operands
[1].reg
== REG_SP
)
18415 as_tsktsk (MVE_BAD_SP
);
18419 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18420 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18421 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18423 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18424 N_U32
| N_S32
| N_KEY
);
18425 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18426 with vmax/min instructions, making the use of SP in assembly really
18427 nonsensical, so instead of issuing a warning like we do for other uses
18428 of SP for the odd register operand we error out. */
18429 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18432 /* Make sure we still check the second operand is an odd one and that PC is
18433 disallowed. This because we are parsing for any GPR operand, to be able
18434 to distinguish between giving a warning or an error for SP as described
18436 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18437 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18439 if (inst
.cond
> COND_ALWAYS
)
18440 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18442 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18444 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18449 do_mve_vmaxnmv (void)
18451 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18452 struct neon_type_el et
18453 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18455 if (inst
.cond
> COND_ALWAYS
)
18456 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18458 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18460 if (inst
.operands
[0].reg
== REG_SP
)
18461 as_tsktsk (MVE_BAD_SP
);
18462 else if (inst
.operands
[0].reg
== REG_PC
)
18463 as_tsktsk (MVE_BAD_PC
);
18465 mve_encode_rq (et
.size
== 16, 64);
18469 do_mve_vmaxv (void)
18471 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18472 struct neon_type_el et
;
18474 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18475 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18477 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18479 if (inst
.cond
> COND_ALWAYS
)
18480 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18482 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18484 if (inst
.operands
[0].reg
== REG_SP
)
18485 as_tsktsk (MVE_BAD_SP
);
18486 else if (inst
.operands
[0].reg
== REG_PC
)
18487 as_tsktsk (MVE_BAD_PC
);
18489 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18494 do_neon_qrdmlah (void)
18496 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18498 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18500 /* Check we're on the correct architecture. */
18501 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18503 = _("instruction form not available on this architecture.");
18504 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18506 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18507 record_feature_use (&fpu_neon_ext_v8_1
);
18509 if (inst
.operands
[2].isscalar
)
18511 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18512 struct neon_type_el et
= neon_check_type (3, rs
,
18513 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18514 NEON_ENCODE (SCALAR
, inst
);
18515 neon_mul_mac (et
, neon_quad (rs
));
18519 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18520 struct neon_type_el et
= neon_check_type (3, rs
,
18521 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18522 NEON_ENCODE (INTEGER
, inst
);
18523 /* The U bit (rounding) comes from bit mask. */
18524 neon_three_same (neon_quad (rs
), 0, et
.size
);
18529 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18530 struct neon_type_el et
18531 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18533 NEON_ENCODE (INTEGER
, inst
);
18534 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18539 do_neon_fcmp_absolute (void)
18541 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18542 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18543 N_F_16_32
| N_KEY
);
18544 /* Size field comes from bit mask. */
18545 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18549 do_neon_fcmp_absolute_inv (void)
18551 neon_exchange_operands ();
18552 do_neon_fcmp_absolute ();
18556 do_neon_step (void)
18558 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18559 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18560 N_F_16_32
| N_KEY
);
18561 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18565 do_neon_abs_neg (void)
18567 enum neon_shape rs
;
18568 struct neon_type_el et
;
18570 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18573 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18574 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18576 if (!check_simd_pred_availability (et
.type
== NT_float
,
18577 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18584 inst
.instruction
|= neon_quad (rs
) << 6;
18585 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18586 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18588 neon_dp_fixup (&inst
);
18594 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18597 enum neon_shape rs
;
18598 struct neon_type_el et
;
18599 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18601 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18602 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18606 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18607 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18611 int imm
= inst
.operands
[2].imm
;
18612 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18613 _("immediate out of range for insert"));
18614 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18620 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18623 enum neon_shape rs
;
18624 struct neon_type_el et
;
18625 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18627 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18628 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18632 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18633 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18636 int imm
= inst
.operands
[2].imm
;
18637 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18638 _("immediate out of range for insert"));
18639 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18643 do_neon_qshlu_imm (void)
18645 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18648 enum neon_shape rs
;
18649 struct neon_type_el et
;
18650 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18652 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18653 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18657 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18658 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18659 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18662 int imm
= inst
.operands
[2].imm
;
18663 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18664 _("immediate out of range for shift"));
18665 /* Only encodes the 'U present' variant of the instruction.
18666 In this case, signed types have OP (bit 8) set to 0.
18667 Unsigned types have OP set to 1. */
18668 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18669 /* The rest of the bits are the same as other immediate shifts. */
18670 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18674 do_neon_qmovn (void)
18676 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18677 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18678 /* Saturating move where operands can be signed or unsigned, and the
18679 destination has the same signedness. */
18680 NEON_ENCODE (INTEGER
, inst
);
18681 if (et
.type
== NT_unsigned
)
18682 inst
.instruction
|= 0xc0;
18684 inst
.instruction
|= 0x80;
18685 neon_two_same (0, 1, et
.size
/ 2);
18689 do_neon_qmovun (void)
18691 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18692 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18693 /* Saturating move with unsigned results. Operands must be signed. */
18694 NEON_ENCODE (INTEGER
, inst
);
18695 neon_two_same (0, 1, et
.size
/ 2);
18699 do_neon_rshift_sat_narrow (void)
18701 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18702 or unsigned. If operands are unsigned, results must also be unsigned. */
18703 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18704 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18705 int imm
= inst
.operands
[2].imm
;
18706 /* This gets the bounds check, size encoding and immediate bits calculation
18710 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18711 VQMOVN.I<size> <Dd>, <Qm>. */
18714 inst
.operands
[2].present
= 0;
18715 inst
.instruction
= N_MNEM_vqmovn
;
18720 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18721 _("immediate out of range"));
18722 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18726 do_neon_rshift_sat_narrow_u (void)
18728 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18729 or unsigned. If operands are unsigned, results must also be unsigned. */
18730 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18731 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18732 int imm
= inst
.operands
[2].imm
;
18733 /* This gets the bounds check, size encoding and immediate bits calculation
18737 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18738 VQMOVUN.I<size> <Dd>, <Qm>. */
18741 inst
.operands
[2].present
= 0;
18742 inst
.instruction
= N_MNEM_vqmovun
;
18747 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18748 _("immediate out of range"));
18749 /* FIXME: The manual is kind of unclear about what value U should have in
18750 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18752 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18756 do_neon_movn (void)
18758 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18759 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18760 NEON_ENCODE (INTEGER
, inst
);
18761 neon_two_same (0, 1, et
.size
/ 2);
18765 do_neon_rshift_narrow (void)
18767 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18768 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18769 int imm
= inst
.operands
[2].imm
;
18770 /* This gets the bounds check, size encoding and immediate bits calculation
18774 /* If immediate is zero then we are a pseudo-instruction for
18775 VMOVN.I<size> <Dd>, <Qm> */
18778 inst
.operands
[2].present
= 0;
18779 inst
.instruction
= N_MNEM_vmovn
;
18784 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18785 _("immediate out of range for narrowing operation"));
18786 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18790 do_neon_shll (void)
18792 /* FIXME: Type checking when lengthening. */
18793 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18794 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18795 unsigned imm
= inst
.operands
[2].imm
;
18797 if (imm
== et
.size
)
18799 /* Maximum shift variant. */
18800 NEON_ENCODE (INTEGER
, inst
);
18801 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18802 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18803 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18804 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18805 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18807 neon_dp_fixup (&inst
);
18811 /* A more-specific type check for non-max versions. */
18812 et
= neon_check_type (2, NS_QDI
,
18813 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18814 NEON_ENCODE (IMMED
, inst
);
18815 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18819 /* Check the various types for the VCVT instruction, and return which version
18820 the current instruction is. */
18822 #define CVT_FLAVOUR_VAR \
18823 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18824 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18825 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18826 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18827 /* Half-precision conversions. */ \
18828 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18829 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18830 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18831 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18832 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18833 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18834 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18835 Compared with single/double precision variants, only the co-processor \
18836 field is different, so the encoding flow is reused here. */ \
18837 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18838 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18839 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18840 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18841 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18842 /* VFP instructions. */ \
18843 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18844 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18845 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18846 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18847 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18848 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18849 /* VFP instructions with bitshift. */ \
18850 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18851 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18852 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18853 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18854 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18855 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18856 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18857 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18859 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18860 neon_cvt_flavour_##C,
18862 /* The different types of conversions we can do. */
18863 enum neon_cvt_flavour
18866 neon_cvt_flavour_invalid
,
18867 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18872 static enum neon_cvt_flavour
18873 get_neon_cvt_flavour (enum neon_shape rs
)
18875 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18876 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18877 if (et.type != NT_invtype) \
18879 inst.error = NULL; \
18880 return (neon_cvt_flavour_##C); \
18883 struct neon_type_el et
;
18884 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18885 || rs
== NS_FF
) ? N_VFP
: 0;
18886 /* The instruction versions which take an immediate take one register
18887 argument, which is extended to the width of the full register. Thus the
18888 "source" and "destination" registers must have the same width. Hack that
18889 here by making the size equal to the key (wider, in this case) operand. */
18890 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18894 return neon_cvt_flavour_invalid
;
18909 /* Neon-syntax VFP conversions. */
18912 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18914 const char *opname
= 0;
18916 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18917 || rs
== NS_FHI
|| rs
== NS_HFI
)
18919 /* Conversions with immediate bitshift. */
18920 const char *enc
[] =
18922 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18928 if (flavour
< (int) ARRAY_SIZE (enc
))
18930 opname
= enc
[flavour
];
18931 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18932 _("operands 0 and 1 must be the same register"));
18933 inst
.operands
[1] = inst
.operands
[2];
18934 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18939 /* Conversions without bitshift. */
18940 const char *enc
[] =
18942 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18948 if (flavour
< (int) ARRAY_SIZE (enc
))
18949 opname
= enc
[flavour
];
18953 do_vfp_nsyn_opcode (opname
);
18955 /* ARMv8.2 fp16 VCVT instruction. */
18956 if (flavour
== neon_cvt_flavour_s32_f16
18957 || flavour
== neon_cvt_flavour_u32_f16
18958 || flavour
== neon_cvt_flavour_f16_u32
18959 || flavour
== neon_cvt_flavour_f16_s32
)
18960 do_scalar_fp16_v82_encode ();
18964 do_vfp_nsyn_cvtz (void)
18966 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18967 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18968 const char *enc
[] =
18970 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18976 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18977 do_vfp_nsyn_opcode (enc
[flavour
]);
18981 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18982 enum neon_cvt_mode mode
)
18987 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18988 D register operands. */
18989 if (flavour
== neon_cvt_flavour_s32_f64
18990 || flavour
== neon_cvt_flavour_u32_f64
)
18991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18994 if (flavour
== neon_cvt_flavour_s32_f16
18995 || flavour
== neon_cvt_flavour_u32_f16
)
18996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18999 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19003 case neon_cvt_flavour_s32_f64
:
19007 case neon_cvt_flavour_s32_f32
:
19011 case neon_cvt_flavour_s32_f16
:
19015 case neon_cvt_flavour_u32_f64
:
19019 case neon_cvt_flavour_u32_f32
:
19023 case neon_cvt_flavour_u32_f16
:
19028 first_error (_("invalid instruction shape"));
19034 case neon_cvt_mode_a
: rm
= 0; break;
19035 case neon_cvt_mode_n
: rm
= 1; break;
19036 case neon_cvt_mode_p
: rm
= 2; break;
19037 case neon_cvt_mode_m
: rm
= 3; break;
19038 default: first_error (_("invalid rounding mode")); return;
19041 NEON_ENCODE (FPV8
, inst
);
19042 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19043 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19044 inst
.instruction
|= sz
<< 8;
19046 /* ARMv8.2 fp16 VCVT instruction. */
19047 if (flavour
== neon_cvt_flavour_s32_f16
19048 ||flavour
== neon_cvt_flavour_u32_f16
)
19049 do_scalar_fp16_v82_encode ();
19050 inst
.instruction
|= op
<< 7;
19051 inst
.instruction
|= rm
<< 16;
19052 inst
.instruction
|= 0xf0000000;
19053 inst
.is_neon
= TRUE
;
19057 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19059 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19060 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19061 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19063 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19065 if (flavour
== neon_cvt_flavour_invalid
)
19068 /* PR11109: Handle round-to-zero for VCVT conversions. */
19069 if (mode
== neon_cvt_mode_z
19070 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19071 && (flavour
== neon_cvt_flavour_s16_f16
19072 || flavour
== neon_cvt_flavour_u16_f16
19073 || flavour
== neon_cvt_flavour_s32_f32
19074 || flavour
== neon_cvt_flavour_u32_f32
19075 || flavour
== neon_cvt_flavour_s32_f64
19076 || flavour
== neon_cvt_flavour_u32_f64
)
19077 && (rs
== NS_FD
|| rs
== NS_FF
))
19079 do_vfp_nsyn_cvtz ();
19083 /* ARMv8.2 fp16 VCVT conversions. */
19084 if (mode
== neon_cvt_mode_z
19085 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19086 && (flavour
== neon_cvt_flavour_s32_f16
19087 || flavour
== neon_cvt_flavour_u32_f16
)
19090 do_vfp_nsyn_cvtz ();
19091 do_scalar_fp16_v82_encode ();
19095 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19096 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19098 /* We are dealing with vcvt with the 'ne' condition. */
19100 inst
.instruction
= N_MNEM_vcvt
;
19101 do_neon_cvt_1 (neon_cvt_mode_z
);
19105 /* VFP rather than Neon conversions. */
19106 if (flavour
>= neon_cvt_flavour_first_fp
)
19108 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19109 do_vfp_nsyn_cvt (rs
, flavour
);
19111 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19119 if (mode
== neon_cvt_mode_z
19120 && (flavour
== neon_cvt_flavour_f16_s16
19121 || flavour
== neon_cvt_flavour_f16_u16
19122 || flavour
== neon_cvt_flavour_s16_f16
19123 || flavour
== neon_cvt_flavour_u16_f16
19124 || flavour
== neon_cvt_flavour_f32_u32
19125 || flavour
== neon_cvt_flavour_f32_s32
19126 || flavour
== neon_cvt_flavour_s32_f32
19127 || flavour
== neon_cvt_flavour_u32_f32
))
19129 if (!check_simd_pred_availability (TRUE
,
19130 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19133 /* fall through. */
19137 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19138 0x0000100, 0x1000100, 0x0, 0x1000000};
19140 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19141 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19144 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19146 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19147 _("immediate value out of range"));
19150 case neon_cvt_flavour_f16_s16
:
19151 case neon_cvt_flavour_f16_u16
:
19152 case neon_cvt_flavour_s16_f16
:
19153 case neon_cvt_flavour_u16_f16
:
19154 constraint (inst
.operands
[2].imm
> 16,
19155 _("immediate value out of range"));
19157 case neon_cvt_flavour_f32_u32
:
19158 case neon_cvt_flavour_f32_s32
:
19159 case neon_cvt_flavour_s32_f32
:
19160 case neon_cvt_flavour_u32_f32
:
19161 constraint (inst
.operands
[2].imm
> 32,
19162 _("immediate value out of range"));
19165 inst
.error
= BAD_FPU
;
19170 /* Fixed-point conversion with #0 immediate is encoded as an
19171 integer conversion. */
19172 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19174 NEON_ENCODE (IMMED
, inst
);
19175 if (flavour
!= neon_cvt_flavour_invalid
)
19176 inst
.instruction
|= enctab
[flavour
];
19177 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19178 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19179 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19180 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19181 inst
.instruction
|= neon_quad (rs
) << 6;
19182 inst
.instruction
|= 1 << 21;
19183 if (flavour
< neon_cvt_flavour_s16_f16
)
19185 inst
.instruction
|= 1 << 21;
19186 immbits
= 32 - inst
.operands
[2].imm
;
19187 inst
.instruction
|= immbits
<< 16;
19191 inst
.instruction
|= 3 << 20;
19192 immbits
= 16 - inst
.operands
[2].imm
;
19193 inst
.instruction
|= immbits
<< 16;
19194 inst
.instruction
&= ~(1 << 9);
19197 neon_dp_fixup (&inst
);
19202 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19203 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19204 && (flavour
== neon_cvt_flavour_s16_f16
19205 || flavour
== neon_cvt_flavour_u16_f16
19206 || flavour
== neon_cvt_flavour_s32_f32
19207 || flavour
== neon_cvt_flavour_u32_f32
))
19209 if (!check_simd_pred_availability (TRUE
,
19210 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19213 else if (mode
== neon_cvt_mode_z
19214 && (flavour
== neon_cvt_flavour_f16_s16
19215 || flavour
== neon_cvt_flavour_f16_u16
19216 || flavour
== neon_cvt_flavour_s16_f16
19217 || flavour
== neon_cvt_flavour_u16_f16
19218 || flavour
== neon_cvt_flavour_f32_u32
19219 || flavour
== neon_cvt_flavour_f32_s32
19220 || flavour
== neon_cvt_flavour_s32_f32
19221 || flavour
== neon_cvt_flavour_u32_f32
))
19223 if (!check_simd_pred_availability (TRUE
,
19224 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19227 /* fall through. */
19229 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19232 NEON_ENCODE (FLOAT
, inst
);
19233 if (!check_simd_pred_availability (TRUE
,
19234 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19238 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19239 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19241 inst
.instruction
|= neon_quad (rs
) << 6;
19242 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19243 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19244 inst
.instruction
|= mode
<< 8;
19245 if (flavour
== neon_cvt_flavour_u16_f16
19246 || flavour
== neon_cvt_flavour_s16_f16
)
19247 /* Mask off the original size bits and reencode them. */
19248 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19251 inst
.instruction
|= 0xfc000000;
19253 inst
.instruction
|= 0xf0000000;
19259 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19260 0x100, 0x180, 0x0, 0x080};
19262 NEON_ENCODE (INTEGER
, inst
);
19264 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19266 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19270 if (flavour
!= neon_cvt_flavour_invalid
)
19271 inst
.instruction
|= enctab
[flavour
];
19273 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19274 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19275 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19276 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19277 inst
.instruction
|= neon_quad (rs
) << 6;
19278 if (flavour
>= neon_cvt_flavour_s16_f16
19279 && flavour
<= neon_cvt_flavour_f16_u16
)
19280 /* Half precision. */
19281 inst
.instruction
|= 1 << 18;
19283 inst
.instruction
|= 2 << 18;
19285 neon_dp_fixup (&inst
);
19290 /* Half-precision conversions for Advanced SIMD -- neon. */
19293 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19297 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19299 as_bad (_("operand size must match register width"));
19304 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19306 as_bad (_("operand size must match register width"));
19312 if (flavour
== neon_cvt_flavour_bf16_f32
)
19314 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19316 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19317 /* VCVT.bf16.f32. */
19318 inst
.instruction
= 0x11b60640;
19321 /* VCVT.f16.f32. */
19322 inst
.instruction
= 0x3b60600;
19325 /* VCVT.f32.f16. */
19326 inst
.instruction
= 0x3b60700;
19328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19332 neon_dp_fixup (&inst
);
19336 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19337 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19338 do_vfp_nsyn_cvt (rs
, flavour
);
19340 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19345 do_neon_cvtr (void)
19347 do_neon_cvt_1 (neon_cvt_mode_x
);
19353 do_neon_cvt_1 (neon_cvt_mode_z
);
19357 do_neon_cvta (void)
19359 do_neon_cvt_1 (neon_cvt_mode_a
);
19363 do_neon_cvtn (void)
19365 do_neon_cvt_1 (neon_cvt_mode_n
);
19369 do_neon_cvtp (void)
19371 do_neon_cvt_1 (neon_cvt_mode_p
);
19375 do_neon_cvtm (void)
19377 do_neon_cvt_1 (neon_cvt_mode_m
);
19381 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19384 mark_feature_used (&fpu_vfp_ext_armv8
);
19386 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19387 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19388 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19389 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19390 inst
.instruction
|= to
? 0x10000 : 0;
19391 inst
.instruction
|= t
? 0x80 : 0;
19392 inst
.instruction
|= is_double
? 0x100 : 0;
19393 do_vfp_cond_or_thumb ();
19397 do_neon_cvttb_1 (bfd_boolean t
)
19399 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19400 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19404 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19406 int single_to_half
= 0;
19407 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19410 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19412 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19413 && (flavour
== neon_cvt_flavour_u16_f16
19414 || flavour
== neon_cvt_flavour_s16_f16
19415 || flavour
== neon_cvt_flavour_f16_s16
19416 || flavour
== neon_cvt_flavour_f16_u16
19417 || flavour
== neon_cvt_flavour_u32_f32
19418 || flavour
== neon_cvt_flavour_s32_f32
19419 || flavour
== neon_cvt_flavour_f32_s32
19420 || flavour
== neon_cvt_flavour_f32_u32
))
19423 inst
.instruction
= N_MNEM_vcvt
;
19424 set_pred_insn_type (INSIDE_VPT_INSN
);
19425 do_neon_cvt_1 (neon_cvt_mode_z
);
19428 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19429 single_to_half
= 1;
19430 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19432 first_error (BAD_FPU
);
19436 inst
.instruction
= 0xee3f0e01;
19437 inst
.instruction
|= single_to_half
<< 28;
19438 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19439 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19440 inst
.instruction
|= t
<< 12;
19441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19442 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19445 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19448 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19450 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19453 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19455 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19457 /* The VCVTB and VCVTT instructions with D-register operands
19458 don't work for SP only targets. */
19459 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19463 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19465 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19467 /* The VCVTB and VCVTT instructions with D-register operands
19468 don't work for SP only targets. */
19469 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19473 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19475 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19477 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19479 inst
.instruction
|= (1 << 8);
19480 inst
.instruction
&= ~(1 << 9);
19481 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19488 do_neon_cvtb (void)
19490 do_neon_cvttb_1 (FALSE
);
19495 do_neon_cvtt (void)
19497 do_neon_cvttb_1 (TRUE
);
19501 neon_move_immediate (void)
19503 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19504 struct neon_type_el et
= neon_check_type (2, rs
,
19505 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19506 unsigned immlo
, immhi
= 0, immbits
;
19507 int op
, cmode
, float_p
;
19509 constraint (et
.type
== NT_invtype
,
19510 _("operand size must be specified for immediate VMOV"));
19512 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19513 op
= (inst
.instruction
& (1 << 5)) != 0;
19515 immlo
= inst
.operands
[1].imm
;
19516 if (inst
.operands
[1].regisimm
)
19517 immhi
= inst
.operands
[1].reg
;
19519 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19520 _("immediate has bits set outside the operand size"));
19522 float_p
= inst
.operands
[1].immisfloat
;
19524 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19525 et
.size
, et
.type
)) == FAIL
)
19527 /* Invert relevant bits only. */
19528 neon_invert_size (&immlo
, &immhi
, et
.size
);
19529 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19530 with one or the other; those cases are caught by
19531 neon_cmode_for_move_imm. */
19533 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19534 &op
, et
.size
, et
.type
)) == FAIL
)
19536 first_error (_("immediate out of range"));
19541 inst
.instruction
&= ~(1 << 5);
19542 inst
.instruction
|= op
<< 5;
19544 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19545 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19546 inst
.instruction
|= neon_quad (rs
) << 6;
19547 inst
.instruction
|= cmode
<< 8;
19549 neon_write_immbits (immbits
);
19555 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19558 if (inst
.operands
[1].isreg
)
19560 enum neon_shape rs
;
19561 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19562 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19564 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19569 NEON_ENCODE (INTEGER
, inst
);
19570 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19571 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19572 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19573 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19574 inst
.instruction
|= neon_quad (rs
) << 6;
19578 NEON_ENCODE (IMMED
, inst
);
19579 neon_move_immediate ();
19582 neon_dp_fixup (&inst
);
19584 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19586 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19590 /* Encode instructions of form:
19592 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19593 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19596 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19598 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19599 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19600 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19601 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19602 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19603 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19604 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19605 inst
.instruction
|= neon_logbits (size
) << 20;
19607 neon_dp_fixup (&inst
);
19611 do_neon_dyadic_long (void)
19613 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19616 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19619 NEON_ENCODE (INTEGER
, inst
);
19620 /* FIXME: Type checking for lengthening op. */
19621 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19622 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19623 neon_mixed_length (et
, et
.size
);
19625 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19626 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19628 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19629 in an IT block with le/lt conditions. */
19631 if (inst
.cond
== 0xf)
19633 else if (inst
.cond
== 0x10)
19636 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19638 if (inst
.instruction
== N_MNEM_vaddl
)
19640 inst
.instruction
= N_MNEM_vadd
;
19641 do_neon_addsub_if_i ();
19643 else if (inst
.instruction
== N_MNEM_vsubl
)
19645 inst
.instruction
= N_MNEM_vsub
;
19646 do_neon_addsub_if_i ();
19648 else if (inst
.instruction
== N_MNEM_vabdl
)
19650 inst
.instruction
= N_MNEM_vabd
;
19651 do_neon_dyadic_if_su ();
19655 first_error (BAD_FPU
);
19659 do_neon_abal (void)
19661 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19662 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19663 neon_mixed_length (et
, et
.size
);
19667 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19669 if (inst
.operands
[2].isscalar
)
19671 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19672 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19673 NEON_ENCODE (SCALAR
, inst
);
19674 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19678 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19679 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19680 NEON_ENCODE (INTEGER
, inst
);
19681 neon_mixed_length (et
, et
.size
);
19686 do_neon_mac_maybe_scalar_long (void)
19688 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19691 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19692 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19695 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19697 unsigned regno
= NEON_SCALAR_REG (scalar
);
19698 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19702 if (regno
> 7 || elno
> 3)
19705 return ((regno
& 0x7)
19706 | ((elno
& 0x1) << 3)
19707 | (((elno
>> 1) & 0x1) << 5));
19711 if (regno
> 15 || elno
> 1)
19714 return (((regno
& 0x1) << 5)
19715 | ((regno
>> 1) & 0x7)
19716 | ((elno
& 0x1) << 3));
19720 first_error (_("scalar out of range for multiply instruction"));
19725 do_neon_fmac_maybe_scalar_long (int subtype
)
19727 enum neon_shape rs
;
19729 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19730 field (bits[21:20]) has different meaning. For scalar index variant, it's
19731 used to differentiate add and subtract, otherwise it's with fixed value
19735 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19736 be a scalar index register. */
19737 if (inst
.operands
[2].isscalar
)
19739 high8
= 0xfe000000;
19742 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19746 high8
= 0xfc000000;
19749 inst
.instruction
|= (0x1 << 23);
19750 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19754 if (inst
.cond
!= COND_ALWAYS
)
19755 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19756 "behaviour is UNPREDICTABLE"));
19758 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19764 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19765 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19766 so we simply pass -1 as size. */
19767 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19768 neon_three_same (quad_p
, 0, size
);
19770 /* Undo neon_dp_fixup. Redo the high eight bits. */
19771 inst
.instruction
&= 0x00ffffff;
19772 inst
.instruction
|= high8
;
19774 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19775 whether the instruction is in Q form and whether Vm is a scalar indexed
19777 if (inst
.operands
[2].isscalar
)
19780 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19781 inst
.instruction
&= 0xffffffd0;
19782 inst
.instruction
|= rm
;
19786 /* Redo Rn as well. */
19787 inst
.instruction
&= 0xfff0ff7f;
19788 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19789 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19794 /* Redo Rn and Rm. */
19795 inst
.instruction
&= 0xfff0ff50;
19796 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19797 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19798 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19799 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19804 do_neon_vfmal (void)
19806 return do_neon_fmac_maybe_scalar_long (0);
19810 do_neon_vfmsl (void)
19812 return do_neon_fmac_maybe_scalar_long (1);
19816 do_neon_dyadic_wide (void)
19818 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19819 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19820 neon_mixed_length (et
, et
.size
);
19824 do_neon_dyadic_narrow (void)
19826 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19827 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19828 /* Operand sign is unimportant, and the U bit is part of the opcode,
19829 so force the operand type to integer. */
19830 et
.type
= NT_integer
;
19831 neon_mixed_length (et
, et
.size
/ 2);
19835 do_neon_mul_sat_scalar_long (void)
19837 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19841 do_neon_vmull (void)
19843 if (inst
.operands
[2].isscalar
)
19844 do_neon_mac_maybe_scalar_long ();
19847 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19848 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19850 if (et
.type
== NT_poly
)
19851 NEON_ENCODE (POLY
, inst
);
19853 NEON_ENCODE (INTEGER
, inst
);
19855 /* For polynomial encoding the U bit must be zero, and the size must
19856 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19857 obviously, as 0b10). */
19860 /* Check we're on the correct architecture. */
19861 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19863 _("Instruction form not available on this architecture.");
19868 neon_mixed_length (et
, et
.size
);
19875 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19876 struct neon_type_el et
= neon_check_type (3, rs
,
19877 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19878 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19880 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19881 _("shift out of range"));
19882 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19883 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19884 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19885 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19886 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19887 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19888 inst
.instruction
|= neon_quad (rs
) << 6;
19889 inst
.instruction
|= imm
<< 8;
19891 neon_dp_fixup (&inst
);
19897 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19900 enum neon_shape rs
;
19901 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19902 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19904 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19906 struct neon_type_el et
= neon_check_type (2, rs
,
19907 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19909 unsigned op
= (inst
.instruction
>> 7) & 3;
19910 /* N (width of reversed regions) is encoded as part of the bitmask. We
19911 extract it here to check the elements to be reversed are smaller.
19912 Otherwise we'd get a reserved instruction. */
19913 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19915 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19916 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19917 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19918 " operands makes instruction UNPREDICTABLE"));
19920 gas_assert (elsize
!= 0);
19921 constraint (et
.size
>= elsize
,
19922 _("elements must be smaller than reversal region"));
19923 neon_two_same (neon_quad (rs
), 1, et
.size
);
19929 if (inst
.operands
[1].isscalar
)
19931 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19933 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19934 struct neon_type_el et
= neon_check_type (2, rs
,
19935 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19936 unsigned sizebits
= et
.size
>> 3;
19937 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19938 int logsize
= neon_logbits (et
.size
);
19939 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19941 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19944 NEON_ENCODE (SCALAR
, inst
);
19945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19947 inst
.instruction
|= LOW4 (dm
);
19948 inst
.instruction
|= HI1 (dm
) << 5;
19949 inst
.instruction
|= neon_quad (rs
) << 6;
19950 inst
.instruction
|= x
<< 17;
19951 inst
.instruction
|= sizebits
<< 16;
19953 neon_dp_fixup (&inst
);
19957 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19958 struct neon_type_el et
= neon_check_type (2, rs
,
19959 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19962 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19969 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19971 if (inst
.operands
[1].reg
== REG_SP
)
19972 as_tsktsk (MVE_BAD_SP
);
19973 else if (inst
.operands
[1].reg
== REG_PC
)
19974 as_tsktsk (MVE_BAD_PC
);
19977 /* Duplicate ARM register to lanes of vector. */
19978 NEON_ENCODE (ARMREG
, inst
);
19981 case 8: inst
.instruction
|= 0x400000; break;
19982 case 16: inst
.instruction
|= 0x000020; break;
19983 case 32: inst
.instruction
|= 0x000000; break;
19986 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19989 inst
.instruction
|= neon_quad (rs
) << 21;
19990 /* The encoding for this instruction is identical for the ARM and Thumb
19991 variants, except for the condition field. */
19992 do_vfp_cond_or_thumb ();
19997 do_mve_mov (int toQ
)
19999 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20001 if (inst
.cond
> COND_ALWAYS
)
20002 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
20004 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20013 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20014 _("Index one must be [2,3] and index two must be two less than"
20016 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20017 _("General purpose registers may not be the same"));
20018 constraint (inst
.operands
[Rt
].reg
== REG_SP
20019 || inst
.operands
[Rt2
].reg
== REG_SP
,
20021 constraint (inst
.operands
[Rt
].reg
== REG_PC
20022 || inst
.operands
[Rt2
].reg
== REG_PC
,
20025 inst
.instruction
= 0xec000f00;
20026 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20027 inst
.instruction
|= !!toQ
<< 20;
20028 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20029 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20030 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20031 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20037 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20040 if (inst
.cond
> COND_ALWAYS
)
20041 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20043 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20045 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20048 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20049 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20050 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20051 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20052 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20057 /* VMOV has particularly many variations. It can be one of:
20058 0. VMOV<c><q> <Qd>, <Qm>
20059 1. VMOV<c><q> <Dd>, <Dm>
20060 (Register operations, which are VORR with Rm = Rn.)
20061 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20062 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20064 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20065 (ARM register to scalar.)
20066 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20067 (Two ARM registers to vector.)
20068 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20069 (Scalar to ARM register.)
20070 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20071 (Vector to two ARM registers.)
20072 8. VMOV.F32 <Sd>, <Sm>
20073 9. VMOV.F64 <Dd>, <Dm>
20074 (VFP register moves.)
20075 10. VMOV.F32 <Sd>, #imm
20076 11. VMOV.F64 <Dd>, #imm
20077 (VFP float immediate load.)
20078 12. VMOV <Rd>, <Sm>
20079 (VFP single to ARM reg.)
20080 13. VMOV <Sd>, <Rm>
20081 (ARM reg to VFP single.)
20082 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20083 (Two ARM regs to two VFP singles.)
20084 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20085 (Two VFP singles to two ARM regs.)
20086 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20087 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20088 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20089 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20091 These cases can be disambiguated using neon_select_shape, except cases 1/9
20092 and 3/11 which depend on the operand type too.
20094 All the encoded bits are hardcoded by this function.
20096 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20097 Cases 5, 7 may be used with VFPv2 and above.
20099 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20100 can specify a type where it doesn't make sense to, and is ignored). */
20105 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20106 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20107 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20108 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20110 struct neon_type_el et
;
20111 const char *ldconst
= 0;
20115 case NS_DD
: /* case 1/9. */
20116 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20117 /* It is not an error here if no type is given. */
20120 /* In MVE we interpret the following instructions as same, so ignoring
20121 the following type (float) and size (64) checks.
20122 a: VMOV<c><q> <Dd>, <Dm>
20123 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20124 if ((et
.type
== NT_float
&& et
.size
== 64)
20125 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20127 do_vfp_nsyn_opcode ("fcpyd");
20130 /* fall through. */
20132 case NS_QQ
: /* case 0/1. */
20134 if (!check_simd_pred_availability (FALSE
,
20135 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20137 /* The architecture manual I have doesn't explicitly state which
20138 value the U bit should have for register->register moves, but
20139 the equivalent VORR instruction has U = 0, so do that. */
20140 inst
.instruction
= 0x0200110;
20141 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20143 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20144 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20147 inst
.instruction
|= neon_quad (rs
) << 6;
20149 neon_dp_fixup (&inst
);
20153 case NS_DI
: /* case 3/11. */
20154 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20156 if (et
.type
== NT_float
&& et
.size
== 64)
20158 /* case 11 (fconstd). */
20159 ldconst
= "fconstd";
20160 goto encode_fconstd
;
20162 /* fall through. */
20164 case NS_QI
: /* case 2/3. */
20165 if (!check_simd_pred_availability (FALSE
,
20166 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20168 inst
.instruction
= 0x0800010;
20169 neon_move_immediate ();
20170 neon_dp_fixup (&inst
);
20173 case NS_SR
: /* case 4. */
20175 unsigned bcdebits
= 0;
20177 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20178 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20180 /* .<size> is optional here, defaulting to .32. */
20181 if (inst
.vectype
.elems
== 0
20182 && inst
.operands
[0].vectype
.type
== NT_invtype
20183 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20185 inst
.vectype
.el
[0].type
= NT_untyped
;
20186 inst
.vectype
.el
[0].size
= 32;
20187 inst
.vectype
.elems
= 1;
20190 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20191 logsize
= neon_logbits (et
.size
);
20195 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20196 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20201 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20202 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20206 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20208 if (inst
.operands
[1].reg
== REG_SP
)
20209 as_tsktsk (MVE_BAD_SP
);
20210 else if (inst
.operands
[1].reg
== REG_PC
)
20211 as_tsktsk (MVE_BAD_PC
);
20213 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20215 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20216 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20221 case 8: bcdebits
= 0x8; break;
20222 case 16: bcdebits
= 0x1; break;
20223 case 32: bcdebits
= 0x0; break;
20227 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20229 inst
.instruction
= 0xe000b10;
20230 do_vfp_cond_or_thumb ();
20231 inst
.instruction
|= LOW4 (dn
) << 16;
20232 inst
.instruction
|= HI1 (dn
) << 7;
20233 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20234 inst
.instruction
|= (bcdebits
& 3) << 5;
20235 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20236 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20240 case NS_DRR
: /* case 5 (fmdrr). */
20241 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20242 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20245 inst
.instruction
= 0xc400b10;
20246 do_vfp_cond_or_thumb ();
20247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20249 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20250 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20253 case NS_RS
: /* case 6. */
20256 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20257 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20258 unsigned abcdebits
= 0;
20260 /* .<dt> is optional here, defaulting to .32. */
20261 if (inst
.vectype
.elems
== 0
20262 && inst
.operands
[0].vectype
.type
== NT_invtype
20263 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20265 inst
.vectype
.el
[0].type
= NT_untyped
;
20266 inst
.vectype
.el
[0].size
= 32;
20267 inst
.vectype
.elems
= 1;
20270 et
= neon_check_type (2, NS_NULL
,
20271 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20272 logsize
= neon_logbits (et
.size
);
20276 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20277 && vfp_or_neon_is_neon (NEON_CHECK_CC
20278 | NEON_CHECK_ARCH
) == FAIL
)
20283 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20284 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20288 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20290 if (inst
.operands
[0].reg
== REG_SP
)
20291 as_tsktsk (MVE_BAD_SP
);
20292 else if (inst
.operands
[0].reg
== REG_PC
)
20293 as_tsktsk (MVE_BAD_PC
);
20296 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20298 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20299 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20303 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20304 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20305 case 32: abcdebits
= 0x00; break;
20309 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20310 inst
.instruction
= 0xe100b10;
20311 do_vfp_cond_or_thumb ();
20312 inst
.instruction
|= LOW4 (dn
) << 16;
20313 inst
.instruction
|= HI1 (dn
) << 7;
20314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20315 inst
.instruction
|= (abcdebits
& 3) << 5;
20316 inst
.instruction
|= (abcdebits
>> 2) << 21;
20317 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20321 case NS_RRD
: /* case 7 (fmrrd). */
20322 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20323 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20326 inst
.instruction
= 0xc500b10;
20327 do_vfp_cond_or_thumb ();
20328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20329 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20330 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20331 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20334 case NS_FF
: /* case 8 (fcpys). */
20335 do_vfp_nsyn_opcode ("fcpys");
20339 case NS_FI
: /* case 10 (fconsts). */
20340 ldconst
= "fconsts";
20342 if (!inst
.operands
[1].immisfloat
)
20345 /* Immediate has to fit in 8 bits so float is enough. */
20346 float imm
= (float) inst
.operands
[1].imm
;
20347 memcpy (&new_imm
, &imm
, sizeof (float));
20348 /* But the assembly may have been written to provide an integer
20349 bit pattern that equates to a float, so check that the
20350 conversion has worked. */
20351 if (is_quarter_float (new_imm
))
20353 if (is_quarter_float (inst
.operands
[1].imm
))
20354 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20356 inst
.operands
[1].imm
= new_imm
;
20357 inst
.operands
[1].immisfloat
= 1;
20361 if (is_quarter_float (inst
.operands
[1].imm
))
20363 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20364 do_vfp_nsyn_opcode (ldconst
);
20366 /* ARMv8.2 fp16 vmov.f16 instruction. */
20368 do_scalar_fp16_v82_encode ();
20371 first_error (_("immediate out of range"));
20375 case NS_RF
: /* case 12 (fmrs). */
20376 do_vfp_nsyn_opcode ("fmrs");
20377 /* ARMv8.2 fp16 vmov.f16 instruction. */
20379 do_scalar_fp16_v82_encode ();
20383 case NS_FR
: /* case 13 (fmsr). */
20384 do_vfp_nsyn_opcode ("fmsr");
20385 /* ARMv8.2 fp16 vmov.f16 instruction. */
20387 do_scalar_fp16_v82_encode ();
20397 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20398 (one of which is a list), but we have parsed four. Do some fiddling to
20399 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20401 case NS_RRFF
: /* case 14 (fmrrs). */
20402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20403 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20405 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20406 _("VFP registers must be adjacent"));
20407 inst
.operands
[2].imm
= 2;
20408 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20409 do_vfp_nsyn_opcode ("fmrrs");
20412 case NS_FFRR
: /* case 15 (fmsrr). */
20413 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20414 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20416 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20417 _("VFP registers must be adjacent"));
20418 inst
.operands
[1] = inst
.operands
[2];
20419 inst
.operands
[2] = inst
.operands
[3];
20420 inst
.operands
[0].imm
= 2;
20421 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20422 do_vfp_nsyn_opcode ("fmsrr");
20426 /* neon_select_shape has determined that the instruction
20427 shape is wrong and has already set the error message. */
20438 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20439 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20440 && !inst
.operands
[2].present
))
20442 inst
.instruction
= 0;
20445 set_pred_insn_type (INSIDE_IT_INSN
);
20450 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20453 if (inst
.cond
!= COND_ALWAYS
)
20454 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20456 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20457 | N_S16
| N_U16
| N_KEY
);
20459 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20460 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20461 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20462 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20463 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20464 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20469 do_neon_rshift_round_imm (void)
20471 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20474 enum neon_shape rs
;
20475 struct neon_type_el et
;
20477 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20479 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20480 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20484 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20485 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20487 int imm
= inst
.operands
[2].imm
;
20489 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20492 inst
.operands
[2].present
= 0;
20497 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20498 _("immediate out of range for shift"));
20499 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20504 do_neon_movhf (void)
20506 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20507 constraint (rs
!= NS_HH
, _("invalid suffix"));
20509 if (inst
.cond
!= COND_ALWAYS
)
20513 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20514 " the behaviour is UNPREDICTABLE"));
20518 inst
.error
= BAD_COND
;
20523 do_vfp_sp_monadic ();
20526 inst
.instruction
|= 0xf0000000;
20530 do_neon_movl (void)
20532 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20533 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20534 unsigned sizebits
= et
.size
>> 3;
20535 inst
.instruction
|= sizebits
<< 19;
20536 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20542 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20543 struct neon_type_el et
= neon_check_type (2, rs
,
20544 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20545 NEON_ENCODE (INTEGER
, inst
);
20546 neon_two_same (neon_quad (rs
), 1, et
.size
);
20550 do_neon_zip_uzp (void)
20552 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20553 struct neon_type_el et
= neon_check_type (2, rs
,
20554 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20555 if (rs
== NS_DD
&& et
.size
== 32)
20557 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20558 inst
.instruction
= N_MNEM_vtrn
;
20562 neon_two_same (neon_quad (rs
), 1, et
.size
);
20566 do_neon_sat_abs_neg (void)
20568 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20571 enum neon_shape rs
;
20572 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20573 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20575 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
,
20577 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20578 neon_two_same (neon_quad (rs
), 1, et
.size
);
20582 do_neon_pair_long (void)
20584 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20585 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20586 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20587 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20588 neon_two_same (neon_quad (rs
), 1, et
.size
);
20592 do_neon_recip_est (void)
20594 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20595 struct neon_type_el et
= neon_check_type (2, rs
,
20596 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20597 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20598 neon_two_same (neon_quad (rs
), 1, et
.size
);
20604 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20607 enum neon_shape rs
;
20608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20609 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20611 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20613 struct neon_type_el et
= neon_check_type (2, rs
,
20614 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20615 neon_two_same (neon_quad (rs
), 1, et
.size
);
20621 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20624 enum neon_shape rs
;
20625 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20626 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20628 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20630 struct neon_type_el et
= neon_check_type (2, rs
,
20631 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20632 neon_two_same (neon_quad (rs
), 1, et
.size
);
20638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20639 struct neon_type_el et
= neon_check_type (2, rs
,
20640 N_EQK
| N_INT
, N_8
| N_KEY
);
20641 neon_two_same (neon_quad (rs
), 1, et
.size
);
20647 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20650 neon_two_same (neon_quad (rs
), 1, -1);
20654 do_neon_tbl_tbx (void)
20656 unsigned listlenbits
;
20657 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20659 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20661 first_error (_("bad list length for table lookup"));
20665 listlenbits
= inst
.operands
[1].imm
- 1;
20666 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20667 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20668 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20669 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20670 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20671 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20672 inst
.instruction
|= listlenbits
<< 8;
20674 neon_dp_fixup (&inst
);
20678 do_neon_ldm_stm (void)
20680 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20681 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20683 /* P, U and L bits are part of bitmask. */
20684 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20685 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20687 if (inst
.operands
[1].issingle
)
20689 do_vfp_nsyn_ldm_stm (is_dbmode
);
20693 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20694 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20696 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20697 _("register list must contain at least 1 and at most 16 "
20700 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20701 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20702 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20703 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20705 inst
.instruction
|= offsetbits
;
20707 do_vfp_cond_or_thumb ();
20711 do_vfp_nsyn_pop (void)
20714 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20715 return do_vfp_nsyn_opcode ("vldm");
20718 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20721 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20722 _("register list must contain at least 1 and at most 16 "
20725 if (inst
.operands
[1].issingle
)
20726 do_vfp_nsyn_opcode ("fldmias");
20728 do_vfp_nsyn_opcode ("fldmiad");
20732 do_vfp_nsyn_push (void)
20735 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20736 return do_vfp_nsyn_opcode ("vstmdb");
20739 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20742 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20743 _("register list must contain at least 1 and at most 16 "
20746 if (inst
.operands
[1].issingle
)
20747 do_vfp_nsyn_opcode ("fstmdbs");
20749 do_vfp_nsyn_opcode ("fstmdbd");
20754 do_neon_ldr_str (void)
20756 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20758 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20759 And is UNPREDICTABLE in thumb mode. */
20761 && inst
.operands
[1].reg
== REG_PC
20762 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20765 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20766 else if (warn_on_deprecated
)
20767 as_tsktsk (_("Use of PC here is deprecated"));
20770 if (inst
.operands
[0].issingle
)
20773 do_vfp_nsyn_opcode ("flds");
20775 do_vfp_nsyn_opcode ("fsts");
20777 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20778 if (inst
.vectype
.el
[0].size
== 16)
20779 do_scalar_fp16_v82_encode ();
20784 do_vfp_nsyn_opcode ("fldd");
20786 do_vfp_nsyn_opcode ("fstd");
20791 do_t_vldr_vstr_sysreg (void)
20793 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20794 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20796 /* Use of PC is UNPREDICTABLE. */
20797 if (inst
.operands
[1].reg
== REG_PC
)
20798 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20800 if (inst
.operands
[1].immisreg
)
20801 inst
.error
= _("instruction does not accept register index");
20803 if (!inst
.operands
[1].isreg
)
20804 inst
.error
= _("instruction does not accept PC-relative addressing");
20806 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20807 inst
.error
= _("immediate value out of range");
20809 inst
.instruction
= 0xec000f80;
20811 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20812 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20813 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20814 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20818 do_vldr_vstr (void)
20820 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20822 /* VLDR/VSTR (System Register). */
20825 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20826 as_bad (_("Instruction not permitted on this architecture"));
20828 do_t_vldr_vstr_sysreg ();
20833 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20834 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20835 as_bad (_("Instruction not permitted on this architecture"));
20836 do_neon_ldr_str ();
20840 /* "interleave" version also handles non-interleaving register VLD1/VST1
20844 do_neon_ld_st_interleave (void)
20846 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20847 N_8
| N_16
| N_32
| N_64
);
20848 unsigned alignbits
= 0;
20850 /* The bits in this table go:
20851 0: register stride of one (0) or two (1)
20852 1,2: register list length, minus one (1, 2, 3, 4).
20853 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20854 We use -1 for invalid entries. */
20855 const int typetable
[] =
20857 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20858 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20859 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20860 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20864 if (et
.type
== NT_invtype
)
20867 if (inst
.operands
[1].immisalign
)
20868 switch (inst
.operands
[1].imm
>> 8)
20870 case 64: alignbits
= 1; break;
20872 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20873 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20874 goto bad_alignment
;
20878 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20879 goto bad_alignment
;
20884 first_error (_("bad alignment"));
20888 inst
.instruction
|= alignbits
<< 4;
20889 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20891 /* Bits [4:6] of the immediate in a list specifier encode register stride
20892 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20893 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20894 up the right value for "type" in a table based on this value and the given
20895 list style, then stick it back. */
20896 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20897 | (((inst
.instruction
>> 8) & 3) << 3);
20899 typebits
= typetable
[idx
];
20901 constraint (typebits
== -1, _("bad list type for instruction"));
20902 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20905 inst
.instruction
&= ~0xf00;
20906 inst
.instruction
|= typebits
<< 8;
20909 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20910 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20911 otherwise. The variable arguments are a list of pairs of legal (size, align)
20912 values, terminated with -1. */
20915 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20918 int result
= FAIL
, thissize
, thisalign
;
20920 if (!inst
.operands
[1].immisalign
)
20926 va_start (ap
, do_alignment
);
20930 thissize
= va_arg (ap
, int);
20931 if (thissize
== -1)
20933 thisalign
= va_arg (ap
, int);
20935 if (size
== thissize
&& align
== thisalign
)
20938 while (result
!= SUCCESS
);
20942 if (result
== SUCCESS
)
20945 first_error (_("unsupported alignment for instruction"));
20951 do_neon_ld_st_lane (void)
20953 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20954 int align_good
, do_alignment
= 0;
20955 int logsize
= neon_logbits (et
.size
);
20956 int align
= inst
.operands
[1].imm
>> 8;
20957 int n
= (inst
.instruction
>> 8) & 3;
20958 int max_el
= 64 / et
.size
;
20960 if (et
.type
== NT_invtype
)
20963 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20964 _("bad list length"));
20965 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20966 _("scalar index out of range"));
20967 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20969 _("stride of 2 unavailable when element size is 8"));
20973 case 0: /* VLD1 / VST1. */
20974 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20976 if (align_good
== FAIL
)
20980 unsigned alignbits
= 0;
20983 case 16: alignbits
= 0x1; break;
20984 case 32: alignbits
= 0x3; break;
20987 inst
.instruction
|= alignbits
<< 4;
20991 case 1: /* VLD2 / VST2. */
20992 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20993 16, 32, 32, 64, -1);
20994 if (align_good
== FAIL
)
20997 inst
.instruction
|= 1 << 4;
21000 case 2: /* VLD3 / VST3. */
21001 constraint (inst
.operands
[1].immisalign
,
21002 _("can't use alignment with this instruction"));
21005 case 3: /* VLD4 / VST4. */
21006 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21007 16, 64, 32, 64, 32, 128, -1);
21008 if (align_good
== FAIL
)
21012 unsigned alignbits
= 0;
21015 case 8: alignbits
= 0x1; break;
21016 case 16: alignbits
= 0x1; break;
21017 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21020 inst
.instruction
|= alignbits
<< 4;
21027 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21028 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21029 inst
.instruction
|= 1 << (4 + logsize
);
21031 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21032 inst
.instruction
|= logsize
<< 10;
21035 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21038 do_neon_ld_dup (void)
21040 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21041 int align_good
, do_alignment
= 0;
21043 if (et
.type
== NT_invtype
)
21046 switch ((inst
.instruction
>> 8) & 3)
21048 case 0: /* VLD1. */
21049 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21050 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21051 &do_alignment
, 16, 16, 32, 32, -1);
21052 if (align_good
== FAIL
)
21054 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21057 case 2: inst
.instruction
|= 1 << 5; break;
21058 default: first_error (_("bad list length")); return;
21060 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21063 case 1: /* VLD2. */
21064 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21065 &do_alignment
, 8, 16, 16, 32, 32, 64,
21067 if (align_good
== FAIL
)
21069 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21070 _("bad list length"));
21071 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21072 inst
.instruction
|= 1 << 5;
21073 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21076 case 2: /* VLD3. */
21077 constraint (inst
.operands
[1].immisalign
,
21078 _("can't use alignment with this instruction"));
21079 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21080 _("bad list length"));
21081 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21082 inst
.instruction
|= 1 << 5;
21083 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21086 case 3: /* VLD4. */
21088 int align
= inst
.operands
[1].imm
>> 8;
21089 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21090 16, 64, 32, 64, 32, 128, -1);
21091 if (align_good
== FAIL
)
21093 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21094 _("bad list length"));
21095 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21096 inst
.instruction
|= 1 << 5;
21097 if (et
.size
== 32 && align
== 128)
21098 inst
.instruction
|= 0x3 << 6;
21100 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21107 inst
.instruction
|= do_alignment
<< 4;
21110 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21111 apart from bits [11:4]. */
21114 do_neon_ldx_stx (void)
21116 if (inst
.operands
[1].isreg
)
21117 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21119 switch (NEON_LANE (inst
.operands
[0].imm
))
21121 case NEON_INTERLEAVE_LANES
:
21122 NEON_ENCODE (INTERLV
, inst
);
21123 do_neon_ld_st_interleave ();
21126 case NEON_ALL_LANES
:
21127 NEON_ENCODE (DUP
, inst
);
21128 if (inst
.instruction
== N_INV
)
21130 first_error ("only loads support such operands");
21137 NEON_ENCODE (LANE
, inst
);
21138 do_neon_ld_st_lane ();
21141 /* L bit comes from bit mask. */
21142 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21143 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21146 if (inst
.operands
[1].postind
)
21148 int postreg
= inst
.operands
[1].imm
& 0xf;
21149 constraint (!inst
.operands
[1].immisreg
,
21150 _("post-index must be a register"));
21151 constraint (postreg
== 0xd || postreg
== 0xf,
21152 _("bad register for post-index"));
21153 inst
.instruction
|= postreg
;
21157 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21158 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21159 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21162 if (inst
.operands
[1].writeback
)
21164 inst
.instruction
|= 0xd;
21167 inst
.instruction
|= 0xf;
21171 inst
.instruction
|= 0xf9000000;
21173 inst
.instruction
|= 0xf4000000;
21178 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21180 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21181 D register operands. */
21182 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21183 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21186 NEON_ENCODE (FPV8
, inst
);
21188 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21190 do_vfp_sp_dyadic ();
21192 /* ARMv8.2 fp16 instruction. */
21194 do_scalar_fp16_v82_encode ();
21197 do_vfp_dp_rd_rn_rm ();
21200 inst
.instruction
|= 0x100;
21202 inst
.instruction
|= 0xf0000000;
21208 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21210 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21211 first_error (_("invalid instruction shape"));
21217 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21218 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21220 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21223 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21226 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21230 do_vrint_1 (enum neon_cvt_mode mode
)
21232 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21233 struct neon_type_el et
;
21238 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21239 D register operands. */
21240 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21241 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21244 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21246 if (et
.type
!= NT_invtype
)
21248 /* VFP encodings. */
21249 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21250 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21251 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21253 NEON_ENCODE (FPV8
, inst
);
21254 if (rs
== NS_FF
|| rs
== NS_HH
)
21255 do_vfp_sp_monadic ();
21257 do_vfp_dp_rd_rm ();
21261 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21262 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21263 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21264 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21265 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21266 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21267 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21271 inst
.instruction
|= (rs
== NS_DD
) << 8;
21272 do_vfp_cond_or_thumb ();
21274 /* ARMv8.2 fp16 vrint instruction. */
21276 do_scalar_fp16_v82_encode ();
21280 /* Neon encodings (or something broken...). */
21282 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21284 if (et
.type
== NT_invtype
)
21287 if (!check_simd_pred_availability (TRUE
,
21288 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21291 NEON_ENCODE (FLOAT
, inst
);
21293 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21294 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21295 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21296 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21297 inst
.instruction
|= neon_quad (rs
) << 6;
21298 /* Mask off the original size bits and reencode them. */
21299 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21300 | neon_logbits (et
.size
) << 18);
21304 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21305 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21306 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21307 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21308 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21309 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21310 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21315 inst
.instruction
|= 0xfc000000;
21317 inst
.instruction
|= 0xf0000000;
21324 do_vrint_1 (neon_cvt_mode_x
);
21330 do_vrint_1 (neon_cvt_mode_z
);
21336 do_vrint_1 (neon_cvt_mode_r
);
21342 do_vrint_1 (neon_cvt_mode_a
);
21348 do_vrint_1 (neon_cvt_mode_n
);
21354 do_vrint_1 (neon_cvt_mode_p
);
21360 do_vrint_1 (neon_cvt_mode_m
);
21364 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21366 unsigned regno
= NEON_SCALAR_REG (opnd
);
21367 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21369 if (elsize
== 16 && elno
< 2 && regno
< 16)
21370 return regno
| (elno
<< 4);
21371 else if (elsize
== 32 && elno
== 0)
21374 first_error (_("scalar out of range"));
21381 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21382 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21383 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21384 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21385 _("expression too complex"));
21386 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21387 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21388 _("immediate out of range"));
21391 if (!check_simd_pred_availability (TRUE
,
21392 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21395 if (inst
.operands
[2].isscalar
)
21397 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21398 first_error (_("invalid instruction shape"));
21399 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21400 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21401 N_KEY
| N_F16
| N_F32
).size
;
21402 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21404 inst
.instruction
= 0xfe000800;
21405 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21406 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21407 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21408 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21409 inst
.instruction
|= LOW4 (m
);
21410 inst
.instruction
|= HI1 (m
) << 5;
21411 inst
.instruction
|= neon_quad (rs
) << 6;
21412 inst
.instruction
|= rot
<< 20;
21413 inst
.instruction
|= (size
== 32) << 23;
21417 enum neon_shape rs
;
21418 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21419 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21421 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21423 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21424 N_KEY
| N_F16
| N_F32
).size
;
21425 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21426 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21427 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21428 as_tsktsk (BAD_MVE_SRCDEST
);
21430 neon_three_same (neon_quad (rs
), 0, -1);
21431 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21432 inst
.instruction
|= 0xfc200800;
21433 inst
.instruction
|= rot
<< 23;
21434 inst
.instruction
|= (size
== 32) << 20;
21441 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21442 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21443 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21444 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21445 _("expression too complex"));
21447 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21448 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21449 enum neon_shape rs
;
21450 struct neon_type_el et
;
21451 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21453 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21454 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21458 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21459 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21461 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21462 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21463 "operand makes instruction UNPREDICTABLE"));
21466 if (et
.type
== NT_invtype
)
21469 if (!check_simd_pred_availability (et
.type
== NT_float
,
21470 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21473 if (et
.type
== NT_float
)
21475 neon_three_same (neon_quad (rs
), 0, -1);
21476 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21477 inst
.instruction
|= 0xfc800800;
21478 inst
.instruction
|= (rot
== 270) << 24;
21479 inst
.instruction
|= (et
.size
== 32) << 20;
21483 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21484 inst
.instruction
= 0xfe000f00;
21485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21486 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21487 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21488 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21489 inst
.instruction
|= (rot
== 270) << 12;
21490 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21491 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21492 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21497 /* Dot Product instructions encoding support. */
21500 do_neon_dotproduct (int unsigned_p
)
21502 enum neon_shape rs
;
21503 unsigned scalar_oprd2
= 0;
21506 if (inst
.cond
!= COND_ALWAYS
)
21507 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21508 "is UNPREDICTABLE"));
21510 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21513 /* Dot Product instructions are in three-same D/Q register format or the third
21514 operand can be a scalar index register. */
21515 if (inst
.operands
[2].isscalar
)
21517 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21518 high8
= 0xfe000000;
21519 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21523 high8
= 0xfc000000;
21524 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21528 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21530 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21532 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21533 Product instruction, so we pass 0 as the "ubit" parameter. And the
21534 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21535 neon_three_same (neon_quad (rs
), 0, 32);
21537 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21538 different NEON three-same encoding. */
21539 inst
.instruction
&= 0x00ffffff;
21540 inst
.instruction
|= high8
;
21541 /* Encode 'U' bit which indicates signedness. */
21542 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21543 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21544 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21545 the instruction encoding. */
21546 if (inst
.operands
[2].isscalar
)
21548 inst
.instruction
&= 0xffffffd0;
21549 inst
.instruction
|= LOW4 (scalar_oprd2
);
21550 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21554 /* Dot Product instructions for signed integer. */
21557 do_neon_dotproduct_s (void)
21559 return do_neon_dotproduct (0);
21562 /* Dot Product instructions for unsigned integer. */
21565 do_neon_dotproduct_u (void)
21567 return do_neon_dotproduct (1);
21573 enum neon_shape rs
;
21574 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21575 if (inst
.operands
[2].isscalar
)
21577 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21578 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21580 inst
.instruction
|= (1 << 25);
21581 int index
= inst
.operands
[2].reg
& 0xf;
21582 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21583 inst
.operands
[2].reg
>>= 4;
21584 constraint (!(inst
.operands
[2].reg
< 16),
21585 _("indexed register must be less than 16"));
21586 neon_three_args (rs
== NS_QQS
);
21587 inst
.instruction
|= (index
<< 5);
21591 inst
.instruction
|= (1 << 21);
21592 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21593 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21594 neon_three_args (rs
== NS_QQQ
);
21601 enum neon_shape rs
;
21602 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21603 if (inst
.operands
[2].isscalar
)
21605 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21606 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21608 inst
.instruction
|= (1 << 25);
21609 int index
= inst
.operands
[2].reg
& 0xf;
21610 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21611 inst
.operands
[2].reg
>>= 4;
21612 constraint (!(inst
.operands
[2].reg
< 16),
21613 _("indexed register must be less than 16"));
21614 neon_three_args (rs
== NS_QQS
);
21615 inst
.instruction
|= (index
<< 5);
21622 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21623 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21625 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21627 neon_three_args (1);
21634 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21635 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21637 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21639 neon_three_args (1);
21644 check_cde_operand (size_t index
, int is_dual
)
21646 unsigned Rx
= inst
.operands
[index
].reg
;
21647 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21648 if (is_dual
== 0 && thumb_mode
)
21650 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21651 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21653 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21654 _("Register must be an even register between r0-r10."));
21658 cde_coproc_enabled (unsigned coproc
)
21662 case 0: return mark_feature_used (&arm_ext_cde0
);
21663 case 1: return mark_feature_used (&arm_ext_cde1
);
21664 case 2: return mark_feature_used (&arm_ext_cde2
);
21665 case 3: return mark_feature_used (&arm_ext_cde3
);
21666 case 4: return mark_feature_used (&arm_ext_cde4
);
21667 case 5: return mark_feature_used (&arm_ext_cde5
);
21668 case 6: return mark_feature_used (&arm_ext_cde6
);
21669 case 7: return mark_feature_used (&arm_ext_cde7
);
21670 default: return FALSE
;
21674 #define cde_coproc_pos 8
21676 cde_handle_coproc (void)
21678 unsigned coproc
= inst
.operands
[0].reg
;
21679 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21680 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21681 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21683 #undef cde_coproc_pos
21686 cxn_handle_predication (bfd_boolean is_accum
)
21688 if (is_accum
&& conditional_insn ())
21689 set_pred_insn_type (INSIDE_IT_INSN
);
21690 else if (conditional_insn ())
21691 /* conditional_insn essentially checks for a suffix, not whether the
21692 instruction is inside an IT block or not.
21693 The non-accumulator versions should not have suffixes. */
21694 inst
.error
= BAD_SYNTAX
;
21696 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21700 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21703 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21707 Rd
= inst
.operands
[1].reg
;
21708 check_cde_operand (1, is_dual
);
21712 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21713 _("cx1d requires consecutive destination registers."));
21714 imm
= inst
.operands
[3].imm
;
21716 else if (is_dual
== 0)
21717 imm
= inst
.operands
[2].imm
;
21721 inst
.instruction
|= Rd
<< 12;
21722 inst
.instruction
|= (imm
& 0x1F80) << 9;
21723 inst
.instruction
|= (imm
& 0x0040) << 1;
21724 inst
.instruction
|= (imm
& 0x003f);
21726 cde_handle_coproc ();
21727 cxn_handle_predication (is_accum
);
21731 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21734 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21736 unsigned imm
, Rd
, Rn
;
21738 Rd
= inst
.operands
[1].reg
;
21742 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21743 _("cx2d requires consecutive destination registers."));
21744 imm
= inst
.operands
[4].imm
;
21745 Rn
= inst
.operands
[3].reg
;
21747 else if (is_dual
== 0)
21749 imm
= inst
.operands
[3].imm
;
21750 Rn
= inst
.operands
[2].reg
;
21755 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21756 check_cde_operand (1, is_dual
);
21758 inst
.instruction
|= Rd
<< 12;
21759 inst
.instruction
|= Rn
<< 16;
21761 inst
.instruction
|= (imm
& 0x0380) << 13;
21762 inst
.instruction
|= (imm
& 0x0040) << 1;
21763 inst
.instruction
|= (imm
& 0x003f);
21765 cde_handle_coproc ();
21766 cxn_handle_predication (is_accum
);
21770 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21773 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21775 unsigned imm
, Rd
, Rn
, Rm
;
21777 Rd
= inst
.operands
[1].reg
;
21781 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21782 _("cx3d requires consecutive destination registers."));
21783 imm
= inst
.operands
[5].imm
;
21784 Rn
= inst
.operands
[3].reg
;
21785 Rm
= inst
.operands
[4].reg
;
21787 else if (is_dual
== 0)
21789 imm
= inst
.operands
[4].imm
;
21790 Rn
= inst
.operands
[2].reg
;
21791 Rm
= inst
.operands
[3].reg
;
21796 check_cde_operand (1, is_dual
);
21797 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21798 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21800 inst
.instruction
|= Rd
;
21801 inst
.instruction
|= Rn
<< 16;
21802 inst
.instruction
|= Rm
<< 12;
21804 inst
.instruction
|= (imm
& 0x0038) << 17;
21805 inst
.instruction
|= (imm
& 0x0004) << 5;
21806 inst
.instruction
|= (imm
& 0x0003) << 4;
21808 cde_handle_coproc ();
21809 cxn_handle_predication (is_accum
);
21815 return do_custom_instruction_1 (0, 0);
21821 return do_custom_instruction_1 (0, 1);
21827 return do_custom_instruction_1 (1, 0);
21833 return do_custom_instruction_1 (1, 1);
21839 return do_custom_instruction_2 (0, 0);
21845 return do_custom_instruction_2 (0, 1);
21851 return do_custom_instruction_2 (1, 0);
21857 return do_custom_instruction_2 (1, 1);
21863 return do_custom_instruction_3 (0, 0);
21869 return do_custom_instruction_3 (0, 1);
21875 return do_custom_instruction_3 (1, 0);
21881 return do_custom_instruction_3 (1, 1);
21885 vcx_assign_vec_d (unsigned regnum
)
21887 inst
.instruction
|= HI4 (regnum
) << 12;
21888 inst
.instruction
|= LOW1 (regnum
) << 22;
21892 vcx_assign_vec_m (unsigned regnum
)
21894 inst
.instruction
|= HI4 (regnum
);
21895 inst
.instruction
|= LOW1 (regnum
) << 5;
21899 vcx_assign_vec_n (unsigned regnum
)
21901 inst
.instruction
|= HI4 (regnum
) << 16;
21902 inst
.instruction
|= LOW1 (regnum
) << 7;
21905 enum vcx_reg_type
{
21911 static enum vcx_reg_type
21912 vcx_get_reg_type (enum neon_shape ns
)
21914 gas_assert (ns
== NS_PQI
21922 || ns
== NS_PFFFI
);
21923 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21925 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21930 #define vcx_size_pos 24
21931 #define vcx_vec_pos 6
21933 vcx_handle_shape (enum vcx_reg_type reg_type
)
21936 if (reg_type
== q_reg
)
21937 inst
.instruction
|= 1 << vcx_vec_pos
;
21938 else if (reg_type
== d_reg
)
21939 inst
.instruction
|= 1 << vcx_size_pos
;
21943 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21944 bits (or equivalent for N and M registers).
21945 Similarly the D registers are encoded as N in D:Vd bits.
21946 While the S registers are encoded as N in the Vd:D bits.
21948 Taking into account the maximum values of these registers we can see a
21949 nicer pattern for calculation:
21950 Q -> 7, D -> 15, S -> 31
21952 If we say that everything is encoded in the Vd:D bits, then we can say
21953 that Q is encoded as 4*N, and D is encoded as 2*N.
21954 This way the bits will end up the same, and calculation is simpler.
21955 (calculation is now:
21956 1. Multiply by a number determined by the register letter.
21957 2. Encode resulting number in Vd:D bits.)
21959 This is made a little more complicated by automatic handling of 'Q'
21960 registers elsewhere, which means the register number is already 2*N where
21961 N is the number the user wrote after the register letter.
21966 #undef vcx_size_pos
21969 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21971 if (reg_type
== q_reg
)
21973 gas_assert (R
% 2 == 0);
21974 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21976 else if (reg_type
== d_reg
)
21977 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21979 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21982 static void (*vcx_assign_vec
[3]) (unsigned) = {
21989 vcx_handle_register_arguments (unsigned num_registers
,
21990 enum vcx_reg_type reg_type
)
21993 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21994 for (i
= 0; i
< num_registers
; i
++)
21996 R
= inst
.operands
[i
+1].reg
;
21997 vcx_ensure_register_in_range (R
, reg_type
);
21998 if (num_registers
== 3 && i
> 0)
22001 vcx_assign_vec
[1] (R
* reg_mult
);
22003 vcx_assign_vec
[2] (R
* reg_mult
);
22006 vcx_assign_vec
[i
](R
* reg_mult
);
22011 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22013 if (reg_type
== q_reg
)
22014 if (inst
.cond
> COND_ALWAYS
)
22015 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22017 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22018 else if (inst
.cond
== COND_ALWAYS
)
22019 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22021 inst
.error
= BAD_NOT_IT
;
22025 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22027 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22028 cde_handle_coproc ();
22029 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22030 vcx_handle_register_arguments (num_args
, reg_type
);
22031 vcx_handle_insn_block (reg_type
);
22032 if (reg_type
== q_reg
)
22033 constraint (!mark_feature_used (&mve_ext
),
22034 _("vcx instructions with Q registers require MVE"));
22036 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22037 && mark_feature_used (&armv8m_fp
))
22038 && !mark_feature_used (&mve_ext
),
22039 _("vcx instructions with S or D registers require either MVE"
22040 " or Armv8-M floating point extension."));
22046 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22047 vcx_handle_common_checks (1, rs
);
22049 unsigned imm
= inst
.operands
[2].imm
;
22050 inst
.instruction
|= (imm
& 0x03f);
22051 inst
.instruction
|= (imm
& 0x040) << 1;
22052 inst
.instruction
|= (imm
& 0x780) << 9;
22054 constraint (imm
>= 2048,
22055 _("vcx1 with S or D registers takes immediate within 0-2047"));
22056 inst
.instruction
|= (imm
& 0x800) << 13;
22062 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22063 vcx_handle_common_checks (2, rs
);
22065 unsigned imm
= inst
.operands
[3].imm
;
22066 inst
.instruction
|= (imm
& 0x01) << 4;
22067 inst
.instruction
|= (imm
& 0x02) << 6;
22068 inst
.instruction
|= (imm
& 0x3c) << 14;
22070 constraint (imm
>= 64,
22071 _("vcx2 with S or D registers takes immediate within 0-63"));
22072 inst
.instruction
|= (imm
& 0x40) << 18;
22078 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22079 vcx_handle_common_checks (3, rs
);
22081 unsigned imm
= inst
.operands
[4].imm
;
22082 inst
.instruction
|= (imm
& 0x1) << 4;
22083 inst
.instruction
|= (imm
& 0x6) << 19;
22084 if (rs
!= NS_PQQQI
)
22085 constraint (imm
>= 8,
22086 _("vcx2 with S or D registers takes immediate within 0-7"));
22087 inst
.instruction
|= (imm
& 0x8) << 21;
22090 /* Crypto v1 instructions. */
22092 do_crypto_2op_1 (unsigned elttype
, int op
)
22094 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22096 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22102 NEON_ENCODE (INTEGER
, inst
);
22103 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22104 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22105 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22106 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22108 inst
.instruction
|= op
<< 6;
22111 inst
.instruction
|= 0xfc000000;
22113 inst
.instruction
|= 0xf0000000;
22117 do_crypto_3op_1 (int u
, int op
)
22119 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22121 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22122 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22127 NEON_ENCODE (INTEGER
, inst
);
22128 neon_three_same (1, u
, 8 << op
);
22134 do_crypto_2op_1 (N_8
, 0);
22140 do_crypto_2op_1 (N_8
, 1);
22146 do_crypto_2op_1 (N_8
, 2);
22152 do_crypto_2op_1 (N_8
, 3);
22158 do_crypto_3op_1 (0, 0);
22164 do_crypto_3op_1 (0, 1);
22170 do_crypto_3op_1 (0, 2);
22176 do_crypto_3op_1 (0, 3);
22182 do_crypto_3op_1 (1, 0);
22188 do_crypto_3op_1 (1, 1);
22192 do_sha256su1 (void)
22194 do_crypto_3op_1 (1, 2);
22200 do_crypto_2op_1 (N_32
, -1);
22206 do_crypto_2op_1 (N_32
, 0);
22210 do_sha256su0 (void)
22212 do_crypto_2op_1 (N_32
, 1);
22216 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22218 unsigned int Rd
= inst
.operands
[0].reg
;
22219 unsigned int Rn
= inst
.operands
[1].reg
;
22220 unsigned int Rm
= inst
.operands
[2].reg
;
22222 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22223 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22224 inst
.instruction
|= LOW4 (Rn
) << 16;
22225 inst
.instruction
|= LOW4 (Rm
);
22226 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22227 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22229 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22230 as_warn (UNPRED_REG ("r15"));
22272 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22274 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22275 do_vfp_sp_dp_cvt ();
22276 do_vfp_cond_or_thumb ();
22282 enum neon_shape rs
;
22283 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22284 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22285 if (inst
.operands
[2].isscalar
)
22287 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22288 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22290 inst
.instruction
|= (1 << 25);
22291 int index
= inst
.operands
[2].reg
& 0xf;
22292 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22293 inst
.operands
[2].reg
>>= 4;
22294 constraint (!(inst
.operands
[2].reg
< 16),
22295 _("indexed register must be less than 16"));
22296 neon_three_args (rs
== NS_QQS
);
22297 inst
.instruction
|= (index
<< 5);
22301 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22302 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22303 neon_three_args (rs
== NS_QQQ
);
22310 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22311 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22313 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22314 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22316 neon_three_args (1);
22320 /* Overall per-instruction processing. */
22322 /* We need to be able to fix up arbitrary expressions in some statements.
22323 This is so that we can handle symbols that are an arbitrary distance from
22324 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22325 which returns part of an address in a form which will be valid for
22326 a data instruction. We do this by pushing the expression into a symbol
22327 in the expr_section, and creating a fix for that. */
22330 fix_new_arm (fragS
* frag
,
22344 /* Create an absolute valued symbol, so we have something to
22345 refer to in the object file. Unfortunately for us, gas's
22346 generic expression parsing will already have folded out
22347 any use of .set foo/.type foo %function that may have
22348 been used to set type information of the target location,
22349 that's being specified symbolically. We have to presume
22350 the user knows what they are doing. */
22354 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22356 symbol
= symbol_find_or_make (name
);
22357 S_SET_SEGMENT (symbol
, absolute_section
);
22358 symbol_set_frag (symbol
, &zero_address_frag
);
22359 S_SET_VALUE (symbol
, exp
->X_add_number
);
22360 exp
->X_op
= O_symbol
;
22361 exp
->X_add_symbol
= symbol
;
22362 exp
->X_add_number
= 0;
22368 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22369 (enum bfd_reloc_code_real
) reloc
);
22373 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22374 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22378 /* Mark whether the fix is to a THUMB instruction, or an ARM
22380 new_fix
->tc_fix_data
= thumb_mode
;
22383 /* Create a frg for an instruction requiring relaxation. */
22385 output_relax_insn (void)
22391 /* The size of the instruction is unknown, so tie the debug info to the
22392 start of the instruction. */
22393 dwarf2_emit_insn (0);
22395 switch (inst
.relocs
[0].exp
.X_op
)
22398 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22399 offset
= inst
.relocs
[0].exp
.X_add_number
;
22403 offset
= inst
.relocs
[0].exp
.X_add_number
;
22406 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22410 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22411 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22412 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22415 /* Write a 32-bit thumb instruction to buf. */
22417 put_thumb32_insn (char * buf
, unsigned long insn
)
22419 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22420 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22424 output_inst (const char * str
)
22430 as_bad ("%s -- `%s'", inst
.error
, str
);
22435 output_relax_insn ();
22438 if (inst
.size
== 0)
22441 to
= frag_more (inst
.size
);
22442 /* PR 9814: Record the thumb mode into the current frag so that we know
22443 what type of NOP padding to use, if necessary. We override any previous
22444 setting so that if the mode has changed then the NOPS that we use will
22445 match the encoding of the last instruction in the frag. */
22446 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22448 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22450 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22451 put_thumb32_insn (to
, inst
.instruction
);
22453 else if (inst
.size
> INSN_SIZE
)
22455 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22456 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22457 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22460 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22463 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22465 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22466 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22467 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22468 inst
.relocs
[r
].type
);
22471 dwarf2_emit_insn (inst
.size
);
22475 output_it_inst (int cond
, int mask
, char * to
)
22477 unsigned long instruction
= 0xbf00;
22480 instruction
|= mask
;
22481 instruction
|= cond
<< 4;
22485 to
= frag_more (2);
22487 dwarf2_emit_insn (2);
22491 md_number_to_chars (to
, instruction
, 2);
22496 /* Tag values used in struct asm_opcode's tag field. */
22499 OT_unconditional
, /* Instruction cannot be conditionalized.
22500 The ARM condition field is still 0xE. */
22501 OT_unconditionalF
, /* Instruction cannot be conditionalized
22502 and carries 0xF in its ARM condition field. */
22503 OT_csuffix
, /* Instruction takes a conditional suffix. */
22504 OT_csuffixF
, /* Some forms of the instruction take a scalar
22505 conditional suffix, others place 0xF where the
22506 condition field would be, others take a vector
22507 conditional suffix. */
22508 OT_cinfix3
, /* Instruction takes a conditional infix,
22509 beginning at character index 3. (In
22510 unified mode, it becomes a suffix.) */
22511 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22512 tsts, cmps, cmns, and teqs. */
22513 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22514 character index 3, even in unified mode. Used for
22515 legacy instructions where suffix and infix forms
22516 may be ambiguous. */
22517 OT_csuf_or_in3
, /* Instruction takes either a conditional
22518 suffix or an infix at character index 3. */
22519 OT_odd_infix_unc
, /* This is the unconditional variant of an
22520 instruction that takes a conditional infix
22521 at an unusual position. In unified mode,
22522 this variant will accept a suffix. */
22523 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22524 are the conditional variants of instructions that
22525 take conditional infixes in unusual positions.
22526 The infix appears at character index
22527 (tag - OT_odd_infix_0). These are not accepted
22528 in unified mode. */
22531 /* Subroutine of md_assemble, responsible for looking up the primary
22532 opcode from the mnemonic the user wrote. STR points to the
22533 beginning of the mnemonic.
22535 This is not simply a hash table lookup, because of conditional
22536 variants. Most instructions have conditional variants, which are
22537 expressed with a _conditional affix_ to the mnemonic. If we were
22538 to encode each conditional variant as a literal string in the opcode
22539 table, it would have approximately 20,000 entries.
22541 Most mnemonics take this affix as a suffix, and in unified syntax,
22542 'most' is upgraded to 'all'. However, in the divided syntax, some
22543 instructions take the affix as an infix, notably the s-variants of
22544 the arithmetic instructions. Of those instructions, all but six
22545 have the infix appear after the third character of the mnemonic.
22547 Accordingly, the algorithm for looking up primary opcodes given
22550 1. Look up the identifier in the opcode table.
22551 If we find a match, go to step U.
22553 2. Look up the last two characters of the identifier in the
22554 conditions table. If we find a match, look up the first N-2
22555 characters of the identifier in the opcode table. If we
22556 find a match, go to step CE.
22558 3. Look up the fourth and fifth characters of the identifier in
22559 the conditions table. If we find a match, extract those
22560 characters from the identifier, and look up the remaining
22561 characters in the opcode table. If we find a match, go
22566 U. Examine the tag field of the opcode structure, in case this is
22567 one of the six instructions with its conditional infix in an
22568 unusual place. If it is, the tag tells us where to find the
22569 infix; look it up in the conditions table and set inst.cond
22570 accordingly. Otherwise, this is an unconditional instruction.
22571 Again set inst.cond accordingly. Return the opcode structure.
22573 CE. Examine the tag field to make sure this is an instruction that
22574 should receive a conditional suffix. If it is not, fail.
22575 Otherwise, set inst.cond from the suffix we already looked up,
22576 and return the opcode structure.
22578 CM. Examine the tag field to make sure this is an instruction that
22579 should receive a conditional infix after the third character.
22580 If it is not, fail. Otherwise, undo the edits to the current
22581 line of input and proceed as for case CE. */
22583 static const struct asm_opcode
*
22584 opcode_lookup (char **str
)
22588 const struct asm_opcode
*opcode
;
22589 const struct asm_cond
*cond
;
22592 /* Scan up to the end of the mnemonic, which must end in white space,
22593 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22594 for (base
= end
= *str
; *end
!= '\0'; end
++)
22595 if (*end
== ' ' || *end
== '.')
22601 /* Handle a possible width suffix and/or Neon type suffix. */
22606 /* The .w and .n suffixes are only valid if the unified syntax is in
22608 if (unified_syntax
&& end
[1] == 'w')
22610 else if (unified_syntax
&& end
[1] == 'n')
22615 inst
.vectype
.elems
= 0;
22617 *str
= end
+ offset
;
22619 if (end
[offset
] == '.')
22621 /* See if we have a Neon type suffix (possible in either unified or
22622 non-unified ARM syntax mode). */
22623 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22626 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22632 /* Look for unaffixed or special-case affixed mnemonic. */
22633 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22639 if (opcode
->tag
< OT_odd_infix_0
)
22641 inst
.cond
= COND_ALWAYS
;
22645 if (warn_on_deprecated
&& unified_syntax
)
22646 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22647 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22648 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22651 inst
.cond
= cond
->value
;
22654 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22656 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22658 if (end
- base
< 2)
22661 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22662 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22664 /* If this opcode can not be vector predicated then don't accept it with a
22665 vector predication code. */
22666 if (opcode
&& !opcode
->mayBeVecPred
)
22669 if (!opcode
|| !cond
)
22671 /* Cannot have a conditional suffix on a mnemonic of less than two
22673 if (end
- base
< 3)
22676 /* Look for suffixed mnemonic. */
22678 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22679 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22683 if (opcode
&& cond
)
22686 switch (opcode
->tag
)
22688 case OT_cinfix3_legacy
:
22689 /* Ignore conditional suffixes matched on infix only mnemonics. */
22693 case OT_cinfix3_deprecated
:
22694 case OT_odd_infix_unc
:
22695 if (!unified_syntax
)
22697 /* Fall through. */
22701 case OT_csuf_or_in3
:
22702 inst
.cond
= cond
->value
;
22705 case OT_unconditional
:
22706 case OT_unconditionalF
:
22708 inst
.cond
= cond
->value
;
22711 /* Delayed diagnostic. */
22712 inst
.error
= BAD_COND
;
22713 inst
.cond
= COND_ALWAYS
;
22722 /* Cannot have a usual-position infix on a mnemonic of less than
22723 six characters (five would be a suffix). */
22724 if (end
- base
< 6)
22727 /* Look for infixed mnemonic in the usual position. */
22729 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22733 memcpy (save
, affix
, 2);
22734 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22735 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22737 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22738 memcpy (affix
, save
, 2);
22741 && (opcode
->tag
== OT_cinfix3
22742 || opcode
->tag
== OT_cinfix3_deprecated
22743 || opcode
->tag
== OT_csuf_or_in3
22744 || opcode
->tag
== OT_cinfix3_legacy
))
22747 if (warn_on_deprecated
&& unified_syntax
22748 && (opcode
->tag
== OT_cinfix3
22749 || opcode
->tag
== OT_cinfix3_deprecated
))
22750 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22752 inst
.cond
= cond
->value
;
22759 /* This function generates an initial IT instruction, leaving its block
22760 virtually open for the new instructions. Eventually,
22761 the mask will be updated by now_pred_add_mask () each time
22762 a new instruction needs to be included in the IT block.
22763 Finally, the block is closed with close_automatic_it_block ().
22764 The block closure can be requested either from md_assemble (),
22765 a tencode (), or due to a label hook. */
22768 new_automatic_it_block (int cond
)
22770 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22771 now_pred
.mask
= 0x18;
22772 now_pred
.cc
= cond
;
22773 now_pred
.block_length
= 1;
22774 mapping_state (MAP_THUMB
);
22775 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22776 now_pred
.warn_deprecated
= FALSE
;
22777 now_pred
.insn_cond
= TRUE
;
22780 /* Close an automatic IT block.
22781 See comments in new_automatic_it_block (). */
22784 close_automatic_it_block (void)
22786 now_pred
.mask
= 0x10;
22787 now_pred
.block_length
= 0;
22790 /* Update the mask of the current automatically-generated IT
22791 instruction. See comments in new_automatic_it_block (). */
22794 now_pred_add_mask (int cond
)
22796 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22797 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22798 | ((bitvalue) << (nbit)))
22799 const int resulting_bit
= (cond
& 1);
22801 now_pred
.mask
&= 0xf;
22802 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22804 (5 - now_pred
.block_length
));
22805 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22807 ((5 - now_pred
.block_length
) - 1));
22808 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22811 #undef SET_BIT_VALUE
22814 /* The IT blocks handling machinery is accessed through the these functions:
22815 it_fsm_pre_encode () from md_assemble ()
22816 set_pred_insn_type () optional, from the tencode functions
22817 set_pred_insn_type_last () ditto
22818 in_pred_block () ditto
22819 it_fsm_post_encode () from md_assemble ()
22820 force_automatic_it_block_close () from label handling functions
22823 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22824 initializing the IT insn type with a generic initial value depending
22825 on the inst.condition.
22826 2) During the tencode function, two things may happen:
22827 a) The tencode function overrides the IT insn type by
22828 calling either set_pred_insn_type (type) or
22829 set_pred_insn_type_last ().
22830 b) The tencode function queries the IT block state by
22831 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22833 Both set_pred_insn_type and in_pred_block run the internal FSM state
22834 handling function (handle_pred_state), because: a) setting the IT insn
22835 type may incur in an invalid state (exiting the function),
22836 and b) querying the state requires the FSM to be updated.
22837 Specifically we want to avoid creating an IT block for conditional
22838 branches, so it_fsm_pre_encode is actually a guess and we can't
22839 determine whether an IT block is required until the tencode () routine
22840 has decided what type of instruction this actually it.
22841 Because of this, if set_pred_insn_type and in_pred_block have to be
22842 used, set_pred_insn_type has to be called first.
22844 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22845 that determines the insn IT type depending on the inst.cond code.
22846 When a tencode () routine encodes an instruction that can be
22847 either outside an IT block, or, in the case of being inside, has to be
22848 the last one, set_pred_insn_type_last () will determine the proper
22849 IT instruction type based on the inst.cond code. Otherwise,
22850 set_pred_insn_type can be called for overriding that logic or
22851 for covering other cases.
22853 Calling handle_pred_state () may not transition the IT block state to
22854 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22855 still queried. Instead, if the FSM determines that the state should
22856 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22857 after the tencode () function: that's what it_fsm_post_encode () does.
22859 Since in_pred_block () calls the state handling function to get an
22860 updated state, an error may occur (due to invalid insns combination).
22861 In that case, inst.error is set.
22862 Therefore, inst.error has to be checked after the execution of
22863 the tencode () routine.
22865 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22866 any pending state change (if any) that didn't take place in
22867 handle_pred_state () as explained above. */
22870 it_fsm_pre_encode (void)
22872 if (inst
.cond
!= COND_ALWAYS
)
22873 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22875 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22877 now_pred
.state_handled
= 0;
22880 /* IT state FSM handling function. */
22881 /* MVE instructions and non-MVE instructions are handled differently because of
22882 the introduction of VPT blocks.
22883 Specifications say that any non-MVE instruction inside a VPT block is
22884 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22885 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22886 few exceptions we have MVE_UNPREDICABLE_INSN.
22887 The error messages provided depending on the different combinations possible
22888 are described in the cases below:
22889 For 'most' MVE instructions:
22890 1) In an IT block, with an IT code: syntax error
22891 2) In an IT block, with a VPT code: error: must be in a VPT block
22892 3) In an IT block, with no code: warning: UNPREDICTABLE
22893 4) In a VPT block, with an IT code: syntax error
22894 5) In a VPT block, with a VPT code: OK!
22895 6) In a VPT block, with no code: error: missing code
22896 7) Outside a pred block, with an IT code: error: syntax error
22897 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22898 9) Outside a pred block, with no code: OK!
22899 For non-MVE instructions:
22900 10) In an IT block, with an IT code: OK!
22901 11) In an IT block, with a VPT code: syntax error
22902 12) In an IT block, with no code: error: missing code
22903 13) In a VPT block, with an IT code: error: should be in an IT block
22904 14) In a VPT block, with a VPT code: syntax error
22905 15) In a VPT block, with no code: UNPREDICTABLE
22906 16) Outside a pred block, with an IT code: error: should be in an IT block
22907 17) Outside a pred block, with a VPT code: syntax error
22908 18) Outside a pred block, with no code: OK!
22913 handle_pred_state (void)
22915 now_pred
.state_handled
= 1;
22916 now_pred
.insn_cond
= FALSE
;
22918 switch (now_pred
.state
)
22920 case OUTSIDE_PRED_BLOCK
:
22921 switch (inst
.pred_insn_type
)
22923 case MVE_UNPREDICABLE_INSN
:
22924 case MVE_OUTSIDE_PRED_INSN
:
22925 if (inst
.cond
< COND_ALWAYS
)
22927 /* Case 7: Outside a pred block, with an IT code: error: syntax
22929 inst
.error
= BAD_SYNTAX
;
22932 /* Case 9: Outside a pred block, with no code: OK! */
22934 case OUTSIDE_PRED_INSN
:
22935 if (inst
.cond
> COND_ALWAYS
)
22937 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22939 inst
.error
= BAD_SYNTAX
;
22942 /* Case 18: Outside a pred block, with no code: OK! */
22945 case INSIDE_VPT_INSN
:
22946 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22948 inst
.error
= BAD_OUT_VPT
;
22951 case INSIDE_IT_INSN
:
22952 case INSIDE_IT_LAST_INSN
:
22953 if (inst
.cond
< COND_ALWAYS
)
22955 /* Case 16: Outside a pred block, with an IT code: error: should
22956 be in an IT block. */
22957 if (thumb_mode
== 0)
22960 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22961 as_tsktsk (_("Warning: conditional outside an IT block"\
22966 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22967 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22969 /* Automatically generate the IT instruction. */
22970 new_automatic_it_block (inst
.cond
);
22971 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22972 close_automatic_it_block ();
22976 inst
.error
= BAD_OUT_IT
;
22982 else if (inst
.cond
> COND_ALWAYS
)
22984 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22986 inst
.error
= BAD_SYNTAX
;
22991 case IF_INSIDE_IT_LAST_INSN
:
22992 case NEUTRAL_IT_INSN
:
22996 if (inst
.cond
!= COND_ALWAYS
)
22997 first_error (BAD_SYNTAX
);
22998 now_pred
.state
= MANUAL_PRED_BLOCK
;
22999 now_pred
.block_length
= 0;
23000 now_pred
.type
= VECTOR_PRED
;
23004 now_pred
.state
= MANUAL_PRED_BLOCK
;
23005 now_pred
.block_length
= 0;
23006 now_pred
.type
= SCALAR_PRED
;
23011 case AUTOMATIC_PRED_BLOCK
:
23012 /* Three things may happen now:
23013 a) We should increment current it block size;
23014 b) We should close current it block (closing insn or 4 insns);
23015 c) We should close current it block and start a new one (due
23016 to incompatible conditions or
23017 4 insns-length block reached). */
23019 switch (inst
.pred_insn_type
)
23021 case INSIDE_VPT_INSN
:
23023 case MVE_UNPREDICABLE_INSN
:
23024 case MVE_OUTSIDE_PRED_INSN
:
23026 case OUTSIDE_PRED_INSN
:
23027 /* The closure of the block shall happen immediately,
23028 so any in_pred_block () call reports the block as closed. */
23029 force_automatic_it_block_close ();
23032 case INSIDE_IT_INSN
:
23033 case INSIDE_IT_LAST_INSN
:
23034 case IF_INSIDE_IT_LAST_INSN
:
23035 now_pred
.block_length
++;
23037 if (now_pred
.block_length
> 4
23038 || !now_pred_compatible (inst
.cond
))
23040 force_automatic_it_block_close ();
23041 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23042 new_automatic_it_block (inst
.cond
);
23046 now_pred
.insn_cond
= TRUE
;
23047 now_pred_add_mask (inst
.cond
);
23050 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23051 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23052 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23053 close_automatic_it_block ();
23057 case NEUTRAL_IT_INSN
:
23058 now_pred
.block_length
++;
23059 now_pred
.insn_cond
= TRUE
;
23061 if (now_pred
.block_length
> 4)
23062 force_automatic_it_block_close ();
23064 now_pred_add_mask (now_pred
.cc
& 1);
23068 close_automatic_it_block ();
23069 now_pred
.state
= MANUAL_PRED_BLOCK
;
23074 case MANUAL_PRED_BLOCK
:
23078 if (now_pred
.type
== SCALAR_PRED
)
23080 /* Check conditional suffixes. */
23081 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23082 now_pred
.mask
<<= 1;
23083 now_pred
.mask
&= 0x1f;
23084 is_last
= (now_pred
.mask
== 0x10);
23088 now_pred
.cc
^= (now_pred
.mask
>> 4);
23089 cond
= now_pred
.cc
+ 0xf;
23090 now_pred
.mask
<<= 1;
23091 now_pred
.mask
&= 0x1f;
23092 is_last
= now_pred
.mask
== 0x10;
23094 now_pred
.insn_cond
= TRUE
;
23096 switch (inst
.pred_insn_type
)
23098 case OUTSIDE_PRED_INSN
:
23099 if (now_pred
.type
== SCALAR_PRED
)
23101 if (inst
.cond
== COND_ALWAYS
)
23103 /* Case 12: In an IT block, with no code: error: missing
23105 inst
.error
= BAD_NOT_IT
;
23108 else if (inst
.cond
> COND_ALWAYS
)
23110 /* Case 11: In an IT block, with a VPT code: syntax error.
23112 inst
.error
= BAD_SYNTAX
;
23115 else if (thumb_mode
)
23117 /* This is for some special cases where a non-MVE
23118 instruction is not allowed in an IT block, such as cbz,
23119 but are put into one with a condition code.
23120 You could argue this should be a syntax error, but we
23121 gave the 'not allowed in IT block' diagnostic in the
23122 past so we will keep doing so. */
23123 inst
.error
= BAD_NOT_IT
;
23130 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23131 as_tsktsk (MVE_NOT_VPT
);
23134 case MVE_OUTSIDE_PRED_INSN
:
23135 if (now_pred
.type
== SCALAR_PRED
)
23137 if (inst
.cond
== COND_ALWAYS
)
23139 /* Case 3: In an IT block, with no code: warning:
23141 as_tsktsk (MVE_NOT_IT
);
23144 else if (inst
.cond
< COND_ALWAYS
)
23146 /* Case 1: In an IT block, with an IT code: syntax error.
23148 inst
.error
= BAD_SYNTAX
;
23156 if (inst
.cond
< COND_ALWAYS
)
23158 /* Case 4: In a VPT block, with an IT code: syntax error.
23160 inst
.error
= BAD_SYNTAX
;
23163 else if (inst
.cond
== COND_ALWAYS
)
23165 /* Case 6: In a VPT block, with no code: error: missing
23167 inst
.error
= BAD_NOT_VPT
;
23175 case MVE_UNPREDICABLE_INSN
:
23176 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23178 case INSIDE_IT_INSN
:
23179 if (inst
.cond
> COND_ALWAYS
)
23181 /* Case 11: In an IT block, with a VPT code: syntax error. */
23182 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23183 inst
.error
= BAD_SYNTAX
;
23186 else if (now_pred
.type
== SCALAR_PRED
)
23188 /* Case 10: In an IT block, with an IT code: OK! */
23189 if (cond
!= inst
.cond
)
23191 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23198 /* Case 13: In a VPT block, with an IT code: error: should be
23200 inst
.error
= BAD_OUT_IT
;
23205 case INSIDE_VPT_INSN
:
23206 if (now_pred
.type
== SCALAR_PRED
)
23208 /* Case 2: In an IT block, with a VPT code: error: must be in a
23210 inst
.error
= BAD_OUT_VPT
;
23213 /* Case 5: In a VPT block, with a VPT code: OK! */
23214 else if (cond
!= inst
.cond
)
23216 inst
.error
= BAD_VPT_COND
;
23220 case INSIDE_IT_LAST_INSN
:
23221 case IF_INSIDE_IT_LAST_INSN
:
23222 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23224 /* Case 4: In a VPT block, with an IT code: syntax error. */
23225 /* Case 11: In an IT block, with a VPT code: syntax error. */
23226 inst
.error
= BAD_SYNTAX
;
23229 else if (cond
!= inst
.cond
)
23231 inst
.error
= BAD_IT_COND
;
23236 inst
.error
= BAD_BRANCH
;
23241 case NEUTRAL_IT_INSN
:
23242 /* The BKPT instruction is unconditional even in a IT or VPT
23247 if (now_pred
.type
== SCALAR_PRED
)
23249 inst
.error
= BAD_IT_IT
;
23252 /* fall through. */
23254 if (inst
.cond
== COND_ALWAYS
)
23256 /* Executing a VPT/VPST instruction inside an IT block or a
23257 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23259 if (now_pred
.type
== SCALAR_PRED
)
23260 as_tsktsk (MVE_NOT_IT
);
23262 as_tsktsk (MVE_NOT_VPT
);
23267 /* VPT/VPST do not accept condition codes. */
23268 inst
.error
= BAD_SYNTAX
;
23279 struct depr_insn_mask
23281 unsigned long pattern
;
23282 unsigned long mask
;
23283 const char* description
;
23286 /* List of 16-bit instruction patterns deprecated in an IT block in
23288 static const struct depr_insn_mask depr_it_insns
[] = {
23289 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23290 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23291 { 0xa000, 0xb800, N_("ADR") },
23292 { 0x4800, 0xf800, N_("Literal loads") },
23293 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23294 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23295 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23296 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23297 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23302 it_fsm_post_encode (void)
23306 if (!now_pred
.state_handled
)
23307 handle_pred_state ();
23309 if (now_pred
.insn_cond
23310 && warn_on_restrict_it
23311 && !now_pred
.warn_deprecated
23312 && warn_on_deprecated
23313 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23314 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23317 if (inst
.instruction
>= 0x10000)
23319 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23320 "performance deprecated in ARMv8-A and ARMv8-R"));
23321 now_pred
.warn_deprecated
= TRUE
;
23325 const struct depr_insn_mask
*p
= depr_it_insns
;
23327 while (p
->mask
!= 0)
23329 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23331 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23332 "instructions of the following class are "
23333 "performance deprecated in ARMv8-A and "
23334 "ARMv8-R: %s"), p
->description
);
23335 now_pred
.warn_deprecated
= TRUE
;
23343 if (now_pred
.block_length
> 1)
23345 as_tsktsk (_("IT blocks containing more than one conditional "
23346 "instruction are performance deprecated in ARMv8-A and "
23348 now_pred
.warn_deprecated
= TRUE
;
23352 is_last
= (now_pred
.mask
== 0x10);
23355 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23361 force_automatic_it_block_close (void)
23363 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23365 close_automatic_it_block ();
23366 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23372 in_pred_block (void)
23374 if (!now_pred
.state_handled
)
23375 handle_pred_state ();
23377 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23380 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23381 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23382 here, hence the "known" in the function name. */
23385 known_t32_only_insn (const struct asm_opcode
*opcode
)
23387 /* Original Thumb-1 wide instruction. */
23388 if (opcode
->tencode
== do_t_blx
23389 || opcode
->tencode
== do_t_branch23
23390 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23391 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23394 /* Wide-only instruction added to ARMv8-M Baseline. */
23395 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23396 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23397 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23398 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23404 /* Whether wide instruction variant can be used if available for a valid OPCODE
23408 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23410 if (known_t32_only_insn (opcode
))
23413 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23414 of variant T3 of B.W is checked in do_t_branch. */
23415 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23416 && opcode
->tencode
== do_t_branch
)
23419 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23420 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23421 && opcode
->tencode
== do_t_mov_cmp
23422 /* Make sure CMP instruction is not affected. */
23423 && opcode
->aencode
== do_mov
)
23426 /* Wide instruction variants of all instructions with narrow *and* wide
23427 variants become available with ARMv6t2. Other opcodes are either
23428 narrow-only or wide-only and are thus available if OPCODE is valid. */
23429 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23432 /* OPCODE with narrow only instruction variant or wide variant not
23438 md_assemble (char *str
)
23441 const struct asm_opcode
* opcode
;
23443 /* Align the previous label if needed. */
23444 if (last_label_seen
!= NULL
)
23446 symbol_set_frag (last_label_seen
, frag_now
);
23447 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23448 S_SET_SEGMENT (last_label_seen
, now_seg
);
23451 memset (&inst
, '\0', sizeof (inst
));
23453 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23454 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23456 opcode
= opcode_lookup (&p
);
23459 /* It wasn't an instruction, but it might be a register alias of
23460 the form alias .req reg, or a Neon .dn/.qn directive. */
23461 if (! create_register_alias (str
, p
)
23462 && ! create_neon_reg_alias (str
, p
))
23463 as_bad (_("bad instruction `%s'"), str
);
23468 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23469 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23471 /* The value which unconditional instructions should have in place of the
23472 condition field. */
23473 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1u;
23477 arm_feature_set variant
;
23479 variant
= cpu_variant
;
23480 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23481 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23482 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23483 /* Check that this instruction is supported for this CPU. */
23484 if (!opcode
->tvariant
23485 || (thumb_mode
== 1
23486 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23488 if (opcode
->tencode
== do_t_swi
)
23489 as_bad (_("SVC is not permitted on this architecture"));
23491 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23494 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23495 && opcode
->tencode
!= do_t_branch
)
23497 as_bad (_("Thumb does not support conditional execution"));
23501 /* Two things are addressed here:
23502 1) Implicit require narrow instructions on Thumb-1.
23503 This avoids relaxation accidentally introducing Thumb-2
23505 2) Reject wide instructions in non Thumb-2 cores.
23507 Only instructions with narrow and wide variants need to be handled
23508 but selecting all non wide-only instructions is easier. */
23509 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23510 && !t32_insn_ok (variant
, opcode
))
23512 if (inst
.size_req
== 0)
23514 else if (inst
.size_req
== 4)
23516 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23517 as_bad (_("selected processor does not support 32bit wide "
23518 "variant of instruction `%s'"), str
);
23520 as_bad (_("selected processor does not support `%s' in "
23521 "Thumb-2 mode"), str
);
23526 inst
.instruction
= opcode
->tvalue
;
23528 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23530 /* Prepare the pred_insn_type for those encodings that don't set
23532 it_fsm_pre_encode ();
23534 opcode
->tencode ();
23536 it_fsm_post_encode ();
23539 if (!(inst
.error
|| inst
.relax
))
23541 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23542 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23543 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23545 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23550 /* Something has gone badly wrong if we try to relax a fixed size
23552 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23554 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23555 *opcode
->tvariant
);
23556 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23557 set those bits when Thumb-2 32-bit instructions are seen. The impact
23558 of relaxable instructions will be considered later after we finish all
23560 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23561 variant
= arm_arch_none
;
23563 variant
= cpu_variant
;
23564 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23565 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23568 check_neon_suffixes
;
23572 mapping_state (MAP_THUMB
);
23575 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23579 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23580 is_bx
= (opcode
->aencode
== do_bx
);
23582 /* Check that this instruction is supported for this CPU. */
23583 if (!(is_bx
&& fix_v4bx
)
23584 && !(opcode
->avariant
&&
23585 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23587 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23592 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23596 inst
.instruction
= opcode
->avalue
;
23597 if (opcode
->tag
== OT_unconditionalF
)
23598 inst
.instruction
|= 0xFU
<< 28;
23600 inst
.instruction
|= inst
.cond
<< 28;
23601 inst
.size
= INSN_SIZE
;
23602 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23604 it_fsm_pre_encode ();
23605 opcode
->aencode ();
23606 it_fsm_post_encode ();
23608 /* Arm mode bx is marked as both v4T and v5 because it's still required
23609 on a hypothetical non-thumb v5 core. */
23611 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23613 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23614 *opcode
->avariant
);
23616 check_neon_suffixes
;
23620 mapping_state (MAP_ARM
);
23625 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23633 check_pred_blocks_finished (void)
23638 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23639 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23640 == MANUAL_PRED_BLOCK
)
23642 if (now_pred
.type
== SCALAR_PRED
)
23643 as_warn (_("section '%s' finished with an open IT block."),
23646 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23650 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23652 if (now_pred
.type
== SCALAR_PRED
)
23653 as_warn (_("file finished with an open IT block."));
23655 as_warn (_("file finished with an open VPT/VPST block."));
23660 /* Various frobbings of labels and their addresses. */
23663 arm_start_line_hook (void)
23665 last_label_seen
= NULL
;
23669 arm_frob_label (symbolS
* sym
)
23671 last_label_seen
= sym
;
23673 ARM_SET_THUMB (sym
, thumb_mode
);
23675 #if defined OBJ_COFF || defined OBJ_ELF
23676 ARM_SET_INTERWORK (sym
, support_interwork
);
23679 force_automatic_it_block_close ();
23681 /* Note - do not allow local symbols (.Lxxx) to be labelled
23682 as Thumb functions. This is because these labels, whilst
23683 they exist inside Thumb code, are not the entry points for
23684 possible ARM->Thumb calls. Also, these labels can be used
23685 as part of a computed goto or switch statement. eg gcc
23686 can generate code that looks like this:
23688 ldr r2, [pc, .Laaa]
23698 The first instruction loads the address of the jump table.
23699 The second instruction converts a table index into a byte offset.
23700 The third instruction gets the jump address out of the table.
23701 The fourth instruction performs the jump.
23703 If the address stored at .Laaa is that of a symbol which has the
23704 Thumb_Func bit set, then the linker will arrange for this address
23705 to have the bottom bit set, which in turn would mean that the
23706 address computation performed by the third instruction would end
23707 up with the bottom bit set. Since the ARM is capable of unaligned
23708 word loads, the instruction would then load the incorrect address
23709 out of the jump table, and chaos would ensue. */
23710 if (label_is_thumb_function_name
23711 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23712 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23714 /* When the address of a Thumb function is taken the bottom
23715 bit of that address should be set. This will allow
23716 interworking between Arm and Thumb functions to work
23719 THUMB_SET_FUNC (sym
, 1);
23721 label_is_thumb_function_name
= FALSE
;
23724 dwarf2_emit_label (sym
);
23728 arm_data_in_code (void)
23730 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23732 *input_line_pointer
= '/';
23733 input_line_pointer
+= 5;
23734 *input_line_pointer
= 0;
23742 arm_canonicalize_symbol_name (char * name
)
23746 if (thumb_mode
&& (len
= strlen (name
)) > 5
23747 && streq (name
+ len
- 5, "/data"))
23748 *(name
+ len
- 5) = 0;
23753 /* Table of all register names defined by default. The user can
23754 define additional names with .req. Note that all register names
23755 should appear in both upper and lowercase variants. Some registers
23756 also have mixed-case names. */
23758 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23759 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23760 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23761 #define REGSET(p,t) \
23762 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23763 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23764 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23765 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23766 #define REGSETH(p,t) \
23767 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23768 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23769 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23770 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23771 #define REGSET2(p,t) \
23772 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23773 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23774 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23775 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23776 #define SPLRBANK(base,bank,t) \
23777 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23778 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23779 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23780 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23781 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23782 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23784 static const struct reg_entry reg_names
[] =
23786 /* ARM integer registers. */
23787 REGSET(r
, RN
), REGSET(R
, RN
),
23789 /* ATPCS synonyms. */
23790 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23791 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23792 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23794 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23795 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23796 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23798 /* Well-known aliases. */
23799 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23800 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23802 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23803 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23805 /* Defining the new Zero register from ARMv8.1-M. */
23809 /* Coprocessor numbers. */
23810 REGSET(p
, CP
), REGSET(P
, CP
),
23812 /* Coprocessor register numbers. The "cr" variants are for backward
23814 REGSET(c
, CN
), REGSET(C
, CN
),
23815 REGSET(cr
, CN
), REGSET(CR
, CN
),
23817 /* ARM banked registers. */
23818 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23819 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23820 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23821 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23822 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23823 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23824 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23826 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23827 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23828 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23829 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23830 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23831 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23832 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23833 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23835 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23836 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23837 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23838 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23839 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23840 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23841 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23842 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23843 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23845 /* FPA registers. */
23846 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23847 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23849 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23850 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23852 /* VFP SP registers. */
23853 REGSET(s
,VFS
), REGSET(S
,VFS
),
23854 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23856 /* VFP DP Registers. */
23857 REGSET(d
,VFD
), REGSET(D
,VFD
),
23858 /* Extra Neon DP registers. */
23859 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23861 /* Neon QP registers. */
23862 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23864 /* VFP control registers. */
23865 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23866 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23867 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23868 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23869 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23870 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23871 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23872 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23873 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23874 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23875 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23877 /* Maverick DSP coprocessor registers. */
23878 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23879 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23881 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23882 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23883 REGDEF(dspsc
,0,DSPSC
),
23885 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23886 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23887 REGDEF(DSPSC
,0,DSPSC
),
23889 /* iWMMXt data registers - p0, c0-15. */
23890 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23892 /* iWMMXt control registers - p1, c0-3. */
23893 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23894 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23895 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23896 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23898 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23899 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23900 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23901 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23902 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23904 /* XScale accumulator registers. */
23905 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23911 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23912 within psr_required_here. */
23913 static const struct asm_psr psrs
[] =
23915 /* Backward compatibility notation. Note that "all" is no longer
23916 truly all possible PSR bits. */
23917 {"all", PSR_c
| PSR_f
},
23921 /* Individual flags. */
23927 /* Combinations of flags. */
23928 {"fs", PSR_f
| PSR_s
},
23929 {"fx", PSR_f
| PSR_x
},
23930 {"fc", PSR_f
| PSR_c
},
23931 {"sf", PSR_s
| PSR_f
},
23932 {"sx", PSR_s
| PSR_x
},
23933 {"sc", PSR_s
| PSR_c
},
23934 {"xf", PSR_x
| PSR_f
},
23935 {"xs", PSR_x
| PSR_s
},
23936 {"xc", PSR_x
| PSR_c
},
23937 {"cf", PSR_c
| PSR_f
},
23938 {"cs", PSR_c
| PSR_s
},
23939 {"cx", PSR_c
| PSR_x
},
23940 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23941 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23942 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23943 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23944 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23945 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23946 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23947 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23948 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23949 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23950 {"scf", PSR_s
| PSR_c
| PSR_f
},
23951 {"scx", PSR_s
| PSR_c
| PSR_x
},
23952 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23953 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23954 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23955 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23956 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23957 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23958 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23959 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23960 {"csf", PSR_c
| PSR_s
| PSR_f
},
23961 {"csx", PSR_c
| PSR_s
| PSR_x
},
23962 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23963 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23964 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23965 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23966 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23967 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23968 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23969 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23970 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23971 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23972 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23973 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23974 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23975 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23976 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23977 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23978 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23979 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23980 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23981 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23982 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23983 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23984 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23985 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23986 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23987 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23990 /* Table of V7M psr names. */
23991 static const struct asm_psr v7m_psrs
[] =
23993 {"apsr", 0x0 }, {"APSR", 0x0 },
23994 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23995 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23996 {"psr", 0x3 }, {"PSR", 0x3 },
23997 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23998 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23999 {"epsr", 0x6 }, {"EPSR", 0x6 },
24000 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
24001 {"msp", 0x8 }, {"MSP", 0x8 },
24002 {"psp", 0x9 }, {"PSP", 0x9 },
24003 {"msplim", 0xa }, {"MSPLIM", 0xa },
24004 {"psplim", 0xb }, {"PSPLIM", 0xb },
24005 {"primask", 0x10}, {"PRIMASK", 0x10},
24006 {"basepri", 0x11}, {"BASEPRI", 0x11},
24007 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
24008 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
24009 {"control", 0x14}, {"CONTROL", 0x14},
24010 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
24011 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24012 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24013 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24014 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24015 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24016 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24017 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24018 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24021 /* Table of all shift-in-operand names. */
24022 static const struct asm_shift_name shift_names
[] =
24024 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24025 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24026 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24027 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24028 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24029 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24030 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24033 /* Table of all explicit relocation names. */
24035 static struct reloc_entry reloc_names
[] =
24037 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24038 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24039 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24040 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24041 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24042 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24043 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24044 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24045 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24046 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24047 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24048 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24049 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24050 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24051 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24052 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24053 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24054 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24055 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24056 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24057 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24058 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24059 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24060 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24061 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24062 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24063 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24067 /* Table of all conditional affixes. */
24068 static const struct asm_cond conds
[] =
24072 {"cs", 0x2}, {"hs", 0x2},
24073 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24086 static const struct asm_cond vconds
[] =
24092 #define UL_BARRIER(L,U,CODE,FEAT) \
24093 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24094 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24096 static struct asm_barrier_opt barrier_opt_names
[] =
24098 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24099 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24101 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24102 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24103 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24104 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24105 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24106 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24107 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24108 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24109 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24110 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24111 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24112 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24113 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24118 /* Table of ARM-format instructions. */
24120 /* Macros for gluing together operand strings. N.B. In all cases
24121 other than OPS0, the trailing OP_stop comes from default
24122 zero-initialization of the unspecified elements of the array. */
24123 #define OPS0() { OP_stop, }
24124 #define OPS1(a) { OP_##a, }
24125 #define OPS2(a,b) { OP_##a,OP_##b, }
24126 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24127 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24128 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24129 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24131 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24132 This is useful when mixing operands for ARM and THUMB, i.e. using the
24133 MIX_ARM_THUMB_OPERANDS macro.
24134 In order to use these macros, prefix the number of operands with _
24136 #define OPS_1(a) { a, }
24137 #define OPS_2(a,b) { a,b, }
24138 #define OPS_3(a,b,c) { a,b,c, }
24139 #define OPS_4(a,b,c,d) { a,b,c,d, }
24140 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24141 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24143 /* These macros abstract out the exact format of the mnemonic table and
24144 save some repeated characters. */
24146 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24147 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24148 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24149 THUMB_VARIANT, do_##ae, do_##te, 0 }
24151 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24152 a T_MNEM_xyz enumerator. */
24153 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24154 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24155 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24156 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24158 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24159 infix after the third character. */
24160 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24161 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24162 THUMB_VARIANT, do_##ae, do_##te, 0 }
24163 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24164 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24165 THUMB_VARIANT, do_##ae, do_##te, 0 }
24166 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24167 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24168 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24169 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24170 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24171 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24172 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24173 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24175 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24176 field is still 0xE. Many of the Thumb variants can be executed
24177 conditionally, so this is checked separately. */
24178 #define TUE(mnem, op, top, nops, ops, ae, te) \
24179 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24180 THUMB_VARIANT, do_##ae, do_##te, 0 }
24182 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24183 Used by mnemonics that have very minimal differences in the encoding for
24184 ARM and Thumb variants and can be handled in a common function. */
24185 #define TUEc(mnem, op, top, nops, ops, en) \
24186 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24187 THUMB_VARIANT, do_##en, do_##en, 0 }
24189 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24190 condition code field. */
24191 #define TUF(mnem, op, top, nops, ops, ae, te) \
24192 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24193 THUMB_VARIANT, do_##ae, do_##te, 0 }
24195 /* ARM-only variants of all the above. */
24196 #define CE(mnem, op, nops, ops, ae) \
24197 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24199 #define C3(mnem, op, nops, ops, ae) \
24200 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24202 /* Thumb-only variants of TCE and TUE. */
24203 #define ToC(mnem, top, nops, ops, te) \
24204 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24207 #define ToU(mnem, top, nops, ops, te) \
24208 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24211 /* T_MNEM_xyz enumerator variants of ToC. */
24212 #define toC(mnem, top, nops, ops, te) \
24213 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24216 /* T_MNEM_xyz enumerator variants of ToU. */
24217 #define toU(mnem, top, nops, ops, te) \
24218 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24221 /* Legacy mnemonics that always have conditional infix after the third
24223 #define CL(mnem, op, nops, ops, ae) \
24224 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24225 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24227 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24228 #define cCE(mnem, op, nops, ops, ae) \
24229 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24231 /* mov instructions that are shared between coprocessor and MVE. */
24232 #define mcCE(mnem, op, nops, ops, ae) \
24233 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24235 /* Legacy coprocessor instructions where conditional infix and conditional
24236 suffix are ambiguous. For consistency this includes all FPA instructions,
24237 not just the potentially ambiguous ones. */
24238 #define cCL(mnem, op, nops, ops, ae) \
24239 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24240 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24242 /* Coprocessor, takes either a suffix or a position-3 infix
24243 (for an FPA corner case). */
24244 #define C3E(mnem, op, nops, ops, ae) \
24245 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24246 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24248 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24249 { m1 #m2 m3, OPS##nops ops, \
24250 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24251 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24253 #define CM(m1, m2, op, nops, ops, ae) \
24254 xCM_ (m1, , m2, op, nops, ops, ae), \
24255 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24256 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24257 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24258 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24259 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24260 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24261 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24262 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24263 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24264 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24265 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24266 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24267 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24268 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24269 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24270 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24271 xCM_ (m1, le, m2, op, nops, ops, ae), \
24272 xCM_ (m1, al, m2, op, nops, ops, ae)
24274 #define UE(mnem, op, nops, ops, ae) \
24275 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24277 #define UF(mnem, op, nops, ops, ae) \
24278 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24280 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24281 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24282 use the same encoding function for each. */
24283 #define NUF(mnem, op, nops, ops, enc) \
24284 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24285 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24287 /* Neon data processing, version which indirects through neon_enc_tab for
24288 the various overloaded versions of opcodes. */
24289 #define nUF(mnem, op, nops, ops, enc) \
24290 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24291 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24293 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24295 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24296 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24297 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24299 #define NCE(mnem, op, nops, ops, enc) \
24300 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24302 #define NCEF(mnem, op, nops, ops, enc) \
24303 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24305 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24306 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24307 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24308 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24310 #define nCE(mnem, op, nops, ops, enc) \
24311 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24313 #define nCEF(mnem, op, nops, ops, enc) \
24314 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24317 #define mCEF(mnem, op, nops, ops, enc) \
24318 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24319 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24322 /* nCEF but for MVE predicated instructions. */
24323 #define mnCEF(mnem, op, nops, ops, enc) \
24324 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24326 /* nCE but for MVE predicated instructions. */
24327 #define mnCE(mnem, op, nops, ops, enc) \
24328 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24330 /* NUF but for potentially MVE predicated instructions. */
24331 #define MNUF(mnem, op, nops, ops, enc) \
24332 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24333 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24335 /* nUF but for potentially MVE predicated instructions. */
24336 #define mnUF(mnem, op, nops, ops, enc) \
24337 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24338 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24340 /* ToC but for potentially MVE predicated instructions. */
24341 #define mToC(mnem, top, nops, ops, te) \
24342 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24345 /* NCE but for MVE predicated instructions. */
24346 #define MNCE(mnem, op, nops, ops, enc) \
24347 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24349 /* NCEF but for MVE predicated instructions. */
24350 #define MNCEF(mnem, op, nops, ops, enc) \
24351 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24354 static const struct asm_opcode insns
[] =
24356 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24357 #define THUMB_VARIANT & arm_ext_v4t
24358 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24360 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24361 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24362 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24363 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24364 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24365 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24366 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24367 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24368 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24369 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24370 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24371 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24372 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24373 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24375 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24376 for setting PSR flag bits. They are obsolete in V6 and do not
24377 have Thumb equivalents. */
24378 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24379 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24380 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24381 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24382 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24383 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24384 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24385 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24386 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24388 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24389 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24390 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24391 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24393 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24394 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24395 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24397 OP_ADDRGLDR
),ldst
, t_ldst
),
24398 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24400 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24401 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24402 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24403 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24404 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24405 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24407 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24408 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24411 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24412 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24413 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24414 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24416 /* Thumb-compatibility pseudo ops. */
24417 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24418 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24419 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24420 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24421 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24422 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24423 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24424 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24425 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24426 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24427 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24428 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24430 /* These may simplify to neg. */
24431 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24432 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24434 #undef THUMB_VARIANT
24435 #define THUMB_VARIANT & arm_ext_os
24437 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24438 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24440 #undef THUMB_VARIANT
24441 #define THUMB_VARIANT & arm_ext_v6
24443 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24445 /* V1 instructions with no Thumb analogue prior to V6T2. */
24446 #undef THUMB_VARIANT
24447 #define THUMB_VARIANT & arm_ext_v6t2
24449 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24450 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24451 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24453 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24454 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24455 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24456 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24458 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24459 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24461 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24462 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24464 /* V1 instructions with no Thumb analogue at all. */
24465 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24466 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24468 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24469 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24470 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24471 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24472 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24473 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24474 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24475 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24478 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24479 #undef THUMB_VARIANT
24480 #define THUMB_VARIANT & arm_ext_v4t
24482 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24483 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24485 #undef THUMB_VARIANT
24486 #define THUMB_VARIANT & arm_ext_v6t2
24488 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24489 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24491 /* Generic coprocessor instructions. */
24492 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24493 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24494 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24495 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24496 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24497 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24498 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24501 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24503 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24504 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24507 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24508 #undef THUMB_VARIANT
24509 #define THUMB_VARIANT & arm_ext_msr
24511 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24512 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24515 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24516 #undef THUMB_VARIANT
24517 #define THUMB_VARIANT & arm_ext_v6t2
24519 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24520 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24521 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24522 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24523 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24524 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24525 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24526 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24529 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24530 #undef THUMB_VARIANT
24531 #define THUMB_VARIANT & arm_ext_v4t
24533 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24534 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24535 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24536 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24537 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24538 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24541 #define ARM_VARIANT & arm_ext_v4t_5
24543 /* ARM Architecture 4T. */
24544 /* Note: bx (and blx) are required on V5, even if the processor does
24545 not support Thumb. */
24546 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24549 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24550 #undef THUMB_VARIANT
24551 #define THUMB_VARIANT & arm_ext_v5t
24553 /* Note: blx has 2 variants; the .value coded here is for
24554 BLX(2). Only this variant has conditional execution. */
24555 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24556 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24558 #undef THUMB_VARIANT
24559 #define THUMB_VARIANT & arm_ext_v6t2
24561 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24562 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24563 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24564 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24565 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24566 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24567 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24568 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24571 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24572 #undef THUMB_VARIANT
24573 #define THUMB_VARIANT & arm_ext_v5exp
24575 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24576 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24577 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24578 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24580 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24581 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24583 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24584 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24585 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24586 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24588 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24589 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24590 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24591 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24593 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24594 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24596 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24597 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24598 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24599 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24602 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24603 #undef THUMB_VARIANT
24604 #define THUMB_VARIANT & arm_ext_v6t2
24606 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24607 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24609 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24610 ADDRGLDRS
), ldrd
, t_ldstd
),
24612 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24613 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24616 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24618 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24621 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24622 #undef THUMB_VARIANT
24623 #define THUMB_VARIANT & arm_ext_v6
24625 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24626 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24627 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24628 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24629 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24630 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24631 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24632 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24633 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24634 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24636 #undef THUMB_VARIANT
24637 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24639 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24640 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24642 #undef THUMB_VARIANT
24643 #define THUMB_VARIANT & arm_ext_v6t2
24645 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24646 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24648 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24649 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24651 /* ARM V6 not included in V7M. */
24652 #undef THUMB_VARIANT
24653 #define THUMB_VARIANT & arm_ext_v6_notm
24654 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24655 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24656 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24657 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24658 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24659 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24660 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24661 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24662 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24663 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24664 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24665 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24666 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24667 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24668 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24669 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24670 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24671 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24672 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24674 /* ARM V6 not included in V7M (eg. integer SIMD). */
24675 #undef THUMB_VARIANT
24676 #define THUMB_VARIANT & arm_ext_v6_dsp
24677 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24678 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24679 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24680 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24681 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 /* Old name for QASX. */
24683 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24685 /* Old name for QSAX. */
24686 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24688 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24689 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 /* Old name for SASX. */
24693 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 /* Old name for SHASX. */
24698 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24700 /* Old name for SHSAX. */
24701 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24705 /* Old name for SSAX. */
24706 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24708 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 /* Old name for UASX. */
24713 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24715 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 /* Old name for UHASX. */
24718 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24720 /* Old name for UHSAX. */
24721 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24727 /* Old name for UQASX. */
24728 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24729 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24730 /* Old name for UQSAX. */
24731 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24732 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24733 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24734 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24735 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24736 /* Old name for USAX. */
24737 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24738 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24739 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24740 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24741 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24742 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24743 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24744 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24745 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24746 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24747 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24748 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24749 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24750 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24751 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24752 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24753 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24754 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24755 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24756 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24757 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24758 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24759 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24760 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24761 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24762 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24763 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24764 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24765 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24766 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24767 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24768 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24769 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24770 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24773 #define ARM_VARIANT & arm_ext_v6k_v6t2
24774 #undef THUMB_VARIANT
24775 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24777 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24778 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24779 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24780 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24782 #undef THUMB_VARIANT
24783 #define THUMB_VARIANT & arm_ext_v6_notm
24784 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24786 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24787 RRnpcb
), strexd
, t_strexd
),
24789 #undef THUMB_VARIANT
24790 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24791 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24793 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24795 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24797 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24799 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24802 #define ARM_VARIANT & arm_ext_sec
24803 #undef THUMB_VARIANT
24804 #define THUMB_VARIANT & arm_ext_sec
24806 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24809 #define ARM_VARIANT & arm_ext_virt
24810 #undef THUMB_VARIANT
24811 #define THUMB_VARIANT & arm_ext_virt
24813 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24814 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24817 #define ARM_VARIANT & arm_ext_pan
24818 #undef THUMB_VARIANT
24819 #define THUMB_VARIANT & arm_ext_pan
24821 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24824 #define ARM_VARIANT & arm_ext_v6t2
24825 #undef THUMB_VARIANT
24826 #define THUMB_VARIANT & arm_ext_v6t2
24828 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24829 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24830 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24831 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24833 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24834 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24836 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24837 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24838 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24839 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24842 #define ARM_VARIANT & arm_ext_v3
24843 #undef THUMB_VARIANT
24844 #define THUMB_VARIANT & arm_ext_v6t2
24846 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24847 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24848 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24851 #define ARM_VARIANT & arm_ext_v6t2
24852 #undef THUMB_VARIANT
24853 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24854 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24855 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24857 /* Thumb-only instructions. */
24859 #define ARM_VARIANT NULL
24860 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24861 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24863 /* ARM does not really have an IT instruction, so always allow it.
24864 The opcode is copied from Thumb in order to allow warnings in
24865 -mimplicit-it=[never | arm] modes. */
24867 #define ARM_VARIANT & arm_ext_v1
24868 #undef THUMB_VARIANT
24869 #define THUMB_VARIANT & arm_ext_v6t2
24871 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24872 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24873 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24874 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24875 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24876 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24877 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24878 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24879 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24880 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24881 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24882 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24883 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24884 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24885 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24886 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24887 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24888 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24890 /* Thumb2 only instructions. */
24892 #define ARM_VARIANT NULL
24894 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24895 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24896 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24897 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24898 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24899 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24901 /* Hardware division instructions. */
24903 #define ARM_VARIANT & arm_ext_adiv
24904 #undef THUMB_VARIANT
24905 #define THUMB_VARIANT & arm_ext_div
24907 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24908 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24910 /* ARM V6M/V7 instructions. */
24912 #define ARM_VARIANT & arm_ext_barrier
24913 #undef THUMB_VARIANT
24914 #define THUMB_VARIANT & arm_ext_barrier
24916 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24917 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24918 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24920 /* ARM V7 instructions. */
24922 #define ARM_VARIANT & arm_ext_v7
24923 #undef THUMB_VARIANT
24924 #define THUMB_VARIANT & arm_ext_v7
24926 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24927 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24930 #define ARM_VARIANT & arm_ext_mp
24931 #undef THUMB_VARIANT
24932 #define THUMB_VARIANT & arm_ext_mp
24934 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24936 /* AArchv8 instructions. */
24938 #define ARM_VARIANT & arm_ext_v8
24940 /* Instructions shared between armv8-a and armv8-m. */
24941 #undef THUMB_VARIANT
24942 #define THUMB_VARIANT & arm_ext_atomics
24944 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24945 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24946 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24947 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24948 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24949 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24950 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24951 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24952 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24953 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24955 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24957 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24959 #undef THUMB_VARIANT
24960 #define THUMB_VARIANT & arm_ext_v8
24962 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24963 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24965 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24967 #undef THUMB_VARIANT
24968 #define THUMB_VARIANT & arm_ext_v8r
24970 #define ARM_VARIANT & arm_ext_v8r
24972 /* ARMv8-R instructions. */
24973 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24975 /* Defined in V8 but is in undefined encoding space for earlier
24976 architectures. However earlier architectures are required to treat
24977 this instuction as a semihosting trap as well. Hence while not explicitly
24978 defined as such, it is in fact correct to define the instruction for all
24980 #undef THUMB_VARIANT
24981 #define THUMB_VARIANT & arm_ext_v1
24983 #define ARM_VARIANT & arm_ext_v1
24984 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24986 /* ARMv8 T32 only. */
24988 #define ARM_VARIANT NULL
24989 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24990 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24991 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24993 /* FP for ARMv8. */
24995 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24996 #undef THUMB_VARIANT
24997 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24999 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25000 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25001 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25002 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
25003 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
25004 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
25005 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
25006 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
25007 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
25008 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
25009 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
25011 /* Crypto v1 extensions. */
25013 #define ARM_VARIANT & fpu_crypto_ext_armv8
25014 #undef THUMB_VARIANT
25015 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25017 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25018 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25019 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25020 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25021 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25022 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25023 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25024 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25025 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25026 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25027 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25028 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25029 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25030 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25033 #define ARM_VARIANT & arm_ext_crc
25034 #undef THUMB_VARIANT
25035 #define THUMB_VARIANT & arm_ext_crc
25036 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25037 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25038 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25039 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25040 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25041 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25043 /* ARMv8.2 RAS extension. */
25045 #define ARM_VARIANT & arm_ext_ras
25046 #undef THUMB_VARIANT
25047 #define THUMB_VARIANT & arm_ext_ras
25048 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25051 #define ARM_VARIANT & arm_ext_v8_3
25052 #undef THUMB_VARIANT
25053 #define THUMB_VARIANT & arm_ext_v8_3
25054 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25057 #define ARM_VARIANT & fpu_neon_ext_dotprod
25058 #undef THUMB_VARIANT
25059 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25060 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25061 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25064 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25065 #undef THUMB_VARIANT
25066 #define THUMB_VARIANT NULL
25068 cCE("wfs", e200110
, 1, (RR
), rd
),
25069 cCE("rfs", e300110
, 1, (RR
), rd
),
25070 cCE("wfc", e400110
, 1, (RR
), rd
),
25071 cCE("rfc", e500110
, 1, (RR
), rd
),
25073 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25074 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25075 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25076 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25078 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25079 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25080 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25081 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25083 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25278 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25280 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25281 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25282 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25283 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25284 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25285 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25286 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25287 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25288 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25289 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25291 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25447 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25449 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25450 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25451 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25452 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25453 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25454 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25455 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25456 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25457 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25458 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25460 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25461 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25462 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25463 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25465 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25466 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25467 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25468 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25469 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25470 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25471 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25472 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25473 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25474 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25475 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25476 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25478 /* The implementation of the FIX instruction is broken on some
25479 assemblers, in that it accepts a precision specifier as well as a
25480 rounding specifier, despite the fact that this is meaningless.
25481 To be more compatible, we accept it as well, though of course it
25482 does not set any bits. */
25483 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25484 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25485 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25486 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25487 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25488 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25489 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25490 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25491 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25492 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25493 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25494 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25495 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25497 /* Instructions that were new with the real FPA, call them V2. */
25499 #define ARM_VARIANT & fpu_fpa_ext_v2
25501 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25502 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25503 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25504 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25505 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25506 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25509 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25510 #undef THUMB_VARIANT
25511 #define THUMB_VARIANT & arm_ext_v6t2
25512 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25513 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25514 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25515 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25516 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25517 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25519 /* Memory operations. */
25520 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25521 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25522 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25523 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25524 #undef THUMB_VARIANT
25526 /* Moves and type conversions. */
25527 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25528 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25529 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25530 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25531 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25532 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25533 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25534 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25535 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25537 /* Memory operations. */
25538 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25539 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25540 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25541 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25542 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25543 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25544 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25545 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25546 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25547 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25548 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25549 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25551 /* Monadic operations. */
25552 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25553 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25554 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25556 /* Dyadic operations. */
25557 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25558 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25559 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25560 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25561 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25562 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25563 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25564 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25565 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25568 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25569 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25570 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25571 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25573 /* Double precision load/store are still present on single precision
25574 implementations. */
25575 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25576 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25577 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25578 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25579 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25580 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25581 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25582 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25585 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25587 /* Moves and type conversions. */
25588 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25589 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25590 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25591 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25592 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25593 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25594 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25595 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25596 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25597 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25598 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25599 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25601 /* Monadic operations. */
25602 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25603 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25604 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25606 /* Dyadic operations. */
25607 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25608 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25609 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25610 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25611 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25612 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25613 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25614 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25615 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25618 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25619 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25620 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25621 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25623 /* Instructions which may belong to either the Neon or VFP instruction sets.
25624 Individual encoder functions perform additional architecture checks. */
25626 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25627 #undef THUMB_VARIANT
25628 #define THUMB_VARIANT & arm_ext_v6t2
25630 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25631 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25632 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25633 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25634 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25635 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25637 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25638 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25640 #undef THUMB_VARIANT
25641 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25643 /* These mnemonics are unique to VFP. */
25644 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25645 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25646 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25647 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25648 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25649 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25651 /* Mnemonics shared by Neon and VFP. */
25652 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25654 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25655 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25656 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25657 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25660 /* NOTE: All VMOV encoding is special-cased! */
25661 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25663 #undef THUMB_VARIANT
25664 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25665 by different feature bits. Since we are setting the Thumb guard, we can
25666 require Thumb-1 which makes it a nop guard and set the right feature bit in
25667 do_vldr_vstr (). */
25668 #define THUMB_VARIANT & arm_ext_v4t
25669 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25670 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25673 #define ARM_VARIANT & arm_ext_fp16
25674 #undef THUMB_VARIANT
25675 #define THUMB_VARIANT & arm_ext_fp16
25676 /* New instructions added from v8.2, allowing the extraction and insertion of
25677 the upper 16 bits of a 32-bit vector register. */
25678 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25679 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25681 /* New backported fma/fms instructions optional in v8.2. */
25682 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25683 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25685 #undef THUMB_VARIANT
25686 #define THUMB_VARIANT & fpu_neon_ext_v1
25688 #define ARM_VARIANT & fpu_neon_ext_v1
25690 /* Data processing with three registers of the same length. */
25691 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25692 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25693 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25694 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25695 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25696 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25697 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25698 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25699 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25700 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25701 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25702 /* If not immediate, fall back to neon_dyadic_i64_su.
25703 shl should accept I8 I16 I32 I64,
25704 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25705 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25706 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25707 /* Logic ops, types optional & ignored. */
25708 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25709 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25710 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25711 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25712 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25713 /* Bitfield ops, untyped. */
25714 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25715 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25716 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25717 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25718 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25719 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25720 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25721 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25722 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25723 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25724 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25725 back to neon_dyadic_if_su. */
25726 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25727 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25728 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25729 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25730 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25731 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25732 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25733 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25734 /* Comparison. Type I8 I16 I32 F32. */
25735 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25736 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25737 /* As above, D registers only. */
25738 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25739 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25740 /* Int and float variants, signedness unimportant. */
25741 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25742 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25743 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25744 /* Add/sub take types I8 I16 I32 I64 F32. */
25745 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25746 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25747 /* vtst takes sizes 8, 16, 32. */
25748 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25749 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25750 /* VMUL takes I8 I16 I32 F32 P8. */
25751 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25752 /* VQD{R}MULH takes S16 S32. */
25753 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25754 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25755 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25756 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25757 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25758 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25759 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25760 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25761 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25762 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25763 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25764 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25765 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25766 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25767 /* ARM v8.1 extension. */
25768 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25769 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25770 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25772 /* Two address, int/float. Types S8 S16 S32 F32. */
25773 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25774 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25776 /* Data processing with two registers and a shift amount. */
25777 /* Right shifts, and variants with rounding.
25778 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25779 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25780 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25781 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25782 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25783 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25784 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25785 /* Shift and insert. Sizes accepted 8 16 32 64. */
25786 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25787 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25788 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25789 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25790 /* Right shift immediate, saturating & narrowing, with rounding variants.
25791 Types accepted S16 S32 S64 U16 U32 U64. */
25792 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25793 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25794 /* As above, unsigned. Types accepted S16 S32 S64. */
25795 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25796 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25797 /* Right shift narrowing. Types accepted I16 I32 I64. */
25798 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25799 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25800 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25801 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25802 /* CVT with optional immediate for fixed-point variant. */
25803 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25805 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25807 /* Data processing, three registers of different lengths. */
25808 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25809 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25810 /* If not scalar, fall back to neon_dyadic_long.
25811 Vector types as above, scalar types S16 S32 U16 U32. */
25812 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25813 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25814 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25815 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25816 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25817 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25818 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25819 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25820 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25821 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25822 /* Saturating doubling multiplies. Types S16 S32. */
25823 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25824 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25825 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25826 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25827 S16 S32 U16 U32. */
25828 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25830 /* Extract. Size 8. */
25831 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25832 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25834 /* Two registers, miscellaneous. */
25835 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25836 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25837 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25838 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25839 /* Vector replicate. Sizes 8 16 32. */
25840 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25841 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25842 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25843 /* VMOVN. Types I16 I32 I64. */
25844 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25845 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25846 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25847 /* VQMOVUN. Types S16 S32 S64. */
25848 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25849 /* VZIP / VUZP. Sizes 8 16 32. */
25850 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25851 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25852 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25853 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25854 /* VQABS / VQNEG. Types S8 S16 S32. */
25855 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25856 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25857 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25858 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25859 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25860 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25861 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25862 /* Reciprocal estimates. Types U32 F16 F32. */
25863 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25864 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25865 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25866 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25867 /* VCLS. Types S8 S16 S32. */
25868 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25869 /* VCLZ. Types I8 I16 I32. */
25870 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25871 /* VCNT. Size 8. */
25872 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25873 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25874 /* Two address, untyped. */
25875 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25876 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25877 /* VTRN. Sizes 8 16 32. */
25878 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25879 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25881 /* Table lookup. Size 8. */
25882 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25883 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25885 #undef THUMB_VARIANT
25886 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25888 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25890 /* Neon element/structure load/store. */
25891 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25892 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25893 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25894 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25895 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25896 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25897 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25898 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25900 #undef THUMB_VARIANT
25901 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25903 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25904 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25905 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25906 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25907 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25908 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25909 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25910 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25911 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25912 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25914 #undef THUMB_VARIANT
25915 #define THUMB_VARIANT & fpu_vfp_ext_v3
25917 #define ARM_VARIANT & fpu_vfp_ext_v3
25919 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25920 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25921 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25922 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25923 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25924 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25925 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25926 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25927 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25930 #define ARM_VARIANT & fpu_vfp_ext_fma
25931 #undef THUMB_VARIANT
25932 #define THUMB_VARIANT & fpu_vfp_ext_fma
25933 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25934 VFP FMA variant; NEON and VFP FMA always includes the NEON
25935 FMA instructions. */
25936 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25937 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25938 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25940 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25941 the v form should always be used. */
25942 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25943 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25944 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25945 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25946 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25947 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25949 #undef THUMB_VARIANT
25951 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25953 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25954 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25955 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25956 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25957 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25958 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25959 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25960 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25963 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25965 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25966 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25967 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25968 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25969 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25970 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25971 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25972 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25973 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25974 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25975 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25976 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25977 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25978 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25979 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25980 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25981 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25982 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25983 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25984 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25985 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25986 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25987 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25988 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25989 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25990 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25991 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25992 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25993 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25994 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25995 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25996 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25997 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25998 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25999 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26000 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26001 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26002 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26012 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26026 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26032 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26033 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26034 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26035 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26046 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26049 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26054 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26056 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26057 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26058 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26059 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26060 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26061 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26062 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26063 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26064 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26065 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26066 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26067 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26068 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26069 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26070 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26071 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26072 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26073 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26074 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26075 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26076 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26077 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26078 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26079 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26080 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26081 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26082 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26083 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26084 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26085 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26086 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26087 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26088 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26089 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26090 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26091 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26092 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26093 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26094 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26095 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26096 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26097 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26098 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26099 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26100 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26101 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26102 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26103 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26104 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26105 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26106 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26107 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26108 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26109 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26110 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26111 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26112 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26113 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26114 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26115 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26116 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26117 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26118 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26119 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26120 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26121 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26122 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26123 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26124 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26125 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26126 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26129 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26131 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26132 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26133 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26134 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26135 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26136 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26137 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26152 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26176 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26179 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26180 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26181 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26182 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26183 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26184 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26185 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26186 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26187 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26190 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26192 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26193 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26194 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26195 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26196 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26197 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26198 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26199 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26200 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26201 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26202 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26203 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26204 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26205 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26206 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26207 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26208 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26209 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26210 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26211 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26212 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26213 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26214 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26215 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26216 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26217 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26218 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26219 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26220 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26221 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26222 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26223 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26224 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26225 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26226 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26227 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26228 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26229 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26230 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26231 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26232 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26233 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26234 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26235 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26236 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26237 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26238 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26239 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26240 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26241 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26242 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26243 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26244 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26245 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26246 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26247 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26248 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26249 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26250 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26251 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26252 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26253 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26254 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26255 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26256 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26257 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26258 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26259 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26260 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26261 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26262 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26263 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26264 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26265 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26266 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26267 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26269 /* ARMv8.5-A instructions. */
26271 #define ARM_VARIANT & arm_ext_sb
26272 #undef THUMB_VARIANT
26273 #define THUMB_VARIANT & arm_ext_sb
26274 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26277 #define ARM_VARIANT & arm_ext_predres
26278 #undef THUMB_VARIANT
26279 #define THUMB_VARIANT & arm_ext_predres
26280 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26281 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26282 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26284 /* ARMv8-M instructions. */
26286 #define ARM_VARIANT NULL
26287 #undef THUMB_VARIANT
26288 #define THUMB_VARIANT & arm_ext_v8m
26289 ToU("sg", e97fe97f
, 0, (), noargs
),
26290 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26291 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26292 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26293 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26294 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26295 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26297 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26298 instructions behave as nop if no VFP is present. */
26299 #undef THUMB_VARIANT
26300 #define THUMB_VARIANT & arm_ext_v8m_main
26301 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26302 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26304 /* Armv8.1-M Mainline instructions. */
26305 #undef THUMB_VARIANT
26306 #define THUMB_VARIANT & arm_ext_v8_1m_main
26307 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26308 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26309 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26310 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26311 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26312 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26313 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26314 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26315 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26317 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26318 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26319 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26320 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26321 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26323 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26324 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26325 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26327 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26328 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26330 #undef THUMB_VARIANT
26331 #define THUMB_VARIANT & mve_ext
26332 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26333 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26334 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26335 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26336 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26337 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26338 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26339 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26340 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26341 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26342 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26343 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26344 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26345 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26346 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26348 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26350 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26351 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26352 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26353 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26354 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26355 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26356 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26357 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26358 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26359 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26360 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26361 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26362 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26364 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26365 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26366 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26367 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26368 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26369 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26370 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26371 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26372 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26373 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26374 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26375 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26376 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26377 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26378 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26380 /* MVE and MVE FP only. */
26381 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26382 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26383 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26384 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26385 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26386 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26387 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26388 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26389 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26390 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26391 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26392 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26393 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26394 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26395 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26396 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26397 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26398 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26400 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26401 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26402 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26403 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26404 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26405 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26406 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26407 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26408 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26409 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26410 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26411 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26412 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26413 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26414 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26415 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26416 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26417 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26418 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26419 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26421 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26422 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26423 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26424 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26425 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26426 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26427 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26428 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26429 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26430 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26431 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26432 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26433 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26434 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26435 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26436 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26437 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26439 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26440 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26441 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26442 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26443 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26444 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26445 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26446 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26447 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26448 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26449 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26450 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26451 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26452 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26453 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26454 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26455 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26456 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26457 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26458 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26460 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26461 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26462 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26463 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26464 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26466 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26467 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26468 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26469 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26470 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26471 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26472 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26473 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26474 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26475 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26476 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26477 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26478 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26479 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26480 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26481 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26482 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26484 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26485 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26486 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26487 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26488 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26489 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26490 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26491 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26492 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26493 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26494 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26495 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26497 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26498 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26499 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26501 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26502 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26503 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26504 toU("lctp", _lctp
, 0, (), t_loloop
),
26506 #undef THUMB_VARIANT
26507 #define THUMB_VARIANT & mve_fp_ext
26508 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26509 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26510 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26511 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26512 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26513 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26514 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26515 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26518 #define ARM_VARIANT & fpu_vfp_ext_v1
26519 #undef THUMB_VARIANT
26520 #define THUMB_VARIANT & arm_ext_v6t2
26522 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26525 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26527 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26528 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26529 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26530 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26531 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26532 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26534 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26535 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26536 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26538 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26539 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26541 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26542 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26544 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26545 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26548 #define ARM_VARIANT & fpu_vfp_ext_v2
26550 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26551 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26552 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26553 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26556 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26557 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26558 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26559 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26560 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26561 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26562 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26565 #define ARM_VARIANT & fpu_neon_ext_v1
26566 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26567 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26568 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26569 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26570 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26571 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26572 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26573 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26574 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26575 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26576 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26577 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26578 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26579 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26580 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26581 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26582 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26583 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26584 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26585 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26586 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26587 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26588 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26589 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26590 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26591 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26592 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26593 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26594 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26595 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26596 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26597 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26598 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26599 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26600 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26601 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26602 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26605 #define ARM_VARIANT & arm_ext_v8_3
26606 #undef THUMB_VARIANT
26607 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26608 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26609 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26612 #define ARM_VARIANT &arm_ext_bf16
26613 #undef THUMB_VARIANT
26614 #define THUMB_VARIANT &arm_ext_bf16
26615 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26616 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26617 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26620 #define ARM_VARIANT &arm_ext_i8mm
26621 #undef THUMB_VARIANT
26622 #define THUMB_VARIANT &arm_ext_i8mm
26623 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26624 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26625 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26626 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26627 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26630 #undef THUMB_VARIANT
26631 #define THUMB_VARIANT &arm_ext_cde
26632 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26633 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26634 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26635 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26637 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26638 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26639 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26640 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26642 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26643 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26644 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26645 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26647 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26648 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26650 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26651 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26653 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26654 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26658 #undef THUMB_VARIANT
26690 /* MD interface: bits in the object file. */
26692 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26693 for use in the a.out file, and stores them in the array pointed to by buf.
26694 This knows about the endian-ness of the target machine and does
26695 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26696 2 (short) and 4 (long) Floating numbers are put out as a series of
26697 LITTLENUMS (shorts, here at least). */
26700 md_number_to_chars (char * buf
, valueT val
, int n
)
26702 if (target_big_endian
)
26703 number_to_chars_bigendian (buf
, val
, n
);
26705 number_to_chars_littleendian (buf
, val
, n
);
26709 md_chars_to_number (char * buf
, int n
)
26712 unsigned char * where
= (unsigned char *) buf
;
26714 if (target_big_endian
)
26719 result
|= (*where
++ & 255);
26727 result
|= (where
[n
] & 255);
26734 /* MD interface: Sections. */
26736 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26737 that an rs_machine_dependent frag may reach. */
26740 arm_frag_max_var (fragS
*fragp
)
26742 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26743 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26745 Note that we generate relaxable instructions even for cases that don't
26746 really need it, like an immediate that's a trivial constant. So we're
26747 overestimating the instruction size for some of those cases. Rather
26748 than putting more intelligence here, it would probably be better to
26749 avoid generating a relaxation frag in the first place when it can be
26750 determined up front that a short instruction will suffice. */
26752 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26756 /* Estimate the size of a frag before relaxing. Assume everything fits in
26760 md_estimate_size_before_relax (fragS
* fragp
,
26761 segT segtype ATTRIBUTE_UNUSED
)
26767 /* Convert a machine dependent frag. */
26770 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26772 unsigned long insn
;
26773 unsigned long old_op
;
26781 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26783 old_op
= bfd_get_16(abfd
, buf
);
26784 if (fragp
->fr_symbol
)
26786 exp
.X_op
= O_symbol
;
26787 exp
.X_add_symbol
= fragp
->fr_symbol
;
26791 exp
.X_op
= O_constant
;
26793 exp
.X_add_number
= fragp
->fr_offset
;
26794 opcode
= fragp
->fr_subtype
;
26797 case T_MNEM_ldr_pc
:
26798 case T_MNEM_ldr_pc2
:
26799 case T_MNEM_ldr_sp
:
26800 case T_MNEM_str_sp
:
26807 if (fragp
->fr_var
== 4)
26809 insn
= THUMB_OP32 (opcode
);
26810 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26812 insn
|= (old_op
& 0x700) << 4;
26816 insn
|= (old_op
& 7) << 12;
26817 insn
|= (old_op
& 0x38) << 13;
26819 insn
|= 0x00000c00;
26820 put_thumb32_insn (buf
, insn
);
26821 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26825 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26827 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26830 if (fragp
->fr_var
== 4)
26832 insn
= THUMB_OP32 (opcode
);
26833 insn
|= (old_op
& 0xf0) << 4;
26834 put_thumb32_insn (buf
, insn
);
26835 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26839 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26840 exp
.X_add_number
-= 4;
26848 if (fragp
->fr_var
== 4)
26850 int r0off
= (opcode
== T_MNEM_mov
26851 || opcode
== T_MNEM_movs
) ? 0 : 8;
26852 insn
= THUMB_OP32 (opcode
);
26853 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26854 insn
|= (old_op
& 0x700) << r0off
;
26855 put_thumb32_insn (buf
, insn
);
26856 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26860 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26865 if (fragp
->fr_var
== 4)
26867 insn
= THUMB_OP32(opcode
);
26868 put_thumb32_insn (buf
, insn
);
26869 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26872 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26876 if (fragp
->fr_var
== 4)
26878 insn
= THUMB_OP32(opcode
);
26879 insn
|= (old_op
& 0xf00) << 14;
26880 put_thumb32_insn (buf
, insn
);
26881 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26884 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26887 case T_MNEM_add_sp
:
26888 case T_MNEM_add_pc
:
26889 case T_MNEM_inc_sp
:
26890 case T_MNEM_dec_sp
:
26891 if (fragp
->fr_var
== 4)
26893 /* ??? Choose between add and addw. */
26894 insn
= THUMB_OP32 (opcode
);
26895 insn
|= (old_op
& 0xf0) << 4;
26896 put_thumb32_insn (buf
, insn
);
26897 if (opcode
== T_MNEM_add_pc
)
26898 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26900 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26903 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26911 if (fragp
->fr_var
== 4)
26913 insn
= THUMB_OP32 (opcode
);
26914 insn
|= (old_op
& 0xf0) << 4;
26915 insn
|= (old_op
& 0xf) << 16;
26916 put_thumb32_insn (buf
, insn
);
26917 if (insn
& (1 << 20))
26918 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26920 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26923 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26929 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26930 (enum bfd_reloc_code_real
) reloc_type
);
26931 fixp
->fx_file
= fragp
->fr_file
;
26932 fixp
->fx_line
= fragp
->fr_line
;
26933 fragp
->fr_fix
+= fragp
->fr_var
;
26935 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26936 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26937 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26938 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26941 /* Return the size of a relaxable immediate operand instruction.
26942 SHIFT and SIZE specify the form of the allowable immediate. */
26944 relax_immediate (fragS
*fragp
, int size
, int shift
)
26950 /* ??? Should be able to do better than this. */
26951 if (fragp
->fr_symbol
)
26954 low
= (1 << shift
) - 1;
26955 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26956 offset
= fragp
->fr_offset
;
26957 /* Force misaligned offsets to 32-bit variant. */
26960 if (offset
& ~mask
)
26965 /* Get the address of a symbol during relaxation. */
26967 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26973 sym
= fragp
->fr_symbol
;
26974 sym_frag
= symbol_get_frag (sym
);
26975 know (S_GET_SEGMENT (sym
) != absolute_section
26976 || sym_frag
== &zero_address_frag
);
26977 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26979 /* If frag has yet to be reached on this pass, assume it will
26980 move by STRETCH just as we did. If this is not so, it will
26981 be because some frag between grows, and that will force
26985 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26989 /* Adjust stretch for any alignment frag. Note that if have
26990 been expanding the earlier code, the symbol may be
26991 defined in what appears to be an earlier frag. FIXME:
26992 This doesn't handle the fr_subtype field, which specifies
26993 a maximum number of bytes to skip when doing an
26995 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26997 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
27000 stretch
= - ((- stretch
)
27001 & ~ ((1 << (int) f
->fr_offset
) - 1));
27003 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27015 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27018 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27023 /* Assume worst case for symbols not known to be in the same section. */
27024 if (fragp
->fr_symbol
== NULL
27025 || !S_IS_DEFINED (fragp
->fr_symbol
)
27026 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27027 || S_IS_WEAK (fragp
->fr_symbol
))
27030 val
= relaxed_symbol_addr (fragp
, stretch
);
27031 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27032 addr
= (addr
+ 4) & ~3;
27033 /* Force misaligned targets to 32-bit variant. */
27037 if (val
< 0 || val
> 1020)
27042 /* Return the size of a relaxable add/sub immediate instruction. */
27044 relax_addsub (fragS
*fragp
, asection
*sec
)
27049 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27050 op
= bfd_get_16(sec
->owner
, buf
);
27051 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27052 return relax_immediate (fragp
, 8, 0);
27054 return relax_immediate (fragp
, 3, 0);
27057 /* Return TRUE iff the definition of symbol S could be pre-empted
27058 (overridden) at link or load time. */
27060 symbol_preemptible (symbolS
*s
)
27062 /* Weak symbols can always be pre-empted. */
27066 /* Non-global symbols cannot be pre-empted. */
27067 if (! S_IS_EXTERNAL (s
))
27071 /* In ELF, a global symbol can be marked protected, or private. In that
27072 case it can't be pre-empted (other definitions in the same link unit
27073 would violate the ODR). */
27074 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27078 /* Other global symbols might be pre-empted. */
27082 /* Return the size of a relaxable branch instruction. BITS is the
27083 size of the offset field in the narrow instruction. */
27086 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27092 /* Assume worst case for symbols not known to be in the same section. */
27093 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27094 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27095 || S_IS_WEAK (fragp
->fr_symbol
))
27099 /* A branch to a function in ARM state will require interworking. */
27100 if (S_IS_DEFINED (fragp
->fr_symbol
)
27101 && ARM_IS_FUNC (fragp
->fr_symbol
))
27105 if (symbol_preemptible (fragp
->fr_symbol
))
27108 val
= relaxed_symbol_addr (fragp
, stretch
);
27109 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27112 /* Offset is a signed value *2 */
27114 if (val
>= limit
|| val
< -limit
)
27120 /* Relax a machine dependent frag. This returns the amount by which
27121 the current size of the frag should change. */
27124 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27129 oldsize
= fragp
->fr_var
;
27130 switch (fragp
->fr_subtype
)
27132 case T_MNEM_ldr_pc2
:
27133 newsize
= relax_adr (fragp
, sec
, stretch
);
27135 case T_MNEM_ldr_pc
:
27136 case T_MNEM_ldr_sp
:
27137 case T_MNEM_str_sp
:
27138 newsize
= relax_immediate (fragp
, 8, 2);
27142 newsize
= relax_immediate (fragp
, 5, 2);
27146 newsize
= relax_immediate (fragp
, 5, 1);
27150 newsize
= relax_immediate (fragp
, 5, 0);
27153 newsize
= relax_adr (fragp
, sec
, stretch
);
27159 newsize
= relax_immediate (fragp
, 8, 0);
27162 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27165 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27167 case T_MNEM_add_sp
:
27168 case T_MNEM_add_pc
:
27169 newsize
= relax_immediate (fragp
, 8, 2);
27171 case T_MNEM_inc_sp
:
27172 case T_MNEM_dec_sp
:
27173 newsize
= relax_immediate (fragp
, 7, 2);
27179 newsize
= relax_addsub (fragp
, sec
);
27185 fragp
->fr_var
= newsize
;
27186 /* Freeze wide instructions that are at or before the same location as
27187 in the previous pass. This avoids infinite loops.
27188 Don't freeze them unconditionally because targets may be artificially
27189 misaligned by the expansion of preceding frags. */
27190 if (stretch
<= 0 && newsize
> 2)
27192 md_convert_frag (sec
->owner
, sec
, fragp
);
27196 return newsize
- oldsize
;
27199 /* Round up a section size to the appropriate boundary. */
27202 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27208 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27209 of an rs_align_code fragment. */
27212 arm_handle_align (fragS
* fragP
)
27214 static unsigned char const arm_noop
[2][2][4] =
27217 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27218 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27221 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27222 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27225 static unsigned char const thumb_noop
[2][2][2] =
27228 {0xc0, 0x46}, /* LE */
27229 {0x46, 0xc0}, /* BE */
27232 {0x00, 0xbf}, /* LE */
27233 {0xbf, 0x00} /* BE */
27236 static unsigned char const wide_thumb_noop
[2][4] =
27237 { /* Wide Thumb-2 */
27238 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27239 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27242 unsigned bytes
, fix
, noop_size
;
27244 const unsigned char * noop
;
27245 const unsigned char *narrow_noop
= NULL
;
27250 if (fragP
->fr_type
!= rs_align_code
)
27253 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27254 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27257 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27258 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27260 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27262 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27264 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27265 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27267 narrow_noop
= thumb_noop
[1][target_big_endian
];
27268 noop
= wide_thumb_noop
[target_big_endian
];
27271 noop
= thumb_noop
[0][target_big_endian
];
27279 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27280 ? selected_cpu
: arm_arch_none
,
27282 [target_big_endian
];
27289 fragP
->fr_var
= noop_size
;
27291 if (bytes
& (noop_size
- 1))
27293 fix
= bytes
& (noop_size
- 1);
27295 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27297 memset (p
, 0, fix
);
27304 if (bytes
& noop_size
)
27306 /* Insert a narrow noop. */
27307 memcpy (p
, narrow_noop
, noop_size
);
27309 bytes
-= noop_size
;
27313 /* Use wide noops for the remainder */
27317 while (bytes
>= noop_size
)
27319 memcpy (p
, noop
, noop_size
);
27321 bytes
-= noop_size
;
27325 fragP
->fr_fix
+= fix
;
27328 /* Called from md_do_align. Used to create an alignment
27329 frag in a code section. */
27332 arm_frag_align_code (int n
, int max
)
27336 /* We assume that there will never be a requirement
27337 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27338 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27343 _("alignments greater than %d bytes not supported in .text sections."),
27344 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27345 as_fatal ("%s", err_msg
);
27348 p
= frag_var (rs_align_code
,
27349 MAX_MEM_FOR_RS_ALIGN_CODE
,
27351 (relax_substateT
) max
,
27358 /* Perform target specific initialisation of a frag.
27359 Note - despite the name this initialisation is not done when the frag
27360 is created, but only when its type is assigned. A frag can be created
27361 and used a long time before its type is set, so beware of assuming that
27362 this initialisation is performed first. */
27366 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27368 /* Record whether this frag is in an ARM or a THUMB area. */
27369 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27372 #else /* OBJ_ELF is defined. */
27374 arm_init_frag (fragS
* fragP
, int max_chars
)
27376 bfd_boolean frag_thumb_mode
;
27378 /* If the current ARM vs THUMB mode has not already
27379 been recorded into this frag then do so now. */
27380 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27381 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27383 /* PR 21809: Do not set a mapping state for debug sections
27384 - it just confuses other tools. */
27385 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27388 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27390 /* Record a mapping symbol for alignment frags. We will delete this
27391 later if the alignment ends up empty. */
27392 switch (fragP
->fr_type
)
27395 case rs_align_test
:
27397 mapping_state_2 (MAP_DATA
, max_chars
);
27399 case rs_align_code
:
27400 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27407 /* When we change sections we need to issue a new mapping symbol. */
27410 arm_elf_change_section (void)
27412 /* Link an unlinked unwind index table section to the .text section. */
27413 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27414 && elf_linked_to_section (now_seg
) == NULL
)
27415 elf_linked_to_section (now_seg
) = text_section
;
27419 arm_elf_section_type (const char * str
, size_t len
)
27421 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27422 return SHT_ARM_EXIDX
;
27427 /* Code to deal with unwinding tables. */
27429 static void add_unwind_adjustsp (offsetT
);
27431 /* Generate any deferred unwind frame offset. */
27434 flush_pending_unwind (void)
27438 offset
= unwind
.pending_offset
;
27439 unwind
.pending_offset
= 0;
27441 add_unwind_adjustsp (offset
);
27444 /* Add an opcode to this list for this function. Two-byte opcodes should
27445 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27449 add_unwind_opcode (valueT op
, int length
)
27451 /* Add any deferred stack adjustment. */
27452 if (unwind
.pending_offset
)
27453 flush_pending_unwind ();
27455 unwind
.sp_restored
= 0;
27457 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27459 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27460 if (unwind
.opcodes
)
27461 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27462 unwind
.opcode_alloc
);
27464 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27469 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27471 unwind
.opcode_count
++;
27475 /* Add unwind opcodes to adjust the stack pointer. */
27478 add_unwind_adjustsp (offsetT offset
)
27482 if (offset
> 0x200)
27484 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27489 /* Long form: 0xb2, uleb128. */
27490 /* This might not fit in a word so add the individual bytes,
27491 remembering the list is built in reverse order. */
27492 o
= (valueT
) ((offset
- 0x204) >> 2);
27494 add_unwind_opcode (0, 1);
27496 /* Calculate the uleb128 encoding of the offset. */
27500 bytes
[n
] = o
& 0x7f;
27506 /* Add the insn. */
27508 add_unwind_opcode (bytes
[n
- 1], 1);
27509 add_unwind_opcode (0xb2, 1);
27511 else if (offset
> 0x100)
27513 /* Two short opcodes. */
27514 add_unwind_opcode (0x3f, 1);
27515 op
= (offset
- 0x104) >> 2;
27516 add_unwind_opcode (op
, 1);
27518 else if (offset
> 0)
27520 /* Short opcode. */
27521 op
= (offset
- 4) >> 2;
27522 add_unwind_opcode (op
, 1);
27524 else if (offset
< 0)
27527 while (offset
> 0x100)
27529 add_unwind_opcode (0x7f, 1);
27532 op
= ((offset
- 4) >> 2) | 0x40;
27533 add_unwind_opcode (op
, 1);
27537 /* Finish the list of unwind opcodes for this function. */
27540 finish_unwind_opcodes (void)
27544 if (unwind
.fp_used
)
27546 /* Adjust sp as necessary. */
27547 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27548 flush_pending_unwind ();
27550 /* After restoring sp from the frame pointer. */
27551 op
= 0x90 | unwind
.fp_reg
;
27552 add_unwind_opcode (op
, 1);
27555 flush_pending_unwind ();
27559 /* Start an exception table entry. If idx is nonzero this is an index table
27563 start_unwind_section (const segT text_seg
, int idx
)
27565 const char * text_name
;
27566 const char * prefix
;
27567 const char * prefix_once
;
27568 struct elf_section_match match
;
27576 prefix
= ELF_STRING_ARM_unwind
;
27577 prefix_once
= ELF_STRING_ARM_unwind_once
;
27578 type
= SHT_ARM_EXIDX
;
27582 prefix
= ELF_STRING_ARM_unwind_info
;
27583 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27584 type
= SHT_PROGBITS
;
27587 text_name
= segment_name (text_seg
);
27588 if (streq (text_name
, ".text"))
27591 if (strncmp (text_name
, ".gnu.linkonce.t.",
27592 strlen (".gnu.linkonce.t.")) == 0)
27594 prefix
= prefix_once
;
27595 text_name
+= strlen (".gnu.linkonce.t.");
27598 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27602 memset (&match
, 0, sizeof (match
));
27604 /* Handle COMDAT group. */
27605 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27607 match
.group_name
= elf_group_name (text_seg
);
27608 if (match
.group_name
== NULL
)
27610 as_bad (_("Group section `%s' has no group signature"),
27611 segment_name (text_seg
));
27612 ignore_rest_of_line ();
27615 flags
|= SHF_GROUP
;
27619 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27622 /* Set the section link for index tables. */
27624 elf_linked_to_section (now_seg
) = text_seg
;
27628 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27629 personality routine data. Returns zero, or the index table value for
27630 an inline entry. */
27633 create_unwind_entry (int have_data
)
27638 /* The current word of data. */
27640 /* The number of bytes left in this word. */
27643 finish_unwind_opcodes ();
27645 /* Remember the current text section. */
27646 unwind
.saved_seg
= now_seg
;
27647 unwind
.saved_subseg
= now_subseg
;
27649 start_unwind_section (now_seg
, 0);
27651 if (unwind
.personality_routine
== NULL
)
27653 if (unwind
.personality_index
== -2)
27656 as_bad (_("handlerdata in cantunwind frame"));
27657 return 1; /* EXIDX_CANTUNWIND. */
27660 /* Use a default personality routine if none is specified. */
27661 if (unwind
.personality_index
== -1)
27663 if (unwind
.opcode_count
> 3)
27664 unwind
.personality_index
= 1;
27666 unwind
.personality_index
= 0;
27669 /* Space for the personality routine entry. */
27670 if (unwind
.personality_index
== 0)
27672 if (unwind
.opcode_count
> 3)
27673 as_bad (_("too many unwind opcodes for personality routine 0"));
27677 /* All the data is inline in the index table. */
27680 while (unwind
.opcode_count
> 0)
27682 unwind
.opcode_count
--;
27683 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27687 /* Pad with "finish" opcodes. */
27689 data
= (data
<< 8) | 0xb0;
27696 /* We get two opcodes "free" in the first word. */
27697 size
= unwind
.opcode_count
- 2;
27701 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27702 if (unwind
.personality_index
!= -1)
27704 as_bad (_("attempt to recreate an unwind entry"));
27708 /* An extra byte is required for the opcode count. */
27709 size
= unwind
.opcode_count
+ 1;
27712 size
= (size
+ 3) >> 2;
27714 as_bad (_("too many unwind opcodes"));
27716 frag_align (2, 0, 0);
27717 record_alignment (now_seg
, 2);
27718 unwind
.table_entry
= expr_build_dot ();
27720 /* Allocate the table entry. */
27721 ptr
= frag_more ((size
<< 2) + 4);
27722 /* PR 13449: Zero the table entries in case some of them are not used. */
27723 memset (ptr
, 0, (size
<< 2) + 4);
27724 where
= frag_now_fix () - ((size
<< 2) + 4);
27726 switch (unwind
.personality_index
)
27729 /* ??? Should this be a PLT generating relocation? */
27730 /* Custom personality routine. */
27731 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27732 BFD_RELOC_ARM_PREL31
);
27737 /* Set the first byte to the number of additional words. */
27738 data
= size
> 0 ? size
- 1 : 0;
27742 /* ABI defined personality routines. */
27744 /* Three opcodes bytes are packed into the first word. */
27751 /* The size and first two opcode bytes go in the first word. */
27752 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27757 /* Should never happen. */
27761 /* Pack the opcodes into words (MSB first), reversing the list at the same
27763 while (unwind
.opcode_count
> 0)
27767 md_number_to_chars (ptr
, data
, 4);
27772 unwind
.opcode_count
--;
27774 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27777 /* Finish off the last word. */
27780 /* Pad with "finish" opcodes. */
27782 data
= (data
<< 8) | 0xb0;
27784 md_number_to_chars (ptr
, data
, 4);
27789 /* Add an empty descriptor if there is no user-specified data. */
27790 ptr
= frag_more (4);
27791 md_number_to_chars (ptr
, 0, 4);
27798 /* Initialize the DWARF-2 unwind information for this procedure. */
27801 tc_arm_frame_initial_instructions (void)
27803 cfi_add_CFA_def_cfa (REG_SP
, 0);
27805 #endif /* OBJ_ELF */
27807 /* Convert REGNAME to a DWARF-2 register number. */
27810 tc_arm_regname_to_dw2regnum (char *regname
)
27812 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27816 /* PR 16694: Allow VFP registers as well. */
27817 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27821 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27830 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27834 exp
.X_op
= O_secrel
;
27835 exp
.X_add_symbol
= symbol
;
27836 exp
.X_add_number
= 0;
27837 emit_expr (&exp
, size
);
27841 /* MD interface: Symbol and relocation handling. */
27843 /* Return the address within the segment that a PC-relative fixup is
27844 relative to. For ARM, PC-relative fixups applied to instructions
27845 are generally relative to the location of the fixup plus 8 bytes.
27846 Thumb branches are offset by 4, and Thumb loads relative to PC
27847 require special handling. */
27850 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27852 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27854 /* If this is pc-relative and we are going to emit a relocation
27855 then we just want to put out any pipeline compensation that the linker
27856 will need. Otherwise we want to use the calculated base.
27857 For WinCE we skip the bias for externals as well, since this
27858 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27860 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27861 || (arm_force_relocation (fixP
)
27863 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27869 switch (fixP
->fx_r_type
)
27871 /* PC relative addressing on the Thumb is slightly odd as the
27872 bottom two bits of the PC are forced to zero for the
27873 calculation. This happens *after* application of the
27874 pipeline offset. However, Thumb adrl already adjusts for
27875 this, so we need not do it again. */
27876 case BFD_RELOC_ARM_THUMB_ADD
:
27879 case BFD_RELOC_ARM_THUMB_OFFSET
:
27880 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27881 case BFD_RELOC_ARM_T32_ADD_PC12
:
27882 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27883 return (base
+ 4) & ~3;
27885 /* Thumb branches are simply offset by +4. */
27886 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27887 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27888 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27889 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27890 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27891 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27892 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27893 case BFD_RELOC_ARM_THUMB_BF17
:
27894 case BFD_RELOC_ARM_THUMB_BF19
:
27895 case BFD_RELOC_ARM_THUMB_BF13
:
27896 case BFD_RELOC_ARM_THUMB_LOOP12
:
27899 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27901 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27902 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27903 && ARM_IS_FUNC (fixP
->fx_addsy
)
27904 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27905 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27908 /* BLX is like branches above, but forces the low two bits of PC to
27910 case BFD_RELOC_THUMB_PCREL_BLX
:
27912 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27913 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27914 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27915 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27916 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27917 return (base
+ 4) & ~3;
27919 /* ARM mode branches are offset by +8. However, the Windows CE
27920 loader expects the relocation not to take this into account. */
27921 case BFD_RELOC_ARM_PCREL_BLX
:
27923 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27924 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27925 && ARM_IS_FUNC (fixP
->fx_addsy
)
27926 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27927 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27930 case BFD_RELOC_ARM_PCREL_CALL
:
27932 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27933 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27934 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27935 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27936 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27939 case BFD_RELOC_ARM_PCREL_BRANCH
:
27940 case BFD_RELOC_ARM_PCREL_JUMP
:
27941 case BFD_RELOC_ARM_PLT32
:
27943 /* When handling fixups immediately, because we have already
27944 discovered the value of a symbol, or the address of the frag involved
27945 we must account for the offset by +8, as the OS loader will never see the reloc.
27946 see fixup_segment() in write.c
27947 The S_IS_EXTERNAL test handles the case of global symbols.
27948 Those need the calculated base, not just the pipe compensation the linker will need. */
27950 && fixP
->fx_addsy
!= NULL
27951 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27952 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27960 /* ARM mode loads relative to PC are also offset by +8. Unlike
27961 branches, the Windows CE loader *does* expect the relocation
27962 to take this into account. */
27963 case BFD_RELOC_ARM_OFFSET_IMM
:
27964 case BFD_RELOC_ARM_OFFSET_IMM8
:
27965 case BFD_RELOC_ARM_HWLITERAL
:
27966 case BFD_RELOC_ARM_LITERAL
:
27967 case BFD_RELOC_ARM_CP_OFF_IMM
:
27971 /* Other PC-relative relocations are un-offset. */
27977 static bfd_boolean flag_warn_syms
= TRUE
;
27980 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27982 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27983 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27984 does mean that the resulting code might be very confusing to the reader.
27985 Also this warning can be triggered if the user omits an operand before
27986 an immediate address, eg:
27990 GAS treats this as an assignment of the value of the symbol foo to a
27991 symbol LDR, and so (without this code) it will not issue any kind of
27992 warning or error message.
27994 Note - ARM instructions are case-insensitive but the strings in the hash
27995 table are all stored in lower case, so we must first ensure that name is
27997 if (flag_warn_syms
&& arm_ops_hsh
)
27999 char * nbuf
= strdup (name
);
28002 for (p
= nbuf
; *p
; p
++)
28004 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
28006 static htab_t already_warned
= NULL
;
28008 if (already_warned
== NULL
)
28009 already_warned
= str_htab_create ();
28010 /* Only warn about the symbol once. To keep the code
28011 simple we let str_hash_insert do the lookup for us. */
28012 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28014 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28015 str_hash_insert (already_warned
, nbuf
, NULL
, 0);
28025 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28026 Otherwise we have no need to default values of symbols. */
28029 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28032 if (name
[0] == '_' && name
[1] == 'G'
28033 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28037 if (symbol_find (name
))
28038 as_bad (_("GOT already in the symbol table"));
28040 GOT_symbol
= symbol_new (name
, undefined_section
,
28041 &zero_address_frag
, 0);
28051 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28052 computed as two separate immediate values, added together. We
28053 already know that this value cannot be computed by just one ARM
28056 static unsigned int
28057 validate_immediate_twopart (unsigned int val
,
28058 unsigned int * highpart
)
28063 for (i
= 0; i
< 32; i
+= 2)
28064 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28070 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28072 else if (a
& 0xff0000)
28074 if (a
& 0xff000000)
28076 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28080 gas_assert (a
& 0xff000000);
28081 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28084 return (a
& 0xff) | (i
<< 7);
28091 validate_offset_imm (unsigned int val
, int hwse
)
28093 if ((hwse
&& val
> 255) || val
> 4095)
28098 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28099 negative immediate constant by altering the instruction. A bit of
28104 by inverting the second operand, and
28107 by negating the second operand. */
28110 negate_data_op (unsigned long * instruction
,
28111 unsigned long value
)
28114 unsigned long negated
, inverted
;
28116 negated
= encode_arm_immediate (-value
);
28117 inverted
= encode_arm_immediate (~value
);
28119 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28122 /* First negates. */
28123 case OPCODE_SUB
: /* ADD <-> SUB */
28124 new_inst
= OPCODE_ADD
;
28129 new_inst
= OPCODE_SUB
;
28133 case OPCODE_CMP
: /* CMP <-> CMN */
28134 new_inst
= OPCODE_CMN
;
28139 new_inst
= OPCODE_CMP
;
28143 /* Now Inverted ops. */
28144 case OPCODE_MOV
: /* MOV <-> MVN */
28145 new_inst
= OPCODE_MVN
;
28150 new_inst
= OPCODE_MOV
;
28154 case OPCODE_AND
: /* AND <-> BIC */
28155 new_inst
= OPCODE_BIC
;
28160 new_inst
= OPCODE_AND
;
28164 case OPCODE_ADC
: /* ADC <-> SBC */
28165 new_inst
= OPCODE_SBC
;
28170 new_inst
= OPCODE_ADC
;
28174 /* We cannot do anything. */
28179 if (value
== (unsigned) FAIL
)
28182 *instruction
&= OPCODE_MASK
;
28183 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28187 /* Like negate_data_op, but for Thumb-2. */
28189 static unsigned int
28190 thumb32_negate_data_op (valueT
*instruction
, unsigned int value
)
28192 unsigned int op
, new_inst
;
28194 unsigned int negated
, inverted
;
28196 negated
= encode_thumb32_immediate (-value
);
28197 inverted
= encode_thumb32_immediate (~value
);
28199 rd
= (*instruction
>> 8) & 0xf;
28200 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28203 /* ADD <-> SUB. Includes CMP <-> CMN. */
28204 case T2_OPCODE_SUB
:
28205 new_inst
= T2_OPCODE_ADD
;
28209 case T2_OPCODE_ADD
:
28210 new_inst
= T2_OPCODE_SUB
;
28214 /* ORR <-> ORN. Includes MOV <-> MVN. */
28215 case T2_OPCODE_ORR
:
28216 new_inst
= T2_OPCODE_ORN
;
28220 case T2_OPCODE_ORN
:
28221 new_inst
= T2_OPCODE_ORR
;
28225 /* AND <-> BIC. TST has no inverted equivalent. */
28226 case T2_OPCODE_AND
:
28227 new_inst
= T2_OPCODE_BIC
;
28234 case T2_OPCODE_BIC
:
28235 new_inst
= T2_OPCODE_AND
;
28240 case T2_OPCODE_ADC
:
28241 new_inst
= T2_OPCODE_SBC
;
28245 case T2_OPCODE_SBC
:
28246 new_inst
= T2_OPCODE_ADC
;
28250 /* We cannot do anything. */
28255 if (value
== (unsigned int)FAIL
)
28258 *instruction
&= T2_OPCODE_MASK
;
28259 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28263 /* Read a 32-bit thumb instruction from buf. */
28265 static unsigned long
28266 get_thumb32_insn (char * buf
)
28268 unsigned long insn
;
28269 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28270 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28275 /* We usually want to set the low bit on the address of thumb function
28276 symbols. In particular .word foo - . should have the low bit set.
28277 Generic code tries to fold the difference of two symbols to
28278 a constant. Prevent this and force a relocation when the first symbols
28279 is a thumb function. */
28282 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28284 if (op
== O_subtract
28285 && l
->X_op
== O_symbol
28286 && r
->X_op
== O_symbol
28287 && THUMB_IS_FUNC (l
->X_add_symbol
))
28289 l
->X_op
= O_subtract
;
28290 l
->X_op_symbol
= r
->X_add_symbol
;
28291 l
->X_add_number
-= r
->X_add_number
;
28295 /* Process as normal. */
28299 /* Encode Thumb2 unconditional branches and calls. The encoding
28300 for the 2 are identical for the immediate values. */
28303 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28305 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28308 addressT S
, I1
, I2
, lo
, hi
;
28310 S
= (value
>> 24) & 0x01;
28311 I1
= (value
>> 23) & 0x01;
28312 I2
= (value
>> 22) & 0x01;
28313 hi
= (value
>> 12) & 0x3ff;
28314 lo
= (value
>> 1) & 0x7ff;
28315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28316 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28317 newval
|= (S
<< 10) | hi
;
28318 newval2
&= ~T2I1I2MASK
;
28319 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28320 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28321 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28325 md_apply_fix (fixS
* fixP
,
28329 valueT value
= * valP
;
28331 unsigned int newimm
;
28332 unsigned long temp
;
28334 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28336 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28338 /* Note whether this will delete the relocation. */
28340 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28343 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28344 consistency with the behaviour on 32-bit hosts. Remember value
28346 value
&= 0xffffffff;
28347 value
^= 0x80000000;
28348 value
-= 0x80000000;
28351 fixP
->fx_addnumber
= value
;
28353 /* Same treatment for fixP->fx_offset. */
28354 fixP
->fx_offset
&= 0xffffffff;
28355 fixP
->fx_offset
^= 0x80000000;
28356 fixP
->fx_offset
-= 0x80000000;
28358 switch (fixP
->fx_r_type
)
28360 case BFD_RELOC_NONE
:
28361 /* This will need to go in the object file. */
28365 case BFD_RELOC_ARM_IMMEDIATE
:
28366 /* We claim that this fixup has been processed here,
28367 even if in fact we generate an error because we do
28368 not have a reloc for it, so tc_gen_reloc will reject it. */
28371 if (fixP
->fx_addsy
)
28373 const char *msg
= 0;
28375 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28376 msg
= _("undefined symbol %s used as an immediate value");
28377 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28378 msg
= _("symbol %s is in a different section");
28379 else if (S_IS_WEAK (fixP
->fx_addsy
))
28380 msg
= _("symbol %s is weak and may be overridden later");
28384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28385 msg
, S_GET_NAME (fixP
->fx_addsy
));
28390 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28392 /* If the offset is negative, we should use encoding A2 for ADR. */
28393 if ((temp
& 0xfff0000) == 0x28f0000 && (offsetT
) value
< 0)
28394 newimm
= negate_data_op (&temp
, value
);
28397 newimm
= encode_arm_immediate (value
);
28399 /* If the instruction will fail, see if we can fix things up by
28400 changing the opcode. */
28401 if (newimm
== (unsigned int) FAIL
)
28402 newimm
= negate_data_op (&temp
, value
);
28403 /* MOV accepts both ARM modified immediate (A1 encoding) and
28404 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28405 When disassembling, MOV is preferred when there is no encoding
28407 if (newimm
== (unsigned int) FAIL
28408 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28409 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28410 && !((temp
>> SBIT_SHIFT
) & 0x1)
28411 && value
<= 0xffff)
28413 /* Clear bits[23:20] to change encoding from A1 to A2. */
28414 temp
&= 0xff0fffff;
28415 /* Encoding high 4bits imm. Code below will encode the remaining
28417 temp
|= (value
& 0x0000f000) << 4;
28418 newimm
= value
& 0x00000fff;
28422 if (newimm
== (unsigned int) FAIL
)
28424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28425 _("invalid constant (%lx) after fixup"),
28426 (unsigned long) value
);
28430 newimm
|= (temp
& 0xfffff000);
28431 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28434 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28436 unsigned int highpart
= 0;
28437 unsigned int newinsn
= 0xe1a00000; /* nop. */
28439 if (fixP
->fx_addsy
)
28441 const char *msg
= 0;
28443 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28444 msg
= _("undefined symbol %s used as an immediate value");
28445 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28446 msg
= _("symbol %s is in a different section");
28447 else if (S_IS_WEAK (fixP
->fx_addsy
))
28448 msg
= _("symbol %s is weak and may be overridden later");
28452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28453 msg
, S_GET_NAME (fixP
->fx_addsy
));
28458 newimm
= encode_arm_immediate (value
);
28459 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28461 /* If the instruction will fail, see if we can fix things up by
28462 changing the opcode. */
28463 if (newimm
== (unsigned int) FAIL
28464 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28466 /* No ? OK - try using two ADD instructions to generate
28468 newimm
= validate_immediate_twopart (value
, & highpart
);
28470 /* Yes - then make sure that the second instruction is
28472 if (newimm
!= (unsigned int) FAIL
)
28474 /* Still No ? Try using a negated value. */
28475 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28476 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28477 /* Otherwise - give up. */
28480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28481 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28486 /* Replace the first operand in the 2nd instruction (which
28487 is the PC) with the destination register. We have
28488 already added in the PC in the first instruction and we
28489 do not want to do it again. */
28490 newinsn
&= ~ 0xf0000;
28491 newinsn
|= ((newinsn
& 0x0f000) << 4);
28494 newimm
|= (temp
& 0xfffff000);
28495 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28497 highpart
|= (newinsn
& 0xfffff000);
28498 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28502 case BFD_RELOC_ARM_OFFSET_IMM
:
28503 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28505 /* Fall through. */
28507 case BFD_RELOC_ARM_LITERAL
:
28508 sign
= (offsetT
) value
> 0;
28510 if ((offsetT
) value
< 0)
28513 if (validate_offset_imm (value
, 0) == FAIL
)
28515 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28517 _("invalid literal constant: pool needs to be closer"));
28519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28520 _("bad immediate value for offset (%ld)"),
28525 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28527 newval
&= 0xfffff000;
28530 newval
&= 0xff7ff000;
28531 newval
|= value
| (sign
? INDEX_UP
: 0);
28533 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28536 case BFD_RELOC_ARM_OFFSET_IMM8
:
28537 case BFD_RELOC_ARM_HWLITERAL
:
28538 sign
= (offsetT
) value
> 0;
28540 if ((offsetT
) value
< 0)
28543 if (validate_offset_imm (value
, 1) == FAIL
)
28545 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28547 _("invalid literal constant: pool needs to be closer"));
28549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28550 _("bad immediate value for 8-bit offset (%ld)"),
28555 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28557 newval
&= 0xfffff0f0;
28560 newval
&= 0xff7ff0f0;
28561 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28563 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28566 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28567 if (value
> 1020 || value
% 4 != 0)
28568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28569 _("bad immediate value for offset (%ld)"), (long) value
);
28572 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28574 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28577 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28578 /* This is a complicated relocation used for all varieties of Thumb32
28579 load/store instruction with immediate offset:
28581 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28582 *4, optional writeback(W)
28583 (doubleword load/store)
28585 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28586 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28587 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28588 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28589 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28591 Uppercase letters indicate bits that are already encoded at
28592 this point. Lowercase letters are our problem. For the
28593 second block of instructions, the secondary opcode nybble
28594 (bits 8..11) is present, and bit 23 is zero, even if this is
28595 a PC-relative operation. */
28596 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28598 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28600 if ((newval
& 0xf0000000) == 0xe0000000)
28602 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28603 if ((offsetT
) value
>= 0)
28604 newval
|= (1 << 23);
28607 if (value
% 4 != 0)
28609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28610 _("offset not a multiple of 4"));
28616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28617 _("offset out of range"));
28622 else if ((newval
& 0x000f0000) == 0x000f0000)
28624 /* PC-relative, 12-bit offset. */
28625 if ((offsetT
) value
>= 0)
28626 newval
|= (1 << 23);
28631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28632 _("offset out of range"));
28637 else if ((newval
& 0x00000100) == 0x00000100)
28639 /* Writeback: 8-bit, +/- offset. */
28640 if ((offsetT
) value
>= 0)
28641 newval
|= (1 << 9);
28646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28647 _("offset out of range"));
28652 else if ((newval
& 0x00000f00) == 0x00000e00)
28654 /* T-instruction: positive 8-bit offset. */
28657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28658 _("offset out of range"));
28666 /* Positive 12-bit or negative 8-bit offset. */
28667 unsigned int limit
;
28668 if ((offsetT
) value
>= 0)
28670 newval
|= (1 << 23);
28680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28681 _("offset out of range"));
28688 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28689 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28692 case BFD_RELOC_ARM_SHIFT_IMM
:
28693 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28696 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28699 _("shift expression is too large"));
28704 /* Shifts of zero must be done as lsl. */
28706 else if (value
== 32)
28708 newval
&= 0xfffff07f;
28709 newval
|= (value
& 0x1f) << 7;
28710 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28713 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28714 case BFD_RELOC_ARM_T32_ADD_IMM
:
28715 case BFD_RELOC_ARM_T32_IMM12
:
28716 case BFD_RELOC_ARM_T32_ADD_PC12
:
28717 /* We claim that this fixup has been processed here,
28718 even if in fact we generate an error because we do
28719 not have a reloc for it, so tc_gen_reloc will reject it. */
28723 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28726 _("undefined symbol %s used as an immediate value"),
28727 S_GET_NAME (fixP
->fx_addsy
));
28731 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28733 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28736 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28737 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28738 Thumb2 modified immediate encoding (T2). */
28739 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28740 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28742 newimm
= encode_thumb32_immediate (value
);
28743 if (newimm
== (unsigned int) FAIL
)
28744 newimm
= thumb32_negate_data_op (&newval
, value
);
28746 if (newimm
== (unsigned int) FAIL
)
28748 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28750 /* Turn add/sum into addw/subw. */
28751 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28752 newval
= (newval
& 0xfeffffff) | 0x02000000;
28753 /* No flat 12-bit imm encoding for addsw/subsw. */
28754 if ((newval
& 0x00100000) == 0)
28756 /* 12 bit immediate for addw/subw. */
28757 if ((offsetT
) value
< 0)
28760 newval
^= 0x00a00000;
28763 newimm
= (unsigned int) FAIL
;
28770 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28771 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28772 disassembling, MOV is preferred when there is no encoding
28774 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28775 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28776 but with the Rn field [19:16] set to 1111. */
28777 && (((newval
>> 16) & 0xf) == 0xf)
28778 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28779 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28780 && value
<= 0xffff)
28782 /* Toggle bit[25] to change encoding from T2 to T3. */
28784 /* Clear bits[19:16]. */
28785 newval
&= 0xfff0ffff;
28786 /* Encoding high 4bits imm. Code below will encode the
28787 remaining low 12bits. */
28788 newval
|= (value
& 0x0000f000) << 4;
28789 newimm
= value
& 0x00000fff;
28794 if (newimm
== (unsigned int)FAIL
)
28796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28797 _("invalid constant (%lx) after fixup"),
28798 (unsigned long) value
);
28802 newval
|= (newimm
& 0x800) << 15;
28803 newval
|= (newimm
& 0x700) << 4;
28804 newval
|= (newimm
& 0x0ff);
28806 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28807 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28810 case BFD_RELOC_ARM_SMC
:
28812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28813 _("invalid smc expression"));
28815 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28816 newval
|= (value
& 0xf);
28817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28820 case BFD_RELOC_ARM_HVC
:
28821 if (value
> 0xffff)
28822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28823 _("invalid hvc expression"));
28824 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28825 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28826 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28829 case BFD_RELOC_ARM_SWI
:
28830 if (fixP
->tc_fix_data
!= 0)
28833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28834 _("invalid swi expression"));
28835 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28841 if (value
> 0x00ffffff)
28842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28843 _("invalid swi expression"));
28844 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28846 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28850 case BFD_RELOC_ARM_MULTI
:
28851 if (value
> 0xffff)
28852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28853 _("invalid expression in load/store multiple"));
28854 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28855 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28859 case BFD_RELOC_ARM_PCREL_CALL
:
28861 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28863 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28864 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28865 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28866 /* Flip the bl to blx. This is a simple flip
28867 bit here because we generate PCREL_CALL for
28868 unconditional bls. */
28870 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28871 newval
= newval
| 0x10000000;
28872 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28878 goto arm_branch_common
;
28880 case BFD_RELOC_ARM_PCREL_JUMP
:
28881 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28883 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28884 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28885 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28887 /* This would map to a bl<cond>, b<cond>,
28888 b<always> to a Thumb function. We
28889 need to force a relocation for this particular
28891 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28894 /* Fall through. */
28896 case BFD_RELOC_ARM_PLT32
:
28898 case BFD_RELOC_ARM_PCREL_BRANCH
:
28900 goto arm_branch_common
;
28902 case BFD_RELOC_ARM_PCREL_BLX
:
28905 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28907 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28908 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28909 && ARM_IS_FUNC (fixP
->fx_addsy
))
28911 /* Flip the blx to a bl and warn. */
28912 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28913 newval
= 0xeb000000;
28914 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28915 _("blx to '%s' an ARM ISA state function changed to bl"),
28917 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28923 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28924 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28928 /* We are going to store value (shifted right by two) in the
28929 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28930 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28934 _("misaligned branch destination"));
28935 if ((value
& 0xfe000000) != 0
28936 && (value
& 0xfe000000) != 0xfe000000)
28937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28941 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28942 newval
|= (value
>> 2) & 0x00ffffff;
28943 /* Set the H bit on BLX instructions. */
28947 newval
|= 0x01000000;
28949 newval
&= ~0x01000000;
28951 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28955 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28956 /* CBZ can only branch forward. */
28958 /* Attempts to use CBZ to branch to the next instruction
28959 (which, strictly speaking, are prohibited) will be turned into
28962 FIXME: It may be better to remove the instruction completely and
28963 perform relaxation. */
28964 if ((offsetT
) value
== -2)
28966 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28967 newval
= 0xbf00; /* NOP encoding T1 */
28968 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28977 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28978 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28984 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28985 if (out_of_range_p (value
, 8))
28986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28990 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28991 newval
|= (value
& 0x1ff) >> 1;
28992 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28996 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28997 if (out_of_range_p (value
, 11))
28998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29002 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29003 newval
|= (value
& 0xfff) >> 1;
29004 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29008 /* This relocation is misnamed, it should be BRANCH21. */
29009 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29011 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29012 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29013 && ARM_IS_FUNC (fixP
->fx_addsy
)
29014 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29016 /* Force a relocation for a branch 20 bits wide. */
29019 if (out_of_range_p (value
, 20))
29020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29021 _("conditional branch out of range"));
29023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29026 addressT S
, J1
, J2
, lo
, hi
;
29028 S
= (value
& 0x00100000) >> 20;
29029 J2
= (value
& 0x00080000) >> 19;
29030 J1
= (value
& 0x00040000) >> 18;
29031 hi
= (value
& 0x0003f000) >> 12;
29032 lo
= (value
& 0x00000ffe) >> 1;
29034 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29035 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29036 newval
|= (S
<< 10) | hi
;
29037 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29038 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29039 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29043 case BFD_RELOC_THUMB_PCREL_BLX
:
29044 /* If there is a blx from a thumb state function to
29045 another thumb function flip this to a bl and warn
29049 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29050 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29051 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29053 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29054 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29055 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29057 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29058 newval
= newval
| 0x1000;
29059 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29060 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29065 goto thumb_bl_common
;
29067 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29068 /* A bl from Thumb state ISA to an internal ARM state function
29069 is converted to a blx. */
29071 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29072 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29073 && ARM_IS_FUNC (fixP
->fx_addsy
)
29074 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29076 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29077 newval
= newval
& ~0x1000;
29078 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29079 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29085 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29086 /* For a BLX instruction, make sure that the relocation is rounded up
29087 to a word boundary. This follows the semantics of the instruction
29088 which specifies that bit 1 of the target address will come from bit
29089 1 of the base address. */
29090 value
= (value
+ 3) & ~ 3;
29093 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29094 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29095 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29098 if (out_of_range_p (value
, 22))
29100 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29102 else if (out_of_range_p (value
, 24))
29103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29104 _("Thumb2 branch out of range"));
29107 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29108 encode_thumb2_b_bl_offset (buf
, value
);
29112 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29113 if (out_of_range_p (value
, 24))
29114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29116 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29117 encode_thumb2_b_bl_offset (buf
, value
);
29122 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29127 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29128 md_number_to_chars (buf
, value
, 2);
29132 case BFD_RELOC_ARM_TLS_CALL
:
29133 case BFD_RELOC_ARM_THM_TLS_CALL
:
29134 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29135 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29136 case BFD_RELOC_ARM_TLS_GOTDESC
:
29137 case BFD_RELOC_ARM_TLS_GD32
:
29138 case BFD_RELOC_ARM_TLS_LE32
:
29139 case BFD_RELOC_ARM_TLS_IE32
:
29140 case BFD_RELOC_ARM_TLS_LDM32
:
29141 case BFD_RELOC_ARM_TLS_LDO32
:
29142 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29145 /* Same handling as above, but with the arm_fdpic guard. */
29146 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29147 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29148 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29151 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29156 _("Relocation supported only in FDPIC mode"));
29160 case BFD_RELOC_ARM_GOT32
:
29161 case BFD_RELOC_ARM_GOTOFF
:
29164 case BFD_RELOC_ARM_GOT_PREL
:
29165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29166 md_number_to_chars (buf
, value
, 4);
29169 case BFD_RELOC_ARM_TARGET2
:
29170 /* TARGET2 is not partial-inplace, so we need to write the
29171 addend here for REL targets, because it won't be written out
29172 during reloc processing later. */
29173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29174 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29177 /* Relocations for FDPIC. */
29178 case BFD_RELOC_ARM_GOTFUNCDESC
:
29179 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29180 case BFD_RELOC_ARM_FUNCDESC
:
29183 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29184 md_number_to_chars (buf
, 0, 4);
29188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29189 _("Relocation supported only in FDPIC mode"));
29194 case BFD_RELOC_RVA
:
29196 case BFD_RELOC_ARM_TARGET1
:
29197 case BFD_RELOC_ARM_ROSEGREL32
:
29198 case BFD_RELOC_ARM_SBREL32
:
29199 case BFD_RELOC_32_PCREL
:
29201 case BFD_RELOC_32_SECREL
:
29203 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29205 /* For WinCE we only do this for pcrel fixups. */
29206 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29208 md_number_to_chars (buf
, value
, 4);
29212 case BFD_RELOC_ARM_PREL31
:
29213 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29215 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29216 if ((value
^ (value
>> 1)) & 0x40000000)
29218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29219 _("rel31 relocation overflow"));
29221 newval
|= value
& 0x7fffffff;
29222 md_number_to_chars (buf
, newval
, 4);
29227 case BFD_RELOC_ARM_CP_OFF_IMM
:
29228 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29229 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29230 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29231 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29233 newval
= get_thumb32_insn (buf
);
29234 if ((newval
& 0x0f200f00) == 0x0d000900)
29236 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29237 has permitted values that are multiples of 2, in the range -510
29239 if (value
+ 510 > 510 + 510 || (value
& 1))
29240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29241 _("co-processor offset out of range"));
29243 else if ((newval
& 0xfe001f80) == 0xec000f80)
29245 if (value
+ 511 > 512 + 511 || (value
& 3))
29246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29247 _("co-processor offset out of range"));
29249 else if (value
+ 1023 > 1023 + 1023 || (value
& 3))
29250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29251 _("co-processor offset out of range"));
29253 sign
= (offsetT
) value
> 0;
29254 if ((offsetT
) value
< 0)
29256 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29257 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29258 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29260 newval
= get_thumb32_insn (buf
);
29263 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29264 newval
&= 0xffffff80;
29266 newval
&= 0xffffff00;
29270 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29271 newval
&= 0xff7fff80;
29273 newval
&= 0xff7fff00;
29274 if ((newval
& 0x0f200f00) == 0x0d000900)
29276 /* This is a fp16 vstr/vldr.
29278 It requires the immediate offset in the instruction is shifted
29279 left by 1 to be a half-word offset.
29281 Here, left shift by 1 first, and later right shift by 2
29282 should get the right offset. */
29285 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29287 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29288 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29289 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29291 put_thumb32_insn (buf
, newval
);
29294 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29295 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29296 if (value
+ 255 > 255 + 255)
29297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29298 _("co-processor offset out of range"));
29300 goto cp_off_common
;
29302 case BFD_RELOC_ARM_THUMB_OFFSET
:
29303 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29304 /* Exactly what ranges, and where the offset is inserted depends
29305 on the type of instruction, we can establish this from the
29307 switch (newval
>> 12)
29309 case 4: /* PC load. */
29310 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29311 forced to zero for these loads; md_pcrel_from has already
29312 compensated for this. */
29314 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29315 _("invalid offset, target not word aligned (0x%08lX)"),
29316 (((unsigned long) fixP
->fx_frag
->fr_address
29317 + (unsigned long) fixP
->fx_where
) & ~3)
29318 + (unsigned long) value
);
29319 else if (get_recorded_alignment (seg
) < 2)
29320 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29321 _("section does not have enough alignment to ensure safe PC-relative loads"));
29323 if (value
& ~0x3fc)
29324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29325 _("invalid offset, value too big (0x%08lX)"),
29328 newval
|= value
>> 2;
29331 case 9: /* SP load/store. */
29332 if (value
& ~0x3fc)
29333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29334 _("invalid offset, value too big (0x%08lX)"),
29336 newval
|= value
>> 2;
29339 case 6: /* Word load/store. */
29341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29342 _("invalid offset, value too big (0x%08lX)"),
29344 newval
|= value
<< 4; /* 6 - 2. */
29347 case 7: /* Byte load/store. */
29349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29350 _("invalid offset, value too big (0x%08lX)"),
29352 newval
|= value
<< 6;
29355 case 8: /* Halfword load/store. */
29357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29358 _("invalid offset, value too big (0x%08lX)"),
29360 newval
|= value
<< 5; /* 6 - 1. */
29364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29365 "Unable to process relocation for thumb opcode: %lx",
29366 (unsigned long) newval
);
29369 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29372 case BFD_RELOC_ARM_THUMB_ADD
:
29373 /* This is a complicated relocation, since we use it for all of
29374 the following immediate relocations:
29378 9bit ADD/SUB SP word-aligned
29379 10bit ADD PC/SP word-aligned
29381 The type of instruction being processed is encoded in the
29388 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29390 int rd
= (newval
>> 4) & 0xf;
29391 int rs
= newval
& 0xf;
29392 int subtract
= !!(newval
& 0x8000);
29394 /* Check for HI regs, only very restricted cases allowed:
29395 Adjusting SP, and using PC or SP to get an address. */
29396 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29397 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29399 _("invalid Hi register with immediate"));
29401 /* If value is negative, choose the opposite instruction. */
29402 if ((offsetT
) value
< 0)
29405 subtract
= !subtract
;
29406 if ((offsetT
) value
< 0)
29407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29408 _("immediate value out of range"));
29413 if (value
& ~0x1fc)
29414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29415 _("invalid immediate for stack address calculation"));
29416 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29417 newval
|= value
>> 2;
29419 else if (rs
== REG_PC
|| rs
== REG_SP
)
29421 /* PR gas/18541. If the addition is for a defined symbol
29422 within range of an ADR instruction then accept it. */
29425 && fixP
->fx_addsy
!= NULL
)
29429 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29430 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29431 || S_IS_WEAK (fixP
->fx_addsy
))
29433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29434 _("address calculation needs a strongly defined nearby symbol"));
29438 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29440 /* Round up to the next 4-byte boundary. */
29445 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29450 _("symbol too far away"));
29460 if (subtract
|| value
& ~0x3fc)
29461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29462 _("invalid immediate for address calculation (value = 0x%08lX)"),
29463 (unsigned long) (subtract
? - value
: value
));
29464 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29466 newval
|= value
>> 2;
29471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29472 _("immediate value out of range"));
29473 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29474 newval
|= (rd
<< 8) | value
;
29479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29480 _("immediate value out of range"));
29481 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29482 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29485 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29488 case BFD_RELOC_ARM_THUMB_IMM
:
29489 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29492 _("invalid immediate: %ld is out of range"),
29495 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29498 case BFD_RELOC_ARM_THUMB_SHIFT
:
29499 /* 5bit shift value (0..32). LSL cannot take 32. */
29500 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29501 temp
= newval
& 0xf800;
29502 if (value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29504 _("invalid shift value: %ld"), (long) value
);
29505 /* Shifts of zero must be encoded as LSL. */
29507 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29508 /* Shifts of 32 are encoded as zero. */
29509 else if (value
== 32)
29511 newval
|= value
<< 6;
29512 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29515 case BFD_RELOC_VTABLE_INHERIT
:
29516 case BFD_RELOC_VTABLE_ENTRY
:
29520 case BFD_RELOC_ARM_MOVW
:
29521 case BFD_RELOC_ARM_MOVT
:
29522 case BFD_RELOC_ARM_THUMB_MOVW
:
29523 case BFD_RELOC_ARM_THUMB_MOVT
:
29524 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29526 /* REL format relocations are limited to a 16-bit addend. */
29527 if (!fixP
->fx_done
)
29529 if (value
+ 0x8000 > 0x7fff + 0x8000)
29530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29531 _("offset out of range"));
29533 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29534 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29539 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29540 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29542 newval
= get_thumb32_insn (buf
);
29543 newval
&= 0xfbf08f00;
29544 newval
|= (value
& 0xf000) << 4;
29545 newval
|= (value
& 0x0800) << 15;
29546 newval
|= (value
& 0x0700) << 4;
29547 newval
|= (value
& 0x00ff);
29548 put_thumb32_insn (buf
, newval
);
29552 newval
= md_chars_to_number (buf
, 4);
29553 newval
&= 0xfff0f000;
29554 newval
|= value
& 0x0fff;
29555 newval
|= (value
& 0xf000) << 4;
29556 md_number_to_chars (buf
, newval
, 4);
29561 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29562 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29563 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29564 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29565 gas_assert (!fixP
->fx_done
);
29568 bfd_boolean is_mov
;
29569 bfd_vma encoded_addend
= value
;
29571 /* Check that addend can be encoded in instruction. */
29572 if (!seg
->use_rela_p
&& value
> 255)
29573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29574 _("the offset 0x%08lX is not representable"),
29575 (unsigned long) encoded_addend
);
29577 /* Extract the instruction. */
29578 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29579 is_mov
= (insn
& 0xf800) == 0x2000;
29584 if (!seg
->use_rela_p
)
29585 insn
|= encoded_addend
;
29591 /* Extract the instruction. */
29592 /* Encoding is the following
29597 /* The following conditions must be true :
29602 rd
= (insn
>> 4) & 0xf;
29604 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29606 _("Unable to process relocation for thumb opcode: %lx"),
29607 (unsigned long) insn
);
29609 /* Encode as ADD immediate8 thumb 1 code. */
29610 insn
= 0x3000 | (rd
<< 8);
29612 /* Place the encoded addend into the first 8 bits of the
29614 if (!seg
->use_rela_p
)
29615 insn
|= encoded_addend
;
29618 /* Update the instruction. */
29619 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29623 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29624 case BFD_RELOC_ARM_ALU_PC_G0
:
29625 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29626 case BFD_RELOC_ARM_ALU_PC_G1
:
29627 case BFD_RELOC_ARM_ALU_PC_G2
:
29628 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29629 case BFD_RELOC_ARM_ALU_SB_G0
:
29630 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29631 case BFD_RELOC_ARM_ALU_SB_G1
:
29632 case BFD_RELOC_ARM_ALU_SB_G2
:
29633 gas_assert (!fixP
->fx_done
);
29634 if (!seg
->use_rela_p
)
29637 bfd_vma encoded_addend
;
29638 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29640 /* Check that the absolute value of the addend can be
29641 expressed as an 8-bit constant plus a rotation. */
29642 encoded_addend
= encode_arm_immediate (addend_abs
);
29643 if (encoded_addend
== (unsigned int) FAIL
)
29644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29645 _("the offset 0x%08lX is not representable"),
29646 (unsigned long) addend_abs
);
29648 /* Extract the instruction. */
29649 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29651 /* If the addend is positive, use an ADD instruction.
29652 Otherwise use a SUB. Take care not to destroy the S bit. */
29653 insn
&= 0xff1fffff;
29654 if ((offsetT
) value
< 0)
29659 /* Place the encoded addend into the first 12 bits of the
29661 insn
&= 0xfffff000;
29662 insn
|= encoded_addend
;
29664 /* Update the instruction. */
29665 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29669 case BFD_RELOC_ARM_LDR_PC_G0
:
29670 case BFD_RELOC_ARM_LDR_PC_G1
:
29671 case BFD_RELOC_ARM_LDR_PC_G2
:
29672 case BFD_RELOC_ARM_LDR_SB_G0
:
29673 case BFD_RELOC_ARM_LDR_SB_G1
:
29674 case BFD_RELOC_ARM_LDR_SB_G2
:
29675 gas_assert (!fixP
->fx_done
);
29676 if (!seg
->use_rela_p
)
29679 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29681 /* Check that the absolute value of the addend can be
29682 encoded in 12 bits. */
29683 if (addend_abs
>= 0x1000)
29684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29685 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29686 (unsigned long) addend_abs
);
29688 /* Extract the instruction. */
29689 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29691 /* If the addend is negative, clear bit 23 of the instruction.
29692 Otherwise set it. */
29693 if ((offsetT
) value
< 0)
29694 insn
&= ~(1 << 23);
29698 /* Place the absolute value of the addend into the first 12 bits
29699 of the instruction. */
29700 insn
&= 0xfffff000;
29701 insn
|= addend_abs
;
29703 /* Update the instruction. */
29704 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29708 case BFD_RELOC_ARM_LDRS_PC_G0
:
29709 case BFD_RELOC_ARM_LDRS_PC_G1
:
29710 case BFD_RELOC_ARM_LDRS_PC_G2
:
29711 case BFD_RELOC_ARM_LDRS_SB_G0
:
29712 case BFD_RELOC_ARM_LDRS_SB_G1
:
29713 case BFD_RELOC_ARM_LDRS_SB_G2
:
29714 gas_assert (!fixP
->fx_done
);
29715 if (!seg
->use_rela_p
)
29718 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29720 /* Check that the absolute value of the addend can be
29721 encoded in 8 bits. */
29722 if (addend_abs
>= 0x100)
29723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29724 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29725 (unsigned long) addend_abs
);
29727 /* Extract the instruction. */
29728 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29730 /* If the addend is negative, clear bit 23 of the instruction.
29731 Otherwise set it. */
29732 if ((offsetT
) value
< 0)
29733 insn
&= ~(1 << 23);
29737 /* Place the first four bits of the absolute value of the addend
29738 into the first 4 bits of the instruction, and the remaining
29739 four into bits 8 .. 11. */
29740 insn
&= 0xfffff0f0;
29741 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29743 /* Update the instruction. */
29744 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29748 case BFD_RELOC_ARM_LDC_PC_G0
:
29749 case BFD_RELOC_ARM_LDC_PC_G1
:
29750 case BFD_RELOC_ARM_LDC_PC_G2
:
29751 case BFD_RELOC_ARM_LDC_SB_G0
:
29752 case BFD_RELOC_ARM_LDC_SB_G1
:
29753 case BFD_RELOC_ARM_LDC_SB_G2
:
29754 gas_assert (!fixP
->fx_done
);
29755 if (!seg
->use_rela_p
)
29758 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29760 /* Check that the absolute value of the addend is a multiple of
29761 four and, when divided by four, fits in 8 bits. */
29762 if (addend_abs
& 0x3)
29763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29764 _("bad offset 0x%08lX (must be word-aligned)"),
29765 (unsigned long) addend_abs
);
29767 if ((addend_abs
>> 2) > 0xff)
29768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29769 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29770 (unsigned long) addend_abs
);
29772 /* Extract the instruction. */
29773 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29775 /* If the addend is negative, clear bit 23 of the instruction.
29776 Otherwise set it. */
29777 if ((offsetT
) value
< 0)
29778 insn
&= ~(1 << 23);
29782 /* Place the addend (divided by four) into the first eight
29783 bits of the instruction. */
29784 insn
&= 0xfffffff0;
29785 insn
|= addend_abs
>> 2;
29787 /* Update the instruction. */
29788 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29792 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29794 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29795 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29796 && ARM_IS_FUNC (fixP
->fx_addsy
)
29797 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29799 /* Force a relocation for a branch 5 bits wide. */
29802 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29806 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29808 addressT boff
= value
>> 1;
29810 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29811 newval
|= (boff
<< 7);
29812 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29816 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29818 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29819 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29820 && ARM_IS_FUNC (fixP
->fx_addsy
)
29821 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29825 if ((value
& ~0x7f) && ((value
& ~0x3f) != (valueT
) ~0x3f))
29826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29827 _("branch out of range"));
29829 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29831 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29833 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29834 addressT diff
= value
- boff
;
29838 newval
|= 1 << 1; /* T bit. */
29840 else if (diff
!= 2)
29842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29843 _("out of range label-relative fixup value"));
29845 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29849 case BFD_RELOC_ARM_THUMB_BF17
:
29851 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29852 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29853 && ARM_IS_FUNC (fixP
->fx_addsy
)
29854 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29856 /* Force a relocation for a branch 17 bits wide. */
29860 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29864 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29867 addressT immA
, immB
, immC
;
29869 immA
= (value
& 0x0001f000) >> 12;
29870 immB
= (value
& 0x00000ffc) >> 2;
29871 immC
= (value
& 0x00000002) >> 1;
29873 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29874 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29876 newval2
|= (immC
<< 11) | (immB
<< 1);
29877 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29878 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29882 case BFD_RELOC_ARM_THUMB_BF19
:
29884 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29885 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29886 && ARM_IS_FUNC (fixP
->fx_addsy
)
29887 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29889 /* Force a relocation for a branch 19 bits wide. */
29893 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29897 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29900 addressT immA
, immB
, immC
;
29902 immA
= (value
& 0x0007f000) >> 12;
29903 immB
= (value
& 0x00000ffc) >> 2;
29904 immC
= (value
& 0x00000002) >> 1;
29906 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29907 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29909 newval2
|= (immC
<< 11) | (immB
<< 1);
29910 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29911 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29915 case BFD_RELOC_ARM_THUMB_BF13
:
29917 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29918 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29919 && ARM_IS_FUNC (fixP
->fx_addsy
)
29920 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29922 /* Force a relocation for a branch 13 bits wide. */
29926 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29930 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29933 addressT immA
, immB
, immC
;
29935 immA
= (value
& 0x00001000) >> 12;
29936 immB
= (value
& 0x00000ffc) >> 2;
29937 immC
= (value
& 0x00000002) >> 1;
29939 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29940 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29942 newval2
|= (immC
<< 11) | (immB
<< 1);
29943 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29944 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29948 case BFD_RELOC_ARM_THUMB_LOOP12
:
29950 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29951 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29952 && ARM_IS_FUNC (fixP
->fx_addsy
)
29953 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29955 /* Force a relocation for a branch 12 bits wide. */
29959 bfd_vma insn
= get_thumb32_insn (buf
);
29960 /* le lr, <label>, le <label> or letp lr, <label> */
29961 if (((insn
& 0xffffffff) == 0xf00fc001)
29962 || ((insn
& 0xffffffff) == 0xf02fc001)
29963 || ((insn
& 0xffffffff) == 0xf01fc001))
29966 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29969 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29971 addressT imml
, immh
;
29973 immh
= (value
& 0x00000ffc) >> 2;
29974 imml
= (value
& 0x00000002) >> 1;
29976 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29977 newval
|= (imml
<< 11) | (immh
<< 1);
29978 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29982 case BFD_RELOC_ARM_V4BX
:
29983 /* This will need to go in the object file. */
29987 case BFD_RELOC_UNUSED
:
29989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29990 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29994 /* Translate internal representation of relocation info to BFD target
29998 tc_gen_reloc (asection
*section
, fixS
*fixp
)
30001 bfd_reloc_code_real_type code
;
30003 reloc
= XNEW (arelent
);
30005 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
30006 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
30007 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
30009 if (fixp
->fx_pcrel
)
30011 if (section
->use_rela_p
)
30012 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30014 fixp
->fx_offset
= reloc
->address
;
30016 reloc
->addend
= fixp
->fx_offset
;
30018 switch (fixp
->fx_r_type
)
30021 if (fixp
->fx_pcrel
)
30023 code
= BFD_RELOC_8_PCREL
;
30026 /* Fall through. */
30029 if (fixp
->fx_pcrel
)
30031 code
= BFD_RELOC_16_PCREL
;
30034 /* Fall through. */
30037 if (fixp
->fx_pcrel
)
30039 code
= BFD_RELOC_32_PCREL
;
30042 /* Fall through. */
30044 case BFD_RELOC_ARM_MOVW
:
30045 if (fixp
->fx_pcrel
)
30047 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30050 /* Fall through. */
30052 case BFD_RELOC_ARM_MOVT
:
30053 if (fixp
->fx_pcrel
)
30055 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30058 /* Fall through. */
30060 case BFD_RELOC_ARM_THUMB_MOVW
:
30061 if (fixp
->fx_pcrel
)
30063 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30066 /* Fall through. */
30068 case BFD_RELOC_ARM_THUMB_MOVT
:
30069 if (fixp
->fx_pcrel
)
30071 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30074 /* Fall through. */
30076 case BFD_RELOC_NONE
:
30077 case BFD_RELOC_ARM_PCREL_BRANCH
:
30078 case BFD_RELOC_ARM_PCREL_BLX
:
30079 case BFD_RELOC_RVA
:
30080 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30081 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30082 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30083 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30084 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30085 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30086 case BFD_RELOC_VTABLE_ENTRY
:
30087 case BFD_RELOC_VTABLE_INHERIT
:
30089 case BFD_RELOC_32_SECREL
:
30091 code
= fixp
->fx_r_type
;
30094 case BFD_RELOC_THUMB_PCREL_BLX
:
30096 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30097 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30100 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30103 case BFD_RELOC_ARM_LITERAL
:
30104 case BFD_RELOC_ARM_HWLITERAL
:
30105 /* If this is called then the a literal has
30106 been referenced across a section boundary. */
30107 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30108 _("literal referenced across section boundary"));
30112 case BFD_RELOC_ARM_TLS_CALL
:
30113 case BFD_RELOC_ARM_THM_TLS_CALL
:
30114 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30115 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30116 case BFD_RELOC_ARM_GOT32
:
30117 case BFD_RELOC_ARM_GOTOFF
:
30118 case BFD_RELOC_ARM_GOT_PREL
:
30119 case BFD_RELOC_ARM_PLT32
:
30120 case BFD_RELOC_ARM_TARGET1
:
30121 case BFD_RELOC_ARM_ROSEGREL32
:
30122 case BFD_RELOC_ARM_SBREL32
:
30123 case BFD_RELOC_ARM_PREL31
:
30124 case BFD_RELOC_ARM_TARGET2
:
30125 case BFD_RELOC_ARM_TLS_LDO32
:
30126 case BFD_RELOC_ARM_PCREL_CALL
:
30127 case BFD_RELOC_ARM_PCREL_JUMP
:
30128 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30129 case BFD_RELOC_ARM_ALU_PC_G0
:
30130 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30131 case BFD_RELOC_ARM_ALU_PC_G1
:
30132 case BFD_RELOC_ARM_ALU_PC_G2
:
30133 case BFD_RELOC_ARM_LDR_PC_G0
:
30134 case BFD_RELOC_ARM_LDR_PC_G1
:
30135 case BFD_RELOC_ARM_LDR_PC_G2
:
30136 case BFD_RELOC_ARM_LDRS_PC_G0
:
30137 case BFD_RELOC_ARM_LDRS_PC_G1
:
30138 case BFD_RELOC_ARM_LDRS_PC_G2
:
30139 case BFD_RELOC_ARM_LDC_PC_G0
:
30140 case BFD_RELOC_ARM_LDC_PC_G1
:
30141 case BFD_RELOC_ARM_LDC_PC_G2
:
30142 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30143 case BFD_RELOC_ARM_ALU_SB_G0
:
30144 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30145 case BFD_RELOC_ARM_ALU_SB_G1
:
30146 case BFD_RELOC_ARM_ALU_SB_G2
:
30147 case BFD_RELOC_ARM_LDR_SB_G0
:
30148 case BFD_RELOC_ARM_LDR_SB_G1
:
30149 case BFD_RELOC_ARM_LDR_SB_G2
:
30150 case BFD_RELOC_ARM_LDRS_SB_G0
:
30151 case BFD_RELOC_ARM_LDRS_SB_G1
:
30152 case BFD_RELOC_ARM_LDRS_SB_G2
:
30153 case BFD_RELOC_ARM_LDC_SB_G0
:
30154 case BFD_RELOC_ARM_LDC_SB_G1
:
30155 case BFD_RELOC_ARM_LDC_SB_G2
:
30156 case BFD_RELOC_ARM_V4BX
:
30157 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30158 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30159 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30160 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30161 case BFD_RELOC_ARM_GOTFUNCDESC
:
30162 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30163 case BFD_RELOC_ARM_FUNCDESC
:
30164 case BFD_RELOC_ARM_THUMB_BF17
:
30165 case BFD_RELOC_ARM_THUMB_BF19
:
30166 case BFD_RELOC_ARM_THUMB_BF13
:
30167 code
= fixp
->fx_r_type
;
30170 case BFD_RELOC_ARM_TLS_GOTDESC
:
30171 case BFD_RELOC_ARM_TLS_GD32
:
30172 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30173 case BFD_RELOC_ARM_TLS_LE32
:
30174 case BFD_RELOC_ARM_TLS_IE32
:
30175 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30176 case BFD_RELOC_ARM_TLS_LDM32
:
30177 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30178 /* BFD will include the symbol's address in the addend.
30179 But we don't want that, so subtract it out again here. */
30180 if (!S_IS_COMMON (fixp
->fx_addsy
))
30181 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30182 code
= fixp
->fx_r_type
;
30186 case BFD_RELOC_ARM_IMMEDIATE
:
30187 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30188 _("internal relocation (type: IMMEDIATE) not fixed up"));
30191 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30193 _("ADRL used for a symbol not defined in the same file"));
30196 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30197 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30198 case BFD_RELOC_ARM_THUMB_LOOP12
:
30199 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30200 _("%s used for a symbol not defined in the same file"),
30201 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30204 case BFD_RELOC_ARM_OFFSET_IMM
:
30205 if (section
->use_rela_p
)
30207 code
= fixp
->fx_r_type
;
30211 if (fixp
->fx_addsy
!= NULL
30212 && !S_IS_DEFINED (fixp
->fx_addsy
)
30213 && S_IS_LOCAL (fixp
->fx_addsy
))
30215 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30216 _("undefined local label `%s'"),
30217 S_GET_NAME (fixp
->fx_addsy
));
30221 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30222 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30229 switch (fixp
->fx_r_type
)
30231 case BFD_RELOC_NONE
: type
= "NONE"; break;
30232 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30233 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30234 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30235 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30236 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30237 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30238 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30239 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30240 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30241 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30242 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30243 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30244 default: type
= _("<unknown>"); break;
30246 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30247 _("cannot represent %s relocation in this object file format"),
30254 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30256 && fixp
->fx_addsy
== GOT_symbol
)
30258 code
= BFD_RELOC_ARM_GOTPC
;
30259 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30263 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30265 if (reloc
->howto
== NULL
)
30267 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30268 _("cannot represent %s relocation in this object file format"),
30269 bfd_get_reloc_code_name (code
));
30273 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30274 vtable entry to be used in the relocation's section offset. */
30275 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30276 reloc
->address
= fixp
->fx_offset
;
30281 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30284 cons_fix_new_arm (fragS
* frag
,
30288 bfd_reloc_code_real_type reloc
)
30293 FIXME: @@ Should look at CPU word size. */
30297 reloc
= BFD_RELOC_8
;
30300 reloc
= BFD_RELOC_16
;
30304 reloc
= BFD_RELOC_32
;
30307 reloc
= BFD_RELOC_64
;
30312 if (exp
->X_op
== O_secrel
)
30314 exp
->X_op
= O_symbol
;
30315 reloc
= BFD_RELOC_32_SECREL
;
30319 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30322 #if defined (OBJ_COFF)
30324 arm_validate_fix (fixS
* fixP
)
30326 /* If the destination of the branch is a defined symbol which does not have
30327 the THUMB_FUNC attribute, then we must be calling a function which has
30328 the (interfacearm) attribute. We look for the Thumb entry point to that
30329 function and change the branch to refer to that function instead. */
30330 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30331 && fixP
->fx_addsy
!= NULL
30332 && S_IS_DEFINED (fixP
->fx_addsy
)
30333 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30335 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30342 arm_force_relocation (struct fix
* fixp
)
30344 #if defined (OBJ_COFF) && defined (TE_PE)
30345 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30349 /* In case we have a call or a branch to a function in ARM ISA mode from
30350 a thumb function or vice-versa force the relocation. These relocations
30351 are cleared off for some cores that might have blx and simple transformations
30355 switch (fixp
->fx_r_type
)
30357 case BFD_RELOC_ARM_PCREL_JUMP
:
30358 case BFD_RELOC_ARM_PCREL_CALL
:
30359 case BFD_RELOC_THUMB_PCREL_BLX
:
30360 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30364 case BFD_RELOC_ARM_PCREL_BLX
:
30365 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30366 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30367 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30368 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30377 /* Resolve these relocations even if the symbol is extern or weak.
30378 Technically this is probably wrong due to symbol preemption.
30379 In practice these relocations do not have enough range to be useful
30380 at dynamic link time, and some code (e.g. in the Linux kernel)
30381 expects these references to be resolved. */
30382 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30384 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30385 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30386 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30387 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30388 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30389 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30390 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30391 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30392 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30393 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30394 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30395 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30396 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30399 /* Always leave these relocations for the linker. */
30400 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30401 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30402 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30405 /* Always generate relocations against function symbols. */
30406 if (fixp
->fx_r_type
== BFD_RELOC_32
30408 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30411 return generic_force_reloc (fixp
);
30414 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30415 /* Relocations against function names must be left unadjusted,
30416 so that the linker can use this information to generate interworking
30417 stubs. The MIPS version of this function
30418 also prevents relocations that are mips-16 specific, but I do not
30419 know why it does this.
30422 There is one other problem that ought to be addressed here, but
30423 which currently is not: Taking the address of a label (rather
30424 than a function) and then later jumping to that address. Such
30425 addresses also ought to have their bottom bit set (assuming that
30426 they reside in Thumb code), but at the moment they will not. */
30429 arm_fix_adjustable (fixS
* fixP
)
30431 if (fixP
->fx_addsy
== NULL
)
30434 /* Preserve relocations against symbols with function type. */
30435 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30438 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30439 && fixP
->fx_subsy
== NULL
)
30442 /* We need the symbol name for the VTABLE entries. */
30443 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30444 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30447 /* Don't allow symbols to be discarded on GOT related relocs. */
30448 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30453 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30454 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30455 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30456 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30457 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30458 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30459 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30460 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30461 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30462 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30463 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30464 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30467 /* Similarly for group relocations. */
30468 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30469 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30470 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30473 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30474 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30475 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30476 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30477 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30478 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30479 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30480 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30481 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30484 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30485 offsets, so keep these symbols. */
30486 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30487 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30492 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30496 elf32_arm_target_format (void)
30498 #if defined (TE_VXWORKS)
30499 return (target_big_endian
30500 ? "elf32-bigarm-vxworks"
30501 : "elf32-littlearm-vxworks");
30502 #elif defined (TE_NACL)
30503 return (target_big_endian
30504 ? "elf32-bigarm-nacl"
30505 : "elf32-littlearm-nacl");
30509 if (target_big_endian
)
30510 return "elf32-bigarm-fdpic";
30512 return "elf32-littlearm-fdpic";
30516 if (target_big_endian
)
30517 return "elf32-bigarm";
30519 return "elf32-littlearm";
30525 armelf_frob_symbol (symbolS
* symp
,
30528 elf_frob_symbol (symp
, puntp
);
30532 /* MD interface: Finalization. */
30537 literal_pool
* pool
;
30539 /* Ensure that all the predication blocks are properly closed. */
30540 check_pred_blocks_finished ();
30542 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30544 /* Put it at the end of the relevant section. */
30545 subseg_set (pool
->section
, pool
->sub_section
);
30547 arm_elf_change_section ();
30554 /* Remove any excess mapping symbols generated for alignment frags in
30555 SEC. We may have created a mapping symbol before a zero byte
30556 alignment; remove it if there's a mapping symbol after the
30559 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30560 void *dummy ATTRIBUTE_UNUSED
)
30562 segment_info_type
*seginfo
= seg_info (sec
);
30565 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30568 for (fragp
= seginfo
->frchainP
->frch_root
;
30570 fragp
= fragp
->fr_next
)
30572 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30573 fragS
*next
= fragp
->fr_next
;
30575 /* Variable-sized frags have been converted to fixed size by
30576 this point. But if this was variable-sized to start with,
30577 there will be a fixed-size frag after it. So don't handle
30579 if (sym
== NULL
|| next
== NULL
)
30582 if (S_GET_VALUE (sym
) < next
->fr_address
)
30583 /* Not at the end of this frag. */
30585 know (S_GET_VALUE (sym
) == next
->fr_address
);
30589 if (next
->tc_frag_data
.first_map
!= NULL
)
30591 /* Next frag starts with a mapping symbol. Discard this
30593 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30597 if (next
->fr_next
== NULL
)
30599 /* This mapping symbol is at the end of the section. Discard
30601 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30602 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30606 /* As long as we have empty frags without any mapping symbols,
30608 /* If the next frag is non-empty and does not start with a
30609 mapping symbol, then this mapping symbol is required. */
30610 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30613 next
= next
->fr_next
;
30615 while (next
!= NULL
);
30620 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30624 arm_adjust_symtab (void)
30629 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30631 if (ARM_IS_THUMB (sym
))
30633 if (THUMB_IS_FUNC (sym
))
30635 /* Mark the symbol as a Thumb function. */
30636 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30637 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30638 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30640 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30641 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30643 as_bad (_("%s: unexpected function type: %d"),
30644 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30646 else switch (S_GET_STORAGE_CLASS (sym
))
30649 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30652 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30655 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30663 if (ARM_IS_INTERWORK (sym
))
30664 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30671 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30673 if (ARM_IS_THUMB (sym
))
30675 elf_symbol_type
* elf_sym
;
30677 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30678 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30680 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30681 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30683 /* If it's a .thumb_func, declare it as so,
30684 otherwise tag label as .code 16. */
30685 if (THUMB_IS_FUNC (sym
))
30686 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30687 ST_BRANCH_TO_THUMB
);
30688 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30689 elf_sym
->internal_elf_sym
.st_info
=
30690 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30695 /* Remove any overlapping mapping symbols generated by alignment frags. */
30696 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30697 /* Now do generic ELF adjustments. */
30698 elf_adjust_symtab ();
30702 /* MD interface: Initialization. */
30705 set_constant_flonums (void)
30709 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30710 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30714 /* Auto-select Thumb mode if it's the only available instruction set for the
30715 given architecture. */
30718 autoselect_thumb_from_cpu_variant (void)
30720 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30721 opcode_select (16);
30730 arm_ops_hsh
= str_htab_create ();
30731 arm_cond_hsh
= str_htab_create ();
30732 arm_vcond_hsh
= str_htab_create ();
30733 arm_shift_hsh
= str_htab_create ();
30734 arm_psr_hsh
= str_htab_create ();
30735 arm_v7m_psr_hsh
= str_htab_create ();
30736 arm_reg_hsh
= str_htab_create ();
30737 arm_reloc_hsh
= str_htab_create ();
30738 arm_barrier_opt_hsh
= str_htab_create ();
30740 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30741 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30742 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, insns
+ i
, 0);
30743 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30744 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, conds
+ i
, 0);
30745 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30746 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, vconds
+ i
, 0);
30747 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30748 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, shift_names
+ i
, 0);
30749 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30750 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, psrs
+ i
, 0);
30751 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30752 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30754 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30755 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, reg_names
+ i
, 0);
30757 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30759 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30760 barrier_opt_names
+ i
, 0);
30762 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30764 struct reloc_entry
* entry
= reloc_names
+ i
;
30766 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30767 /* This makes encode_branch() use the EABI versions of this relocation. */
30768 entry
->reloc
= BFD_RELOC_UNUSED
;
30770 str_hash_insert (arm_reloc_hsh
, entry
->name
, entry
, 0);
30774 set_constant_flonums ();
30776 /* Set the cpu variant based on the command-line options. We prefer
30777 -mcpu= over -march= if both are set (as for GCC); and we prefer
30778 -mfpu= over any other way of setting the floating point unit.
30779 Use of legacy options with new options are faulted. */
30782 if (mcpu_cpu_opt
|| march_cpu_opt
)
30783 as_bad (_("use of old and new-style options to set CPU type"));
30785 selected_arch
= *legacy_cpu
;
30787 else if (mcpu_cpu_opt
)
30789 selected_arch
= *mcpu_cpu_opt
;
30790 selected_ext
= *mcpu_ext_opt
;
30792 else if (march_cpu_opt
)
30794 selected_arch
= *march_cpu_opt
;
30795 selected_ext
= *march_ext_opt
;
30797 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30802 as_bad (_("use of old and new-style options to set FPU type"));
30804 selected_fpu
= *legacy_fpu
;
30807 selected_fpu
= *mfpu_opt
;
30810 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30811 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30812 /* Some environments specify a default FPU. If they don't, infer it
30813 from the processor. */
30815 selected_fpu
= *mcpu_fpu_opt
;
30816 else if (march_fpu_opt
)
30817 selected_fpu
= *march_fpu_opt
;
30819 selected_fpu
= fpu_default
;
30823 if (ARM_FEATURE_ZERO (selected_fpu
))
30825 if (!no_cpu_selected ())
30826 selected_fpu
= fpu_default
;
30828 selected_fpu
= fpu_arch_fpa
;
30832 if (ARM_FEATURE_ZERO (selected_arch
))
30834 selected_arch
= cpu_default
;
30835 selected_cpu
= selected_arch
;
30837 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30839 /* Autodection of feature mode: allow all features in cpu_variant but leave
30840 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30841 after all instruction have been processed and we can decide what CPU
30842 should be selected. */
30843 if (ARM_FEATURE_ZERO (selected_arch
))
30844 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30846 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30849 autoselect_thumb_from_cpu_variant ();
30851 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30853 #if defined OBJ_COFF || defined OBJ_ELF
30855 unsigned int flags
= 0;
30857 #if defined OBJ_ELF
30858 flags
= meabi_flags
;
30860 switch (meabi_flags
)
30862 case EF_ARM_EABI_UNKNOWN
:
30864 /* Set the flags in the private structure. */
30865 if (uses_apcs_26
) flags
|= F_APCS26
;
30866 if (support_interwork
) flags
|= F_INTERWORK
;
30867 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30868 if (pic_code
) flags
|= F_PIC
;
30869 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30870 flags
|= F_SOFT_FLOAT
;
30872 switch (mfloat_abi_opt
)
30874 case ARM_FLOAT_ABI_SOFT
:
30875 case ARM_FLOAT_ABI_SOFTFP
:
30876 flags
|= F_SOFT_FLOAT
;
30879 case ARM_FLOAT_ABI_HARD
:
30880 if (flags
& F_SOFT_FLOAT
)
30881 as_bad (_("hard-float conflicts with specified fpu"));
30885 /* Using pure-endian doubles (even if soft-float). */
30886 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30887 flags
|= F_VFP_FLOAT
;
30889 #if defined OBJ_ELF
30890 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30891 flags
|= EF_ARM_MAVERICK_FLOAT
;
30894 case EF_ARM_EABI_VER4
:
30895 case EF_ARM_EABI_VER5
:
30896 /* No additional flags to set. */
30903 bfd_set_private_flags (stdoutput
, flags
);
30905 /* We have run out flags in the COFF header to encode the
30906 status of ATPCS support, so instead we create a dummy,
30907 empty, debug section called .arm.atpcs. */
30912 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30916 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30917 bfd_set_section_size (sec
, 0);
30918 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30924 /* Record the CPU type as well. */
30925 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30926 mach
= bfd_mach_arm_iWMMXt2
;
30927 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30928 mach
= bfd_mach_arm_iWMMXt
;
30929 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30930 mach
= bfd_mach_arm_XScale
;
30931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30932 mach
= bfd_mach_arm_ep9312
;
30933 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30934 mach
= bfd_mach_arm_5TE
;
30935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30938 mach
= bfd_mach_arm_5T
;
30940 mach
= bfd_mach_arm_5
;
30942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30944 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30945 mach
= bfd_mach_arm_4T
;
30947 mach
= bfd_mach_arm_4
;
30949 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30950 mach
= bfd_mach_arm_3M
;
30951 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30952 mach
= bfd_mach_arm_3
;
30953 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30954 mach
= bfd_mach_arm_2a
;
30955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30956 mach
= bfd_mach_arm_2
;
30958 mach
= bfd_mach_arm_unknown
;
30960 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30963 /* Command line processing. */
30966 Invocation line includes a switch not recognized by the base assembler.
30967 See if it's a processor-specific option.
30969 This routine is somewhat complicated by the need for backwards
30970 compatibility (since older releases of gcc can't be changed).
30971 The new options try to make the interface as compatible as
30974 New options (supported) are:
30976 -mcpu=<cpu name> Assemble for selected processor
30977 -march=<architecture name> Assemble for selected architecture
30978 -mfpu=<fpu architecture> Assemble for selected FPU.
30979 -EB/-mbig-endian Big-endian
30980 -EL/-mlittle-endian Little-endian
30981 -k Generate PIC code
30982 -mthumb Start in Thumb mode
30983 -mthumb-interwork Code supports ARM/Thumb interworking
30985 -m[no-]warn-deprecated Warn about deprecated features
30986 -m[no-]warn-syms Warn when symbols match instructions
30988 For now we will also provide support for:
30990 -mapcs-32 32-bit Program counter
30991 -mapcs-26 26-bit Program counter
30992 -macps-float Floats passed in FP registers
30993 -mapcs-reentrant Reentrant code
30995 (sometime these will probably be replaced with -mapcs=<list of options>
30996 and -matpcs=<list of options>)
30998 The remaining options are only supported for back-wards compatibility.
30999 Cpu variants, the arm part is optional:
31000 -m[arm]1 Currently not supported.
31001 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
31002 -m[arm]3 Arm 3 processor
31003 -m[arm]6[xx], Arm 6 processors
31004 -m[arm]7[xx][t][[d]m] Arm 7 processors
31005 -m[arm]8[10] Arm 8 processors
31006 -m[arm]9[20][tdmi] Arm 9 processors
31007 -mstrongarm[110[0]] StrongARM processors
31008 -mxscale XScale processors
31009 -m[arm]v[2345[t[e]]] Arm architectures
31010 -mall All (except the ARM1)
31012 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31013 -mfpe-old (No float load/store multiples)
31014 -mvfpxd VFP Single precision
31016 -mno-fpu Disable all floating point instructions
31018 The following CPU names are recognized:
31019 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31020 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31021 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31022 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31023 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31024 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31025 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31029 const char * md_shortopts
= "m:k";
31031 #ifdef ARM_BI_ENDIAN
31032 #define OPTION_EB (OPTION_MD_BASE + 0)
31033 #define OPTION_EL (OPTION_MD_BASE + 1)
31035 #if TARGET_BYTES_BIG_ENDIAN
31036 #define OPTION_EB (OPTION_MD_BASE + 0)
31038 #define OPTION_EL (OPTION_MD_BASE + 1)
31041 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31042 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31044 struct option md_longopts
[] =
31047 {"EB", no_argument
, NULL
, OPTION_EB
},
31050 {"EL", no_argument
, NULL
, OPTION_EL
},
31052 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31054 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31056 {NULL
, no_argument
, NULL
, 0}
31059 size_t md_longopts_size
= sizeof (md_longopts
);
31061 struct arm_option_table
31063 const char * option
; /* Option name to match. */
31064 const char * help
; /* Help information. */
31065 int * var
; /* Variable to change. */
31066 int value
; /* What to change it to. */
31067 const char * deprecated
; /* If non-null, print this message. */
31070 struct arm_option_table arm_opts
[] =
31072 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31073 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31074 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31075 &support_interwork
, 1, NULL
},
31076 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31077 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31078 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31080 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31081 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31082 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31083 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31086 /* These are recognized by the assembler, but have no affect on code. */
31087 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31088 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31090 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31091 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31092 &warn_on_deprecated
, 0, NULL
},
31094 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31095 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31096 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31098 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31099 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31100 {NULL
, NULL
, NULL
, 0, NULL
}
31103 struct arm_legacy_option_table
31105 const char * option
; /* Option name to match. */
31106 const arm_feature_set
** var
; /* Variable to change. */
31107 const arm_feature_set value
; /* What to change it to. */
31108 const char * deprecated
; /* If non-null, print this message. */
31111 const struct arm_legacy_option_table arm_legacy_opts
[] =
31113 /* DON'T add any new processors to this list -- we want the whole list
31114 to go away... Add them to the processors table instead. */
31115 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31116 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31117 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31118 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31119 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31120 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31121 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31122 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31123 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31124 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31125 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31126 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31127 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31128 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31129 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31130 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31131 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31132 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31133 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31134 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31135 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31136 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31137 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31138 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31139 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31140 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31141 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31142 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31143 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31144 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31145 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31146 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31147 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31148 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31149 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31150 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31151 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31152 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31153 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31154 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31155 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31156 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31157 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31158 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31159 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31160 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31161 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31162 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31163 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31164 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31165 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31166 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31167 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31168 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31169 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31170 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31171 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31172 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31173 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31174 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31175 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31176 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31177 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31178 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31179 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31180 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31181 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31182 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31183 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31184 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31185 N_("use -mcpu=strongarm110")},
31186 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31187 N_("use -mcpu=strongarm1100")},
31188 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31189 N_("use -mcpu=strongarm1110")},
31190 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31191 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31192 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31194 /* Architecture variants -- don't add any more to this list either. */
31195 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31196 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31197 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31198 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31199 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31200 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31201 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31202 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31203 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31204 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31205 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31206 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31207 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31208 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31209 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31210 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31211 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31212 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31214 /* Floating point variants -- don't add any more to this list either. */
31215 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31216 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31217 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31218 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31219 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31221 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31224 struct arm_cpu_option_table
31228 const arm_feature_set value
;
31229 const arm_feature_set ext
;
31230 /* For some CPUs we assume an FPU unless the user explicitly sets
31232 const arm_feature_set default_fpu
;
31233 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31235 const char * canonical_name
;
31238 /* This list should, at a minimum, contain all the cpu names
31239 recognized by GCC. */
31240 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31242 static const struct arm_cpu_option_table arm_cpus
[] =
31244 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31247 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31250 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31253 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31256 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31259 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31262 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31265 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31268 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31271 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31274 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31277 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31280 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31283 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31286 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31289 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31292 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31295 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31298 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31301 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31304 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31307 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31310 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31313 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31316 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31319 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31322 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31325 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31328 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31331 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31334 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31337 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31340 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31343 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31346 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31349 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31352 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31355 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31358 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31361 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31364 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31367 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31370 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31373 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31376 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31379 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31383 /* For V5 or later processors we default to using VFP; but the user
31384 should really set the FPU type explicitly. */
31385 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31388 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31391 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31394 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31397 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31400 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31403 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31406 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31409 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31412 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31415 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31418 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31421 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31424 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31427 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31430 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31433 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31436 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31439 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31442 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31445 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31448 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31451 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31454 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31457 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31460 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31463 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31466 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31469 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31472 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31475 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31478 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31481 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31484 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31487 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31490 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31493 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31494 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31496 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31498 FPU_ARCH_NEON_VFP_V4
),
31499 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31500 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31501 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31502 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31503 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31504 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31505 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31507 FPU_ARCH_NEON_VFP_V4
),
31508 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31510 FPU_ARCH_NEON_VFP_V4
),
31511 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31513 FPU_ARCH_NEON_VFP_V4
),
31514 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31515 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31516 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31517 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31518 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31519 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31520 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31521 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31522 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31523 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31524 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31525 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31526 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31527 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31528 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31529 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31530 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31531 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31532 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31533 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31534 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31535 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31536 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31537 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31538 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31539 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31540 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31541 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31542 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31543 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31544 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31545 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31546 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31547 ARM_CPU_OPT ("cortex-a78", "Cortex-A78", ARM_ARCH_V8_2A
,
31548 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31549 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31550 ARM_CPU_OPT ("cortex-a78ae", "Cortex-A78AE", ARM_ARCH_V8_2A
,
31551 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31552 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31553 ARM_CPU_OPT ("cortex-a78c", "Cortex-A78C", ARM_ARCH_V8_2A
,
31554 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31555 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31556 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31557 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31558 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31559 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31562 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31564 FPU_ARCH_VFP_V3D16
),
31565 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31566 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31568 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31569 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31570 FPU_ARCH_VFP_V3D16
),
31571 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31572 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31573 FPU_ARCH_VFP_V3D16
),
31574 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31575 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31576 FPU_ARCH_NEON_VFP_ARMV8
),
31577 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31578 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31580 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31581 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31583 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31586 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31589 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31592 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31595 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31598 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31601 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31604 ARM_CPU_OPT ("cortex-x1", "Cortex-X1", ARM_ARCH_V8_2A
,
31605 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31606 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31607 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31608 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31609 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31610 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31611 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31612 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31613 ARM_CPU_OPT ("neoverse-n2", "Neoverse N2", ARM_ARCH_V8_5A
,
31614 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31617 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31618 ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A
,
31619 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31622 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31623 /* ??? XSCALE is really an architecture. */
31624 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31628 /* ??? iwmmxt is not a processor. */
31629 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31632 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31635 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31640 ARM_CPU_OPT ("ep9312", "ARM920T",
31641 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31642 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31644 /* Marvell processors. */
31645 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31646 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31647 FPU_ARCH_VFP_V3D16
),
31648 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31649 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31650 FPU_ARCH_NEON_VFP_V4
),
31652 /* APM X-Gene family. */
31653 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31655 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31656 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31657 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31658 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31660 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31664 struct arm_ext_table
31668 const arm_feature_set merge
;
31669 const arm_feature_set clear
;
31672 struct arm_arch_option_table
31676 const arm_feature_set value
;
31677 const arm_feature_set default_fpu
;
31678 const struct arm_ext_table
* ext_table
;
31681 /* Used to add support for +E and +noE extension. */
31682 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31683 /* Used to add support for a +E extension. */
31684 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31685 /* Used to add support for a +noE extension. */
31686 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31688 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31689 ~0 & ~FPU_ENDIAN_PURE)
31691 static const struct arm_ext_table armv5te_ext_table
[] =
31693 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31694 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31697 static const struct arm_ext_table armv7_ext_table
[] =
31699 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31700 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31703 static const struct arm_ext_table armv7ve_ext_table
[] =
31705 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31706 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31707 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31708 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31709 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31710 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31711 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31713 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31714 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31716 /* Aliases for +simd. */
31717 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31719 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31720 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31721 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31723 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31726 static const struct arm_ext_table armv7a_ext_table
[] =
31728 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31729 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31730 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31731 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31732 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31733 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31734 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31736 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31737 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31739 /* Aliases for +simd. */
31740 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31741 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31743 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31744 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31746 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31747 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31748 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31751 static const struct arm_ext_table armv7r_ext_table
[] =
31753 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31754 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31755 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31756 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31757 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31758 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31759 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31760 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31761 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31764 static const struct arm_ext_table armv7em_ext_table
[] =
31766 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31767 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31768 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31769 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31770 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31771 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31772 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31775 static const struct arm_ext_table armv8a_ext_table
[] =
31777 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31778 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31779 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31780 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31782 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31783 should use the +simd option to turn on FP. */
31784 ARM_REMOVE ("fp", ALL_FP
),
31785 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31786 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31787 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31791 static const struct arm_ext_table armv81a_ext_table
[] =
31793 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31794 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31795 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31797 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31798 should use the +simd option to turn on FP. */
31799 ARM_REMOVE ("fp", ALL_FP
),
31800 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31801 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31802 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31805 static const struct arm_ext_table armv82a_ext_table
[] =
31807 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31808 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31809 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31810 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31811 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31812 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31813 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31814 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31816 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31817 should use the +simd option to turn on FP. */
31818 ARM_REMOVE ("fp", ALL_FP
),
31819 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31820 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31821 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31824 static const struct arm_ext_table armv84a_ext_table
[] =
31826 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31827 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31828 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31829 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31830 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31831 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31833 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31834 should use the +simd option to turn on FP. */
31835 ARM_REMOVE ("fp", ALL_FP
),
31836 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31837 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31838 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31841 static const struct arm_ext_table armv85a_ext_table
[] =
31843 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31844 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31845 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31846 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31847 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31848 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31850 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31851 should use the +simd option to turn on FP. */
31852 ARM_REMOVE ("fp", ALL_FP
),
31853 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31856 static const struct arm_ext_table armv86a_ext_table
[] =
31858 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31859 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31862 #define CDE_EXTENSIONS \
31863 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31864 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31865 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31866 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31867 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31868 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31869 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31870 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31872 static const struct arm_ext_table armv8m_main_ext_table
[] =
31874 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31875 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31876 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31877 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31879 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31883 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31885 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31886 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31888 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31889 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31892 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31893 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31894 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31895 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31897 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31898 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31899 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31901 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31904 #undef CDE_EXTENSIONS
31906 static const struct arm_ext_table armv8r_ext_table
[] =
31908 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31909 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31910 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31911 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31912 ARM_REMOVE ("fp", ALL_FP
),
31913 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31914 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31917 /* This list should, at a minimum, contain all the architecture names
31918 recognized by GCC. */
31919 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31920 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31921 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31923 static const struct arm_arch_option_table arm_archs
[] =
31925 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31926 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31927 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31928 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31929 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31930 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31931 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31932 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31933 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31934 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31935 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31936 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31937 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31938 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31939 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31940 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31941 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31942 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31943 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31944 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31945 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31946 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31947 kept to preserve existing behaviour. */
31948 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31949 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31950 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31951 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31952 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31953 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31954 kept to preserve existing behaviour. */
31955 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31956 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31957 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31958 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31959 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31960 /* The official spelling of the ARMv7 profile variants is the dashed form.
31961 Accept the non-dashed form for compatibility with old toolchains. */
31962 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31963 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31964 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31965 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31966 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31967 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31968 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31969 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31970 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31971 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31973 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31975 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31976 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31977 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31978 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31979 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31980 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31981 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31982 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31983 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31984 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31985 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31986 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31988 #undef ARM_ARCH_OPT
31990 /* ISA extensions in the co-processor and main instruction set space. */
31992 struct arm_option_extension_value_table
31996 const arm_feature_set merge_value
;
31997 const arm_feature_set clear_value
;
31998 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31999 indicates that an extension is available for all architectures while
32000 ARM_ANY marks an empty entry. */
32001 const arm_feature_set allowed_archs
[2];
32004 /* The following table must be in alphabetical order with a NULL last entry. */
32006 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
32007 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
32009 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
32010 use the context sensitive approach using arm_ext_table's. */
32011 static const struct arm_option_extension_value_table arm_extensions
[] =
32013 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32014 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32016 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
32017 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
32018 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32019 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
32020 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
32022 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32023 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32024 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
32025 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
32026 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32027 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32028 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32030 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32031 | ARM_EXT2_FP16_FML
),
32032 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32033 | ARM_EXT2_FP16_FML
),
32035 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32036 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32037 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32038 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32039 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32040 Thumb divide instruction. Due to this having the same name as the
32041 previous entry, this will be ignored when doing command-line parsing and
32042 only considered by build attribute selection code. */
32043 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32044 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32045 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32046 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32047 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32048 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32049 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32050 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32051 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32052 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32053 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32054 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32055 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32056 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32057 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32058 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32059 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32060 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32061 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32062 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32063 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32065 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32066 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32067 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32068 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32069 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32070 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32071 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32072 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32074 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32075 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32076 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32077 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32078 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32079 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32080 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32081 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32083 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32084 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32085 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32086 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32087 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32091 /* ISA floating-point and Advanced SIMD extensions. */
32092 struct arm_option_fpu_value_table
32095 const arm_feature_set value
;
32098 /* This list should, at a minimum, contain all the fpu names
32099 recognized by GCC. */
32100 static const struct arm_option_fpu_value_table arm_fpus
[] =
32102 {"softfpa", FPU_NONE
},
32103 {"fpe", FPU_ARCH_FPE
},
32104 {"fpe2", FPU_ARCH_FPE
},
32105 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32106 {"fpa", FPU_ARCH_FPA
},
32107 {"fpa10", FPU_ARCH_FPA
},
32108 {"fpa11", FPU_ARCH_FPA
},
32109 {"arm7500fe", FPU_ARCH_FPA
},
32110 {"softvfp", FPU_ARCH_VFP
},
32111 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32112 {"vfp", FPU_ARCH_VFP_V2
},
32113 {"vfp9", FPU_ARCH_VFP_V2
},
32114 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32115 {"vfp10", FPU_ARCH_VFP_V2
},
32116 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32117 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32118 {"vfpv2", FPU_ARCH_VFP_V2
},
32119 {"vfpv3", FPU_ARCH_VFP_V3
},
32120 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32121 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32122 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32123 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32124 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32125 {"arm1020t", FPU_ARCH_VFP_V1
},
32126 {"arm1020e", FPU_ARCH_VFP_V2
},
32127 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32128 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32129 {"maverick", FPU_ARCH_MAVERICK
},
32130 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32131 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32132 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32133 {"vfpv4", FPU_ARCH_VFP_V4
},
32134 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32135 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32136 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32137 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32138 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32139 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32140 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32141 {"crypto-neon-fp-armv8",
32142 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32143 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32144 {"crypto-neon-fp-armv8.1",
32145 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32146 {NULL
, ARM_ARCH_NONE
}
32149 struct arm_option_value_table
32155 static const struct arm_option_value_table arm_float_abis
[] =
32157 {"hard", ARM_FLOAT_ABI_HARD
},
32158 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32159 {"soft", ARM_FLOAT_ABI_SOFT
},
32164 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32165 static const struct arm_option_value_table arm_eabis
[] =
32167 {"gnu", EF_ARM_EABI_UNKNOWN
},
32168 {"4", EF_ARM_EABI_VER4
},
32169 {"5", EF_ARM_EABI_VER5
},
32174 struct arm_long_option_table
32176 const char * option
; /* Substring to match. */
32177 const char * help
; /* Help information. */
32178 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32179 const char * deprecated
; /* If non-null, print this message. */
32183 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32184 arm_feature_set
*ext_set
,
32185 const struct arm_ext_table
*ext_table
)
32187 /* We insist on extensions being specified in alphabetical order, and with
32188 extensions being added before being removed. We achieve this by having
32189 the global ARM_EXTENSIONS table in alphabetical order, and using the
32190 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32191 or removing it (0) and only allowing it to change in the order
32193 const struct arm_option_extension_value_table
* opt
= NULL
;
32194 const arm_feature_set arm_any
= ARM_ANY
;
32195 int adding_value
= -1;
32197 while (str
!= NULL
&& *str
!= 0)
32204 as_bad (_("invalid architectural extension"));
32209 ext
= strchr (str
, '+');
32214 len
= strlen (str
);
32216 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32218 if (adding_value
!= 0)
32221 opt
= arm_extensions
;
32229 if (adding_value
== -1)
32232 opt
= arm_extensions
;
32234 else if (adding_value
!= 1)
32236 as_bad (_("must specify extensions to add before specifying "
32237 "those to remove"));
32244 as_bad (_("missing architectural extension"));
32248 gas_assert (adding_value
!= -1);
32249 gas_assert (opt
!= NULL
);
32251 if (ext_table
!= NULL
)
32253 const struct arm_ext_table
* ext_opt
= ext_table
;
32254 bfd_boolean found
= FALSE
;
32255 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32256 if (ext_opt
->name_len
== len
32257 && strncmp (ext_opt
->name
, str
, len
) == 0)
32261 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32262 /* TODO: Option not supported. When we remove the
32263 legacy table this case should error out. */
32266 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32270 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32271 /* TODO: Option not supported. When we remove the
32272 legacy table this case should error out. */
32274 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32286 /* Scan over the options table trying to find an exact match. */
32287 for (; opt
->name
!= NULL
; opt
++)
32288 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32290 int i
, nb_allowed_archs
=
32291 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32292 /* Check we can apply the extension to this architecture. */
32293 for (i
= 0; i
< nb_allowed_archs
; i
++)
32296 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32298 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32301 if (i
== nb_allowed_archs
)
32303 as_bad (_("extension does not apply to the base architecture"));
32307 /* Add or remove the extension. */
32309 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32311 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32313 /* Allowing Thumb division instructions for ARMv7 in autodetection
32314 rely on this break so that duplicate extensions (extensions
32315 with the same name as a previous extension in the list) are not
32316 considered for command-line parsing. */
32320 if (opt
->name
== NULL
)
32322 /* Did we fail to find an extension because it wasn't specified in
32323 alphabetical order, or because it does not exist? */
32325 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32326 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32329 if (opt
->name
== NULL
)
32330 as_bad (_("unknown architectural extension `%s'"), str
);
32332 as_bad (_("architectural extensions must be specified in "
32333 "alphabetical order"));
32339 /* We should skip the extension we've just matched the next time
32351 arm_parse_fp16_opt (const char *str
)
32353 if (strcasecmp (str
, "ieee") == 0)
32354 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32355 else if (strcasecmp (str
, "alternative") == 0)
32356 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32359 as_bad (_("unrecognised float16 format \"%s\""), str
);
32367 arm_parse_cpu (const char *str
)
32369 const struct arm_cpu_option_table
*opt
;
32370 const char *ext
= strchr (str
, '+');
32376 len
= strlen (str
);
32380 as_bad (_("missing cpu name `%s'"), str
);
32384 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32385 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32387 mcpu_cpu_opt
= &opt
->value
;
32388 if (mcpu_ext_opt
== NULL
)
32389 mcpu_ext_opt
= XNEW (arm_feature_set
);
32390 *mcpu_ext_opt
= opt
->ext
;
32391 mcpu_fpu_opt
= &opt
->default_fpu
;
32392 if (opt
->canonical_name
)
32394 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32395 strcpy (selected_cpu_name
, opt
->canonical_name
);
32401 if (len
>= sizeof selected_cpu_name
)
32402 len
= (sizeof selected_cpu_name
) - 1;
32404 for (i
= 0; i
< len
; i
++)
32405 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32406 selected_cpu_name
[i
] = 0;
32410 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32415 as_bad (_("unknown cpu `%s'"), str
);
32420 arm_parse_arch (const char *str
)
32422 const struct arm_arch_option_table
*opt
;
32423 const char *ext
= strchr (str
, '+');
32429 len
= strlen (str
);
32433 as_bad (_("missing architecture name `%s'"), str
);
32437 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32438 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32440 march_cpu_opt
= &opt
->value
;
32441 if (march_ext_opt
== NULL
)
32442 march_ext_opt
= XNEW (arm_feature_set
);
32443 *march_ext_opt
= arm_arch_none
;
32444 march_fpu_opt
= &opt
->default_fpu
;
32445 selected_ctx_ext_table
= opt
->ext_table
;
32446 strcpy (selected_cpu_name
, opt
->name
);
32449 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32455 as_bad (_("unknown architecture `%s'\n"), str
);
32460 arm_parse_fpu (const char * str
)
32462 const struct arm_option_fpu_value_table
* opt
;
32464 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32465 if (streq (opt
->name
, str
))
32467 mfpu_opt
= &opt
->value
;
32471 as_bad (_("unknown floating point format `%s'\n"), str
);
32476 arm_parse_float_abi (const char * str
)
32478 const struct arm_option_value_table
* opt
;
32480 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32481 if (streq (opt
->name
, str
))
32483 mfloat_abi_opt
= opt
->value
;
32487 as_bad (_("unknown floating point abi `%s'\n"), str
);
32493 arm_parse_eabi (const char * str
)
32495 const struct arm_option_value_table
*opt
;
32497 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32498 if (streq (opt
->name
, str
))
32500 meabi_flags
= opt
->value
;
32503 as_bad (_("unknown EABI `%s'\n"), str
);
32509 arm_parse_it_mode (const char * str
)
32511 bfd_boolean ret
= TRUE
;
32513 if (streq ("arm", str
))
32514 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32515 else if (streq ("thumb", str
))
32516 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32517 else if (streq ("always", str
))
32518 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32519 else if (streq ("never", str
))
32520 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32523 as_bad (_("unknown implicit IT mode `%s', should be "\
32524 "arm, thumb, always, or never."), str
);
32532 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32534 codecomposer_syntax
= TRUE
;
32535 arm_comment_chars
[0] = ';';
32536 arm_line_separator_chars
[0] = 0;
32540 struct arm_long_option_table arm_long_opts
[] =
32542 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32543 arm_parse_cpu
, NULL
},
32544 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32545 arm_parse_arch
, NULL
},
32546 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32547 arm_parse_fpu
, NULL
},
32548 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32549 arm_parse_float_abi
, NULL
},
32551 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32552 arm_parse_eabi
, NULL
},
32554 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32555 arm_parse_it_mode
, NULL
},
32556 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32557 arm_ccs_mode
, NULL
},
32559 N_("[ieee|alternative]\n\
32560 set the encoding for half precision floating point "
32561 "numbers to IEEE\n\
32562 or Arm alternative format."),
32563 arm_parse_fp16_opt
, NULL
},
32564 {NULL
, NULL
, 0, NULL
}
32568 md_parse_option (int c
, const char * arg
)
32570 struct arm_option_table
*opt
;
32571 const struct arm_legacy_option_table
*fopt
;
32572 struct arm_long_option_table
*lopt
;
32578 target_big_endian
= 1;
32584 target_big_endian
= 0;
32588 case OPTION_FIX_V4BX
:
32596 #endif /* OBJ_ELF */
32599 /* Listing option. Just ignore these, we don't support additional
32604 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32606 if (c
== opt
->option
[0]
32607 && ((arg
== NULL
&& opt
->option
[1] == 0)
32608 || streq (arg
, opt
->option
+ 1)))
32610 /* If the option is deprecated, tell the user. */
32611 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32612 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32613 arg
? arg
: "", _(opt
->deprecated
));
32615 if (opt
->var
!= NULL
)
32616 *opt
->var
= opt
->value
;
32622 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32624 if (c
== fopt
->option
[0]
32625 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32626 || streq (arg
, fopt
->option
+ 1)))
32628 /* If the option is deprecated, tell the user. */
32629 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32630 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32631 arg
? arg
: "", _(fopt
->deprecated
));
32633 if (fopt
->var
!= NULL
)
32634 *fopt
->var
= &fopt
->value
;
32640 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32642 /* These options are expected to have an argument. */
32643 if (c
== lopt
->option
[0]
32645 && strncmp (arg
, lopt
->option
+ 1,
32646 strlen (lopt
->option
+ 1)) == 0)
32648 /* If the option is deprecated, tell the user. */
32649 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32650 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32651 _(lopt
->deprecated
));
32653 /* Call the sup-option parser. */
32654 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32665 md_show_usage (FILE * fp
)
32667 struct arm_option_table
*opt
;
32668 struct arm_long_option_table
*lopt
;
32670 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32672 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32673 if (opt
->help
!= NULL
)
32674 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32676 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32677 if (lopt
->help
!= NULL
)
32678 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32682 -EB assemble code for a big-endian cpu\n"));
32687 -EL assemble code for a little-endian cpu\n"));
32691 --fix-v4bx Allow BX in ARMv4 code\n"));
32695 --fdpic generate an FDPIC object file\n"));
32696 #endif /* OBJ_ELF */
32704 arm_feature_set flags
;
32705 } cpu_arch_ver_table
;
32707 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32708 chronologically for architectures, with an exception for ARMv6-M and
32709 ARMv6S-M due to legacy reasons. No new architecture should have a
32710 special case. This allows for build attribute selection results to be
32711 stable when new architectures are added. */
32712 static const cpu_arch_ver_table cpu_arch_ver
[] =
32714 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32715 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32716 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32717 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32718 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32719 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32720 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32721 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32722 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32723 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32724 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32725 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32726 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32727 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32728 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32729 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32730 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32731 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32732 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32733 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32734 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32735 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32736 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32737 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32739 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32740 always selected build attributes to match those of ARMv6-M
32741 (resp. ARMv6S-M). However, due to these architectures being a strict
32742 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32743 would be selected when fully respecting chronology of architectures.
32744 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32745 move them before ARMv7 architectures. */
32746 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32747 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32749 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32750 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32751 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32752 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32753 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32754 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32755 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32756 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32757 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32758 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32759 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32760 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32761 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32762 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32763 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32764 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32765 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32766 {-1, ARM_ARCH_NONE
}
32769 /* Set an attribute if it has not already been set by the user. */
32772 aeabi_set_attribute_int (int tag
, int value
)
32775 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32776 || !attributes_set_explicitly
[tag
])
32777 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32781 aeabi_set_attribute_string (int tag
, const char *value
)
32784 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32785 || !attributes_set_explicitly
[tag
])
32786 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32789 /* Return whether features in the *NEEDED feature set are available via
32790 extensions for the architecture whose feature set is *ARCH_FSET. */
32793 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32794 const arm_feature_set
*needed
)
32796 int i
, nb_allowed_archs
;
32797 arm_feature_set ext_fset
;
32798 const struct arm_option_extension_value_table
*opt
;
32800 ext_fset
= arm_arch_none
;
32801 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32803 /* Extension does not provide any feature we need. */
32804 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32808 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32809 for (i
= 0; i
< nb_allowed_archs
; i
++)
32812 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32815 /* Extension is available, add it. */
32816 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32817 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32821 /* Can we enable all features in *needed? */
32822 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32825 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32826 a given architecture feature set *ARCH_EXT_FSET including extension feature
32827 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32828 - if true, check for an exact match of the architecture modulo extensions;
32829 - otherwise, select build attribute value of the first superset
32830 architecture released so that results remains stable when new architectures
32832 For -march/-mcpu=all the build attribute value of the most featureful
32833 architecture is returned. Tag_CPU_arch_profile result is returned in
32837 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32838 const arm_feature_set
*ext_fset
,
32839 char *profile
, int exact_match
)
32841 arm_feature_set arch_fset
;
32842 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32844 /* Select most featureful architecture with all its extensions if building
32845 for -march=all as the feature sets used to set build attributes. */
32846 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32848 /* Force revisiting of decision for each new architecture. */
32849 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32851 return TAG_CPU_ARCH_V8
;
32854 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32856 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32858 arm_feature_set known_arch_fset
;
32860 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32863 /* Base architecture match user-specified architecture and
32864 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32865 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32870 /* Base architecture match user-specified architecture only
32871 (eg. ARMv6-M in the same case as above). Record it in case we
32872 find a match with above condition. */
32873 else if (p_ver_ret
== NULL
32874 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32880 /* Architecture has all features wanted. */
32881 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32883 arm_feature_set added_fset
;
32885 /* Compute features added by this architecture over the one
32886 recorded in p_ver_ret. */
32887 if (p_ver_ret
!= NULL
)
32888 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32890 /* First architecture that match incl. with extensions, or the
32891 only difference in features over the recorded match is
32892 features that were optional and are now mandatory. */
32893 if (p_ver_ret
== NULL
32894 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32900 else if (p_ver_ret
== NULL
)
32902 arm_feature_set needed_ext_fset
;
32904 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32906 /* Architecture has all features needed when using some
32907 extensions. Record it and continue searching in case there
32908 exist an architecture providing all needed features without
32909 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32911 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32918 if (p_ver_ret
== NULL
)
32922 /* Tag_CPU_arch_profile. */
32923 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32924 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32925 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32926 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32927 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32929 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32930 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32932 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32936 return p_ver_ret
->val
;
32939 /* Set the public EABI object attributes. */
32942 aeabi_set_public_attributes (void)
32944 char profile
= '\0';
32947 int fp16_optional
= 0;
32948 int skip_exact_match
= 0;
32949 arm_feature_set flags
, flags_arch
, flags_ext
;
32951 /* Autodetection mode, choose the architecture based the instructions
32953 if (no_cpu_selected ())
32955 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32957 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32958 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32960 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32961 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32963 /* Code run during relaxation relies on selected_cpu being set. */
32964 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32965 flags_ext
= arm_arch_none
;
32966 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32967 selected_ext
= flags_ext
;
32968 selected_cpu
= flags
;
32970 /* Otherwise, choose the architecture based on the capabilities of the
32974 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32975 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32976 flags_ext
= selected_ext
;
32977 flags
= selected_cpu
;
32979 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32981 /* Allow the user to override the reported architecture. */
32982 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32984 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32985 flags_ext
= arm_arch_none
;
32988 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32990 /* When this function is run again after relaxation has happened there is no
32991 way to determine whether an architecture or CPU was specified by the user:
32992 - selected_cpu is set above for relaxation to work;
32993 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32994 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32995 Therefore, if not in -march=all case we first try an exact match and fall
32996 back to autodetection. */
32997 if (!skip_exact_match
)
32998 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
33000 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
33002 as_bad (_("no architecture contains all the instructions used\n"));
33004 /* Tag_CPU_name. */
33005 if (selected_cpu_name
[0])
33009 q
= selected_cpu_name
;
33010 if (strncmp (q
, "armv", 4) == 0)
33015 for (i
= 0; q
[i
]; i
++)
33016 q
[i
] = TOUPPER (q
[i
]);
33018 aeabi_set_attribute_string (Tag_CPU_name
, q
);
33021 /* Tag_CPU_arch. */
33022 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
33024 /* Tag_CPU_arch_profile. */
33025 if (profile
!= '\0')
33026 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
33028 /* Tag_DSP_extension. */
33029 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33030 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33032 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33033 /* Tag_ARM_ISA_use. */
33034 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33035 || ARM_FEATURE_ZERO (flags_arch
))
33036 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33038 /* Tag_THUMB_ISA_use. */
33039 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33040 || ARM_FEATURE_ZERO (flags_arch
))
33044 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33045 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33047 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33051 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33054 /* Tag_VFP_arch. */
33055 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33056 aeabi_set_attribute_int (Tag_VFP_arch
,
33057 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33059 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33060 aeabi_set_attribute_int (Tag_VFP_arch
,
33061 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33063 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33066 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33068 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33070 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33073 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33074 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33075 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33076 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33077 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33079 /* Tag_ABI_HardFP_use. */
33080 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33081 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33082 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33084 /* Tag_WMMX_arch. */
33085 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33086 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33087 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33088 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33090 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33091 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33092 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33093 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33094 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33095 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33097 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33099 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33103 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33108 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33109 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33110 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33111 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33113 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33114 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33115 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33119 We set Tag_DIV_use to two when integer divide instructions have been used
33120 in ARM state, or when Thumb integer divide instructions have been used,
33121 but we have no architecture profile set, nor have we any ARM instructions.
33123 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33124 by the base architecture.
33126 For new architectures we will have to check these tests. */
33127 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33128 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33129 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33130 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33131 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33132 || (profile
== '\0'
33133 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33134 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33135 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33137 /* Tag_MP_extension_use. */
33138 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33139 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33141 /* Tag Virtualization_use. */
33142 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33144 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33147 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33149 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33150 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33153 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33154 finished and free extension feature bits which will not be used anymore. */
33157 arm_md_post_relax (void)
33159 aeabi_set_public_attributes ();
33160 XDELETE (mcpu_ext_opt
);
33161 mcpu_ext_opt
= NULL
;
33162 XDELETE (march_ext_opt
);
33163 march_ext_opt
= NULL
;
33166 /* Add the default contents for the .ARM.attributes section. */
33171 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33174 aeabi_set_public_attributes ();
33176 #endif /* OBJ_ELF */
33178 /* Parse a .cpu directive. */
33181 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33183 const struct arm_cpu_option_table
*opt
;
33187 name
= input_line_pointer
;
33188 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33189 input_line_pointer
++;
33190 saved_char
= *input_line_pointer
;
33191 *input_line_pointer
= 0;
33193 /* Skip the first "all" entry. */
33194 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33195 if (streq (opt
->name
, name
))
33197 selected_arch
= opt
->value
;
33198 selected_ext
= opt
->ext
;
33199 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33200 if (opt
->canonical_name
)
33201 strcpy (selected_cpu_name
, opt
->canonical_name
);
33205 for (i
= 0; opt
->name
[i
]; i
++)
33206 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33208 selected_cpu_name
[i
] = 0;
33210 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33212 *input_line_pointer
= saved_char
;
33213 demand_empty_rest_of_line ();
33216 as_bad (_("unknown cpu `%s'"), name
);
33217 *input_line_pointer
= saved_char
;
33218 ignore_rest_of_line ();
33221 /* Parse a .arch directive. */
33224 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33226 const struct arm_arch_option_table
*opt
;
33230 name
= input_line_pointer
;
33231 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33232 input_line_pointer
++;
33233 saved_char
= *input_line_pointer
;
33234 *input_line_pointer
= 0;
33236 /* Skip the first "all" entry. */
33237 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33238 if (streq (opt
->name
, name
))
33240 selected_arch
= opt
->value
;
33241 selected_ctx_ext_table
= opt
->ext_table
;
33242 selected_ext
= arm_arch_none
;
33243 selected_cpu
= selected_arch
;
33244 strcpy (selected_cpu_name
, opt
->name
);
33245 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33246 *input_line_pointer
= saved_char
;
33247 demand_empty_rest_of_line ();
33251 as_bad (_("unknown architecture `%s'\n"), name
);
33252 *input_line_pointer
= saved_char
;
33253 ignore_rest_of_line ();
33256 /* Parse a .object_arch directive. */
33259 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33261 const struct arm_arch_option_table
*opt
;
33265 name
= input_line_pointer
;
33266 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33267 input_line_pointer
++;
33268 saved_char
= *input_line_pointer
;
33269 *input_line_pointer
= 0;
33271 /* Skip the first "all" entry. */
33272 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33273 if (streq (opt
->name
, name
))
33275 selected_object_arch
= opt
->value
;
33276 *input_line_pointer
= saved_char
;
33277 demand_empty_rest_of_line ();
33281 as_bad (_("unknown architecture `%s'\n"), name
);
33282 *input_line_pointer
= saved_char
;
33283 ignore_rest_of_line ();
33286 /* Parse a .arch_extension directive. */
33289 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33291 const struct arm_option_extension_value_table
*opt
;
33294 int adding_value
= 1;
33296 name
= input_line_pointer
;
33297 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33298 input_line_pointer
++;
33299 saved_char
= *input_line_pointer
;
33300 *input_line_pointer
= 0;
33302 if (strlen (name
) >= 2
33303 && strncmp (name
, "no", 2) == 0)
33309 /* Check the context specific extension table */
33310 if (selected_ctx_ext_table
)
33312 const struct arm_ext_table
* ext_opt
;
33313 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33315 if (streq (ext_opt
->name
, name
))
33319 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33320 /* TODO: Option not supported. When we remove the
33321 legacy table this case should error out. */
33323 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33327 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33329 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33330 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33331 *input_line_pointer
= saved_char
;
33332 demand_empty_rest_of_line ();
33338 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33339 if (streq (opt
->name
, name
))
33341 int i
, nb_allowed_archs
=
33342 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33343 for (i
= 0; i
< nb_allowed_archs
; i
++)
33346 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33348 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33352 if (i
== nb_allowed_archs
)
33354 as_bad (_("architectural extension `%s' is not allowed for the "
33355 "current base architecture"), name
);
33360 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33363 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33365 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33366 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33367 *input_line_pointer
= saved_char
;
33368 demand_empty_rest_of_line ();
33369 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33370 on this return so that duplicate extensions (extensions with the
33371 same name as a previous extension in the list) are not considered
33372 for command-line parsing. */
33376 if (opt
->name
== NULL
)
33377 as_bad (_("unknown architecture extension `%s'\n"), name
);
33379 *input_line_pointer
= saved_char
;
33380 ignore_rest_of_line ();
33383 /* Parse a .fpu directive. */
33386 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33388 const struct arm_option_fpu_value_table
*opt
;
33392 name
= input_line_pointer
;
33393 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33394 input_line_pointer
++;
33395 saved_char
= *input_line_pointer
;
33396 *input_line_pointer
= 0;
33398 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33399 if (streq (opt
->name
, name
))
33401 selected_fpu
= opt
->value
;
33402 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33403 #ifndef CPU_DEFAULT
33404 if (no_cpu_selected ())
33405 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33408 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33409 *input_line_pointer
= saved_char
;
33410 demand_empty_rest_of_line ();
33414 as_bad (_("unknown floating point format `%s'\n"), name
);
33415 *input_line_pointer
= saved_char
;
33416 ignore_rest_of_line ();
33419 /* Copy symbol information. */
33422 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33424 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33428 /* Given a symbolic attribute NAME, return the proper integer value.
33429 Returns -1 if the attribute is not known. */
33432 arm_convert_symbolic_attribute (const char *name
)
33434 static const struct
33439 attribute_table
[] =
33441 /* When you modify this table you should
33442 also modify the list in doc/c-arm.texi. */
33443 #define T(tag) {#tag, tag}
33444 T (Tag_CPU_raw_name
),
33447 T (Tag_CPU_arch_profile
),
33448 T (Tag_ARM_ISA_use
),
33449 T (Tag_THUMB_ISA_use
),
33453 T (Tag_Advanced_SIMD_arch
),
33454 T (Tag_PCS_config
),
33455 T (Tag_ABI_PCS_R9_use
),
33456 T (Tag_ABI_PCS_RW_data
),
33457 T (Tag_ABI_PCS_RO_data
),
33458 T (Tag_ABI_PCS_GOT_use
),
33459 T (Tag_ABI_PCS_wchar_t
),
33460 T (Tag_ABI_FP_rounding
),
33461 T (Tag_ABI_FP_denormal
),
33462 T (Tag_ABI_FP_exceptions
),
33463 T (Tag_ABI_FP_user_exceptions
),
33464 T (Tag_ABI_FP_number_model
),
33465 T (Tag_ABI_align_needed
),
33466 T (Tag_ABI_align8_needed
),
33467 T (Tag_ABI_align_preserved
),
33468 T (Tag_ABI_align8_preserved
),
33469 T (Tag_ABI_enum_size
),
33470 T (Tag_ABI_HardFP_use
),
33471 T (Tag_ABI_VFP_args
),
33472 T (Tag_ABI_WMMX_args
),
33473 T (Tag_ABI_optimization_goals
),
33474 T (Tag_ABI_FP_optimization_goals
),
33475 T (Tag_compatibility
),
33476 T (Tag_CPU_unaligned_access
),
33477 T (Tag_FP_HP_extension
),
33478 T (Tag_VFP_HP_extension
),
33479 T (Tag_ABI_FP_16bit_format
),
33480 T (Tag_MPextension_use
),
33482 T (Tag_nodefaults
),
33483 T (Tag_also_compatible_with
),
33484 T (Tag_conformance
),
33486 T (Tag_Virtualization_use
),
33487 T (Tag_DSP_extension
),
33489 /* We deliberately do not include Tag_MPextension_use_legacy. */
33497 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33498 if (streq (name
, attribute_table
[i
].name
))
33499 return attribute_table
[i
].tag
;
33504 /* Apply sym value for relocations only in the case that they are for
33505 local symbols in the same segment as the fixup and you have the
33506 respective architectural feature for blx and simple switches. */
33509 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33512 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33513 /* PR 17444: If the local symbol is in a different section then a reloc
33514 will always be generated for it, so applying the symbol value now
33515 will result in a double offset being stored in the relocation. */
33516 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33517 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33519 switch (fixP
->fx_r_type
)
33521 case BFD_RELOC_ARM_PCREL_BLX
:
33522 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33523 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33527 case BFD_RELOC_ARM_PCREL_CALL
:
33528 case BFD_RELOC_THUMB_PCREL_BLX
:
33529 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33540 #endif /* OBJ_ELF */