1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR
, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR
, /* ARM LR register */
6930 OP_RRe
, /* ARM register, only even numbered. */
6931 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST
, /* ARM register list */
6935 OP_CLRMLST
, /* CLRM register list */
6936 OP_VRSLST
, /* VFP single-precision register list */
6937 OP_VRDLST
, /* VFP double-precision register list */
6938 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST
, /* Neon element/structure list */
6941 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2
, /* MVE vector list with two elements. */
6943 OP_MSTRLST4
, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV
, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6970 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6971 OP_VLDR
, /* VLDR operand. */
6973 OP_I0
, /* immediate zero */
6974 OP_I7
, /* immediate value 0 .. 7 */
6975 OP_I15
, /* 0 .. 15 */
6976 OP_I16
, /* 1 .. 16 */
6977 OP_I16z
, /* 0 .. 16 */
6978 OP_I31
, /* 0 .. 31 */
6979 OP_I31w
, /* 0 .. 31, optional trailing ! */
6980 OP_I32
, /* 1 .. 32 */
6981 OP_I32z
, /* 0 .. 32 */
6982 OP_I63
, /* 0 .. 63 */
6983 OP_I63s
, /* -64 .. 63 */
6984 OP_I64
, /* 1 .. 64 */
6985 OP_I64z
, /* 0 .. 64 */
6986 OP_I255
, /* 0 .. 255 */
6988 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6989 OP_I7b
, /* 0 .. 7 */
6990 OP_I15b
, /* 0 .. 15 */
6991 OP_I31b
, /* 0 .. 31 */
6993 OP_SH
, /* shifter operand */
6994 OP_SHG
, /* shifter operand with possible group relocation */
6995 OP_ADDR
, /* Memory address expression (any mode) */
6996 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6997 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6998 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6999 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7000 OP_EXP
, /* arbitrary expression */
7001 OP_EXPi
, /* same, with optional immediate prefix */
7002 OP_EXPr
, /* same, with optional relocation suffix */
7003 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7004 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7005 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7006 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7008 OP_CPSF
, /* CPS flags */
7009 OP_ENDI
, /* Endianness specifier */
7010 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7011 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7012 OP_COND
, /* conditional code */
7013 OP_TB
, /* Table branch. */
7015 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7017 OP_RRnpc_I0
, /* ARM register or literal 0 */
7018 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7019 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7020 OP_RF_IF
, /* FPA register or immediate */
7021 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7022 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7024 /* Optional operands. */
7025 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7026 OP_oI31b
, /* 0 .. 31 */
7027 OP_oI32b
, /* 1 .. 32 */
7028 OP_oI32z
, /* 0 .. 32 */
7029 OP_oIffffb
, /* 0 .. 65535 */
7030 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7032 OP_oRR
, /* ARM register */
7033 OP_oLR
, /* ARM LR register */
7034 OP_oRRnpc
, /* ARM register, not the PC */
7035 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7036 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7037 OP_oRND
, /* Optional Neon double precision register */
7038 OP_oRNQ
, /* Optional Neon quad precision register */
7039 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7040 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7041 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7042 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7044 OP_oSHll
, /* LSL immediate */
7045 OP_oSHar
, /* ASR immediate */
7046 OP_oSHllar
, /* LSL or ASR immediate */
7047 OP_oROR
, /* ROR 0/8/16/24 */
7048 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7050 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7052 /* Some pre-defined mixed (ARM/THUMB) operands. */
7053 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7054 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7055 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7057 OP_FIRST_OPTIONAL
= OP_oI7b
7060 /* Generic instruction operand parser. This does no encoding and no
7061 semantic validation; it merely squirrels values away in the inst
7062 structure. Returns SUCCESS or FAIL depending on whether the
7063 specified grammar matched. */
7065 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7067 unsigned const int *upat
= pattern
;
7068 char *backtrack_pos
= 0;
7069 const char *backtrack_error
= 0;
7070 int i
, val
= 0, backtrack_index
= 0;
7071 enum arm_reg_type rtype
;
7072 parse_operand_result result
;
7073 unsigned int op_parse_code
;
7074 bfd_boolean partial_match
;
7076 #define po_char_or_fail(chr) \
7079 if (skip_past_char (&str, chr) == FAIL) \
7084 #define po_reg_or_fail(regtype) \
7087 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7088 & inst.operands[i].vectype); \
7091 first_error (_(reg_expected_msgs[regtype])); \
7094 inst.operands[i].reg = val; \
7095 inst.operands[i].isreg = 1; \
7096 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7097 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7098 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7099 || rtype == REG_TYPE_VFD \
7100 || rtype == REG_TYPE_NQ); \
7101 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7105 #define po_reg_or_goto(regtype, label) \
7108 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7109 & inst.operands[i].vectype); \
7113 inst.operands[i].reg = val; \
7114 inst.operands[i].isreg = 1; \
7115 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7116 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7117 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7118 || rtype == REG_TYPE_VFD \
7119 || rtype == REG_TYPE_NQ); \
7120 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7124 #define po_imm_or_fail(min, max, popt) \
7127 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7129 inst.operands[i].imm = val; \
7133 #define po_scalar_or_goto(elsz, label, reg_type) \
7136 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7140 inst.operands[i].reg = val; \
7141 inst.operands[i].isscalar = 1; \
7145 #define po_misc_or_fail(expr) \
7153 #define po_misc_or_fail_no_backtrack(expr) \
7157 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7158 backtrack_pos = 0; \
7159 if (result != PARSE_OPERAND_SUCCESS) \
7164 #define po_barrier_or_imm(str) \
7167 val = parse_barrier (&str); \
7168 if (val == FAIL && ! ISALPHA (*str)) \
7171 /* ISB can only take SY as an option. */ \
7172 || ((inst.instruction & 0xf0) == 0x60 \
7175 inst.error = _("invalid barrier type"); \
7176 backtrack_pos = 0; \
7182 skip_whitespace (str
);
7184 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7186 op_parse_code
= upat
[i
];
7187 if (op_parse_code
>= 1<<16)
7188 op_parse_code
= thumb
? (op_parse_code
>> 16)
7189 : (op_parse_code
& ((1<<16)-1));
7191 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7193 /* Remember where we are in case we need to backtrack. */
7194 backtrack_pos
= str
;
7195 backtrack_error
= inst
.error
;
7196 backtrack_index
= i
;
7199 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7200 po_char_or_fail (',');
7202 switch (op_parse_code
)
7214 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7215 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7216 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7217 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7218 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7219 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7222 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7226 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7229 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7231 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7233 /* Also accept generic coprocessor regs for unknown registers. */
7235 po_reg_or_fail (REG_TYPE_CN
);
7237 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7238 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7239 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7240 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7241 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7242 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7243 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7244 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7245 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7246 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7249 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7252 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7253 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7255 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7260 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7264 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7266 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7269 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7271 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7274 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7276 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7281 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7284 po_reg_or_fail (REG_TYPE_NSDQ
);
7288 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7292 po_reg_or_fail (REG_TYPE_MQ
);
7294 /* Neon scalar. Using an element size of 8 means that some invalid
7295 scalars are accepted here, so deal with those in later code. */
7296 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7300 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7303 po_imm_or_fail (0, 0, TRUE
);
7308 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7312 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7317 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7320 if (parse_ifimm_zero (&str
))
7321 inst
.operands
[i
].imm
= 0;
7325 = _("only floating point zero is allowed as immediate value");
7333 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7336 po_reg_or_fail (REG_TYPE_RN
);
7340 case OP_RNSDQ_RNSC_MQ_RR
:
7341 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7344 case OP_RNSDQ_RNSC_MQ
:
7345 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7350 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7354 po_reg_or_fail (REG_TYPE_NSDQ
);
7361 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7364 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7367 po_reg_or_fail (REG_TYPE_NSD
);
7371 case OP_RNDQMQ_RNSC_RR
:
7372 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7375 case OP_RNDQ_RNSC_RR
:
7376 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7378 case OP_RNDQMQ_RNSC
:
7379 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7384 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7387 po_reg_or_fail (REG_TYPE_NDQ
);
7393 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7396 po_reg_or_fail (REG_TYPE_VFD
);
7401 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7402 not careful then bad things might happen. */
7403 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7406 case OP_RNDQMQ_Ibig
:
7407 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7412 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7415 /* There's a possibility of getting a 64-bit immediate here, so
7416 we need special handling. */
7417 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7420 inst
.error
= _("immediate value is out of range");
7426 case OP_RNDQMQ_I63b_RR
:
7427 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7430 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7435 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7438 po_imm_or_fail (0, 63, TRUE
);
7443 po_char_or_fail ('[');
7444 po_reg_or_fail (REG_TYPE_RN
);
7445 po_char_or_fail (']');
7451 po_reg_or_fail (REG_TYPE_RN
);
7452 if (skip_past_char (&str
, '!') == SUCCESS
)
7453 inst
.operands
[i
].writeback
= 1;
7457 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7458 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7459 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7460 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7461 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7462 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7463 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7464 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7465 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7466 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7467 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7468 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7470 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7472 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7473 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7475 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7476 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7477 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7478 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7480 /* Immediate variants */
7482 po_char_or_fail ('{');
7483 po_imm_or_fail (0, 255, TRUE
);
7484 po_char_or_fail ('}');
7488 /* The expression parser chokes on a trailing !, so we have
7489 to find it first and zap it. */
7492 while (*s
&& *s
!= ',')
7497 inst
.operands
[i
].writeback
= 1;
7499 po_imm_or_fail (0, 31, TRUE
);
7507 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7512 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7517 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7519 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7521 val
= parse_reloc (&str
);
7524 inst
.error
= _("unrecognized relocation suffix");
7527 else if (val
!= BFD_RELOC_UNUSED
)
7529 inst
.operands
[i
].imm
= val
;
7530 inst
.operands
[i
].hasreloc
= 1;
7536 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7538 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7540 inst
.operands
[i
].hasreloc
= 1;
7542 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7544 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7545 inst
.operands
[i
].hasreloc
= 0;
7549 /* Operand for MOVW or MOVT. */
7551 po_misc_or_fail (parse_half (&str
));
7554 /* Register or expression. */
7555 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7556 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7558 /* Register or immediate. */
7559 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7560 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7562 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7564 if (!is_immediate_prefix (*str
))
7567 val
= parse_fpa_immediate (&str
);
7570 /* FPA immediates are encoded as registers 8-15.
7571 parse_fpa_immediate has already applied the offset. */
7572 inst
.operands
[i
].reg
= val
;
7573 inst
.operands
[i
].isreg
= 1;
7576 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7577 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7579 /* Two kinds of register. */
7582 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7584 || (rege
->type
!= REG_TYPE_MMXWR
7585 && rege
->type
!= REG_TYPE_MMXWC
7586 && rege
->type
!= REG_TYPE_MMXWCG
))
7588 inst
.error
= _("iWMMXt data or control register expected");
7591 inst
.operands
[i
].reg
= rege
->number
;
7592 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7598 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7600 || (rege
->type
!= REG_TYPE_MMXWC
7601 && rege
->type
!= REG_TYPE_MMXWCG
))
7603 inst
.error
= _("iWMMXt control register expected");
7606 inst
.operands
[i
].reg
= rege
->number
;
7607 inst
.operands
[i
].isreg
= 1;
7612 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7613 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7614 case OP_oROR
: val
= parse_ror (&str
); break;
7616 case OP_COND
: val
= parse_cond (&str
); break;
7617 case OP_oBARRIER_I15
:
7618 po_barrier_or_imm (str
); break;
7620 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7626 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7627 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7629 inst
.error
= _("Banked registers are not available with this "
7635 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7639 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7642 val
= parse_sys_vldr_vstr (&str
);
7646 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7651 if (strncasecmp (str
, "APSR_", 5) == 0)
7658 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7659 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7660 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7661 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7662 default: found
= 16;
7666 inst
.operands
[i
].isvec
= 1;
7667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7668 inst
.operands
[i
].reg
= REG_PC
;
7675 po_misc_or_fail (parse_tb (&str
));
7678 /* Register lists. */
7680 val
= parse_reg_list (&str
, REGLIST_RN
);
7683 inst
.operands
[i
].writeback
= 1;
7689 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7693 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7698 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7703 /* Allow Q registers too. */
7704 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7705 REGLIST_NEON_D
, &partial_match
);
7709 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7710 REGLIST_VFP_S
, &partial_match
);
7711 inst
.operands
[i
].issingle
= 1;
7716 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7717 REGLIST_VFP_D_VPR
, &partial_match
);
7718 if (val
== FAIL
&& !partial_match
)
7721 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7722 REGLIST_VFP_S_VPR
, &partial_match
);
7723 inst
.operands
[i
].issingle
= 1;
7728 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7729 REGLIST_NEON_D
, &partial_match
);
7734 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7735 1, &inst
.operands
[i
].vectype
);
7736 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7740 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7741 0, &inst
.operands
[i
].vectype
);
7744 /* Addressing modes */
7746 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7750 po_misc_or_fail (parse_address (&str
, i
));
7754 po_misc_or_fail_no_backtrack (
7755 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7759 po_misc_or_fail_no_backtrack (
7760 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7764 po_misc_or_fail_no_backtrack (
7765 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7769 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7773 po_misc_or_fail_no_backtrack (
7774 parse_shifter_operand_group_reloc (&str
, i
));
7778 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7782 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7786 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7791 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7794 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7797 po_reg_or_fail (REG_TYPE_ZR
);
7801 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7804 /* Various value-based sanity checks and shared operations. We
7805 do not signal immediate failures for the register constraints;
7806 this allows a syntax error to take precedence. */
7807 switch (op_parse_code
)
7815 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7816 inst
.error
= BAD_PC
;
7821 if (inst
.operands
[i
].isreg
)
7823 if (inst
.operands
[i
].reg
== REG_PC
)
7824 inst
.error
= BAD_PC
;
7825 else if (inst
.operands
[i
].reg
== REG_SP
7826 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7827 relaxed since ARMv8-A. */
7828 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7831 inst
.error
= BAD_SP
;
7837 if (inst
.operands
[i
].isreg
7838 && inst
.operands
[i
].reg
== REG_PC
7839 && (inst
.operands
[i
].writeback
|| thumb
))
7840 inst
.error
= BAD_PC
;
7845 if (inst
.operands
[i
].isreg
)
7855 case OP_oBARRIER_I15
:
7868 inst
.operands
[i
].imm
= val
;
7873 if (inst
.operands
[i
].reg
!= REG_LR
)
7874 inst
.error
= _("operand must be LR register");
7879 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7880 inst
.error
= BAD_PC
;
7884 if (inst
.operands
[i
].isreg
7885 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7886 inst
.error
= BAD_ODD
;
7890 if (inst
.operands
[i
].isreg
)
7892 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7893 inst
.error
= BAD_EVEN
;
7894 else if (inst
.operands
[i
].reg
== REG_SP
)
7895 as_tsktsk (MVE_BAD_SP
);
7896 else if (inst
.operands
[i
].reg
== REG_PC
)
7897 inst
.error
= BAD_PC
;
7905 /* If we get here, this operand was successfully parsed. */
7906 inst
.operands
[i
].present
= 1;
7910 inst
.error
= BAD_ARGS
;
7915 /* The parse routine should already have set inst.error, but set a
7916 default here just in case. */
7918 inst
.error
= BAD_SYNTAX
;
7922 /* Do not backtrack over a trailing optional argument that
7923 absorbed some text. We will only fail again, with the
7924 'garbage following instruction' error message, which is
7925 probably less helpful than the current one. */
7926 if (backtrack_index
== i
&& backtrack_pos
!= str
7927 && upat
[i
+1] == OP_stop
)
7930 inst
.error
= BAD_SYNTAX
;
7934 /* Try again, skipping the optional argument at backtrack_pos. */
7935 str
= backtrack_pos
;
7936 inst
.error
= backtrack_error
;
7937 inst
.operands
[backtrack_index
].present
= 0;
7938 i
= backtrack_index
;
7942 /* Check that we have parsed all the arguments. */
7943 if (*str
!= '\0' && !inst
.error
)
7944 inst
.error
= _("garbage following instruction");
7946 return inst
.error
? FAIL
: SUCCESS
;
7949 #undef po_char_or_fail
7950 #undef po_reg_or_fail
7951 #undef po_reg_or_goto
7952 #undef po_imm_or_fail
7953 #undef po_scalar_or_fail
7954 #undef po_barrier_or_imm
7956 /* Shorthand macro for instruction encoding functions issuing errors. */
7957 #define constraint(expr, err) \
7968 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7969 instructions are unpredictable if these registers are used. This
7970 is the BadReg predicate in ARM's Thumb-2 documentation.
7972 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7973 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7974 #define reject_bad_reg(reg) \
7976 if (reg == REG_PC) \
7978 inst.error = BAD_PC; \
7981 else if (reg == REG_SP \
7982 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7984 inst.error = BAD_SP; \
7989 /* If REG is R13 (the stack pointer), warn that its use is
7991 #define warn_deprecated_sp(reg) \
7993 if (warn_on_deprecated && reg == REG_SP) \
7994 as_tsktsk (_("use of r13 is deprecated")); \
7997 /* Functions for operand encoding. ARM, then Thumb. */
7999 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8001 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8003 The only binary encoding difference is the Coprocessor number. Coprocessor
8004 9 is used for half-precision calculations or conversions. The format of the
8005 instruction is the same as the equivalent Coprocessor 10 instruction that
8006 exists for Single-Precision operation. */
8009 do_scalar_fp16_v82_encode (void)
8011 if (inst
.cond
< COND_ALWAYS
)
8012 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8013 " the behaviour is UNPREDICTABLE"));
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8017 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8018 mark_feature_used (&arm_ext_fp16
);
8021 /* If VAL can be encoded in the immediate field of an ARM instruction,
8022 return the encoded form. Otherwise, return FAIL. */
8025 encode_arm_immediate (unsigned int val
)
8032 for (i
= 2; i
< 32; i
+= 2)
8033 if ((a
= rotate_left (val
, i
)) <= 0xff)
8034 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8039 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8040 return the encoded form. Otherwise, return FAIL. */
8042 encode_thumb32_immediate (unsigned int val
)
8049 for (i
= 1; i
<= 24; i
++)
8052 if ((val
& ~(0xff << i
)) == 0)
8053 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8057 if (val
== ((a
<< 16) | a
))
8059 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8063 if (val
== ((a
<< 16) | a
))
8064 return 0x200 | (a
>> 8);
8068 /* Encode a VFP SP or DP register number into inst.instruction. */
8071 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8073 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8076 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8079 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8082 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8087 first_error (_("D register out of range for selected VFP version"));
8095 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8099 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8103 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8107 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8111 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8115 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8123 /* Encode a <shift> in an ARM-format instruction. The immediate,
8124 if any, is handled by md_apply_fix. */
8126 encode_arm_shift (int i
)
8128 /* register-shifted register. */
8129 if (inst
.operands
[i
].immisreg
)
8132 for (op_index
= 0; op_index
<= i
; ++op_index
)
8134 /* Check the operand only when it's presented. In pre-UAL syntax,
8135 if the destination register is the same as the first operand, two
8136 register form of the instruction can be used. */
8137 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8138 && inst
.operands
[op_index
].reg
== REG_PC
)
8139 as_warn (UNPRED_REG ("r15"));
8142 if (inst
.operands
[i
].imm
== REG_PC
)
8143 as_warn (UNPRED_REG ("r15"));
8146 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8147 inst
.instruction
|= SHIFT_ROR
<< 5;
8150 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8151 if (inst
.operands
[i
].immisreg
)
8153 inst
.instruction
|= SHIFT_BY_REG
;
8154 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8157 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8162 encode_arm_shifter_operand (int i
)
8164 if (inst
.operands
[i
].isreg
)
8166 inst
.instruction
|= inst
.operands
[i
].reg
;
8167 encode_arm_shift (i
);
8171 inst
.instruction
|= INST_IMMEDIATE
;
8172 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8173 inst
.instruction
|= inst
.operands
[i
].imm
;
8177 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8179 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8182 Generate an error if the operand is not a register. */
8183 constraint (!inst
.operands
[i
].isreg
,
8184 _("Instruction does not support =N addresses"));
8186 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8188 if (inst
.operands
[i
].preind
)
8192 inst
.error
= _("instruction does not accept preindexed addressing");
8195 inst
.instruction
|= PRE_INDEX
;
8196 if (inst
.operands
[i
].writeback
)
8197 inst
.instruction
|= WRITE_BACK
;
8200 else if (inst
.operands
[i
].postind
)
8202 gas_assert (inst
.operands
[i
].writeback
);
8204 inst
.instruction
|= WRITE_BACK
;
8206 else /* unindexed - only for coprocessor */
8208 inst
.error
= _("instruction does not accept unindexed addressing");
8212 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8213 && (((inst
.instruction
& 0x000f0000) >> 16)
8214 == ((inst
.instruction
& 0x0000f000) >> 12)))
8215 as_warn ((inst
.instruction
& LOAD_BIT
)
8216 ? _("destination register same as write-back base")
8217 : _("source register same as write-back base"));
8220 /* inst.operands[i] was set up by parse_address. Encode it into an
8221 ARM-format mode 2 load or store instruction. If is_t is true,
8222 reject forms that cannot be used with a T instruction (i.e. not
8225 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8227 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8229 encode_arm_addr_mode_common (i
, is_t
);
8231 if (inst
.operands
[i
].immisreg
)
8233 constraint ((inst
.operands
[i
].imm
== REG_PC
8234 || (is_pc
&& inst
.operands
[i
].writeback
)),
8236 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8237 inst
.instruction
|= inst
.operands
[i
].imm
;
8238 if (!inst
.operands
[i
].negative
)
8239 inst
.instruction
|= INDEX_UP
;
8240 if (inst
.operands
[i
].shifted
)
8242 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8243 inst
.instruction
|= SHIFT_ROR
<< 5;
8246 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8247 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8251 else /* immediate offset in inst.relocs[0] */
8253 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8255 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8257 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8258 cannot use PC in addressing.
8259 PC cannot be used in writeback addressing, either. */
8260 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8263 /* Use of PC in str is deprecated for ARMv7. */
8264 if (warn_on_deprecated
8266 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8267 as_tsktsk (_("use of PC in this instruction is deprecated"));
8270 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8272 /* Prefer + for zero encoded value. */
8273 if (!inst
.operands
[i
].negative
)
8274 inst
.instruction
|= INDEX_UP
;
8275 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8280 /* inst.operands[i] was set up by parse_address. Encode it into an
8281 ARM-format mode 3 load or store instruction. Reject forms that
8282 cannot be used with such instructions. If is_t is true, reject
8283 forms that cannot be used with a T instruction (i.e. not
8286 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8288 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8290 inst
.error
= _("instruction does not accept scaled register index");
8294 encode_arm_addr_mode_common (i
, is_t
);
8296 if (inst
.operands
[i
].immisreg
)
8298 constraint ((inst
.operands
[i
].imm
== REG_PC
8299 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8301 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8303 inst
.instruction
|= inst
.operands
[i
].imm
;
8304 if (!inst
.operands
[i
].negative
)
8305 inst
.instruction
|= INDEX_UP
;
8307 else /* immediate offset in inst.relocs[0] */
8309 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8310 && inst
.operands
[i
].writeback
),
8312 inst
.instruction
|= HWOFFSET_IMM
;
8313 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8315 /* Prefer + for zero encoded value. */
8316 if (!inst
.operands
[i
].negative
)
8317 inst
.instruction
|= INDEX_UP
;
8319 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8324 /* Write immediate bits [7:0] to the following locations:
8326 |28/24|23 19|18 16|15 4|3 0|
8327 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8329 This function is used by VMOV/VMVN/VORR/VBIC. */
8332 neon_write_immbits (unsigned immbits
)
8334 inst
.instruction
|= immbits
& 0xf;
8335 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8336 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8339 /* Invert low-order SIZE bits of XHI:XLO. */
8342 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8344 unsigned immlo
= xlo
? *xlo
: 0;
8345 unsigned immhi
= xhi
? *xhi
: 0;
8350 immlo
= (~immlo
) & 0xff;
8354 immlo
= (~immlo
) & 0xffff;
8358 immhi
= (~immhi
) & 0xffffffff;
8362 immlo
= (~immlo
) & 0xffffffff;
8376 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8380 neon_bits_same_in_bytes (unsigned imm
)
8382 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8383 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8384 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8385 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8388 /* For immediate of above form, return 0bABCD. */
8391 neon_squash_bits (unsigned imm
)
8393 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8394 | ((imm
& 0x01000000) >> 21);
8397 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8400 neon_qfloat_bits (unsigned imm
)
8402 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8405 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8406 the instruction. *OP is passed as the initial value of the op field, and
8407 may be set to a different value depending on the constant (i.e.
8408 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8409 MVN). If the immediate looks like a repeated pattern then also
8410 try smaller element sizes. */
8413 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8414 unsigned *immbits
, int *op
, int size
,
8415 enum neon_el_type type
)
8417 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8419 if (type
== NT_float
&& !float_p
)
8422 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8424 if (size
!= 32 || *op
== 1)
8426 *immbits
= neon_qfloat_bits (immlo
);
8432 if (neon_bits_same_in_bytes (immhi
)
8433 && neon_bits_same_in_bytes (immlo
))
8437 *immbits
= (neon_squash_bits (immhi
) << 4)
8438 | neon_squash_bits (immlo
);
8449 if (immlo
== (immlo
& 0x000000ff))
8454 else if (immlo
== (immlo
& 0x0000ff00))
8456 *immbits
= immlo
>> 8;
8459 else if (immlo
== (immlo
& 0x00ff0000))
8461 *immbits
= immlo
>> 16;
8464 else if (immlo
== (immlo
& 0xff000000))
8466 *immbits
= immlo
>> 24;
8469 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8471 *immbits
= (immlo
>> 8) & 0xff;
8474 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8476 *immbits
= (immlo
>> 16) & 0xff;
8480 if ((immlo
& 0xffff) != (immlo
>> 16))
8487 if (immlo
== (immlo
& 0x000000ff))
8492 else if (immlo
== (immlo
& 0x0000ff00))
8494 *immbits
= immlo
>> 8;
8498 if ((immlo
& 0xff) != (immlo
>> 8))
8503 if (immlo
== (immlo
& 0x000000ff))
8505 /* Don't allow MVN with 8-bit immediate. */
8515 #if defined BFD_HOST_64_BIT
8516 /* Returns TRUE if double precision value V may be cast
8517 to single precision without loss of accuracy. */
8520 is_double_a_single (bfd_int64_t v
)
8522 int exp
= (int)((v
>> 52) & 0x7FF);
8523 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8525 return (exp
== 0 || exp
== 0x7FF
8526 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8527 && (mantissa
& 0x1FFFFFFFl
) == 0;
8530 /* Returns a double precision value casted to single precision
8531 (ignoring the least significant bits in exponent and mantissa). */
8534 double_to_single (bfd_int64_t v
)
8536 int sign
= (int) ((v
>> 63) & 1l);
8537 int exp
= (int) ((v
>> 52) & 0x7FF);
8538 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8544 exp
= exp
- 1023 + 127;
8553 /* No denormalized numbers. */
8559 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8561 #endif /* BFD_HOST_64_BIT */
8570 static void do_vfp_nsyn_opcode (const char *);
8572 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8573 Determine whether it can be performed with a move instruction; if
8574 it can, convert inst.instruction to that move instruction and
8575 return TRUE; if it can't, convert inst.instruction to a literal-pool
8576 load and return FALSE. If this is not a valid thing to do in the
8577 current context, set inst.error and return TRUE.
8579 inst.operands[i] describes the destination register. */
8582 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8585 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8586 bfd_boolean arm_p
= (t
== CONST_ARM
);
8589 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8593 if ((inst
.instruction
& tbit
) == 0)
8595 inst
.error
= _("invalid pseudo operation");
8599 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8600 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8601 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8603 inst
.error
= _("constant expression expected");
8607 if (inst
.relocs
[0].exp
.X_op
== O_constant
8608 || inst
.relocs
[0].exp
.X_op
== O_big
)
8610 #if defined BFD_HOST_64_BIT
8615 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8617 LITTLENUM_TYPE w
[X_PRECISION
];
8620 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8622 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8624 /* FIXME: Should we check words w[2..5] ? */
8629 #if defined BFD_HOST_64_BIT
8631 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8632 << LITTLENUM_NUMBER_OF_BITS
)
8633 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8634 << LITTLENUM_NUMBER_OF_BITS
)
8635 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8636 << LITTLENUM_NUMBER_OF_BITS
)
8637 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8639 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8640 | (l
[0] & LITTLENUM_MASK
);
8644 v
= inst
.relocs
[0].exp
.X_add_number
;
8646 if (!inst
.operands
[i
].issingle
)
8650 /* LDR should not use lead in a flag-setting instruction being
8651 chosen so we do not check whether movs can be used. */
8653 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8654 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8655 && inst
.operands
[i
].reg
!= 13
8656 && inst
.operands
[i
].reg
!= 15)
8658 /* Check if on thumb2 it can be done with a mov.w, mvn or
8659 movw instruction. */
8660 unsigned int newimm
;
8661 bfd_boolean isNegated
;
8663 newimm
= encode_thumb32_immediate (v
);
8664 if (newimm
!= (unsigned int) FAIL
)
8668 newimm
= encode_thumb32_immediate (~v
);
8669 if (newimm
!= (unsigned int) FAIL
)
8673 /* The number can be loaded with a mov.w or mvn
8675 if (newimm
!= (unsigned int) FAIL
8676 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8678 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8679 | (inst
.operands
[i
].reg
<< 8));
8680 /* Change to MOVN. */
8681 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8682 inst
.instruction
|= (newimm
& 0x800) << 15;
8683 inst
.instruction
|= (newimm
& 0x700) << 4;
8684 inst
.instruction
|= (newimm
& 0x0ff);
8687 /* The number can be loaded with a movw instruction. */
8688 else if ((v
& ~0xFFFF) == 0
8689 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8691 int imm
= v
& 0xFFFF;
8693 inst
.instruction
= 0xf2400000; /* MOVW. */
8694 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8695 inst
.instruction
|= (imm
& 0xf000) << 4;
8696 inst
.instruction
|= (imm
& 0x0800) << 15;
8697 inst
.instruction
|= (imm
& 0x0700) << 4;
8698 inst
.instruction
|= (imm
& 0x00ff);
8705 int value
= encode_arm_immediate (v
);
8709 /* This can be done with a mov instruction. */
8710 inst
.instruction
&= LITERAL_MASK
;
8711 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8712 inst
.instruction
|= value
& 0xfff;
8716 value
= encode_arm_immediate (~ v
);
8719 /* This can be done with a mvn instruction. */
8720 inst
.instruction
&= LITERAL_MASK
;
8721 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8722 inst
.instruction
|= value
& 0xfff;
8726 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8729 unsigned immbits
= 0;
8730 unsigned immlo
= inst
.operands
[1].imm
;
8731 unsigned immhi
= inst
.operands
[1].regisimm
8732 ? inst
.operands
[1].reg
8733 : inst
.relocs
[0].exp
.X_unsigned
8735 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8736 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8737 &op
, 64, NT_invtype
);
8741 neon_invert_size (&immlo
, &immhi
, 64);
8743 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8744 &op
, 64, NT_invtype
);
8749 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8755 /* Fill other bits in vmov encoding for both thumb and arm. */
8757 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8759 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8760 neon_write_immbits (immbits
);
8768 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8769 if (inst
.operands
[i
].issingle
8770 && is_quarter_float (inst
.operands
[1].imm
)
8771 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8773 inst
.operands
[1].imm
=
8774 neon_qfloat_bits (v
);
8775 do_vfp_nsyn_opcode ("fconsts");
8779 /* If our host does not support a 64-bit type then we cannot perform
8780 the following optimization. This mean that there will be a
8781 discrepancy between the output produced by an assembler built for
8782 a 32-bit-only host and the output produced from a 64-bit host, but
8783 this cannot be helped. */
8784 #if defined BFD_HOST_64_BIT
8785 else if (!inst
.operands
[1].issingle
8786 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8788 if (is_double_a_single (v
)
8789 && is_quarter_float (double_to_single (v
)))
8791 inst
.operands
[1].imm
=
8792 neon_qfloat_bits (double_to_single (v
));
8793 do_vfp_nsyn_opcode ("fconstd");
8801 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8802 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8805 inst
.operands
[1].reg
= REG_PC
;
8806 inst
.operands
[1].isreg
= 1;
8807 inst
.operands
[1].preind
= 1;
8808 inst
.relocs
[0].pc_rel
= 1;
8809 inst
.relocs
[0].type
= (thumb_p
8810 ? BFD_RELOC_ARM_THUMB_OFFSET
8812 ? BFD_RELOC_ARM_HWLITERAL
8813 : BFD_RELOC_ARM_LITERAL
));
8817 /* inst.operands[i] was set up by parse_address. Encode it into an
8818 ARM-format instruction. Reject all forms which cannot be encoded
8819 into a coprocessor load/store instruction. If wb_ok is false,
8820 reject use of writeback; if unind_ok is false, reject use of
8821 unindexed addressing. If reloc_override is not 0, use it instead
8822 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8823 (in which case it is preserved). */
8826 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8828 if (!inst
.operands
[i
].isreg
)
8831 if (! inst
.operands
[0].isvec
)
8833 inst
.error
= _("invalid co-processor operand");
8836 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8840 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8842 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8844 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8846 gas_assert (!inst
.operands
[i
].writeback
);
8849 inst
.error
= _("instruction does not support unindexed addressing");
8852 inst
.instruction
|= inst
.operands
[i
].imm
;
8853 inst
.instruction
|= INDEX_UP
;
8857 if (inst
.operands
[i
].preind
)
8858 inst
.instruction
|= PRE_INDEX
;
8860 if (inst
.operands
[i
].writeback
)
8862 if (inst
.operands
[i
].reg
== REG_PC
)
8864 inst
.error
= _("pc may not be used with write-back");
8869 inst
.error
= _("instruction does not support writeback");
8872 inst
.instruction
|= WRITE_BACK
;
8876 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8877 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8878 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8879 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8882 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8884 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8887 /* Prefer + for zero encoded value. */
8888 if (!inst
.operands
[i
].negative
)
8889 inst
.instruction
|= INDEX_UP
;
8894 /* Functions for instruction encoding, sorted by sub-architecture.
8895 First some generics; their names are taken from the conventional
8896 bit positions for register arguments in ARM format instructions. */
8906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8912 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8918 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8919 inst
.instruction
|= inst
.operands
[1].reg
;
8925 inst
.instruction
|= inst
.operands
[0].reg
;
8926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8933 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8939 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8940 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8946 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8951 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8953 if (ARM_CPU_IS_ANY (cpu_variant
))
8955 as_tsktsk ("%s", msg
);
8958 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8970 unsigned Rn
= inst
.operands
[2].reg
;
8971 /* Enforce restrictions on SWP instruction. */
8972 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8974 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8975 _("Rn must not overlap other operands"));
8977 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8979 if (!check_obsolete (&arm_ext_v8
,
8980 _("swp{b} use is obsoleted for ARMv8 and later"))
8981 && warn_on_deprecated
8982 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8983 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 inst
.instruction
|= inst
.operands
[1].reg
;
8988 inst
.instruction
|= Rn
<< 16;
8994 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8996 inst
.instruction
|= inst
.operands
[2].reg
;
9002 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9003 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9004 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9005 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9007 inst
.instruction
|= inst
.operands
[0].reg
;
9008 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9009 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9015 inst
.instruction
|= inst
.operands
[0].imm
;
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9025 /* ARM instructions, in alphabetical order by function name (except
9026 that wrapper functions appear immediately after the function they
9029 /* This is a pseudo-op of the form "adr rd, label" to be converted
9030 into a relative address of the form "add rd, pc, #label-.-8". */
9035 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9037 /* Frag hacking will turn this into a sub instruction if the offset turns
9038 out to be negative. */
9039 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9040 inst
.relocs
[0].pc_rel
= 1;
9041 inst
.relocs
[0].exp
.X_add_number
-= 8;
9043 if (support_interwork
9044 && inst
.relocs
[0].exp
.X_op
== O_symbol
9045 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9046 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9047 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9048 inst
.relocs
[0].exp
.X_add_number
|= 1;
9051 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9052 into a relative address of the form:
9053 add rd, pc, #low(label-.-8)"
9054 add rd, rd, #high(label-.-8)" */
9059 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9061 /* Frag hacking will turn this into a sub instruction if the offset turns
9062 out to be negative. */
9063 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9064 inst
.relocs
[0].pc_rel
= 1;
9065 inst
.size
= INSN_SIZE
* 2;
9066 inst
.relocs
[0].exp
.X_add_number
-= 8;
9068 if (support_interwork
9069 && inst
.relocs
[0].exp
.X_op
== O_symbol
9070 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9071 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9072 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9073 inst
.relocs
[0].exp
.X_add_number
|= 1;
9079 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9080 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9082 if (!inst
.operands
[1].present
)
9083 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9086 encode_arm_shifter_operand (2);
9092 if (inst
.operands
[0].present
)
9093 inst
.instruction
|= inst
.operands
[0].imm
;
9095 inst
.instruction
|= 0xf;
9101 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9102 constraint (msb
> 32, _("bit-field extends past end of register"));
9103 /* The instruction encoding stores the LSB and MSB,
9104 not the LSB and width. */
9105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9106 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9107 inst
.instruction
|= (msb
- 1) << 16;
9115 /* #0 in second position is alternative syntax for bfc, which is
9116 the same instruction but with REG_PC in the Rm field. */
9117 if (!inst
.operands
[1].isreg
)
9118 inst
.operands
[1].reg
= REG_PC
;
9120 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9121 constraint (msb
> 32, _("bit-field extends past end of register"));
9122 /* The instruction encoding stores the LSB and MSB,
9123 not the LSB and width. */
9124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9125 inst
.instruction
|= inst
.operands
[1].reg
;
9126 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9127 inst
.instruction
|= (msb
- 1) << 16;
9133 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9134 _("bit-field extends past end of register"));
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 inst
.instruction
|= inst
.operands
[1].reg
;
9137 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9138 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9141 /* ARM V5 breakpoint instruction (argument parse)
9142 BKPT <16 bit unsigned immediate>
9143 Instruction is not conditional.
9144 The bit pattern given in insns[] has the COND_ALWAYS condition,
9145 and it is an error if the caller tried to override that. */
9150 /* Top 12 of 16 bits to bits 19:8. */
9151 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9153 /* Bottom 4 of 16 bits to bits 3:0. */
9154 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9158 encode_branch (int default_reloc
)
9160 if (inst
.operands
[0].hasreloc
)
9162 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9163 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9164 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9165 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9166 ? BFD_RELOC_ARM_PLT32
9167 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9170 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9171 inst
.relocs
[0].pc_rel
= 1;
9178 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9179 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9182 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9189 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9191 if (inst
.cond
== COND_ALWAYS
)
9192 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9194 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9201 /* ARM V5 branch-link-exchange instruction (argument parse)
9202 BLX <target_addr> ie BLX(1)
9203 BLX{<condition>} <Rm> ie BLX(2)
9204 Unfortunately, there are two different opcodes for this mnemonic.
9205 So, the insns[].value is not used, and the code here zaps values
9206 into inst.instruction.
9207 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9212 if (inst
.operands
[0].isreg
)
9214 /* Arg is a register; the opcode provided by insns[] is correct.
9215 It is not illegal to do "blx pc", just useless. */
9216 if (inst
.operands
[0].reg
== REG_PC
)
9217 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9219 inst
.instruction
|= inst
.operands
[0].reg
;
9223 /* Arg is an address; this instruction cannot be executed
9224 conditionally, and the opcode must be adjusted.
9225 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9226 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9227 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9228 inst
.instruction
= 0xfa000000;
9229 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9236 bfd_boolean want_reloc
;
9238 if (inst
.operands
[0].reg
== REG_PC
)
9239 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9241 inst
.instruction
|= inst
.operands
[0].reg
;
9242 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9243 it is for ARMv4t or earlier. */
9244 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9245 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9246 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9250 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9255 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9259 /* ARM v5TEJ. Jump to Jazelle code. */
9264 if (inst
.operands
[0].reg
== REG_PC
)
9265 as_tsktsk (_("use of r15 in bxj is not really useful"));
9267 inst
.instruction
|= inst
.operands
[0].reg
;
9270 /* Co-processor data operation:
9271 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9272 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9277 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9278 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9279 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9280 inst
.instruction
|= inst
.operands
[4].reg
;
9281 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9288 encode_arm_shifter_operand (1);
9291 /* Transfer between coprocessor and ARM registers.
9292 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9297 No special properties. */
9299 struct deprecated_coproc_regs_s
9306 arm_feature_set deprecated
;
9307 arm_feature_set obsoleted
;
9308 const char *dep_msg
;
9309 const char *obs_msg
;
9312 #define DEPR_ACCESS_V8 \
9313 N_("This coprocessor register access is deprecated in ARMv8")
9315 /* Table of all deprecated coprocessor registers. */
9316 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9318 {15, 0, 7, 10, 5, /* CP15DMB. */
9319 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9320 DEPR_ACCESS_V8
, NULL
},
9321 {15, 0, 7, 10, 4, /* CP15DSB. */
9322 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9323 DEPR_ACCESS_V8
, NULL
},
9324 {15, 0, 7, 5, 4, /* CP15ISB. */
9325 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9326 DEPR_ACCESS_V8
, NULL
},
9327 {14, 6, 1, 0, 0, /* TEEHBR. */
9328 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9329 DEPR_ACCESS_V8
, NULL
},
9330 {14, 6, 0, 0, 0, /* TEECR. */
9331 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9332 DEPR_ACCESS_V8
, NULL
},
9335 #undef DEPR_ACCESS_V8
9337 static const size_t deprecated_coproc_reg_count
=
9338 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9346 Rd
= inst
.operands
[2].reg
;
9349 if (inst
.instruction
== 0xee000010
9350 || inst
.instruction
== 0xfe000010)
9352 reject_bad_reg (Rd
);
9353 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9355 constraint (Rd
== REG_SP
, BAD_SP
);
9360 if (inst
.instruction
== 0xe000010)
9361 constraint (Rd
== REG_PC
, BAD_PC
);
9364 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9366 const struct deprecated_coproc_regs_s
*r
=
9367 deprecated_coproc_regs
+ i
;
9369 if (inst
.operands
[0].reg
== r
->cp
9370 && inst
.operands
[1].imm
== r
->opc1
9371 && inst
.operands
[3].reg
== r
->crn
9372 && inst
.operands
[4].reg
== r
->crm
9373 && inst
.operands
[5].imm
== r
->opc2
)
9375 if (! ARM_CPU_IS_ANY (cpu_variant
)
9376 && warn_on_deprecated
9377 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9378 as_tsktsk ("%s", r
->dep_msg
);
9382 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9383 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9384 inst
.instruction
|= Rd
<< 12;
9385 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9386 inst
.instruction
|= inst
.operands
[4].reg
;
9387 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9390 /* Transfer between coprocessor register and pair of ARM registers.
9391 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9396 Two XScale instructions are special cases of these:
9398 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9399 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9401 Result unpredictable if Rd or Rn is R15. */
9408 Rd
= inst
.operands
[2].reg
;
9409 Rn
= inst
.operands
[3].reg
;
9413 reject_bad_reg (Rd
);
9414 reject_bad_reg (Rn
);
9418 constraint (Rd
== REG_PC
, BAD_PC
);
9419 constraint (Rn
== REG_PC
, BAD_PC
);
9422 /* Only check the MRRC{2} variants. */
9423 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9425 /* If Rd == Rn, error that the operation is
9426 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9427 constraint (Rd
== Rn
, BAD_OVERLAP
);
9430 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9431 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9432 inst
.instruction
|= Rd
<< 12;
9433 inst
.instruction
|= Rn
<< 16;
9434 inst
.instruction
|= inst
.operands
[4].reg
;
9440 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9441 if (inst
.operands
[1].present
)
9443 inst
.instruction
|= CPSI_MMOD
;
9444 inst
.instruction
|= inst
.operands
[1].imm
;
9451 inst
.instruction
|= inst
.operands
[0].imm
;
9457 unsigned Rd
, Rn
, Rm
;
9459 Rd
= inst
.operands
[0].reg
;
9460 Rn
= (inst
.operands
[1].present
9461 ? inst
.operands
[1].reg
: Rd
);
9462 Rm
= inst
.operands
[2].reg
;
9464 constraint ((Rd
== REG_PC
), BAD_PC
);
9465 constraint ((Rn
== REG_PC
), BAD_PC
);
9466 constraint ((Rm
== REG_PC
), BAD_PC
);
9468 inst
.instruction
|= Rd
<< 16;
9469 inst
.instruction
|= Rn
<< 0;
9470 inst
.instruction
|= Rm
<< 8;
9476 /* There is no IT instruction in ARM mode. We
9477 process it to do the validation as if in
9478 thumb mode, just in case the code gets
9479 assembled for thumb using the unified syntax. */
9484 set_pred_insn_type (IT_INSN
);
9485 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9486 now_pred
.cc
= inst
.operands
[0].imm
;
9490 /* If there is only one register in the register list,
9491 then return its register number. Otherwise return -1. */
9493 only_one_reg_in_list (int range
)
9495 int i
= ffs (range
) - 1;
9496 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9500 encode_ldmstm(int from_push_pop_mnem
)
9502 int base_reg
= inst
.operands
[0].reg
;
9503 int range
= inst
.operands
[1].imm
;
9506 inst
.instruction
|= base_reg
<< 16;
9507 inst
.instruction
|= range
;
9509 if (inst
.operands
[1].writeback
)
9510 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9512 if (inst
.operands
[0].writeback
)
9514 inst
.instruction
|= WRITE_BACK
;
9515 /* Check for unpredictable uses of writeback. */
9516 if (inst
.instruction
& LOAD_BIT
)
9518 /* Not allowed in LDM type 2. */
9519 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9520 && ((range
& (1 << REG_PC
)) == 0))
9521 as_warn (_("writeback of base register is UNPREDICTABLE"));
9522 /* Only allowed if base reg not in list for other types. */
9523 else if (range
& (1 << base_reg
))
9524 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9528 /* Not allowed for type 2. */
9529 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9530 as_warn (_("writeback of base register is UNPREDICTABLE"));
9531 /* Only allowed if base reg not in list, or first in list. */
9532 else if ((range
& (1 << base_reg
))
9533 && (range
& ((1 << base_reg
) - 1)))
9534 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9538 /* If PUSH/POP has only one register, then use the A2 encoding. */
9539 one_reg
= only_one_reg_in_list (range
);
9540 if (from_push_pop_mnem
&& one_reg
>= 0)
9542 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9544 if (is_push
&& one_reg
== 13 /* SP */)
9545 /* PR 22483: The A2 encoding cannot be used when
9546 pushing the stack pointer as this is UNPREDICTABLE. */
9549 inst
.instruction
&= A_COND_MASK
;
9550 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9551 inst
.instruction
|= one_reg
<< 12;
9558 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9561 /* ARMv5TE load-consecutive (argument parse)
9570 constraint (inst
.operands
[0].reg
% 2 != 0,
9571 _("first transfer register must be even"));
9572 constraint (inst
.operands
[1].present
9573 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9574 _("can only transfer two consecutive registers"));
9575 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9576 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9578 if (!inst
.operands
[1].present
)
9579 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9581 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9582 register and the first register written; we have to diagnose
9583 overlap between the base and the second register written here. */
9585 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9586 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9587 as_warn (_("base register written back, and overlaps "
9588 "second transfer register"));
9590 if (!(inst
.instruction
& V4_STR_BIT
))
9592 /* For an index-register load, the index register must not overlap the
9593 destination (even if not write-back). */
9594 if (inst
.operands
[2].immisreg
9595 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9596 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9597 as_warn (_("index register overlaps transfer register"));
9599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9600 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9606 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9607 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9608 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9609 || inst
.operands
[1].negative
9610 /* This can arise if the programmer has written
9612 or if they have mistakenly used a register name as the last
9615 It is very difficult to distinguish between these two cases
9616 because "rX" might actually be a label. ie the register
9617 name has been occluded by a symbol of the same name. So we
9618 just generate a general 'bad addressing mode' type error
9619 message and leave it up to the programmer to discover the
9620 true cause and fix their mistake. */
9621 || (inst
.operands
[1].reg
== REG_PC
),
9624 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9625 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9626 _("offset must be zero in ARM encoding"));
9628 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9631 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9632 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9638 constraint (inst
.operands
[0].reg
% 2 != 0,
9639 _("even register required"));
9640 constraint (inst
.operands
[1].present
9641 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9642 _("can only load two consecutive registers"));
9643 /* If op 1 were present and equal to PC, this function wouldn't
9644 have been called in the first place. */
9645 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9648 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9651 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9652 which is not a multiple of four is UNPREDICTABLE. */
9654 check_ldr_r15_aligned (void)
9656 constraint (!(inst
.operands
[1].immisreg
)
9657 && (inst
.operands
[0].reg
== REG_PC
9658 && inst
.operands
[1].reg
== REG_PC
9659 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9660 _("ldr to register 15 must be 4-byte aligned"));
9666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9667 if (!inst
.operands
[1].isreg
)
9668 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9670 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9671 check_ldr_r15_aligned ();
9677 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9679 if (inst
.operands
[1].preind
)
9681 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9682 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9683 _("this instruction requires a post-indexed address"));
9685 inst
.operands
[1].preind
= 0;
9686 inst
.operands
[1].postind
= 1;
9687 inst
.operands
[1].writeback
= 1;
9689 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9690 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9693 /* Halfword and signed-byte load/store operations. */
9698 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9700 if (!inst
.operands
[1].isreg
)
9701 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9703 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9709 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9711 if (inst
.operands
[1].preind
)
9713 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9714 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9715 _("this instruction requires a post-indexed address"));
9717 inst
.operands
[1].preind
= 0;
9718 inst
.operands
[1].postind
= 1;
9719 inst
.operands
[1].writeback
= 1;
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9722 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9725 /* Co-processor register load/store.
9726 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9731 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9732 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9738 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9739 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9740 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9741 && !(inst
.instruction
& 0x00400000))
9742 as_tsktsk (_("Rd and Rm should be different in mla"));
9744 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9745 inst
.instruction
|= inst
.operands
[1].reg
;
9746 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9747 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9753 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9754 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9756 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9757 encode_arm_shifter_operand (1);
9760 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9767 top
= (inst
.instruction
& 0x00400000) != 0;
9768 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9769 _(":lower16: not allowed in this instruction"));
9770 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9771 _(":upper16: not allowed in this instruction"));
9772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9773 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9775 imm
= inst
.relocs
[0].exp
.X_add_number
;
9776 /* The value is in two pieces: 0:11, 16:19. */
9777 inst
.instruction
|= (imm
& 0x00000fff);
9778 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9783 do_vfp_nsyn_mrs (void)
9785 if (inst
.operands
[0].isvec
)
9787 if (inst
.operands
[1].reg
!= 1)
9788 first_error (_("operand 1 must be FPSCR"));
9789 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9790 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9791 do_vfp_nsyn_opcode ("fmstat");
9793 else if (inst
.operands
[1].isvec
)
9794 do_vfp_nsyn_opcode ("fmrx");
9802 do_vfp_nsyn_msr (void)
9804 if (inst
.operands
[0].isvec
)
9805 do_vfp_nsyn_opcode ("fmxr");
9815 unsigned Rt
= inst
.operands
[0].reg
;
9817 if (thumb_mode
&& Rt
== REG_SP
)
9819 inst
.error
= BAD_SP
;
9823 /* MVFR2 is only valid at ARMv8-A. */
9824 if (inst
.operands
[1].reg
== 5)
9825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9828 /* APSR_ sets isvec. All other refs to PC are illegal. */
9829 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9831 inst
.error
= BAD_PC
;
9835 /* If we get through parsing the register name, we just insert the number
9836 generated into the instruction without further validation. */
9837 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9838 inst
.instruction
|= (Rt
<< 12);
9844 unsigned Rt
= inst
.operands
[1].reg
;
9847 reject_bad_reg (Rt
);
9848 else if (Rt
== REG_PC
)
9850 inst
.error
= BAD_PC
;
9854 /* MVFR2 is only valid for ARMv8-A. */
9855 if (inst
.operands
[0].reg
== 5)
9856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9859 /* If we get through parsing the register name, we just insert the number
9860 generated into the instruction without further validation. */
9861 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9862 inst
.instruction
|= (Rt
<< 12);
9870 if (do_vfp_nsyn_mrs () == SUCCESS
)
9873 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9876 if (inst
.operands
[1].isreg
)
9878 br
= inst
.operands
[1].reg
;
9879 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9880 as_bad (_("bad register for mrs"));
9884 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9885 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9887 _("'APSR', 'CPSR' or 'SPSR' expected"));
9888 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9891 inst
.instruction
|= br
;
9894 /* Two possible forms:
9895 "{C|S}PSR_<field>, Rm",
9896 "{C|S}PSR_f, #expression". */
9901 if (do_vfp_nsyn_msr () == SUCCESS
)
9904 inst
.instruction
|= inst
.operands
[0].imm
;
9905 if (inst
.operands
[1].isreg
)
9906 inst
.instruction
|= inst
.operands
[1].reg
;
9909 inst
.instruction
|= INST_IMMEDIATE
;
9910 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9911 inst
.relocs
[0].pc_rel
= 0;
9918 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9920 if (!inst
.operands
[2].present
)
9921 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9923 inst
.instruction
|= inst
.operands
[1].reg
;
9924 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9926 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9927 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9928 as_tsktsk (_("Rd and Rm should be different in mul"));
9931 /* Long Multiply Parser
9932 UMULL RdLo, RdHi, Rm, Rs
9933 SMULL RdLo, RdHi, Rm, Rs
9934 UMLAL RdLo, RdHi, Rm, Rs
9935 SMLAL RdLo, RdHi, Rm, Rs. */
9940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9941 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9942 inst
.instruction
|= inst
.operands
[2].reg
;
9943 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9945 /* rdhi and rdlo must be different. */
9946 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9947 as_tsktsk (_("rdhi and rdlo must be different"));
9949 /* rdhi, rdlo and rm must all be different before armv6. */
9950 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9951 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9952 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9953 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9959 if (inst
.operands
[0].present
9960 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9962 /* Architectural NOP hints are CPSR sets with no bits selected. */
9963 inst
.instruction
&= 0xf0000000;
9964 inst
.instruction
|= 0x0320f000;
9965 if (inst
.operands
[0].present
)
9966 inst
.instruction
|= inst
.operands
[0].imm
;
9970 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9971 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9972 Condition defaults to COND_ALWAYS.
9973 Error if Rd, Rn or Rm are R15. */
9978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9980 inst
.instruction
|= inst
.operands
[2].reg
;
9981 if (inst
.operands
[3].present
)
9982 encode_arm_shift (3);
9985 /* ARM V6 PKHTB (Argument Parse). */
9990 if (!inst
.operands
[3].present
)
9992 /* If the shift specifier is omitted, turn the instruction
9993 into pkhbt rd, rm, rn. */
9994 inst
.instruction
&= 0xfff00010;
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9996 inst
.instruction
|= inst
.operands
[1].reg
;
9997 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10002 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10003 inst
.instruction
|= inst
.operands
[2].reg
;
10004 encode_arm_shift (3);
10008 /* ARMv5TE: Preload-Cache
10009 MP Extensions: Preload for write
10013 Syntactically, like LDR with B=1, W=0, L=1. */
10018 constraint (!inst
.operands
[0].isreg
,
10019 _("'[' expected after PLD mnemonic"));
10020 constraint (inst
.operands
[0].postind
,
10021 _("post-indexed expression used in preload instruction"));
10022 constraint (inst
.operands
[0].writeback
,
10023 _("writeback used in preload instruction"));
10024 constraint (!inst
.operands
[0].preind
,
10025 _("unindexed addressing used in preload instruction"));
10026 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10029 /* ARMv7: PLI <addr_mode> */
10033 constraint (!inst
.operands
[0].isreg
,
10034 _("'[' expected after PLI mnemonic"));
10035 constraint (inst
.operands
[0].postind
,
10036 _("post-indexed expression used in preload instruction"));
10037 constraint (inst
.operands
[0].writeback
,
10038 _("writeback used in preload instruction"));
10039 constraint (!inst
.operands
[0].preind
,
10040 _("unindexed addressing used in preload instruction"));
10041 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10042 inst
.instruction
&= ~PRE_INDEX
;
10048 constraint (inst
.operands
[0].writeback
,
10049 _("push/pop do not support {reglist}^"));
10050 inst
.operands
[1] = inst
.operands
[0];
10051 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10052 inst
.operands
[0].isreg
= 1;
10053 inst
.operands
[0].writeback
= 1;
10054 inst
.operands
[0].reg
= REG_SP
;
10055 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10058 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10059 word at the specified address and the following word
10061 Unconditionally executed.
10062 Error if Rn is R15. */
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10068 if (inst
.operands
[0].writeback
)
10069 inst
.instruction
|= WRITE_BACK
;
10072 /* ARM V6 ssat (argument parse). */
10077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10078 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10079 inst
.instruction
|= inst
.operands
[2].reg
;
10081 if (inst
.operands
[3].present
)
10082 encode_arm_shift (3);
10085 /* ARM V6 usat (argument parse). */
10090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10091 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10092 inst
.instruction
|= inst
.operands
[2].reg
;
10094 if (inst
.operands
[3].present
)
10095 encode_arm_shift (3);
10098 /* ARM V6 ssat16 (argument parse). */
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10104 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10105 inst
.instruction
|= inst
.operands
[2].reg
;
10111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10112 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10113 inst
.instruction
|= inst
.operands
[2].reg
;
10116 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10117 preserving the other bits.
10119 setend <endian_specifier>, where <endian_specifier> is either
10125 if (warn_on_deprecated
10126 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10127 as_tsktsk (_("setend use is deprecated for ARMv8"));
10129 if (inst
.operands
[0].imm
)
10130 inst
.instruction
|= 0x200;
10136 unsigned int Rm
= (inst
.operands
[1].present
10137 ? inst
.operands
[1].reg
10138 : inst
.operands
[0].reg
);
10140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10141 inst
.instruction
|= Rm
;
10142 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10144 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10145 inst
.instruction
|= SHIFT_BY_REG
;
10146 /* PR 12854: Error on extraneous shifts. */
10147 constraint (inst
.operands
[2].shifted
,
10148 _("extraneous shift as part of operand to shift insn"));
10151 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10157 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10158 inst
.relocs
[0].pc_rel
= 0;
10164 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10165 inst
.relocs
[0].pc_rel
= 0;
10171 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10172 inst
.relocs
[0].pc_rel
= 0;
10178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10179 _("selected processor does not support SETPAN instruction"));
10181 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10188 _("selected processor does not support SETPAN instruction"));
10190 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10193 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10194 SMLAxy{cond} Rd,Rm,Rs,Rn
10195 SMLAWy{cond} Rd,Rm,Rs,Rn
10196 Error if any register is R15. */
10201 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10202 inst
.instruction
|= inst
.operands
[1].reg
;
10203 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10204 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10207 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10208 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10209 Error if any register is R15.
10210 Warning if Rdlo == Rdhi. */
10215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10216 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10217 inst
.instruction
|= inst
.operands
[2].reg
;
10218 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10220 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10221 as_tsktsk (_("rdhi and rdlo must be different"));
10224 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10225 SMULxy{cond} Rd,Rm,Rs
10226 Error if any register is R15. */
10231 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10232 inst
.instruction
|= inst
.operands
[1].reg
;
10233 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10236 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10237 the same for both ARM and Thumb-2. */
10244 if (inst
.operands
[0].present
)
10246 reg
= inst
.operands
[0].reg
;
10247 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10252 inst
.instruction
|= reg
<< 16;
10253 inst
.instruction
|= inst
.operands
[1].imm
;
10254 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10255 inst
.instruction
|= WRITE_BACK
;
10258 /* ARM V6 strex (argument parse). */
10263 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10264 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10265 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10266 || inst
.operands
[2].negative
10267 /* See comment in do_ldrex(). */
10268 || (inst
.operands
[2].reg
== REG_PC
),
10271 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10272 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10274 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10275 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10276 _("offset must be zero in ARM encoding"));
10278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10279 inst
.instruction
|= inst
.operands
[1].reg
;
10280 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10281 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10285 do_t_strexbh (void)
10287 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10288 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10289 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10290 || inst
.operands
[2].negative
,
10293 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10294 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10302 constraint (inst
.operands
[1].reg
% 2 != 0,
10303 _("even register required"));
10304 constraint (inst
.operands
[2].present
10305 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10306 _("can only store two consecutive registers"));
10307 /* If op 2 were present and equal to PC, this function wouldn't
10308 have been called in the first place. */
10309 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10311 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10312 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10313 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10317 inst
.instruction
|= inst
.operands
[1].reg
;
10318 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10326 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10334 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10335 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10340 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10341 extends it to 32-bits, and adds the result to a value in another
10342 register. You can specify a rotation by 0, 8, 16, or 24 bits
10343 before extracting the 16-bit value.
10344 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10345 Condition defaults to COND_ALWAYS.
10346 Error if any register uses R15. */
10351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10353 inst
.instruction
|= inst
.operands
[2].reg
;
10354 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10359 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10360 Condition defaults to COND_ALWAYS.
10361 Error if any register uses R15. */
10366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10367 inst
.instruction
|= inst
.operands
[1].reg
;
10368 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10371 /* VFP instructions. In a logical order: SP variant first, monad
10372 before dyad, arithmetic then move then load/store. */
10375 do_vfp_sp_monadic (void)
10377 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10378 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10381 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10382 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10386 do_vfp_sp_dyadic (void)
10388 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10389 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10390 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10394 do_vfp_sp_compare_z (void)
10396 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10400 do_vfp_dp_sp_cvt (void)
10402 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10403 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10407 do_vfp_sp_dp_cvt (void)
10409 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10410 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10414 do_vfp_reg_from_sp (void)
10416 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10417 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10421 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10425 do_vfp_reg2_from_sp2 (void)
10427 constraint (inst
.operands
[2].imm
!= 2,
10428 _("only two consecutive VFP SP registers allowed here"));
10429 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10430 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10431 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10435 do_vfp_sp_from_reg (void)
10437 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10438 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10441 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10442 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10446 do_vfp_sp2_from_reg2 (void)
10448 constraint (inst
.operands
[0].imm
!= 2,
10449 _("only two consecutive VFP SP registers allowed here"));
10450 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10451 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10452 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10456 do_vfp_sp_ldst (void)
10458 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10459 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10463 do_vfp_dp_ldst (void)
10465 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10466 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10471 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10473 if (inst
.operands
[0].writeback
)
10474 inst
.instruction
|= WRITE_BACK
;
10476 constraint (ldstm_type
!= VFP_LDSTMIA
,
10477 _("this addressing mode requires base-register writeback"));
10478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10479 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10480 inst
.instruction
|= inst
.operands
[1].imm
;
10484 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10488 if (inst
.operands
[0].writeback
)
10489 inst
.instruction
|= WRITE_BACK
;
10491 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10492 _("this addressing mode requires base-register writeback"));
10494 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10495 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10497 count
= inst
.operands
[1].imm
<< 1;
10498 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10501 inst
.instruction
|= count
;
10505 do_vfp_sp_ldstmia (void)
10507 vfp_sp_ldstm (VFP_LDSTMIA
);
10511 do_vfp_sp_ldstmdb (void)
10513 vfp_sp_ldstm (VFP_LDSTMDB
);
10517 do_vfp_dp_ldstmia (void)
10519 vfp_dp_ldstm (VFP_LDSTMIA
);
10523 do_vfp_dp_ldstmdb (void)
10525 vfp_dp_ldstm (VFP_LDSTMDB
);
10529 do_vfp_xp_ldstmia (void)
10531 vfp_dp_ldstm (VFP_LDSTMIAX
);
10535 do_vfp_xp_ldstmdb (void)
10537 vfp_dp_ldstm (VFP_LDSTMDBX
);
10541 do_vfp_dp_rd_rm (void)
10543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10544 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10547 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10548 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10552 do_vfp_dp_rn_rd (void)
10554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10555 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10559 do_vfp_dp_rd_rn (void)
10561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10562 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10566 do_vfp_dp_rd_rn_rm (void)
10568 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10569 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10574 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10578 do_vfp_dp_rd (void)
10580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10584 do_vfp_dp_rm_rd_rn (void)
10586 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10587 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10592 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10595 /* VFPv3 instructions. */
10597 do_vfp_sp_const (void)
10599 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10600 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10601 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10605 do_vfp_dp_const (void)
10607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10608 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10609 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10613 vfp_conv (int srcsize
)
10615 int immbits
= srcsize
- inst
.operands
[1].imm
;
10617 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10619 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10620 i.e. immbits must be in range 0 - 16. */
10621 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10624 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10626 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10627 i.e. immbits must be in range 0 - 31. */
10628 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10632 inst
.instruction
|= (immbits
& 1) << 5;
10633 inst
.instruction
|= (immbits
>> 1);
10637 do_vfp_sp_conv_16 (void)
10639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10644 do_vfp_dp_conv_16 (void)
10646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10651 do_vfp_sp_conv_32 (void)
10653 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10658 do_vfp_dp_conv_32 (void)
10660 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10664 /* FPA instructions. Also in a logical order. */
10669 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10670 inst
.instruction
|= inst
.operands
[1].reg
;
10674 do_fpa_ldmstm (void)
10676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10677 switch (inst
.operands
[1].imm
)
10679 case 1: inst
.instruction
|= CP_T_X
; break;
10680 case 2: inst
.instruction
|= CP_T_Y
; break;
10681 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10686 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10688 /* The instruction specified "ea" or "fd", so we can only accept
10689 [Rn]{!}. The instruction does not really support stacking or
10690 unstacking, so we have to emulate these by setting appropriate
10691 bits and offsets. */
10692 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10693 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10694 _("this instruction does not support indexing"));
10696 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10697 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10699 if (!(inst
.instruction
& INDEX_UP
))
10700 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10702 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10704 inst
.operands
[2].preind
= 0;
10705 inst
.operands
[2].postind
= 1;
10709 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10712 /* iWMMXt instructions: strictly in alphabetical order. */
10715 do_iwmmxt_tandorc (void)
10717 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10721 do_iwmmxt_textrc (void)
10723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10724 inst
.instruction
|= inst
.operands
[1].imm
;
10728 do_iwmmxt_textrm (void)
10730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10732 inst
.instruction
|= inst
.operands
[2].imm
;
10736 do_iwmmxt_tinsr (void)
10738 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10739 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10740 inst
.instruction
|= inst
.operands
[2].imm
;
10744 do_iwmmxt_tmia (void)
10746 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10747 inst
.instruction
|= inst
.operands
[1].reg
;
10748 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10752 do_iwmmxt_waligni (void)
10754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10755 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10756 inst
.instruction
|= inst
.operands
[2].reg
;
10757 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10761 do_iwmmxt_wmerge (void)
10763 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10764 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10765 inst
.instruction
|= inst
.operands
[2].reg
;
10766 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10770 do_iwmmxt_wmov (void)
10772 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10773 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10774 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10775 inst
.instruction
|= inst
.operands
[1].reg
;
10779 do_iwmmxt_wldstbh (void)
10782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10784 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10786 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10787 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10791 do_iwmmxt_wldstw (void)
10793 /* RIWR_RIWC clears .isreg for a control register. */
10794 if (!inst
.operands
[0].isreg
)
10796 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10797 inst
.instruction
|= 0xf0000000;
10800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10801 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10805 do_iwmmxt_wldstd (void)
10807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10808 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10809 && inst
.operands
[1].immisreg
)
10811 inst
.instruction
&= ~0x1a000ff;
10812 inst
.instruction
|= (0xfU
<< 28);
10813 if (inst
.operands
[1].preind
)
10814 inst
.instruction
|= PRE_INDEX
;
10815 if (!inst
.operands
[1].negative
)
10816 inst
.instruction
|= INDEX_UP
;
10817 if (inst
.operands
[1].writeback
)
10818 inst
.instruction
|= WRITE_BACK
;
10819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10820 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10821 inst
.instruction
|= inst
.operands
[1].imm
;
10824 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10828 do_iwmmxt_wshufh (void)
10830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10832 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10833 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10837 do_iwmmxt_wzero (void)
10839 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10840 inst
.instruction
|= inst
.operands
[0].reg
;
10841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10842 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10846 do_iwmmxt_wrwrwr_or_imm5 (void)
10848 if (inst
.operands
[2].isreg
)
10851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10852 _("immediate operand requires iWMMXt2"));
10854 if (inst
.operands
[2].imm
== 0)
10856 switch ((inst
.instruction
>> 20) & 0xf)
10862 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10863 inst
.operands
[2].imm
= 16;
10864 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10870 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10871 inst
.operands
[2].imm
= 32;
10872 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10879 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10881 wrn
= (inst
.instruction
>> 16) & 0xf;
10882 inst
.instruction
&= 0xff0fff0f;
10883 inst
.instruction
|= wrn
;
10884 /* Bail out here; the instruction is now assembled. */
10889 /* Map 32 -> 0, etc. */
10890 inst
.operands
[2].imm
&= 0x1f;
10891 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10895 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10896 operations first, then control, shift, and load/store. */
10898 /* Insns like "foo X,Y,Z". */
10901 do_mav_triple (void)
10903 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10904 inst
.instruction
|= inst
.operands
[1].reg
;
10905 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10908 /* Insns like "foo W,X,Y,Z".
10909 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10914 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10915 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10916 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10917 inst
.instruction
|= inst
.operands
[3].reg
;
10920 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10922 do_mav_dspsc (void)
10924 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10927 /* Maverick shift immediate instructions.
10928 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10929 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10932 do_mav_shift (void)
10934 int imm
= inst
.operands
[2].imm
;
10936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10939 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10940 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10941 Bit 4 should be 0. */
10942 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10944 inst
.instruction
|= imm
;
10947 /* XScale instructions. Also sorted arithmetic before move. */
10949 /* Xscale multiply-accumulate (argument parse)
10952 MIAxycc acc0,Rm,Rs. */
10957 inst
.instruction
|= inst
.operands
[1].reg
;
10958 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10961 /* Xscale move-accumulator-register (argument parse)
10963 MARcc acc0,RdLo,RdHi. */
10968 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10969 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10972 /* Xscale move-register-accumulator (argument parse)
10974 MRAcc RdLo,RdHi,acc0. */
10979 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10981 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10984 /* Encoding functions relevant only to Thumb. */
10986 /* inst.operands[i] is a shifted-register operand; encode
10987 it into inst.instruction in the format used by Thumb32. */
10990 encode_thumb32_shifted_operand (int i
)
10992 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10993 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10995 constraint (inst
.operands
[i
].immisreg
,
10996 _("shift by register not allowed in thumb mode"));
10997 inst
.instruction
|= inst
.operands
[i
].reg
;
10998 if (shift
== SHIFT_RRX
)
10999 inst
.instruction
|= SHIFT_ROR
<< 4;
11002 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11003 _("expression too complex"));
11005 constraint (value
> 32
11006 || (value
== 32 && (shift
== SHIFT_LSL
11007 || shift
== SHIFT_ROR
)),
11008 _("shift expression is too large"));
11012 else if (value
== 32)
11015 inst
.instruction
|= shift
<< 4;
11016 inst
.instruction
|= (value
& 0x1c) << 10;
11017 inst
.instruction
|= (value
& 0x03) << 6;
11022 /* inst.operands[i] was set up by parse_address. Encode it into a
11023 Thumb32 format load or store instruction. Reject forms that cannot
11024 be used with such instructions. If is_t is true, reject forms that
11025 cannot be used with a T instruction; if is_d is true, reject forms
11026 that cannot be used with a D instruction. If it is a store insn,
11027 reject PC in Rn. */
11030 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11032 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11034 constraint (!inst
.operands
[i
].isreg
,
11035 _("Instruction does not support =N addresses"));
11037 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11038 if (inst
.operands
[i
].immisreg
)
11040 constraint (is_pc
, BAD_PC_ADDRESSING
);
11041 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11042 constraint (inst
.operands
[i
].negative
,
11043 _("Thumb does not support negative register indexing"));
11044 constraint (inst
.operands
[i
].postind
,
11045 _("Thumb does not support register post-indexing"));
11046 constraint (inst
.operands
[i
].writeback
,
11047 _("Thumb does not support register indexing with writeback"));
11048 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11049 _("Thumb supports only LSL in shifted register indexing"));
11051 inst
.instruction
|= inst
.operands
[i
].imm
;
11052 if (inst
.operands
[i
].shifted
)
11054 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11055 _("expression too complex"));
11056 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11057 || inst
.relocs
[0].exp
.X_add_number
> 3,
11058 _("shift out of range"));
11059 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11061 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11063 else if (inst
.operands
[i
].preind
)
11065 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11066 constraint (is_t
&& inst
.operands
[i
].writeback
,
11067 _("cannot use writeback with this instruction"));
11068 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11069 BAD_PC_ADDRESSING
);
11073 inst
.instruction
|= 0x01000000;
11074 if (inst
.operands
[i
].writeback
)
11075 inst
.instruction
|= 0x00200000;
11079 inst
.instruction
|= 0x00000c00;
11080 if (inst
.operands
[i
].writeback
)
11081 inst
.instruction
|= 0x00000100;
11083 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11085 else if (inst
.operands
[i
].postind
)
11087 gas_assert (inst
.operands
[i
].writeback
);
11088 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11089 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11092 inst
.instruction
|= 0x00200000;
11094 inst
.instruction
|= 0x00000900;
11095 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11097 else /* unindexed - only for coprocessor */
11098 inst
.error
= _("instruction does not accept unindexed addressing");
11101 /* Table of Thumb instructions which exist in both 16- and 32-bit
11102 encodings (the latter only in post-V6T2 cores). The index is the
11103 value used in the insns table below. When there is more than one
11104 possible 16-bit encoding for the instruction, this table always
11106 Also contains several pseudo-instructions used during relaxation. */
11107 #define T16_32_TAB \
11108 X(_adc, 4140, eb400000), \
11109 X(_adcs, 4140, eb500000), \
11110 X(_add, 1c00, eb000000), \
11111 X(_adds, 1c00, eb100000), \
11112 X(_addi, 0000, f1000000), \
11113 X(_addis, 0000, f1100000), \
11114 X(_add_pc,000f, f20f0000), \
11115 X(_add_sp,000d, f10d0000), \
11116 X(_adr, 000f, f20f0000), \
11117 X(_and, 4000, ea000000), \
11118 X(_ands, 4000, ea100000), \
11119 X(_asr, 1000, fa40f000), \
11120 X(_asrs, 1000, fa50f000), \
11121 X(_b, e000, f000b000), \
11122 X(_bcond, d000, f0008000), \
11123 X(_bf, 0000, f040e001), \
11124 X(_bfcsel,0000, f000e001), \
11125 X(_bfx, 0000, f060e001), \
11126 X(_bfl, 0000, f000c001), \
11127 X(_bflx, 0000, f070e001), \
11128 X(_bic, 4380, ea200000), \
11129 X(_bics, 4380, ea300000), \
11130 X(_cmn, 42c0, eb100f00), \
11131 X(_cmp, 2800, ebb00f00), \
11132 X(_cpsie, b660, f3af8400), \
11133 X(_cpsid, b670, f3af8600), \
11134 X(_cpy, 4600, ea4f0000), \
11135 X(_dec_sp,80dd, f1ad0d00), \
11136 X(_dls, 0000, f040e001), \
11137 X(_dlstp, 0000, f000e001), \
11138 X(_eor, 4040, ea800000), \
11139 X(_eors, 4040, ea900000), \
11140 X(_inc_sp,00dd, f10d0d00), \
11141 X(_lctp, 0000, f00fe001), \
11142 X(_ldmia, c800, e8900000), \
11143 X(_ldr, 6800, f8500000), \
11144 X(_ldrb, 7800, f8100000), \
11145 X(_ldrh, 8800, f8300000), \
11146 X(_ldrsb, 5600, f9100000), \
11147 X(_ldrsh, 5e00, f9300000), \
11148 X(_ldr_pc,4800, f85f0000), \
11149 X(_ldr_pc2,4800, f85f0000), \
11150 X(_ldr_sp,9800, f85d0000), \
11151 X(_le, 0000, f00fc001), \
11152 X(_letp, 0000, f01fc001), \
11153 X(_lsl, 0000, fa00f000), \
11154 X(_lsls, 0000, fa10f000), \
11155 X(_lsr, 0800, fa20f000), \
11156 X(_lsrs, 0800, fa30f000), \
11157 X(_mov, 2000, ea4f0000), \
11158 X(_movs, 2000, ea5f0000), \
11159 X(_mul, 4340, fb00f000), \
11160 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11161 X(_mvn, 43c0, ea6f0000), \
11162 X(_mvns, 43c0, ea7f0000), \
11163 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11164 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11165 X(_orr, 4300, ea400000), \
11166 X(_orrs, 4300, ea500000), \
11167 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11168 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11169 X(_rev, ba00, fa90f080), \
11170 X(_rev16, ba40, fa90f090), \
11171 X(_revsh, bac0, fa90f0b0), \
11172 X(_ror, 41c0, fa60f000), \
11173 X(_rors, 41c0, fa70f000), \
11174 X(_sbc, 4180, eb600000), \
11175 X(_sbcs, 4180, eb700000), \
11176 X(_stmia, c000, e8800000), \
11177 X(_str, 6000, f8400000), \
11178 X(_strb, 7000, f8000000), \
11179 X(_strh, 8000, f8200000), \
11180 X(_str_sp,9000, f84d0000), \
11181 X(_sub, 1e00, eba00000), \
11182 X(_subs, 1e00, ebb00000), \
11183 X(_subi, 8000, f1a00000), \
11184 X(_subis, 8000, f1b00000), \
11185 X(_sxtb, b240, fa4ff080), \
11186 X(_sxth, b200, fa0ff080), \
11187 X(_tst, 4200, ea100f00), \
11188 X(_uxtb, b2c0, fa5ff080), \
11189 X(_uxth, b280, fa1ff080), \
11190 X(_nop, bf00, f3af8000), \
11191 X(_yield, bf10, f3af8001), \
11192 X(_wfe, bf20, f3af8002), \
11193 X(_wfi, bf30, f3af8003), \
11194 X(_wls, 0000, f040c001), \
11195 X(_wlstp, 0000, f000c001), \
11196 X(_sev, bf40, f3af8004), \
11197 X(_sevl, bf50, f3af8005), \
11198 X(_udf, de00, f7f0a000)
11200 /* To catch errors in encoding functions, the codes are all offset by
11201 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11202 as 16-bit instructions. */
11203 #define X(a,b,c) T_MNEM##a
11204 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11207 #define X(a,b,c) 0x##b
11208 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11209 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11212 #define X(a,b,c) 0x##c
11213 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11214 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11215 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11219 /* Thumb instruction encoders, in alphabetical order. */
11221 /* ADDW or SUBW. */
11224 do_t_add_sub_w (void)
11228 Rd
= inst
.operands
[0].reg
;
11229 Rn
= inst
.operands
[1].reg
;
11231 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11232 is the SP-{plus,minus}-immediate form of the instruction. */
11234 constraint (Rd
== REG_PC
, BAD_PC
);
11236 reject_bad_reg (Rd
);
11238 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11239 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11242 /* Parse an add or subtract instruction. We get here with inst.instruction
11243 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11246 do_t_add_sub (void)
11250 Rd
= inst
.operands
[0].reg
;
11251 Rs
= (inst
.operands
[1].present
11252 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11253 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11256 set_pred_insn_type_last ();
11258 if (unified_syntax
)
11261 bfd_boolean narrow
;
11264 flags
= (inst
.instruction
== T_MNEM_adds
11265 || inst
.instruction
== T_MNEM_subs
);
11267 narrow
= !in_pred_block ();
11269 narrow
= in_pred_block ();
11270 if (!inst
.operands
[2].isreg
)
11274 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11275 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11277 add
= (inst
.instruction
== T_MNEM_add
11278 || inst
.instruction
== T_MNEM_adds
);
11280 if (inst
.size_req
!= 4)
11282 /* Attempt to use a narrow opcode, with relaxation if
11284 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11285 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11286 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11287 opcode
= T_MNEM_add_sp
;
11288 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11289 opcode
= T_MNEM_add_pc
;
11290 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11293 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11295 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11299 inst
.instruction
= THUMB_OP16(opcode
);
11300 inst
.instruction
|= (Rd
<< 4) | Rs
;
11301 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11302 || (inst
.relocs
[0].type
11303 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11305 if (inst
.size_req
== 2)
11306 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11308 inst
.relax
= opcode
;
11312 constraint (inst
.size_req
== 2, BAD_HIREG
);
11314 if (inst
.size_req
== 4
11315 || (inst
.size_req
!= 2 && !opcode
))
11317 constraint ((inst
.relocs
[0].type
11318 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11319 && (inst
.relocs
[0].type
11320 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11321 THUMB1_RELOC_ONLY
);
11324 constraint (add
, BAD_PC
);
11325 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11326 _("only SUBS PC, LR, #const allowed"));
11327 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11328 _("expression too complex"));
11329 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11330 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11331 _("immediate value out of range"));
11332 inst
.instruction
= T2_SUBS_PC_LR
11333 | inst
.relocs
[0].exp
.X_add_number
;
11334 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11337 else if (Rs
== REG_PC
)
11339 /* Always use addw/subw. */
11340 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11341 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11345 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11346 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11349 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11351 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11353 inst
.instruction
|= Rd
<< 8;
11354 inst
.instruction
|= Rs
<< 16;
11359 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11360 unsigned int shift
= inst
.operands
[2].shift_kind
;
11362 Rn
= inst
.operands
[2].reg
;
11363 /* See if we can do this with a 16-bit instruction. */
11364 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11366 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11371 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11372 || inst
.instruction
== T_MNEM_add
)
11374 : T_OPCODE_SUB_R3
);
11375 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11379 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11381 /* Thumb-1 cores (except v6-M) require at least one high
11382 register in a narrow non flag setting add. */
11383 if (Rd
> 7 || Rn
> 7
11384 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11385 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11392 inst
.instruction
= T_OPCODE_ADD_HI
;
11393 inst
.instruction
|= (Rd
& 8) << 4;
11394 inst
.instruction
|= (Rd
& 7);
11395 inst
.instruction
|= Rn
<< 3;
11401 constraint (Rd
== REG_PC
, BAD_PC
);
11402 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11403 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11404 constraint (Rs
== REG_PC
, BAD_PC
);
11405 reject_bad_reg (Rn
);
11407 /* If we get here, it can't be done in 16 bits. */
11408 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11409 _("shift must be constant"));
11410 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11411 inst
.instruction
|= Rd
<< 8;
11412 inst
.instruction
|= Rs
<< 16;
11413 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11414 _("shift value over 3 not allowed in thumb mode"));
11415 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11416 _("only LSL shift allowed in thumb mode"));
11417 encode_thumb32_shifted_operand (2);
11422 constraint (inst
.instruction
== T_MNEM_adds
11423 || inst
.instruction
== T_MNEM_subs
,
11426 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11428 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11429 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11432 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11433 ? 0x0000 : 0x8000);
11434 inst
.instruction
|= (Rd
<< 4) | Rs
;
11435 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11439 Rn
= inst
.operands
[2].reg
;
11440 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11442 /* We now have Rd, Rs, and Rn set to registers. */
11443 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11445 /* Can't do this for SUB. */
11446 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11447 inst
.instruction
= T_OPCODE_ADD_HI
;
11448 inst
.instruction
|= (Rd
& 8) << 4;
11449 inst
.instruction
|= (Rd
& 7);
11451 inst
.instruction
|= Rn
<< 3;
11453 inst
.instruction
|= Rs
<< 3;
11455 constraint (1, _("dest must overlap one source register"));
11459 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11460 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11461 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11471 Rd
= inst
.operands
[0].reg
;
11472 reject_bad_reg (Rd
);
11474 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11476 /* Defer to section relaxation. */
11477 inst
.relax
= inst
.instruction
;
11478 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11479 inst
.instruction
|= Rd
<< 4;
11481 else if (unified_syntax
&& inst
.size_req
!= 2)
11483 /* Generate a 32-bit opcode. */
11484 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11485 inst
.instruction
|= Rd
<< 8;
11486 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11487 inst
.relocs
[0].pc_rel
= 1;
11491 /* Generate a 16-bit opcode. */
11492 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11493 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11494 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11495 inst
.relocs
[0].pc_rel
= 1;
11496 inst
.instruction
|= Rd
<< 4;
11499 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11500 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11501 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11502 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11503 inst
.relocs
[0].exp
.X_add_number
+= 1;
11506 /* Arithmetic instructions for which there is just one 16-bit
11507 instruction encoding, and it allows only two low registers.
11508 For maximal compatibility with ARM syntax, we allow three register
11509 operands even when Thumb-32 instructions are not available, as long
11510 as the first two are identical. For instance, both "sbc r0,r1" and
11511 "sbc r0,r0,r1" are allowed. */
11517 Rd
= inst
.operands
[0].reg
;
11518 Rs
= (inst
.operands
[1].present
11519 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11520 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11521 Rn
= inst
.operands
[2].reg
;
11523 reject_bad_reg (Rd
);
11524 reject_bad_reg (Rs
);
11525 if (inst
.operands
[2].isreg
)
11526 reject_bad_reg (Rn
);
11528 if (unified_syntax
)
11530 if (!inst
.operands
[2].isreg
)
11532 /* For an immediate, we always generate a 32-bit opcode;
11533 section relaxation will shrink it later if possible. */
11534 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11535 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11536 inst
.instruction
|= Rd
<< 8;
11537 inst
.instruction
|= Rs
<< 16;
11538 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11542 bfd_boolean narrow
;
11544 /* See if we can do this with a 16-bit instruction. */
11545 if (THUMB_SETS_FLAGS (inst
.instruction
))
11546 narrow
= !in_pred_block ();
11548 narrow
= in_pred_block ();
11550 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11552 if (inst
.operands
[2].shifted
)
11554 if (inst
.size_req
== 4)
11560 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11561 inst
.instruction
|= Rd
;
11562 inst
.instruction
|= Rn
<< 3;
11566 /* If we get here, it can't be done in 16 bits. */
11567 constraint (inst
.operands
[2].shifted
11568 && inst
.operands
[2].immisreg
,
11569 _("shift must be constant"));
11570 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11571 inst
.instruction
|= Rd
<< 8;
11572 inst
.instruction
|= Rs
<< 16;
11573 encode_thumb32_shifted_operand (2);
11578 /* On its face this is a lie - the instruction does set the
11579 flags. However, the only supported mnemonic in this mode
11580 says it doesn't. */
11581 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11583 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11584 _("unshifted register required"));
11585 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11586 constraint (Rd
!= Rs
,
11587 _("dest and source1 must be the same register"));
11589 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11590 inst
.instruction
|= Rd
;
11591 inst
.instruction
|= Rn
<< 3;
11595 /* Similarly, but for instructions where the arithmetic operation is
11596 commutative, so we can allow either of them to be different from
11597 the destination operand in a 16-bit instruction. For instance, all
11598 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11605 Rd
= inst
.operands
[0].reg
;
11606 Rs
= (inst
.operands
[1].present
11607 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11608 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11609 Rn
= inst
.operands
[2].reg
;
11611 reject_bad_reg (Rd
);
11612 reject_bad_reg (Rs
);
11613 if (inst
.operands
[2].isreg
)
11614 reject_bad_reg (Rn
);
11616 if (unified_syntax
)
11618 if (!inst
.operands
[2].isreg
)
11620 /* For an immediate, we always generate a 32-bit opcode;
11621 section relaxation will shrink it later if possible. */
11622 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11623 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11624 inst
.instruction
|= Rd
<< 8;
11625 inst
.instruction
|= Rs
<< 16;
11626 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11630 bfd_boolean narrow
;
11632 /* See if we can do this with a 16-bit instruction. */
11633 if (THUMB_SETS_FLAGS (inst
.instruction
))
11634 narrow
= !in_pred_block ();
11636 narrow
= in_pred_block ();
11638 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11640 if (inst
.operands
[2].shifted
)
11642 if (inst
.size_req
== 4)
11649 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11650 inst
.instruction
|= Rd
;
11651 inst
.instruction
|= Rn
<< 3;
11656 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11657 inst
.instruction
|= Rd
;
11658 inst
.instruction
|= Rs
<< 3;
11663 /* If we get here, it can't be done in 16 bits. */
11664 constraint (inst
.operands
[2].shifted
11665 && inst
.operands
[2].immisreg
,
11666 _("shift must be constant"));
11667 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11668 inst
.instruction
|= Rd
<< 8;
11669 inst
.instruction
|= Rs
<< 16;
11670 encode_thumb32_shifted_operand (2);
11675 /* On its face this is a lie - the instruction does set the
11676 flags. However, the only supported mnemonic in this mode
11677 says it doesn't. */
11678 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11680 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11681 _("unshifted register required"));
11682 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11684 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11685 inst
.instruction
|= Rd
;
11688 inst
.instruction
|= Rn
<< 3;
11690 inst
.instruction
|= Rs
<< 3;
11692 constraint (1, _("dest must overlap one source register"));
11700 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11701 constraint (msb
> 32, _("bit-field extends past end of register"));
11702 /* The instruction encoding stores the LSB and MSB,
11703 not the LSB and width. */
11704 Rd
= inst
.operands
[0].reg
;
11705 reject_bad_reg (Rd
);
11706 inst
.instruction
|= Rd
<< 8;
11707 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11708 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11709 inst
.instruction
|= msb
- 1;
11718 Rd
= inst
.operands
[0].reg
;
11719 reject_bad_reg (Rd
);
11721 /* #0 in second position is alternative syntax for bfc, which is
11722 the same instruction but with REG_PC in the Rm field. */
11723 if (!inst
.operands
[1].isreg
)
11727 Rn
= inst
.operands
[1].reg
;
11728 reject_bad_reg (Rn
);
11731 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11732 constraint (msb
> 32, _("bit-field extends past end of register"));
11733 /* The instruction encoding stores the LSB and MSB,
11734 not the LSB and width. */
11735 inst
.instruction
|= Rd
<< 8;
11736 inst
.instruction
|= Rn
<< 16;
11737 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11738 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11739 inst
.instruction
|= msb
- 1;
11747 Rd
= inst
.operands
[0].reg
;
11748 Rn
= inst
.operands
[1].reg
;
11750 reject_bad_reg (Rd
);
11751 reject_bad_reg (Rn
);
11753 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11754 _("bit-field extends past end of register"));
11755 inst
.instruction
|= Rd
<< 8;
11756 inst
.instruction
|= Rn
<< 16;
11757 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11758 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11759 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11762 /* ARM V5 Thumb BLX (argument parse)
11763 BLX <target_addr> which is BLX(1)
11764 BLX <Rm> which is BLX(2)
11765 Unfortunately, there are two different opcodes for this mnemonic.
11766 So, the insns[].value is not used, and the code here zaps values
11767 into inst.instruction.
11769 ??? How to take advantage of the additional two bits of displacement
11770 available in Thumb32 mode? Need new relocation? */
11775 set_pred_insn_type_last ();
11777 if (inst
.operands
[0].isreg
)
11779 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11780 /* We have a register, so this is BLX(2). */
11781 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11785 /* No register. This must be BLX(1). */
11786 inst
.instruction
= 0xf000e800;
11787 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11796 bfd_reloc_code_real_type reloc
;
11799 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11801 if (in_pred_block ())
11803 /* Conditional branches inside IT blocks are encoded as unconditional
11805 cond
= COND_ALWAYS
;
11810 if (cond
!= COND_ALWAYS
)
11811 opcode
= T_MNEM_bcond
;
11813 opcode
= inst
.instruction
;
11816 && (inst
.size_req
== 4
11817 || (inst
.size_req
!= 2
11818 && (inst
.operands
[0].hasreloc
11819 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11821 inst
.instruction
= THUMB_OP32(opcode
);
11822 if (cond
== COND_ALWAYS
)
11823 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11826 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11827 _("selected architecture does not support "
11828 "wide conditional branch instruction"));
11830 gas_assert (cond
!= 0xF);
11831 inst
.instruction
|= cond
<< 22;
11832 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11837 inst
.instruction
= THUMB_OP16(opcode
);
11838 if (cond
== COND_ALWAYS
)
11839 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11842 inst
.instruction
|= cond
<< 8;
11843 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11845 /* Allow section relaxation. */
11846 if (unified_syntax
&& inst
.size_req
!= 2)
11847 inst
.relax
= opcode
;
11849 inst
.relocs
[0].type
= reloc
;
11850 inst
.relocs
[0].pc_rel
= 1;
11853 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11854 between the two is the maximum immediate allowed - which is passed in
11857 do_t_bkpt_hlt1 (int range
)
11859 constraint (inst
.cond
!= COND_ALWAYS
,
11860 _("instruction is always unconditional"));
11861 if (inst
.operands
[0].present
)
11863 constraint (inst
.operands
[0].imm
> range
,
11864 _("immediate value out of range"));
11865 inst
.instruction
|= inst
.operands
[0].imm
;
11868 set_pred_insn_type (NEUTRAL_IT_INSN
);
11874 do_t_bkpt_hlt1 (63);
11880 do_t_bkpt_hlt1 (255);
11884 do_t_branch23 (void)
11886 set_pred_insn_type_last ();
11887 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11889 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11890 this file. We used to simply ignore the PLT reloc type here --
11891 the branch encoding is now needed to deal with TLSCALL relocs.
11892 So if we see a PLT reloc now, put it back to how it used to be to
11893 keep the preexisting behaviour. */
11894 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11895 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11897 #if defined(OBJ_COFF)
11898 /* If the destination of the branch is a defined symbol which does not have
11899 the THUMB_FUNC attribute, then we must be calling a function which has
11900 the (interfacearm) attribute. We look for the Thumb entry point to that
11901 function and change the branch to refer to that function instead. */
11902 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11903 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11904 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11905 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11906 inst
.relocs
[0].exp
.X_add_symbol
11907 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11914 set_pred_insn_type_last ();
11915 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11916 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11917 should cause the alignment to be checked once it is known. This is
11918 because BX PC only works if the instruction is word aligned. */
11926 set_pred_insn_type_last ();
11927 Rm
= inst
.operands
[0].reg
;
11928 reject_bad_reg (Rm
);
11929 inst
.instruction
|= Rm
<< 16;
11938 Rd
= inst
.operands
[0].reg
;
11939 Rm
= inst
.operands
[1].reg
;
11941 reject_bad_reg (Rd
);
11942 reject_bad_reg (Rm
);
11944 inst
.instruction
|= Rd
<< 8;
11945 inst
.instruction
|= Rm
<< 16;
11946 inst
.instruction
|= Rm
;
11952 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11958 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11959 inst
.instruction
|= inst
.operands
[0].imm
;
11965 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11967 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11968 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11970 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11971 inst
.instruction
= 0xf3af8000;
11972 inst
.instruction
|= imod
<< 9;
11973 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11974 if (inst
.operands
[1].present
)
11975 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11979 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11980 && (inst
.operands
[0].imm
& 4),
11981 _("selected processor does not support 'A' form "
11982 "of this instruction"));
11983 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11984 _("Thumb does not support the 2-argument "
11985 "form of this instruction"));
11986 inst
.instruction
|= inst
.operands
[0].imm
;
11990 /* THUMB CPY instruction (argument parse). */
11995 if (inst
.size_req
== 4)
11997 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11998 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11999 inst
.instruction
|= inst
.operands
[1].reg
;
12003 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12004 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12005 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12012 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12013 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12014 inst
.instruction
|= inst
.operands
[0].reg
;
12015 inst
.relocs
[0].pc_rel
= 1;
12016 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12022 inst
.instruction
|= inst
.operands
[0].imm
;
12028 unsigned Rd
, Rn
, Rm
;
12030 Rd
= inst
.operands
[0].reg
;
12031 Rn
= (inst
.operands
[1].present
12032 ? inst
.operands
[1].reg
: Rd
);
12033 Rm
= inst
.operands
[2].reg
;
12035 reject_bad_reg (Rd
);
12036 reject_bad_reg (Rn
);
12037 reject_bad_reg (Rm
);
12039 inst
.instruction
|= Rd
<< 8;
12040 inst
.instruction
|= Rn
<< 16;
12041 inst
.instruction
|= Rm
;
12047 if (unified_syntax
&& inst
.size_req
== 4)
12048 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12050 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12056 unsigned int cond
= inst
.operands
[0].imm
;
12058 set_pred_insn_type (IT_INSN
);
12059 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12060 now_pred
.cc
= cond
;
12061 now_pred
.warn_deprecated
= FALSE
;
12062 now_pred
.type
= SCALAR_PRED
;
12064 /* If the condition is a negative condition, invert the mask. */
12065 if ((cond
& 0x1) == 0x0)
12067 unsigned int mask
= inst
.instruction
& 0x000f;
12069 if ((mask
& 0x7) == 0)
12071 /* No conversion needed. */
12072 now_pred
.block_length
= 1;
12074 else if ((mask
& 0x3) == 0)
12077 now_pred
.block_length
= 2;
12079 else if ((mask
& 0x1) == 0)
12082 now_pred
.block_length
= 3;
12087 now_pred
.block_length
= 4;
12090 inst
.instruction
&= 0xfff0;
12091 inst
.instruction
|= mask
;
12094 inst
.instruction
|= cond
<< 4;
12097 /* Helper function used for both push/pop and ldm/stm. */
12099 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12100 bfd_boolean writeback
)
12102 bfd_boolean load
, store
;
12104 gas_assert (base
!= -1 || !do_io
);
12105 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12106 store
= do_io
&& !load
;
12108 if (mask
& (1 << 13))
12109 inst
.error
= _("SP not allowed in register list");
12111 if (do_io
&& (mask
& (1 << base
)) != 0
12113 inst
.error
= _("having the base register in the register list when "
12114 "using write back is UNPREDICTABLE");
12118 if (mask
& (1 << 15))
12120 if (mask
& (1 << 14))
12121 inst
.error
= _("LR and PC should not both be in register list");
12123 set_pred_insn_type_last ();
12128 if (mask
& (1 << 15))
12129 inst
.error
= _("PC not allowed in register list");
12132 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12134 /* Single register transfers implemented as str/ldr. */
12137 if (inst
.instruction
& (1 << 23))
12138 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12140 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12144 if (inst
.instruction
& (1 << 23))
12145 inst
.instruction
= 0x00800000; /* ia -> [base] */
12147 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12150 inst
.instruction
|= 0xf8400000;
12152 inst
.instruction
|= 0x00100000;
12154 mask
= ffs (mask
) - 1;
12157 else if (writeback
)
12158 inst
.instruction
|= WRITE_BACK
;
12160 inst
.instruction
|= mask
;
12162 inst
.instruction
|= base
<< 16;
12168 /* This really doesn't seem worth it. */
12169 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12170 _("expression too complex"));
12171 constraint (inst
.operands
[1].writeback
,
12172 _("Thumb load/store multiple does not support {reglist}^"));
12174 if (unified_syntax
)
12176 bfd_boolean narrow
;
12180 /* See if we can use a 16-bit instruction. */
12181 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12182 && inst
.size_req
!= 4
12183 && !(inst
.operands
[1].imm
& ~0xff))
12185 mask
= 1 << inst
.operands
[0].reg
;
12187 if (inst
.operands
[0].reg
<= 7)
12189 if (inst
.instruction
== T_MNEM_stmia
12190 ? inst
.operands
[0].writeback
12191 : (inst
.operands
[0].writeback
12192 == !(inst
.operands
[1].imm
& mask
)))
12194 if (inst
.instruction
== T_MNEM_stmia
12195 && (inst
.operands
[1].imm
& mask
)
12196 && (inst
.operands
[1].imm
& (mask
- 1)))
12197 as_warn (_("value stored for r%d is UNKNOWN"),
12198 inst
.operands
[0].reg
);
12200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12201 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12202 inst
.instruction
|= inst
.operands
[1].imm
;
12205 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12207 /* This means 1 register in reg list one of 3 situations:
12208 1. Instruction is stmia, but without writeback.
12209 2. lmdia without writeback, but with Rn not in
12211 3. ldmia with writeback, but with Rn in reglist.
12212 Case 3 is UNPREDICTABLE behaviour, so we handle
12213 case 1 and 2 which can be converted into a 16-bit
12214 str or ldr. The SP cases are handled below. */
12215 unsigned long opcode
;
12216 /* First, record an error for Case 3. */
12217 if (inst
.operands
[1].imm
& mask
12218 && inst
.operands
[0].writeback
)
12220 _("having the base register in the register list when "
12221 "using write back is UNPREDICTABLE");
12223 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12225 inst
.instruction
= THUMB_OP16 (opcode
);
12226 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12227 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12231 else if (inst
.operands
[0] .reg
== REG_SP
)
12233 if (inst
.operands
[0].writeback
)
12236 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12237 ? T_MNEM_push
: T_MNEM_pop
);
12238 inst
.instruction
|= inst
.operands
[1].imm
;
12241 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12244 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12245 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12246 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12254 if (inst
.instruction
< 0xffff)
12255 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12257 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12258 inst
.operands
[1].imm
,
12259 inst
.operands
[0].writeback
);
12264 constraint (inst
.operands
[0].reg
> 7
12265 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12266 constraint (inst
.instruction
!= T_MNEM_ldmia
12267 && inst
.instruction
!= T_MNEM_stmia
,
12268 _("Thumb-2 instruction only valid in unified syntax"));
12269 if (inst
.instruction
== T_MNEM_stmia
)
12271 if (!inst
.operands
[0].writeback
)
12272 as_warn (_("this instruction will write back the base register"));
12273 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12274 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12275 as_warn (_("value stored for r%d is UNKNOWN"),
12276 inst
.operands
[0].reg
);
12280 if (!inst
.operands
[0].writeback
12281 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12282 as_warn (_("this instruction will write back the base register"));
12283 else if (inst
.operands
[0].writeback
12284 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12285 as_warn (_("this instruction will not write back the base register"));
12288 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12289 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12290 inst
.instruction
|= inst
.operands
[1].imm
;
12297 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12298 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12299 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12300 || inst
.operands
[1].negative
,
12303 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12307 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12313 if (!inst
.operands
[1].present
)
12315 constraint (inst
.operands
[0].reg
== REG_LR
,
12316 _("r14 not allowed as first register "
12317 "when second register is omitted"));
12318 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12320 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12323 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12324 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12325 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12331 unsigned long opcode
;
12334 if (inst
.operands
[0].isreg
12335 && !inst
.operands
[0].preind
12336 && inst
.operands
[0].reg
== REG_PC
)
12337 set_pred_insn_type_last ();
12339 opcode
= inst
.instruction
;
12340 if (unified_syntax
)
12342 if (!inst
.operands
[1].isreg
)
12344 if (opcode
<= 0xffff)
12345 inst
.instruction
= THUMB_OP32 (opcode
);
12346 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12349 if (inst
.operands
[1].isreg
12350 && !inst
.operands
[1].writeback
12351 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12352 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12353 && opcode
<= 0xffff
12354 && inst
.size_req
!= 4)
12356 /* Insn may have a 16-bit form. */
12357 Rn
= inst
.operands
[1].reg
;
12358 if (inst
.operands
[1].immisreg
)
12360 inst
.instruction
= THUMB_OP16 (opcode
);
12362 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12364 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12365 reject_bad_reg (inst
.operands
[1].imm
);
12367 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12368 && opcode
!= T_MNEM_ldrsb
)
12369 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12370 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12377 if (inst
.relocs
[0].pc_rel
)
12378 opcode
= T_MNEM_ldr_pc2
;
12380 opcode
= T_MNEM_ldr_pc
;
12384 if (opcode
== T_MNEM_ldr
)
12385 opcode
= T_MNEM_ldr_sp
;
12387 opcode
= T_MNEM_str_sp
;
12389 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12393 inst
.instruction
= inst
.operands
[0].reg
;
12394 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12396 inst
.instruction
|= THUMB_OP16 (opcode
);
12397 if (inst
.size_req
== 2)
12398 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12400 inst
.relax
= opcode
;
12404 /* Definitely a 32-bit variant. */
12406 /* Warning for Erratum 752419. */
12407 if (opcode
== T_MNEM_ldr
12408 && inst
.operands
[0].reg
== REG_SP
12409 && inst
.operands
[1].writeback
== 1
12410 && !inst
.operands
[1].immisreg
)
12412 if (no_cpu_selected ()
12413 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12414 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12415 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12416 as_warn (_("This instruction may be unpredictable "
12417 "if executed on M-profile cores "
12418 "with interrupts enabled."));
12421 /* Do some validations regarding addressing modes. */
12422 if (inst
.operands
[1].immisreg
)
12423 reject_bad_reg (inst
.operands
[1].imm
);
12425 constraint (inst
.operands
[1].writeback
== 1
12426 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12429 inst
.instruction
= THUMB_OP32 (opcode
);
12430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12431 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12432 check_ldr_r15_aligned ();
12436 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12438 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12440 /* Only [Rn,Rm] is acceptable. */
12441 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12442 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12443 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12444 || inst
.operands
[1].negative
,
12445 _("Thumb does not support this addressing mode"));
12446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12450 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12451 if (!inst
.operands
[1].isreg
)
12452 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12455 constraint (!inst
.operands
[1].preind
12456 || inst
.operands
[1].shifted
12457 || inst
.operands
[1].writeback
,
12458 _("Thumb does not support this addressing mode"));
12459 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12461 constraint (inst
.instruction
& 0x0600,
12462 _("byte or halfword not valid for base register"));
12463 constraint (inst
.operands
[1].reg
== REG_PC
12464 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12465 _("r15 based store not allowed"));
12466 constraint (inst
.operands
[1].immisreg
,
12467 _("invalid base register for register offset"));
12469 if (inst
.operands
[1].reg
== REG_PC
)
12470 inst
.instruction
= T_OPCODE_LDR_PC
;
12471 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12472 inst
.instruction
= T_OPCODE_LDR_SP
;
12474 inst
.instruction
= T_OPCODE_STR_SP
;
12476 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12477 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12481 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12482 if (!inst
.operands
[1].immisreg
)
12484 /* Immediate offset. */
12485 inst
.instruction
|= inst
.operands
[0].reg
;
12486 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12487 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12491 /* Register offset. */
12492 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12493 constraint (inst
.operands
[1].negative
,
12494 _("Thumb does not support this addressing mode"));
12497 switch (inst
.instruction
)
12499 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12500 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12501 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12502 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12503 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12504 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12505 case 0x5600 /* ldrsb */:
12506 case 0x5e00 /* ldrsh */: break;
12510 inst
.instruction
|= inst
.operands
[0].reg
;
12511 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12512 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12518 if (!inst
.operands
[1].present
)
12520 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12521 constraint (inst
.operands
[0].reg
== REG_LR
,
12522 _("r14 not allowed here"));
12523 constraint (inst
.operands
[0].reg
== REG_R12
,
12524 _("r12 not allowed here"));
12527 if (inst
.operands
[2].writeback
12528 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12529 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12530 as_warn (_("base register written back, and overlaps "
12531 "one of transfer registers"));
12533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12534 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12535 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12542 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12548 unsigned Rd
, Rn
, Rm
, Ra
;
12550 Rd
= inst
.operands
[0].reg
;
12551 Rn
= inst
.operands
[1].reg
;
12552 Rm
= inst
.operands
[2].reg
;
12553 Ra
= inst
.operands
[3].reg
;
12555 reject_bad_reg (Rd
);
12556 reject_bad_reg (Rn
);
12557 reject_bad_reg (Rm
);
12558 reject_bad_reg (Ra
);
12560 inst
.instruction
|= Rd
<< 8;
12561 inst
.instruction
|= Rn
<< 16;
12562 inst
.instruction
|= Rm
;
12563 inst
.instruction
|= Ra
<< 12;
12569 unsigned RdLo
, RdHi
, Rn
, Rm
;
12571 RdLo
= inst
.operands
[0].reg
;
12572 RdHi
= inst
.operands
[1].reg
;
12573 Rn
= inst
.operands
[2].reg
;
12574 Rm
= inst
.operands
[3].reg
;
12576 reject_bad_reg (RdLo
);
12577 reject_bad_reg (RdHi
);
12578 reject_bad_reg (Rn
);
12579 reject_bad_reg (Rm
);
12581 inst
.instruction
|= RdLo
<< 12;
12582 inst
.instruction
|= RdHi
<< 8;
12583 inst
.instruction
|= Rn
<< 16;
12584 inst
.instruction
|= Rm
;
12588 do_t_mov_cmp (void)
12592 Rn
= inst
.operands
[0].reg
;
12593 Rm
= inst
.operands
[1].reg
;
12596 set_pred_insn_type_last ();
12598 if (unified_syntax
)
12600 int r0off
= (inst
.instruction
== T_MNEM_mov
12601 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12602 unsigned long opcode
;
12603 bfd_boolean narrow
;
12604 bfd_boolean low_regs
;
12606 low_regs
= (Rn
<= 7 && Rm
<= 7);
12607 opcode
= inst
.instruction
;
12608 if (in_pred_block ())
12609 narrow
= opcode
!= T_MNEM_movs
;
12611 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12612 if (inst
.size_req
== 4
12613 || inst
.operands
[1].shifted
)
12616 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12617 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12618 && !inst
.operands
[1].shifted
12622 inst
.instruction
= T2_SUBS_PC_LR
;
12626 if (opcode
== T_MNEM_cmp
)
12628 constraint (Rn
== REG_PC
, BAD_PC
);
12631 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12633 warn_deprecated_sp (Rm
);
12634 /* R15 was documented as a valid choice for Rm in ARMv6,
12635 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12636 tools reject R15, so we do too. */
12637 constraint (Rm
== REG_PC
, BAD_PC
);
12640 reject_bad_reg (Rm
);
12642 else if (opcode
== T_MNEM_mov
12643 || opcode
== T_MNEM_movs
)
12645 if (inst
.operands
[1].isreg
)
12647 if (opcode
== T_MNEM_movs
)
12649 reject_bad_reg (Rn
);
12650 reject_bad_reg (Rm
);
12654 /* This is mov.n. */
12655 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12656 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12658 as_tsktsk (_("Use of r%u as a source register is "
12659 "deprecated when r%u is the destination "
12660 "register."), Rm
, Rn
);
12665 /* This is mov.w. */
12666 constraint (Rn
== REG_PC
, BAD_PC
);
12667 constraint (Rm
== REG_PC
, BAD_PC
);
12668 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12669 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12673 reject_bad_reg (Rn
);
12676 if (!inst
.operands
[1].isreg
)
12678 /* Immediate operand. */
12679 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12681 if (low_regs
&& narrow
)
12683 inst
.instruction
= THUMB_OP16 (opcode
);
12684 inst
.instruction
|= Rn
<< 8;
12685 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12686 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12688 if (inst
.size_req
== 2)
12689 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12691 inst
.relax
= opcode
;
12696 constraint ((inst
.relocs
[0].type
12697 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12698 && (inst
.relocs
[0].type
12699 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12700 THUMB1_RELOC_ONLY
);
12702 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12703 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12704 inst
.instruction
|= Rn
<< r0off
;
12705 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12708 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12709 && (inst
.instruction
== T_MNEM_mov
12710 || inst
.instruction
== T_MNEM_movs
))
12712 /* Register shifts are encoded as separate shift instructions. */
12713 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12715 if (in_pred_block ())
12720 if (inst
.size_req
== 4)
12723 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12729 switch (inst
.operands
[1].shift_kind
)
12732 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12735 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12738 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12741 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12747 inst
.instruction
= opcode
;
12750 inst
.instruction
|= Rn
;
12751 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12756 inst
.instruction
|= CONDS_BIT
;
12758 inst
.instruction
|= Rn
<< 8;
12759 inst
.instruction
|= Rm
<< 16;
12760 inst
.instruction
|= inst
.operands
[1].imm
;
12765 /* Some mov with immediate shift have narrow variants.
12766 Register shifts are handled above. */
12767 if (low_regs
&& inst
.operands
[1].shifted
12768 && (inst
.instruction
== T_MNEM_mov
12769 || inst
.instruction
== T_MNEM_movs
))
12771 if (in_pred_block ())
12772 narrow
= (inst
.instruction
== T_MNEM_mov
);
12774 narrow
= (inst
.instruction
== T_MNEM_movs
);
12779 switch (inst
.operands
[1].shift_kind
)
12781 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12782 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12783 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12784 default: narrow
= FALSE
; break;
12790 inst
.instruction
|= Rn
;
12791 inst
.instruction
|= Rm
<< 3;
12792 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12796 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12797 inst
.instruction
|= Rn
<< r0off
;
12798 encode_thumb32_shifted_operand (1);
12802 switch (inst
.instruction
)
12805 /* In v4t or v5t a move of two lowregs produces unpredictable
12806 results. Don't allow this. */
12809 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12810 "MOV Rd, Rs with two low registers is not "
12811 "permitted on this architecture");
12812 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12816 inst
.instruction
= T_OPCODE_MOV_HR
;
12817 inst
.instruction
|= (Rn
& 0x8) << 4;
12818 inst
.instruction
|= (Rn
& 0x7);
12819 inst
.instruction
|= Rm
<< 3;
12823 /* We know we have low registers at this point.
12824 Generate LSLS Rd, Rs, #0. */
12825 inst
.instruction
= T_OPCODE_LSL_I
;
12826 inst
.instruction
|= Rn
;
12827 inst
.instruction
|= Rm
<< 3;
12833 inst
.instruction
= T_OPCODE_CMP_LR
;
12834 inst
.instruction
|= Rn
;
12835 inst
.instruction
|= Rm
<< 3;
12839 inst
.instruction
= T_OPCODE_CMP_HR
;
12840 inst
.instruction
|= (Rn
& 0x8) << 4;
12841 inst
.instruction
|= (Rn
& 0x7);
12842 inst
.instruction
|= Rm
<< 3;
12849 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12851 /* PR 10443: Do not silently ignore shifted operands. */
12852 constraint (inst
.operands
[1].shifted
,
12853 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12855 if (inst
.operands
[1].isreg
)
12857 if (Rn
< 8 && Rm
< 8)
12859 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12860 since a MOV instruction produces unpredictable results. */
12861 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12862 inst
.instruction
= T_OPCODE_ADD_I3
;
12864 inst
.instruction
= T_OPCODE_CMP_LR
;
12866 inst
.instruction
|= Rn
;
12867 inst
.instruction
|= Rm
<< 3;
12871 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12872 inst
.instruction
= T_OPCODE_MOV_HR
;
12874 inst
.instruction
= T_OPCODE_CMP_HR
;
12880 constraint (Rn
> 7,
12881 _("only lo regs allowed with immediate"));
12882 inst
.instruction
|= Rn
<< 8;
12883 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12894 top
= (inst
.instruction
& 0x00800000) != 0;
12895 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12897 constraint (top
, _(":lower16: not allowed in this instruction"));
12898 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12900 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12902 constraint (!top
, _(":upper16: not allowed in this instruction"));
12903 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12906 Rd
= inst
.operands
[0].reg
;
12907 reject_bad_reg (Rd
);
12909 inst
.instruction
|= Rd
<< 8;
12910 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12912 imm
= inst
.relocs
[0].exp
.X_add_number
;
12913 inst
.instruction
|= (imm
& 0xf000) << 4;
12914 inst
.instruction
|= (imm
& 0x0800) << 15;
12915 inst
.instruction
|= (imm
& 0x0700) << 4;
12916 inst
.instruction
|= (imm
& 0x00ff);
12921 do_t_mvn_tst (void)
12925 Rn
= inst
.operands
[0].reg
;
12926 Rm
= inst
.operands
[1].reg
;
12928 if (inst
.instruction
== T_MNEM_cmp
12929 || inst
.instruction
== T_MNEM_cmn
)
12930 constraint (Rn
== REG_PC
, BAD_PC
);
12932 reject_bad_reg (Rn
);
12933 reject_bad_reg (Rm
);
12935 if (unified_syntax
)
12937 int r0off
= (inst
.instruction
== T_MNEM_mvn
12938 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12939 bfd_boolean narrow
;
12941 if (inst
.size_req
== 4
12942 || inst
.instruction
> 0xffff
12943 || inst
.operands
[1].shifted
12944 || Rn
> 7 || Rm
> 7)
12946 else if (inst
.instruction
== T_MNEM_cmn
12947 || inst
.instruction
== T_MNEM_tst
)
12949 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12950 narrow
= !in_pred_block ();
12952 narrow
= in_pred_block ();
12954 if (!inst
.operands
[1].isreg
)
12956 /* For an immediate, we always generate a 32-bit opcode;
12957 section relaxation will shrink it later if possible. */
12958 if (inst
.instruction
< 0xffff)
12959 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12960 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12961 inst
.instruction
|= Rn
<< r0off
;
12962 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12966 /* See if we can do this with a 16-bit instruction. */
12969 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12970 inst
.instruction
|= Rn
;
12971 inst
.instruction
|= Rm
<< 3;
12975 constraint (inst
.operands
[1].shifted
12976 && inst
.operands
[1].immisreg
,
12977 _("shift must be constant"));
12978 if (inst
.instruction
< 0xffff)
12979 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12980 inst
.instruction
|= Rn
<< r0off
;
12981 encode_thumb32_shifted_operand (1);
12987 constraint (inst
.instruction
> 0xffff
12988 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12989 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12990 _("unshifted register required"));
12991 constraint (Rn
> 7 || Rm
> 7,
12994 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12995 inst
.instruction
|= Rn
;
12996 inst
.instruction
|= Rm
<< 3;
13005 if (do_vfp_nsyn_mrs () == SUCCESS
)
13008 Rd
= inst
.operands
[0].reg
;
13009 reject_bad_reg (Rd
);
13010 inst
.instruction
|= Rd
<< 8;
13012 if (inst
.operands
[1].isreg
)
13014 unsigned br
= inst
.operands
[1].reg
;
13015 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13016 as_bad (_("bad register for mrs"));
13018 inst
.instruction
|= br
& (0xf << 16);
13019 inst
.instruction
|= (br
& 0x300) >> 4;
13020 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13024 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13026 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13028 /* PR gas/12698: The constraint is only applied for m_profile.
13029 If the user has specified -march=all, we want to ignore it as
13030 we are building for any CPU type, including non-m variants. */
13031 bfd_boolean m_profile
=
13032 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13033 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13034 "not support requested special purpose register"));
13037 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13039 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13040 _("'APSR', 'CPSR' or 'SPSR' expected"));
13042 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13043 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13044 inst
.instruction
|= 0xf0000;
13054 if (do_vfp_nsyn_msr () == SUCCESS
)
13057 constraint (!inst
.operands
[1].isreg
,
13058 _("Thumb encoding does not support an immediate here"));
13060 if (inst
.operands
[0].isreg
)
13061 flags
= (int)(inst
.operands
[0].reg
);
13063 flags
= inst
.operands
[0].imm
;
13065 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13067 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13069 /* PR gas/12698: The constraint is only applied for m_profile.
13070 If the user has specified -march=all, we want to ignore it as
13071 we are building for any CPU type, including non-m variants. */
13072 bfd_boolean m_profile
=
13073 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13074 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13075 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13076 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13077 && bits
!= PSR_f
)) && m_profile
,
13078 _("selected processor does not support requested special "
13079 "purpose register"));
13082 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13083 "requested special purpose register"));
13085 Rn
= inst
.operands
[1].reg
;
13086 reject_bad_reg (Rn
);
13088 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13089 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13090 inst
.instruction
|= (flags
& 0x300) >> 4;
13091 inst
.instruction
|= (flags
& 0xff);
13092 inst
.instruction
|= Rn
<< 16;
13098 bfd_boolean narrow
;
13099 unsigned Rd
, Rn
, Rm
;
13101 if (!inst
.operands
[2].present
)
13102 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13104 Rd
= inst
.operands
[0].reg
;
13105 Rn
= inst
.operands
[1].reg
;
13106 Rm
= inst
.operands
[2].reg
;
13108 if (unified_syntax
)
13110 if (inst
.size_req
== 4
13116 else if (inst
.instruction
== T_MNEM_muls
)
13117 narrow
= !in_pred_block ();
13119 narrow
= in_pred_block ();
13123 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13124 constraint (Rn
> 7 || Rm
> 7,
13131 /* 16-bit MULS/Conditional MUL. */
13132 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13133 inst
.instruction
|= Rd
;
13136 inst
.instruction
|= Rm
<< 3;
13138 inst
.instruction
|= Rn
<< 3;
13140 constraint (1, _("dest must overlap one source register"));
13144 constraint (inst
.instruction
!= T_MNEM_mul
,
13145 _("Thumb-2 MUL must not set flags"));
13147 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13148 inst
.instruction
|= Rd
<< 8;
13149 inst
.instruction
|= Rn
<< 16;
13150 inst
.instruction
|= Rm
<< 0;
13152 reject_bad_reg (Rd
);
13153 reject_bad_reg (Rn
);
13154 reject_bad_reg (Rm
);
13161 unsigned RdLo
, RdHi
, Rn
, Rm
;
13163 RdLo
= inst
.operands
[0].reg
;
13164 RdHi
= inst
.operands
[1].reg
;
13165 Rn
= inst
.operands
[2].reg
;
13166 Rm
= inst
.operands
[3].reg
;
13168 reject_bad_reg (RdLo
);
13169 reject_bad_reg (RdHi
);
13170 reject_bad_reg (Rn
);
13171 reject_bad_reg (Rm
);
13173 inst
.instruction
|= RdLo
<< 12;
13174 inst
.instruction
|= RdHi
<< 8;
13175 inst
.instruction
|= Rn
<< 16;
13176 inst
.instruction
|= Rm
;
13179 as_tsktsk (_("rdhi and rdlo must be different"));
13185 set_pred_insn_type (NEUTRAL_IT_INSN
);
13187 if (unified_syntax
)
13189 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13191 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13192 inst
.instruction
|= inst
.operands
[0].imm
;
13196 /* PR9722: Check for Thumb2 availability before
13197 generating a thumb2 nop instruction. */
13198 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13201 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13204 inst
.instruction
= 0x46c0;
13209 constraint (inst
.operands
[0].present
,
13210 _("Thumb does not support NOP with hints"));
13211 inst
.instruction
= 0x46c0;
13218 if (unified_syntax
)
13220 bfd_boolean narrow
;
13222 if (THUMB_SETS_FLAGS (inst
.instruction
))
13223 narrow
= !in_pred_block ();
13225 narrow
= in_pred_block ();
13226 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13228 if (inst
.size_req
== 4)
13233 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13239 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13240 inst
.instruction
|= inst
.operands
[0].reg
;
13241 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13246 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13248 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13250 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13251 inst
.instruction
|= inst
.operands
[0].reg
;
13252 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13261 Rd
= inst
.operands
[0].reg
;
13262 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13264 reject_bad_reg (Rd
);
13265 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13266 reject_bad_reg (Rn
);
13268 inst
.instruction
|= Rd
<< 8;
13269 inst
.instruction
|= Rn
<< 16;
13271 if (!inst
.operands
[2].isreg
)
13273 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13274 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13280 Rm
= inst
.operands
[2].reg
;
13281 reject_bad_reg (Rm
);
13283 constraint (inst
.operands
[2].shifted
13284 && inst
.operands
[2].immisreg
,
13285 _("shift must be constant"));
13286 encode_thumb32_shifted_operand (2);
13293 unsigned Rd
, Rn
, Rm
;
13295 Rd
= inst
.operands
[0].reg
;
13296 Rn
= inst
.operands
[1].reg
;
13297 Rm
= inst
.operands
[2].reg
;
13299 reject_bad_reg (Rd
);
13300 reject_bad_reg (Rn
);
13301 reject_bad_reg (Rm
);
13303 inst
.instruction
|= Rd
<< 8;
13304 inst
.instruction
|= Rn
<< 16;
13305 inst
.instruction
|= Rm
;
13306 if (inst
.operands
[3].present
)
13308 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13309 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13310 _("expression too complex"));
13311 inst
.instruction
|= (val
& 0x1c) << 10;
13312 inst
.instruction
|= (val
& 0x03) << 6;
13319 if (!inst
.operands
[3].present
)
13323 inst
.instruction
&= ~0x00000020;
13325 /* PR 10168. Swap the Rm and Rn registers. */
13326 Rtmp
= inst
.operands
[1].reg
;
13327 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13328 inst
.operands
[2].reg
= Rtmp
;
13336 if (inst
.operands
[0].immisreg
)
13337 reject_bad_reg (inst
.operands
[0].imm
);
13339 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13343 do_t_push_pop (void)
13347 constraint (inst
.operands
[0].writeback
,
13348 _("push/pop do not support {reglist}^"));
13349 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13350 _("expression too complex"));
13352 mask
= inst
.operands
[0].imm
;
13353 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13354 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13355 else if (inst
.size_req
!= 4
13356 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13357 ? REG_LR
: REG_PC
)))
13359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13360 inst
.instruction
|= THUMB_PP_PC_LR
;
13361 inst
.instruction
|= mask
& 0xff;
13363 else if (unified_syntax
)
13365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13366 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13370 inst
.error
= _("invalid register list to push/pop instruction");
13378 if (unified_syntax
)
13379 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13382 inst
.error
= _("invalid register list to push/pop instruction");
13388 do_t_vscclrm (void)
13390 if (inst
.operands
[0].issingle
)
13392 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13393 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13394 inst
.instruction
|= inst
.operands
[0].imm
;
13398 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13399 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13400 inst
.instruction
|= 1 << 8;
13401 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13410 Rd
= inst
.operands
[0].reg
;
13411 Rm
= inst
.operands
[1].reg
;
13413 reject_bad_reg (Rd
);
13414 reject_bad_reg (Rm
);
13416 inst
.instruction
|= Rd
<< 8;
13417 inst
.instruction
|= Rm
<< 16;
13418 inst
.instruction
|= Rm
;
13426 Rd
= inst
.operands
[0].reg
;
13427 Rm
= inst
.operands
[1].reg
;
13429 reject_bad_reg (Rd
);
13430 reject_bad_reg (Rm
);
13432 if (Rd
<= 7 && Rm
<= 7
13433 && inst
.size_req
!= 4)
13435 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13436 inst
.instruction
|= Rd
;
13437 inst
.instruction
|= Rm
<< 3;
13439 else if (unified_syntax
)
13441 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13442 inst
.instruction
|= Rd
<< 8;
13443 inst
.instruction
|= Rm
<< 16;
13444 inst
.instruction
|= Rm
;
13447 inst
.error
= BAD_HIREG
;
13455 Rd
= inst
.operands
[0].reg
;
13456 Rm
= inst
.operands
[1].reg
;
13458 reject_bad_reg (Rd
);
13459 reject_bad_reg (Rm
);
13461 inst
.instruction
|= Rd
<< 8;
13462 inst
.instruction
|= Rm
;
13470 Rd
= inst
.operands
[0].reg
;
13471 Rs
= (inst
.operands
[1].present
13472 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13473 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13475 reject_bad_reg (Rd
);
13476 reject_bad_reg (Rs
);
13477 if (inst
.operands
[2].isreg
)
13478 reject_bad_reg (inst
.operands
[2].reg
);
13480 inst
.instruction
|= Rd
<< 8;
13481 inst
.instruction
|= Rs
<< 16;
13482 if (!inst
.operands
[2].isreg
)
13484 bfd_boolean narrow
;
13486 if ((inst
.instruction
& 0x00100000) != 0)
13487 narrow
= !in_pred_block ();
13489 narrow
= in_pred_block ();
13491 if (Rd
> 7 || Rs
> 7)
13494 if (inst
.size_req
== 4 || !unified_syntax
)
13497 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13498 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13501 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13502 relaxation, but it doesn't seem worth the hassle. */
13505 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13506 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13507 inst
.instruction
|= Rs
<< 3;
13508 inst
.instruction
|= Rd
;
13512 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13513 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13517 encode_thumb32_shifted_operand (2);
13523 if (warn_on_deprecated
13524 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13525 as_tsktsk (_("setend use is deprecated for ARMv8"));
13527 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13528 if (inst
.operands
[0].imm
)
13529 inst
.instruction
|= 0x8;
13535 if (!inst
.operands
[1].present
)
13536 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13538 if (unified_syntax
)
13540 bfd_boolean narrow
;
13543 switch (inst
.instruction
)
13546 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13548 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13550 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13552 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13556 if (THUMB_SETS_FLAGS (inst
.instruction
))
13557 narrow
= !in_pred_block ();
13559 narrow
= in_pred_block ();
13560 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13562 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13564 if (inst
.operands
[2].isreg
13565 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13566 || inst
.operands
[2].reg
> 7))
13568 if (inst
.size_req
== 4)
13571 reject_bad_reg (inst
.operands
[0].reg
);
13572 reject_bad_reg (inst
.operands
[1].reg
);
13576 if (inst
.operands
[2].isreg
)
13578 reject_bad_reg (inst
.operands
[2].reg
);
13579 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13580 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13581 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13582 inst
.instruction
|= inst
.operands
[2].reg
;
13584 /* PR 12854: Error on extraneous shifts. */
13585 constraint (inst
.operands
[2].shifted
,
13586 _("extraneous shift as part of operand to shift insn"));
13590 inst
.operands
[1].shifted
= 1;
13591 inst
.operands
[1].shift_kind
= shift_kind
;
13592 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13593 ? T_MNEM_movs
: T_MNEM_mov
);
13594 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13595 encode_thumb32_shifted_operand (1);
13596 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13597 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13602 if (inst
.operands
[2].isreg
)
13604 switch (shift_kind
)
13606 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13607 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13608 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13609 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13613 inst
.instruction
|= inst
.operands
[0].reg
;
13614 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13616 /* PR 12854: Error on extraneous shifts. */
13617 constraint (inst
.operands
[2].shifted
,
13618 _("extraneous shift as part of operand to shift insn"));
13622 switch (shift_kind
)
13624 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13625 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13626 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13629 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13630 inst
.instruction
|= inst
.operands
[0].reg
;
13631 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13637 constraint (inst
.operands
[0].reg
> 7
13638 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13639 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13641 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13643 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13644 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13645 _("source1 and dest must be same register"));
13647 switch (inst
.instruction
)
13649 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13650 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13651 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13652 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13656 inst
.instruction
|= inst
.operands
[0].reg
;
13657 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13659 /* PR 12854: Error on extraneous shifts. */
13660 constraint (inst
.operands
[2].shifted
,
13661 _("extraneous shift as part of operand to shift insn"));
13665 switch (inst
.instruction
)
13667 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13668 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13669 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13670 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13673 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13674 inst
.instruction
|= inst
.operands
[0].reg
;
13675 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13683 unsigned Rd
, Rn
, Rm
;
13685 Rd
= inst
.operands
[0].reg
;
13686 Rn
= inst
.operands
[1].reg
;
13687 Rm
= inst
.operands
[2].reg
;
13689 reject_bad_reg (Rd
);
13690 reject_bad_reg (Rn
);
13691 reject_bad_reg (Rm
);
13693 inst
.instruction
|= Rd
<< 8;
13694 inst
.instruction
|= Rn
<< 16;
13695 inst
.instruction
|= Rm
;
13701 unsigned Rd
, Rn
, Rm
;
13703 Rd
= inst
.operands
[0].reg
;
13704 Rm
= inst
.operands
[1].reg
;
13705 Rn
= inst
.operands
[2].reg
;
13707 reject_bad_reg (Rd
);
13708 reject_bad_reg (Rn
);
13709 reject_bad_reg (Rm
);
13711 inst
.instruction
|= Rd
<< 8;
13712 inst
.instruction
|= Rn
<< 16;
13713 inst
.instruction
|= Rm
;
13719 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13720 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13721 _("SMC is not permitted on this architecture"));
13722 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13723 _("expression too complex"));
13724 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13725 inst
.instruction
|= (value
& 0xf000) >> 12;
13726 inst
.instruction
|= (value
& 0x0ff0);
13727 inst
.instruction
|= (value
& 0x000f) << 16;
13728 /* PR gas/15623: SMC instructions must be last in an IT block. */
13729 set_pred_insn_type_last ();
13735 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13737 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13738 inst
.instruction
|= (value
& 0x0fff);
13739 inst
.instruction
|= (value
& 0xf000) << 4;
13743 do_t_ssat_usat (int bias
)
13747 Rd
= inst
.operands
[0].reg
;
13748 Rn
= inst
.operands
[2].reg
;
13750 reject_bad_reg (Rd
);
13751 reject_bad_reg (Rn
);
13753 inst
.instruction
|= Rd
<< 8;
13754 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13755 inst
.instruction
|= Rn
<< 16;
13757 if (inst
.operands
[3].present
)
13759 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13761 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13763 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13764 _("expression too complex"));
13766 if (shift_amount
!= 0)
13768 constraint (shift_amount
> 31,
13769 _("shift expression is too large"));
13771 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13772 inst
.instruction
|= 0x00200000; /* sh bit. */
13774 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13775 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13783 do_t_ssat_usat (1);
13791 Rd
= inst
.operands
[0].reg
;
13792 Rn
= inst
.operands
[2].reg
;
13794 reject_bad_reg (Rd
);
13795 reject_bad_reg (Rn
);
13797 inst
.instruction
|= Rd
<< 8;
13798 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13799 inst
.instruction
|= Rn
<< 16;
13805 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13806 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13807 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13808 || inst
.operands
[2].negative
,
13811 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13813 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13814 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13815 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13816 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13822 if (!inst
.operands
[2].present
)
13823 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13825 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13826 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13827 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13830 inst
.instruction
|= inst
.operands
[0].reg
;
13831 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13832 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13833 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13839 unsigned Rd
, Rn
, Rm
;
13841 Rd
= inst
.operands
[0].reg
;
13842 Rn
= inst
.operands
[1].reg
;
13843 Rm
= inst
.operands
[2].reg
;
13845 reject_bad_reg (Rd
);
13846 reject_bad_reg (Rn
);
13847 reject_bad_reg (Rm
);
13849 inst
.instruction
|= Rd
<< 8;
13850 inst
.instruction
|= Rn
<< 16;
13851 inst
.instruction
|= Rm
;
13852 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13860 Rd
= inst
.operands
[0].reg
;
13861 Rm
= inst
.operands
[1].reg
;
13863 reject_bad_reg (Rd
);
13864 reject_bad_reg (Rm
);
13866 if (inst
.instruction
<= 0xffff
13867 && inst
.size_req
!= 4
13868 && Rd
<= 7 && Rm
<= 7
13869 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13871 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13872 inst
.instruction
|= Rd
;
13873 inst
.instruction
|= Rm
<< 3;
13875 else if (unified_syntax
)
13877 if (inst
.instruction
<= 0xffff)
13878 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13879 inst
.instruction
|= Rd
<< 8;
13880 inst
.instruction
|= Rm
;
13881 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13885 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13886 _("Thumb encoding does not support rotation"));
13887 constraint (1, BAD_HIREG
);
13894 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13903 half
= (inst
.instruction
& 0x10) != 0;
13904 set_pred_insn_type_last ();
13905 constraint (inst
.operands
[0].immisreg
,
13906 _("instruction requires register index"));
13908 Rn
= inst
.operands
[0].reg
;
13909 Rm
= inst
.operands
[0].imm
;
13911 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13912 constraint (Rn
== REG_SP
, BAD_SP
);
13913 reject_bad_reg (Rm
);
13915 constraint (!half
&& inst
.operands
[0].shifted
,
13916 _("instruction does not allow shifted index"));
13917 inst
.instruction
|= (Rn
<< 16) | Rm
;
13923 if (!inst
.operands
[0].present
)
13924 inst
.operands
[0].imm
= 0;
13926 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13928 constraint (inst
.size_req
== 2,
13929 _("immediate value out of range"));
13930 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13931 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13932 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13936 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13937 inst
.instruction
|= inst
.operands
[0].imm
;
13940 set_pred_insn_type (NEUTRAL_IT_INSN
);
13947 do_t_ssat_usat (0);
13955 Rd
= inst
.operands
[0].reg
;
13956 Rn
= inst
.operands
[2].reg
;
13958 reject_bad_reg (Rd
);
13959 reject_bad_reg (Rn
);
13961 inst
.instruction
|= Rd
<< 8;
13962 inst
.instruction
|= inst
.operands
[1].imm
;
13963 inst
.instruction
|= Rn
<< 16;
13966 /* Checking the range of the branch offset (VAL) with NBITS bits
13967 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13969 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13971 gas_assert (nbits
> 0 && nbits
<= 32);
13974 int cmp
= (1 << (nbits
- 1));
13975 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13980 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13986 /* For branches in Armv8.1-M Mainline. */
13988 do_t_branch_future (void)
13990 unsigned long insn
= inst
.instruction
;
13992 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13993 if (inst
.operands
[0].hasreloc
== 0)
13995 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13996 as_bad (BAD_BRANCH_OFF
);
13998 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14002 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14003 inst
.relocs
[0].pc_rel
= 1;
14009 if (inst
.operands
[1].hasreloc
== 0)
14011 int val
= inst
.operands
[1].imm
;
14012 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14013 as_bad (BAD_BRANCH_OFF
);
14015 int immA
= (val
& 0x0001f000) >> 12;
14016 int immB
= (val
& 0x00000ffc) >> 2;
14017 int immC
= (val
& 0x00000002) >> 1;
14018 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14022 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14023 inst
.relocs
[1].pc_rel
= 1;
14028 if (inst
.operands
[1].hasreloc
== 0)
14030 int val
= inst
.operands
[1].imm
;
14031 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14032 as_bad (BAD_BRANCH_OFF
);
14034 int immA
= (val
& 0x0007f000) >> 12;
14035 int immB
= (val
& 0x00000ffc) >> 2;
14036 int immC
= (val
& 0x00000002) >> 1;
14037 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14041 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14042 inst
.relocs
[1].pc_rel
= 1;
14046 case T_MNEM_bfcsel
:
14048 if (inst
.operands
[1].hasreloc
== 0)
14050 int val
= inst
.operands
[1].imm
;
14051 int immA
= (val
& 0x00001000) >> 12;
14052 int immB
= (val
& 0x00000ffc) >> 2;
14053 int immC
= (val
& 0x00000002) >> 1;
14054 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14058 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14059 inst
.relocs
[1].pc_rel
= 1;
14063 if (inst
.operands
[2].hasreloc
== 0)
14065 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14066 int val2
= inst
.operands
[2].imm
;
14067 int val0
= inst
.operands
[0].imm
& 0x1f;
14068 int diff
= val2
- val0
;
14070 inst
.instruction
|= 1 << 17; /* T bit. */
14071 else if (diff
!= 2)
14072 as_bad (_("out of range label-relative fixup value"));
14076 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14077 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14078 inst
.relocs
[2].pc_rel
= 1;
14082 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14083 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14095 /* Helper function for do_t_loloop to handle relocations. */
14097 v8_1_loop_reloc (int is_le
)
14099 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14101 int value
= inst
.relocs
[0].exp
.X_add_number
;
14102 value
= (is_le
) ? -value
: value
;
14104 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14105 as_bad (BAD_BRANCH_OFF
);
14109 immh
= (value
& 0x00000ffc) >> 2;
14110 imml
= (value
& 0x00000002) >> 1;
14112 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14116 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14117 inst
.relocs
[0].pc_rel
= 1;
14121 /* MVE instruction encoder helpers. */
14122 #define M_MNEM_vabav 0xee800f01
14123 #define M_MNEM_vmladav 0xeef00e00
14124 #define M_MNEM_vmladava 0xeef00e20
14125 #define M_MNEM_vmladavx 0xeef01e00
14126 #define M_MNEM_vmladavax 0xeef01e20
14127 #define M_MNEM_vmlsdav 0xeef00e01
14128 #define M_MNEM_vmlsdava 0xeef00e21
14129 #define M_MNEM_vmlsdavx 0xeef01e01
14130 #define M_MNEM_vmlsdavax 0xeef01e21
14131 #define M_MNEM_vmullt 0xee011e00
14132 #define M_MNEM_vmullb 0xee010e00
14133 #define M_MNEM_vst20 0xfc801e00
14134 #define M_MNEM_vst21 0xfc801e20
14135 #define M_MNEM_vst40 0xfc801e01
14136 #define M_MNEM_vst41 0xfc801e21
14137 #define M_MNEM_vst42 0xfc801e41
14138 #define M_MNEM_vst43 0xfc801e61
14139 #define M_MNEM_vld20 0xfc901e00
14140 #define M_MNEM_vld21 0xfc901e20
14141 #define M_MNEM_vld40 0xfc901e01
14142 #define M_MNEM_vld41 0xfc901e21
14143 #define M_MNEM_vld42 0xfc901e41
14144 #define M_MNEM_vld43 0xfc901e61
14145 #define M_MNEM_vstrb 0xec000e00
14146 #define M_MNEM_vstrh 0xec000e10
14147 #define M_MNEM_vstrw 0xec000e40
14148 #define M_MNEM_vstrd 0xec000e50
14149 #define M_MNEM_vldrb 0xec100e00
14150 #define M_MNEM_vldrh 0xec100e10
14151 #define M_MNEM_vldrw 0xec100e40
14152 #define M_MNEM_vldrd 0xec100e50
14153 #define M_MNEM_vmovlt 0xeea01f40
14154 #define M_MNEM_vmovlb 0xeea00f40
14155 #define M_MNEM_vmovnt 0xfe311e81
14156 #define M_MNEM_vmovnb 0xfe310e81
14157 #define M_MNEM_vadc 0xee300f00
14158 #define M_MNEM_vadci 0xee301f00
14159 #define M_MNEM_vbrsr 0xfe011e60
14160 #define M_MNEM_vaddlv 0xee890f00
14161 #define M_MNEM_vaddlva 0xee890f20
14162 #define M_MNEM_vaddv 0xeef10f00
14163 #define M_MNEM_vaddva 0xeef10f20
14164 #define M_MNEM_vddup 0xee011f6e
14165 #define M_MNEM_vdwdup 0xee011f60
14166 #define M_MNEM_vidup 0xee010f6e
14167 #define M_MNEM_viwdup 0xee010f60
14168 #define M_MNEM_vmaxv 0xeee20f00
14169 #define M_MNEM_vmaxav 0xeee00f00
14170 #define M_MNEM_vminv 0xeee20f80
14171 #define M_MNEM_vminav 0xeee00f80
14172 #define M_MNEM_vmlaldav 0xee800e00
14173 #define M_MNEM_vmlaldava 0xee800e20
14174 #define M_MNEM_vmlaldavx 0xee801e00
14175 #define M_MNEM_vmlaldavax 0xee801e20
14176 #define M_MNEM_vmlsldav 0xee800e01
14177 #define M_MNEM_vmlsldava 0xee800e21
14178 #define M_MNEM_vmlsldavx 0xee801e01
14179 #define M_MNEM_vmlsldavax 0xee801e21
14180 #define M_MNEM_vrmlaldavhx 0xee801f00
14181 #define M_MNEM_vrmlaldavhax 0xee801f20
14182 #define M_MNEM_vrmlsldavh 0xfe800e01
14183 #define M_MNEM_vrmlsldavha 0xfe800e21
14184 #define M_MNEM_vrmlsldavhx 0xfe801e01
14185 #define M_MNEM_vrmlsldavhax 0xfe801e21
14186 #define M_MNEM_vqmovnt 0xee331e01
14187 #define M_MNEM_vqmovnb 0xee330e01
14188 #define M_MNEM_vqmovunt 0xee311e81
14189 #define M_MNEM_vqmovunb 0xee310e81
14190 #define M_MNEM_vshrnt 0xee801fc1
14191 #define M_MNEM_vshrnb 0xee800fc1
14192 #define M_MNEM_vrshrnt 0xfe801fc1
14193 #define M_MNEM_vqshrnt 0xee801f40
14194 #define M_MNEM_vqshrnb 0xee800f40
14195 #define M_MNEM_vqshrunt 0xee801fc0
14196 #define M_MNEM_vqshrunb 0xee800fc0
14197 #define M_MNEM_vrshrnb 0xfe800fc1
14198 #define M_MNEM_vqrshrnt 0xee801f41
14199 #define M_MNEM_vqrshrnb 0xee800f41
14200 #define M_MNEM_vqrshrunt 0xfe801fc0
14201 #define M_MNEM_vqrshrunb 0xfe800fc0
14203 /* Neon instruction encoder helpers. */
14205 /* Encodings for the different types for various Neon opcodes. */
14207 /* An "invalid" code for the following tables. */
14210 struct neon_tab_entry
14213 unsigned float_or_poly
;
14214 unsigned scalar_or_imm
;
14217 /* Map overloaded Neon opcodes to their respective encodings. */
14218 #define NEON_ENC_TAB \
14219 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14220 X(vabdl, 0x0800700, N_INV, N_INV), \
14221 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14222 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14223 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14224 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14225 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14226 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14227 X(vaddl, 0x0800000, N_INV, N_INV), \
14228 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14229 X(vsubl, 0x0800200, N_INV, N_INV), \
14230 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14231 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14232 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14233 /* Register variants of the following two instructions are encoded as
14234 vcge / vcgt with the operands reversed. */ \
14235 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14236 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14237 X(vfma, N_INV, 0x0000c10, N_INV), \
14238 X(vfms, N_INV, 0x0200c10, N_INV), \
14239 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14240 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14241 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14242 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14243 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14244 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14245 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14246 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14247 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14248 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14249 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14250 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14251 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14252 X(vshl, 0x0000400, N_INV, 0x0800510), \
14253 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14254 X(vand, 0x0000110, N_INV, 0x0800030), \
14255 X(vbic, 0x0100110, N_INV, 0x0800030), \
14256 X(veor, 0x1000110, N_INV, N_INV), \
14257 X(vorn, 0x0300110, N_INV, 0x0800010), \
14258 X(vorr, 0x0200110, N_INV, 0x0800010), \
14259 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14260 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14261 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14262 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14263 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14264 X(vst1, 0x0000000, 0x0800000, N_INV), \
14265 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14266 X(vst2, 0x0000100, 0x0800100, N_INV), \
14267 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14268 X(vst3, 0x0000200, 0x0800200, N_INV), \
14269 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14270 X(vst4, 0x0000300, 0x0800300, N_INV), \
14271 X(vmovn, 0x1b20200, N_INV, N_INV), \
14272 X(vtrn, 0x1b20080, N_INV, N_INV), \
14273 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14274 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14275 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14276 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14277 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14278 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14279 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14280 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14281 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14282 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14283 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14284 X(vseleq, 0xe000a00, N_INV, N_INV), \
14285 X(vselvs, 0xe100a00, N_INV, N_INV), \
14286 X(vselge, 0xe200a00, N_INV, N_INV), \
14287 X(vselgt, 0xe300a00, N_INV, N_INV), \
14288 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14289 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14290 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14291 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14292 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14293 X(aes, 0x3b00300, N_INV, N_INV), \
14294 X(sha3op, 0x2000c00, N_INV, N_INV), \
14295 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14296 X(sha2op, 0x3ba0380, N_INV, N_INV)
14300 #define X(OPC,I,F,S) N_MNEM_##OPC
14305 static const struct neon_tab_entry neon_enc_tab
[] =
14307 #define X(OPC,I,F,S) { (I), (F), (S) }
14312 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14313 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14314 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14315 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14316 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14317 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14318 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14319 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14320 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14321 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14322 #define NEON_ENC_SINGLE_(X) \
14323 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14324 #define NEON_ENC_DOUBLE_(X) \
14325 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14326 #define NEON_ENC_FPV8_(X) \
14327 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14329 #define NEON_ENCODE(type, inst) \
14332 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14333 inst.is_neon = 1; \
14337 #define check_neon_suffixes \
14340 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14342 as_bad (_("invalid neon suffix for non neon instruction")); \
14348 /* Define shapes for instruction operands. The following mnemonic characters
14349 are used in this table:
14351 F - VFP S<n> register
14352 D - Neon D<n> register
14353 Q - Neon Q<n> register
14357 L - D<n> register list
14359 This table is used to generate various data:
14360 - enumerations of the form NS_DDR to be used as arguments to
14362 - a table classifying shapes into single, double, quad, mixed.
14363 - a table used to drive neon_select_shape. */
14365 #define NEON_SHAPE_DEF \
14366 X(4, (R, R, Q, Q), QUAD), \
14367 X(4, (Q, R, R, I), QUAD), \
14368 X(4, (R, R, S, S), QUAD), \
14369 X(4, (S, S, R, R), QUAD), \
14370 X(3, (Q, R, I), QUAD), \
14371 X(3, (I, Q, Q), QUAD), \
14372 X(3, (I, Q, R), QUAD), \
14373 X(3, (R, Q, Q), QUAD), \
14374 X(3, (D, D, D), DOUBLE), \
14375 X(3, (Q, Q, Q), QUAD), \
14376 X(3, (D, D, I), DOUBLE), \
14377 X(3, (Q, Q, I), QUAD), \
14378 X(3, (D, D, S), DOUBLE), \
14379 X(3, (Q, Q, S), QUAD), \
14380 X(3, (Q, Q, R), QUAD), \
14381 X(3, (R, R, Q), QUAD), \
14382 X(2, (R, Q), QUAD), \
14383 X(2, (D, D), DOUBLE), \
14384 X(2, (Q, Q), QUAD), \
14385 X(2, (D, S), DOUBLE), \
14386 X(2, (Q, S), QUAD), \
14387 X(2, (D, R), DOUBLE), \
14388 X(2, (Q, R), QUAD), \
14389 X(2, (D, I), DOUBLE), \
14390 X(2, (Q, I), QUAD), \
14391 X(3, (D, L, D), DOUBLE), \
14392 X(2, (D, Q), MIXED), \
14393 X(2, (Q, D), MIXED), \
14394 X(3, (D, Q, I), MIXED), \
14395 X(3, (Q, D, I), MIXED), \
14396 X(3, (Q, D, D), MIXED), \
14397 X(3, (D, Q, Q), MIXED), \
14398 X(3, (Q, Q, D), MIXED), \
14399 X(3, (Q, D, S), MIXED), \
14400 X(3, (D, Q, S), MIXED), \
14401 X(4, (D, D, D, I), DOUBLE), \
14402 X(4, (Q, Q, Q, I), QUAD), \
14403 X(4, (D, D, S, I), DOUBLE), \
14404 X(4, (Q, Q, S, I), QUAD), \
14405 X(2, (F, F), SINGLE), \
14406 X(3, (F, F, F), SINGLE), \
14407 X(2, (F, I), SINGLE), \
14408 X(2, (F, D), MIXED), \
14409 X(2, (D, F), MIXED), \
14410 X(3, (F, F, I), MIXED), \
14411 X(4, (R, R, F, F), SINGLE), \
14412 X(4, (F, F, R, R), SINGLE), \
14413 X(3, (D, R, R), DOUBLE), \
14414 X(3, (R, R, D), DOUBLE), \
14415 X(2, (S, R), SINGLE), \
14416 X(2, (R, S), SINGLE), \
14417 X(2, (F, R), SINGLE), \
14418 X(2, (R, F), SINGLE), \
14419 /* Used for MVE tail predicated loop instructions. */\
14420 X(2, (R, R), QUAD), \
14421 /* Half float shape supported so far. */\
14422 X (2, (H, D), MIXED), \
14423 X (2, (D, H), MIXED), \
14424 X (2, (H, F), MIXED), \
14425 X (2, (F, H), MIXED), \
14426 X (2, (H, H), HALF), \
14427 X (2, (H, R), HALF), \
14428 X (2, (R, H), HALF), \
14429 X (2, (H, I), HALF), \
14430 X (3, (H, H, H), HALF), \
14431 X (3, (H, F, I), MIXED), \
14432 X (3, (F, H, I), MIXED), \
14433 X (3, (D, H, H), MIXED), \
14434 X (3, (D, H, S), MIXED)
14436 #define S2(A,B) NS_##A##B
14437 #define S3(A,B,C) NS_##A##B##C
14438 #define S4(A,B,C,D) NS_##A##B##C##D
14440 #define X(N, L, C) S##N L
14453 enum neon_shape_class
14462 #define X(N, L, C) SC_##C
14464 static enum neon_shape_class neon_shape_class
[] =
14483 /* Register widths of above. */
14484 static unsigned neon_shape_el_size
[] =
14496 struct neon_shape_info
14499 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14502 #define S2(A,B) { SE_##A, SE_##B }
14503 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14504 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14506 #define X(N, L, C) { N, S##N L }
14508 static struct neon_shape_info neon_shape_tab
[] =
14518 /* Bit masks used in type checking given instructions.
14519 'N_EQK' means the type must be the same as (or based on in some way) the key
14520 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14521 set, various other bits can be set as well in order to modify the meaning of
14522 the type constraint. */
14524 enum neon_type_mask
14548 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14549 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14550 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14551 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14552 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14553 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14554 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14555 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14556 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14557 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14558 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14560 N_MAX_NONSPECIAL
= N_P64
14563 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14565 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14566 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14567 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14568 #define N_S_32 (N_S8 | N_S16 | N_S32)
14569 #define N_F_16_32 (N_F16 | N_F32)
14570 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14571 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14572 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14573 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14574 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14575 #define N_F_MVE (N_F16 | N_F32)
14576 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14578 /* Pass this as the first type argument to neon_check_type to ignore types
14580 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14582 /* Select a "shape" for the current instruction (describing register types or
14583 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14584 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14585 function of operand parsing, so this function doesn't need to be called.
14586 Shapes should be listed in order of decreasing length. */
14588 static enum neon_shape
14589 neon_select_shape (enum neon_shape shape
, ...)
14592 enum neon_shape first_shape
= shape
;
14594 /* Fix missing optional operands. FIXME: we don't know at this point how
14595 many arguments we should have, so this makes the assumption that we have
14596 > 1. This is true of all current Neon opcodes, I think, but may not be
14597 true in the future. */
14598 if (!inst
.operands
[1].present
)
14599 inst
.operands
[1] = inst
.operands
[0];
14601 va_start (ap
, shape
);
14603 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14608 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14610 if (!inst
.operands
[j
].present
)
14616 switch (neon_shape_tab
[shape
].el
[j
])
14618 /* If a .f16, .16, .u16, .s16 type specifier is given over
14619 a VFP single precision register operand, it's essentially
14620 means only half of the register is used.
14622 If the type specifier is given after the mnemonics, the
14623 information is stored in inst.vectype. If the type specifier
14624 is given after register operand, the information is stored
14625 in inst.operands[].vectype.
14627 When there is only one type specifier, and all the register
14628 operands are the same type of hardware register, the type
14629 specifier applies to all register operands.
14631 If no type specifier is given, the shape is inferred from
14632 operand information.
14635 vadd.f16 s0, s1, s2: NS_HHH
14636 vabs.f16 s0, s1: NS_HH
14637 vmov.f16 s0, r1: NS_HR
14638 vmov.f16 r0, s1: NS_RH
14639 vcvt.f16 r0, s1: NS_RH
14640 vcvt.f16.s32 s2, s2, #29: NS_HFI
14641 vcvt.f16.s32 s2, s2: NS_HF
14644 if (!(inst
.operands
[j
].isreg
14645 && inst
.operands
[j
].isvec
14646 && inst
.operands
[j
].issingle
14647 && !inst
.operands
[j
].isquad
14648 && ((inst
.vectype
.elems
== 1
14649 && inst
.vectype
.el
[0].size
== 16)
14650 || (inst
.vectype
.elems
> 1
14651 && inst
.vectype
.el
[j
].size
== 16)
14652 || (inst
.vectype
.elems
== 0
14653 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14654 && inst
.operands
[j
].vectype
.size
== 16))))
14659 if (!(inst
.operands
[j
].isreg
14660 && inst
.operands
[j
].isvec
14661 && inst
.operands
[j
].issingle
14662 && !inst
.operands
[j
].isquad
14663 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14664 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14665 || (inst
.vectype
.elems
== 0
14666 && (inst
.operands
[j
].vectype
.size
== 32
14667 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14672 if (!(inst
.operands
[j
].isreg
14673 && inst
.operands
[j
].isvec
14674 && !inst
.operands
[j
].isquad
14675 && !inst
.operands
[j
].issingle
))
14680 if (!(inst
.operands
[j
].isreg
14681 && !inst
.operands
[j
].isvec
))
14686 if (!(inst
.operands
[j
].isreg
14687 && inst
.operands
[j
].isvec
14688 && inst
.operands
[j
].isquad
14689 && !inst
.operands
[j
].issingle
))
14694 if (!(!inst
.operands
[j
].isreg
14695 && !inst
.operands
[j
].isscalar
))
14700 if (!(!inst
.operands
[j
].isreg
14701 && inst
.operands
[j
].isscalar
))
14711 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14712 /* We've matched all the entries in the shape table, and we don't
14713 have any left over operands which have not been matched. */
14719 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14720 first_error (_("invalid instruction shape"));
14725 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14726 means the Q bit should be set). */
14729 neon_quad (enum neon_shape shape
)
14731 return neon_shape_class
[shape
] == SC_QUAD
;
14735 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14738 /* Allow modification to be made to types which are constrained to be
14739 based on the key element, based on bits set alongside N_EQK. */
14740 if ((typebits
& N_EQK
) != 0)
14742 if ((typebits
& N_HLF
) != 0)
14744 else if ((typebits
& N_DBL
) != 0)
14746 if ((typebits
& N_SGN
) != 0)
14747 *g_type
= NT_signed
;
14748 else if ((typebits
& N_UNS
) != 0)
14749 *g_type
= NT_unsigned
;
14750 else if ((typebits
& N_INT
) != 0)
14751 *g_type
= NT_integer
;
14752 else if ((typebits
& N_FLT
) != 0)
14753 *g_type
= NT_float
;
14754 else if ((typebits
& N_SIZ
) != 0)
14755 *g_type
= NT_untyped
;
14759 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14760 operand type, i.e. the single type specified in a Neon instruction when it
14761 is the only one given. */
14763 static struct neon_type_el
14764 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14766 struct neon_type_el dest
= *key
;
14768 gas_assert ((thisarg
& N_EQK
) != 0);
14770 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14775 /* Convert Neon type and size into compact bitmask representation. */
14777 static enum neon_type_mask
14778 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14785 case 8: return N_8
;
14786 case 16: return N_16
;
14787 case 32: return N_32
;
14788 case 64: return N_64
;
14796 case 8: return N_I8
;
14797 case 16: return N_I16
;
14798 case 32: return N_I32
;
14799 case 64: return N_I64
;
14807 case 16: return N_F16
;
14808 case 32: return N_F32
;
14809 case 64: return N_F64
;
14817 case 8: return N_P8
;
14818 case 16: return N_P16
;
14819 case 64: return N_P64
;
14827 case 8: return N_S8
;
14828 case 16: return N_S16
;
14829 case 32: return N_S32
;
14830 case 64: return N_S64
;
14838 case 8: return N_U8
;
14839 case 16: return N_U16
;
14840 case 32: return N_U32
;
14841 case 64: return N_U64
;
14852 /* Convert compact Neon bitmask type representation to a type and size. Only
14853 handles the case where a single bit is set in the mask. */
14856 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14857 enum neon_type_mask mask
)
14859 if ((mask
& N_EQK
) != 0)
14862 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14864 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14866 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14868 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14873 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14875 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14876 *type
= NT_unsigned
;
14877 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14878 *type
= NT_integer
;
14879 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14880 *type
= NT_untyped
;
14881 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14883 else if ((mask
& (N_F_ALL
)) != 0)
14891 /* Modify a bitmask of allowed types. This is only needed for type
14895 modify_types_allowed (unsigned allowed
, unsigned mods
)
14898 enum neon_el_type type
;
14904 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14906 if (el_type_of_type_chk (&type
, &size
,
14907 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14909 neon_modify_type_size (mods
, &type
, &size
);
14910 destmask
|= type_chk_of_el_type (type
, size
);
14917 /* Check type and return type classification.
14918 The manual states (paraphrase): If one datatype is given, it indicates the
14920 - the second operand, if there is one
14921 - the operand, if there is no second operand
14922 - the result, if there are no operands.
14923 This isn't quite good enough though, so we use a concept of a "key" datatype
14924 which is set on a per-instruction basis, which is the one which matters when
14925 only one data type is written.
14926 Note: this function has side-effects (e.g. filling in missing operands). All
14927 Neon instructions should call it before performing bit encoding. */
14929 static struct neon_type_el
14930 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14933 unsigned i
, pass
, key_el
= 0;
14934 unsigned types
[NEON_MAX_TYPE_ELS
];
14935 enum neon_el_type k_type
= NT_invtype
;
14936 unsigned k_size
= -1u;
14937 struct neon_type_el badtype
= {NT_invtype
, -1};
14938 unsigned key_allowed
= 0;
14940 /* Optional registers in Neon instructions are always (not) in operand 1.
14941 Fill in the missing operand here, if it was omitted. */
14942 if (els
> 1 && !inst
.operands
[1].present
)
14943 inst
.operands
[1] = inst
.operands
[0];
14945 /* Suck up all the varargs. */
14947 for (i
= 0; i
< els
; i
++)
14949 unsigned thisarg
= va_arg (ap
, unsigned);
14950 if (thisarg
== N_IGNORE_TYPE
)
14955 types
[i
] = thisarg
;
14956 if ((thisarg
& N_KEY
) != 0)
14961 if (inst
.vectype
.elems
> 0)
14962 for (i
= 0; i
< els
; i
++)
14963 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14965 first_error (_("types specified in both the mnemonic and operands"));
14969 /* Duplicate inst.vectype elements here as necessary.
14970 FIXME: No idea if this is exactly the same as the ARM assembler,
14971 particularly when an insn takes one register and one non-register
14973 if (inst
.vectype
.elems
== 1 && els
> 1)
14976 inst
.vectype
.elems
= els
;
14977 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14978 for (j
= 0; j
< els
; j
++)
14980 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14983 else if (inst
.vectype
.elems
== 0 && els
> 0)
14986 /* No types were given after the mnemonic, so look for types specified
14987 after each operand. We allow some flexibility here; as long as the
14988 "key" operand has a type, we can infer the others. */
14989 for (j
= 0; j
< els
; j
++)
14990 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14991 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14993 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14995 for (j
= 0; j
< els
; j
++)
14996 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14997 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15002 first_error (_("operand types can't be inferred"));
15006 else if (inst
.vectype
.elems
!= els
)
15008 first_error (_("type specifier has the wrong number of parts"));
15012 for (pass
= 0; pass
< 2; pass
++)
15014 for (i
= 0; i
< els
; i
++)
15016 unsigned thisarg
= types
[i
];
15017 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15018 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15019 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15020 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15022 /* Decay more-specific signed & unsigned types to sign-insensitive
15023 integer types if sign-specific variants are unavailable. */
15024 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15025 && (types_allowed
& N_SU_ALL
) == 0)
15026 g_type
= NT_integer
;
15028 /* If only untyped args are allowed, decay any more specific types to
15029 them. Some instructions only care about signs for some element
15030 sizes, so handle that properly. */
15031 if (((types_allowed
& N_UNT
) == 0)
15032 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15033 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15034 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15035 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15036 g_type
= NT_untyped
;
15040 if ((thisarg
& N_KEY
) != 0)
15044 key_allowed
= thisarg
& ~N_KEY
;
15046 /* Check architecture constraint on FP16 extension. */
15048 && k_type
== NT_float
15049 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15051 inst
.error
= _(BAD_FP16
);
15058 if ((thisarg
& N_VFP
) != 0)
15060 enum neon_shape_el regshape
;
15061 unsigned regwidth
, match
;
15063 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15066 first_error (_("invalid instruction shape"));
15069 regshape
= neon_shape_tab
[ns
].el
[i
];
15070 regwidth
= neon_shape_el_size
[regshape
];
15072 /* In VFP mode, operands must match register widths. If we
15073 have a key operand, use its width, else use the width of
15074 the current operand. */
15080 /* FP16 will use a single precision register. */
15081 if (regwidth
== 32 && match
== 16)
15083 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15087 inst
.error
= _(BAD_FP16
);
15092 if (regwidth
!= match
)
15094 first_error (_("operand size must match register width"));
15099 if ((thisarg
& N_EQK
) == 0)
15101 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15103 if ((given_type
& types_allowed
) == 0)
15105 first_error (BAD_SIMD_TYPE
);
15111 enum neon_el_type mod_k_type
= k_type
;
15112 unsigned mod_k_size
= k_size
;
15113 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15114 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15116 first_error (_("inconsistent types in Neon instruction"));
15124 return inst
.vectype
.el
[key_el
];
15127 /* Neon-style VFP instruction forwarding. */
15129 /* Thumb VFP instructions have 0xE in the condition field. */
15132 do_vfp_cond_or_thumb (void)
15137 inst
.instruction
|= 0xe0000000;
15139 inst
.instruction
|= inst
.cond
<< 28;
15142 /* Look up and encode a simple mnemonic, for use as a helper function for the
15143 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15144 etc. It is assumed that operand parsing has already been done, and that the
15145 operands are in the form expected by the given opcode (this isn't necessarily
15146 the same as the form in which they were parsed, hence some massaging must
15147 take place before this function is called).
15148 Checks current arch version against that in the looked-up opcode. */
15151 do_vfp_nsyn_opcode (const char *opname
)
15153 const struct asm_opcode
*opcode
;
15155 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15161 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15168 inst
.instruction
= opcode
->tvalue
;
15169 opcode
->tencode ();
15173 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15174 opcode
->aencode ();
15179 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15181 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15183 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15186 do_vfp_nsyn_opcode ("fadds");
15188 do_vfp_nsyn_opcode ("fsubs");
15190 /* ARMv8.2 fp16 instruction. */
15192 do_scalar_fp16_v82_encode ();
15197 do_vfp_nsyn_opcode ("faddd");
15199 do_vfp_nsyn_opcode ("fsubd");
15203 /* Check operand types to see if this is a VFP instruction, and if so call
15207 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15209 enum neon_shape rs
;
15210 struct neon_type_el et
;
15215 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15216 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15220 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15221 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15222 N_F_ALL
| N_KEY
| N_VFP
);
15229 if (et
.type
!= NT_invtype
)
15240 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15242 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15244 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15247 do_vfp_nsyn_opcode ("fmacs");
15249 do_vfp_nsyn_opcode ("fnmacs");
15251 /* ARMv8.2 fp16 instruction. */
15253 do_scalar_fp16_v82_encode ();
15258 do_vfp_nsyn_opcode ("fmacd");
15260 do_vfp_nsyn_opcode ("fnmacd");
15265 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15267 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15269 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15272 do_vfp_nsyn_opcode ("ffmas");
15274 do_vfp_nsyn_opcode ("ffnmas");
15276 /* ARMv8.2 fp16 instruction. */
15278 do_scalar_fp16_v82_encode ();
15283 do_vfp_nsyn_opcode ("ffmad");
15285 do_vfp_nsyn_opcode ("ffnmad");
15290 do_vfp_nsyn_mul (enum neon_shape rs
)
15292 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15294 do_vfp_nsyn_opcode ("fmuls");
15296 /* ARMv8.2 fp16 instruction. */
15298 do_scalar_fp16_v82_encode ();
15301 do_vfp_nsyn_opcode ("fmuld");
15305 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15307 int is_neg
= (inst
.instruction
& 0x80) != 0;
15308 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15310 if (rs
== NS_FF
|| rs
== NS_HH
)
15313 do_vfp_nsyn_opcode ("fnegs");
15315 do_vfp_nsyn_opcode ("fabss");
15317 /* ARMv8.2 fp16 instruction. */
15319 do_scalar_fp16_v82_encode ();
15324 do_vfp_nsyn_opcode ("fnegd");
15326 do_vfp_nsyn_opcode ("fabsd");
15330 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15331 insns belong to Neon, and are handled elsewhere. */
15334 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15336 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15340 do_vfp_nsyn_opcode ("fldmdbs");
15342 do_vfp_nsyn_opcode ("fldmias");
15347 do_vfp_nsyn_opcode ("fstmdbs");
15349 do_vfp_nsyn_opcode ("fstmias");
15354 do_vfp_nsyn_sqrt (void)
15356 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15357 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15359 if (rs
== NS_FF
|| rs
== NS_HH
)
15361 do_vfp_nsyn_opcode ("fsqrts");
15363 /* ARMv8.2 fp16 instruction. */
15365 do_scalar_fp16_v82_encode ();
15368 do_vfp_nsyn_opcode ("fsqrtd");
15372 do_vfp_nsyn_div (void)
15374 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15375 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15376 N_F_ALL
| N_KEY
| N_VFP
);
15378 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15380 do_vfp_nsyn_opcode ("fdivs");
15382 /* ARMv8.2 fp16 instruction. */
15384 do_scalar_fp16_v82_encode ();
15387 do_vfp_nsyn_opcode ("fdivd");
15391 do_vfp_nsyn_nmul (void)
15393 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15394 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15395 N_F_ALL
| N_KEY
| N_VFP
);
15397 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15399 NEON_ENCODE (SINGLE
, inst
);
15400 do_vfp_sp_dyadic ();
15402 /* ARMv8.2 fp16 instruction. */
15404 do_scalar_fp16_v82_encode ();
15408 NEON_ENCODE (DOUBLE
, inst
);
15409 do_vfp_dp_rd_rn_rm ();
15411 do_vfp_cond_or_thumb ();
15415 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15419 neon_logbits (unsigned x
)
15421 return ffs (x
) - 4;
15424 #define LOW4(R) ((R) & 0xf)
15425 #define HI1(R) (((R) >> 4) & 1)
15428 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15433 first_error (BAD_EL_TYPE
);
15436 switch (inst
.operands
[0].imm
)
15439 first_error (_("invalid condition"));
15461 /* only accept eq and ne. */
15462 if (inst
.operands
[0].imm
> 1)
15464 first_error (_("invalid condition"));
15467 return inst
.operands
[0].imm
;
15469 if (inst
.operands
[0].imm
== 0x2)
15471 else if (inst
.operands
[0].imm
== 0x8)
15475 first_error (_("invalid condition"));
15479 switch (inst
.operands
[0].imm
)
15482 first_error (_("invalid condition"));
15498 /* Should be unreachable. */
15505 /* We are dealing with a vector predicated block. */
15506 if (inst
.operands
[0].present
)
15508 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15509 struct neon_type_el et
15510 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15513 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15515 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15517 if (et
.type
== NT_invtype
)
15520 if (et
.type
== NT_float
)
15522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15524 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15525 inst
.instruction
|= (et
.size
== 16) << 28;
15526 inst
.instruction
|= 0x3 << 20;
15530 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15532 inst
.instruction
|= 1 << 28;
15533 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15536 if (inst
.operands
[2].isquad
)
15538 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15539 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15540 inst
.instruction
|= (fcond
& 0x2) >> 1;
15544 if (inst
.operands
[2].reg
== REG_SP
)
15545 as_tsktsk (MVE_BAD_SP
);
15546 inst
.instruction
|= 1 << 6;
15547 inst
.instruction
|= (fcond
& 0x2) << 4;
15548 inst
.instruction
|= inst
.operands
[2].reg
;
15550 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15551 inst
.instruction
|= (fcond
& 0x4) << 10;
15552 inst
.instruction
|= (fcond
& 0x1) << 7;
15555 set_pred_insn_type (VPT_INSN
);
15557 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15558 | ((inst
.instruction
& 0xe000) >> 13);
15559 now_pred
.warn_deprecated
= FALSE
;
15560 now_pred
.type
= VECTOR_PRED
;
15567 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15568 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15569 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15570 if (!inst
.operands
[2].present
)
15571 first_error (_("MVE vector or ARM register expected"));
15572 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15574 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15575 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15576 && inst
.operands
[1].isquad
)
15578 inst
.instruction
= N_MNEM_vcmp
;
15582 if (inst
.cond
> COND_ALWAYS
)
15583 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15585 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15587 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15588 struct neon_type_el et
15589 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15592 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15593 && !inst
.operands
[2].iszr
, BAD_PC
);
15595 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15597 inst
.instruction
= 0xee010f00;
15598 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15599 inst
.instruction
|= (fcond
& 0x4) << 10;
15600 inst
.instruction
|= (fcond
& 0x1) << 7;
15601 if (et
.type
== NT_float
)
15603 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15605 inst
.instruction
|= (et
.size
== 16) << 28;
15606 inst
.instruction
|= 0x3 << 20;
15610 inst
.instruction
|= 1 << 28;
15611 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15613 if (inst
.operands
[2].isquad
)
15615 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15616 inst
.instruction
|= (fcond
& 0x2) >> 1;
15617 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15621 if (inst
.operands
[2].reg
== REG_SP
)
15622 as_tsktsk (MVE_BAD_SP
);
15623 inst
.instruction
|= 1 << 6;
15624 inst
.instruction
|= (fcond
& 0x2) << 4;
15625 inst
.instruction
|= inst
.operands
[2].reg
;
15633 do_mve_vmaxa_vmina (void)
15635 if (inst
.cond
> COND_ALWAYS
)
15636 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15638 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15640 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15641 struct neon_type_el et
15642 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15644 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15645 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15646 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15647 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15648 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15653 do_mve_vfmas (void)
15655 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15656 struct neon_type_el et
15657 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15659 if (inst
.cond
> COND_ALWAYS
)
15660 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15662 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15664 if (inst
.operands
[2].reg
== REG_SP
)
15665 as_tsktsk (MVE_BAD_SP
);
15666 else if (inst
.operands
[2].reg
== REG_PC
)
15667 as_tsktsk (MVE_BAD_PC
);
15669 inst
.instruction
|= (et
.size
== 16) << 28;
15670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15672 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15673 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15674 inst
.instruction
|= inst
.operands
[2].reg
;
15679 do_mve_viddup (void)
15681 if (inst
.cond
> COND_ALWAYS
)
15682 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15684 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15686 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15687 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15688 _("immediate must be either 1, 2, 4 or 8"));
15690 enum neon_shape rs
;
15691 struct neon_type_el et
;
15693 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15695 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15696 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15701 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15702 if (inst
.operands
[2].reg
== REG_SP
)
15703 as_tsktsk (MVE_BAD_SP
);
15704 else if (inst
.operands
[2].reg
== REG_PC
)
15705 first_error (BAD_PC
);
15707 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15708 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15709 Rm
= inst
.operands
[2].reg
>> 1;
15711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15712 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15713 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15714 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15715 inst
.instruction
|= (imm
> 2) << 7;
15716 inst
.instruction
|= Rm
<< 1;
15717 inst
.instruction
|= (imm
== 2 || imm
== 8);
15722 do_mve_vmlas (void)
15724 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15725 struct neon_type_el et
15726 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15728 if (inst
.operands
[2].reg
== REG_PC
)
15729 as_tsktsk (MVE_BAD_PC
);
15730 else if (inst
.operands
[2].reg
== REG_SP
)
15731 as_tsktsk (MVE_BAD_SP
);
15733 if (inst
.cond
> COND_ALWAYS
)
15734 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15736 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15738 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15740 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15741 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15742 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15743 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15744 inst
.instruction
|= inst
.operands
[2].reg
;
15749 do_mve_vshll (void)
15751 struct neon_type_el et
15752 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15754 if (inst
.cond
> COND_ALWAYS
)
15755 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15757 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15759 int imm
= inst
.operands
[2].imm
;
15760 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15761 _("immediate value out of range"));
15763 if ((unsigned)imm
== et
.size
)
15765 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15766 inst
.instruction
|= 0x110001;
15770 inst
.instruction
|= (et
.size
+ imm
) << 16;
15771 inst
.instruction
|= 0x800140;
15774 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15776 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15778 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15783 do_mve_vshlc (void)
15785 if (inst
.cond
> COND_ALWAYS
)
15786 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15788 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15790 if (inst
.operands
[1].reg
== REG_PC
)
15791 as_tsktsk (MVE_BAD_PC
);
15792 else if (inst
.operands
[1].reg
== REG_SP
)
15793 as_tsktsk (MVE_BAD_SP
);
15795 int imm
= inst
.operands
[2].imm
;
15796 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15799 inst
.instruction
|= (imm
& 0x1f) << 16;
15800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15801 inst
.instruction
|= inst
.operands
[1].reg
;
15806 do_mve_vshrn (void)
15809 switch (inst
.instruction
)
15811 case M_MNEM_vshrnt
:
15812 case M_MNEM_vshrnb
:
15813 case M_MNEM_vrshrnt
:
15814 case M_MNEM_vrshrnb
:
15815 types
= N_I16
| N_I32
;
15817 case M_MNEM_vqshrnt
:
15818 case M_MNEM_vqshrnb
:
15819 case M_MNEM_vqrshrnt
:
15820 case M_MNEM_vqrshrnb
:
15821 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15823 case M_MNEM_vqshrunt
:
15824 case M_MNEM_vqshrunb
:
15825 case M_MNEM_vqrshrunt
:
15826 case M_MNEM_vqrshrunb
:
15827 types
= N_S16
| N_S32
;
15833 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15835 if (inst
.cond
> COND_ALWAYS
)
15836 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15838 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15840 unsigned Qd
= inst
.operands
[0].reg
;
15841 unsigned Qm
= inst
.operands
[1].reg
;
15842 unsigned imm
= inst
.operands
[2].imm
;
15843 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15845 ? _("immediate operand expected in the range [1,8]")
15846 : _("immediate operand expected in the range [1,16]"));
15848 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15849 inst
.instruction
|= HI1 (Qd
) << 22;
15850 inst
.instruction
|= (et
.size
- imm
) << 16;
15851 inst
.instruction
|= LOW4 (Qd
) << 12;
15852 inst
.instruction
|= HI1 (Qm
) << 5;
15853 inst
.instruction
|= LOW4 (Qm
);
15858 do_mve_vqmovn (void)
15860 struct neon_type_el et
;
15861 if (inst
.instruction
== M_MNEM_vqmovnt
15862 || inst
.instruction
== M_MNEM_vqmovnb
)
15863 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15864 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15866 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15868 if (inst
.cond
> COND_ALWAYS
)
15869 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15871 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15873 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15875 inst
.instruction
|= (et
.size
== 32) << 18;
15876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15877 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15878 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15883 do_mve_vpsel (void)
15885 neon_select_shape (NS_QQQ
, NS_NULL
);
15887 if (inst
.cond
> COND_ALWAYS
)
15888 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15890 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15892 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15893 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15894 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15895 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15896 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15897 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15902 do_mve_vpnot (void)
15904 if (inst
.cond
> COND_ALWAYS
)
15905 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15907 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15911 do_mve_vmaxnma_vminnma (void)
15913 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15914 struct neon_type_el et
15915 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15917 if (inst
.cond
> COND_ALWAYS
)
15918 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15920 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15922 inst
.instruction
|= (et
.size
== 16) << 28;
15923 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15925 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15931 do_mve_vcmul (void)
15933 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15934 struct neon_type_el et
15935 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15937 if (inst
.cond
> COND_ALWAYS
)
15938 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15940 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15942 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15943 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15944 _("immediate out of range"));
15946 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15947 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15948 as_tsktsk (BAD_MVE_SRCDEST
);
15950 inst
.instruction
|= (et
.size
== 32) << 28;
15951 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15952 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15953 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15954 inst
.instruction
|= (rot
> 90) << 12;
15955 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15956 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15957 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15958 inst
.instruction
|= (rot
== 90 || rot
== 270);
15962 /* To handle the Low Overhead Loop instructions
15963 in Armv8.1-M Mainline and MVE. */
15967 unsigned long insn
= inst
.instruction
;
15969 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
15971 if (insn
== T_MNEM_lctp
)
15974 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
15976 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
15978 struct neon_type_el et
15979 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15980 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15987 constraint (!inst
.operands
[0].present
,
15989 /* fall through. */
15992 if (!inst
.operands
[0].present
)
15993 inst
.instruction
|= 1 << 21;
15995 v8_1_loop_reloc (TRUE
);
16000 v8_1_loop_reloc (FALSE
);
16001 /* fall through. */
16004 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16006 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16007 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16008 else if (inst
.operands
[1].reg
== REG_PC
)
16009 as_tsktsk (MVE_BAD_PC
);
16010 if (inst
.operands
[1].reg
== REG_SP
)
16011 as_tsktsk (MVE_BAD_SP
);
16013 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16023 do_vfp_nsyn_cmp (void)
16025 enum neon_shape rs
;
16026 if (!inst
.operands
[0].isreg
)
16033 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16038 if (inst
.operands
[1].isreg
)
16040 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16041 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16043 if (rs
== NS_FF
|| rs
== NS_HH
)
16045 NEON_ENCODE (SINGLE
, inst
);
16046 do_vfp_sp_monadic ();
16050 NEON_ENCODE (DOUBLE
, inst
);
16051 do_vfp_dp_rd_rm ();
16056 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16057 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16059 switch (inst
.instruction
& 0x0fffffff)
16062 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16065 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16071 if (rs
== NS_FI
|| rs
== NS_HI
)
16073 NEON_ENCODE (SINGLE
, inst
);
16074 do_vfp_sp_compare_z ();
16078 NEON_ENCODE (DOUBLE
, inst
);
16082 do_vfp_cond_or_thumb ();
16084 /* ARMv8.2 fp16 instruction. */
16085 if (rs
== NS_HI
|| rs
== NS_HH
)
16086 do_scalar_fp16_v82_encode ();
16090 nsyn_insert_sp (void)
16092 inst
.operands
[1] = inst
.operands
[0];
16093 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16094 inst
.operands
[0].reg
= REG_SP
;
16095 inst
.operands
[0].isreg
= 1;
16096 inst
.operands
[0].writeback
= 1;
16097 inst
.operands
[0].present
= 1;
16101 do_vfp_nsyn_push (void)
16105 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16106 _("register list must contain at least 1 and at most 16 "
16109 if (inst
.operands
[1].issingle
)
16110 do_vfp_nsyn_opcode ("fstmdbs");
16112 do_vfp_nsyn_opcode ("fstmdbd");
16116 do_vfp_nsyn_pop (void)
16120 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16121 _("register list must contain at least 1 and at most 16 "
16124 if (inst
.operands
[1].issingle
)
16125 do_vfp_nsyn_opcode ("fldmias");
16127 do_vfp_nsyn_opcode ("fldmiad");
16130 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16131 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16134 neon_dp_fixup (struct arm_it
* insn
)
16136 unsigned int i
= insn
->instruction
;
16141 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16152 insn
->instruction
= i
;
16156 mve_encode_qqr (int size
, int U
, int fp
)
16158 if (inst
.operands
[2].reg
== REG_SP
)
16159 as_tsktsk (MVE_BAD_SP
);
16160 else if (inst
.operands
[2].reg
== REG_PC
)
16161 as_tsktsk (MVE_BAD_PC
);
16166 if (((unsigned)inst
.instruction
) == 0xd00)
16167 inst
.instruction
= 0xee300f40;
16169 else if (((unsigned)inst
.instruction
) == 0x200d00)
16170 inst
.instruction
= 0xee301f40;
16172 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16173 inst
.instruction
= 0xee310e60;
16175 /* Setting size which is 1 for F16 and 0 for F32. */
16176 inst
.instruction
|= (size
== 16) << 28;
16181 if (((unsigned)inst
.instruction
) == 0x800)
16182 inst
.instruction
= 0xee010f40;
16184 else if (((unsigned)inst
.instruction
) == 0x1000800)
16185 inst
.instruction
= 0xee011f40;
16187 else if (((unsigned)inst
.instruction
) == 0)
16188 inst
.instruction
= 0xee000f40;
16190 else if (((unsigned)inst
.instruction
) == 0x200)
16191 inst
.instruction
= 0xee001f40;
16193 else if (((unsigned)inst
.instruction
) == 0x900)
16194 inst
.instruction
= 0xee010e40;
16196 else if (((unsigned)inst
.instruction
) == 0x910)
16197 inst
.instruction
= 0xee011e60;
16199 else if (((unsigned)inst
.instruction
) == 0x10)
16200 inst
.instruction
= 0xee000f60;
16202 else if (((unsigned)inst
.instruction
) == 0x210)
16203 inst
.instruction
= 0xee001f60;
16205 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16206 inst
.instruction
= 0xee000e40;
16208 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16209 inst
.instruction
= 0xee010e60;
16211 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16212 inst
.instruction
= 0xfe010e60;
16215 inst
.instruction
|= U
<< 28;
16217 /* Setting bits for size. */
16218 inst
.instruction
|= neon_logbits (size
) << 20;
16220 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16221 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16222 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16223 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16224 inst
.instruction
|= inst
.operands
[2].reg
;
16229 mve_encode_rqq (unsigned bit28
, unsigned size
)
16231 inst
.instruction
|= bit28
<< 28;
16232 inst
.instruction
|= neon_logbits (size
) << 20;
16233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16235 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16236 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16237 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16242 mve_encode_qqq (int ubit
, int size
)
16245 inst
.instruction
|= (ubit
!= 0) << 28;
16246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16247 inst
.instruction
|= neon_logbits (size
) << 20;
16248 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16249 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16250 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16251 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16252 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16258 mve_encode_rq (unsigned bit28
, unsigned size
)
16260 inst
.instruction
|= bit28
<< 28;
16261 inst
.instruction
|= neon_logbits (size
) << 18;
16262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16263 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16268 mve_encode_rrqq (unsigned U
, unsigned size
)
16270 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16272 inst
.instruction
|= U
<< 28;
16273 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16274 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16275 inst
.instruction
|= (size
== 32) << 16;
16276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16277 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16278 inst
.instruction
|= inst
.operands
[3].reg
;
16282 /* Encode insns with bit pattern:
16284 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16285 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16287 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16288 different meaning for some instruction. */
16291 neon_three_same (int isquad
, int ubit
, int size
)
16293 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16294 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16295 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16296 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16297 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16298 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16299 inst
.instruction
|= (isquad
!= 0) << 6;
16300 inst
.instruction
|= (ubit
!= 0) << 24;
16302 inst
.instruction
|= neon_logbits (size
) << 20;
16304 neon_dp_fixup (&inst
);
16307 /* Encode instructions of the form:
16309 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16310 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16312 Don't write size if SIZE == -1. */
16315 neon_two_same (int qbit
, int ubit
, int size
)
16317 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16318 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16319 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16320 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16321 inst
.instruction
|= (qbit
!= 0) << 6;
16322 inst
.instruction
|= (ubit
!= 0) << 24;
16325 inst
.instruction
|= neon_logbits (size
) << 18;
16327 neon_dp_fixup (&inst
);
16330 enum vfp_or_neon_is_neon_bits
16333 NEON_CHECK_ARCH
= 2,
16334 NEON_CHECK_ARCH8
= 4
16337 /* Call this function if an instruction which may have belonged to the VFP or
16338 Neon instruction sets, but turned out to be a Neon instruction (due to the
16339 operand types involved, etc.). We have to check and/or fix-up a couple of
16342 - Make sure the user hasn't attempted to make a Neon instruction
16344 - Alter the value in the condition code field if necessary.
16345 - Make sure that the arch supports Neon instructions.
16347 Which of these operations take place depends on bits from enum
16348 vfp_or_neon_is_neon_bits.
16350 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16351 current instruction's condition is COND_ALWAYS, the condition field is
16352 changed to inst.uncond_value. This is necessary because instructions shared
16353 between VFP and Neon may be conditional for the VFP variants only, and the
16354 unconditional Neon version must have, e.g., 0xF in the condition field. */
16357 vfp_or_neon_is_neon (unsigned check
)
16359 /* Conditions are always legal in Thumb mode (IT blocks). */
16360 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16362 if (inst
.cond
!= COND_ALWAYS
)
16364 first_error (_(BAD_COND
));
16367 if (inst
.uncond_value
!= -1)
16368 inst
.instruction
|= inst
.uncond_value
<< 28;
16372 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16373 || ((check
& NEON_CHECK_ARCH8
)
16374 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16376 first_error (_(BAD_FPU
));
16384 /* Return TRUE if the SIMD instruction is available for the current
16385 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16386 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16387 vfp_or_neon_is_neon for the NEON specific checks. */
16390 check_simd_pred_availability (int fp
, unsigned check
)
16392 if (inst
.cond
> COND_ALWAYS
)
16394 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16396 inst
.error
= BAD_FPU
;
16399 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16401 else if (inst
.cond
< COND_ALWAYS
)
16403 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16404 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16405 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16410 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16411 && vfp_or_neon_is_neon (check
) == FAIL
)
16414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16415 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16420 /* Neon instruction encoders, in approximate order of appearance. */
16423 do_neon_dyadic_i_su (void)
16425 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16428 enum neon_shape rs
;
16429 struct neon_type_el et
;
16430 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16431 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16433 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16435 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16439 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16441 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16445 do_neon_dyadic_i64_su (void)
16447 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16449 enum neon_shape rs
;
16450 struct neon_type_el et
;
16451 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16453 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16454 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16458 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16459 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16462 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16464 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16468 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16471 unsigned size
= et
.size
>> 3;
16472 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16473 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16474 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16475 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16476 inst
.instruction
|= (isquad
!= 0) << 6;
16477 inst
.instruction
|= immbits
<< 16;
16478 inst
.instruction
|= (size
>> 3) << 7;
16479 inst
.instruction
|= (size
& 0x7) << 19;
16481 inst
.instruction
|= (uval
!= 0) << 24;
16483 neon_dp_fixup (&inst
);
16489 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16492 if (!inst
.operands
[2].isreg
)
16494 enum neon_shape rs
;
16495 struct neon_type_el et
;
16496 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16498 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16499 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16503 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16504 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16506 int imm
= inst
.operands
[2].imm
;
16508 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16509 _("immediate out of range for shift"));
16510 NEON_ENCODE (IMMED
, inst
);
16511 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16515 enum neon_shape rs
;
16516 struct neon_type_el et
;
16517 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16519 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16520 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16524 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16525 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16531 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16532 _("invalid instruction shape"));
16533 if (inst
.operands
[2].reg
== REG_SP
)
16534 as_tsktsk (MVE_BAD_SP
);
16535 else if (inst
.operands
[2].reg
== REG_PC
)
16536 as_tsktsk (MVE_BAD_PC
);
16538 inst
.instruction
= 0xee311e60;
16539 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16541 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16542 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16543 inst
.instruction
|= inst
.operands
[2].reg
;
16550 /* VSHL/VQSHL 3-register variants have syntax such as:
16552 whereas other 3-register operations encoded by neon_three_same have
16555 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16556 operands[2].reg here. */
16557 tmp
= inst
.operands
[2].reg
;
16558 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16559 inst
.operands
[1].reg
= tmp
;
16560 NEON_ENCODE (INTEGER
, inst
);
16561 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16567 do_neon_qshl (void)
16569 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16572 if (!inst
.operands
[2].isreg
)
16574 enum neon_shape rs
;
16575 struct neon_type_el et
;
16576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16578 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16579 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16583 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16584 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16586 int imm
= inst
.operands
[2].imm
;
16588 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16589 _("immediate out of range for shift"));
16590 NEON_ENCODE (IMMED
, inst
);
16591 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16595 enum neon_shape rs
;
16596 struct neon_type_el et
;
16598 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16600 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16601 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16605 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16606 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16611 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16612 _("invalid instruction shape"));
16613 if (inst
.operands
[2].reg
== REG_SP
)
16614 as_tsktsk (MVE_BAD_SP
);
16615 else if (inst
.operands
[2].reg
== REG_PC
)
16616 as_tsktsk (MVE_BAD_PC
);
16618 inst
.instruction
= 0xee311ee0;
16619 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16621 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16622 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16623 inst
.instruction
|= inst
.operands
[2].reg
;
16630 /* See note in do_neon_shl. */
16631 tmp
= inst
.operands
[2].reg
;
16632 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16633 inst
.operands
[1].reg
= tmp
;
16634 NEON_ENCODE (INTEGER
, inst
);
16635 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16641 do_neon_rshl (void)
16643 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16646 enum neon_shape rs
;
16647 struct neon_type_el et
;
16648 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16650 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16651 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16655 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16656 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16663 if (inst
.operands
[2].reg
== REG_PC
)
16664 as_tsktsk (MVE_BAD_PC
);
16665 else if (inst
.operands
[2].reg
== REG_SP
)
16666 as_tsktsk (MVE_BAD_SP
);
16668 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16669 _("invalid instruction shape"));
16671 if (inst
.instruction
== 0x0000510)
16672 /* We are dealing with vqrshl. */
16673 inst
.instruction
= 0xee331ee0;
16675 /* We are dealing with vrshl. */
16676 inst
.instruction
= 0xee331e60;
16678 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16679 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16680 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16681 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16682 inst
.instruction
|= inst
.operands
[2].reg
;
16687 tmp
= inst
.operands
[2].reg
;
16688 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16689 inst
.operands
[1].reg
= tmp
;
16690 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16695 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16697 /* Handle .I8 pseudo-instructions. */
16700 /* Unfortunately, this will make everything apart from zero out-of-range.
16701 FIXME is this the intended semantics? There doesn't seem much point in
16702 accepting .I8 if so. */
16703 immediate
|= immediate
<< 8;
16709 if (immediate
== (immediate
& 0x000000ff))
16711 *immbits
= immediate
;
16714 else if (immediate
== (immediate
& 0x0000ff00))
16716 *immbits
= immediate
>> 8;
16719 else if (immediate
== (immediate
& 0x00ff0000))
16721 *immbits
= immediate
>> 16;
16724 else if (immediate
== (immediate
& 0xff000000))
16726 *immbits
= immediate
>> 24;
16729 if ((immediate
& 0xffff) != (immediate
>> 16))
16730 goto bad_immediate
;
16731 immediate
&= 0xffff;
16734 if (immediate
== (immediate
& 0x000000ff))
16736 *immbits
= immediate
;
16739 else if (immediate
== (immediate
& 0x0000ff00))
16741 *immbits
= immediate
>> 8;
16746 first_error (_("immediate value out of range"));
16751 do_neon_logic (void)
16753 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16755 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16757 && !check_simd_pred_availability (FALSE
,
16758 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16760 else if (rs
!= NS_QQQ
16761 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16762 first_error (BAD_FPU
);
16764 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16765 /* U bit and size field were set as part of the bitmask. */
16766 NEON_ENCODE (INTEGER
, inst
);
16767 neon_three_same (neon_quad (rs
), 0, -1);
16771 const int three_ops_form
= (inst
.operands
[2].present
16772 && !inst
.operands
[2].isreg
);
16773 const int immoperand
= (three_ops_form
? 2 : 1);
16774 enum neon_shape rs
= (three_ops_form
16775 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16776 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16777 /* Because neon_select_shape makes the second operand a copy of the first
16778 if the second operand is not present. */
16780 && !check_simd_pred_availability (FALSE
,
16781 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16783 else if (rs
!= NS_QQI
16784 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16785 first_error (BAD_FPU
);
16787 struct neon_type_el et
;
16788 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16789 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16791 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16794 if (et
.type
== NT_invtype
)
16796 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16801 if (three_ops_form
)
16802 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16803 _("first and second operands shall be the same register"));
16805 NEON_ENCODE (IMMED
, inst
);
16807 immbits
= inst
.operands
[immoperand
].imm
;
16810 /* .i64 is a pseudo-op, so the immediate must be a repeating
16812 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16813 inst
.operands
[immoperand
].reg
: 0))
16815 /* Set immbits to an invalid constant. */
16816 immbits
= 0xdeadbeef;
16823 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16827 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16831 /* Pseudo-instruction for VBIC. */
16832 neon_invert_size (&immbits
, 0, et
.size
);
16833 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16837 /* Pseudo-instruction for VORR. */
16838 neon_invert_size (&immbits
, 0, et
.size
);
16839 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16849 inst
.instruction
|= neon_quad (rs
) << 6;
16850 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16851 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16852 inst
.instruction
|= cmode
<< 8;
16853 neon_write_immbits (immbits
);
16855 neon_dp_fixup (&inst
);
16860 do_neon_bitfield (void)
16862 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16863 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16864 neon_three_same (neon_quad (rs
), 0, -1);
16868 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16871 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16872 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16874 if (et
.type
== NT_float
)
16876 NEON_ENCODE (FLOAT
, inst
);
16878 mve_encode_qqr (et
.size
, 0, 1);
16880 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16884 NEON_ENCODE (INTEGER
, inst
);
16886 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16888 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16894 do_neon_dyadic_if_su_d (void)
16896 /* This version only allow D registers, but that constraint is enforced during
16897 operand parsing so we don't need to do anything extra here. */
16898 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16902 do_neon_dyadic_if_i_d (void)
16904 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16905 affected if we specify unsigned args. */
16906 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16910 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16912 constraint (size
< 32, BAD_ADDR_MODE
);
16913 constraint (size
!= elsize
, BAD_EL_TYPE
);
16914 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16915 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16916 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16917 _("destination register and offset register may not be the"
16920 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16927 constraint ((imm
% (size
/ 8) != 0)
16928 || imm
> (0x7f << neon_logbits (size
)),
16929 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16930 " range of +/-[0,508]")
16931 : _("immediate must be a multiple of 8 in the"
16932 " range of +/-[0,1016]"));
16933 inst
.instruction
|= 0x11 << 24;
16934 inst
.instruction
|= add
<< 23;
16935 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16936 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16937 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16938 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16939 inst
.instruction
|= 1 << 12;
16940 inst
.instruction
|= (size
== 64) << 8;
16941 inst
.instruction
&= 0xffffff00;
16942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16943 inst
.instruction
|= imm
>> neon_logbits (size
);
16947 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16949 unsigned os
= inst
.operands
[1].imm
>> 5;
16950 constraint (os
!= 0 && size
== 8,
16951 _("can not shift offsets when accessing less than half-word"));
16952 constraint (os
&& os
!= neon_logbits (size
),
16953 _("shift immediate must be 1, 2 or 3 for half-word, word"
16954 " or double-word accesses respectively"));
16955 if (inst
.operands
[1].reg
== REG_PC
)
16956 as_tsktsk (MVE_BAD_PC
);
16961 constraint (elsize
>= 64, BAD_EL_TYPE
);
16964 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16968 constraint (elsize
!= size
, BAD_EL_TYPE
);
16973 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16977 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16978 _("destination register and offset register may not be"
16980 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16982 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16983 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16984 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16988 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16991 inst
.instruction
|= 1 << 23;
16992 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16993 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16994 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16995 inst
.instruction
|= neon_logbits (elsize
) << 7;
16996 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16997 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16998 inst
.instruction
|= !!os
;
17002 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17004 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17006 constraint (size
>= 64, BAD_ADDR_MODE
);
17010 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17013 constraint (elsize
!= size
, BAD_EL_TYPE
);
17020 constraint (elsize
!= size
&& type
!= NT_unsigned
17021 && type
!= NT_signed
, BAD_EL_TYPE
);
17025 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17028 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17036 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17041 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17044 constraint (1, _("immediate must be a multiple of 2 in the"
17045 " range of +/-[0,254]"));
17048 constraint (1, _("immediate must be a multiple of 4 in the"
17049 " range of +/-[0,508]"));
17054 if (size
!= elsize
)
17056 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17057 constraint (inst
.operands
[0].reg
> 14,
17058 _("MVE vector register in the range [Q0..Q7] expected"));
17059 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17060 inst
.instruction
|= (size
== 16) << 19;
17061 inst
.instruction
|= neon_logbits (elsize
) << 7;
17065 if (inst
.operands
[1].reg
== REG_PC
)
17066 as_tsktsk (MVE_BAD_PC
);
17067 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17068 as_tsktsk (MVE_BAD_SP
);
17069 inst
.instruction
|= 1 << 12;
17070 inst
.instruction
|= neon_logbits (size
) << 7;
17072 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17073 inst
.instruction
|= add
<< 23;
17074 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17075 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17077 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17078 inst
.instruction
&= 0xffffff80;
17079 inst
.instruction
|= imm
>> neon_logbits (size
);
17084 do_mve_vstr_vldr (void)
17089 if (inst
.cond
> COND_ALWAYS
)
17090 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17092 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17094 switch (inst
.instruction
)
17101 /* fall through. */
17107 /* fall through. */
17113 /* fall through. */
17119 /* fall through. */
17124 unsigned elsize
= inst
.vectype
.el
[0].size
;
17126 if (inst
.operands
[1].isquad
)
17128 /* We are dealing with [Q, imm]{!} cases. */
17129 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17133 if (inst
.operands
[1].immisreg
== 2)
17135 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17136 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17138 else if (!inst
.operands
[1].immisreg
)
17140 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17141 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17144 constraint (1, BAD_ADDR_MODE
);
17151 do_mve_vst_vld (void)
17153 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17156 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17157 || inst
.relocs
[0].exp
.X_add_number
!= 0
17158 || inst
.operands
[1].immisreg
!= 0,
17160 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17161 if (inst
.operands
[1].reg
== REG_PC
)
17162 as_tsktsk (MVE_BAD_PC
);
17163 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17164 as_tsktsk (MVE_BAD_SP
);
17167 /* These instructions are one of the "exceptions" mentioned in
17168 handle_pred_state. They are MVE instructions that are not VPT compatible
17169 and do not accept a VPT code, thus appending such a code is a syntax
17171 if (inst
.cond
> COND_ALWAYS
)
17172 first_error (BAD_SYNTAX
);
17173 /* If we append a scalar condition code we can set this to
17174 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17175 else if (inst
.cond
< COND_ALWAYS
)
17176 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17178 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17180 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17181 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17182 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17183 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17184 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17189 do_mve_vaddlv (void)
17191 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17192 struct neon_type_el et
17193 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17195 if (et
.type
== NT_invtype
)
17196 first_error (BAD_EL_TYPE
);
17198 if (inst
.cond
> COND_ALWAYS
)
17199 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17201 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17203 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17205 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17206 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17207 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17208 inst
.instruction
|= inst
.operands
[2].reg
;
17213 do_neon_dyadic_if_su (void)
17215 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17216 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17219 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17220 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17221 && et
.type
== NT_float
17222 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17224 if (!check_simd_pred_availability (et
.type
== NT_float
,
17225 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17228 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17232 do_neon_addsub_if_i (void)
17234 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17235 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17239 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17240 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17242 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17243 /* If we are parsing Q registers and the element types match MVE, which NEON
17244 also supports, then we must check whether this is an instruction that can
17245 be used by both MVE/NEON. This distinction can be made based on whether
17246 they are predicated or not. */
17247 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17249 if (!check_simd_pred_availability (et
.type
== NT_float
,
17250 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17255 /* If they are either in a D register or are using an unsupported. */
17257 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17261 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17262 affected if we specify unsigned args. */
17263 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17266 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17268 V<op> A,B (A is operand 0, B is operand 2)
17273 so handle that case specially. */
17276 neon_exchange_operands (void)
17278 if (inst
.operands
[1].present
)
17280 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17282 /* Swap operands[1] and operands[2]. */
17283 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17284 inst
.operands
[1] = inst
.operands
[2];
17285 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17290 inst
.operands
[1] = inst
.operands
[2];
17291 inst
.operands
[2] = inst
.operands
[0];
17296 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17298 if (inst
.operands
[2].isreg
)
17301 neon_exchange_operands ();
17302 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17306 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17307 struct neon_type_el et
= neon_check_type (2, rs
,
17308 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17310 NEON_ENCODE (IMMED
, inst
);
17311 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17312 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17313 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17314 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17315 inst
.instruction
|= neon_quad (rs
) << 6;
17316 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17317 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17319 neon_dp_fixup (&inst
);
17326 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17330 do_neon_cmp_inv (void)
17332 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17338 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17341 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17342 scalars, which are encoded in 5 bits, M : Rm.
17343 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17344 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17347 Dot Product instructions are similar to multiply instructions except elsize
17348 should always be 32.
17350 This function translates SCALAR, which is GAS's internal encoding of indexed
17351 scalar register, to raw encoding. There is also register and index range
17352 check based on ELSIZE. */
17355 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17357 unsigned regno
= NEON_SCALAR_REG (scalar
);
17358 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17363 if (regno
> 7 || elno
> 3)
17365 return regno
| (elno
<< 3);
17368 if (regno
> 15 || elno
> 1)
17370 return regno
| (elno
<< 4);
17374 first_error (_("scalar out of range for multiply instruction"));
17380 /* Encode multiply / multiply-accumulate scalar instructions. */
17383 neon_mul_mac (struct neon_type_el et
, int ubit
)
17387 /* Give a more helpful error message if we have an invalid type. */
17388 if (et
.type
== NT_invtype
)
17391 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17392 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17393 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17394 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17395 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17396 inst
.instruction
|= LOW4 (scalar
);
17397 inst
.instruction
|= HI1 (scalar
) << 5;
17398 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17399 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17400 inst
.instruction
|= (ubit
!= 0) << 24;
17402 neon_dp_fixup (&inst
);
17406 do_neon_mac_maybe_scalar (void)
17408 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17411 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17414 if (inst
.operands
[2].isscalar
)
17416 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17417 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17418 struct neon_type_el et
= neon_check_type (3, rs
,
17419 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17420 NEON_ENCODE (SCALAR
, inst
);
17421 neon_mul_mac (et
, neon_quad (rs
));
17423 else if (!inst
.operands
[2].isvec
)
17425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17427 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17428 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17430 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17434 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17435 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17436 affected if we specify unsigned args. */
17437 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17442 do_neon_fmac (void)
17444 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17445 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17448 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17451 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17453 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17454 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17459 if (inst
.operands
[2].reg
== REG_SP
)
17460 as_tsktsk (MVE_BAD_SP
);
17461 else if (inst
.operands
[2].reg
== REG_PC
)
17462 as_tsktsk (MVE_BAD_PC
);
17464 inst
.instruction
= 0xee310e40;
17465 inst
.instruction
|= (et
.size
== 16) << 28;
17466 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17467 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17468 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17469 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17470 inst
.instruction
|= inst
.operands
[2].reg
;
17477 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17480 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17486 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17487 struct neon_type_el et
= neon_check_type (3, rs
,
17488 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17489 neon_three_same (neon_quad (rs
), 0, et
.size
);
17492 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17493 same types as the MAC equivalents. The polynomial type for this instruction
17494 is encoded the same as the integer type. */
17499 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17502 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17505 if (inst
.operands
[2].isscalar
)
17507 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17508 do_neon_mac_maybe_scalar ();
17512 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17514 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17515 struct neon_type_el et
17516 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17517 if (et
.type
== NT_float
)
17518 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17521 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17525 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17526 neon_dyadic_misc (NT_poly
,
17527 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17533 do_neon_qdmulh (void)
17535 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17538 if (inst
.operands
[2].isscalar
)
17540 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17541 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17542 struct neon_type_el et
= neon_check_type (3, rs
,
17543 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17544 NEON_ENCODE (SCALAR
, inst
);
17545 neon_mul_mac (et
, neon_quad (rs
));
17549 enum neon_shape rs
;
17550 struct neon_type_el et
;
17551 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17553 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17554 et
= neon_check_type (3, rs
,
17555 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17559 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17560 et
= neon_check_type (3, rs
,
17561 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17564 NEON_ENCODE (INTEGER
, inst
);
17566 mve_encode_qqr (et
.size
, 0, 0);
17568 /* The U bit (rounding) comes from bit mask. */
17569 neon_three_same (neon_quad (rs
), 0, et
.size
);
17574 do_mve_vaddv (void)
17576 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17577 struct neon_type_el et
17578 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17580 if (et
.type
== NT_invtype
)
17581 first_error (BAD_EL_TYPE
);
17583 if (inst
.cond
> COND_ALWAYS
)
17584 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17586 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17588 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17590 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17594 do_mve_vhcadd (void)
17596 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17597 struct neon_type_el et
17598 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17600 if (inst
.cond
> COND_ALWAYS
)
17601 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17603 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17605 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17606 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17608 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17609 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17610 "operand makes instruction UNPREDICTABLE"));
17612 mve_encode_qqq (0, et
.size
);
17613 inst
.instruction
|= (rot
== 270) << 12;
17618 do_mve_vqdmull (void)
17620 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17621 struct neon_type_el et
17622 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17625 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17626 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17627 as_tsktsk (BAD_MVE_SRCDEST
);
17629 if (inst
.cond
> COND_ALWAYS
)
17630 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17632 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17636 mve_encode_qqq (et
.size
== 32, 64);
17637 inst
.instruction
|= 1;
17641 mve_encode_qqr (64, et
.size
== 32, 0);
17642 inst
.instruction
|= 0x3 << 5;
17649 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17650 struct neon_type_el et
17651 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17653 if (et
.type
== NT_invtype
)
17654 first_error (BAD_EL_TYPE
);
17656 if (inst
.cond
> COND_ALWAYS
)
17657 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17659 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17661 mve_encode_qqq (0, 64);
17665 do_mve_vbrsr (void)
17667 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17668 struct neon_type_el et
17669 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17671 if (inst
.cond
> COND_ALWAYS
)
17672 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17674 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17676 mve_encode_qqr (et
.size
, 0, 0);
17682 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17684 if (inst
.cond
> COND_ALWAYS
)
17685 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17687 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17689 mve_encode_qqq (1, 64);
17693 do_mve_vmulh (void)
17695 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17696 struct neon_type_el et
17697 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17699 if (inst
.cond
> COND_ALWAYS
)
17700 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17702 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17704 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17708 do_mve_vqdmlah (void)
17710 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17711 struct neon_type_el et
17712 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17714 if (inst
.cond
> COND_ALWAYS
)
17715 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17717 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17719 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17723 do_mve_vqdmladh (void)
17725 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17726 struct neon_type_el et
17727 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17729 if (inst
.cond
> COND_ALWAYS
)
17730 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17732 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17735 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17736 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17737 as_tsktsk (BAD_MVE_SRCDEST
);
17739 mve_encode_qqq (0, et
.size
);
17744 do_mve_vmull (void)
17747 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17748 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17749 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17750 && inst
.cond
== COND_ALWAYS
17751 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17756 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17757 N_SUF_32
| N_F64
| N_P8
17758 | N_P16
| N_I_MVE
| N_KEY
);
17759 if (((et
.type
== NT_poly
) && et
.size
== 8
17760 && ARM_CPU_IS_ANY (cpu_variant
))
17761 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17768 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17769 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17770 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17772 /* We are dealing with MVE's vmullt. */
17774 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17775 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17776 as_tsktsk (BAD_MVE_SRCDEST
);
17778 if (inst
.cond
> COND_ALWAYS
)
17779 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17781 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17783 if (et
.type
== NT_poly
)
17784 mve_encode_qqq (neon_logbits (et
.size
), 64);
17786 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17791 inst
.instruction
= N_MNEM_vmul
;
17794 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17799 do_mve_vabav (void)
17801 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17806 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17809 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17810 | N_S16
| N_S32
| N_U8
| N_U16
17813 if (inst
.cond
> COND_ALWAYS
)
17814 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17816 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17818 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17822 do_mve_vmladav (void)
17824 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17825 struct neon_type_el et
= neon_check_type (3, rs
,
17826 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17828 if (et
.type
== NT_unsigned
17829 && (inst
.instruction
== M_MNEM_vmladavx
17830 || inst
.instruction
== M_MNEM_vmladavax
17831 || inst
.instruction
== M_MNEM_vmlsdav
17832 || inst
.instruction
== M_MNEM_vmlsdava
17833 || inst
.instruction
== M_MNEM_vmlsdavx
17834 || inst
.instruction
== M_MNEM_vmlsdavax
))
17835 first_error (BAD_SIMD_TYPE
);
17837 constraint (inst
.operands
[2].reg
> 14,
17838 _("MVE vector register in the range [Q0..Q7] expected"));
17840 if (inst
.cond
> COND_ALWAYS
)
17841 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17843 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17845 if (inst
.instruction
== M_MNEM_vmlsdav
17846 || inst
.instruction
== M_MNEM_vmlsdava
17847 || inst
.instruction
== M_MNEM_vmlsdavx
17848 || inst
.instruction
== M_MNEM_vmlsdavax
)
17849 inst
.instruction
|= (et
.size
== 8) << 28;
17851 inst
.instruction
|= (et
.size
== 8) << 8;
17853 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17854 inst
.instruction
|= (et
.size
== 32) << 16;
17858 do_mve_vmlaldav (void)
17860 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17861 struct neon_type_el et
17862 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17863 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17865 if (et
.type
== NT_unsigned
17866 && (inst
.instruction
== M_MNEM_vmlsldav
17867 || inst
.instruction
== M_MNEM_vmlsldava
17868 || inst
.instruction
== M_MNEM_vmlsldavx
17869 || inst
.instruction
== M_MNEM_vmlsldavax
))
17870 first_error (BAD_SIMD_TYPE
);
17872 if (inst
.cond
> COND_ALWAYS
)
17873 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17875 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17877 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17881 do_mve_vrmlaldavh (void)
17883 struct neon_type_el et
;
17884 if (inst
.instruction
== M_MNEM_vrmlsldavh
17885 || inst
.instruction
== M_MNEM_vrmlsldavha
17886 || inst
.instruction
== M_MNEM_vrmlsldavhx
17887 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17889 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17890 if (inst
.operands
[1].reg
== REG_SP
)
17891 as_tsktsk (MVE_BAD_SP
);
17895 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17896 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17897 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17899 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17900 N_U32
| N_S32
| N_KEY
);
17901 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17902 with vmax/min instructions, making the use of SP in assembly really
17903 nonsensical, so instead of issuing a warning like we do for other uses
17904 of SP for the odd register operand we error out. */
17905 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17908 /* Make sure we still check the second operand is an odd one and that PC is
17909 disallowed. This because we are parsing for any GPR operand, to be able
17910 to distinguish between giving a warning or an error for SP as described
17912 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17913 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17915 if (inst
.cond
> COND_ALWAYS
)
17916 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17918 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17920 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17925 do_mve_vmaxnmv (void)
17927 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17928 struct neon_type_el et
17929 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17931 if (inst
.cond
> COND_ALWAYS
)
17932 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17934 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17936 if (inst
.operands
[0].reg
== REG_SP
)
17937 as_tsktsk (MVE_BAD_SP
);
17938 else if (inst
.operands
[0].reg
== REG_PC
)
17939 as_tsktsk (MVE_BAD_PC
);
17941 mve_encode_rq (et
.size
== 16, 64);
17945 do_mve_vmaxv (void)
17947 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17948 struct neon_type_el et
;
17950 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17951 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17953 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17955 if (inst
.cond
> COND_ALWAYS
)
17956 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17958 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17960 if (inst
.operands
[0].reg
== REG_SP
)
17961 as_tsktsk (MVE_BAD_SP
);
17962 else if (inst
.operands
[0].reg
== REG_PC
)
17963 as_tsktsk (MVE_BAD_PC
);
17965 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17970 do_neon_qrdmlah (void)
17972 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17974 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17976 /* Check we're on the correct architecture. */
17977 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17979 = _("instruction form not available on this architecture.");
17980 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17982 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17983 record_feature_use (&fpu_neon_ext_v8_1
);
17985 if (inst
.operands
[2].isscalar
)
17987 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17988 struct neon_type_el et
= neon_check_type (3, rs
,
17989 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17990 NEON_ENCODE (SCALAR
, inst
);
17991 neon_mul_mac (et
, neon_quad (rs
));
17995 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17996 struct neon_type_el et
= neon_check_type (3, rs
,
17997 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17998 NEON_ENCODE (INTEGER
, inst
);
17999 /* The U bit (rounding) comes from bit mask. */
18000 neon_three_same (neon_quad (rs
), 0, et
.size
);
18005 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18006 struct neon_type_el et
18007 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18009 NEON_ENCODE (INTEGER
, inst
);
18010 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18015 do_neon_fcmp_absolute (void)
18017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18018 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18019 N_F_16_32
| N_KEY
);
18020 /* Size field comes from bit mask. */
18021 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18025 do_neon_fcmp_absolute_inv (void)
18027 neon_exchange_operands ();
18028 do_neon_fcmp_absolute ();
18032 do_neon_step (void)
18034 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18035 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18036 N_F_16_32
| N_KEY
);
18037 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18041 do_neon_abs_neg (void)
18043 enum neon_shape rs
;
18044 struct neon_type_el et
;
18046 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18049 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18050 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18052 if (!check_simd_pred_availability (et
.type
== NT_float
,
18053 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18056 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18057 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18058 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18059 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18060 inst
.instruction
|= neon_quad (rs
) << 6;
18061 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18062 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18064 neon_dp_fixup (&inst
);
18070 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18073 enum neon_shape rs
;
18074 struct neon_type_el et
;
18075 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18077 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18078 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18082 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18083 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18087 int imm
= inst
.operands
[2].imm
;
18088 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18089 _("immediate out of range for insert"));
18090 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18096 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18099 enum neon_shape rs
;
18100 struct neon_type_el et
;
18101 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18103 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18104 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18108 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18109 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18112 int imm
= inst
.operands
[2].imm
;
18113 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18114 _("immediate out of range for insert"));
18115 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18119 do_neon_qshlu_imm (void)
18121 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18124 enum neon_shape rs
;
18125 struct neon_type_el et
;
18126 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18128 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18129 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18133 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18134 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18135 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18138 int imm
= inst
.operands
[2].imm
;
18139 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18140 _("immediate out of range for shift"));
18141 /* Only encodes the 'U present' variant of the instruction.
18142 In this case, signed types have OP (bit 8) set to 0.
18143 Unsigned types have OP set to 1. */
18144 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18145 /* The rest of the bits are the same as other immediate shifts. */
18146 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18150 do_neon_qmovn (void)
18152 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18153 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18154 /* Saturating move where operands can be signed or unsigned, and the
18155 destination has the same signedness. */
18156 NEON_ENCODE (INTEGER
, inst
);
18157 if (et
.type
== NT_unsigned
)
18158 inst
.instruction
|= 0xc0;
18160 inst
.instruction
|= 0x80;
18161 neon_two_same (0, 1, et
.size
/ 2);
18165 do_neon_qmovun (void)
18167 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18168 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18169 /* Saturating move with unsigned results. Operands must be signed. */
18170 NEON_ENCODE (INTEGER
, inst
);
18171 neon_two_same (0, 1, et
.size
/ 2);
18175 do_neon_rshift_sat_narrow (void)
18177 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18178 or unsigned. If operands are unsigned, results must also be unsigned. */
18179 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18180 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18181 int imm
= inst
.operands
[2].imm
;
18182 /* This gets the bounds check, size encoding and immediate bits calculation
18186 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18187 VQMOVN.I<size> <Dd>, <Qm>. */
18190 inst
.operands
[2].present
= 0;
18191 inst
.instruction
= N_MNEM_vqmovn
;
18196 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18197 _("immediate out of range"));
18198 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18202 do_neon_rshift_sat_narrow_u (void)
18204 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18205 or unsigned. If operands are unsigned, results must also be unsigned. */
18206 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18207 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18208 int imm
= inst
.operands
[2].imm
;
18209 /* This gets the bounds check, size encoding and immediate bits calculation
18213 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18214 VQMOVUN.I<size> <Dd>, <Qm>. */
18217 inst
.operands
[2].present
= 0;
18218 inst
.instruction
= N_MNEM_vqmovun
;
18223 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18224 _("immediate out of range"));
18225 /* FIXME: The manual is kind of unclear about what value U should have in
18226 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18228 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18232 do_neon_movn (void)
18234 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18235 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18236 NEON_ENCODE (INTEGER
, inst
);
18237 neon_two_same (0, 1, et
.size
/ 2);
18241 do_neon_rshift_narrow (void)
18243 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18244 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18245 int imm
= inst
.operands
[2].imm
;
18246 /* This gets the bounds check, size encoding and immediate bits calculation
18250 /* If immediate is zero then we are a pseudo-instruction for
18251 VMOVN.I<size> <Dd>, <Qm> */
18254 inst
.operands
[2].present
= 0;
18255 inst
.instruction
= N_MNEM_vmovn
;
18260 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18261 _("immediate out of range for narrowing operation"));
18262 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18266 do_neon_shll (void)
18268 /* FIXME: Type checking when lengthening. */
18269 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18270 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18271 unsigned imm
= inst
.operands
[2].imm
;
18273 if (imm
== et
.size
)
18275 /* Maximum shift variant. */
18276 NEON_ENCODE (INTEGER
, inst
);
18277 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18278 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18279 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18280 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18281 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18283 neon_dp_fixup (&inst
);
18287 /* A more-specific type check for non-max versions. */
18288 et
= neon_check_type (2, NS_QDI
,
18289 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18290 NEON_ENCODE (IMMED
, inst
);
18291 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18295 /* Check the various types for the VCVT instruction, and return which version
18296 the current instruction is. */
18298 #define CVT_FLAVOUR_VAR \
18299 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18300 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18301 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18302 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18303 /* Half-precision conversions. */ \
18304 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18305 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18306 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18307 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18308 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18309 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18310 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18311 Compared with single/double precision variants, only the co-processor \
18312 field is different, so the encoding flow is reused here. */ \
18313 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18314 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18315 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18316 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18317 /* VFP instructions. */ \
18318 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18319 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18320 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18321 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18322 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18323 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18324 /* VFP instructions with bitshift. */ \
18325 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18326 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18327 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18328 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18329 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18330 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18331 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18332 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18334 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18335 neon_cvt_flavour_##C,
18337 /* The different types of conversions we can do. */
18338 enum neon_cvt_flavour
18341 neon_cvt_flavour_invalid
,
18342 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18347 static enum neon_cvt_flavour
18348 get_neon_cvt_flavour (enum neon_shape rs
)
18350 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18351 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18352 if (et.type != NT_invtype) \
18354 inst.error = NULL; \
18355 return (neon_cvt_flavour_##C); \
18358 struct neon_type_el et
;
18359 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18360 || rs
== NS_FF
) ? N_VFP
: 0;
18361 /* The instruction versions which take an immediate take one register
18362 argument, which is extended to the width of the full register. Thus the
18363 "source" and "destination" registers must have the same width. Hack that
18364 here by making the size equal to the key (wider, in this case) operand. */
18365 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18369 return neon_cvt_flavour_invalid
;
18384 /* Neon-syntax VFP conversions. */
18387 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18389 const char *opname
= 0;
18391 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18392 || rs
== NS_FHI
|| rs
== NS_HFI
)
18394 /* Conversions with immediate bitshift. */
18395 const char *enc
[] =
18397 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18403 if (flavour
< (int) ARRAY_SIZE (enc
))
18405 opname
= enc
[flavour
];
18406 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18407 _("operands 0 and 1 must be the same register"));
18408 inst
.operands
[1] = inst
.operands
[2];
18409 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18414 /* Conversions without bitshift. */
18415 const char *enc
[] =
18417 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18423 if (flavour
< (int) ARRAY_SIZE (enc
))
18424 opname
= enc
[flavour
];
18428 do_vfp_nsyn_opcode (opname
);
18430 /* ARMv8.2 fp16 VCVT instruction. */
18431 if (flavour
== neon_cvt_flavour_s32_f16
18432 || flavour
== neon_cvt_flavour_u32_f16
18433 || flavour
== neon_cvt_flavour_f16_u32
18434 || flavour
== neon_cvt_flavour_f16_s32
)
18435 do_scalar_fp16_v82_encode ();
18439 do_vfp_nsyn_cvtz (void)
18441 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18442 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18443 const char *enc
[] =
18445 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18451 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18452 do_vfp_nsyn_opcode (enc
[flavour
]);
18456 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18457 enum neon_cvt_mode mode
)
18462 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18463 D register operands. */
18464 if (flavour
== neon_cvt_flavour_s32_f64
18465 || flavour
== neon_cvt_flavour_u32_f64
)
18466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18469 if (flavour
== neon_cvt_flavour_s32_f16
18470 || flavour
== neon_cvt_flavour_u32_f16
)
18471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18474 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18478 case neon_cvt_flavour_s32_f64
:
18482 case neon_cvt_flavour_s32_f32
:
18486 case neon_cvt_flavour_s32_f16
:
18490 case neon_cvt_flavour_u32_f64
:
18494 case neon_cvt_flavour_u32_f32
:
18498 case neon_cvt_flavour_u32_f16
:
18503 first_error (_("invalid instruction shape"));
18509 case neon_cvt_mode_a
: rm
= 0; break;
18510 case neon_cvt_mode_n
: rm
= 1; break;
18511 case neon_cvt_mode_p
: rm
= 2; break;
18512 case neon_cvt_mode_m
: rm
= 3; break;
18513 default: first_error (_("invalid rounding mode")); return;
18516 NEON_ENCODE (FPV8
, inst
);
18517 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18518 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18519 inst
.instruction
|= sz
<< 8;
18521 /* ARMv8.2 fp16 VCVT instruction. */
18522 if (flavour
== neon_cvt_flavour_s32_f16
18523 ||flavour
== neon_cvt_flavour_u32_f16
)
18524 do_scalar_fp16_v82_encode ();
18525 inst
.instruction
|= op
<< 7;
18526 inst
.instruction
|= rm
<< 16;
18527 inst
.instruction
|= 0xf0000000;
18528 inst
.is_neon
= TRUE
;
18532 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18534 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18535 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18536 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18538 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18540 if (flavour
== neon_cvt_flavour_invalid
)
18543 /* PR11109: Handle round-to-zero for VCVT conversions. */
18544 if (mode
== neon_cvt_mode_z
18545 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18546 && (flavour
== neon_cvt_flavour_s16_f16
18547 || flavour
== neon_cvt_flavour_u16_f16
18548 || flavour
== neon_cvt_flavour_s32_f32
18549 || flavour
== neon_cvt_flavour_u32_f32
18550 || flavour
== neon_cvt_flavour_s32_f64
18551 || flavour
== neon_cvt_flavour_u32_f64
)
18552 && (rs
== NS_FD
|| rs
== NS_FF
))
18554 do_vfp_nsyn_cvtz ();
18558 /* ARMv8.2 fp16 VCVT conversions. */
18559 if (mode
== neon_cvt_mode_z
18560 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18561 && (flavour
== neon_cvt_flavour_s32_f16
18562 || flavour
== neon_cvt_flavour_u32_f16
)
18565 do_vfp_nsyn_cvtz ();
18566 do_scalar_fp16_v82_encode ();
18570 /* VFP rather than Neon conversions. */
18571 if (flavour
>= neon_cvt_flavour_first_fp
)
18573 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18574 do_vfp_nsyn_cvt (rs
, flavour
);
18576 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18584 if (mode
== neon_cvt_mode_z
18585 && (flavour
== neon_cvt_flavour_f16_s16
18586 || flavour
== neon_cvt_flavour_f16_u16
18587 || flavour
== neon_cvt_flavour_s16_f16
18588 || flavour
== neon_cvt_flavour_u16_f16
18589 || flavour
== neon_cvt_flavour_f32_u32
18590 || flavour
== neon_cvt_flavour_f32_s32
18591 || flavour
== neon_cvt_flavour_s32_f32
18592 || flavour
== neon_cvt_flavour_u32_f32
))
18594 if (!check_simd_pred_availability (TRUE
,
18595 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18598 else if (mode
== neon_cvt_mode_n
)
18600 /* We are dealing with vcvt with the 'ne' condition. */
18602 inst
.instruction
= N_MNEM_vcvt
;
18603 do_neon_cvt_1 (neon_cvt_mode_z
);
18606 /* fall through. */
18610 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18611 0x0000100, 0x1000100, 0x0, 0x1000000};
18613 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18614 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18619 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18620 _("immediate value out of range"));
18623 case neon_cvt_flavour_f16_s16
:
18624 case neon_cvt_flavour_f16_u16
:
18625 case neon_cvt_flavour_s16_f16
:
18626 case neon_cvt_flavour_u16_f16
:
18627 constraint (inst
.operands
[2].imm
> 16,
18628 _("immediate value out of range"));
18630 case neon_cvt_flavour_f32_u32
:
18631 case neon_cvt_flavour_f32_s32
:
18632 case neon_cvt_flavour_s32_f32
:
18633 case neon_cvt_flavour_u32_f32
:
18634 constraint (inst
.operands
[2].imm
> 32,
18635 _("immediate value out of range"));
18638 inst
.error
= BAD_FPU
;
18643 /* Fixed-point conversion with #0 immediate is encoded as an
18644 integer conversion. */
18645 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18647 NEON_ENCODE (IMMED
, inst
);
18648 if (flavour
!= neon_cvt_flavour_invalid
)
18649 inst
.instruction
|= enctab
[flavour
];
18650 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18651 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18652 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18653 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18654 inst
.instruction
|= neon_quad (rs
) << 6;
18655 inst
.instruction
|= 1 << 21;
18656 if (flavour
< neon_cvt_flavour_s16_f16
)
18658 inst
.instruction
|= 1 << 21;
18659 immbits
= 32 - inst
.operands
[2].imm
;
18660 inst
.instruction
|= immbits
<< 16;
18664 inst
.instruction
|= 3 << 20;
18665 immbits
= 16 - inst
.operands
[2].imm
;
18666 inst
.instruction
|= immbits
<< 16;
18667 inst
.instruction
&= ~(1 << 9);
18670 neon_dp_fixup (&inst
);
18675 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18676 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18677 && (flavour
== neon_cvt_flavour_s16_f16
18678 || flavour
== neon_cvt_flavour_u16_f16
18679 || flavour
== neon_cvt_flavour_s32_f32
18680 || flavour
== neon_cvt_flavour_u32_f32
))
18682 if (!check_simd_pred_availability (TRUE
,
18683 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18686 else if (mode
== neon_cvt_mode_z
18687 && (flavour
== neon_cvt_flavour_f16_s16
18688 || flavour
== neon_cvt_flavour_f16_u16
18689 || flavour
== neon_cvt_flavour_s16_f16
18690 || flavour
== neon_cvt_flavour_u16_f16
18691 || flavour
== neon_cvt_flavour_f32_u32
18692 || flavour
== neon_cvt_flavour_f32_s32
18693 || flavour
== neon_cvt_flavour_s32_f32
18694 || flavour
== neon_cvt_flavour_u32_f32
))
18696 if (!check_simd_pred_availability (TRUE
,
18697 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18700 /* fall through. */
18702 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18705 NEON_ENCODE (FLOAT
, inst
);
18706 if (!check_simd_pred_availability (TRUE
,
18707 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18714 inst
.instruction
|= neon_quad (rs
) << 6;
18715 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18716 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18717 inst
.instruction
|= mode
<< 8;
18718 if (flavour
== neon_cvt_flavour_u16_f16
18719 || flavour
== neon_cvt_flavour_s16_f16
)
18720 /* Mask off the original size bits and reencode them. */
18721 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18724 inst
.instruction
|= 0xfc000000;
18726 inst
.instruction
|= 0xf0000000;
18732 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18733 0x100, 0x180, 0x0, 0x080};
18735 NEON_ENCODE (INTEGER
, inst
);
18737 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18739 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18743 if (flavour
!= neon_cvt_flavour_invalid
)
18744 inst
.instruction
|= enctab
[flavour
];
18746 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18750 inst
.instruction
|= neon_quad (rs
) << 6;
18751 if (flavour
>= neon_cvt_flavour_s16_f16
18752 && flavour
<= neon_cvt_flavour_f16_u16
)
18753 /* Half precision. */
18754 inst
.instruction
|= 1 << 18;
18756 inst
.instruction
|= 2 << 18;
18758 neon_dp_fixup (&inst
);
18763 /* Half-precision conversions for Advanced SIMD -- neon. */
18766 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18770 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18772 as_bad (_("operand size must match register width"));
18777 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18779 as_bad (_("operand size must match register width"));
18784 inst
.instruction
= 0x3b60600;
18786 inst
.instruction
= 0x3b60700;
18788 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18789 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18790 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18791 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18792 neon_dp_fixup (&inst
);
18796 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18797 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18798 do_vfp_nsyn_cvt (rs
, flavour
);
18800 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18805 do_neon_cvtr (void)
18807 do_neon_cvt_1 (neon_cvt_mode_x
);
18813 do_neon_cvt_1 (neon_cvt_mode_z
);
18817 do_neon_cvta (void)
18819 do_neon_cvt_1 (neon_cvt_mode_a
);
18823 do_neon_cvtn (void)
18825 do_neon_cvt_1 (neon_cvt_mode_n
);
18829 do_neon_cvtp (void)
18831 do_neon_cvt_1 (neon_cvt_mode_p
);
18835 do_neon_cvtm (void)
18837 do_neon_cvt_1 (neon_cvt_mode_m
);
18841 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18844 mark_feature_used (&fpu_vfp_ext_armv8
);
18846 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18847 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18848 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18849 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18850 inst
.instruction
|= to
? 0x10000 : 0;
18851 inst
.instruction
|= t
? 0x80 : 0;
18852 inst
.instruction
|= is_double
? 0x100 : 0;
18853 do_vfp_cond_or_thumb ();
18857 do_neon_cvttb_1 (bfd_boolean t
)
18859 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18860 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18864 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18866 int single_to_half
= 0;
18867 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
18870 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18873 && (flavour
== neon_cvt_flavour_u16_f16
18874 || flavour
== neon_cvt_flavour_s16_f16
18875 || flavour
== neon_cvt_flavour_f16_s16
18876 || flavour
== neon_cvt_flavour_f16_u16
18877 || flavour
== neon_cvt_flavour_u32_f32
18878 || flavour
== neon_cvt_flavour_s32_f32
18879 || flavour
== neon_cvt_flavour_f32_s32
18880 || flavour
== neon_cvt_flavour_f32_u32
))
18883 inst
.instruction
= N_MNEM_vcvt
;
18884 set_pred_insn_type (INSIDE_VPT_INSN
);
18885 do_neon_cvt_1 (neon_cvt_mode_z
);
18888 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18889 single_to_half
= 1;
18890 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18892 first_error (BAD_FPU
);
18896 inst
.instruction
= 0xee3f0e01;
18897 inst
.instruction
|= single_to_half
<< 28;
18898 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18900 inst
.instruction
|= t
<< 12;
18901 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18902 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18905 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18908 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18910 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18913 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18915 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18917 /* The VCVTB and VCVTT instructions with D-register operands
18918 don't work for SP only targets. */
18919 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18923 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18925 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18927 /* The VCVTB and VCVTT instructions with D-register operands
18928 don't work for SP only targets. */
18929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18933 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18940 do_neon_cvtb (void)
18942 do_neon_cvttb_1 (FALSE
);
18947 do_neon_cvtt (void)
18949 do_neon_cvttb_1 (TRUE
);
18953 neon_move_immediate (void)
18955 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18956 struct neon_type_el et
= neon_check_type (2, rs
,
18957 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18958 unsigned immlo
, immhi
= 0, immbits
;
18959 int op
, cmode
, float_p
;
18961 constraint (et
.type
== NT_invtype
,
18962 _("operand size must be specified for immediate VMOV"));
18964 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18965 op
= (inst
.instruction
& (1 << 5)) != 0;
18967 immlo
= inst
.operands
[1].imm
;
18968 if (inst
.operands
[1].regisimm
)
18969 immhi
= inst
.operands
[1].reg
;
18971 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18972 _("immediate has bits set outside the operand size"));
18974 float_p
= inst
.operands
[1].immisfloat
;
18976 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18977 et
.size
, et
.type
)) == FAIL
)
18979 /* Invert relevant bits only. */
18980 neon_invert_size (&immlo
, &immhi
, et
.size
);
18981 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18982 with one or the other; those cases are caught by
18983 neon_cmode_for_move_imm. */
18985 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18986 &op
, et
.size
, et
.type
)) == FAIL
)
18988 first_error (_("immediate out of range"));
18993 inst
.instruction
&= ~(1 << 5);
18994 inst
.instruction
|= op
<< 5;
18996 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18998 inst
.instruction
|= neon_quad (rs
) << 6;
18999 inst
.instruction
|= cmode
<< 8;
19001 neon_write_immbits (immbits
);
19007 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19010 if (inst
.operands
[1].isreg
)
19012 enum neon_shape rs
;
19013 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19014 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19016 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19018 NEON_ENCODE (INTEGER
, inst
);
19019 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19020 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19021 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19022 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19023 inst
.instruction
|= neon_quad (rs
) << 6;
19027 NEON_ENCODE (IMMED
, inst
);
19028 neon_move_immediate ();
19031 neon_dp_fixup (&inst
);
19033 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19035 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19036 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19037 _("immediate value out of range"));
19041 /* Encode instructions of form:
19043 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19044 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19047 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19049 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19050 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19051 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19052 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19053 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19054 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19055 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19056 inst
.instruction
|= neon_logbits (size
) << 20;
19058 neon_dp_fixup (&inst
);
19062 do_neon_dyadic_long (void)
19064 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19067 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19070 NEON_ENCODE (INTEGER
, inst
);
19071 /* FIXME: Type checking for lengthening op. */
19072 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19073 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19074 neon_mixed_length (et
, et
.size
);
19076 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19077 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19079 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19080 in an IT block with le/lt conditions. */
19082 if (inst
.cond
== 0xf)
19084 else if (inst
.cond
== 0x10)
19087 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19089 if (inst
.instruction
== N_MNEM_vaddl
)
19091 inst
.instruction
= N_MNEM_vadd
;
19092 do_neon_addsub_if_i ();
19094 else if (inst
.instruction
== N_MNEM_vsubl
)
19096 inst
.instruction
= N_MNEM_vsub
;
19097 do_neon_addsub_if_i ();
19099 else if (inst
.instruction
== N_MNEM_vabdl
)
19101 inst
.instruction
= N_MNEM_vabd
;
19102 do_neon_dyadic_if_su ();
19106 first_error (BAD_FPU
);
19110 do_neon_abal (void)
19112 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19113 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19114 neon_mixed_length (et
, et
.size
);
19118 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19120 if (inst
.operands
[2].isscalar
)
19122 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19123 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19124 NEON_ENCODE (SCALAR
, inst
);
19125 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19129 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19130 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19131 NEON_ENCODE (INTEGER
, inst
);
19132 neon_mixed_length (et
, et
.size
);
19137 do_neon_mac_maybe_scalar_long (void)
19139 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19142 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19143 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19146 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19148 unsigned regno
= NEON_SCALAR_REG (scalar
);
19149 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19153 if (regno
> 7 || elno
> 3)
19156 return ((regno
& 0x7)
19157 | ((elno
& 0x1) << 3)
19158 | (((elno
>> 1) & 0x1) << 5));
19162 if (regno
> 15 || elno
> 1)
19165 return (((regno
& 0x1) << 5)
19166 | ((regno
>> 1) & 0x7)
19167 | ((elno
& 0x1) << 3));
19171 first_error (_("scalar out of range for multiply instruction"));
19176 do_neon_fmac_maybe_scalar_long (int subtype
)
19178 enum neon_shape rs
;
19180 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19181 field (bits[21:20]) has different meaning. For scalar index variant, it's
19182 used to differentiate add and subtract, otherwise it's with fixed value
19186 if (inst
.cond
!= COND_ALWAYS
)
19187 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19188 "behaviour is UNPREDICTABLE"));
19190 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19196 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19197 be a scalar index register. */
19198 if (inst
.operands
[2].isscalar
)
19200 high8
= 0xfe000000;
19203 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19207 high8
= 0xfc000000;
19210 inst
.instruction
|= (0x1 << 23);
19211 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19214 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19216 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19217 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19218 so we simply pass -1 as size. */
19219 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19220 neon_three_same (quad_p
, 0, size
);
19222 /* Undo neon_dp_fixup. Redo the high eight bits. */
19223 inst
.instruction
&= 0x00ffffff;
19224 inst
.instruction
|= high8
;
19226 #define LOW1(R) ((R) & 0x1)
19227 #define HI4(R) (((R) >> 1) & 0xf)
19228 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19229 whether the instruction is in Q form and whether Vm is a scalar indexed
19231 if (inst
.operands
[2].isscalar
)
19234 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19235 inst
.instruction
&= 0xffffffd0;
19236 inst
.instruction
|= rm
;
19240 /* Redo Rn as well. */
19241 inst
.instruction
&= 0xfff0ff7f;
19242 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19243 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19248 /* Redo Rn and Rm. */
19249 inst
.instruction
&= 0xfff0ff50;
19250 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19251 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19252 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19253 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19258 do_neon_vfmal (void)
19260 return do_neon_fmac_maybe_scalar_long (0);
19264 do_neon_vfmsl (void)
19266 return do_neon_fmac_maybe_scalar_long (1);
19270 do_neon_dyadic_wide (void)
19272 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19273 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19274 neon_mixed_length (et
, et
.size
);
19278 do_neon_dyadic_narrow (void)
19280 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19281 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19282 /* Operand sign is unimportant, and the U bit is part of the opcode,
19283 so force the operand type to integer. */
19284 et
.type
= NT_integer
;
19285 neon_mixed_length (et
, et
.size
/ 2);
19289 do_neon_mul_sat_scalar_long (void)
19291 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19295 do_neon_vmull (void)
19297 if (inst
.operands
[2].isscalar
)
19298 do_neon_mac_maybe_scalar_long ();
19301 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19302 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19304 if (et
.type
== NT_poly
)
19305 NEON_ENCODE (POLY
, inst
);
19307 NEON_ENCODE (INTEGER
, inst
);
19309 /* For polynomial encoding the U bit must be zero, and the size must
19310 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19311 obviously, as 0b10). */
19314 /* Check we're on the correct architecture. */
19315 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19317 _("Instruction form not available on this architecture.");
19322 neon_mixed_length (et
, et
.size
);
19329 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19330 struct neon_type_el et
= neon_check_type (3, rs
,
19331 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19332 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19334 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19335 _("shift out of range"));
19336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19337 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19338 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19339 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19340 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19341 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19342 inst
.instruction
|= neon_quad (rs
) << 6;
19343 inst
.instruction
|= imm
<< 8;
19345 neon_dp_fixup (&inst
);
19351 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19354 enum neon_shape rs
;
19355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19356 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19358 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19360 struct neon_type_el et
= neon_check_type (2, rs
,
19361 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19363 unsigned op
= (inst
.instruction
>> 7) & 3;
19364 /* N (width of reversed regions) is encoded as part of the bitmask. We
19365 extract it here to check the elements to be reversed are smaller.
19366 Otherwise we'd get a reserved instruction. */
19367 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19369 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19370 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19371 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19372 " operands makes instruction UNPREDICTABLE"));
19374 gas_assert (elsize
!= 0);
19375 constraint (et
.size
>= elsize
,
19376 _("elements must be smaller than reversal region"));
19377 neon_two_same (neon_quad (rs
), 1, et
.size
);
19383 if (inst
.operands
[1].isscalar
)
19385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19387 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19388 struct neon_type_el et
= neon_check_type (2, rs
,
19389 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19390 unsigned sizebits
= et
.size
>> 3;
19391 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19392 int logsize
= neon_logbits (et
.size
);
19393 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19395 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19398 NEON_ENCODE (SCALAR
, inst
);
19399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19401 inst
.instruction
|= LOW4 (dm
);
19402 inst
.instruction
|= HI1 (dm
) << 5;
19403 inst
.instruction
|= neon_quad (rs
) << 6;
19404 inst
.instruction
|= x
<< 17;
19405 inst
.instruction
|= sizebits
<< 16;
19407 neon_dp_fixup (&inst
);
19411 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19412 struct neon_type_el et
= neon_check_type (2, rs
,
19413 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19416 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19420 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19423 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19425 if (inst
.operands
[1].reg
== REG_SP
)
19426 as_tsktsk (MVE_BAD_SP
);
19427 else if (inst
.operands
[1].reg
== REG_PC
)
19428 as_tsktsk (MVE_BAD_PC
);
19431 /* Duplicate ARM register to lanes of vector. */
19432 NEON_ENCODE (ARMREG
, inst
);
19435 case 8: inst
.instruction
|= 0x400000; break;
19436 case 16: inst
.instruction
|= 0x000020; break;
19437 case 32: inst
.instruction
|= 0x000000; break;
19440 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19441 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19442 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19443 inst
.instruction
|= neon_quad (rs
) << 21;
19444 /* The encoding for this instruction is identical for the ARM and Thumb
19445 variants, except for the condition field. */
19446 do_vfp_cond_or_thumb ();
19451 do_mve_mov (int toQ
)
19453 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19455 if (inst
.cond
> COND_ALWAYS
)
19456 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19458 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19467 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19468 _("Index one must be [2,3] and index two must be two less than"
19470 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19471 _("General purpose registers may not be the same"));
19472 constraint (inst
.operands
[Rt
].reg
== REG_SP
19473 || inst
.operands
[Rt2
].reg
== REG_SP
,
19475 constraint (inst
.operands
[Rt
].reg
== REG_PC
19476 || inst
.operands
[Rt2
].reg
== REG_PC
,
19479 inst
.instruction
= 0xec000f00;
19480 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19481 inst
.instruction
|= !!toQ
<< 20;
19482 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19483 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19484 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19485 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19491 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19494 if (inst
.cond
> COND_ALWAYS
)
19495 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19497 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19499 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19502 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19503 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19504 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19505 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19506 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19511 /* VMOV has particularly many variations. It can be one of:
19512 0. VMOV<c><q> <Qd>, <Qm>
19513 1. VMOV<c><q> <Dd>, <Dm>
19514 (Register operations, which are VORR with Rm = Rn.)
19515 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19516 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19518 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19519 (ARM register to scalar.)
19520 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19521 (Two ARM registers to vector.)
19522 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19523 (Scalar to ARM register.)
19524 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19525 (Vector to two ARM registers.)
19526 8. VMOV.F32 <Sd>, <Sm>
19527 9. VMOV.F64 <Dd>, <Dm>
19528 (VFP register moves.)
19529 10. VMOV.F32 <Sd>, #imm
19530 11. VMOV.F64 <Dd>, #imm
19531 (VFP float immediate load.)
19532 12. VMOV <Rd>, <Sm>
19533 (VFP single to ARM reg.)
19534 13. VMOV <Sd>, <Rm>
19535 (ARM reg to VFP single.)
19536 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19537 (Two ARM regs to two VFP singles.)
19538 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19539 (Two VFP singles to two ARM regs.)
19540 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19541 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19542 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19543 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19545 These cases can be disambiguated using neon_select_shape, except cases 1/9
19546 and 3/11 which depend on the operand type too.
19548 All the encoded bits are hardcoded by this function.
19550 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19551 Cases 5, 7 may be used with VFPv2 and above.
19553 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19554 can specify a type where it doesn't make sense to, and is ignored). */
19559 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19560 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19561 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19562 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19564 struct neon_type_el et
;
19565 const char *ldconst
= 0;
19569 case NS_DD
: /* case 1/9. */
19570 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19571 /* It is not an error here if no type is given. */
19573 if (et
.type
== NT_float
&& et
.size
== 64)
19575 do_vfp_nsyn_opcode ("fcpyd");
19578 /* fall through. */
19580 case NS_QQ
: /* case 0/1. */
19582 if (!check_simd_pred_availability (FALSE
,
19583 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19585 /* The architecture manual I have doesn't explicitly state which
19586 value the U bit should have for register->register moves, but
19587 the equivalent VORR instruction has U = 0, so do that. */
19588 inst
.instruction
= 0x0200110;
19589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19593 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19594 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19595 inst
.instruction
|= neon_quad (rs
) << 6;
19597 neon_dp_fixup (&inst
);
19601 case NS_DI
: /* case 3/11. */
19602 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19604 if (et
.type
== NT_float
&& et
.size
== 64)
19606 /* case 11 (fconstd). */
19607 ldconst
= "fconstd";
19608 goto encode_fconstd
;
19610 /* fall through. */
19612 case NS_QI
: /* case 2/3. */
19613 if (!check_simd_pred_availability (FALSE
,
19614 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19616 inst
.instruction
= 0x0800010;
19617 neon_move_immediate ();
19618 neon_dp_fixup (&inst
);
19621 case NS_SR
: /* case 4. */
19623 unsigned bcdebits
= 0;
19625 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19626 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19628 /* .<size> is optional here, defaulting to .32. */
19629 if (inst
.vectype
.elems
== 0
19630 && inst
.operands
[0].vectype
.type
== NT_invtype
19631 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19633 inst
.vectype
.el
[0].type
= NT_untyped
;
19634 inst
.vectype
.el
[0].size
= 32;
19635 inst
.vectype
.elems
= 1;
19638 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19639 logsize
= neon_logbits (et
.size
);
19643 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19644 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19649 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19650 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19654 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19656 if (inst
.operands
[1].reg
== REG_SP
)
19657 as_tsktsk (MVE_BAD_SP
);
19658 else if (inst
.operands
[1].reg
== REG_PC
)
19659 as_tsktsk (MVE_BAD_PC
);
19661 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19663 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19664 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19669 case 8: bcdebits
= 0x8; break;
19670 case 16: bcdebits
= 0x1; break;
19671 case 32: bcdebits
= 0x0; break;
19675 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19677 inst
.instruction
= 0xe000b10;
19678 do_vfp_cond_or_thumb ();
19679 inst
.instruction
|= LOW4 (dn
) << 16;
19680 inst
.instruction
|= HI1 (dn
) << 7;
19681 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19682 inst
.instruction
|= (bcdebits
& 3) << 5;
19683 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19684 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19688 case NS_DRR
: /* case 5 (fmdrr). */
19689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19690 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19693 inst
.instruction
= 0xc400b10;
19694 do_vfp_cond_or_thumb ();
19695 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19696 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19697 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19698 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19701 case NS_RS
: /* case 6. */
19704 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19705 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19706 unsigned abcdebits
= 0;
19708 /* .<dt> is optional here, defaulting to .32. */
19709 if (inst
.vectype
.elems
== 0
19710 && inst
.operands
[0].vectype
.type
== NT_invtype
19711 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19713 inst
.vectype
.el
[0].type
= NT_untyped
;
19714 inst
.vectype
.el
[0].size
= 32;
19715 inst
.vectype
.elems
= 1;
19718 et
= neon_check_type (2, NS_NULL
,
19719 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19720 logsize
= neon_logbits (et
.size
);
19724 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19725 && vfp_or_neon_is_neon (NEON_CHECK_CC
19726 | NEON_CHECK_ARCH
) == FAIL
)
19731 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19732 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19736 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19738 if (inst
.operands
[0].reg
== REG_SP
)
19739 as_tsktsk (MVE_BAD_SP
);
19740 else if (inst
.operands
[0].reg
== REG_PC
)
19741 as_tsktsk (MVE_BAD_PC
);
19744 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19746 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19747 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19751 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19752 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19753 case 32: abcdebits
= 0x00; break;
19757 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19758 inst
.instruction
= 0xe100b10;
19759 do_vfp_cond_or_thumb ();
19760 inst
.instruction
|= LOW4 (dn
) << 16;
19761 inst
.instruction
|= HI1 (dn
) << 7;
19762 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19763 inst
.instruction
|= (abcdebits
& 3) << 5;
19764 inst
.instruction
|= (abcdebits
>> 2) << 21;
19765 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19769 case NS_RRD
: /* case 7 (fmrrd). */
19770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19771 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19774 inst
.instruction
= 0xc500b10;
19775 do_vfp_cond_or_thumb ();
19776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19777 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19778 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19779 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19782 case NS_FF
: /* case 8 (fcpys). */
19783 do_vfp_nsyn_opcode ("fcpys");
19787 case NS_FI
: /* case 10 (fconsts). */
19788 ldconst
= "fconsts";
19790 if (!inst
.operands
[1].immisfloat
)
19793 /* Immediate has to fit in 8 bits so float is enough. */
19794 float imm
= (float) inst
.operands
[1].imm
;
19795 memcpy (&new_imm
, &imm
, sizeof (float));
19796 /* But the assembly may have been written to provide an integer
19797 bit pattern that equates to a float, so check that the
19798 conversion has worked. */
19799 if (is_quarter_float (new_imm
))
19801 if (is_quarter_float (inst
.operands
[1].imm
))
19802 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19804 inst
.operands
[1].imm
= new_imm
;
19805 inst
.operands
[1].immisfloat
= 1;
19809 if (is_quarter_float (inst
.operands
[1].imm
))
19811 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19812 do_vfp_nsyn_opcode (ldconst
);
19814 /* ARMv8.2 fp16 vmov.f16 instruction. */
19816 do_scalar_fp16_v82_encode ();
19819 first_error (_("immediate out of range"));
19823 case NS_RF
: /* case 12 (fmrs). */
19824 do_vfp_nsyn_opcode ("fmrs");
19825 /* ARMv8.2 fp16 vmov.f16 instruction. */
19827 do_scalar_fp16_v82_encode ();
19831 case NS_FR
: /* case 13 (fmsr). */
19832 do_vfp_nsyn_opcode ("fmsr");
19833 /* ARMv8.2 fp16 vmov.f16 instruction. */
19835 do_scalar_fp16_v82_encode ();
19845 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19846 (one of which is a list), but we have parsed four. Do some fiddling to
19847 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19849 case NS_RRFF
: /* case 14 (fmrrs). */
19850 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19851 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19853 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19854 _("VFP registers must be adjacent"));
19855 inst
.operands
[2].imm
= 2;
19856 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19857 do_vfp_nsyn_opcode ("fmrrs");
19860 case NS_FFRR
: /* case 15 (fmsrr). */
19861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19862 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19864 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19865 _("VFP registers must be adjacent"));
19866 inst
.operands
[1] = inst
.operands
[2];
19867 inst
.operands
[2] = inst
.operands
[3];
19868 inst
.operands
[0].imm
= 2;
19869 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19870 do_vfp_nsyn_opcode ("fmsrr");
19874 /* neon_select_shape has determined that the instruction
19875 shape is wrong and has already set the error message. */
19886 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19887 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19888 && !inst
.operands
[2].present
))
19890 inst
.instruction
= 0;
19893 set_pred_insn_type (INSIDE_IT_INSN
);
19898 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19901 if (inst
.cond
!= COND_ALWAYS
)
19902 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19904 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19905 | N_S16
| N_U16
| N_KEY
);
19907 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19908 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19909 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19910 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19911 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19917 do_neon_rshift_round_imm (void)
19919 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19922 enum neon_shape rs
;
19923 struct neon_type_el et
;
19925 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19927 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
19928 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
19932 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19933 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19935 int imm
= inst
.operands
[2].imm
;
19937 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19940 inst
.operands
[2].present
= 0;
19945 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19946 _("immediate out of range for shift"));
19947 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19952 do_neon_movhf (void)
19954 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19955 constraint (rs
!= NS_HH
, _("invalid suffix"));
19957 if (inst
.cond
!= COND_ALWAYS
)
19961 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19962 " the behaviour is UNPREDICTABLE"));
19966 inst
.error
= BAD_COND
;
19971 do_vfp_sp_monadic ();
19974 inst
.instruction
|= 0xf0000000;
19978 do_neon_movl (void)
19980 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19981 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19982 unsigned sizebits
= et
.size
>> 3;
19983 inst
.instruction
|= sizebits
<< 19;
19984 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19990 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19991 struct neon_type_el et
= neon_check_type (2, rs
,
19992 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19993 NEON_ENCODE (INTEGER
, inst
);
19994 neon_two_same (neon_quad (rs
), 1, et
.size
);
19998 do_neon_zip_uzp (void)
20000 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20001 struct neon_type_el et
= neon_check_type (2, rs
,
20002 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20003 if (rs
== NS_DD
&& et
.size
== 32)
20005 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20006 inst
.instruction
= N_MNEM_vtrn
;
20010 neon_two_same (neon_quad (rs
), 1, et
.size
);
20014 do_neon_sat_abs_neg (void)
20016 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20019 enum neon_shape rs
;
20020 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20021 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20023 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20024 struct neon_type_el et
= neon_check_type (2, rs
,
20025 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20026 neon_two_same (neon_quad (rs
), 1, et
.size
);
20030 do_neon_pair_long (void)
20032 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20033 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20034 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20035 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20036 neon_two_same (neon_quad (rs
), 1, et
.size
);
20040 do_neon_recip_est (void)
20042 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20043 struct neon_type_el et
= neon_check_type (2, rs
,
20044 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20045 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20046 neon_two_same (neon_quad (rs
), 1, et
.size
);
20052 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20055 enum neon_shape rs
;
20056 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20057 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20059 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20061 struct neon_type_el et
= neon_check_type (2, rs
,
20062 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20063 neon_two_same (neon_quad (rs
), 1, et
.size
);
20069 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20072 enum neon_shape rs
;
20073 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20074 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20076 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20078 struct neon_type_el et
= neon_check_type (2, rs
,
20079 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20080 neon_two_same (neon_quad (rs
), 1, et
.size
);
20086 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20087 struct neon_type_el et
= neon_check_type (2, rs
,
20088 N_EQK
| N_INT
, N_8
| N_KEY
);
20089 neon_two_same (neon_quad (rs
), 1, et
.size
);
20095 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20096 neon_two_same (neon_quad (rs
), 1, -1);
20100 do_neon_tbl_tbx (void)
20102 unsigned listlenbits
;
20103 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20105 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20107 first_error (_("bad list length for table lookup"));
20111 listlenbits
= inst
.operands
[1].imm
- 1;
20112 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20113 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20114 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20115 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20116 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20117 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20118 inst
.instruction
|= listlenbits
<< 8;
20120 neon_dp_fixup (&inst
);
20124 do_neon_ldm_stm (void)
20126 /* P, U and L bits are part of bitmask. */
20127 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20128 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20130 if (inst
.operands
[1].issingle
)
20132 do_vfp_nsyn_ldm_stm (is_dbmode
);
20136 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20137 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20139 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20140 _("register list must contain at least 1 and at most 16 "
20143 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20144 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20148 inst
.instruction
|= offsetbits
;
20150 do_vfp_cond_or_thumb ();
20154 do_neon_ldr_str (void)
20156 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20158 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20159 And is UNPREDICTABLE in thumb mode. */
20161 && inst
.operands
[1].reg
== REG_PC
20162 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20165 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20166 else if (warn_on_deprecated
)
20167 as_tsktsk (_("Use of PC here is deprecated"));
20170 if (inst
.operands
[0].issingle
)
20173 do_vfp_nsyn_opcode ("flds");
20175 do_vfp_nsyn_opcode ("fsts");
20177 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20178 if (inst
.vectype
.el
[0].size
== 16)
20179 do_scalar_fp16_v82_encode ();
20184 do_vfp_nsyn_opcode ("fldd");
20186 do_vfp_nsyn_opcode ("fstd");
20191 do_t_vldr_vstr_sysreg (void)
20193 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20194 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20196 /* Use of PC is UNPREDICTABLE. */
20197 if (inst
.operands
[1].reg
== REG_PC
)
20198 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20200 if (inst
.operands
[1].immisreg
)
20201 inst
.error
= _("instruction does not accept register index");
20203 if (!inst
.operands
[1].isreg
)
20204 inst
.error
= _("instruction does not accept PC-relative addressing");
20206 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20207 inst
.error
= _("immediate value out of range");
20209 inst
.instruction
= 0xec000f80;
20211 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20212 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20213 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20214 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20218 do_vldr_vstr (void)
20220 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20222 /* VLDR/VSTR (System Register). */
20225 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20226 as_bad (_("Instruction not permitted on this architecture"));
20228 do_t_vldr_vstr_sysreg ();
20233 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20234 as_bad (_("Instruction not permitted on this architecture"));
20235 do_neon_ldr_str ();
20239 /* "interleave" version also handles non-interleaving register VLD1/VST1
20243 do_neon_ld_st_interleave (void)
20245 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20246 N_8
| N_16
| N_32
| N_64
);
20247 unsigned alignbits
= 0;
20249 /* The bits in this table go:
20250 0: register stride of one (0) or two (1)
20251 1,2: register list length, minus one (1, 2, 3, 4).
20252 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20253 We use -1 for invalid entries. */
20254 const int typetable
[] =
20256 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20257 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20258 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20259 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20263 if (et
.type
== NT_invtype
)
20266 if (inst
.operands
[1].immisalign
)
20267 switch (inst
.operands
[1].imm
>> 8)
20269 case 64: alignbits
= 1; break;
20271 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20272 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20273 goto bad_alignment
;
20277 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20278 goto bad_alignment
;
20283 first_error (_("bad alignment"));
20287 inst
.instruction
|= alignbits
<< 4;
20288 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20290 /* Bits [4:6] of the immediate in a list specifier encode register stride
20291 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20292 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20293 up the right value for "type" in a table based on this value and the given
20294 list style, then stick it back. */
20295 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20296 | (((inst
.instruction
>> 8) & 3) << 3);
20298 typebits
= typetable
[idx
];
20300 constraint (typebits
== -1, _("bad list type for instruction"));
20301 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20304 inst
.instruction
&= ~0xf00;
20305 inst
.instruction
|= typebits
<< 8;
20308 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20309 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20310 otherwise. The variable arguments are a list of pairs of legal (size, align)
20311 values, terminated with -1. */
20314 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20317 int result
= FAIL
, thissize
, thisalign
;
20319 if (!inst
.operands
[1].immisalign
)
20325 va_start (ap
, do_alignment
);
20329 thissize
= va_arg (ap
, int);
20330 if (thissize
== -1)
20332 thisalign
= va_arg (ap
, int);
20334 if (size
== thissize
&& align
== thisalign
)
20337 while (result
!= SUCCESS
);
20341 if (result
== SUCCESS
)
20344 first_error (_("unsupported alignment for instruction"));
20350 do_neon_ld_st_lane (void)
20352 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20353 int align_good
, do_alignment
= 0;
20354 int logsize
= neon_logbits (et
.size
);
20355 int align
= inst
.operands
[1].imm
>> 8;
20356 int n
= (inst
.instruction
>> 8) & 3;
20357 int max_el
= 64 / et
.size
;
20359 if (et
.type
== NT_invtype
)
20362 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20363 _("bad list length"));
20364 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20365 _("scalar index out of range"));
20366 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20368 _("stride of 2 unavailable when element size is 8"));
20372 case 0: /* VLD1 / VST1. */
20373 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20375 if (align_good
== FAIL
)
20379 unsigned alignbits
= 0;
20382 case 16: alignbits
= 0x1; break;
20383 case 32: alignbits
= 0x3; break;
20386 inst
.instruction
|= alignbits
<< 4;
20390 case 1: /* VLD2 / VST2. */
20391 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20392 16, 32, 32, 64, -1);
20393 if (align_good
== FAIL
)
20396 inst
.instruction
|= 1 << 4;
20399 case 2: /* VLD3 / VST3. */
20400 constraint (inst
.operands
[1].immisalign
,
20401 _("can't use alignment with this instruction"));
20404 case 3: /* VLD4 / VST4. */
20405 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20406 16, 64, 32, 64, 32, 128, -1);
20407 if (align_good
== FAIL
)
20411 unsigned alignbits
= 0;
20414 case 8: alignbits
= 0x1; break;
20415 case 16: alignbits
= 0x1; break;
20416 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20419 inst
.instruction
|= alignbits
<< 4;
20426 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20427 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20428 inst
.instruction
|= 1 << (4 + logsize
);
20430 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20431 inst
.instruction
|= logsize
<< 10;
20434 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20437 do_neon_ld_dup (void)
20439 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20440 int align_good
, do_alignment
= 0;
20442 if (et
.type
== NT_invtype
)
20445 switch ((inst
.instruction
>> 8) & 3)
20447 case 0: /* VLD1. */
20448 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20449 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20450 &do_alignment
, 16, 16, 32, 32, -1);
20451 if (align_good
== FAIL
)
20453 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20456 case 2: inst
.instruction
|= 1 << 5; break;
20457 default: first_error (_("bad list length")); return;
20459 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20462 case 1: /* VLD2. */
20463 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20464 &do_alignment
, 8, 16, 16, 32, 32, 64,
20466 if (align_good
== FAIL
)
20468 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20469 _("bad list length"));
20470 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20471 inst
.instruction
|= 1 << 5;
20472 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20475 case 2: /* VLD3. */
20476 constraint (inst
.operands
[1].immisalign
,
20477 _("can't use alignment with this instruction"));
20478 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20479 _("bad list length"));
20480 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20481 inst
.instruction
|= 1 << 5;
20482 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20485 case 3: /* VLD4. */
20487 int align
= inst
.operands
[1].imm
>> 8;
20488 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20489 16, 64, 32, 64, 32, 128, -1);
20490 if (align_good
== FAIL
)
20492 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20493 _("bad list length"));
20494 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20495 inst
.instruction
|= 1 << 5;
20496 if (et
.size
== 32 && align
== 128)
20497 inst
.instruction
|= 0x3 << 6;
20499 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20506 inst
.instruction
|= do_alignment
<< 4;
20509 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20510 apart from bits [11:4]. */
20513 do_neon_ldx_stx (void)
20515 if (inst
.operands
[1].isreg
)
20516 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20518 switch (NEON_LANE (inst
.operands
[0].imm
))
20520 case NEON_INTERLEAVE_LANES
:
20521 NEON_ENCODE (INTERLV
, inst
);
20522 do_neon_ld_st_interleave ();
20525 case NEON_ALL_LANES
:
20526 NEON_ENCODE (DUP
, inst
);
20527 if (inst
.instruction
== N_INV
)
20529 first_error ("only loads support such operands");
20536 NEON_ENCODE (LANE
, inst
);
20537 do_neon_ld_st_lane ();
20540 /* L bit comes from bit mask. */
20541 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20542 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20543 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20545 if (inst
.operands
[1].postind
)
20547 int postreg
= inst
.operands
[1].imm
& 0xf;
20548 constraint (!inst
.operands
[1].immisreg
,
20549 _("post-index must be a register"));
20550 constraint (postreg
== 0xd || postreg
== 0xf,
20551 _("bad register for post-index"));
20552 inst
.instruction
|= postreg
;
20556 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20557 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20558 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20561 if (inst
.operands
[1].writeback
)
20563 inst
.instruction
|= 0xd;
20566 inst
.instruction
|= 0xf;
20570 inst
.instruction
|= 0xf9000000;
20572 inst
.instruction
|= 0xf4000000;
20577 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20579 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20580 D register operands. */
20581 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20582 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20585 NEON_ENCODE (FPV8
, inst
);
20587 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20589 do_vfp_sp_dyadic ();
20591 /* ARMv8.2 fp16 instruction. */
20593 do_scalar_fp16_v82_encode ();
20596 do_vfp_dp_rd_rn_rm ();
20599 inst
.instruction
|= 0x100;
20601 inst
.instruction
|= 0xf0000000;
20607 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20609 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20610 first_error (_("invalid instruction shape"));
20616 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20617 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20619 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20622 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20625 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20629 do_vrint_1 (enum neon_cvt_mode mode
)
20631 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20632 struct neon_type_el et
;
20637 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20638 D register operands. */
20639 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20640 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20643 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20645 if (et
.type
!= NT_invtype
)
20647 /* VFP encodings. */
20648 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20649 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20650 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20652 NEON_ENCODE (FPV8
, inst
);
20653 if (rs
== NS_FF
|| rs
== NS_HH
)
20654 do_vfp_sp_monadic ();
20656 do_vfp_dp_rd_rm ();
20660 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20661 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20662 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20663 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20664 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20665 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20666 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20670 inst
.instruction
|= (rs
== NS_DD
) << 8;
20671 do_vfp_cond_or_thumb ();
20673 /* ARMv8.2 fp16 vrint instruction. */
20675 do_scalar_fp16_v82_encode ();
20679 /* Neon encodings (or something broken...). */
20681 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20683 if (et
.type
== NT_invtype
)
20686 if (!check_simd_pred_availability (TRUE
,
20687 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20690 NEON_ENCODE (FLOAT
, inst
);
20692 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20693 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20695 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20696 inst
.instruction
|= neon_quad (rs
) << 6;
20697 /* Mask off the original size bits and reencode them. */
20698 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20699 | neon_logbits (et
.size
) << 18);
20703 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20704 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20705 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20706 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20707 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20708 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20709 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20714 inst
.instruction
|= 0xfc000000;
20716 inst
.instruction
|= 0xf0000000;
20723 do_vrint_1 (neon_cvt_mode_x
);
20729 do_vrint_1 (neon_cvt_mode_z
);
20735 do_vrint_1 (neon_cvt_mode_r
);
20741 do_vrint_1 (neon_cvt_mode_a
);
20747 do_vrint_1 (neon_cvt_mode_n
);
20753 do_vrint_1 (neon_cvt_mode_p
);
20759 do_vrint_1 (neon_cvt_mode_m
);
20763 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20765 unsigned regno
= NEON_SCALAR_REG (opnd
);
20766 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20768 if (elsize
== 16 && elno
< 2 && regno
< 16)
20769 return regno
| (elno
<< 4);
20770 else if (elsize
== 32 && elno
== 0)
20773 first_error (_("scalar out of range"));
20780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20781 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20782 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20783 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20784 _("expression too complex"));
20785 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20786 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20787 _("immediate out of range"));
20790 if (!check_simd_pred_availability (TRUE
,
20791 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20794 if (inst
.operands
[2].isscalar
)
20796 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20797 first_error (_("invalid instruction shape"));
20798 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20799 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20800 N_KEY
| N_F16
| N_F32
).size
;
20801 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20803 inst
.instruction
= 0xfe000800;
20804 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20805 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20806 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20807 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20808 inst
.instruction
|= LOW4 (m
);
20809 inst
.instruction
|= HI1 (m
) << 5;
20810 inst
.instruction
|= neon_quad (rs
) << 6;
20811 inst
.instruction
|= rot
<< 20;
20812 inst
.instruction
|= (size
== 32) << 23;
20816 enum neon_shape rs
;
20817 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20818 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20820 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20822 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20823 N_KEY
| N_F16
| N_F32
).size
;
20824 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20825 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20826 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20827 as_tsktsk (BAD_MVE_SRCDEST
);
20829 neon_three_same (neon_quad (rs
), 0, -1);
20830 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20831 inst
.instruction
|= 0xfc200800;
20832 inst
.instruction
|= rot
<< 23;
20833 inst
.instruction
|= (size
== 32) << 20;
20840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20841 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20842 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20843 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20844 _("expression too complex"));
20846 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20847 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20848 enum neon_shape rs
;
20849 struct neon_type_el et
;
20850 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20852 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20853 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20857 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20858 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20860 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20861 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20862 "operand makes instruction UNPREDICTABLE"));
20865 if (et
.type
== NT_invtype
)
20868 if (!check_simd_pred_availability (et
.type
== NT_float
,
20869 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20872 if (et
.type
== NT_float
)
20874 neon_three_same (neon_quad (rs
), 0, -1);
20875 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20876 inst
.instruction
|= 0xfc800800;
20877 inst
.instruction
|= (rot
== 270) << 24;
20878 inst
.instruction
|= (et
.size
== 32) << 20;
20882 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20883 inst
.instruction
= 0xfe000f00;
20884 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20885 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20886 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20887 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20888 inst
.instruction
|= (rot
== 270) << 12;
20889 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20890 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20891 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20896 /* Dot Product instructions encoding support. */
20899 do_neon_dotproduct (int unsigned_p
)
20901 enum neon_shape rs
;
20902 unsigned scalar_oprd2
= 0;
20905 if (inst
.cond
!= COND_ALWAYS
)
20906 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20907 "is UNPREDICTABLE"));
20909 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20912 /* Dot Product instructions are in three-same D/Q register format or the third
20913 operand can be a scalar index register. */
20914 if (inst
.operands
[2].isscalar
)
20916 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20917 high8
= 0xfe000000;
20918 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20922 high8
= 0xfc000000;
20923 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20927 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20929 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20931 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20932 Product instruction, so we pass 0 as the "ubit" parameter. And the
20933 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20934 neon_three_same (neon_quad (rs
), 0, 32);
20936 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20937 different NEON three-same encoding. */
20938 inst
.instruction
&= 0x00ffffff;
20939 inst
.instruction
|= high8
;
20940 /* Encode 'U' bit which indicates signedness. */
20941 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20942 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20943 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20944 the instruction encoding. */
20945 if (inst
.operands
[2].isscalar
)
20947 inst
.instruction
&= 0xffffffd0;
20948 inst
.instruction
|= LOW4 (scalar_oprd2
);
20949 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20953 /* Dot Product instructions for signed integer. */
20956 do_neon_dotproduct_s (void)
20958 return do_neon_dotproduct (0);
20961 /* Dot Product instructions for unsigned integer. */
20964 do_neon_dotproduct_u (void)
20966 return do_neon_dotproduct (1);
20969 /* Crypto v1 instructions. */
20971 do_crypto_2op_1 (unsigned elttype
, int op
)
20973 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20975 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20981 NEON_ENCODE (INTEGER
, inst
);
20982 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20983 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20984 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20985 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20987 inst
.instruction
|= op
<< 6;
20990 inst
.instruction
|= 0xfc000000;
20992 inst
.instruction
|= 0xf0000000;
20996 do_crypto_3op_1 (int u
, int op
)
20998 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21000 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21001 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21006 NEON_ENCODE (INTEGER
, inst
);
21007 neon_three_same (1, u
, 8 << op
);
21013 do_crypto_2op_1 (N_8
, 0);
21019 do_crypto_2op_1 (N_8
, 1);
21025 do_crypto_2op_1 (N_8
, 2);
21031 do_crypto_2op_1 (N_8
, 3);
21037 do_crypto_3op_1 (0, 0);
21043 do_crypto_3op_1 (0, 1);
21049 do_crypto_3op_1 (0, 2);
21055 do_crypto_3op_1 (0, 3);
21061 do_crypto_3op_1 (1, 0);
21067 do_crypto_3op_1 (1, 1);
21071 do_sha256su1 (void)
21073 do_crypto_3op_1 (1, 2);
21079 do_crypto_2op_1 (N_32
, -1);
21085 do_crypto_2op_1 (N_32
, 0);
21089 do_sha256su0 (void)
21091 do_crypto_2op_1 (N_32
, 1);
21095 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21097 unsigned int Rd
= inst
.operands
[0].reg
;
21098 unsigned int Rn
= inst
.operands
[1].reg
;
21099 unsigned int Rm
= inst
.operands
[2].reg
;
21101 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21102 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21103 inst
.instruction
|= LOW4 (Rn
) << 16;
21104 inst
.instruction
|= LOW4 (Rm
);
21105 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21106 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21108 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21109 as_warn (UNPRED_REG ("r15"));
21151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21153 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21154 do_vfp_sp_dp_cvt ();
21155 do_vfp_cond_or_thumb ();
21159 /* Overall per-instruction processing. */
21161 /* We need to be able to fix up arbitrary expressions in some statements.
21162 This is so that we can handle symbols that are an arbitrary distance from
21163 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21164 which returns part of an address in a form which will be valid for
21165 a data instruction. We do this by pushing the expression into a symbol
21166 in the expr_section, and creating a fix for that. */
21169 fix_new_arm (fragS
* frag
,
21183 /* Create an absolute valued symbol, so we have something to
21184 refer to in the object file. Unfortunately for us, gas's
21185 generic expression parsing will already have folded out
21186 any use of .set foo/.type foo %function that may have
21187 been used to set type information of the target location,
21188 that's being specified symbolically. We have to presume
21189 the user knows what they are doing. */
21193 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21195 symbol
= symbol_find_or_make (name
);
21196 S_SET_SEGMENT (symbol
, absolute_section
);
21197 symbol_set_frag (symbol
, &zero_address_frag
);
21198 S_SET_VALUE (symbol
, exp
->X_add_number
);
21199 exp
->X_op
= O_symbol
;
21200 exp
->X_add_symbol
= symbol
;
21201 exp
->X_add_number
= 0;
21207 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21208 (enum bfd_reloc_code_real
) reloc
);
21212 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21213 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21217 /* Mark whether the fix is to a THUMB instruction, or an ARM
21219 new_fix
->tc_fix_data
= thumb_mode
;
21222 /* Create a frg for an instruction requiring relaxation. */
21224 output_relax_insn (void)
21230 /* The size of the instruction is unknown, so tie the debug info to the
21231 start of the instruction. */
21232 dwarf2_emit_insn (0);
21234 switch (inst
.relocs
[0].exp
.X_op
)
21237 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21238 offset
= inst
.relocs
[0].exp
.X_add_number
;
21242 offset
= inst
.relocs
[0].exp
.X_add_number
;
21245 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21249 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21250 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21251 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21254 /* Write a 32-bit thumb instruction to buf. */
21256 put_thumb32_insn (char * buf
, unsigned long insn
)
21258 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21259 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21263 output_inst (const char * str
)
21269 as_bad ("%s -- `%s'", inst
.error
, str
);
21274 output_relax_insn ();
21277 if (inst
.size
== 0)
21280 to
= frag_more (inst
.size
);
21281 /* PR 9814: Record the thumb mode into the current frag so that we know
21282 what type of NOP padding to use, if necessary. We override any previous
21283 setting so that if the mode has changed then the NOPS that we use will
21284 match the encoding of the last instruction in the frag. */
21285 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21287 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21289 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21290 put_thumb32_insn (to
, inst
.instruction
);
21292 else if (inst
.size
> INSN_SIZE
)
21294 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21295 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21296 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21299 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21302 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21304 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21305 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21306 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21307 inst
.relocs
[r
].type
);
21310 dwarf2_emit_insn (inst
.size
);
21314 output_it_inst (int cond
, int mask
, char * to
)
21316 unsigned long instruction
= 0xbf00;
21319 instruction
|= mask
;
21320 instruction
|= cond
<< 4;
21324 to
= frag_more (2);
21326 dwarf2_emit_insn (2);
21330 md_number_to_chars (to
, instruction
, 2);
21335 /* Tag values used in struct asm_opcode's tag field. */
21338 OT_unconditional
, /* Instruction cannot be conditionalized.
21339 The ARM condition field is still 0xE. */
21340 OT_unconditionalF
, /* Instruction cannot be conditionalized
21341 and carries 0xF in its ARM condition field. */
21342 OT_csuffix
, /* Instruction takes a conditional suffix. */
21343 OT_csuffixF
, /* Some forms of the instruction take a scalar
21344 conditional suffix, others place 0xF where the
21345 condition field would be, others take a vector
21346 conditional suffix. */
21347 OT_cinfix3
, /* Instruction takes a conditional infix,
21348 beginning at character index 3. (In
21349 unified mode, it becomes a suffix.) */
21350 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21351 tsts, cmps, cmns, and teqs. */
21352 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21353 character index 3, even in unified mode. Used for
21354 legacy instructions where suffix and infix forms
21355 may be ambiguous. */
21356 OT_csuf_or_in3
, /* Instruction takes either a conditional
21357 suffix or an infix at character index 3. */
21358 OT_odd_infix_unc
, /* This is the unconditional variant of an
21359 instruction that takes a conditional infix
21360 at an unusual position. In unified mode,
21361 this variant will accept a suffix. */
21362 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21363 are the conditional variants of instructions that
21364 take conditional infixes in unusual positions.
21365 The infix appears at character index
21366 (tag - OT_odd_infix_0). These are not accepted
21367 in unified mode. */
21370 /* Subroutine of md_assemble, responsible for looking up the primary
21371 opcode from the mnemonic the user wrote. STR points to the
21372 beginning of the mnemonic.
21374 This is not simply a hash table lookup, because of conditional
21375 variants. Most instructions have conditional variants, which are
21376 expressed with a _conditional affix_ to the mnemonic. If we were
21377 to encode each conditional variant as a literal string in the opcode
21378 table, it would have approximately 20,000 entries.
21380 Most mnemonics take this affix as a suffix, and in unified syntax,
21381 'most' is upgraded to 'all'. However, in the divided syntax, some
21382 instructions take the affix as an infix, notably the s-variants of
21383 the arithmetic instructions. Of those instructions, all but six
21384 have the infix appear after the third character of the mnemonic.
21386 Accordingly, the algorithm for looking up primary opcodes given
21389 1. Look up the identifier in the opcode table.
21390 If we find a match, go to step U.
21392 2. Look up the last two characters of the identifier in the
21393 conditions table. If we find a match, look up the first N-2
21394 characters of the identifier in the opcode table. If we
21395 find a match, go to step CE.
21397 3. Look up the fourth and fifth characters of the identifier in
21398 the conditions table. If we find a match, extract those
21399 characters from the identifier, and look up the remaining
21400 characters in the opcode table. If we find a match, go
21405 U. Examine the tag field of the opcode structure, in case this is
21406 one of the six instructions with its conditional infix in an
21407 unusual place. If it is, the tag tells us where to find the
21408 infix; look it up in the conditions table and set inst.cond
21409 accordingly. Otherwise, this is an unconditional instruction.
21410 Again set inst.cond accordingly. Return the opcode structure.
21412 CE. Examine the tag field to make sure this is an instruction that
21413 should receive a conditional suffix. If it is not, fail.
21414 Otherwise, set inst.cond from the suffix we already looked up,
21415 and return the opcode structure.
21417 CM. Examine the tag field to make sure this is an instruction that
21418 should receive a conditional infix after the third character.
21419 If it is not, fail. Otherwise, undo the edits to the current
21420 line of input and proceed as for case CE. */
21422 static const struct asm_opcode
*
21423 opcode_lookup (char **str
)
21427 const struct asm_opcode
*opcode
;
21428 const struct asm_cond
*cond
;
21431 /* Scan up to the end of the mnemonic, which must end in white space,
21432 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21433 for (base
= end
= *str
; *end
!= '\0'; end
++)
21434 if (*end
== ' ' || *end
== '.')
21440 /* Handle a possible width suffix and/or Neon type suffix. */
21445 /* The .w and .n suffixes are only valid if the unified syntax is in
21447 if (unified_syntax
&& end
[1] == 'w')
21449 else if (unified_syntax
&& end
[1] == 'n')
21454 inst
.vectype
.elems
= 0;
21456 *str
= end
+ offset
;
21458 if (end
[offset
] == '.')
21460 /* See if we have a Neon type suffix (possible in either unified or
21461 non-unified ARM syntax mode). */
21462 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21465 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21471 /* Look for unaffixed or special-case affixed mnemonic. */
21472 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21477 if (opcode
->tag
< OT_odd_infix_0
)
21479 inst
.cond
= COND_ALWAYS
;
21483 if (warn_on_deprecated
&& unified_syntax
)
21484 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21485 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21486 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21489 inst
.cond
= cond
->value
;
21492 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21494 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21496 if (end
- base
< 2)
21499 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21500 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21502 /* If this opcode can not be vector predicated then don't accept it with a
21503 vector predication code. */
21504 if (opcode
&& !opcode
->mayBeVecPred
)
21507 if (!opcode
|| !cond
)
21509 /* Cannot have a conditional suffix on a mnemonic of less than two
21511 if (end
- base
< 3)
21514 /* Look for suffixed mnemonic. */
21516 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21517 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21521 if (opcode
&& cond
)
21524 switch (opcode
->tag
)
21526 case OT_cinfix3_legacy
:
21527 /* Ignore conditional suffixes matched on infix only mnemonics. */
21531 case OT_cinfix3_deprecated
:
21532 case OT_odd_infix_unc
:
21533 if (!unified_syntax
)
21535 /* Fall through. */
21539 case OT_csuf_or_in3
:
21540 inst
.cond
= cond
->value
;
21543 case OT_unconditional
:
21544 case OT_unconditionalF
:
21546 inst
.cond
= cond
->value
;
21549 /* Delayed diagnostic. */
21550 inst
.error
= BAD_COND
;
21551 inst
.cond
= COND_ALWAYS
;
21560 /* Cannot have a usual-position infix on a mnemonic of less than
21561 six characters (five would be a suffix). */
21562 if (end
- base
< 6)
21565 /* Look for infixed mnemonic in the usual position. */
21567 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21571 memcpy (save
, affix
, 2);
21572 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21573 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21575 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21576 memcpy (affix
, save
, 2);
21579 && (opcode
->tag
== OT_cinfix3
21580 || opcode
->tag
== OT_cinfix3_deprecated
21581 || opcode
->tag
== OT_csuf_or_in3
21582 || opcode
->tag
== OT_cinfix3_legacy
))
21585 if (warn_on_deprecated
&& unified_syntax
21586 && (opcode
->tag
== OT_cinfix3
21587 || opcode
->tag
== OT_cinfix3_deprecated
))
21588 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21590 inst
.cond
= cond
->value
;
21597 /* This function generates an initial IT instruction, leaving its block
21598 virtually open for the new instructions. Eventually,
21599 the mask will be updated by now_pred_add_mask () each time
21600 a new instruction needs to be included in the IT block.
21601 Finally, the block is closed with close_automatic_it_block ().
21602 The block closure can be requested either from md_assemble (),
21603 a tencode (), or due to a label hook. */
21606 new_automatic_it_block (int cond
)
21608 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21609 now_pred
.mask
= 0x18;
21610 now_pred
.cc
= cond
;
21611 now_pred
.block_length
= 1;
21612 mapping_state (MAP_THUMB
);
21613 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21614 now_pred
.warn_deprecated
= FALSE
;
21615 now_pred
.insn_cond
= TRUE
;
21618 /* Close an automatic IT block.
21619 See comments in new_automatic_it_block (). */
21622 close_automatic_it_block (void)
21624 now_pred
.mask
= 0x10;
21625 now_pred
.block_length
= 0;
21628 /* Update the mask of the current automatically-generated IT
21629 instruction. See comments in new_automatic_it_block (). */
21632 now_pred_add_mask (int cond
)
21634 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21635 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21636 | ((bitvalue) << (nbit)))
21637 const int resulting_bit
= (cond
& 1);
21639 now_pred
.mask
&= 0xf;
21640 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21642 (5 - now_pred
.block_length
));
21643 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21645 ((5 - now_pred
.block_length
) - 1));
21646 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21649 #undef SET_BIT_VALUE
21652 /* The IT blocks handling machinery is accessed through the these functions:
21653 it_fsm_pre_encode () from md_assemble ()
21654 set_pred_insn_type () optional, from the tencode functions
21655 set_pred_insn_type_last () ditto
21656 in_pred_block () ditto
21657 it_fsm_post_encode () from md_assemble ()
21658 force_automatic_it_block_close () from label handling functions
21661 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21662 initializing the IT insn type with a generic initial value depending
21663 on the inst.condition.
21664 2) During the tencode function, two things may happen:
21665 a) The tencode function overrides the IT insn type by
21666 calling either set_pred_insn_type (type) or
21667 set_pred_insn_type_last ().
21668 b) The tencode function queries the IT block state by
21669 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21671 Both set_pred_insn_type and in_pred_block run the internal FSM state
21672 handling function (handle_pred_state), because: a) setting the IT insn
21673 type may incur in an invalid state (exiting the function),
21674 and b) querying the state requires the FSM to be updated.
21675 Specifically we want to avoid creating an IT block for conditional
21676 branches, so it_fsm_pre_encode is actually a guess and we can't
21677 determine whether an IT block is required until the tencode () routine
21678 has decided what type of instruction this actually it.
21679 Because of this, if set_pred_insn_type and in_pred_block have to be
21680 used, set_pred_insn_type has to be called first.
21682 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21683 that determines the insn IT type depending on the inst.cond code.
21684 When a tencode () routine encodes an instruction that can be
21685 either outside an IT block, or, in the case of being inside, has to be
21686 the last one, set_pred_insn_type_last () will determine the proper
21687 IT instruction type based on the inst.cond code. Otherwise,
21688 set_pred_insn_type can be called for overriding that logic or
21689 for covering other cases.
21691 Calling handle_pred_state () may not transition the IT block state to
21692 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21693 still queried. Instead, if the FSM determines that the state should
21694 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21695 after the tencode () function: that's what it_fsm_post_encode () does.
21697 Since in_pred_block () calls the state handling function to get an
21698 updated state, an error may occur (due to invalid insns combination).
21699 In that case, inst.error is set.
21700 Therefore, inst.error has to be checked after the execution of
21701 the tencode () routine.
21703 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21704 any pending state change (if any) that didn't take place in
21705 handle_pred_state () as explained above. */
21708 it_fsm_pre_encode (void)
21710 if (inst
.cond
!= COND_ALWAYS
)
21711 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21713 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21715 now_pred
.state_handled
= 0;
21718 /* IT state FSM handling function. */
21719 /* MVE instructions and non-MVE instructions are handled differently because of
21720 the introduction of VPT blocks.
21721 Specifications say that any non-MVE instruction inside a VPT block is
21722 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21723 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21724 few exceptions we have MVE_UNPREDICABLE_INSN.
21725 The error messages provided depending on the different combinations possible
21726 are described in the cases below:
21727 For 'most' MVE instructions:
21728 1) In an IT block, with an IT code: syntax error
21729 2) In an IT block, with a VPT code: error: must be in a VPT block
21730 3) In an IT block, with no code: warning: UNPREDICTABLE
21731 4) In a VPT block, with an IT code: syntax error
21732 5) In a VPT block, with a VPT code: OK!
21733 6) In a VPT block, with no code: error: missing code
21734 7) Outside a pred block, with an IT code: error: syntax error
21735 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21736 9) Outside a pred block, with no code: OK!
21737 For non-MVE instructions:
21738 10) In an IT block, with an IT code: OK!
21739 11) In an IT block, with a VPT code: syntax error
21740 12) In an IT block, with no code: error: missing code
21741 13) In a VPT block, with an IT code: error: should be in an IT block
21742 14) In a VPT block, with a VPT code: syntax error
21743 15) In a VPT block, with no code: UNPREDICTABLE
21744 16) Outside a pred block, with an IT code: error: should be in an IT block
21745 17) Outside a pred block, with a VPT code: syntax error
21746 18) Outside a pred block, with no code: OK!
21751 handle_pred_state (void)
21753 now_pred
.state_handled
= 1;
21754 now_pred
.insn_cond
= FALSE
;
21756 switch (now_pred
.state
)
21758 case OUTSIDE_PRED_BLOCK
:
21759 switch (inst
.pred_insn_type
)
21761 case MVE_UNPREDICABLE_INSN
:
21762 case MVE_OUTSIDE_PRED_INSN
:
21763 if (inst
.cond
< COND_ALWAYS
)
21765 /* Case 7: Outside a pred block, with an IT code: error: syntax
21767 inst
.error
= BAD_SYNTAX
;
21770 /* Case 9: Outside a pred block, with no code: OK! */
21772 case OUTSIDE_PRED_INSN
:
21773 if (inst
.cond
> COND_ALWAYS
)
21775 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21777 inst
.error
= BAD_SYNTAX
;
21780 /* Case 18: Outside a pred block, with no code: OK! */
21783 case INSIDE_VPT_INSN
:
21784 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21786 inst
.error
= BAD_OUT_VPT
;
21789 case INSIDE_IT_INSN
:
21790 case INSIDE_IT_LAST_INSN
:
21791 if (inst
.cond
< COND_ALWAYS
)
21793 /* Case 16: Outside a pred block, with an IT code: error: should
21794 be in an IT block. */
21795 if (thumb_mode
== 0)
21798 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21799 as_tsktsk (_("Warning: conditional outside an IT block"\
21804 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21805 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21807 /* Automatically generate the IT instruction. */
21808 new_automatic_it_block (inst
.cond
);
21809 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21810 close_automatic_it_block ();
21814 inst
.error
= BAD_OUT_IT
;
21820 else if (inst
.cond
> COND_ALWAYS
)
21822 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21824 inst
.error
= BAD_SYNTAX
;
21829 case IF_INSIDE_IT_LAST_INSN
:
21830 case NEUTRAL_IT_INSN
:
21834 if (inst
.cond
!= COND_ALWAYS
)
21835 first_error (BAD_SYNTAX
);
21836 now_pred
.state
= MANUAL_PRED_BLOCK
;
21837 now_pred
.block_length
= 0;
21838 now_pred
.type
= VECTOR_PRED
;
21842 now_pred
.state
= MANUAL_PRED_BLOCK
;
21843 now_pred
.block_length
= 0;
21844 now_pred
.type
= SCALAR_PRED
;
21849 case AUTOMATIC_PRED_BLOCK
:
21850 /* Three things may happen now:
21851 a) We should increment current it block size;
21852 b) We should close current it block (closing insn or 4 insns);
21853 c) We should close current it block and start a new one (due
21854 to incompatible conditions or
21855 4 insns-length block reached). */
21857 switch (inst
.pred_insn_type
)
21859 case INSIDE_VPT_INSN
:
21861 case MVE_UNPREDICABLE_INSN
:
21862 case MVE_OUTSIDE_PRED_INSN
:
21864 case OUTSIDE_PRED_INSN
:
21865 /* The closure of the block shall happen immediately,
21866 so any in_pred_block () call reports the block as closed. */
21867 force_automatic_it_block_close ();
21870 case INSIDE_IT_INSN
:
21871 case INSIDE_IT_LAST_INSN
:
21872 case IF_INSIDE_IT_LAST_INSN
:
21873 now_pred
.block_length
++;
21875 if (now_pred
.block_length
> 4
21876 || !now_pred_compatible (inst
.cond
))
21878 force_automatic_it_block_close ();
21879 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21880 new_automatic_it_block (inst
.cond
);
21884 now_pred
.insn_cond
= TRUE
;
21885 now_pred_add_mask (inst
.cond
);
21888 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21889 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21890 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21891 close_automatic_it_block ();
21894 case NEUTRAL_IT_INSN
:
21895 now_pred
.block_length
++;
21896 now_pred
.insn_cond
= TRUE
;
21898 if (now_pred
.block_length
> 4)
21899 force_automatic_it_block_close ();
21901 now_pred_add_mask (now_pred
.cc
& 1);
21905 close_automatic_it_block ();
21906 now_pred
.state
= MANUAL_PRED_BLOCK
;
21911 case MANUAL_PRED_BLOCK
:
21914 if (now_pred
.type
== SCALAR_PRED
)
21916 /* Check conditional suffixes. */
21917 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21918 now_pred
.mask
<<= 1;
21919 now_pred
.mask
&= 0x1f;
21920 is_last
= (now_pred
.mask
== 0x10);
21924 now_pred
.cc
^= (now_pred
.mask
>> 4);
21925 cond
= now_pred
.cc
+ 0xf;
21926 now_pred
.mask
<<= 1;
21927 now_pred
.mask
&= 0x1f;
21928 is_last
= now_pred
.mask
== 0x10;
21930 now_pred
.insn_cond
= TRUE
;
21932 switch (inst
.pred_insn_type
)
21934 case OUTSIDE_PRED_INSN
:
21935 if (now_pred
.type
== SCALAR_PRED
)
21937 if (inst
.cond
== COND_ALWAYS
)
21939 /* Case 12: In an IT block, with no code: error: missing
21941 inst
.error
= BAD_NOT_IT
;
21944 else if (inst
.cond
> COND_ALWAYS
)
21946 /* Case 11: In an IT block, with a VPT code: syntax error.
21948 inst
.error
= BAD_SYNTAX
;
21951 else if (thumb_mode
)
21953 /* This is for some special cases where a non-MVE
21954 instruction is not allowed in an IT block, such as cbz,
21955 but are put into one with a condition code.
21956 You could argue this should be a syntax error, but we
21957 gave the 'not allowed in IT block' diagnostic in the
21958 past so we will keep doing so. */
21959 inst
.error
= BAD_NOT_IT
;
21966 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21967 as_tsktsk (MVE_NOT_VPT
);
21970 case MVE_OUTSIDE_PRED_INSN
:
21971 if (now_pred
.type
== SCALAR_PRED
)
21973 if (inst
.cond
== COND_ALWAYS
)
21975 /* Case 3: In an IT block, with no code: warning:
21977 as_tsktsk (MVE_NOT_IT
);
21980 else if (inst
.cond
< COND_ALWAYS
)
21982 /* Case 1: In an IT block, with an IT code: syntax error.
21984 inst
.error
= BAD_SYNTAX
;
21992 if (inst
.cond
< COND_ALWAYS
)
21994 /* Case 4: In a VPT block, with an IT code: syntax error.
21996 inst
.error
= BAD_SYNTAX
;
21999 else if (inst
.cond
== COND_ALWAYS
)
22001 /* Case 6: In a VPT block, with no code: error: missing
22003 inst
.error
= BAD_NOT_VPT
;
22011 case MVE_UNPREDICABLE_INSN
:
22012 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22014 case INSIDE_IT_INSN
:
22015 if (inst
.cond
> COND_ALWAYS
)
22017 /* Case 11: In an IT block, with a VPT code: syntax error. */
22018 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22019 inst
.error
= BAD_SYNTAX
;
22022 else if (now_pred
.type
== SCALAR_PRED
)
22024 /* Case 10: In an IT block, with an IT code: OK! */
22025 if (cond
!= inst
.cond
)
22027 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22034 /* Case 13: In a VPT block, with an IT code: error: should be
22036 inst
.error
= BAD_OUT_IT
;
22041 case INSIDE_VPT_INSN
:
22042 if (now_pred
.type
== SCALAR_PRED
)
22044 /* Case 2: In an IT block, with a VPT code: error: must be in a
22046 inst
.error
= BAD_OUT_VPT
;
22049 /* Case 5: In a VPT block, with a VPT code: OK! */
22050 else if (cond
!= inst
.cond
)
22052 inst
.error
= BAD_VPT_COND
;
22056 case INSIDE_IT_LAST_INSN
:
22057 case IF_INSIDE_IT_LAST_INSN
:
22058 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22060 /* Case 4: In a VPT block, with an IT code: syntax error. */
22061 /* Case 11: In an IT block, with a VPT code: syntax error. */
22062 inst
.error
= BAD_SYNTAX
;
22065 else if (cond
!= inst
.cond
)
22067 inst
.error
= BAD_IT_COND
;
22072 inst
.error
= BAD_BRANCH
;
22077 case NEUTRAL_IT_INSN
:
22078 /* The BKPT instruction is unconditional even in a IT or VPT
22083 if (now_pred
.type
== SCALAR_PRED
)
22085 inst
.error
= BAD_IT_IT
;
22088 /* fall through. */
22090 if (inst
.cond
== COND_ALWAYS
)
22092 /* Executing a VPT/VPST instruction inside an IT block or a
22093 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22095 if (now_pred
.type
== SCALAR_PRED
)
22096 as_tsktsk (MVE_NOT_IT
);
22098 as_tsktsk (MVE_NOT_VPT
);
22103 /* VPT/VPST do not accept condition codes. */
22104 inst
.error
= BAD_SYNTAX
;
22115 struct depr_insn_mask
22117 unsigned long pattern
;
22118 unsigned long mask
;
22119 const char* description
;
22122 /* List of 16-bit instruction patterns deprecated in an IT block in
22124 static const struct depr_insn_mask depr_it_insns
[] = {
22125 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22126 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22127 { 0xa000, 0xb800, N_("ADR") },
22128 { 0x4800, 0xf800, N_("Literal loads") },
22129 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22130 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22131 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22132 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22133 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22138 it_fsm_post_encode (void)
22142 if (!now_pred
.state_handled
)
22143 handle_pred_state ();
22145 if (now_pred
.insn_cond
22146 && !now_pred
.warn_deprecated
22147 && warn_on_deprecated
22148 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22149 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22151 if (inst
.instruction
>= 0x10000)
22153 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22154 "performance deprecated in ARMv8-A and ARMv8-R"));
22155 now_pred
.warn_deprecated
= TRUE
;
22159 const struct depr_insn_mask
*p
= depr_it_insns
;
22161 while (p
->mask
!= 0)
22163 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22165 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22166 "instructions of the following class are "
22167 "performance deprecated in ARMv8-A and "
22168 "ARMv8-R: %s"), p
->description
);
22169 now_pred
.warn_deprecated
= TRUE
;
22177 if (now_pred
.block_length
> 1)
22179 as_tsktsk (_("IT blocks containing more than one conditional "
22180 "instruction are performance deprecated in ARMv8-A and "
22182 now_pred
.warn_deprecated
= TRUE
;
22186 is_last
= (now_pred
.mask
== 0x10);
22189 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22195 force_automatic_it_block_close (void)
22197 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22199 close_automatic_it_block ();
22200 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22206 in_pred_block (void)
22208 if (!now_pred
.state_handled
)
22209 handle_pred_state ();
22211 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22214 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22215 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22216 here, hence the "known" in the function name. */
22219 known_t32_only_insn (const struct asm_opcode
*opcode
)
22221 /* Original Thumb-1 wide instruction. */
22222 if (opcode
->tencode
== do_t_blx
22223 || opcode
->tencode
== do_t_branch23
22224 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22225 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22228 /* Wide-only instruction added to ARMv8-M Baseline. */
22229 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22230 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22231 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22232 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22238 /* Whether wide instruction variant can be used if available for a valid OPCODE
22242 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22244 if (known_t32_only_insn (opcode
))
22247 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22248 of variant T3 of B.W is checked in do_t_branch. */
22249 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22250 && opcode
->tencode
== do_t_branch
)
22253 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22254 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22255 && opcode
->tencode
== do_t_mov_cmp
22256 /* Make sure CMP instruction is not affected. */
22257 && opcode
->aencode
== do_mov
)
22260 /* Wide instruction variants of all instructions with narrow *and* wide
22261 variants become available with ARMv6t2. Other opcodes are either
22262 narrow-only or wide-only and are thus available if OPCODE is valid. */
22263 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22266 /* OPCODE with narrow only instruction variant or wide variant not
22272 md_assemble (char *str
)
22275 const struct asm_opcode
* opcode
;
22277 /* Align the previous label if needed. */
22278 if (last_label_seen
!= NULL
)
22280 symbol_set_frag (last_label_seen
, frag_now
);
22281 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22282 S_SET_SEGMENT (last_label_seen
, now_seg
);
22285 memset (&inst
, '\0', sizeof (inst
));
22287 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22288 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22290 opcode
= opcode_lookup (&p
);
22293 /* It wasn't an instruction, but it might be a register alias of
22294 the form alias .req reg, or a Neon .dn/.qn directive. */
22295 if (! create_register_alias (str
, p
)
22296 && ! create_neon_reg_alias (str
, p
))
22297 as_bad (_("bad instruction `%s'"), str
);
22302 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22303 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22305 /* The value which unconditional instructions should have in place of the
22306 condition field. */
22307 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22311 arm_feature_set variant
;
22313 variant
= cpu_variant
;
22314 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22315 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22316 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22317 /* Check that this instruction is supported for this CPU. */
22318 if (!opcode
->tvariant
22319 || (thumb_mode
== 1
22320 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22322 if (opcode
->tencode
== do_t_swi
)
22323 as_bad (_("SVC is not permitted on this architecture"));
22325 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22328 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22329 && opcode
->tencode
!= do_t_branch
)
22331 as_bad (_("Thumb does not support conditional execution"));
22335 /* Two things are addressed here:
22336 1) Implicit require narrow instructions on Thumb-1.
22337 This avoids relaxation accidentally introducing Thumb-2
22339 2) Reject wide instructions in non Thumb-2 cores.
22341 Only instructions with narrow and wide variants need to be handled
22342 but selecting all non wide-only instructions is easier. */
22343 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22344 && !t32_insn_ok (variant
, opcode
))
22346 if (inst
.size_req
== 0)
22348 else if (inst
.size_req
== 4)
22350 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22351 as_bad (_("selected processor does not support 32bit wide "
22352 "variant of instruction `%s'"), str
);
22354 as_bad (_("selected processor does not support `%s' in "
22355 "Thumb-2 mode"), str
);
22360 inst
.instruction
= opcode
->tvalue
;
22362 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22364 /* Prepare the pred_insn_type for those encodings that don't set
22366 it_fsm_pre_encode ();
22368 opcode
->tencode ();
22370 it_fsm_post_encode ();
22373 if (!(inst
.error
|| inst
.relax
))
22375 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22376 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22377 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22379 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22384 /* Something has gone badly wrong if we try to relax a fixed size
22386 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22388 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22389 *opcode
->tvariant
);
22390 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22391 set those bits when Thumb-2 32-bit instructions are seen. The impact
22392 of relaxable instructions will be considered later after we finish all
22394 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22395 variant
= arm_arch_none
;
22397 variant
= cpu_variant
;
22398 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22399 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22402 check_neon_suffixes
;
22406 mapping_state (MAP_THUMB
);
22409 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22413 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22414 is_bx
= (opcode
->aencode
== do_bx
);
22416 /* Check that this instruction is supported for this CPU. */
22417 if (!(is_bx
&& fix_v4bx
)
22418 && !(opcode
->avariant
&&
22419 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22421 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22426 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22430 inst
.instruction
= opcode
->avalue
;
22431 if (opcode
->tag
== OT_unconditionalF
)
22432 inst
.instruction
|= 0xFU
<< 28;
22434 inst
.instruction
|= inst
.cond
<< 28;
22435 inst
.size
= INSN_SIZE
;
22436 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22438 it_fsm_pre_encode ();
22439 opcode
->aencode ();
22440 it_fsm_post_encode ();
22442 /* Arm mode bx is marked as both v4T and v5 because it's still required
22443 on a hypothetical non-thumb v5 core. */
22445 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22447 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22448 *opcode
->avariant
);
22450 check_neon_suffixes
;
22454 mapping_state (MAP_ARM
);
22459 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22467 check_pred_blocks_finished (void)
22472 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22473 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22474 == MANUAL_PRED_BLOCK
)
22476 if (now_pred
.type
== SCALAR_PRED
)
22477 as_warn (_("section '%s' finished with an open IT block."),
22480 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22484 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22486 if (now_pred
.type
== SCALAR_PRED
)
22487 as_warn (_("file finished with an open IT block."));
22489 as_warn (_("file finished with an open VPT/VPST block."));
22494 /* Various frobbings of labels and their addresses. */
22497 arm_start_line_hook (void)
22499 last_label_seen
= NULL
;
22503 arm_frob_label (symbolS
* sym
)
22505 last_label_seen
= sym
;
22507 ARM_SET_THUMB (sym
, thumb_mode
);
22509 #if defined OBJ_COFF || defined OBJ_ELF
22510 ARM_SET_INTERWORK (sym
, support_interwork
);
22513 force_automatic_it_block_close ();
22515 /* Note - do not allow local symbols (.Lxxx) to be labelled
22516 as Thumb functions. This is because these labels, whilst
22517 they exist inside Thumb code, are not the entry points for
22518 possible ARM->Thumb calls. Also, these labels can be used
22519 as part of a computed goto or switch statement. eg gcc
22520 can generate code that looks like this:
22522 ldr r2, [pc, .Laaa]
22532 The first instruction loads the address of the jump table.
22533 The second instruction converts a table index into a byte offset.
22534 The third instruction gets the jump address out of the table.
22535 The fourth instruction performs the jump.
22537 If the address stored at .Laaa is that of a symbol which has the
22538 Thumb_Func bit set, then the linker will arrange for this address
22539 to have the bottom bit set, which in turn would mean that the
22540 address computation performed by the third instruction would end
22541 up with the bottom bit set. Since the ARM is capable of unaligned
22542 word loads, the instruction would then load the incorrect address
22543 out of the jump table, and chaos would ensue. */
22544 if (label_is_thumb_function_name
22545 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22546 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22548 /* When the address of a Thumb function is taken the bottom
22549 bit of that address should be set. This will allow
22550 interworking between Arm and Thumb functions to work
22553 THUMB_SET_FUNC (sym
, 1);
22555 label_is_thumb_function_name
= FALSE
;
22558 dwarf2_emit_label (sym
);
22562 arm_data_in_code (void)
22564 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22566 *input_line_pointer
= '/';
22567 input_line_pointer
+= 5;
22568 *input_line_pointer
= 0;
22576 arm_canonicalize_symbol_name (char * name
)
22580 if (thumb_mode
&& (len
= strlen (name
)) > 5
22581 && streq (name
+ len
- 5, "/data"))
22582 *(name
+ len
- 5) = 0;
22587 /* Table of all register names defined by default. The user can
22588 define additional names with .req. Note that all register names
22589 should appear in both upper and lowercase variants. Some registers
22590 also have mixed-case names. */
22592 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22593 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22594 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22595 #define REGSET(p,t) \
22596 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22597 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22598 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22599 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22600 #define REGSETH(p,t) \
22601 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22602 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22603 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22604 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22605 #define REGSET2(p,t) \
22606 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22607 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22608 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22609 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22610 #define SPLRBANK(base,bank,t) \
22611 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22612 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22613 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22614 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22615 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22616 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22618 static const struct reg_entry reg_names
[] =
22620 /* ARM integer registers. */
22621 REGSET(r
, RN
), REGSET(R
, RN
),
22623 /* ATPCS synonyms. */
22624 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22625 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22626 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22628 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22629 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22630 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22632 /* Well-known aliases. */
22633 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22634 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22636 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22637 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22639 /* Defining the new Zero register from ARMv8.1-M. */
22643 /* Coprocessor numbers. */
22644 REGSET(p
, CP
), REGSET(P
, CP
),
22646 /* Coprocessor register numbers. The "cr" variants are for backward
22648 REGSET(c
, CN
), REGSET(C
, CN
),
22649 REGSET(cr
, CN
), REGSET(CR
, CN
),
22651 /* ARM banked registers. */
22652 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22653 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22654 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22655 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22656 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22657 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22658 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22660 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22661 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22662 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22663 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22664 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22665 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22666 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22667 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22669 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22670 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22671 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22672 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22673 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22674 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22675 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22676 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22677 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22679 /* FPA registers. */
22680 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22681 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22683 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22684 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22686 /* VFP SP registers. */
22687 REGSET(s
,VFS
), REGSET(S
,VFS
),
22688 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22690 /* VFP DP Registers. */
22691 REGSET(d
,VFD
), REGSET(D
,VFD
),
22692 /* Extra Neon DP registers. */
22693 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22695 /* Neon QP registers. */
22696 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22698 /* VFP control registers. */
22699 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22700 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22701 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22702 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22703 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22704 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22705 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22707 /* Maverick DSP coprocessor registers. */
22708 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22709 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22711 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22712 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22713 REGDEF(dspsc
,0,DSPSC
),
22715 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22716 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22717 REGDEF(DSPSC
,0,DSPSC
),
22719 /* iWMMXt data registers - p0, c0-15. */
22720 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22722 /* iWMMXt control registers - p1, c0-3. */
22723 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22724 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22725 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22726 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22728 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22729 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22730 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22731 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22732 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22734 /* XScale accumulator registers. */
22735 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22741 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22742 within psr_required_here. */
22743 static const struct asm_psr psrs
[] =
22745 /* Backward compatibility notation. Note that "all" is no longer
22746 truly all possible PSR bits. */
22747 {"all", PSR_c
| PSR_f
},
22751 /* Individual flags. */
22757 /* Combinations of flags. */
22758 {"fs", PSR_f
| PSR_s
},
22759 {"fx", PSR_f
| PSR_x
},
22760 {"fc", PSR_f
| PSR_c
},
22761 {"sf", PSR_s
| PSR_f
},
22762 {"sx", PSR_s
| PSR_x
},
22763 {"sc", PSR_s
| PSR_c
},
22764 {"xf", PSR_x
| PSR_f
},
22765 {"xs", PSR_x
| PSR_s
},
22766 {"xc", PSR_x
| PSR_c
},
22767 {"cf", PSR_c
| PSR_f
},
22768 {"cs", PSR_c
| PSR_s
},
22769 {"cx", PSR_c
| PSR_x
},
22770 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22771 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22772 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22773 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22774 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22775 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22776 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22777 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22778 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22779 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22780 {"scf", PSR_s
| PSR_c
| PSR_f
},
22781 {"scx", PSR_s
| PSR_c
| PSR_x
},
22782 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22783 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22784 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22785 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22786 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22787 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22788 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22789 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22790 {"csf", PSR_c
| PSR_s
| PSR_f
},
22791 {"csx", PSR_c
| PSR_s
| PSR_x
},
22792 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22793 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22794 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22795 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22796 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22797 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22798 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22799 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22800 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22801 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22802 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22803 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22804 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22805 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22806 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22807 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22808 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22809 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22810 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22811 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22812 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22813 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22814 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22815 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22816 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22817 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22820 /* Table of V7M psr names. */
22821 static const struct asm_psr v7m_psrs
[] =
22823 {"apsr", 0x0 }, {"APSR", 0x0 },
22824 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22825 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22826 {"psr", 0x3 }, {"PSR", 0x3 },
22827 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22828 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22829 {"epsr", 0x6 }, {"EPSR", 0x6 },
22830 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22831 {"msp", 0x8 }, {"MSP", 0x8 },
22832 {"psp", 0x9 }, {"PSP", 0x9 },
22833 {"msplim", 0xa }, {"MSPLIM", 0xa },
22834 {"psplim", 0xb }, {"PSPLIM", 0xb },
22835 {"primask", 0x10}, {"PRIMASK", 0x10},
22836 {"basepri", 0x11}, {"BASEPRI", 0x11},
22837 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22838 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22839 {"control", 0x14}, {"CONTROL", 0x14},
22840 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22841 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22842 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22843 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22844 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22845 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22846 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22847 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22848 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22851 /* Table of all shift-in-operand names. */
22852 static const struct asm_shift_name shift_names
[] =
22854 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22855 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22856 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22857 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22858 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22859 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22860 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22863 /* Table of all explicit relocation names. */
22865 static struct reloc_entry reloc_names
[] =
22867 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22868 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22869 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22870 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22871 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22872 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22873 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22874 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22875 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22876 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22877 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22878 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22879 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22880 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22881 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22882 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22883 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22884 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22885 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22886 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22887 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22888 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22889 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22890 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22891 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22892 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22893 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22897 /* Table of all conditional affixes. */
22898 static const struct asm_cond conds
[] =
22902 {"cs", 0x2}, {"hs", 0x2},
22903 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22916 static const struct asm_cond vconds
[] =
22922 #define UL_BARRIER(L,U,CODE,FEAT) \
22923 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22924 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22926 static struct asm_barrier_opt barrier_opt_names
[] =
22928 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22929 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22930 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22931 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22932 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22933 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22934 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22935 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22936 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22937 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22938 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22939 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22940 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22941 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22942 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22943 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22948 /* Table of ARM-format instructions. */
22950 /* Macros for gluing together operand strings. N.B. In all cases
22951 other than OPS0, the trailing OP_stop comes from default
22952 zero-initialization of the unspecified elements of the array. */
22953 #define OPS0() { OP_stop, }
22954 #define OPS1(a) { OP_##a, }
22955 #define OPS2(a,b) { OP_##a,OP_##b, }
22956 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22957 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22958 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22959 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22961 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22962 This is useful when mixing operands for ARM and THUMB, i.e. using the
22963 MIX_ARM_THUMB_OPERANDS macro.
22964 In order to use these macros, prefix the number of operands with _
22966 #define OPS_1(a) { a, }
22967 #define OPS_2(a,b) { a,b, }
22968 #define OPS_3(a,b,c) { a,b,c, }
22969 #define OPS_4(a,b,c,d) { a,b,c,d, }
22970 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22971 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22973 /* These macros abstract out the exact format of the mnemonic table and
22974 save some repeated characters. */
22976 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22977 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22978 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22979 THUMB_VARIANT, do_##ae, do_##te, 0 }
22981 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22982 a T_MNEM_xyz enumerator. */
22983 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22984 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22985 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22986 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22988 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22989 infix after the third character. */
22990 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22991 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22992 THUMB_VARIANT, do_##ae, do_##te, 0 }
22993 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22994 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
22995 THUMB_VARIANT, do_##ae, do_##te, 0 }
22996 #define TC3(mnem, aop, top, nops, ops, ae, te) \
22997 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
22998 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
22999 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23000 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23001 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23002 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23003 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23005 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23006 field is still 0xE. Many of the Thumb variants can be executed
23007 conditionally, so this is checked separately. */
23008 #define TUE(mnem, op, top, nops, ops, ae, te) \
23009 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23010 THUMB_VARIANT, do_##ae, do_##te, 0 }
23012 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23013 Used by mnemonics that have very minimal differences in the encoding for
23014 ARM and Thumb variants and can be handled in a common function. */
23015 #define TUEc(mnem, op, top, nops, ops, en) \
23016 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23017 THUMB_VARIANT, do_##en, do_##en, 0 }
23019 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23020 condition code field. */
23021 #define TUF(mnem, op, top, nops, ops, ae, te) \
23022 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23023 THUMB_VARIANT, do_##ae, do_##te, 0 }
23025 /* ARM-only variants of all the above. */
23026 #define CE(mnem, op, nops, ops, ae) \
23027 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23029 #define C3(mnem, op, nops, ops, ae) \
23030 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23032 /* Thumb-only variants of TCE and TUE. */
23033 #define ToC(mnem, top, nops, ops, te) \
23034 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23037 #define ToU(mnem, top, nops, ops, te) \
23038 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23041 /* T_MNEM_xyz enumerator variants of ToC. */
23042 #define toC(mnem, top, nops, ops, te) \
23043 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23046 /* T_MNEM_xyz enumerator variants of ToU. */
23047 #define toU(mnem, top, nops, ops, te) \
23048 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23051 /* Legacy mnemonics that always have conditional infix after the third
23053 #define CL(mnem, op, nops, ops, ae) \
23054 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23055 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23057 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23058 #define cCE(mnem, op, nops, ops, ae) \
23059 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23061 /* mov instructions that are shared between coprocessor and MVE. */
23062 #define mcCE(mnem, op, nops, ops, ae) \
23063 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23065 /* Legacy coprocessor instructions where conditional infix and conditional
23066 suffix are ambiguous. For consistency this includes all FPA instructions,
23067 not just the potentially ambiguous ones. */
23068 #define cCL(mnem, op, nops, ops, ae) \
23069 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23070 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23072 /* Coprocessor, takes either a suffix or a position-3 infix
23073 (for an FPA corner case). */
23074 #define C3E(mnem, op, nops, ops, ae) \
23075 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23076 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23078 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23079 { m1 #m2 m3, OPS##nops ops, \
23080 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23081 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23083 #define CM(m1, m2, op, nops, ops, ae) \
23084 xCM_ (m1, , m2, op, nops, ops, ae), \
23085 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23086 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23087 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23088 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23089 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23090 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23091 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23092 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23093 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23094 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23095 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23096 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23097 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23098 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23099 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23100 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23101 xCM_ (m1, le, m2, op, nops, ops, ae), \
23102 xCM_ (m1, al, m2, op, nops, ops, ae)
23104 #define UE(mnem, op, nops, ops, ae) \
23105 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23107 #define UF(mnem, op, nops, ops, ae) \
23108 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23110 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23111 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23112 use the same encoding function for each. */
23113 #define NUF(mnem, op, nops, ops, enc) \
23114 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23115 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23117 /* Neon data processing, version which indirects through neon_enc_tab for
23118 the various overloaded versions of opcodes. */
23119 #define nUF(mnem, op, nops, ops, enc) \
23120 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23121 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23123 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23125 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23126 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23127 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23129 #define NCE(mnem, op, nops, ops, enc) \
23130 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23132 #define NCEF(mnem, op, nops, ops, enc) \
23133 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23135 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23136 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23137 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23138 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23140 #define nCE(mnem, op, nops, ops, enc) \
23141 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23143 #define nCEF(mnem, op, nops, ops, enc) \
23144 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23147 #define mCEF(mnem, op, nops, ops, enc) \
23148 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23149 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23152 /* nCEF but for MVE predicated instructions. */
23153 #define mnCEF(mnem, op, nops, ops, enc) \
23154 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23156 /* nCE but for MVE predicated instructions. */
23157 #define mnCE(mnem, op, nops, ops, enc) \
23158 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23160 /* NUF but for potentially MVE predicated instructions. */
23161 #define MNUF(mnem, op, nops, ops, enc) \
23162 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23163 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23165 /* nUF but for potentially MVE predicated instructions. */
23166 #define mnUF(mnem, op, nops, ops, enc) \
23167 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23168 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23170 /* ToC but for potentially MVE predicated instructions. */
23171 #define mToC(mnem, top, nops, ops, te) \
23172 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23175 /* NCE but for MVE predicated instructions. */
23176 #define MNCE(mnem, op, nops, ops, enc) \
23177 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23179 /* NCEF but for MVE predicated instructions. */
23180 #define MNCEF(mnem, op, nops, ops, enc) \
23181 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23184 static const struct asm_opcode insns
[] =
23186 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23187 #define THUMB_VARIANT & arm_ext_v4t
23188 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23189 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23190 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23191 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23192 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23193 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23194 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23195 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23196 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23197 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23198 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23199 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23200 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23201 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23202 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23203 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23205 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23206 for setting PSR flag bits. They are obsolete in V6 and do not
23207 have Thumb equivalents. */
23208 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23209 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23210 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23211 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23212 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23213 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23214 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23215 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23216 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23218 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23219 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23220 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23221 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23223 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23224 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23225 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23227 OP_ADDRGLDR
),ldst
, t_ldst
),
23228 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23230 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23231 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23232 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23233 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23234 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23235 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23237 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23238 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23241 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23242 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23243 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23244 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23246 /* Thumb-compatibility pseudo ops. */
23247 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23248 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23249 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23250 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23251 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23252 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23253 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23254 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23255 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23256 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23257 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23258 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23260 /* These may simplify to neg. */
23261 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23262 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23264 #undef THUMB_VARIANT
23265 #define THUMB_VARIANT & arm_ext_os
23267 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23268 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23270 #undef THUMB_VARIANT
23271 #define THUMB_VARIANT & arm_ext_v6
23273 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23275 /* V1 instructions with no Thumb analogue prior to V6T2. */
23276 #undef THUMB_VARIANT
23277 #define THUMB_VARIANT & arm_ext_v6t2
23279 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23280 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23281 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23283 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23284 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23285 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23286 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23288 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23289 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23291 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23292 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23294 /* V1 instructions with no Thumb analogue at all. */
23295 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23296 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23298 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23299 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23300 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23301 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23302 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23303 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23304 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23305 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23308 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23309 #undef THUMB_VARIANT
23310 #define THUMB_VARIANT & arm_ext_v4t
23312 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23313 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23315 #undef THUMB_VARIANT
23316 #define THUMB_VARIANT & arm_ext_v6t2
23318 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23319 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23321 /* Generic coprocessor instructions. */
23322 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23323 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23324 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23325 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23326 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23327 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23328 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23331 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23333 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23334 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23337 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23338 #undef THUMB_VARIANT
23339 #define THUMB_VARIANT & arm_ext_msr
23341 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23342 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23345 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23346 #undef THUMB_VARIANT
23347 #define THUMB_VARIANT & arm_ext_v6t2
23349 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23350 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23351 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23352 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23353 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23354 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23355 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23356 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23359 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23360 #undef THUMB_VARIANT
23361 #define THUMB_VARIANT & arm_ext_v4t
23363 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23364 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23365 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23366 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23367 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23368 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23371 #define ARM_VARIANT & arm_ext_v4t_5
23373 /* ARM Architecture 4T. */
23374 /* Note: bx (and blx) are required on V5, even if the processor does
23375 not support Thumb. */
23376 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23379 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23380 #undef THUMB_VARIANT
23381 #define THUMB_VARIANT & arm_ext_v5t
23383 /* Note: blx has 2 variants; the .value coded here is for
23384 BLX(2). Only this variant has conditional execution. */
23385 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23386 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23388 #undef THUMB_VARIANT
23389 #define THUMB_VARIANT & arm_ext_v6t2
23391 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23392 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23393 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23394 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23395 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23396 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23397 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23398 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23401 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23402 #undef THUMB_VARIANT
23403 #define THUMB_VARIANT & arm_ext_v5exp
23405 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23406 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23407 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23408 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23410 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23411 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23413 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23414 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23415 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23416 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23418 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23419 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23420 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23421 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23423 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23424 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23426 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23427 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23428 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23429 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23432 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23433 #undef THUMB_VARIANT
23434 #define THUMB_VARIANT & arm_ext_v6t2
23436 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23437 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23439 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23440 ADDRGLDRS
), ldrd
, t_ldstd
),
23442 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23443 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23446 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23448 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23451 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23452 #undef THUMB_VARIANT
23453 #define THUMB_VARIANT & arm_ext_v6
23455 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23456 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23457 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23458 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23459 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23460 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23461 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23462 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23463 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23464 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23466 #undef THUMB_VARIANT
23467 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23469 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23470 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23472 #undef THUMB_VARIANT
23473 #define THUMB_VARIANT & arm_ext_v6t2
23475 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23476 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23478 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23479 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23481 /* ARM V6 not included in V7M. */
23482 #undef THUMB_VARIANT
23483 #define THUMB_VARIANT & arm_ext_v6_notm
23484 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23485 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23486 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23487 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23488 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23489 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23490 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23491 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23492 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23493 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23494 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23495 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23496 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23497 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23498 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23499 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23500 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23501 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23502 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23504 /* ARM V6 not included in V7M (eg. integer SIMD). */
23505 #undef THUMB_VARIANT
23506 #define THUMB_VARIANT & arm_ext_v6_dsp
23507 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23508 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23509 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23510 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23511 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23512 /* Old name for QASX. */
23513 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23514 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23515 /* Old name for QSAX. */
23516 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23517 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23518 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23519 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23520 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23521 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23522 /* Old name for SASX. */
23523 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23524 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23525 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23526 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23527 /* Old name for SHASX. */
23528 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23529 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23530 /* Old name for SHSAX. */
23531 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23532 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23533 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23534 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23535 /* Old name for SSAX. */
23536 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23537 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23538 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23539 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23540 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23541 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23542 /* Old name for UASX. */
23543 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23544 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23545 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23546 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23547 /* Old name for UHASX. */
23548 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23549 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23550 /* Old name for UHSAX. */
23551 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23552 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23553 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23554 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23555 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23556 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23557 /* Old name for UQASX. */
23558 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23559 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23560 /* Old name for UQSAX. */
23561 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23562 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23563 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23564 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23565 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23566 /* Old name for USAX. */
23567 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23568 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23569 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23570 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23571 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23572 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23573 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23574 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23575 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23576 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23577 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23578 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23579 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23580 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23581 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23582 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23583 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23584 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23585 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23586 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23587 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23588 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23589 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23590 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23591 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23592 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23593 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23594 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23595 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23596 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23597 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23598 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23599 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23600 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23603 #define ARM_VARIANT & arm_ext_v6k_v6t2
23604 #undef THUMB_VARIANT
23605 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23607 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23608 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23609 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23610 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23612 #undef THUMB_VARIANT
23613 #define THUMB_VARIANT & arm_ext_v6_notm
23614 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23616 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23617 RRnpcb
), strexd
, t_strexd
),
23619 #undef THUMB_VARIANT
23620 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23621 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23623 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23625 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23627 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23629 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23632 #define ARM_VARIANT & arm_ext_sec
23633 #undef THUMB_VARIANT
23634 #define THUMB_VARIANT & arm_ext_sec
23636 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23639 #define ARM_VARIANT & arm_ext_virt
23640 #undef THUMB_VARIANT
23641 #define THUMB_VARIANT & arm_ext_virt
23643 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23644 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23647 #define ARM_VARIANT & arm_ext_pan
23648 #undef THUMB_VARIANT
23649 #define THUMB_VARIANT & arm_ext_pan
23651 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23654 #define ARM_VARIANT & arm_ext_v6t2
23655 #undef THUMB_VARIANT
23656 #define THUMB_VARIANT & arm_ext_v6t2
23658 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23659 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23660 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23661 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23663 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23664 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23666 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23667 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23668 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23669 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23672 #define ARM_VARIANT & arm_ext_v3
23673 #undef THUMB_VARIANT
23674 #define THUMB_VARIANT & arm_ext_v6t2
23676 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23677 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23678 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23681 #define ARM_VARIANT & arm_ext_v6t2
23682 #undef THUMB_VARIANT
23683 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23684 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23685 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23687 /* Thumb-only instructions. */
23689 #define ARM_VARIANT NULL
23690 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23691 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23693 /* ARM does not really have an IT instruction, so always allow it.
23694 The opcode is copied from Thumb in order to allow warnings in
23695 -mimplicit-it=[never | arm] modes. */
23697 #define ARM_VARIANT & arm_ext_v1
23698 #undef THUMB_VARIANT
23699 #define THUMB_VARIANT & arm_ext_v6t2
23701 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23702 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23703 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23704 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23705 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23706 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23707 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23708 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23709 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23710 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23711 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23712 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23713 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23714 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23715 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23716 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23717 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23718 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23720 /* Thumb2 only instructions. */
23722 #define ARM_VARIANT NULL
23724 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23725 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23726 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23727 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23728 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23729 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23731 /* Hardware division instructions. */
23733 #define ARM_VARIANT & arm_ext_adiv
23734 #undef THUMB_VARIANT
23735 #define THUMB_VARIANT & arm_ext_div
23737 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23738 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23740 /* ARM V6M/V7 instructions. */
23742 #define ARM_VARIANT & arm_ext_barrier
23743 #undef THUMB_VARIANT
23744 #define THUMB_VARIANT & arm_ext_barrier
23746 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23747 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23748 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23750 /* ARM V7 instructions. */
23752 #define ARM_VARIANT & arm_ext_v7
23753 #undef THUMB_VARIANT
23754 #define THUMB_VARIANT & arm_ext_v7
23756 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23757 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23760 #define ARM_VARIANT & arm_ext_mp
23761 #undef THUMB_VARIANT
23762 #define THUMB_VARIANT & arm_ext_mp
23764 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23766 /* AArchv8 instructions. */
23768 #define ARM_VARIANT & arm_ext_v8
23770 /* Instructions shared between armv8-a and armv8-m. */
23771 #undef THUMB_VARIANT
23772 #define THUMB_VARIANT & arm_ext_atomics
23774 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23775 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23776 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23777 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23778 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23779 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23780 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23781 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23782 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23783 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23785 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23787 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23789 #undef THUMB_VARIANT
23790 #define THUMB_VARIANT & arm_ext_v8
23792 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23793 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23795 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23798 /* Defined in V8 but is in undefined encoding space for earlier
23799 architectures. However earlier architectures are required to treat
23800 this instuction as a semihosting trap as well. Hence while not explicitly
23801 defined as such, it is in fact correct to define the instruction for all
23803 #undef THUMB_VARIANT
23804 #define THUMB_VARIANT & arm_ext_v1
23806 #define ARM_VARIANT & arm_ext_v1
23807 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23809 /* ARMv8 T32 only. */
23811 #define ARM_VARIANT NULL
23812 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23813 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23814 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23816 /* FP for ARMv8. */
23818 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23819 #undef THUMB_VARIANT
23820 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23822 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23823 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23824 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23825 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23826 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23827 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23828 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23829 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23830 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23831 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23832 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23834 /* Crypto v1 extensions. */
23836 #define ARM_VARIANT & fpu_crypto_ext_armv8
23837 #undef THUMB_VARIANT
23838 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23840 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23841 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23842 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23843 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23844 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23845 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23846 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23847 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23848 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23849 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23850 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23851 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23852 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23853 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23856 #define ARM_VARIANT & crc_ext_armv8
23857 #undef THUMB_VARIANT
23858 #define THUMB_VARIANT & crc_ext_armv8
23859 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23860 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23861 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23862 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23863 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23864 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23866 /* ARMv8.2 RAS extension. */
23868 #define ARM_VARIANT & arm_ext_ras
23869 #undef THUMB_VARIANT
23870 #define THUMB_VARIANT & arm_ext_ras
23871 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23874 #define ARM_VARIANT & arm_ext_v8_3
23875 #undef THUMB_VARIANT
23876 #define THUMB_VARIANT & arm_ext_v8_3
23877 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23880 #define ARM_VARIANT & fpu_neon_ext_dotprod
23881 #undef THUMB_VARIANT
23882 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23883 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23884 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23887 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23888 #undef THUMB_VARIANT
23889 #define THUMB_VARIANT NULL
23891 cCE("wfs", e200110
, 1, (RR
), rd
),
23892 cCE("rfs", e300110
, 1, (RR
), rd
),
23893 cCE("wfc", e400110
, 1, (RR
), rd
),
23894 cCE("rfc", e500110
, 1, (RR
), rd
),
23896 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23897 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23898 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23899 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23901 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23902 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23903 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23904 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23906 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23907 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23908 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23909 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23910 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23911 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23912 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23913 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23914 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23915 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23916 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23917 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23919 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23920 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23921 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23922 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23923 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23924 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23925 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23926 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23927 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23928 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23929 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23930 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23932 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23933 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23934 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23935 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23936 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23937 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23938 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23939 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23940 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23941 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23942 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23943 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23945 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23946 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23947 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23948 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23949 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23950 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23951 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23952 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23953 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23954 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23955 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23956 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23958 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23959 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23960 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23961 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23962 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23963 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23964 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23965 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23966 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23967 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23968 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23969 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23971 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23972 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23973 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23974 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23975 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23976 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23977 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23978 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23979 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23980 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23981 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23982 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23984 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23985 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23986 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23987 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23988 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23989 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23990 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23991 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23992 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23993 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23994 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
23995 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
23997 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
23998 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
23999 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24000 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24001 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24002 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24003 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24004 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24005 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24006 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24007 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24008 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24010 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24011 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24012 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24013 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24014 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24015 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24016 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24017 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24018 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24019 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24020 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24021 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24023 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24024 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24025 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24026 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24027 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24028 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24029 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24030 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24031 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24032 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24033 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24034 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24036 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24037 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24038 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24039 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24040 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24041 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24042 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24043 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24044 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24045 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24046 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24047 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24049 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24050 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24051 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24052 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24053 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24054 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24055 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24056 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24057 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24058 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24059 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24060 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24062 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24063 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24064 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24065 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24066 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24067 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24068 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24069 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24070 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24071 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24072 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24073 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24075 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24076 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24077 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24078 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24079 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24080 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24081 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24082 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24083 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24084 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24085 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24086 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24088 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24089 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24090 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24091 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24092 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24093 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24094 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24095 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24096 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24097 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24098 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24099 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24101 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24102 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24103 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24104 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24105 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24106 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24107 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24108 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24109 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24110 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24111 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24112 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24114 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24115 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24116 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24117 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24118 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24119 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24120 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24121 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24122 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24123 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24124 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24125 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24127 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24128 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24129 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24130 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24131 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24132 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24133 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24134 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24135 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24136 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24137 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24138 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24140 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24141 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24142 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24143 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24144 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24145 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24146 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24147 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24148 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24149 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24150 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24151 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24153 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24154 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24155 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24156 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24157 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24158 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24159 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24160 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24161 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24162 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24163 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24164 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24166 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24167 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24168 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24169 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24170 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24171 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24172 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24173 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24174 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24175 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24176 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24177 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24179 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24180 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24181 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24182 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24183 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24184 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24185 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24186 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24187 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24188 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24189 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24190 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24192 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24193 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24194 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24195 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24196 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24197 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24198 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24199 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24200 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24201 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24202 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24203 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24205 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24206 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24207 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24208 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24209 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24210 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24211 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24212 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24213 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24214 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24215 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24216 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24218 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24219 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24220 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24221 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24222 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24223 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24224 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24225 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24226 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24227 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24228 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24229 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24231 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24232 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24233 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24234 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24235 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24236 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24237 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24238 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24239 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24240 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24241 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24242 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24244 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24245 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24246 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24247 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24248 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24249 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24250 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24251 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24252 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24253 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24254 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24255 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24257 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24258 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24259 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24260 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24261 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24262 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24263 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24264 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24265 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24266 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24267 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24268 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24270 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24271 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24272 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24273 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24274 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24275 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24276 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24277 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24278 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24279 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24280 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24281 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24283 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24284 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24285 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24286 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24288 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24289 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24290 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24291 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24292 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24293 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24294 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24295 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24296 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24297 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24298 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24299 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24301 /* The implementation of the FIX instruction is broken on some
24302 assemblers, in that it accepts a precision specifier as well as a
24303 rounding specifier, despite the fact that this is meaningless.
24304 To be more compatible, we accept it as well, though of course it
24305 does not set any bits. */
24306 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24307 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24308 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24309 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24310 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24311 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24312 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24313 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24314 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24315 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24316 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24317 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24318 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24320 /* Instructions that were new with the real FPA, call them V2. */
24322 #define ARM_VARIANT & fpu_fpa_ext_v2
24324 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24325 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24326 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24327 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24328 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24329 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24332 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24334 /* Moves and type conversions. */
24335 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24336 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24337 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24338 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24339 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24340 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24341 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24342 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24343 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24344 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24345 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24347 /* Memory operations. */
24348 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24349 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24350 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24351 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24352 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24353 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24354 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24355 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24356 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24357 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24358 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24359 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24360 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24361 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24362 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24363 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24364 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24365 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24367 /* Monadic operations. */
24368 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24369 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24370 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24372 /* Dyadic operations. */
24373 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24374 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24375 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24376 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24377 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24378 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24379 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24380 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24381 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24384 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24385 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24386 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24387 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24389 /* Double precision load/store are still present on single precision
24390 implementations. */
24391 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24392 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24393 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24394 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24395 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24396 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24397 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24398 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24399 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24400 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24403 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24405 /* Moves and type conversions. */
24406 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24407 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24408 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24409 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24410 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24411 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24412 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24413 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24414 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24415 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24416 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24417 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24419 /* Monadic operations. */
24420 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24421 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24422 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24424 /* Dyadic operations. */
24425 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24426 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24427 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24428 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24429 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24430 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24431 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24432 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24433 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24436 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24437 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24438 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24439 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24441 /* Instructions which may belong to either the Neon or VFP instruction sets.
24442 Individual encoder functions perform additional architecture checks. */
24444 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24445 #undef THUMB_VARIANT
24446 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24448 /* These mnemonics are unique to VFP. */
24449 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24450 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24451 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24452 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24453 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24454 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24455 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24456 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24458 /* Mnemonics shared by Neon and VFP. */
24459 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24461 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24462 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24463 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24464 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24465 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24466 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24468 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24469 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24470 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24471 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24474 /* NOTE: All VMOV encoding is special-cased! */
24475 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24477 #undef THUMB_VARIANT
24478 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24479 by different feature bits. Since we are setting the Thumb guard, we can
24480 require Thumb-1 which makes it a nop guard and set the right feature bit in
24481 do_vldr_vstr (). */
24482 #define THUMB_VARIANT & arm_ext_v4t
24483 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24484 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24487 #define ARM_VARIANT & arm_ext_fp16
24488 #undef THUMB_VARIANT
24489 #define THUMB_VARIANT & arm_ext_fp16
24490 /* New instructions added from v8.2, allowing the extraction and insertion of
24491 the upper 16 bits of a 32-bit vector register. */
24492 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24493 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24495 /* New backported fma/fms instructions optional in v8.2. */
24496 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24497 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24499 #undef THUMB_VARIANT
24500 #define THUMB_VARIANT & fpu_neon_ext_v1
24502 #define ARM_VARIANT & fpu_neon_ext_v1
24504 /* Data processing with three registers of the same length. */
24505 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24506 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24507 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24508 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24509 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24510 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24511 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24512 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24513 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24514 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24515 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24516 /* If not immediate, fall back to neon_dyadic_i64_su.
24517 shl should accept I8 I16 I32 I64,
24518 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24519 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24520 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24521 /* Logic ops, types optional & ignored. */
24522 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24523 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24524 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24525 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24526 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24527 /* Bitfield ops, untyped. */
24528 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24529 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24530 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24531 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24532 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24533 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24534 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24535 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24536 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24537 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24538 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24539 back to neon_dyadic_if_su. */
24540 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24541 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24542 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24543 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24544 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24545 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24546 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24547 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24548 /* Comparison. Type I8 I16 I32 F32. */
24549 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24550 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24551 /* As above, D registers only. */
24552 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24553 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24554 /* Int and float variants, signedness unimportant. */
24555 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24556 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24557 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24558 /* Add/sub take types I8 I16 I32 I64 F32. */
24559 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24560 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24561 /* vtst takes sizes 8, 16, 32. */
24562 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24563 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24564 /* VMUL takes I8 I16 I32 F32 P8. */
24565 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24566 /* VQD{R}MULH takes S16 S32. */
24567 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24568 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24569 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24570 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24571 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24572 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24573 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24574 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24575 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24576 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24577 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24578 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24579 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24580 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24581 /* ARM v8.1 extension. */
24582 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24583 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24584 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24586 /* Two address, int/float. Types S8 S16 S32 F32. */
24587 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24588 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24590 /* Data processing with two registers and a shift amount. */
24591 /* Right shifts, and variants with rounding.
24592 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24593 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24594 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24595 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24596 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24597 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24598 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24599 /* Shift and insert. Sizes accepted 8 16 32 64. */
24600 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24601 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24602 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24603 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24604 /* Right shift immediate, saturating & narrowing, with rounding variants.
24605 Types accepted S16 S32 S64 U16 U32 U64. */
24606 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24607 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24608 /* As above, unsigned. Types accepted S16 S32 S64. */
24609 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24610 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24611 /* Right shift narrowing. Types accepted I16 I32 I64. */
24612 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24613 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24614 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24615 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24616 /* CVT with optional immediate for fixed-point variant. */
24617 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24619 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24621 /* Data processing, three registers of different lengths. */
24622 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24623 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24624 /* If not scalar, fall back to neon_dyadic_long.
24625 Vector types as above, scalar types S16 S32 U16 U32. */
24626 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24627 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24628 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24629 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24630 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24631 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24632 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24633 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24634 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24635 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24636 /* Saturating doubling multiplies. Types S16 S32. */
24637 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24638 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24639 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24640 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24641 S16 S32 U16 U32. */
24642 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24644 /* Extract. Size 8. */
24645 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24646 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24648 /* Two registers, miscellaneous. */
24649 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24650 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24651 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24652 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24653 /* Vector replicate. Sizes 8 16 32. */
24654 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24655 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24656 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24657 /* VMOVN. Types I16 I32 I64. */
24658 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24659 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24660 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24661 /* VQMOVUN. Types S16 S32 S64. */
24662 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24663 /* VZIP / VUZP. Sizes 8 16 32. */
24664 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24665 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24666 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24667 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24668 /* VQABS / VQNEG. Types S8 S16 S32. */
24669 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24670 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24671 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24672 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24673 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24674 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24675 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24676 /* Reciprocal estimates. Types U32 F16 F32. */
24677 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24678 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24679 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24680 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24681 /* VCLS. Types S8 S16 S32. */
24682 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24683 /* VCLZ. Types I8 I16 I32. */
24684 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24685 /* VCNT. Size 8. */
24686 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24687 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24688 /* Two address, untyped. */
24689 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24690 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24691 /* VTRN. Sizes 8 16 32. */
24692 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24693 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24695 /* Table lookup. Size 8. */
24696 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24697 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24699 #undef THUMB_VARIANT
24700 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24702 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24704 /* Neon element/structure load/store. */
24705 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24706 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24707 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24708 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24709 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24710 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24711 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24712 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24714 #undef THUMB_VARIANT
24715 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24717 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24718 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24719 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24720 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24721 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24722 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24723 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24724 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24725 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24726 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24728 #undef THUMB_VARIANT
24729 #define THUMB_VARIANT & fpu_vfp_ext_v3
24731 #define ARM_VARIANT & fpu_vfp_ext_v3
24733 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24734 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24735 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24736 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24737 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24738 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24739 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24740 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24741 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24744 #define ARM_VARIANT & fpu_vfp_ext_fma
24745 #undef THUMB_VARIANT
24746 #define THUMB_VARIANT & fpu_vfp_ext_fma
24747 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24748 VFP FMA variant; NEON and VFP FMA always includes the NEON
24749 FMA instructions. */
24750 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24751 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24753 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24754 the v form should always be used. */
24755 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24756 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24757 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24758 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24759 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24760 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24762 #undef THUMB_VARIANT
24764 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24766 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24767 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24768 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24769 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24770 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24771 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24772 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24773 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24776 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24778 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24779 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24780 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24781 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24782 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24783 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24784 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24785 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24786 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24787 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24788 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24789 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24790 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24791 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24792 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24793 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24794 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24795 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24796 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24797 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24798 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24799 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24800 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24801 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24802 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24803 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24804 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24805 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24806 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24807 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24808 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24809 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24810 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24811 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24812 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24813 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24814 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24815 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24816 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24817 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24818 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24819 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24820 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24821 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24822 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24823 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24824 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24825 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24826 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24827 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24828 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24829 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24830 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24831 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24832 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24833 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24834 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24835 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24836 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24837 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24838 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24839 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24840 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24841 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24842 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24843 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24844 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24845 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24846 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24847 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24848 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24849 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24850 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24851 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24852 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24853 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24854 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24855 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24856 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24857 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24858 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24859 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24860 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24861 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24862 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24863 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24864 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24865 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24866 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24867 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24868 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24869 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24870 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24871 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24872 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24873 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24874 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24875 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24876 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24877 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24878 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24879 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24880 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24881 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24882 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24883 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24884 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24885 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24886 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24887 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24888 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24889 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24890 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24891 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24892 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24893 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24894 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24895 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24896 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24897 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24898 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24899 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24900 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24901 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24902 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24903 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24904 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24905 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24906 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24907 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24908 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24909 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24910 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24911 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24912 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24913 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24914 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24915 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24916 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24917 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24918 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24919 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24920 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24921 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24922 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24923 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24924 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24925 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24926 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24927 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24928 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24929 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24930 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24931 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24932 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24933 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24934 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24935 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24936 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24937 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24938 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24939 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24942 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24944 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24945 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24946 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24947 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24948 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24949 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24950 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24951 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24952 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24953 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24954 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24955 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24956 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24957 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24958 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24959 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24960 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24961 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24962 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24963 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24964 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24965 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24966 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24967 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24968 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24969 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24970 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24971 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24972 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24973 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24974 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24975 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24976 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24977 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24978 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24979 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24980 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24981 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24982 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24983 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24984 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24985 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24986 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24987 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24988 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24989 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24990 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24991 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24992 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24993 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24994 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24995 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24996 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24997 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24998 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24999 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25000 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25003 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25005 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25006 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25007 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25008 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25009 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25010 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25011 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25012 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25013 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25014 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25015 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25016 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25017 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25018 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25019 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25020 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25021 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25022 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25023 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25024 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25025 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25026 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25027 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25028 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25029 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25030 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25031 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25032 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25033 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25034 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25035 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25036 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25037 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25038 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25039 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25040 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25041 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25042 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25043 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25044 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25045 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25046 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25047 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25048 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25049 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25050 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25051 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25052 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25053 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25054 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25055 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25056 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25057 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25058 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25059 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25060 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25061 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25062 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25063 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25064 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25065 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25066 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25067 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25068 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25069 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25070 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25071 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25072 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25073 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25074 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25075 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25076 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25077 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25078 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25079 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25080 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25082 /* ARMv8.5-A instructions. */
25084 #define ARM_VARIANT & arm_ext_sb
25085 #undef THUMB_VARIANT
25086 #define THUMB_VARIANT & arm_ext_sb
25087 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25090 #define ARM_VARIANT & arm_ext_predres
25091 #undef THUMB_VARIANT
25092 #define THUMB_VARIANT & arm_ext_predres
25093 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25094 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25095 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25097 /* ARMv8-M instructions. */
25099 #define ARM_VARIANT NULL
25100 #undef THUMB_VARIANT
25101 #define THUMB_VARIANT & arm_ext_v8m
25102 ToU("sg", e97fe97f
, 0, (), noargs
),
25103 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25104 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25105 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25106 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25107 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25108 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25110 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25111 instructions behave as nop if no VFP is present. */
25112 #undef THUMB_VARIANT
25113 #define THUMB_VARIANT & arm_ext_v8m_main
25114 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25115 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25117 /* Armv8.1-M Mainline instructions. */
25118 #undef THUMB_VARIANT
25119 #define THUMB_VARIANT & arm_ext_v8_1m_main
25120 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25121 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25122 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25123 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25124 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25126 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25127 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25128 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25130 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25131 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25133 #undef THUMB_VARIANT
25134 #define THUMB_VARIANT & mve_ext
25136 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25137 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25138 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25139 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25140 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25141 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25142 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25143 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25144 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25145 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25146 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25147 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25148 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25149 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25150 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25152 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25153 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25154 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25155 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25156 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25157 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25158 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25159 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25160 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25161 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25162 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25163 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25164 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25165 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25166 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25168 /* MVE and MVE FP only. */
25169 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25170 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25171 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25172 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25173 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25174 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25175 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25176 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25177 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25178 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25179 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25180 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25181 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25182 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25183 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25184 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25185 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25187 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25188 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25189 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25190 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25191 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25192 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25193 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25194 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25195 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25196 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25197 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25198 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25199 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25200 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25201 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25202 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25203 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25204 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25205 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25206 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25208 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25209 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25210 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25211 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25212 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25213 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25214 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25215 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25216 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25217 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25218 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25219 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25220 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25221 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25222 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25223 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25224 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25226 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25227 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25228 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25229 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25230 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25231 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25232 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25233 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25234 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25235 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25236 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25237 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25238 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25239 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25240 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25241 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25242 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25243 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25244 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25245 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25247 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25248 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25249 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25250 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25251 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25253 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25254 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25255 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25256 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25257 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25258 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25259 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25260 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25261 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25262 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25263 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25264 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25265 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25266 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25267 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25268 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25269 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25271 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25272 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25273 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25274 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25275 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25276 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25277 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25278 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25279 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25280 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25281 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25282 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25284 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25285 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25286 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25288 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25289 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25290 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25291 toU("lctp", _lctp
, 0, (), t_loloop
),
25293 #undef THUMB_VARIANT
25294 #define THUMB_VARIANT & mve_fp_ext
25295 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25296 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25297 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25298 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25299 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25300 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25301 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25302 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25305 #define ARM_VARIANT & fpu_vfp_ext_v1
25306 #undef THUMB_VARIANT
25307 #define THUMB_VARIANT & arm_ext_v6t2
25308 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25309 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25311 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25314 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25316 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25317 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25318 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25319 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25321 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25322 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25323 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25325 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25326 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25328 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25329 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25331 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25332 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25335 #define ARM_VARIANT & fpu_vfp_ext_v2
25337 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25338 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25339 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25340 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25343 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25344 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25345 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25346 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25347 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25348 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25349 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25352 #define ARM_VARIANT & fpu_neon_ext_v1
25353 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25354 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25355 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25356 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25357 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25358 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25359 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25360 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25361 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25362 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25363 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25364 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25365 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25366 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25367 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25368 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25369 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25370 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25371 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25372 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25373 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25374 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25375 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25376 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25377 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25378 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25379 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25380 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25381 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25382 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25383 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25384 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25385 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25386 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25387 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25388 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25389 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25392 #define ARM_VARIANT & arm_ext_v8_3
25393 #undef THUMB_VARIANT
25394 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25395 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25396 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25399 #undef THUMB_VARIANT
25431 /* MD interface: bits in the object file. */
25433 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25434 for use in the a.out file, and stores them in the array pointed to by buf.
25435 This knows about the endian-ness of the target machine and does
25436 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25437 2 (short) and 4 (long) Floating numbers are put out as a series of
25438 LITTLENUMS (shorts, here at least). */
25441 md_number_to_chars (char * buf
, valueT val
, int n
)
25443 if (target_big_endian
)
25444 number_to_chars_bigendian (buf
, val
, n
);
25446 number_to_chars_littleendian (buf
, val
, n
);
25450 md_chars_to_number (char * buf
, int n
)
25453 unsigned char * where
= (unsigned char *) buf
;
25455 if (target_big_endian
)
25460 result
|= (*where
++ & 255);
25468 result
|= (where
[n
] & 255);
25475 /* MD interface: Sections. */
25477 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25478 that an rs_machine_dependent frag may reach. */
25481 arm_frag_max_var (fragS
*fragp
)
25483 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25484 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25486 Note that we generate relaxable instructions even for cases that don't
25487 really need it, like an immediate that's a trivial constant. So we're
25488 overestimating the instruction size for some of those cases. Rather
25489 than putting more intelligence here, it would probably be better to
25490 avoid generating a relaxation frag in the first place when it can be
25491 determined up front that a short instruction will suffice. */
25493 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25497 /* Estimate the size of a frag before relaxing. Assume everything fits in
25501 md_estimate_size_before_relax (fragS
* fragp
,
25502 segT segtype ATTRIBUTE_UNUSED
)
25508 /* Convert a machine dependent frag. */
25511 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25513 unsigned long insn
;
25514 unsigned long old_op
;
25522 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25524 old_op
= bfd_get_16(abfd
, buf
);
25525 if (fragp
->fr_symbol
)
25527 exp
.X_op
= O_symbol
;
25528 exp
.X_add_symbol
= fragp
->fr_symbol
;
25532 exp
.X_op
= O_constant
;
25534 exp
.X_add_number
= fragp
->fr_offset
;
25535 opcode
= fragp
->fr_subtype
;
25538 case T_MNEM_ldr_pc
:
25539 case T_MNEM_ldr_pc2
:
25540 case T_MNEM_ldr_sp
:
25541 case T_MNEM_str_sp
:
25548 if (fragp
->fr_var
== 4)
25550 insn
= THUMB_OP32 (opcode
);
25551 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25553 insn
|= (old_op
& 0x700) << 4;
25557 insn
|= (old_op
& 7) << 12;
25558 insn
|= (old_op
& 0x38) << 13;
25560 insn
|= 0x00000c00;
25561 put_thumb32_insn (buf
, insn
);
25562 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25566 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25568 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25571 if (fragp
->fr_var
== 4)
25573 insn
= THUMB_OP32 (opcode
);
25574 insn
|= (old_op
& 0xf0) << 4;
25575 put_thumb32_insn (buf
, insn
);
25576 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25580 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25581 exp
.X_add_number
-= 4;
25589 if (fragp
->fr_var
== 4)
25591 int r0off
= (opcode
== T_MNEM_mov
25592 || opcode
== T_MNEM_movs
) ? 0 : 8;
25593 insn
= THUMB_OP32 (opcode
);
25594 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25595 insn
|= (old_op
& 0x700) << r0off
;
25596 put_thumb32_insn (buf
, insn
);
25597 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25601 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25606 if (fragp
->fr_var
== 4)
25608 insn
= THUMB_OP32(opcode
);
25609 put_thumb32_insn (buf
, insn
);
25610 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25613 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25617 if (fragp
->fr_var
== 4)
25619 insn
= THUMB_OP32(opcode
);
25620 insn
|= (old_op
& 0xf00) << 14;
25621 put_thumb32_insn (buf
, insn
);
25622 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25625 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25628 case T_MNEM_add_sp
:
25629 case T_MNEM_add_pc
:
25630 case T_MNEM_inc_sp
:
25631 case T_MNEM_dec_sp
:
25632 if (fragp
->fr_var
== 4)
25634 /* ??? Choose between add and addw. */
25635 insn
= THUMB_OP32 (opcode
);
25636 insn
|= (old_op
& 0xf0) << 4;
25637 put_thumb32_insn (buf
, insn
);
25638 if (opcode
== T_MNEM_add_pc
)
25639 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25641 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25644 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25652 if (fragp
->fr_var
== 4)
25654 insn
= THUMB_OP32 (opcode
);
25655 insn
|= (old_op
& 0xf0) << 4;
25656 insn
|= (old_op
& 0xf) << 16;
25657 put_thumb32_insn (buf
, insn
);
25658 if (insn
& (1 << 20))
25659 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25661 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25664 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25670 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25671 (enum bfd_reloc_code_real
) reloc_type
);
25672 fixp
->fx_file
= fragp
->fr_file
;
25673 fixp
->fx_line
= fragp
->fr_line
;
25674 fragp
->fr_fix
+= fragp
->fr_var
;
25676 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25677 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25678 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25679 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25682 /* Return the size of a relaxable immediate operand instruction.
25683 SHIFT and SIZE specify the form of the allowable immediate. */
25685 relax_immediate (fragS
*fragp
, int size
, int shift
)
25691 /* ??? Should be able to do better than this. */
25692 if (fragp
->fr_symbol
)
25695 low
= (1 << shift
) - 1;
25696 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25697 offset
= fragp
->fr_offset
;
25698 /* Force misaligned offsets to 32-bit variant. */
25701 if (offset
& ~mask
)
25706 /* Get the address of a symbol during relaxation. */
25708 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25714 sym
= fragp
->fr_symbol
;
25715 sym_frag
= symbol_get_frag (sym
);
25716 know (S_GET_SEGMENT (sym
) != absolute_section
25717 || sym_frag
== &zero_address_frag
);
25718 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25720 /* If frag has yet to be reached on this pass, assume it will
25721 move by STRETCH just as we did. If this is not so, it will
25722 be because some frag between grows, and that will force
25726 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25730 /* Adjust stretch for any alignment frag. Note that if have
25731 been expanding the earlier code, the symbol may be
25732 defined in what appears to be an earlier frag. FIXME:
25733 This doesn't handle the fr_subtype field, which specifies
25734 a maximum number of bytes to skip when doing an
25736 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25738 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25741 stretch
= - ((- stretch
)
25742 & ~ ((1 << (int) f
->fr_offset
) - 1));
25744 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25756 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25759 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25764 /* Assume worst case for symbols not known to be in the same section. */
25765 if (fragp
->fr_symbol
== NULL
25766 || !S_IS_DEFINED (fragp
->fr_symbol
)
25767 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25768 || S_IS_WEAK (fragp
->fr_symbol
))
25771 val
= relaxed_symbol_addr (fragp
, stretch
);
25772 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25773 addr
= (addr
+ 4) & ~3;
25774 /* Force misaligned targets to 32-bit variant. */
25778 if (val
< 0 || val
> 1020)
25783 /* Return the size of a relaxable add/sub immediate instruction. */
25785 relax_addsub (fragS
*fragp
, asection
*sec
)
25790 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25791 op
= bfd_get_16(sec
->owner
, buf
);
25792 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25793 return relax_immediate (fragp
, 8, 0);
25795 return relax_immediate (fragp
, 3, 0);
25798 /* Return TRUE iff the definition of symbol S could be pre-empted
25799 (overridden) at link or load time. */
25801 symbol_preemptible (symbolS
*s
)
25803 /* Weak symbols can always be pre-empted. */
25807 /* Non-global symbols cannot be pre-empted. */
25808 if (! S_IS_EXTERNAL (s
))
25812 /* In ELF, a global symbol can be marked protected, or private. In that
25813 case it can't be pre-empted (other definitions in the same link unit
25814 would violate the ODR). */
25815 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25819 /* Other global symbols might be pre-empted. */
25823 /* Return the size of a relaxable branch instruction. BITS is the
25824 size of the offset field in the narrow instruction. */
25827 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25833 /* Assume worst case for symbols not known to be in the same section. */
25834 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25835 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25836 || S_IS_WEAK (fragp
->fr_symbol
))
25840 /* A branch to a function in ARM state will require interworking. */
25841 if (S_IS_DEFINED (fragp
->fr_symbol
)
25842 && ARM_IS_FUNC (fragp
->fr_symbol
))
25846 if (symbol_preemptible (fragp
->fr_symbol
))
25849 val
= relaxed_symbol_addr (fragp
, stretch
);
25850 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25853 /* Offset is a signed value *2 */
25855 if (val
>= limit
|| val
< -limit
)
25861 /* Relax a machine dependent frag. This returns the amount by which
25862 the current size of the frag should change. */
25865 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25870 oldsize
= fragp
->fr_var
;
25871 switch (fragp
->fr_subtype
)
25873 case T_MNEM_ldr_pc2
:
25874 newsize
= relax_adr (fragp
, sec
, stretch
);
25876 case T_MNEM_ldr_pc
:
25877 case T_MNEM_ldr_sp
:
25878 case T_MNEM_str_sp
:
25879 newsize
= relax_immediate (fragp
, 8, 2);
25883 newsize
= relax_immediate (fragp
, 5, 2);
25887 newsize
= relax_immediate (fragp
, 5, 1);
25891 newsize
= relax_immediate (fragp
, 5, 0);
25894 newsize
= relax_adr (fragp
, sec
, stretch
);
25900 newsize
= relax_immediate (fragp
, 8, 0);
25903 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25906 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25908 case T_MNEM_add_sp
:
25909 case T_MNEM_add_pc
:
25910 newsize
= relax_immediate (fragp
, 8, 2);
25912 case T_MNEM_inc_sp
:
25913 case T_MNEM_dec_sp
:
25914 newsize
= relax_immediate (fragp
, 7, 2);
25920 newsize
= relax_addsub (fragp
, sec
);
25926 fragp
->fr_var
= newsize
;
25927 /* Freeze wide instructions that are at or before the same location as
25928 in the previous pass. This avoids infinite loops.
25929 Don't freeze them unconditionally because targets may be artificially
25930 misaligned by the expansion of preceding frags. */
25931 if (stretch
<= 0 && newsize
> 2)
25933 md_convert_frag (sec
->owner
, sec
, fragp
);
25937 return newsize
- oldsize
;
25940 /* Round up a section size to the appropriate boundary. */
25943 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25949 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25950 of an rs_align_code fragment. */
25953 arm_handle_align (fragS
* fragP
)
25955 static unsigned char const arm_noop
[2][2][4] =
25958 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25959 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25962 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25963 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25966 static unsigned char const thumb_noop
[2][2][2] =
25969 {0xc0, 0x46}, /* LE */
25970 {0x46, 0xc0}, /* BE */
25973 {0x00, 0xbf}, /* LE */
25974 {0xbf, 0x00} /* BE */
25977 static unsigned char const wide_thumb_noop
[2][4] =
25978 { /* Wide Thumb-2 */
25979 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25980 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25983 unsigned bytes
, fix
, noop_size
;
25985 const unsigned char * noop
;
25986 const unsigned char *narrow_noop
= NULL
;
25991 if (fragP
->fr_type
!= rs_align_code
)
25994 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
25995 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
25998 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
25999 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26001 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26003 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26005 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26006 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26008 narrow_noop
= thumb_noop
[1][target_big_endian
];
26009 noop
= wide_thumb_noop
[target_big_endian
];
26012 noop
= thumb_noop
[0][target_big_endian
];
26020 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26021 ? selected_cpu
: arm_arch_none
,
26023 [target_big_endian
];
26030 fragP
->fr_var
= noop_size
;
26032 if (bytes
& (noop_size
- 1))
26034 fix
= bytes
& (noop_size
- 1);
26036 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26038 memset (p
, 0, fix
);
26045 if (bytes
& noop_size
)
26047 /* Insert a narrow noop. */
26048 memcpy (p
, narrow_noop
, noop_size
);
26050 bytes
-= noop_size
;
26054 /* Use wide noops for the remainder */
26058 while (bytes
>= noop_size
)
26060 memcpy (p
, noop
, noop_size
);
26062 bytes
-= noop_size
;
26066 fragP
->fr_fix
+= fix
;
26069 /* Called from md_do_align. Used to create an alignment
26070 frag in a code section. */
26073 arm_frag_align_code (int n
, int max
)
26077 /* We assume that there will never be a requirement
26078 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26079 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26084 _("alignments greater than %d bytes not supported in .text sections."),
26085 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26086 as_fatal ("%s", err_msg
);
26089 p
= frag_var (rs_align_code
,
26090 MAX_MEM_FOR_RS_ALIGN_CODE
,
26092 (relax_substateT
) max
,
26099 /* Perform target specific initialisation of a frag.
26100 Note - despite the name this initialisation is not done when the frag
26101 is created, but only when its type is assigned. A frag can be created
26102 and used a long time before its type is set, so beware of assuming that
26103 this initialisation is performed first. */
26107 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26109 /* Record whether this frag is in an ARM or a THUMB area. */
26110 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26113 #else /* OBJ_ELF is defined. */
26115 arm_init_frag (fragS
* fragP
, int max_chars
)
26117 bfd_boolean frag_thumb_mode
;
26119 /* If the current ARM vs THUMB mode has not already
26120 been recorded into this frag then do so now. */
26121 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26122 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26124 /* PR 21809: Do not set a mapping state for debug sections
26125 - it just confuses other tools. */
26126 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26129 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26131 /* Record a mapping symbol for alignment frags. We will delete this
26132 later if the alignment ends up empty. */
26133 switch (fragP
->fr_type
)
26136 case rs_align_test
:
26138 mapping_state_2 (MAP_DATA
, max_chars
);
26140 case rs_align_code
:
26141 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26148 /* When we change sections we need to issue a new mapping symbol. */
26151 arm_elf_change_section (void)
26153 /* Link an unlinked unwind index table section to the .text section. */
26154 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26155 && elf_linked_to_section (now_seg
) == NULL
)
26156 elf_linked_to_section (now_seg
) = text_section
;
26160 arm_elf_section_type (const char * str
, size_t len
)
26162 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26163 return SHT_ARM_EXIDX
;
26168 /* Code to deal with unwinding tables. */
26170 static void add_unwind_adjustsp (offsetT
);
26172 /* Generate any deferred unwind frame offset. */
26175 flush_pending_unwind (void)
26179 offset
= unwind
.pending_offset
;
26180 unwind
.pending_offset
= 0;
26182 add_unwind_adjustsp (offset
);
26185 /* Add an opcode to this list for this function. Two-byte opcodes should
26186 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26190 add_unwind_opcode (valueT op
, int length
)
26192 /* Add any deferred stack adjustment. */
26193 if (unwind
.pending_offset
)
26194 flush_pending_unwind ();
26196 unwind
.sp_restored
= 0;
26198 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26200 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26201 if (unwind
.opcodes
)
26202 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26203 unwind
.opcode_alloc
);
26205 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26210 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26212 unwind
.opcode_count
++;
26216 /* Add unwind opcodes to adjust the stack pointer. */
26219 add_unwind_adjustsp (offsetT offset
)
26223 if (offset
> 0x200)
26225 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26230 /* Long form: 0xb2, uleb128. */
26231 /* This might not fit in a word so add the individual bytes,
26232 remembering the list is built in reverse order. */
26233 o
= (valueT
) ((offset
- 0x204) >> 2);
26235 add_unwind_opcode (0, 1);
26237 /* Calculate the uleb128 encoding of the offset. */
26241 bytes
[n
] = o
& 0x7f;
26247 /* Add the insn. */
26249 add_unwind_opcode (bytes
[n
- 1], 1);
26250 add_unwind_opcode (0xb2, 1);
26252 else if (offset
> 0x100)
26254 /* Two short opcodes. */
26255 add_unwind_opcode (0x3f, 1);
26256 op
= (offset
- 0x104) >> 2;
26257 add_unwind_opcode (op
, 1);
26259 else if (offset
> 0)
26261 /* Short opcode. */
26262 op
= (offset
- 4) >> 2;
26263 add_unwind_opcode (op
, 1);
26265 else if (offset
< 0)
26268 while (offset
> 0x100)
26270 add_unwind_opcode (0x7f, 1);
26273 op
= ((offset
- 4) >> 2) | 0x40;
26274 add_unwind_opcode (op
, 1);
26278 /* Finish the list of unwind opcodes for this function. */
26281 finish_unwind_opcodes (void)
26285 if (unwind
.fp_used
)
26287 /* Adjust sp as necessary. */
26288 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26289 flush_pending_unwind ();
26291 /* After restoring sp from the frame pointer. */
26292 op
= 0x90 | unwind
.fp_reg
;
26293 add_unwind_opcode (op
, 1);
26296 flush_pending_unwind ();
26300 /* Start an exception table entry. If idx is nonzero this is an index table
26304 start_unwind_section (const segT text_seg
, int idx
)
26306 const char * text_name
;
26307 const char * prefix
;
26308 const char * prefix_once
;
26309 const char * group_name
;
26317 prefix
= ELF_STRING_ARM_unwind
;
26318 prefix_once
= ELF_STRING_ARM_unwind_once
;
26319 type
= SHT_ARM_EXIDX
;
26323 prefix
= ELF_STRING_ARM_unwind_info
;
26324 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26325 type
= SHT_PROGBITS
;
26328 text_name
= segment_name (text_seg
);
26329 if (streq (text_name
, ".text"))
26332 if (strncmp (text_name
, ".gnu.linkonce.t.",
26333 strlen (".gnu.linkonce.t.")) == 0)
26335 prefix
= prefix_once
;
26336 text_name
+= strlen (".gnu.linkonce.t.");
26339 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26345 /* Handle COMDAT group. */
26346 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26348 group_name
= elf_group_name (text_seg
);
26349 if (group_name
== NULL
)
26351 as_bad (_("Group section `%s' has no group signature"),
26352 segment_name (text_seg
));
26353 ignore_rest_of_line ();
26356 flags
|= SHF_GROUP
;
26360 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26363 /* Set the section link for index tables. */
26365 elf_linked_to_section (now_seg
) = text_seg
;
26369 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26370 personality routine data. Returns zero, or the index table value for
26371 an inline entry. */
26374 create_unwind_entry (int have_data
)
26379 /* The current word of data. */
26381 /* The number of bytes left in this word. */
26384 finish_unwind_opcodes ();
26386 /* Remember the current text section. */
26387 unwind
.saved_seg
= now_seg
;
26388 unwind
.saved_subseg
= now_subseg
;
26390 start_unwind_section (now_seg
, 0);
26392 if (unwind
.personality_routine
== NULL
)
26394 if (unwind
.personality_index
== -2)
26397 as_bad (_("handlerdata in cantunwind frame"));
26398 return 1; /* EXIDX_CANTUNWIND. */
26401 /* Use a default personality routine if none is specified. */
26402 if (unwind
.personality_index
== -1)
26404 if (unwind
.opcode_count
> 3)
26405 unwind
.personality_index
= 1;
26407 unwind
.personality_index
= 0;
26410 /* Space for the personality routine entry. */
26411 if (unwind
.personality_index
== 0)
26413 if (unwind
.opcode_count
> 3)
26414 as_bad (_("too many unwind opcodes for personality routine 0"));
26418 /* All the data is inline in the index table. */
26421 while (unwind
.opcode_count
> 0)
26423 unwind
.opcode_count
--;
26424 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26428 /* Pad with "finish" opcodes. */
26430 data
= (data
<< 8) | 0xb0;
26437 /* We get two opcodes "free" in the first word. */
26438 size
= unwind
.opcode_count
- 2;
26442 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26443 if (unwind
.personality_index
!= -1)
26445 as_bad (_("attempt to recreate an unwind entry"));
26449 /* An extra byte is required for the opcode count. */
26450 size
= unwind
.opcode_count
+ 1;
26453 size
= (size
+ 3) >> 2;
26455 as_bad (_("too many unwind opcodes"));
26457 frag_align (2, 0, 0);
26458 record_alignment (now_seg
, 2);
26459 unwind
.table_entry
= expr_build_dot ();
26461 /* Allocate the table entry. */
26462 ptr
= frag_more ((size
<< 2) + 4);
26463 /* PR 13449: Zero the table entries in case some of them are not used. */
26464 memset (ptr
, 0, (size
<< 2) + 4);
26465 where
= frag_now_fix () - ((size
<< 2) + 4);
26467 switch (unwind
.personality_index
)
26470 /* ??? Should this be a PLT generating relocation? */
26471 /* Custom personality routine. */
26472 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26473 BFD_RELOC_ARM_PREL31
);
26478 /* Set the first byte to the number of additional words. */
26479 data
= size
> 0 ? size
- 1 : 0;
26483 /* ABI defined personality routines. */
26485 /* Three opcodes bytes are packed into the first word. */
26492 /* The size and first two opcode bytes go in the first word. */
26493 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26498 /* Should never happen. */
26502 /* Pack the opcodes into words (MSB first), reversing the list at the same
26504 while (unwind
.opcode_count
> 0)
26508 md_number_to_chars (ptr
, data
, 4);
26513 unwind
.opcode_count
--;
26515 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26518 /* Finish off the last word. */
26521 /* Pad with "finish" opcodes. */
26523 data
= (data
<< 8) | 0xb0;
26525 md_number_to_chars (ptr
, data
, 4);
26530 /* Add an empty descriptor if there is no user-specified data. */
26531 ptr
= frag_more (4);
26532 md_number_to_chars (ptr
, 0, 4);
26539 /* Initialize the DWARF-2 unwind information for this procedure. */
26542 tc_arm_frame_initial_instructions (void)
26544 cfi_add_CFA_def_cfa (REG_SP
, 0);
26546 #endif /* OBJ_ELF */
26548 /* Convert REGNAME to a DWARF-2 register number. */
26551 tc_arm_regname_to_dw2regnum (char *regname
)
26553 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26557 /* PR 16694: Allow VFP registers as well. */
26558 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26562 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26571 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26575 exp
.X_op
= O_secrel
;
26576 exp
.X_add_symbol
= symbol
;
26577 exp
.X_add_number
= 0;
26578 emit_expr (&exp
, size
);
26582 /* MD interface: Symbol and relocation handling. */
26584 /* Return the address within the segment that a PC-relative fixup is
26585 relative to. For ARM, PC-relative fixups applied to instructions
26586 are generally relative to the location of the fixup plus 8 bytes.
26587 Thumb branches are offset by 4, and Thumb loads relative to PC
26588 require special handling. */
26591 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26593 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26595 /* If this is pc-relative and we are going to emit a relocation
26596 then we just want to put out any pipeline compensation that the linker
26597 will need. Otherwise we want to use the calculated base.
26598 For WinCE we skip the bias for externals as well, since this
26599 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26601 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26602 || (arm_force_relocation (fixP
)
26604 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26610 switch (fixP
->fx_r_type
)
26612 /* PC relative addressing on the Thumb is slightly odd as the
26613 bottom two bits of the PC are forced to zero for the
26614 calculation. This happens *after* application of the
26615 pipeline offset. However, Thumb adrl already adjusts for
26616 this, so we need not do it again. */
26617 case BFD_RELOC_ARM_THUMB_ADD
:
26620 case BFD_RELOC_ARM_THUMB_OFFSET
:
26621 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26622 case BFD_RELOC_ARM_T32_ADD_PC12
:
26623 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26624 return (base
+ 4) & ~3;
26626 /* Thumb branches are simply offset by +4. */
26627 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26628 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26629 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26630 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26631 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26632 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26633 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26634 case BFD_RELOC_ARM_THUMB_BF17
:
26635 case BFD_RELOC_ARM_THUMB_BF19
:
26636 case BFD_RELOC_ARM_THUMB_BF13
:
26637 case BFD_RELOC_ARM_THUMB_LOOP12
:
26640 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26642 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26643 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26644 && ARM_IS_FUNC (fixP
->fx_addsy
)
26645 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26646 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26649 /* BLX is like branches above, but forces the low two bits of PC to
26651 case BFD_RELOC_THUMB_PCREL_BLX
:
26653 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26654 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26655 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26656 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26657 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26658 return (base
+ 4) & ~3;
26660 /* ARM mode branches are offset by +8. However, the Windows CE
26661 loader expects the relocation not to take this into account. */
26662 case BFD_RELOC_ARM_PCREL_BLX
:
26664 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26665 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26666 && ARM_IS_FUNC (fixP
->fx_addsy
)
26667 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26668 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26671 case BFD_RELOC_ARM_PCREL_CALL
:
26673 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26674 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26675 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26676 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26677 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26680 case BFD_RELOC_ARM_PCREL_BRANCH
:
26681 case BFD_RELOC_ARM_PCREL_JUMP
:
26682 case BFD_RELOC_ARM_PLT32
:
26684 /* When handling fixups immediately, because we have already
26685 discovered the value of a symbol, or the address of the frag involved
26686 we must account for the offset by +8, as the OS loader will never see the reloc.
26687 see fixup_segment() in write.c
26688 The S_IS_EXTERNAL test handles the case of global symbols.
26689 Those need the calculated base, not just the pipe compensation the linker will need. */
26691 && fixP
->fx_addsy
!= NULL
26692 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26693 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26701 /* ARM mode loads relative to PC are also offset by +8. Unlike
26702 branches, the Windows CE loader *does* expect the relocation
26703 to take this into account. */
26704 case BFD_RELOC_ARM_OFFSET_IMM
:
26705 case BFD_RELOC_ARM_OFFSET_IMM8
:
26706 case BFD_RELOC_ARM_HWLITERAL
:
26707 case BFD_RELOC_ARM_LITERAL
:
26708 case BFD_RELOC_ARM_CP_OFF_IMM
:
26712 /* Other PC-relative relocations are un-offset. */
26718 static bfd_boolean flag_warn_syms
= TRUE
;
26721 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26723 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26724 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26725 does mean that the resulting code might be very confusing to the reader.
26726 Also this warning can be triggered if the user omits an operand before
26727 an immediate address, eg:
26731 GAS treats this as an assignment of the value of the symbol foo to a
26732 symbol LDR, and so (without this code) it will not issue any kind of
26733 warning or error message.
26735 Note - ARM instructions are case-insensitive but the strings in the hash
26736 table are all stored in lower case, so we must first ensure that name is
26738 if (flag_warn_syms
&& arm_ops_hsh
)
26740 char * nbuf
= strdup (name
);
26743 for (p
= nbuf
; *p
; p
++)
26745 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26747 static struct hash_control
* already_warned
= NULL
;
26749 if (already_warned
== NULL
)
26750 already_warned
= hash_new ();
26751 /* Only warn about the symbol once. To keep the code
26752 simple we let hash_insert do the lookup for us. */
26753 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26754 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26763 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26764 Otherwise we have no need to default values of symbols. */
26767 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26770 if (name
[0] == '_' && name
[1] == 'G'
26771 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26775 if (symbol_find (name
))
26776 as_bad (_("GOT already in the symbol table"));
26778 GOT_symbol
= symbol_new (name
, undefined_section
,
26779 (valueT
) 0, & zero_address_frag
);
26789 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26790 computed as two separate immediate values, added together. We
26791 already know that this value cannot be computed by just one ARM
26794 static unsigned int
26795 validate_immediate_twopart (unsigned int val
,
26796 unsigned int * highpart
)
26801 for (i
= 0; i
< 32; i
+= 2)
26802 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26808 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26810 else if (a
& 0xff0000)
26812 if (a
& 0xff000000)
26814 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26818 gas_assert (a
& 0xff000000);
26819 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26822 return (a
& 0xff) | (i
<< 7);
26829 validate_offset_imm (unsigned int val
, int hwse
)
26831 if ((hwse
&& val
> 255) || val
> 4095)
26836 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26837 negative immediate constant by altering the instruction. A bit of
26842 by inverting the second operand, and
26845 by negating the second operand. */
26848 negate_data_op (unsigned long * instruction
,
26849 unsigned long value
)
26852 unsigned long negated
, inverted
;
26854 negated
= encode_arm_immediate (-value
);
26855 inverted
= encode_arm_immediate (~value
);
26857 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26860 /* First negates. */
26861 case OPCODE_SUB
: /* ADD <-> SUB */
26862 new_inst
= OPCODE_ADD
;
26867 new_inst
= OPCODE_SUB
;
26871 case OPCODE_CMP
: /* CMP <-> CMN */
26872 new_inst
= OPCODE_CMN
;
26877 new_inst
= OPCODE_CMP
;
26881 /* Now Inverted ops. */
26882 case OPCODE_MOV
: /* MOV <-> MVN */
26883 new_inst
= OPCODE_MVN
;
26888 new_inst
= OPCODE_MOV
;
26892 case OPCODE_AND
: /* AND <-> BIC */
26893 new_inst
= OPCODE_BIC
;
26898 new_inst
= OPCODE_AND
;
26902 case OPCODE_ADC
: /* ADC <-> SBC */
26903 new_inst
= OPCODE_SBC
;
26908 new_inst
= OPCODE_ADC
;
26912 /* We cannot do anything. */
26917 if (value
== (unsigned) FAIL
)
26920 *instruction
&= OPCODE_MASK
;
26921 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26925 /* Like negate_data_op, but for Thumb-2. */
26927 static unsigned int
26928 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26932 unsigned int negated
, inverted
;
26934 negated
= encode_thumb32_immediate (-value
);
26935 inverted
= encode_thumb32_immediate (~value
);
26937 rd
= (*instruction
>> 8) & 0xf;
26938 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26941 /* ADD <-> SUB. Includes CMP <-> CMN. */
26942 case T2_OPCODE_SUB
:
26943 new_inst
= T2_OPCODE_ADD
;
26947 case T2_OPCODE_ADD
:
26948 new_inst
= T2_OPCODE_SUB
;
26952 /* ORR <-> ORN. Includes MOV <-> MVN. */
26953 case T2_OPCODE_ORR
:
26954 new_inst
= T2_OPCODE_ORN
;
26958 case T2_OPCODE_ORN
:
26959 new_inst
= T2_OPCODE_ORR
;
26963 /* AND <-> BIC. TST has no inverted equivalent. */
26964 case T2_OPCODE_AND
:
26965 new_inst
= T2_OPCODE_BIC
;
26972 case T2_OPCODE_BIC
:
26973 new_inst
= T2_OPCODE_AND
;
26978 case T2_OPCODE_ADC
:
26979 new_inst
= T2_OPCODE_SBC
;
26983 case T2_OPCODE_SBC
:
26984 new_inst
= T2_OPCODE_ADC
;
26988 /* We cannot do anything. */
26993 if (value
== (unsigned int)FAIL
)
26996 *instruction
&= T2_OPCODE_MASK
;
26997 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27001 /* Read a 32-bit thumb instruction from buf. */
27003 static unsigned long
27004 get_thumb32_insn (char * buf
)
27006 unsigned long insn
;
27007 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27008 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27013 /* We usually want to set the low bit on the address of thumb function
27014 symbols. In particular .word foo - . should have the low bit set.
27015 Generic code tries to fold the difference of two symbols to
27016 a constant. Prevent this and force a relocation when the first symbols
27017 is a thumb function. */
27020 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27022 if (op
== O_subtract
27023 && l
->X_op
== O_symbol
27024 && r
->X_op
== O_symbol
27025 && THUMB_IS_FUNC (l
->X_add_symbol
))
27027 l
->X_op
= O_subtract
;
27028 l
->X_op_symbol
= r
->X_add_symbol
;
27029 l
->X_add_number
-= r
->X_add_number
;
27033 /* Process as normal. */
27037 /* Encode Thumb2 unconditional branches and calls. The encoding
27038 for the 2 are identical for the immediate values. */
27041 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27043 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27046 addressT S
, I1
, I2
, lo
, hi
;
27048 S
= (value
>> 24) & 0x01;
27049 I1
= (value
>> 23) & 0x01;
27050 I2
= (value
>> 22) & 0x01;
27051 hi
= (value
>> 12) & 0x3ff;
27052 lo
= (value
>> 1) & 0x7ff;
27053 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27054 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27055 newval
|= (S
<< 10) | hi
;
27056 newval2
&= ~T2I1I2MASK
;
27057 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27058 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27059 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27063 md_apply_fix (fixS
* fixP
,
27067 offsetT value
= * valP
;
27069 unsigned int newimm
;
27070 unsigned long temp
;
27072 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27074 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27076 /* Note whether this will delete the relocation. */
27078 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27081 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27082 consistency with the behaviour on 32-bit hosts. Remember value
27084 value
&= 0xffffffff;
27085 value
^= 0x80000000;
27086 value
-= 0x80000000;
27089 fixP
->fx_addnumber
= value
;
27091 /* Same treatment for fixP->fx_offset. */
27092 fixP
->fx_offset
&= 0xffffffff;
27093 fixP
->fx_offset
^= 0x80000000;
27094 fixP
->fx_offset
-= 0x80000000;
27096 switch (fixP
->fx_r_type
)
27098 case BFD_RELOC_NONE
:
27099 /* This will need to go in the object file. */
27103 case BFD_RELOC_ARM_IMMEDIATE
:
27104 /* We claim that this fixup has been processed here,
27105 even if in fact we generate an error because we do
27106 not have a reloc for it, so tc_gen_reloc will reject it. */
27109 if (fixP
->fx_addsy
)
27111 const char *msg
= 0;
27113 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27114 msg
= _("undefined symbol %s used as an immediate value");
27115 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27116 msg
= _("symbol %s is in a different section");
27117 else if (S_IS_WEAK (fixP
->fx_addsy
))
27118 msg
= _("symbol %s is weak and may be overridden later");
27122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27123 msg
, S_GET_NAME (fixP
->fx_addsy
));
27128 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27130 /* If the offset is negative, we should use encoding A2 for ADR. */
27131 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27132 newimm
= negate_data_op (&temp
, value
);
27135 newimm
= encode_arm_immediate (value
);
27137 /* If the instruction will fail, see if we can fix things up by
27138 changing the opcode. */
27139 if (newimm
== (unsigned int) FAIL
)
27140 newimm
= negate_data_op (&temp
, value
);
27141 /* MOV accepts both ARM modified immediate (A1 encoding) and
27142 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27143 When disassembling, MOV is preferred when there is no encoding
27145 if (newimm
== (unsigned int) FAIL
27146 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27147 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27148 && !((temp
>> SBIT_SHIFT
) & 0x1)
27149 && value
>= 0 && value
<= 0xffff)
27151 /* Clear bits[23:20] to change encoding from A1 to A2. */
27152 temp
&= 0xff0fffff;
27153 /* Encoding high 4bits imm. Code below will encode the remaining
27155 temp
|= (value
& 0x0000f000) << 4;
27156 newimm
= value
& 0x00000fff;
27160 if (newimm
== (unsigned int) FAIL
)
27162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27163 _("invalid constant (%lx) after fixup"),
27164 (unsigned long) value
);
27168 newimm
|= (temp
& 0xfffff000);
27169 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27172 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27174 unsigned int highpart
= 0;
27175 unsigned int newinsn
= 0xe1a00000; /* nop. */
27177 if (fixP
->fx_addsy
)
27179 const char *msg
= 0;
27181 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27182 msg
= _("undefined symbol %s used as an immediate value");
27183 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27184 msg
= _("symbol %s is in a different section");
27185 else if (S_IS_WEAK (fixP
->fx_addsy
))
27186 msg
= _("symbol %s is weak and may be overridden later");
27190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27191 msg
, S_GET_NAME (fixP
->fx_addsy
));
27196 newimm
= encode_arm_immediate (value
);
27197 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27199 /* If the instruction will fail, see if we can fix things up by
27200 changing the opcode. */
27201 if (newimm
== (unsigned int) FAIL
27202 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27204 /* No ? OK - try using two ADD instructions to generate
27206 newimm
= validate_immediate_twopart (value
, & highpart
);
27208 /* Yes - then make sure that the second instruction is
27210 if (newimm
!= (unsigned int) FAIL
)
27212 /* Still No ? Try using a negated value. */
27213 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27214 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27215 /* Otherwise - give up. */
27218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27219 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27224 /* Replace the first operand in the 2nd instruction (which
27225 is the PC) with the destination register. We have
27226 already added in the PC in the first instruction and we
27227 do not want to do it again. */
27228 newinsn
&= ~ 0xf0000;
27229 newinsn
|= ((newinsn
& 0x0f000) << 4);
27232 newimm
|= (temp
& 0xfffff000);
27233 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27235 highpart
|= (newinsn
& 0xfffff000);
27236 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27240 case BFD_RELOC_ARM_OFFSET_IMM
:
27241 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27243 /* Fall through. */
27245 case BFD_RELOC_ARM_LITERAL
:
27251 if (validate_offset_imm (value
, 0) == FAIL
)
27253 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27254 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27255 _("invalid literal constant: pool needs to be closer"));
27257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27258 _("bad immediate value for offset (%ld)"),
27263 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27265 newval
&= 0xfffff000;
27268 newval
&= 0xff7ff000;
27269 newval
|= value
| (sign
? INDEX_UP
: 0);
27271 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27274 case BFD_RELOC_ARM_OFFSET_IMM8
:
27275 case BFD_RELOC_ARM_HWLITERAL
:
27281 if (validate_offset_imm (value
, 1) == FAIL
)
27283 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27285 _("invalid literal constant: pool needs to be closer"));
27287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27288 _("bad immediate value for 8-bit offset (%ld)"),
27293 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27295 newval
&= 0xfffff0f0;
27298 newval
&= 0xff7ff0f0;
27299 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27301 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27304 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27305 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27307 _("bad immediate value for offset (%ld)"), (long) value
);
27310 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27312 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27315 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27316 /* This is a complicated relocation used for all varieties of Thumb32
27317 load/store instruction with immediate offset:
27319 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27320 *4, optional writeback(W)
27321 (doubleword load/store)
27323 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27324 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27325 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27326 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27327 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27329 Uppercase letters indicate bits that are already encoded at
27330 this point. Lowercase letters are our problem. For the
27331 second block of instructions, the secondary opcode nybble
27332 (bits 8..11) is present, and bit 23 is zero, even if this is
27333 a PC-relative operation. */
27334 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27336 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27338 if ((newval
& 0xf0000000) == 0xe0000000)
27340 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27342 newval
|= (1 << 23);
27345 if (value
% 4 != 0)
27347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27348 _("offset not a multiple of 4"));
27354 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27355 _("offset out of range"));
27360 else if ((newval
& 0x000f0000) == 0x000f0000)
27362 /* PC-relative, 12-bit offset. */
27364 newval
|= (1 << 23);
27369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27370 _("offset out of range"));
27375 else if ((newval
& 0x00000100) == 0x00000100)
27377 /* Writeback: 8-bit, +/- offset. */
27379 newval
|= (1 << 9);
27384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27385 _("offset out of range"));
27390 else if ((newval
& 0x00000f00) == 0x00000e00)
27392 /* T-instruction: positive 8-bit offset. */
27393 if (value
< 0 || value
> 0xff)
27395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27396 _("offset out of range"));
27404 /* Positive 12-bit or negative 8-bit offset. */
27408 newval
|= (1 << 23);
27418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27419 _("offset out of range"));
27426 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27427 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27430 case BFD_RELOC_ARM_SHIFT_IMM
:
27431 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27432 if (((unsigned long) value
) > 32
27434 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27437 _("shift expression is too large"));
27442 /* Shifts of zero must be done as lsl. */
27444 else if (value
== 32)
27446 newval
&= 0xfffff07f;
27447 newval
|= (value
& 0x1f) << 7;
27448 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27451 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27452 case BFD_RELOC_ARM_T32_ADD_IMM
:
27453 case BFD_RELOC_ARM_T32_IMM12
:
27454 case BFD_RELOC_ARM_T32_ADD_PC12
:
27455 /* We claim that this fixup has been processed here,
27456 even if in fact we generate an error because we do
27457 not have a reloc for it, so tc_gen_reloc will reject it. */
27461 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27464 _("undefined symbol %s used as an immediate value"),
27465 S_GET_NAME (fixP
->fx_addsy
));
27469 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27471 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27474 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27475 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27476 Thumb2 modified immediate encoding (T2). */
27477 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27478 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27480 newimm
= encode_thumb32_immediate (value
);
27481 if (newimm
== (unsigned int) FAIL
)
27482 newimm
= thumb32_negate_data_op (&newval
, value
);
27484 if (newimm
== (unsigned int) FAIL
)
27486 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27488 /* Turn add/sum into addw/subw. */
27489 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27490 newval
= (newval
& 0xfeffffff) | 0x02000000;
27491 /* No flat 12-bit imm encoding for addsw/subsw. */
27492 if ((newval
& 0x00100000) == 0)
27494 /* 12 bit immediate for addw/subw. */
27498 newval
^= 0x00a00000;
27501 newimm
= (unsigned int) FAIL
;
27508 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27509 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27510 disassembling, MOV is preferred when there is no encoding
27512 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27513 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27514 but with the Rn field [19:16] set to 1111. */
27515 && (((newval
>> 16) & 0xf) == 0xf)
27516 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27517 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27518 && value
>= 0 && value
<= 0xffff)
27520 /* Toggle bit[25] to change encoding from T2 to T3. */
27522 /* Clear bits[19:16]. */
27523 newval
&= 0xfff0ffff;
27524 /* Encoding high 4bits imm. Code below will encode the
27525 remaining low 12bits. */
27526 newval
|= (value
& 0x0000f000) << 4;
27527 newimm
= value
& 0x00000fff;
27532 if (newimm
== (unsigned int)FAIL
)
27534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27535 _("invalid constant (%lx) after fixup"),
27536 (unsigned long) value
);
27540 newval
|= (newimm
& 0x800) << 15;
27541 newval
|= (newimm
& 0x700) << 4;
27542 newval
|= (newimm
& 0x0ff);
27544 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27545 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27548 case BFD_RELOC_ARM_SMC
:
27549 if (((unsigned long) value
) > 0xffff)
27550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27551 _("invalid smc expression"));
27552 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27553 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27554 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27557 case BFD_RELOC_ARM_HVC
:
27558 if (((unsigned long) value
) > 0xffff)
27559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27560 _("invalid hvc expression"));
27561 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27562 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27563 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27566 case BFD_RELOC_ARM_SWI
:
27567 if (fixP
->tc_fix_data
!= 0)
27569 if (((unsigned long) value
) > 0xff)
27570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27571 _("invalid swi expression"));
27572 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27574 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27578 if (((unsigned long) value
) > 0x00ffffff)
27579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27580 _("invalid swi expression"));
27581 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27587 case BFD_RELOC_ARM_MULTI
:
27588 if (((unsigned long) value
) > 0xffff)
27589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27590 _("invalid expression in load/store multiple"));
27591 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27592 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27596 case BFD_RELOC_ARM_PCREL_CALL
:
27598 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27600 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27601 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27602 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27603 /* Flip the bl to blx. This is a simple flip
27604 bit here because we generate PCREL_CALL for
27605 unconditional bls. */
27607 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27608 newval
= newval
| 0x10000000;
27609 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27615 goto arm_branch_common
;
27617 case BFD_RELOC_ARM_PCREL_JUMP
:
27618 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27620 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27621 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27622 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27624 /* This would map to a bl<cond>, b<cond>,
27625 b<always> to a Thumb function. We
27626 need to force a relocation for this particular
27628 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27631 /* Fall through. */
27633 case BFD_RELOC_ARM_PLT32
:
27635 case BFD_RELOC_ARM_PCREL_BRANCH
:
27637 goto arm_branch_common
;
27639 case BFD_RELOC_ARM_PCREL_BLX
:
27642 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27644 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27645 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27646 && ARM_IS_FUNC (fixP
->fx_addsy
))
27648 /* Flip the blx to a bl and warn. */
27649 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27650 newval
= 0xeb000000;
27651 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27652 _("blx to '%s' an ARM ISA state function changed to bl"),
27654 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27660 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27661 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27665 /* We are going to store value (shifted right by two) in the
27666 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27667 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27671 _("misaligned branch destination"));
27672 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27673 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27676 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27678 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27679 newval
|= (value
>> 2) & 0x00ffffff;
27680 /* Set the H bit on BLX instructions. */
27684 newval
|= 0x01000000;
27686 newval
&= ~0x01000000;
27688 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27692 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27693 /* CBZ can only branch forward. */
27695 /* Attempts to use CBZ to branch to the next instruction
27696 (which, strictly speaking, are prohibited) will be turned into
27699 FIXME: It may be better to remove the instruction completely and
27700 perform relaxation. */
27703 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27704 newval
= 0xbf00; /* NOP encoding T1 */
27705 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27712 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27714 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27715 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27716 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27721 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27722 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27727 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27728 newval
|= (value
& 0x1ff) >> 1;
27729 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27733 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27734 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27737 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27739 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27740 newval
|= (value
& 0xfff) >> 1;
27741 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27745 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27747 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27748 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27749 && ARM_IS_FUNC (fixP
->fx_addsy
)
27750 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27752 /* Force a relocation for a branch 20 bits wide. */
27755 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27757 _("conditional branch out of range"));
27759 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27762 addressT S
, J1
, J2
, lo
, hi
;
27764 S
= (value
& 0x00100000) >> 20;
27765 J2
= (value
& 0x00080000) >> 19;
27766 J1
= (value
& 0x00040000) >> 18;
27767 hi
= (value
& 0x0003f000) >> 12;
27768 lo
= (value
& 0x00000ffe) >> 1;
27770 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27771 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27772 newval
|= (S
<< 10) | hi
;
27773 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27774 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27775 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27779 case BFD_RELOC_THUMB_PCREL_BLX
:
27780 /* If there is a blx from a thumb state function to
27781 another thumb function flip this to a bl and warn
27785 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27786 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27787 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27789 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27790 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27791 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27793 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27794 newval
= newval
| 0x1000;
27795 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27796 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27801 goto thumb_bl_common
;
27803 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27804 /* A bl from Thumb state ISA to an internal ARM state function
27805 is converted to a blx. */
27807 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27808 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27809 && ARM_IS_FUNC (fixP
->fx_addsy
)
27810 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27812 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27813 newval
= newval
& ~0x1000;
27814 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27815 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27821 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27822 /* For a BLX instruction, make sure that the relocation is rounded up
27823 to a word boundary. This follows the semantics of the instruction
27824 which specifies that bit 1 of the target address will come from bit
27825 1 of the base address. */
27826 value
= (value
+ 3) & ~ 3;
27829 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27830 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27831 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27834 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27836 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27838 else if ((value
& ~0x1ffffff)
27839 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27841 _("Thumb2 branch out of range"));
27844 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27845 encode_thumb2_b_bl_offset (buf
, value
);
27849 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27850 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27854 encode_thumb2_b_bl_offset (buf
, value
);
27859 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27864 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27865 md_number_to_chars (buf
, value
, 2);
27869 case BFD_RELOC_ARM_TLS_CALL
:
27870 case BFD_RELOC_ARM_THM_TLS_CALL
:
27871 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27872 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27873 case BFD_RELOC_ARM_TLS_GOTDESC
:
27874 case BFD_RELOC_ARM_TLS_GD32
:
27875 case BFD_RELOC_ARM_TLS_LE32
:
27876 case BFD_RELOC_ARM_TLS_IE32
:
27877 case BFD_RELOC_ARM_TLS_LDM32
:
27878 case BFD_RELOC_ARM_TLS_LDO32
:
27879 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27882 /* Same handling as above, but with the arm_fdpic guard. */
27883 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27884 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27885 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27888 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27893 _("Relocation supported only in FDPIC mode"));
27897 case BFD_RELOC_ARM_GOT32
:
27898 case BFD_RELOC_ARM_GOTOFF
:
27901 case BFD_RELOC_ARM_GOT_PREL
:
27902 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27903 md_number_to_chars (buf
, value
, 4);
27906 case BFD_RELOC_ARM_TARGET2
:
27907 /* TARGET2 is not partial-inplace, so we need to write the
27908 addend here for REL targets, because it won't be written out
27909 during reloc processing later. */
27910 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27911 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27914 /* Relocations for FDPIC. */
27915 case BFD_RELOC_ARM_GOTFUNCDESC
:
27916 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27917 case BFD_RELOC_ARM_FUNCDESC
:
27920 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27921 md_number_to_chars (buf
, 0, 4);
27925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27926 _("Relocation supported only in FDPIC mode"));
27931 case BFD_RELOC_RVA
:
27933 case BFD_RELOC_ARM_TARGET1
:
27934 case BFD_RELOC_ARM_ROSEGREL32
:
27935 case BFD_RELOC_ARM_SBREL32
:
27936 case BFD_RELOC_32_PCREL
:
27938 case BFD_RELOC_32_SECREL
:
27940 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27942 /* For WinCE we only do this for pcrel fixups. */
27943 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27945 md_number_to_chars (buf
, value
, 4);
27949 case BFD_RELOC_ARM_PREL31
:
27950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27952 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27953 if ((value
^ (value
>> 1)) & 0x40000000)
27955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27956 _("rel31 relocation overflow"));
27958 newval
|= value
& 0x7fffffff;
27959 md_number_to_chars (buf
, newval
, 4);
27964 case BFD_RELOC_ARM_CP_OFF_IMM
:
27965 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27966 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27967 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27968 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27970 newval
= get_thumb32_insn (buf
);
27971 if ((newval
& 0x0f200f00) == 0x0d000900)
27973 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27974 has permitted values that are multiples of 2, in the range 0
27976 if (value
< -510 || value
> 510 || (value
& 1))
27977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27978 _("co-processor offset out of range"));
27980 else if ((newval
& 0xfe001f80) == 0xec000f80)
27982 if (value
< -511 || value
> 512 || (value
& 3))
27983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27984 _("co-processor offset out of range"));
27986 else if (value
< -1023 || value
> 1023 || (value
& 3))
27987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27988 _("co-processor offset out of range"));
27993 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27994 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
27995 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27997 newval
= get_thumb32_insn (buf
);
28000 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28001 newval
&= 0xffffff80;
28003 newval
&= 0xffffff00;
28007 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28008 newval
&= 0xff7fff80;
28010 newval
&= 0xff7fff00;
28011 if ((newval
& 0x0f200f00) == 0x0d000900)
28013 /* This is a fp16 vstr/vldr.
28015 It requires the immediate offset in the instruction is shifted
28016 left by 1 to be a half-word offset.
28018 Here, left shift by 1 first, and later right shift by 2
28019 should get the right offset. */
28022 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28024 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28025 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28026 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28028 put_thumb32_insn (buf
, newval
);
28031 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28032 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28033 if (value
< -255 || value
> 255)
28034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28035 _("co-processor offset out of range"));
28037 goto cp_off_common
;
28039 case BFD_RELOC_ARM_THUMB_OFFSET
:
28040 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28041 /* Exactly what ranges, and where the offset is inserted depends
28042 on the type of instruction, we can establish this from the
28044 switch (newval
>> 12)
28046 case 4: /* PC load. */
28047 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28048 forced to zero for these loads; md_pcrel_from has already
28049 compensated for this. */
28051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28052 _("invalid offset, target not word aligned (0x%08lX)"),
28053 (((unsigned long) fixP
->fx_frag
->fr_address
28054 + (unsigned long) fixP
->fx_where
) & ~3)
28055 + (unsigned long) value
);
28057 if (value
& ~0x3fc)
28058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28059 _("invalid offset, value too big (0x%08lX)"),
28062 newval
|= value
>> 2;
28065 case 9: /* SP load/store. */
28066 if (value
& ~0x3fc)
28067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28068 _("invalid offset, value too big (0x%08lX)"),
28070 newval
|= value
>> 2;
28073 case 6: /* Word load/store. */
28075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28076 _("invalid offset, value too big (0x%08lX)"),
28078 newval
|= value
<< 4; /* 6 - 2. */
28081 case 7: /* Byte load/store. */
28083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28084 _("invalid offset, value too big (0x%08lX)"),
28086 newval
|= value
<< 6;
28089 case 8: /* Halfword load/store. */
28091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28092 _("invalid offset, value too big (0x%08lX)"),
28094 newval
|= value
<< 5; /* 6 - 1. */
28098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28099 "Unable to process relocation for thumb opcode: %lx",
28100 (unsigned long) newval
);
28103 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28106 case BFD_RELOC_ARM_THUMB_ADD
:
28107 /* This is a complicated relocation, since we use it for all of
28108 the following immediate relocations:
28112 9bit ADD/SUB SP word-aligned
28113 10bit ADD PC/SP word-aligned
28115 The type of instruction being processed is encoded in the
28122 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28124 int rd
= (newval
>> 4) & 0xf;
28125 int rs
= newval
& 0xf;
28126 int subtract
= !!(newval
& 0x8000);
28128 /* Check for HI regs, only very restricted cases allowed:
28129 Adjusting SP, and using PC or SP to get an address. */
28130 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28131 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28133 _("invalid Hi register with immediate"));
28135 /* If value is negative, choose the opposite instruction. */
28139 subtract
= !subtract
;
28141 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28142 _("immediate value out of range"));
28147 if (value
& ~0x1fc)
28148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28149 _("invalid immediate for stack address calculation"));
28150 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28151 newval
|= value
>> 2;
28153 else if (rs
== REG_PC
|| rs
== REG_SP
)
28155 /* PR gas/18541. If the addition is for a defined symbol
28156 within range of an ADR instruction then accept it. */
28159 && fixP
->fx_addsy
!= NULL
)
28163 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28164 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28165 || S_IS_WEAK (fixP
->fx_addsy
))
28167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28168 _("address calculation needs a strongly defined nearby symbol"));
28172 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28174 /* Round up to the next 4-byte boundary. */
28179 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28184 _("symbol too far away"));
28194 if (subtract
|| value
& ~0x3fc)
28195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28196 _("invalid immediate for address calculation (value = 0x%08lX)"),
28197 (unsigned long) (subtract
? - value
: value
));
28198 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28200 newval
|= value
>> 2;
28205 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28206 _("immediate value out of range"));
28207 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28208 newval
|= (rd
<< 8) | value
;
28213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28214 _("immediate value out of range"));
28215 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28216 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28219 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28222 case BFD_RELOC_ARM_THUMB_IMM
:
28223 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28224 if (value
< 0 || value
> 255)
28225 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28226 _("invalid immediate: %ld is out of range"),
28229 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28232 case BFD_RELOC_ARM_THUMB_SHIFT
:
28233 /* 5bit shift value (0..32). LSL cannot take 32. */
28234 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28235 temp
= newval
& 0xf800;
28236 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28238 _("invalid shift value: %ld"), (long) value
);
28239 /* Shifts of zero must be encoded as LSL. */
28241 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28242 /* Shifts of 32 are encoded as zero. */
28243 else if (value
== 32)
28245 newval
|= value
<< 6;
28246 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28249 case BFD_RELOC_VTABLE_INHERIT
:
28250 case BFD_RELOC_VTABLE_ENTRY
:
28254 case BFD_RELOC_ARM_MOVW
:
28255 case BFD_RELOC_ARM_MOVT
:
28256 case BFD_RELOC_ARM_THUMB_MOVW
:
28257 case BFD_RELOC_ARM_THUMB_MOVT
:
28258 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28260 /* REL format relocations are limited to a 16-bit addend. */
28261 if (!fixP
->fx_done
)
28263 if (value
< -0x8000 || value
> 0x7fff)
28264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28265 _("offset out of range"));
28267 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28268 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28273 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28274 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28276 newval
= get_thumb32_insn (buf
);
28277 newval
&= 0xfbf08f00;
28278 newval
|= (value
& 0xf000) << 4;
28279 newval
|= (value
& 0x0800) << 15;
28280 newval
|= (value
& 0x0700) << 4;
28281 newval
|= (value
& 0x00ff);
28282 put_thumb32_insn (buf
, newval
);
28286 newval
= md_chars_to_number (buf
, 4);
28287 newval
&= 0xfff0f000;
28288 newval
|= value
& 0x0fff;
28289 newval
|= (value
& 0xf000) << 4;
28290 md_number_to_chars (buf
, newval
, 4);
28295 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28296 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28297 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28298 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28299 gas_assert (!fixP
->fx_done
);
28302 bfd_boolean is_mov
;
28303 bfd_vma encoded_addend
= value
;
28305 /* Check that addend can be encoded in instruction. */
28306 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28308 _("the offset 0x%08lX is not representable"),
28309 (unsigned long) encoded_addend
);
28311 /* Extract the instruction. */
28312 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28313 is_mov
= (insn
& 0xf800) == 0x2000;
28318 if (!seg
->use_rela_p
)
28319 insn
|= encoded_addend
;
28325 /* Extract the instruction. */
28326 /* Encoding is the following
28331 /* The following conditions must be true :
28336 rd
= (insn
>> 4) & 0xf;
28338 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28340 _("Unable to process relocation for thumb opcode: %lx"),
28341 (unsigned long) insn
);
28343 /* Encode as ADD immediate8 thumb 1 code. */
28344 insn
= 0x3000 | (rd
<< 8);
28346 /* Place the encoded addend into the first 8 bits of the
28348 if (!seg
->use_rela_p
)
28349 insn
|= encoded_addend
;
28352 /* Update the instruction. */
28353 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28357 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28358 case BFD_RELOC_ARM_ALU_PC_G0
:
28359 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28360 case BFD_RELOC_ARM_ALU_PC_G1
:
28361 case BFD_RELOC_ARM_ALU_PC_G2
:
28362 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28363 case BFD_RELOC_ARM_ALU_SB_G0
:
28364 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28365 case BFD_RELOC_ARM_ALU_SB_G1
:
28366 case BFD_RELOC_ARM_ALU_SB_G2
:
28367 gas_assert (!fixP
->fx_done
);
28368 if (!seg
->use_rela_p
)
28371 bfd_vma encoded_addend
;
28372 bfd_vma addend_abs
= llabs (value
);
28374 /* Check that the absolute value of the addend can be
28375 expressed as an 8-bit constant plus a rotation. */
28376 encoded_addend
= encode_arm_immediate (addend_abs
);
28377 if (encoded_addend
== (unsigned int) FAIL
)
28378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28379 _("the offset 0x%08lX is not representable"),
28380 (unsigned long) addend_abs
);
28382 /* Extract the instruction. */
28383 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28385 /* If the addend is positive, use an ADD instruction.
28386 Otherwise use a SUB. Take care not to destroy the S bit. */
28387 insn
&= 0xff1fffff;
28393 /* Place the encoded addend into the first 12 bits of the
28395 insn
&= 0xfffff000;
28396 insn
|= encoded_addend
;
28398 /* Update the instruction. */
28399 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28403 case BFD_RELOC_ARM_LDR_PC_G0
:
28404 case BFD_RELOC_ARM_LDR_PC_G1
:
28405 case BFD_RELOC_ARM_LDR_PC_G2
:
28406 case BFD_RELOC_ARM_LDR_SB_G0
:
28407 case BFD_RELOC_ARM_LDR_SB_G1
:
28408 case BFD_RELOC_ARM_LDR_SB_G2
:
28409 gas_assert (!fixP
->fx_done
);
28410 if (!seg
->use_rela_p
)
28413 bfd_vma addend_abs
= llabs (value
);
28415 /* Check that the absolute value of the addend can be
28416 encoded in 12 bits. */
28417 if (addend_abs
>= 0x1000)
28418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28419 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28420 (unsigned long) addend_abs
);
28422 /* Extract the instruction. */
28423 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28425 /* If the addend is negative, clear bit 23 of the instruction.
28426 Otherwise set it. */
28428 insn
&= ~(1 << 23);
28432 /* Place the absolute value of the addend into the first 12 bits
28433 of the instruction. */
28434 insn
&= 0xfffff000;
28435 insn
|= addend_abs
;
28437 /* Update the instruction. */
28438 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28442 case BFD_RELOC_ARM_LDRS_PC_G0
:
28443 case BFD_RELOC_ARM_LDRS_PC_G1
:
28444 case BFD_RELOC_ARM_LDRS_PC_G2
:
28445 case BFD_RELOC_ARM_LDRS_SB_G0
:
28446 case BFD_RELOC_ARM_LDRS_SB_G1
:
28447 case BFD_RELOC_ARM_LDRS_SB_G2
:
28448 gas_assert (!fixP
->fx_done
);
28449 if (!seg
->use_rela_p
)
28452 bfd_vma addend_abs
= llabs (value
);
28454 /* Check that the absolute value of the addend can be
28455 encoded in 8 bits. */
28456 if (addend_abs
>= 0x100)
28457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28458 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28459 (unsigned long) addend_abs
);
28461 /* Extract the instruction. */
28462 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28464 /* If the addend is negative, clear bit 23 of the instruction.
28465 Otherwise set it. */
28467 insn
&= ~(1 << 23);
28471 /* Place the first four bits of the absolute value of the addend
28472 into the first 4 bits of the instruction, and the remaining
28473 four into bits 8 .. 11. */
28474 insn
&= 0xfffff0f0;
28475 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28477 /* Update the instruction. */
28478 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28482 case BFD_RELOC_ARM_LDC_PC_G0
:
28483 case BFD_RELOC_ARM_LDC_PC_G1
:
28484 case BFD_RELOC_ARM_LDC_PC_G2
:
28485 case BFD_RELOC_ARM_LDC_SB_G0
:
28486 case BFD_RELOC_ARM_LDC_SB_G1
:
28487 case BFD_RELOC_ARM_LDC_SB_G2
:
28488 gas_assert (!fixP
->fx_done
);
28489 if (!seg
->use_rela_p
)
28492 bfd_vma addend_abs
= llabs (value
);
28494 /* Check that the absolute value of the addend is a multiple of
28495 four and, when divided by four, fits in 8 bits. */
28496 if (addend_abs
& 0x3)
28497 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28498 _("bad offset 0x%08lX (must be word-aligned)"),
28499 (unsigned long) addend_abs
);
28501 if ((addend_abs
>> 2) > 0xff)
28502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28503 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28504 (unsigned long) addend_abs
);
28506 /* Extract the instruction. */
28507 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28509 /* If the addend is negative, clear bit 23 of the instruction.
28510 Otherwise set it. */
28512 insn
&= ~(1 << 23);
28516 /* Place the addend (divided by four) into the first eight
28517 bits of the instruction. */
28518 insn
&= 0xfffffff0;
28519 insn
|= addend_abs
>> 2;
28521 /* Update the instruction. */
28522 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28526 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28528 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28529 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28530 && ARM_IS_FUNC (fixP
->fx_addsy
)
28531 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28533 /* Force a relocation for a branch 5 bits wide. */
28536 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28540 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28542 addressT boff
= value
>> 1;
28544 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28545 newval
|= (boff
<< 7);
28546 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28550 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28552 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28553 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28554 && ARM_IS_FUNC (fixP
->fx_addsy
)
28555 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28559 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28561 _("branch out of range"));
28563 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28565 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28567 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28568 addressT diff
= value
- boff
;
28572 newval
|= 1 << 1; /* T bit. */
28574 else if (diff
!= 2)
28576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28577 _("out of range label-relative fixup value"));
28579 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28583 case BFD_RELOC_ARM_THUMB_BF17
:
28585 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28586 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28587 && ARM_IS_FUNC (fixP
->fx_addsy
)
28588 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28590 /* Force a relocation for a branch 17 bits wide. */
28594 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28598 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28601 addressT immA
, immB
, immC
;
28603 immA
= (value
& 0x0001f000) >> 12;
28604 immB
= (value
& 0x00000ffc) >> 2;
28605 immC
= (value
& 0x00000002) >> 1;
28607 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28608 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28610 newval2
|= (immC
<< 11) | (immB
<< 1);
28611 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28612 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28616 case BFD_RELOC_ARM_THUMB_BF19
:
28618 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28619 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28620 && ARM_IS_FUNC (fixP
->fx_addsy
)
28621 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28623 /* Force a relocation for a branch 19 bits wide. */
28627 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28631 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28634 addressT immA
, immB
, immC
;
28636 immA
= (value
& 0x0007f000) >> 12;
28637 immB
= (value
& 0x00000ffc) >> 2;
28638 immC
= (value
& 0x00000002) >> 1;
28640 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28641 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28643 newval2
|= (immC
<< 11) | (immB
<< 1);
28644 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28645 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28649 case BFD_RELOC_ARM_THUMB_BF13
:
28651 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28652 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28653 && ARM_IS_FUNC (fixP
->fx_addsy
)
28654 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28656 /* Force a relocation for a branch 13 bits wide. */
28660 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28664 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28667 addressT immA
, immB
, immC
;
28669 immA
= (value
& 0x00001000) >> 12;
28670 immB
= (value
& 0x00000ffc) >> 2;
28671 immC
= (value
& 0x00000002) >> 1;
28673 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28674 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28676 newval2
|= (immC
<< 11) | (immB
<< 1);
28677 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28678 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28682 case BFD_RELOC_ARM_THUMB_LOOP12
:
28684 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28685 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28686 && ARM_IS_FUNC (fixP
->fx_addsy
)
28687 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28689 /* Force a relocation for a branch 12 bits wide. */
28693 bfd_vma insn
= get_thumb32_insn (buf
);
28694 /* le lr, <label>, le <label> or letp lr, <label> */
28695 if (((insn
& 0xffffffff) == 0xf00fc001)
28696 || ((insn
& 0xffffffff) == 0xf02fc001)
28697 || ((insn
& 0xffffffff) == 0xf01fc001))
28700 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28703 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28705 addressT imml
, immh
;
28707 immh
= (value
& 0x00000ffc) >> 2;
28708 imml
= (value
& 0x00000002) >> 1;
28710 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28711 newval
|= (imml
<< 11) | (immh
<< 1);
28712 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28716 case BFD_RELOC_ARM_V4BX
:
28717 /* This will need to go in the object file. */
28721 case BFD_RELOC_UNUSED
:
28723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28724 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28728 /* Translate internal representation of relocation info to BFD target
28732 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28735 bfd_reloc_code_real_type code
;
28737 reloc
= XNEW (arelent
);
28739 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28740 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28741 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28743 if (fixp
->fx_pcrel
)
28745 if (section
->use_rela_p
)
28746 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28748 fixp
->fx_offset
= reloc
->address
;
28750 reloc
->addend
= fixp
->fx_offset
;
28752 switch (fixp
->fx_r_type
)
28755 if (fixp
->fx_pcrel
)
28757 code
= BFD_RELOC_8_PCREL
;
28760 /* Fall through. */
28763 if (fixp
->fx_pcrel
)
28765 code
= BFD_RELOC_16_PCREL
;
28768 /* Fall through. */
28771 if (fixp
->fx_pcrel
)
28773 code
= BFD_RELOC_32_PCREL
;
28776 /* Fall through. */
28778 case BFD_RELOC_ARM_MOVW
:
28779 if (fixp
->fx_pcrel
)
28781 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28784 /* Fall through. */
28786 case BFD_RELOC_ARM_MOVT
:
28787 if (fixp
->fx_pcrel
)
28789 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28792 /* Fall through. */
28794 case BFD_RELOC_ARM_THUMB_MOVW
:
28795 if (fixp
->fx_pcrel
)
28797 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28800 /* Fall through. */
28802 case BFD_RELOC_ARM_THUMB_MOVT
:
28803 if (fixp
->fx_pcrel
)
28805 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28808 /* Fall through. */
28810 case BFD_RELOC_NONE
:
28811 case BFD_RELOC_ARM_PCREL_BRANCH
:
28812 case BFD_RELOC_ARM_PCREL_BLX
:
28813 case BFD_RELOC_RVA
:
28814 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28815 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28816 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28817 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28818 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28819 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28820 case BFD_RELOC_VTABLE_ENTRY
:
28821 case BFD_RELOC_VTABLE_INHERIT
:
28823 case BFD_RELOC_32_SECREL
:
28825 code
= fixp
->fx_r_type
;
28828 case BFD_RELOC_THUMB_PCREL_BLX
:
28830 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28831 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28834 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28837 case BFD_RELOC_ARM_LITERAL
:
28838 case BFD_RELOC_ARM_HWLITERAL
:
28839 /* If this is called then the a literal has
28840 been referenced across a section boundary. */
28841 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28842 _("literal referenced across section boundary"));
28846 case BFD_RELOC_ARM_TLS_CALL
:
28847 case BFD_RELOC_ARM_THM_TLS_CALL
:
28848 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28849 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28850 case BFD_RELOC_ARM_GOT32
:
28851 case BFD_RELOC_ARM_GOTOFF
:
28852 case BFD_RELOC_ARM_GOT_PREL
:
28853 case BFD_RELOC_ARM_PLT32
:
28854 case BFD_RELOC_ARM_TARGET1
:
28855 case BFD_RELOC_ARM_ROSEGREL32
:
28856 case BFD_RELOC_ARM_SBREL32
:
28857 case BFD_RELOC_ARM_PREL31
:
28858 case BFD_RELOC_ARM_TARGET2
:
28859 case BFD_RELOC_ARM_TLS_LDO32
:
28860 case BFD_RELOC_ARM_PCREL_CALL
:
28861 case BFD_RELOC_ARM_PCREL_JUMP
:
28862 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28863 case BFD_RELOC_ARM_ALU_PC_G0
:
28864 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28865 case BFD_RELOC_ARM_ALU_PC_G1
:
28866 case BFD_RELOC_ARM_ALU_PC_G2
:
28867 case BFD_RELOC_ARM_LDR_PC_G0
:
28868 case BFD_RELOC_ARM_LDR_PC_G1
:
28869 case BFD_RELOC_ARM_LDR_PC_G2
:
28870 case BFD_RELOC_ARM_LDRS_PC_G0
:
28871 case BFD_RELOC_ARM_LDRS_PC_G1
:
28872 case BFD_RELOC_ARM_LDRS_PC_G2
:
28873 case BFD_RELOC_ARM_LDC_PC_G0
:
28874 case BFD_RELOC_ARM_LDC_PC_G1
:
28875 case BFD_RELOC_ARM_LDC_PC_G2
:
28876 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28877 case BFD_RELOC_ARM_ALU_SB_G0
:
28878 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28879 case BFD_RELOC_ARM_ALU_SB_G1
:
28880 case BFD_RELOC_ARM_ALU_SB_G2
:
28881 case BFD_RELOC_ARM_LDR_SB_G0
:
28882 case BFD_RELOC_ARM_LDR_SB_G1
:
28883 case BFD_RELOC_ARM_LDR_SB_G2
:
28884 case BFD_RELOC_ARM_LDRS_SB_G0
:
28885 case BFD_RELOC_ARM_LDRS_SB_G1
:
28886 case BFD_RELOC_ARM_LDRS_SB_G2
:
28887 case BFD_RELOC_ARM_LDC_SB_G0
:
28888 case BFD_RELOC_ARM_LDC_SB_G1
:
28889 case BFD_RELOC_ARM_LDC_SB_G2
:
28890 case BFD_RELOC_ARM_V4BX
:
28891 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28892 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28893 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28894 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28895 case BFD_RELOC_ARM_GOTFUNCDESC
:
28896 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28897 case BFD_RELOC_ARM_FUNCDESC
:
28898 case BFD_RELOC_ARM_THUMB_BF17
:
28899 case BFD_RELOC_ARM_THUMB_BF19
:
28900 case BFD_RELOC_ARM_THUMB_BF13
:
28901 code
= fixp
->fx_r_type
;
28904 case BFD_RELOC_ARM_TLS_GOTDESC
:
28905 case BFD_RELOC_ARM_TLS_GD32
:
28906 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28907 case BFD_RELOC_ARM_TLS_LE32
:
28908 case BFD_RELOC_ARM_TLS_IE32
:
28909 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28910 case BFD_RELOC_ARM_TLS_LDM32
:
28911 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28912 /* BFD will include the symbol's address in the addend.
28913 But we don't want that, so subtract it out again here. */
28914 if (!S_IS_COMMON (fixp
->fx_addsy
))
28915 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28916 code
= fixp
->fx_r_type
;
28920 case BFD_RELOC_ARM_IMMEDIATE
:
28921 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28922 _("internal relocation (type: IMMEDIATE) not fixed up"));
28925 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28926 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28927 _("ADRL used for a symbol not defined in the same file"));
28930 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28931 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28932 case BFD_RELOC_ARM_THUMB_LOOP12
:
28933 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28934 _("%s used for a symbol not defined in the same file"),
28935 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28938 case BFD_RELOC_ARM_OFFSET_IMM
:
28939 if (section
->use_rela_p
)
28941 code
= fixp
->fx_r_type
;
28945 if (fixp
->fx_addsy
!= NULL
28946 && !S_IS_DEFINED (fixp
->fx_addsy
)
28947 && S_IS_LOCAL (fixp
->fx_addsy
))
28949 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28950 _("undefined local label `%s'"),
28951 S_GET_NAME (fixp
->fx_addsy
));
28955 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28956 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28963 switch (fixp
->fx_r_type
)
28965 case BFD_RELOC_NONE
: type
= "NONE"; break;
28966 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28967 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28968 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28969 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28970 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28971 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28972 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28973 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28974 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28975 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28976 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28977 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28978 default: type
= _("<unknown>"); break;
28980 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28981 _("cannot represent %s relocation in this object file format"),
28988 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28990 && fixp
->fx_addsy
== GOT_symbol
)
28992 code
= BFD_RELOC_ARM_GOTPC
;
28993 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
28997 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
28999 if (reloc
->howto
== NULL
)
29001 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29002 _("cannot represent %s relocation in this object file format"),
29003 bfd_get_reloc_code_name (code
));
29007 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29008 vtable entry to be used in the relocation's section offset. */
29009 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29010 reloc
->address
= fixp
->fx_offset
;
29015 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29018 cons_fix_new_arm (fragS
* frag
,
29022 bfd_reloc_code_real_type reloc
)
29027 FIXME: @@ Should look at CPU word size. */
29031 reloc
= BFD_RELOC_8
;
29034 reloc
= BFD_RELOC_16
;
29038 reloc
= BFD_RELOC_32
;
29041 reloc
= BFD_RELOC_64
;
29046 if (exp
->X_op
== O_secrel
)
29048 exp
->X_op
= O_symbol
;
29049 reloc
= BFD_RELOC_32_SECREL
;
29053 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29056 #if defined (OBJ_COFF)
29058 arm_validate_fix (fixS
* fixP
)
29060 /* If the destination of the branch is a defined symbol which does not have
29061 the THUMB_FUNC attribute, then we must be calling a function which has
29062 the (interfacearm) attribute. We look for the Thumb entry point to that
29063 function and change the branch to refer to that function instead. */
29064 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29065 && fixP
->fx_addsy
!= NULL
29066 && S_IS_DEFINED (fixP
->fx_addsy
)
29067 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29069 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29076 arm_force_relocation (struct fix
* fixp
)
29078 #if defined (OBJ_COFF) && defined (TE_PE)
29079 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29083 /* In case we have a call or a branch to a function in ARM ISA mode from
29084 a thumb function or vice-versa force the relocation. These relocations
29085 are cleared off for some cores that might have blx and simple transformations
29089 switch (fixp
->fx_r_type
)
29091 case BFD_RELOC_ARM_PCREL_JUMP
:
29092 case BFD_RELOC_ARM_PCREL_CALL
:
29093 case BFD_RELOC_THUMB_PCREL_BLX
:
29094 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29098 case BFD_RELOC_ARM_PCREL_BLX
:
29099 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29100 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29101 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29102 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29111 /* Resolve these relocations even if the symbol is extern or weak.
29112 Technically this is probably wrong due to symbol preemption.
29113 In practice these relocations do not have enough range to be useful
29114 at dynamic link time, and some code (e.g. in the Linux kernel)
29115 expects these references to be resolved. */
29116 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29117 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29118 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29119 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29120 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29121 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29122 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29123 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29124 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29125 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29126 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29127 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29128 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29129 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29132 /* Always leave these relocations for the linker. */
29133 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29134 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29135 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29138 /* Always generate relocations against function symbols. */
29139 if (fixp
->fx_r_type
== BFD_RELOC_32
29141 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29144 return generic_force_reloc (fixp
);
29147 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29148 /* Relocations against function names must be left unadjusted,
29149 so that the linker can use this information to generate interworking
29150 stubs. The MIPS version of this function
29151 also prevents relocations that are mips-16 specific, but I do not
29152 know why it does this.
29155 There is one other problem that ought to be addressed here, but
29156 which currently is not: Taking the address of a label (rather
29157 than a function) and then later jumping to that address. Such
29158 addresses also ought to have their bottom bit set (assuming that
29159 they reside in Thumb code), but at the moment they will not. */
29162 arm_fix_adjustable (fixS
* fixP
)
29164 if (fixP
->fx_addsy
== NULL
)
29167 /* Preserve relocations against symbols with function type. */
29168 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29171 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29172 && fixP
->fx_subsy
== NULL
)
29175 /* We need the symbol name for the VTABLE entries. */
29176 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29177 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29180 /* Don't allow symbols to be discarded on GOT related relocs. */
29181 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29182 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29183 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29184 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29185 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29186 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29187 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29188 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29189 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29190 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29191 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29192 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29193 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29194 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29195 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29196 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29197 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29200 /* Similarly for group relocations. */
29201 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29202 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29203 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29206 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29207 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29208 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29209 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29210 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29211 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29212 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29213 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29214 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29217 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29218 offsets, so keep these symbols. */
29219 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29220 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29225 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29229 elf32_arm_target_format (void)
29232 return (target_big_endian
29233 ? "elf32-bigarm-symbian"
29234 : "elf32-littlearm-symbian");
29235 #elif defined (TE_VXWORKS)
29236 return (target_big_endian
29237 ? "elf32-bigarm-vxworks"
29238 : "elf32-littlearm-vxworks");
29239 #elif defined (TE_NACL)
29240 return (target_big_endian
29241 ? "elf32-bigarm-nacl"
29242 : "elf32-littlearm-nacl");
29246 if (target_big_endian
)
29247 return "elf32-bigarm-fdpic";
29249 return "elf32-littlearm-fdpic";
29253 if (target_big_endian
)
29254 return "elf32-bigarm";
29256 return "elf32-littlearm";
29262 armelf_frob_symbol (symbolS
* symp
,
29265 elf_frob_symbol (symp
, puntp
);
29269 /* MD interface: Finalization. */
29274 literal_pool
* pool
;
29276 /* Ensure that all the predication blocks are properly closed. */
29277 check_pred_blocks_finished ();
29279 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29281 /* Put it at the end of the relevant section. */
29282 subseg_set (pool
->section
, pool
->sub_section
);
29284 arm_elf_change_section ();
29291 /* Remove any excess mapping symbols generated for alignment frags in
29292 SEC. We may have created a mapping symbol before a zero byte
29293 alignment; remove it if there's a mapping symbol after the
29296 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29297 void *dummy ATTRIBUTE_UNUSED
)
29299 segment_info_type
*seginfo
= seg_info (sec
);
29302 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29305 for (fragp
= seginfo
->frchainP
->frch_root
;
29307 fragp
= fragp
->fr_next
)
29309 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29310 fragS
*next
= fragp
->fr_next
;
29312 /* Variable-sized frags have been converted to fixed size by
29313 this point. But if this was variable-sized to start with,
29314 there will be a fixed-size frag after it. So don't handle
29316 if (sym
== NULL
|| next
== NULL
)
29319 if (S_GET_VALUE (sym
) < next
->fr_address
)
29320 /* Not at the end of this frag. */
29322 know (S_GET_VALUE (sym
) == next
->fr_address
);
29326 if (next
->tc_frag_data
.first_map
!= NULL
)
29328 /* Next frag starts with a mapping symbol. Discard this
29330 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29334 if (next
->fr_next
== NULL
)
29336 /* This mapping symbol is at the end of the section. Discard
29338 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29339 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29343 /* As long as we have empty frags without any mapping symbols,
29345 /* If the next frag is non-empty and does not start with a
29346 mapping symbol, then this mapping symbol is required. */
29347 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29350 next
= next
->fr_next
;
29352 while (next
!= NULL
);
29357 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29361 arm_adjust_symtab (void)
29366 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29368 if (ARM_IS_THUMB (sym
))
29370 if (THUMB_IS_FUNC (sym
))
29372 /* Mark the symbol as a Thumb function. */
29373 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29374 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29375 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29377 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29378 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29380 as_bad (_("%s: unexpected function type: %d"),
29381 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29383 else switch (S_GET_STORAGE_CLASS (sym
))
29386 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29389 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29392 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29400 if (ARM_IS_INTERWORK (sym
))
29401 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29408 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29410 if (ARM_IS_THUMB (sym
))
29412 elf_symbol_type
* elf_sym
;
29414 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29415 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29417 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29418 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29420 /* If it's a .thumb_func, declare it as so,
29421 otherwise tag label as .code 16. */
29422 if (THUMB_IS_FUNC (sym
))
29423 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29424 ST_BRANCH_TO_THUMB
);
29425 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29426 elf_sym
->internal_elf_sym
.st_info
=
29427 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29432 /* Remove any overlapping mapping symbols generated by alignment frags. */
29433 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29434 /* Now do generic ELF adjustments. */
29435 elf_adjust_symtab ();
29439 /* MD interface: Initialization. */
29442 set_constant_flonums (void)
29446 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29447 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29451 /* Auto-select Thumb mode if it's the only available instruction set for the
29452 given architecture. */
29455 autoselect_thumb_from_cpu_variant (void)
29457 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29458 opcode_select (16);
29467 if ( (arm_ops_hsh
= hash_new ()) == NULL
29468 || (arm_cond_hsh
= hash_new ()) == NULL
29469 || (arm_vcond_hsh
= hash_new ()) == NULL
29470 || (arm_shift_hsh
= hash_new ()) == NULL
29471 || (arm_psr_hsh
= hash_new ()) == NULL
29472 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29473 || (arm_reg_hsh
= hash_new ()) == NULL
29474 || (arm_reloc_hsh
= hash_new ()) == NULL
29475 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29476 as_fatal (_("virtual memory exhausted"));
29478 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29479 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29480 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29481 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29482 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29483 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29484 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29485 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29486 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29487 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29488 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29489 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29490 (void *) (v7m_psrs
+ i
));
29491 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29492 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29494 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29496 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29497 (void *) (barrier_opt_names
+ i
));
29499 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29501 struct reloc_entry
* entry
= reloc_names
+ i
;
29503 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29504 /* This makes encode_branch() use the EABI versions of this relocation. */
29505 entry
->reloc
= BFD_RELOC_UNUSED
;
29507 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29511 set_constant_flonums ();
29513 /* Set the cpu variant based on the command-line options. We prefer
29514 -mcpu= over -march= if both are set (as for GCC); and we prefer
29515 -mfpu= over any other way of setting the floating point unit.
29516 Use of legacy options with new options are faulted. */
29519 if (mcpu_cpu_opt
|| march_cpu_opt
)
29520 as_bad (_("use of old and new-style options to set CPU type"));
29522 selected_arch
= *legacy_cpu
;
29524 else if (mcpu_cpu_opt
)
29526 selected_arch
= *mcpu_cpu_opt
;
29527 selected_ext
= *mcpu_ext_opt
;
29529 else if (march_cpu_opt
)
29531 selected_arch
= *march_cpu_opt
;
29532 selected_ext
= *march_ext_opt
;
29534 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29539 as_bad (_("use of old and new-style options to set FPU type"));
29541 selected_fpu
= *legacy_fpu
;
29544 selected_fpu
= *mfpu_opt
;
29547 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29548 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29549 /* Some environments specify a default FPU. If they don't, infer it
29550 from the processor. */
29552 selected_fpu
= *mcpu_fpu_opt
;
29553 else if (march_fpu_opt
)
29554 selected_fpu
= *march_fpu_opt
;
29556 selected_fpu
= fpu_default
;
29560 if (ARM_FEATURE_ZERO (selected_fpu
))
29562 if (!no_cpu_selected ())
29563 selected_fpu
= fpu_default
;
29565 selected_fpu
= fpu_arch_fpa
;
29569 if (ARM_FEATURE_ZERO (selected_arch
))
29571 selected_arch
= cpu_default
;
29572 selected_cpu
= selected_arch
;
29574 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29576 /* Autodection of feature mode: allow all features in cpu_variant but leave
29577 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29578 after all instruction have been processed and we can decide what CPU
29579 should be selected. */
29580 if (ARM_FEATURE_ZERO (selected_arch
))
29581 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29583 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29586 autoselect_thumb_from_cpu_variant ();
29588 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29590 #if defined OBJ_COFF || defined OBJ_ELF
29592 unsigned int flags
= 0;
29594 #if defined OBJ_ELF
29595 flags
= meabi_flags
;
29597 switch (meabi_flags
)
29599 case EF_ARM_EABI_UNKNOWN
:
29601 /* Set the flags in the private structure. */
29602 if (uses_apcs_26
) flags
|= F_APCS26
;
29603 if (support_interwork
) flags
|= F_INTERWORK
;
29604 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29605 if (pic_code
) flags
|= F_PIC
;
29606 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29607 flags
|= F_SOFT_FLOAT
;
29609 switch (mfloat_abi_opt
)
29611 case ARM_FLOAT_ABI_SOFT
:
29612 case ARM_FLOAT_ABI_SOFTFP
:
29613 flags
|= F_SOFT_FLOAT
;
29616 case ARM_FLOAT_ABI_HARD
:
29617 if (flags
& F_SOFT_FLOAT
)
29618 as_bad (_("hard-float conflicts with specified fpu"));
29622 /* Using pure-endian doubles (even if soft-float). */
29623 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29624 flags
|= F_VFP_FLOAT
;
29626 #if defined OBJ_ELF
29627 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29628 flags
|= EF_ARM_MAVERICK_FLOAT
;
29631 case EF_ARM_EABI_VER4
:
29632 case EF_ARM_EABI_VER5
:
29633 /* No additional flags to set. */
29640 bfd_set_private_flags (stdoutput
, flags
);
29642 /* We have run out flags in the COFF header to encode the
29643 status of ATPCS support, so instead we create a dummy,
29644 empty, debug section called .arm.atpcs. */
29649 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29653 bfd_set_section_flags
29654 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29655 bfd_set_section_size (stdoutput
, sec
, 0);
29656 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29662 /* Record the CPU type as well. */
29663 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29664 mach
= bfd_mach_arm_iWMMXt2
;
29665 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29666 mach
= bfd_mach_arm_iWMMXt
;
29667 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29668 mach
= bfd_mach_arm_XScale
;
29669 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29670 mach
= bfd_mach_arm_ep9312
;
29671 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29672 mach
= bfd_mach_arm_5TE
;
29673 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29675 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29676 mach
= bfd_mach_arm_5T
;
29678 mach
= bfd_mach_arm_5
;
29680 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29682 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29683 mach
= bfd_mach_arm_4T
;
29685 mach
= bfd_mach_arm_4
;
29687 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29688 mach
= bfd_mach_arm_3M
;
29689 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29690 mach
= bfd_mach_arm_3
;
29691 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29692 mach
= bfd_mach_arm_2a
;
29693 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29694 mach
= bfd_mach_arm_2
;
29696 mach
= bfd_mach_arm_unknown
;
29698 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29701 /* Command line processing. */
29704 Invocation line includes a switch not recognized by the base assembler.
29705 See if it's a processor-specific option.
29707 This routine is somewhat complicated by the need for backwards
29708 compatibility (since older releases of gcc can't be changed).
29709 The new options try to make the interface as compatible as
29712 New options (supported) are:
29714 -mcpu=<cpu name> Assemble for selected processor
29715 -march=<architecture name> Assemble for selected architecture
29716 -mfpu=<fpu architecture> Assemble for selected FPU.
29717 -EB/-mbig-endian Big-endian
29718 -EL/-mlittle-endian Little-endian
29719 -k Generate PIC code
29720 -mthumb Start in Thumb mode
29721 -mthumb-interwork Code supports ARM/Thumb interworking
29723 -m[no-]warn-deprecated Warn about deprecated features
29724 -m[no-]warn-syms Warn when symbols match instructions
29726 For now we will also provide support for:
29728 -mapcs-32 32-bit Program counter
29729 -mapcs-26 26-bit Program counter
29730 -macps-float Floats passed in FP registers
29731 -mapcs-reentrant Reentrant code
29733 (sometime these will probably be replaced with -mapcs=<list of options>
29734 and -matpcs=<list of options>)
29736 The remaining options are only supported for back-wards compatibility.
29737 Cpu variants, the arm part is optional:
29738 -m[arm]1 Currently not supported.
29739 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29740 -m[arm]3 Arm 3 processor
29741 -m[arm]6[xx], Arm 6 processors
29742 -m[arm]7[xx][t][[d]m] Arm 7 processors
29743 -m[arm]8[10] Arm 8 processors
29744 -m[arm]9[20][tdmi] Arm 9 processors
29745 -mstrongarm[110[0]] StrongARM processors
29746 -mxscale XScale processors
29747 -m[arm]v[2345[t[e]]] Arm architectures
29748 -mall All (except the ARM1)
29750 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29751 -mfpe-old (No float load/store multiples)
29752 -mvfpxd VFP Single precision
29754 -mno-fpu Disable all floating point instructions
29756 The following CPU names are recognized:
29757 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29758 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29759 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29760 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29761 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29762 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29763 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29767 const char * md_shortopts
= "m:k";
29769 #ifdef ARM_BI_ENDIAN
29770 #define OPTION_EB (OPTION_MD_BASE + 0)
29771 #define OPTION_EL (OPTION_MD_BASE + 1)
29773 #if TARGET_BYTES_BIG_ENDIAN
29774 #define OPTION_EB (OPTION_MD_BASE + 0)
29776 #define OPTION_EL (OPTION_MD_BASE + 1)
29779 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29780 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29782 struct option md_longopts
[] =
29785 {"EB", no_argument
, NULL
, OPTION_EB
},
29788 {"EL", no_argument
, NULL
, OPTION_EL
},
29790 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29792 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29794 {NULL
, no_argument
, NULL
, 0}
29797 size_t md_longopts_size
= sizeof (md_longopts
);
29799 struct arm_option_table
29801 const char * option
; /* Option name to match. */
29802 const char * help
; /* Help information. */
29803 int * var
; /* Variable to change. */
29804 int value
; /* What to change it to. */
29805 const char * deprecated
; /* If non-null, print this message. */
29808 struct arm_option_table arm_opts
[] =
29810 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29811 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29812 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29813 &support_interwork
, 1, NULL
},
29814 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29815 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29816 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29818 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29819 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29820 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29821 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29824 /* These are recognized by the assembler, but have no affect on code. */
29825 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29826 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29828 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29829 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29830 &warn_on_deprecated
, 0, NULL
},
29831 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29832 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29833 {NULL
, NULL
, NULL
, 0, NULL
}
29836 struct arm_legacy_option_table
29838 const char * option
; /* Option name to match. */
29839 const arm_feature_set
** var
; /* Variable to change. */
29840 const arm_feature_set value
; /* What to change it to. */
29841 const char * deprecated
; /* If non-null, print this message. */
29844 const struct arm_legacy_option_table arm_legacy_opts
[] =
29846 /* DON'T add any new processors to this list -- we want the whole list
29847 to go away... Add them to the processors table instead. */
29848 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29849 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29850 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29851 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29852 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29853 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29854 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29855 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29856 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29857 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29858 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29859 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29860 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29861 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29862 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29863 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29864 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29865 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29866 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29867 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29868 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29869 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29870 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29871 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29872 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29873 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29874 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29875 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29876 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29877 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29878 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29879 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29880 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29881 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29882 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29883 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29884 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29885 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29886 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29887 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29888 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29889 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29890 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29891 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29892 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29893 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29894 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29895 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29896 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29897 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29898 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29899 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29900 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29901 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29902 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29903 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29904 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29905 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29906 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29907 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29908 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29909 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29910 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29911 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29912 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29913 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29914 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29915 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29916 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29917 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29918 N_("use -mcpu=strongarm110")},
29919 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29920 N_("use -mcpu=strongarm1100")},
29921 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29922 N_("use -mcpu=strongarm1110")},
29923 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29924 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29925 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29927 /* Architecture variants -- don't add any more to this list either. */
29928 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29929 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29930 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29931 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29932 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29933 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29934 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29935 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29936 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29937 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29938 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29939 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29940 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29941 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29942 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29943 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29944 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29945 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29947 /* Floating point variants -- don't add any more to this list either. */
29948 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29949 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29950 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29951 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29952 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29954 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29957 struct arm_cpu_option_table
29961 const arm_feature_set value
;
29962 const arm_feature_set ext
;
29963 /* For some CPUs we assume an FPU unless the user explicitly sets
29965 const arm_feature_set default_fpu
;
29966 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29968 const char * canonical_name
;
29971 /* This list should, at a minimum, contain all the cpu names
29972 recognized by GCC. */
29973 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29975 static const struct arm_cpu_option_table arm_cpus
[] =
29977 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29980 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29983 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29986 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29989 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29992 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
29995 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
29998 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30001 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30004 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30007 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30010 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30013 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30016 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30019 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30022 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30025 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30028 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30031 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30034 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30037 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30040 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30043 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30046 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30049 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30052 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30055 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30058 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30061 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30064 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30067 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30070 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30073 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30076 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30079 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30082 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30085 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30088 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30091 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30094 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30097 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30100 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30103 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30106 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30109 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30112 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30116 /* For V5 or later processors we default to using VFP; but the user
30117 should really set the FPU type explicitly. */
30118 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30121 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30124 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30127 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30130 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30133 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30136 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30139 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30142 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30145 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30148 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30151 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30154 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30157 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30160 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30163 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30166 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30169 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30172 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30175 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30178 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30181 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30184 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30187 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30190 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30193 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30196 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30199 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30202 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30205 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30208 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30211 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30214 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30217 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30220 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30223 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30226 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30227 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30229 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30231 FPU_ARCH_NEON_VFP_V4
),
30232 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30233 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30234 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30235 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30236 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30237 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30238 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30240 FPU_ARCH_NEON_VFP_V4
),
30241 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30243 FPU_ARCH_NEON_VFP_V4
),
30244 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30246 FPU_ARCH_NEON_VFP_V4
),
30247 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30248 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30249 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30250 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30251 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30252 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30253 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30254 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30255 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30256 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30258 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30259 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30260 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30261 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30262 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30263 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30264 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30265 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30266 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30267 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30268 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30270 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30271 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30272 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30273 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30274 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30276 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30277 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30280 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30282 FPU_ARCH_VFP_V3D16
),
30283 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30284 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30286 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30287 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30288 FPU_ARCH_VFP_V3D16
),
30289 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30290 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30291 FPU_ARCH_VFP_V3D16
),
30292 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30293 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30294 FPU_ARCH_NEON_VFP_ARMV8
),
30295 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30296 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30298 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30301 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30304 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30307 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30310 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30313 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30316 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30319 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30320 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30321 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30322 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30323 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30324 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30325 /* ??? XSCALE is really an architecture. */
30326 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30330 /* ??? iwmmxt is not a processor. */
30331 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30334 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30337 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30342 ARM_CPU_OPT ("ep9312", "ARM920T",
30343 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30344 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30346 /* Marvell processors. */
30347 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30348 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30349 FPU_ARCH_VFP_V3D16
),
30350 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30351 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30352 FPU_ARCH_NEON_VFP_V4
),
30354 /* APM X-Gene family. */
30355 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30357 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30358 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30359 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30360 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30362 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30366 struct arm_ext_table
30370 const arm_feature_set merge
;
30371 const arm_feature_set clear
;
30374 struct arm_arch_option_table
30378 const arm_feature_set value
;
30379 const arm_feature_set default_fpu
;
30380 const struct arm_ext_table
* ext_table
;
30383 /* Used to add support for +E and +noE extension. */
30384 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30385 /* Used to add support for a +E extension. */
30386 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30387 /* Used to add support for a +noE extension. */
30388 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30390 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30391 ~0 & ~FPU_ENDIAN_PURE)
30393 static const struct arm_ext_table armv5te_ext_table
[] =
30395 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30396 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30399 static const struct arm_ext_table armv7_ext_table
[] =
30401 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30402 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30405 static const struct arm_ext_table armv7ve_ext_table
[] =
30407 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30408 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30409 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30410 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30411 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30412 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30413 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30415 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30416 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30418 /* Aliases for +simd. */
30419 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30421 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30422 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30423 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30425 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30428 static const struct arm_ext_table armv7a_ext_table
[] =
30430 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30431 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30432 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30433 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30434 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30435 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30436 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30438 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30439 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30441 /* Aliases for +simd. */
30442 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30443 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30445 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30446 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30448 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30449 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30450 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30453 static const struct arm_ext_table armv7r_ext_table
[] =
30455 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30456 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30457 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30458 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30459 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30460 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30461 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30462 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30463 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30466 static const struct arm_ext_table armv7em_ext_table
[] =
30468 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30469 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30470 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30471 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30472 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30473 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30474 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30477 static const struct arm_ext_table armv8a_ext_table
[] =
30479 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30480 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30481 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30482 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30484 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30485 should use the +simd option to turn on FP. */
30486 ARM_REMOVE ("fp", ALL_FP
),
30487 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30488 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30489 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30493 static const struct arm_ext_table armv81a_ext_table
[] =
30495 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30496 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30497 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30499 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30500 should use the +simd option to turn on FP. */
30501 ARM_REMOVE ("fp", ALL_FP
),
30502 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30503 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30504 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30507 static const struct arm_ext_table armv82a_ext_table
[] =
30509 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30510 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30511 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30512 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30513 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30514 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30516 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30517 should use the +simd option to turn on FP. */
30518 ARM_REMOVE ("fp", ALL_FP
),
30519 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30520 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30521 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30524 static const struct arm_ext_table armv84a_ext_table
[] =
30526 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30527 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30528 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30529 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30531 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30532 should use the +simd option to turn on FP. */
30533 ARM_REMOVE ("fp", ALL_FP
),
30534 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30535 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30536 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30539 static const struct arm_ext_table armv85a_ext_table
[] =
30541 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30542 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30543 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30544 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30546 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30547 should use the +simd option to turn on FP. */
30548 ARM_REMOVE ("fp", ALL_FP
),
30549 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30552 static const struct arm_ext_table armv8m_main_ext_table
[] =
30554 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30555 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30556 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30557 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30558 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30561 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30563 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30564 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30566 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30567 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30570 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30571 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30572 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30573 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30575 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30576 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30577 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30578 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30581 static const struct arm_ext_table armv8r_ext_table
[] =
30583 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30584 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30585 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30586 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30587 ARM_REMOVE ("fp", ALL_FP
),
30588 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30589 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30592 /* This list should, at a minimum, contain all the architecture names
30593 recognized by GCC. */
30594 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30595 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30596 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30598 static const struct arm_arch_option_table arm_archs
[] =
30600 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30601 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30602 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30603 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30604 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30605 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30606 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30607 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30608 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30609 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30610 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30611 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30612 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30613 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30614 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30615 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30616 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30617 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30618 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30619 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30620 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30621 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30622 kept to preserve existing behaviour. */
30623 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30624 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30625 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30626 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30627 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30628 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30629 kept to preserve existing behaviour. */
30630 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30631 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30632 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30633 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30634 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30635 /* The official spelling of the ARMv7 profile variants is the dashed form.
30636 Accept the non-dashed form for compatibility with old toolchains. */
30637 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30638 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30639 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30640 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30641 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30642 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30643 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30644 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30645 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30646 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30648 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30650 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30651 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30652 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30653 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30654 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30655 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30656 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30657 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30658 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30659 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30660 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30662 #undef ARM_ARCH_OPT
30664 /* ISA extensions in the co-processor and main instruction set space. */
30666 struct arm_option_extension_value_table
30670 const arm_feature_set merge_value
;
30671 const arm_feature_set clear_value
;
30672 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30673 indicates that an extension is available for all architectures while
30674 ARM_ANY marks an empty entry. */
30675 const arm_feature_set allowed_archs
[2];
30678 /* The following table must be in alphabetical order with a NULL last entry. */
30680 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30681 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30683 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30684 use the context sensitive approach using arm_ext_table's. */
30685 static const struct arm_option_extension_value_table arm_extensions
[] =
30687 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30688 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30689 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30690 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30691 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30692 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30693 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30695 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30696 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30697 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30698 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30699 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30700 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30701 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30703 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30704 | ARM_EXT2_FP16_FML
),
30705 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30706 | ARM_EXT2_FP16_FML
),
30708 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30709 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30710 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30711 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30712 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30713 Thumb divide instruction. Due to this having the same name as the
30714 previous entry, this will be ignored when doing command-line parsing and
30715 only considered by build attribute selection code. */
30716 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30717 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30718 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30719 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30720 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30721 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30722 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30723 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30724 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30725 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30726 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30727 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30728 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30729 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30730 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30731 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30732 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30733 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30734 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30735 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30736 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30738 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30739 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30740 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30741 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30742 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30743 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30744 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30745 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30747 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30748 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30749 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30750 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30751 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30752 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30753 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30754 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30756 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30757 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30758 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30759 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30760 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30764 /* ISA floating-point and Advanced SIMD extensions. */
30765 struct arm_option_fpu_value_table
30768 const arm_feature_set value
;
30771 /* This list should, at a minimum, contain all the fpu names
30772 recognized by GCC. */
30773 static const struct arm_option_fpu_value_table arm_fpus
[] =
30775 {"softfpa", FPU_NONE
},
30776 {"fpe", FPU_ARCH_FPE
},
30777 {"fpe2", FPU_ARCH_FPE
},
30778 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30779 {"fpa", FPU_ARCH_FPA
},
30780 {"fpa10", FPU_ARCH_FPA
},
30781 {"fpa11", FPU_ARCH_FPA
},
30782 {"arm7500fe", FPU_ARCH_FPA
},
30783 {"softvfp", FPU_ARCH_VFP
},
30784 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30785 {"vfp", FPU_ARCH_VFP_V2
},
30786 {"vfp9", FPU_ARCH_VFP_V2
},
30787 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30788 {"vfp10", FPU_ARCH_VFP_V2
},
30789 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30790 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30791 {"vfpv2", FPU_ARCH_VFP_V2
},
30792 {"vfpv3", FPU_ARCH_VFP_V3
},
30793 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30794 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30795 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30796 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30797 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30798 {"arm1020t", FPU_ARCH_VFP_V1
},
30799 {"arm1020e", FPU_ARCH_VFP_V2
},
30800 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30801 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30802 {"maverick", FPU_ARCH_MAVERICK
},
30803 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30804 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30805 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30806 {"vfpv4", FPU_ARCH_VFP_V4
},
30807 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30808 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30809 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30810 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30811 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30812 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30813 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30814 {"crypto-neon-fp-armv8",
30815 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30816 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30817 {"crypto-neon-fp-armv8.1",
30818 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30819 {NULL
, ARM_ARCH_NONE
}
30822 struct arm_option_value_table
30828 static const struct arm_option_value_table arm_float_abis
[] =
30830 {"hard", ARM_FLOAT_ABI_HARD
},
30831 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30832 {"soft", ARM_FLOAT_ABI_SOFT
},
30837 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30838 static const struct arm_option_value_table arm_eabis
[] =
30840 {"gnu", EF_ARM_EABI_UNKNOWN
},
30841 {"4", EF_ARM_EABI_VER4
},
30842 {"5", EF_ARM_EABI_VER5
},
30847 struct arm_long_option_table
30849 const char * option
; /* Substring to match. */
30850 const char * help
; /* Help information. */
30851 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30852 const char * deprecated
; /* If non-null, print this message. */
30856 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30857 arm_feature_set
*ext_set
,
30858 const struct arm_ext_table
*ext_table
)
30860 /* We insist on extensions being specified in alphabetical order, and with
30861 extensions being added before being removed. We achieve this by having
30862 the global ARM_EXTENSIONS table in alphabetical order, and using the
30863 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30864 or removing it (0) and only allowing it to change in the order
30866 const struct arm_option_extension_value_table
* opt
= NULL
;
30867 const arm_feature_set arm_any
= ARM_ANY
;
30868 int adding_value
= -1;
30870 while (str
!= NULL
&& *str
!= 0)
30877 as_bad (_("invalid architectural extension"));
30882 ext
= strchr (str
, '+');
30887 len
= strlen (str
);
30889 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30891 if (adding_value
!= 0)
30894 opt
= arm_extensions
;
30902 if (adding_value
== -1)
30905 opt
= arm_extensions
;
30907 else if (adding_value
!= 1)
30909 as_bad (_("must specify extensions to add before specifying "
30910 "those to remove"));
30917 as_bad (_("missing architectural extension"));
30921 gas_assert (adding_value
!= -1);
30922 gas_assert (opt
!= NULL
);
30924 if (ext_table
!= NULL
)
30926 const struct arm_ext_table
* ext_opt
= ext_table
;
30927 bfd_boolean found
= FALSE
;
30928 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30929 if (ext_opt
->name_len
== len
30930 && strncmp (ext_opt
->name
, str
, len
) == 0)
30934 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30935 /* TODO: Option not supported. When we remove the
30936 legacy table this case should error out. */
30939 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30943 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30944 /* TODO: Option not supported. When we remove the
30945 legacy table this case should error out. */
30947 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30959 /* Scan over the options table trying to find an exact match. */
30960 for (; opt
->name
!= NULL
; opt
++)
30961 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30963 int i
, nb_allowed_archs
=
30964 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30965 /* Check we can apply the extension to this architecture. */
30966 for (i
= 0; i
< nb_allowed_archs
; i
++)
30969 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30971 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30974 if (i
== nb_allowed_archs
)
30976 as_bad (_("extension does not apply to the base architecture"));
30980 /* Add or remove the extension. */
30982 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30984 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30986 /* Allowing Thumb division instructions for ARMv7 in autodetection
30987 rely on this break so that duplicate extensions (extensions
30988 with the same name as a previous extension in the list) are not
30989 considered for command-line parsing. */
30993 if (opt
->name
== NULL
)
30995 /* Did we fail to find an extension because it wasn't specified in
30996 alphabetical order, or because it does not exist? */
30998 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30999 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31002 if (opt
->name
== NULL
)
31003 as_bad (_("unknown architectural extension `%s'"), str
);
31005 as_bad (_("architectural extensions must be specified in "
31006 "alphabetical order"));
31012 /* We should skip the extension we've just matched the next time
31024 arm_parse_cpu (const char *str
)
31026 const struct arm_cpu_option_table
*opt
;
31027 const char *ext
= strchr (str
, '+');
31033 len
= strlen (str
);
31037 as_bad (_("missing cpu name `%s'"), str
);
31041 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31042 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31044 mcpu_cpu_opt
= &opt
->value
;
31045 if (mcpu_ext_opt
== NULL
)
31046 mcpu_ext_opt
= XNEW (arm_feature_set
);
31047 *mcpu_ext_opt
= opt
->ext
;
31048 mcpu_fpu_opt
= &opt
->default_fpu
;
31049 if (opt
->canonical_name
)
31051 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31052 strcpy (selected_cpu_name
, opt
->canonical_name
);
31058 if (len
>= sizeof selected_cpu_name
)
31059 len
= (sizeof selected_cpu_name
) - 1;
31061 for (i
= 0; i
< len
; i
++)
31062 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31063 selected_cpu_name
[i
] = 0;
31067 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31072 as_bad (_("unknown cpu `%s'"), str
);
31077 arm_parse_arch (const char *str
)
31079 const struct arm_arch_option_table
*opt
;
31080 const char *ext
= strchr (str
, '+');
31086 len
= strlen (str
);
31090 as_bad (_("missing architecture name `%s'"), str
);
31094 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31095 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31097 march_cpu_opt
= &opt
->value
;
31098 if (march_ext_opt
== NULL
)
31099 march_ext_opt
= XNEW (arm_feature_set
);
31100 *march_ext_opt
= arm_arch_none
;
31101 march_fpu_opt
= &opt
->default_fpu
;
31102 strcpy (selected_cpu_name
, opt
->name
);
31105 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31111 as_bad (_("unknown architecture `%s'\n"), str
);
31116 arm_parse_fpu (const char * str
)
31118 const struct arm_option_fpu_value_table
* opt
;
31120 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31121 if (streq (opt
->name
, str
))
31123 mfpu_opt
= &opt
->value
;
31127 as_bad (_("unknown floating point format `%s'\n"), str
);
31132 arm_parse_float_abi (const char * str
)
31134 const struct arm_option_value_table
* opt
;
31136 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31137 if (streq (opt
->name
, str
))
31139 mfloat_abi_opt
= opt
->value
;
31143 as_bad (_("unknown floating point abi `%s'\n"), str
);
31149 arm_parse_eabi (const char * str
)
31151 const struct arm_option_value_table
*opt
;
31153 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31154 if (streq (opt
->name
, str
))
31156 meabi_flags
= opt
->value
;
31159 as_bad (_("unknown EABI `%s'\n"), str
);
31165 arm_parse_it_mode (const char * str
)
31167 bfd_boolean ret
= TRUE
;
31169 if (streq ("arm", str
))
31170 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31171 else if (streq ("thumb", str
))
31172 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31173 else if (streq ("always", str
))
31174 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31175 else if (streq ("never", str
))
31176 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31179 as_bad (_("unknown implicit IT mode `%s', should be "\
31180 "arm, thumb, always, or never."), str
);
31188 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31190 codecomposer_syntax
= TRUE
;
31191 arm_comment_chars
[0] = ';';
31192 arm_line_separator_chars
[0] = 0;
31196 struct arm_long_option_table arm_long_opts
[] =
31198 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31199 arm_parse_cpu
, NULL
},
31200 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31201 arm_parse_arch
, NULL
},
31202 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31203 arm_parse_fpu
, NULL
},
31204 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31205 arm_parse_float_abi
, NULL
},
31207 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31208 arm_parse_eabi
, NULL
},
31210 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31211 arm_parse_it_mode
, NULL
},
31212 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31213 arm_ccs_mode
, NULL
},
31214 {NULL
, NULL
, 0, NULL
}
31218 md_parse_option (int c
, const char * arg
)
31220 struct arm_option_table
*opt
;
31221 const struct arm_legacy_option_table
*fopt
;
31222 struct arm_long_option_table
*lopt
;
31228 target_big_endian
= 1;
31234 target_big_endian
= 0;
31238 case OPTION_FIX_V4BX
:
31246 #endif /* OBJ_ELF */
31249 /* Listing option. Just ignore these, we don't support additional
31254 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31256 if (c
== opt
->option
[0]
31257 && ((arg
== NULL
&& opt
->option
[1] == 0)
31258 || streq (arg
, opt
->option
+ 1)))
31260 /* If the option is deprecated, tell the user. */
31261 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31262 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31263 arg
? arg
: "", _(opt
->deprecated
));
31265 if (opt
->var
!= NULL
)
31266 *opt
->var
= opt
->value
;
31272 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31274 if (c
== fopt
->option
[0]
31275 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31276 || streq (arg
, fopt
->option
+ 1)))
31278 /* If the option is deprecated, tell the user. */
31279 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31280 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31281 arg
? arg
: "", _(fopt
->deprecated
));
31283 if (fopt
->var
!= NULL
)
31284 *fopt
->var
= &fopt
->value
;
31290 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31292 /* These options are expected to have an argument. */
31293 if (c
== lopt
->option
[0]
31295 && strncmp (arg
, lopt
->option
+ 1,
31296 strlen (lopt
->option
+ 1)) == 0)
31298 /* If the option is deprecated, tell the user. */
31299 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31300 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31301 _(lopt
->deprecated
));
31303 /* Call the sup-option parser. */
31304 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31315 md_show_usage (FILE * fp
)
31317 struct arm_option_table
*opt
;
31318 struct arm_long_option_table
*lopt
;
31320 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31322 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31323 if (opt
->help
!= NULL
)
31324 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31326 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31327 if (lopt
->help
!= NULL
)
31328 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31332 -EB assemble code for a big-endian cpu\n"));
31337 -EL assemble code for a little-endian cpu\n"));
31341 --fix-v4bx Allow BX in ARMv4 code\n"));
31345 --fdpic generate an FDPIC object file\n"));
31346 #endif /* OBJ_ELF */
31354 arm_feature_set flags
;
31355 } cpu_arch_ver_table
;
31357 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31358 chronologically for architectures, with an exception for ARMv6-M and
31359 ARMv6S-M due to legacy reasons. No new architecture should have a
31360 special case. This allows for build attribute selection results to be
31361 stable when new architectures are added. */
31362 static const cpu_arch_ver_table cpu_arch_ver
[] =
31364 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31365 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31366 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31367 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31368 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31369 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31370 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31371 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31372 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31373 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31374 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31375 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31376 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31377 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31378 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31379 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31380 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31381 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31382 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31383 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31384 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31385 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31386 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31387 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31389 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31390 always selected build attributes to match those of ARMv6-M
31391 (resp. ARMv6S-M). However, due to these architectures being a strict
31392 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31393 would be selected when fully respecting chronology of architectures.
31394 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31395 move them before ARMv7 architectures. */
31396 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31397 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31399 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31400 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31401 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31402 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31403 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31404 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31405 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31406 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31407 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31408 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31409 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31410 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31411 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31412 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31413 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31414 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31415 {-1, ARM_ARCH_NONE
}
31418 /* Set an attribute if it has not already been set by the user. */
31421 aeabi_set_attribute_int (int tag
, int value
)
31424 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31425 || !attributes_set_explicitly
[tag
])
31426 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31430 aeabi_set_attribute_string (int tag
, const char *value
)
31433 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31434 || !attributes_set_explicitly
[tag
])
31435 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31438 /* Return whether features in the *NEEDED feature set are available via
31439 extensions for the architecture whose feature set is *ARCH_FSET. */
31442 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31443 const arm_feature_set
*needed
)
31445 int i
, nb_allowed_archs
;
31446 arm_feature_set ext_fset
;
31447 const struct arm_option_extension_value_table
*opt
;
31449 ext_fset
= arm_arch_none
;
31450 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31452 /* Extension does not provide any feature we need. */
31453 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31457 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31458 for (i
= 0; i
< nb_allowed_archs
; i
++)
31461 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31464 /* Extension is available, add it. */
31465 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31466 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31470 /* Can we enable all features in *needed? */
31471 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31474 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31475 a given architecture feature set *ARCH_EXT_FSET including extension feature
31476 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31477 - if true, check for an exact match of the architecture modulo extensions;
31478 - otherwise, select build attribute value of the first superset
31479 architecture released so that results remains stable when new architectures
31481 For -march/-mcpu=all the build attribute value of the most featureful
31482 architecture is returned. Tag_CPU_arch_profile result is returned in
31486 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31487 const arm_feature_set
*ext_fset
,
31488 char *profile
, int exact_match
)
31490 arm_feature_set arch_fset
;
31491 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31493 /* Select most featureful architecture with all its extensions if building
31494 for -march=all as the feature sets used to set build attributes. */
31495 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31497 /* Force revisiting of decision for each new architecture. */
31498 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31500 return TAG_CPU_ARCH_V8
;
31503 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31505 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31507 arm_feature_set known_arch_fset
;
31509 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31512 /* Base architecture match user-specified architecture and
31513 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31514 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31519 /* Base architecture match user-specified architecture only
31520 (eg. ARMv6-M in the same case as above). Record it in case we
31521 find a match with above condition. */
31522 else if (p_ver_ret
== NULL
31523 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31529 /* Architecture has all features wanted. */
31530 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31532 arm_feature_set added_fset
;
31534 /* Compute features added by this architecture over the one
31535 recorded in p_ver_ret. */
31536 if (p_ver_ret
!= NULL
)
31537 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31539 /* First architecture that match incl. with extensions, or the
31540 only difference in features over the recorded match is
31541 features that were optional and are now mandatory. */
31542 if (p_ver_ret
== NULL
31543 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31549 else if (p_ver_ret
== NULL
)
31551 arm_feature_set needed_ext_fset
;
31553 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31555 /* Architecture has all features needed when using some
31556 extensions. Record it and continue searching in case there
31557 exist an architecture providing all needed features without
31558 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31560 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31567 if (p_ver_ret
== NULL
)
31571 /* Tag_CPU_arch_profile. */
31572 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31573 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31574 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31575 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31577 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31579 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31583 return p_ver_ret
->val
;
31586 /* Set the public EABI object attributes. */
31589 aeabi_set_public_attributes (void)
31591 char profile
= '\0';
31594 int fp16_optional
= 0;
31595 int skip_exact_match
= 0;
31596 arm_feature_set flags
, flags_arch
, flags_ext
;
31598 /* Autodetection mode, choose the architecture based the instructions
31600 if (no_cpu_selected ())
31602 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31604 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31605 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31607 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31608 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31610 /* Code run during relaxation relies on selected_cpu being set. */
31611 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31612 flags_ext
= arm_arch_none
;
31613 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31614 selected_ext
= flags_ext
;
31615 selected_cpu
= flags
;
31617 /* Otherwise, choose the architecture based on the capabilities of the
31621 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31622 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31623 flags_ext
= selected_ext
;
31624 flags
= selected_cpu
;
31626 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31628 /* Allow the user to override the reported architecture. */
31629 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31631 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31632 flags_ext
= arm_arch_none
;
31635 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31637 /* When this function is run again after relaxation has happened there is no
31638 way to determine whether an architecture or CPU was specified by the user:
31639 - selected_cpu is set above for relaxation to work;
31640 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31641 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31642 Therefore, if not in -march=all case we first try an exact match and fall
31643 back to autodetection. */
31644 if (!skip_exact_match
)
31645 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31647 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31649 as_bad (_("no architecture contains all the instructions used\n"));
31651 /* Tag_CPU_name. */
31652 if (selected_cpu_name
[0])
31656 q
= selected_cpu_name
;
31657 if (strncmp (q
, "armv", 4) == 0)
31662 for (i
= 0; q
[i
]; i
++)
31663 q
[i
] = TOUPPER (q
[i
]);
31665 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31668 /* Tag_CPU_arch. */
31669 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31671 /* Tag_CPU_arch_profile. */
31672 if (profile
!= '\0')
31673 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31675 /* Tag_DSP_extension. */
31676 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31677 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31679 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31680 /* Tag_ARM_ISA_use. */
31681 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31682 || ARM_FEATURE_ZERO (flags_arch
))
31683 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31685 /* Tag_THUMB_ISA_use. */
31686 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31687 || ARM_FEATURE_ZERO (flags_arch
))
31691 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31692 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31694 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31698 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31701 /* Tag_VFP_arch. */
31702 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31703 aeabi_set_attribute_int (Tag_VFP_arch
,
31704 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31706 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31707 aeabi_set_attribute_int (Tag_VFP_arch
,
31708 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31710 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31713 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31715 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31717 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31720 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31721 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31722 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31723 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31724 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31726 /* Tag_ABI_HardFP_use. */
31727 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31728 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31729 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31731 /* Tag_WMMX_arch. */
31732 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31733 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31734 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31735 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31737 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31738 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31739 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31740 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31741 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31742 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31744 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31746 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31750 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31755 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31756 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31757 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31758 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31760 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31761 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31762 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31766 We set Tag_DIV_use to two when integer divide instructions have been used
31767 in ARM state, or when Thumb integer divide instructions have been used,
31768 but we have no architecture profile set, nor have we any ARM instructions.
31770 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31771 by the base architecture.
31773 For new architectures we will have to check these tests. */
31774 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31775 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31776 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31777 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31778 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31779 || (profile
== '\0'
31780 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31781 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31782 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31784 /* Tag_MP_extension_use. */
31785 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31786 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31788 /* Tag Virtualization_use. */
31789 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31791 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31794 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31797 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31798 finished and free extension feature bits which will not be used anymore. */
31801 arm_md_post_relax (void)
31803 aeabi_set_public_attributes ();
31804 XDELETE (mcpu_ext_opt
);
31805 mcpu_ext_opt
= NULL
;
31806 XDELETE (march_ext_opt
);
31807 march_ext_opt
= NULL
;
31810 /* Add the default contents for the .ARM.attributes section. */
31815 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31818 aeabi_set_public_attributes ();
31820 #endif /* OBJ_ELF */
31822 /* Parse a .cpu directive. */
31825 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31827 const struct arm_cpu_option_table
*opt
;
31831 name
= input_line_pointer
;
31832 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31833 input_line_pointer
++;
31834 saved_char
= *input_line_pointer
;
31835 *input_line_pointer
= 0;
31837 /* Skip the first "all" entry. */
31838 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31839 if (streq (opt
->name
, name
))
31841 selected_arch
= opt
->value
;
31842 selected_ext
= opt
->ext
;
31843 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31844 if (opt
->canonical_name
)
31845 strcpy (selected_cpu_name
, opt
->canonical_name
);
31849 for (i
= 0; opt
->name
[i
]; i
++)
31850 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31852 selected_cpu_name
[i
] = 0;
31854 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31856 *input_line_pointer
= saved_char
;
31857 demand_empty_rest_of_line ();
31860 as_bad (_("unknown cpu `%s'"), name
);
31861 *input_line_pointer
= saved_char
;
31862 ignore_rest_of_line ();
31865 /* Parse a .arch directive. */
31868 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31870 const struct arm_arch_option_table
*opt
;
31874 name
= input_line_pointer
;
31875 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31876 input_line_pointer
++;
31877 saved_char
= *input_line_pointer
;
31878 *input_line_pointer
= 0;
31880 /* Skip the first "all" entry. */
31881 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31882 if (streq (opt
->name
, name
))
31884 selected_arch
= opt
->value
;
31885 selected_ext
= arm_arch_none
;
31886 selected_cpu
= selected_arch
;
31887 strcpy (selected_cpu_name
, opt
->name
);
31888 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31889 *input_line_pointer
= saved_char
;
31890 demand_empty_rest_of_line ();
31894 as_bad (_("unknown architecture `%s'\n"), name
);
31895 *input_line_pointer
= saved_char
;
31896 ignore_rest_of_line ();
31899 /* Parse a .object_arch directive. */
31902 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31904 const struct arm_arch_option_table
*opt
;
31908 name
= input_line_pointer
;
31909 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31910 input_line_pointer
++;
31911 saved_char
= *input_line_pointer
;
31912 *input_line_pointer
= 0;
31914 /* Skip the first "all" entry. */
31915 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31916 if (streq (opt
->name
, name
))
31918 selected_object_arch
= opt
->value
;
31919 *input_line_pointer
= saved_char
;
31920 demand_empty_rest_of_line ();
31924 as_bad (_("unknown architecture `%s'\n"), name
);
31925 *input_line_pointer
= saved_char
;
31926 ignore_rest_of_line ();
31929 /* Parse a .arch_extension directive. */
31932 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31934 const struct arm_option_extension_value_table
*opt
;
31937 int adding_value
= 1;
31939 name
= input_line_pointer
;
31940 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31941 input_line_pointer
++;
31942 saved_char
= *input_line_pointer
;
31943 *input_line_pointer
= 0;
31945 if (strlen (name
) >= 2
31946 && strncmp (name
, "no", 2) == 0)
31952 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31953 if (streq (opt
->name
, name
))
31955 int i
, nb_allowed_archs
=
31956 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31957 for (i
= 0; i
< nb_allowed_archs
; i
++)
31960 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31962 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31966 if (i
== nb_allowed_archs
)
31968 as_bad (_("architectural extension `%s' is not allowed for the "
31969 "current base architecture"), name
);
31974 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31977 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31979 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31980 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31981 *input_line_pointer
= saved_char
;
31982 demand_empty_rest_of_line ();
31983 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31984 on this return so that duplicate extensions (extensions with the
31985 same name as a previous extension in the list) are not considered
31986 for command-line parsing. */
31990 if (opt
->name
== NULL
)
31991 as_bad (_("unknown architecture extension `%s'\n"), name
);
31993 *input_line_pointer
= saved_char
;
31994 ignore_rest_of_line ();
31997 /* Parse a .fpu directive. */
32000 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32002 const struct arm_option_fpu_value_table
*opt
;
32006 name
= input_line_pointer
;
32007 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32008 input_line_pointer
++;
32009 saved_char
= *input_line_pointer
;
32010 *input_line_pointer
= 0;
32012 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32013 if (streq (opt
->name
, name
))
32015 selected_fpu
= opt
->value
;
32016 #ifndef CPU_DEFAULT
32017 if (no_cpu_selected ())
32018 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32021 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32022 *input_line_pointer
= saved_char
;
32023 demand_empty_rest_of_line ();
32027 as_bad (_("unknown floating point format `%s'\n"), name
);
32028 *input_line_pointer
= saved_char
;
32029 ignore_rest_of_line ();
32032 /* Copy symbol information. */
32035 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32037 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32041 /* Given a symbolic attribute NAME, return the proper integer value.
32042 Returns -1 if the attribute is not known. */
32045 arm_convert_symbolic_attribute (const char *name
)
32047 static const struct
32052 attribute_table
[] =
32054 /* When you modify this table you should
32055 also modify the list in doc/c-arm.texi. */
32056 #define T(tag) {#tag, tag}
32057 T (Tag_CPU_raw_name
),
32060 T (Tag_CPU_arch_profile
),
32061 T (Tag_ARM_ISA_use
),
32062 T (Tag_THUMB_ISA_use
),
32066 T (Tag_Advanced_SIMD_arch
),
32067 T (Tag_PCS_config
),
32068 T (Tag_ABI_PCS_R9_use
),
32069 T (Tag_ABI_PCS_RW_data
),
32070 T (Tag_ABI_PCS_RO_data
),
32071 T (Tag_ABI_PCS_GOT_use
),
32072 T (Tag_ABI_PCS_wchar_t
),
32073 T (Tag_ABI_FP_rounding
),
32074 T (Tag_ABI_FP_denormal
),
32075 T (Tag_ABI_FP_exceptions
),
32076 T (Tag_ABI_FP_user_exceptions
),
32077 T (Tag_ABI_FP_number_model
),
32078 T (Tag_ABI_align_needed
),
32079 T (Tag_ABI_align8_needed
),
32080 T (Tag_ABI_align_preserved
),
32081 T (Tag_ABI_align8_preserved
),
32082 T (Tag_ABI_enum_size
),
32083 T (Tag_ABI_HardFP_use
),
32084 T (Tag_ABI_VFP_args
),
32085 T (Tag_ABI_WMMX_args
),
32086 T (Tag_ABI_optimization_goals
),
32087 T (Tag_ABI_FP_optimization_goals
),
32088 T (Tag_compatibility
),
32089 T (Tag_CPU_unaligned_access
),
32090 T (Tag_FP_HP_extension
),
32091 T (Tag_VFP_HP_extension
),
32092 T (Tag_ABI_FP_16bit_format
),
32093 T (Tag_MPextension_use
),
32095 T (Tag_nodefaults
),
32096 T (Tag_also_compatible_with
),
32097 T (Tag_conformance
),
32099 T (Tag_Virtualization_use
),
32100 T (Tag_DSP_extension
),
32102 /* We deliberately do not include Tag_MPextension_use_legacy. */
32110 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32111 if (streq (name
, attribute_table
[i
].name
))
32112 return attribute_table
[i
].tag
;
32117 /* Apply sym value for relocations only in the case that they are for
32118 local symbols in the same segment as the fixup and you have the
32119 respective architectural feature for blx and simple switches. */
32122 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32125 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32126 /* PR 17444: If the local symbol is in a different section then a reloc
32127 will always be generated for it, so applying the symbol value now
32128 will result in a double offset being stored in the relocation. */
32129 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32130 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32132 switch (fixP
->fx_r_type
)
32134 case BFD_RELOC_ARM_PCREL_BLX
:
32135 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32136 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32140 case BFD_RELOC_ARM_PCREL_CALL
:
32141 case BFD_RELOC_THUMB_PCREL_BLX
:
32142 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32153 #endif /* OBJ_ELF */