1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[16];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2873 end_name
= input_line_pointer
;
2876 if (*input_line_pointer
!= ',')
2879 as_bad (_("expected comma after name \"%s\""), name
);
2881 ignore_rest_of_line ();
2885 input_line_pointer
++;
2888 if (name
[0] == '.' && name
[1] == '\0')
2890 /* XXX - this should not happen to .thumb_set. */
2894 if ((symbolP
= symbol_find (name
)) == NULL
2895 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2898 /* When doing symbol listings, play games with dummy fragments living
2899 outside the normal fragment chain to record the file and line info
2901 if (listing
& LISTING_SYMBOLS
)
2903 extern struct list_info_struct
* listing_tail
;
2904 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2906 memset (dummy_frag
, 0, sizeof (fragS
));
2907 dummy_frag
->fr_type
= rs_fill
;
2908 dummy_frag
->line
= listing_tail
;
2909 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2910 dummy_frag
->fr_symbol
= symbolP
;
2914 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2917 /* "set" symbols are local unless otherwise specified. */
2918 SF_SET_LOCAL (symbolP
);
2919 #endif /* OBJ_COFF */
2920 } /* Make a new symbol. */
2922 symbol_table_insert (symbolP
);
2927 && S_IS_DEFINED (symbolP
)
2928 && S_GET_SEGMENT (symbolP
) != reg_section
)
2929 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2931 pseudo_set (symbolP
);
2933 demand_empty_rest_of_line ();
2935 /* XXX Now we come to the Thumb specific bit of code. */
2937 THUMB_SET_FUNC (symbolP
, 1);
2938 ARM_SET_THUMB (symbolP
, 1);
2939 #if defined OBJ_ELF || defined OBJ_COFF
2940 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2944 /* Directives: Mode selection. */
2946 /* .syntax [unified|divided] - choose the new unified syntax
2947 (same for Arm and Thumb encoding, modulo slight differences in what
2948 can be represented) or the old divergent syntax for each mode. */
2950 s_syntax (int unused ATTRIBUTE_UNUSED
)
2954 name
= input_line_pointer
;
2955 delim
= get_symbol_end ();
2957 if (!strcasecmp (name
, "unified"))
2958 unified_syntax
= TRUE
;
2959 else if (!strcasecmp (name
, "divided"))
2960 unified_syntax
= FALSE
;
2963 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2966 *input_line_pointer
= delim
;
2967 demand_empty_rest_of_line ();
2970 /* Directives: sectioning and alignment. */
2972 /* Same as s_align_ptwo but align 0 => align 2. */
2975 s_align (int unused ATTRIBUTE_UNUSED
)
2980 long max_alignment
= 15;
2982 temp
= get_absolute_expression ();
2983 if (temp
> max_alignment
)
2984 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2987 as_bad (_("alignment negative. 0 assumed."));
2991 if (*input_line_pointer
== ',')
2993 input_line_pointer
++;
2994 temp_fill
= get_absolute_expression ();
3006 /* Only make a frag if we HAVE to. */
3007 if (temp
&& !need_pass_2
)
3009 if (!fill_p
&& subseg_text_p (now_seg
))
3010 frag_align_code (temp
, 0);
3012 frag_align (temp
, (int) temp_fill
, 0);
3014 demand_empty_rest_of_line ();
3016 record_alignment (now_seg
, temp
);
3020 s_bss (int ignore ATTRIBUTE_UNUSED
)
3022 /* We don't support putting frags in the BSS segment, we fake it by
3023 marking in_bss, then looking at s_skip for clues. */
3024 subseg_set (bss_section
, 0);
3025 demand_empty_rest_of_line ();
3027 #ifdef md_elf_section_change_hook
3028 md_elf_section_change_hook ();
3033 s_even (int ignore ATTRIBUTE_UNUSED
)
3035 /* Never make frag if expect extra pass. */
3037 frag_align (1, 0, 0);
3039 record_alignment (now_seg
, 1);
3041 demand_empty_rest_of_line ();
3044 /* Directives: CodeComposer Studio. */
3046 /* .ref (for CodeComposer Studio syntax only). */
3048 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3050 if (codecomposer_syntax
)
3051 ignore_rest_of_line ();
3053 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3056 /* If name is not NULL, then it is used for marking the beginning of a
3057 function, wherease if it is NULL then it means the function end. */
3059 asmfunc_debug (const char * name
)
3061 static const char * last_name
= NULL
;
3065 gas_assert (last_name
== NULL
);
3068 if (debug_type
== DEBUG_STABS
)
3069 stabs_generate_asm_func (name
, name
);
3073 gas_assert (last_name
!= NULL
);
3075 if (debug_type
== DEBUG_STABS
)
3076 stabs_generate_asm_endfunc (last_name
, last_name
);
3083 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3085 if (codecomposer_syntax
)
3087 switch (asmfunc_state
)
3089 case OUTSIDE_ASMFUNC
:
3090 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3093 case WAITING_ASMFUNC_NAME
:
3094 as_bad (_(".asmfunc repeated."));
3097 case WAITING_ENDASMFUNC
:
3098 as_bad (_(".asmfunc without function."));
3101 demand_empty_rest_of_line ();
3104 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3108 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3110 if (codecomposer_syntax
)
3112 switch (asmfunc_state
)
3114 case OUTSIDE_ASMFUNC
:
3115 as_bad (_(".endasmfunc without a .asmfunc."));
3118 case WAITING_ASMFUNC_NAME
:
3119 as_bad (_(".endasmfunc without function."));
3122 case WAITING_ENDASMFUNC
:
3123 asmfunc_state
= OUTSIDE_ASMFUNC
;
3124 asmfunc_debug (NULL
);
3127 demand_empty_rest_of_line ();
3130 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3134 s_ccs_def (int name
)
3136 if (codecomposer_syntax
)
3139 as_bad (_(".def pseudo-op only available with -mccs flag."));
3142 /* Directives: Literal pools. */
3144 static literal_pool
*
3145 find_literal_pool (void)
3147 literal_pool
* pool
;
3149 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3151 if (pool
->section
== now_seg
3152 && pool
->sub_section
== now_subseg
)
3159 static literal_pool
*
3160 find_or_make_literal_pool (void)
3162 /* Next literal pool ID number. */
3163 static unsigned int latest_pool_num
= 1;
3164 literal_pool
* pool
;
3166 pool
= find_literal_pool ();
3170 /* Create a new pool. */
3171 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3175 pool
->next_free_entry
= 0;
3176 pool
->section
= now_seg
;
3177 pool
->sub_section
= now_subseg
;
3178 pool
->next
= list_of_pools
;
3179 pool
->symbol
= NULL
;
3180 pool
->alignment
= 2;
3182 /* Add it to the list. */
3183 list_of_pools
= pool
;
3186 /* New pools, and emptied pools, will have a NULL symbol. */
3187 if (pool
->symbol
== NULL
)
3189 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3190 (valueT
) 0, &zero_address_frag
);
3191 pool
->id
= latest_pool_num
++;
3198 /* Add the literal in the global 'inst'
3199 structure to the relevant literal pool. */
3202 add_to_lit_pool (unsigned int nbytes
)
3204 #define PADDING_SLOT 0x1
3205 #define LIT_ENTRY_SIZE_MASK 0xFF
3206 literal_pool
* pool
;
3207 unsigned int entry
, pool_size
= 0;
3208 bfd_boolean padding_slot_p
= FALSE
;
3214 imm1
= inst
.operands
[1].imm
;
3215 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3216 : inst
.reloc
.exp
.X_unsigned
? 0
3217 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3218 if (target_big_endian
)
3221 imm2
= inst
.operands
[1].imm
;
3225 pool
= find_or_make_literal_pool ();
3227 /* Check if this literal value is already in the pool. */
3228 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3232 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3233 && (inst
.reloc
.exp
.X_op
== O_constant
)
3234 && (pool
->literals
[entry
].X_add_number
3235 == inst
.reloc
.exp
.X_add_number
)
3236 && (pool
->literals
[entry
].X_md
== nbytes
)
3237 && (pool
->literals
[entry
].X_unsigned
3238 == inst
.reloc
.exp
.X_unsigned
))
3241 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3242 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3243 && (pool
->literals
[entry
].X_add_number
3244 == inst
.reloc
.exp
.X_add_number
)
3245 && (pool
->literals
[entry
].X_add_symbol
3246 == inst
.reloc
.exp
.X_add_symbol
)
3247 && (pool
->literals
[entry
].X_op_symbol
3248 == inst
.reloc
.exp
.X_op_symbol
)
3249 && (pool
->literals
[entry
].X_md
== nbytes
))
3252 else if ((nbytes
== 8)
3253 && !(pool_size
& 0x7)
3254 && ((entry
+ 1) != pool
->next_free_entry
)
3255 && (pool
->literals
[entry
].X_op
== O_constant
)
3256 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3257 && (pool
->literals
[entry
].X_unsigned
3258 == inst
.reloc
.exp
.X_unsigned
)
3259 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3260 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3261 && (pool
->literals
[entry
+ 1].X_unsigned
3262 == inst
.reloc
.exp
.X_unsigned
))
3265 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3266 if (padding_slot_p
&& (nbytes
== 4))
3272 /* Do we need to create a new entry? */
3273 if (entry
== pool
->next_free_entry
)
3275 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3277 inst
.error
= _("literal pool overflow");
3283 /* For 8-byte entries, we align to an 8-byte boundary,
3284 and split it into two 4-byte entries, because on 32-bit
3285 host, 8-byte constants are treated as big num, thus
3286 saved in "generic_bignum" which will be overwritten
3287 by later assignments.
3289 We also need to make sure there is enough space for
3292 We also check to make sure the literal operand is a
3294 if (!(inst
.reloc
.exp
.X_op
== O_constant
3295 || inst
.reloc
.exp
.X_op
== O_big
))
3297 inst
.error
= _("invalid type for literal pool");
3300 else if (pool_size
& 0x7)
3302 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3304 inst
.error
= _("literal pool overflow");
3308 pool
->literals
[entry
] = inst
.reloc
.exp
;
3309 pool
->literals
[entry
].X_add_number
= 0;
3310 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3311 pool
->next_free_entry
+= 1;
3314 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3316 inst
.error
= _("literal pool overflow");
3320 pool
->literals
[entry
] = inst
.reloc
.exp
;
3321 pool
->literals
[entry
].X_op
= O_constant
;
3322 pool
->literals
[entry
].X_add_number
= imm1
;
3323 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3324 pool
->literals
[entry
++].X_md
= 4;
3325 pool
->literals
[entry
] = inst
.reloc
.exp
;
3326 pool
->literals
[entry
].X_op
= O_constant
;
3327 pool
->literals
[entry
].X_add_number
= imm2
;
3328 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3329 pool
->literals
[entry
].X_md
= 4;
3330 pool
->alignment
= 3;
3331 pool
->next_free_entry
+= 1;
3335 pool
->literals
[entry
] = inst
.reloc
.exp
;
3336 pool
->literals
[entry
].X_md
= 4;
3340 /* PR ld/12974: Record the location of the first source line to reference
3341 this entry in the literal pool. If it turns out during linking that the
3342 symbol does not exist we will be able to give an accurate line number for
3343 the (first use of the) missing reference. */
3344 if (debug_type
== DEBUG_DWARF2
)
3345 dwarf2_where (pool
->locs
+ entry
);
3347 pool
->next_free_entry
+= 1;
3349 else if (padding_slot_p
)
3351 pool
->literals
[entry
] = inst
.reloc
.exp
;
3352 pool
->literals
[entry
].X_md
= nbytes
;
3355 inst
.reloc
.exp
.X_op
= O_symbol
;
3356 inst
.reloc
.exp
.X_add_number
= pool_size
;
3357 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3363 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3365 bfd_boolean ret
= TRUE
;
3367 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3369 const char *label
= rest
;
3371 while (!is_end_of_line
[(int) label
[-1]])
3376 as_bad (_("Invalid label '%s'"), label
);
3380 asmfunc_debug (label
);
3382 asmfunc_state
= WAITING_ENDASMFUNC
;
3388 /* Can't use symbol_new here, so have to create a symbol and then at
3389 a later date assign it a value. Thats what these functions do. */
3392 symbol_locate (symbolS
* symbolP
,
3393 const char * name
, /* It is copied, the caller can modify. */
3394 segT segment
, /* Segment identifier (SEG_<something>). */
3395 valueT valu
, /* Symbol value. */
3396 fragS
* frag
) /* Associated fragment. */
3399 char * preserved_copy_of_name
;
3401 name_length
= strlen (name
) + 1; /* +1 for \0. */
3402 obstack_grow (¬es
, name
, name_length
);
3403 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3405 #ifdef tc_canonicalize_symbol_name
3406 preserved_copy_of_name
=
3407 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3410 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3412 S_SET_SEGMENT (symbolP
, segment
);
3413 S_SET_VALUE (symbolP
, valu
);
3414 symbol_clear_list_pointers (symbolP
);
3416 symbol_set_frag (symbolP
, frag
);
3418 /* Link to end of symbol chain. */
3420 extern int symbol_table_frozen
;
3422 if (symbol_table_frozen
)
3426 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3428 obj_symbol_new_hook (symbolP
);
3430 #ifdef tc_symbol_new_hook
3431 tc_symbol_new_hook (symbolP
);
3435 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3436 #endif /* DEBUG_SYMS */
3440 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3443 literal_pool
* pool
;
3446 pool
= find_literal_pool ();
3448 || pool
->symbol
== NULL
3449 || pool
->next_free_entry
== 0)
3452 /* Align pool as you have word accesses.
3453 Only make a frag if we have to. */
3455 frag_align (pool
->alignment
, 0, 0);
3457 record_alignment (now_seg
, 2);
3460 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3461 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3463 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3465 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3466 (valueT
) frag_now_fix (), frag_now
);
3467 symbol_table_insert (pool
->symbol
);
3469 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3471 #if defined OBJ_COFF || defined OBJ_ELF
3472 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3475 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3478 if (debug_type
== DEBUG_DWARF2
)
3479 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3481 /* First output the expression in the instruction to the pool. */
3482 emit_expr (&(pool
->literals
[entry
]),
3483 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3486 /* Mark the pool as empty. */
3487 pool
->next_free_entry
= 0;
3488 pool
->symbol
= NULL
;
3492 /* Forward declarations for functions below, in the MD interface
3494 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3495 static valueT
create_unwind_entry (int);
3496 static void start_unwind_section (const segT
, int);
3497 static void add_unwind_opcode (valueT
, int);
3498 static void flush_pending_unwind (void);
3500 /* Directives: Data. */
3503 s_arm_elf_cons (int nbytes
)
3507 #ifdef md_flush_pending_output
3508 md_flush_pending_output ();
3511 if (is_it_end_of_statement ())
3513 demand_empty_rest_of_line ();
3517 #ifdef md_cons_align
3518 md_cons_align (nbytes
);
3521 mapping_state (MAP_DATA
);
3525 char *base
= input_line_pointer
;
3529 if (exp
.X_op
!= O_symbol
)
3530 emit_expr (&exp
, (unsigned int) nbytes
);
3533 char *before_reloc
= input_line_pointer
;
3534 reloc
= parse_reloc (&input_line_pointer
);
3537 as_bad (_("unrecognized relocation suffix"));
3538 ignore_rest_of_line ();
3541 else if (reloc
== BFD_RELOC_UNUSED
)
3542 emit_expr (&exp
, (unsigned int) nbytes
);
3545 reloc_howto_type
*howto
= (reloc_howto_type
*)
3546 bfd_reloc_type_lookup (stdoutput
,
3547 (bfd_reloc_code_real_type
) reloc
);
3548 int size
= bfd_get_reloc_size (howto
);
3550 if (reloc
== BFD_RELOC_ARM_PLT32
)
3552 as_bad (_("(plt) is only valid on branch targets"));
3553 reloc
= BFD_RELOC_UNUSED
;
3558 as_bad (_("%s relocations do not fit in %d bytes"),
3559 howto
->name
, nbytes
);
3562 /* We've parsed an expression stopping at O_symbol.
3563 But there may be more expression left now that we
3564 have parsed the relocation marker. Parse it again.
3565 XXX Surely there is a cleaner way to do this. */
3566 char *p
= input_line_pointer
;
3568 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3569 memcpy (save_buf
, base
, input_line_pointer
- base
);
3570 memmove (base
+ (input_line_pointer
- before_reloc
),
3571 base
, before_reloc
- base
);
3573 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3575 memcpy (base
, save_buf
, p
- base
);
3577 offset
= nbytes
- size
;
3578 p
= frag_more (nbytes
);
3579 memset (p
, 0, nbytes
);
3580 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3581 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3586 while (*input_line_pointer
++ == ',');
3588 /* Put terminator back into stream. */
3589 input_line_pointer
--;
3590 demand_empty_rest_of_line ();
3593 /* Emit an expression containing a 32-bit thumb instruction.
3594 Implementation based on put_thumb32_insn. */
3597 emit_thumb32_expr (expressionS
* exp
)
3599 expressionS exp_high
= *exp
;
3601 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3602 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3603 exp
->X_add_number
&= 0xffff;
3604 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3607 /* Guess the instruction size based on the opcode. */
3610 thumb_insn_size (int opcode
)
3612 if ((unsigned int) opcode
< 0xe800u
)
3614 else if ((unsigned int) opcode
>= 0xe8000000u
)
3621 emit_insn (expressionS
*exp
, int nbytes
)
3625 if (exp
->X_op
== O_constant
)
3630 size
= thumb_insn_size (exp
->X_add_number
);
3634 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3636 as_bad (_(".inst.n operand too big. "\
3637 "Use .inst.w instead"));
3642 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3643 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3645 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3647 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3648 emit_thumb32_expr (exp
);
3650 emit_expr (exp
, (unsigned int) size
);
3652 it_fsm_post_encode ();
3656 as_bad (_("cannot determine Thumb instruction size. " \
3657 "Use .inst.n/.inst.w instead"));
3660 as_bad (_("constant expression required"));
3665 /* Like s_arm_elf_cons but do not use md_cons_align and
3666 set the mapping state to MAP_ARM/MAP_THUMB. */
3669 s_arm_elf_inst (int nbytes
)
3671 if (is_it_end_of_statement ())
3673 demand_empty_rest_of_line ();
3677 /* Calling mapping_state () here will not change ARM/THUMB,
3678 but will ensure not to be in DATA state. */
3681 mapping_state (MAP_THUMB
);
3686 as_bad (_("width suffixes are invalid in ARM mode"));
3687 ignore_rest_of_line ();
3693 mapping_state (MAP_ARM
);
3702 if (! emit_insn (& exp
, nbytes
))
3704 ignore_rest_of_line ();
3708 while (*input_line_pointer
++ == ',');
3710 /* Put terminator back into stream. */
3711 input_line_pointer
--;
3712 demand_empty_rest_of_line ();
3715 /* Parse a .rel31 directive. */
3718 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3725 if (*input_line_pointer
== '1')
3726 highbit
= 0x80000000;
3727 else if (*input_line_pointer
!= '0')
3728 as_bad (_("expected 0 or 1"));
3730 input_line_pointer
++;
3731 if (*input_line_pointer
!= ',')
3732 as_bad (_("missing comma"));
3733 input_line_pointer
++;
3735 #ifdef md_flush_pending_output
3736 md_flush_pending_output ();
3739 #ifdef md_cons_align
3743 mapping_state (MAP_DATA
);
3748 md_number_to_chars (p
, highbit
, 4);
3749 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3750 BFD_RELOC_ARM_PREL31
);
3752 demand_empty_rest_of_line ();
3755 /* Directives: AEABI stack-unwind tables. */
3757 /* Parse an unwind_fnstart directive. Simply records the current location. */
3760 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3762 demand_empty_rest_of_line ();
3763 if (unwind
.proc_start
)
3765 as_bad (_("duplicate .fnstart directive"));
3769 /* Mark the start of the function. */
3770 unwind
.proc_start
= expr_build_dot ();
3772 /* Reset the rest of the unwind info. */
3773 unwind
.opcode_count
= 0;
3774 unwind
.table_entry
= NULL
;
3775 unwind
.personality_routine
= NULL
;
3776 unwind
.personality_index
= -1;
3777 unwind
.frame_size
= 0;
3778 unwind
.fp_offset
= 0;
3779 unwind
.fp_reg
= REG_SP
;
3781 unwind
.sp_restored
= 0;
3785 /* Parse a handlerdata directive. Creates the exception handling table entry
3786 for the function. */
3789 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3791 demand_empty_rest_of_line ();
3792 if (!unwind
.proc_start
)
3793 as_bad (MISSING_FNSTART
);
3795 if (unwind
.table_entry
)
3796 as_bad (_("duplicate .handlerdata directive"));
3798 create_unwind_entry (1);
3801 /* Parse an unwind_fnend directive. Generates the index table entry. */
3804 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3809 unsigned int marked_pr_dependency
;
3811 demand_empty_rest_of_line ();
3813 if (!unwind
.proc_start
)
3815 as_bad (_(".fnend directive without .fnstart"));
3819 /* Add eh table entry. */
3820 if (unwind
.table_entry
== NULL
)
3821 val
= create_unwind_entry (0);
3825 /* Add index table entry. This is two words. */
3826 start_unwind_section (unwind
.saved_seg
, 1);
3827 frag_align (2, 0, 0);
3828 record_alignment (now_seg
, 2);
3830 ptr
= frag_more (8);
3832 where
= frag_now_fix () - 8;
3834 /* Self relative offset of the function start. */
3835 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3836 BFD_RELOC_ARM_PREL31
);
3838 /* Indicate dependency on EHABI-defined personality routines to the
3839 linker, if it hasn't been done already. */
3840 marked_pr_dependency
3841 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3842 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3843 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3845 static const char *const name
[] =
3847 "__aeabi_unwind_cpp_pr0",
3848 "__aeabi_unwind_cpp_pr1",
3849 "__aeabi_unwind_cpp_pr2"
3851 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3852 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3853 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3854 |= 1 << unwind
.personality_index
;
3858 /* Inline exception table entry. */
3859 md_number_to_chars (ptr
+ 4, val
, 4);
3861 /* Self relative offset of the table entry. */
3862 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3863 BFD_RELOC_ARM_PREL31
);
3865 /* Restore the original section. */
3866 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3868 unwind
.proc_start
= NULL
;
3872 /* Parse an unwind_cantunwind directive. */
3875 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3877 demand_empty_rest_of_line ();
3878 if (!unwind
.proc_start
)
3879 as_bad (MISSING_FNSTART
);
3881 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3882 as_bad (_("personality routine specified for cantunwind frame"));
3884 unwind
.personality_index
= -2;
3888 /* Parse a personalityindex directive. */
3891 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3895 if (!unwind
.proc_start
)
3896 as_bad (MISSING_FNSTART
);
3898 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3899 as_bad (_("duplicate .personalityindex directive"));
3903 if (exp
.X_op
!= O_constant
3904 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3906 as_bad (_("bad personality routine number"));
3907 ignore_rest_of_line ();
3911 unwind
.personality_index
= exp
.X_add_number
;
3913 demand_empty_rest_of_line ();
3917 /* Parse a personality directive. */
3920 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3924 if (!unwind
.proc_start
)
3925 as_bad (MISSING_FNSTART
);
3927 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3928 as_bad (_("duplicate .personality directive"));
3930 name
= input_line_pointer
;
3931 c
= get_symbol_end ();
3932 p
= input_line_pointer
;
3933 unwind
.personality_routine
= symbol_find_or_make (name
);
3935 demand_empty_rest_of_line ();
3939 /* Parse a directive saving core registers. */
3942 s_arm_unwind_save_core (void)
3948 range
= parse_reg_list (&input_line_pointer
);
3951 as_bad (_("expected register list"));
3952 ignore_rest_of_line ();
3956 demand_empty_rest_of_line ();
3958 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3959 into .unwind_save {..., sp...}. We aren't bothered about the value of
3960 ip because it is clobbered by calls. */
3961 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3962 && (range
& 0x3000) == 0x1000)
3964 unwind
.opcode_count
--;
3965 unwind
.sp_restored
= 0;
3966 range
= (range
| 0x2000) & ~0x1000;
3967 unwind
.pending_offset
= 0;
3973 /* See if we can use the short opcodes. These pop a block of up to 8
3974 registers starting with r4, plus maybe r14. */
3975 for (n
= 0; n
< 8; n
++)
3977 /* Break at the first non-saved register. */
3978 if ((range
& (1 << (n
+ 4))) == 0)
3981 /* See if there are any other bits set. */
3982 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3984 /* Use the long form. */
3985 op
= 0x8000 | ((range
>> 4) & 0xfff);
3986 add_unwind_opcode (op
, 2);
3990 /* Use the short form. */
3992 op
= 0xa8; /* Pop r14. */
3994 op
= 0xa0; /* Do not pop r14. */
3996 add_unwind_opcode (op
, 1);
4003 op
= 0xb100 | (range
& 0xf);
4004 add_unwind_opcode (op
, 2);
4007 /* Record the number of bytes pushed. */
4008 for (n
= 0; n
< 16; n
++)
4010 if (range
& (1 << n
))
4011 unwind
.frame_size
+= 4;
4016 /* Parse a directive saving FPA registers. */
4019 s_arm_unwind_save_fpa (int reg
)
4025 /* Get Number of registers to transfer. */
4026 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4029 exp
.X_op
= O_illegal
;
4031 if (exp
.X_op
!= O_constant
)
4033 as_bad (_("expected , <constant>"));
4034 ignore_rest_of_line ();
4038 num_regs
= exp
.X_add_number
;
4040 if (num_regs
< 1 || num_regs
> 4)
4042 as_bad (_("number of registers must be in the range [1:4]"));
4043 ignore_rest_of_line ();
4047 demand_empty_rest_of_line ();
4052 op
= 0xb4 | (num_regs
- 1);
4053 add_unwind_opcode (op
, 1);
4058 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4059 add_unwind_opcode (op
, 2);
4061 unwind
.frame_size
+= num_regs
* 12;
4065 /* Parse a directive saving VFP registers for ARMv6 and above. */
4068 s_arm_unwind_save_vfp_armv6 (void)
4073 int num_vfpv3_regs
= 0;
4074 int num_regs_below_16
;
4076 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4086 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4087 than FSTMX/FLDMX-style ones). */
4089 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4091 num_vfpv3_regs
= count
;
4092 else if (start
+ count
> 16)
4093 num_vfpv3_regs
= start
+ count
- 16;
4095 if (num_vfpv3_regs
> 0)
4097 int start_offset
= start
> 16 ? start
- 16 : 0;
4098 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4099 add_unwind_opcode (op
, 2);
4102 /* Generate opcode for registers numbered in the range 0 .. 15. */
4103 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4104 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4105 if (num_regs_below_16
> 0)
4107 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4108 add_unwind_opcode (op
, 2);
4111 unwind
.frame_size
+= count
* 8;
4115 /* Parse a directive saving VFP registers for pre-ARMv6. */
4118 s_arm_unwind_save_vfp (void)
4124 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4127 as_bad (_("expected register list"));
4128 ignore_rest_of_line ();
4132 demand_empty_rest_of_line ();
4137 op
= 0xb8 | (count
- 1);
4138 add_unwind_opcode (op
, 1);
4143 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4144 add_unwind_opcode (op
, 2);
4146 unwind
.frame_size
+= count
* 8 + 4;
4150 /* Parse a directive saving iWMMXt data registers. */
4153 s_arm_unwind_save_mmxwr (void)
4161 if (*input_line_pointer
== '{')
4162 input_line_pointer
++;
4166 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4170 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4175 as_tsktsk (_("register list not in ascending order"));
4178 if (*input_line_pointer
== '-')
4180 input_line_pointer
++;
4181 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4184 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4187 else if (reg
>= hi_reg
)
4189 as_bad (_("bad register range"));
4192 for (; reg
< hi_reg
; reg
++)
4196 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4198 skip_past_char (&input_line_pointer
, '}');
4200 demand_empty_rest_of_line ();
4202 /* Generate any deferred opcodes because we're going to be looking at
4204 flush_pending_unwind ();
4206 for (i
= 0; i
< 16; i
++)
4208 if (mask
& (1 << i
))
4209 unwind
.frame_size
+= 8;
4212 /* Attempt to combine with a previous opcode. We do this because gcc
4213 likes to output separate unwind directives for a single block of
4215 if (unwind
.opcode_count
> 0)
4217 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4218 if ((i
& 0xf8) == 0xc0)
4221 /* Only merge if the blocks are contiguous. */
4224 if ((mask
& 0xfe00) == (1 << 9))
4226 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4227 unwind
.opcode_count
--;
4230 else if (i
== 6 && unwind
.opcode_count
>= 2)
4232 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4236 op
= 0xffff << (reg
- 1);
4238 && ((mask
& op
) == (1u << (reg
- 1))))
4240 op
= (1 << (reg
+ i
+ 1)) - 1;
4241 op
&= ~((1 << reg
) - 1);
4243 unwind
.opcode_count
-= 2;
4250 /* We want to generate opcodes in the order the registers have been
4251 saved, ie. descending order. */
4252 for (reg
= 15; reg
>= -1; reg
--)
4254 /* Save registers in blocks. */
4256 || !(mask
& (1 << reg
)))
4258 /* We found an unsaved reg. Generate opcodes to save the
4265 op
= 0xc0 | (hi_reg
- 10);
4266 add_unwind_opcode (op
, 1);
4271 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4272 add_unwind_opcode (op
, 2);
4281 ignore_rest_of_line ();
4285 s_arm_unwind_save_mmxwcg (void)
4292 if (*input_line_pointer
== '{')
4293 input_line_pointer
++;
4295 skip_whitespace (input_line_pointer
);
4299 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4303 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4309 as_tsktsk (_("register list not in ascending order"));
4312 if (*input_line_pointer
== '-')
4314 input_line_pointer
++;
4315 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4318 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4321 else if (reg
>= hi_reg
)
4323 as_bad (_("bad register range"));
4326 for (; reg
< hi_reg
; reg
++)
4330 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4332 skip_past_char (&input_line_pointer
, '}');
4334 demand_empty_rest_of_line ();
4336 /* Generate any deferred opcodes because we're going to be looking at
4338 flush_pending_unwind ();
4340 for (reg
= 0; reg
< 16; reg
++)
4342 if (mask
& (1 << reg
))
4343 unwind
.frame_size
+= 4;
4346 add_unwind_opcode (op
, 2);
4349 ignore_rest_of_line ();
4353 /* Parse an unwind_save directive.
4354 If the argument is non-zero, this is a .vsave directive. */
4357 s_arm_unwind_save (int arch_v6
)
4360 struct reg_entry
*reg
;
4361 bfd_boolean had_brace
= FALSE
;
4363 if (!unwind
.proc_start
)
4364 as_bad (MISSING_FNSTART
);
4366 /* Figure out what sort of save we have. */
4367 peek
= input_line_pointer
;
4375 reg
= arm_reg_parse_multi (&peek
);
4379 as_bad (_("register expected"));
4380 ignore_rest_of_line ();
4389 as_bad (_("FPA .unwind_save does not take a register list"));
4390 ignore_rest_of_line ();
4393 input_line_pointer
= peek
;
4394 s_arm_unwind_save_fpa (reg
->number
);
4398 s_arm_unwind_save_core ();
4403 s_arm_unwind_save_vfp_armv6 ();
4405 s_arm_unwind_save_vfp ();
4408 case REG_TYPE_MMXWR
:
4409 s_arm_unwind_save_mmxwr ();
4412 case REG_TYPE_MMXWCG
:
4413 s_arm_unwind_save_mmxwcg ();
4417 as_bad (_(".unwind_save does not support this kind of register"));
4418 ignore_rest_of_line ();
4423 /* Parse an unwind_movsp directive. */
4426 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4438 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4439 ignore_rest_of_line ();
4443 /* Optional constant. */
4444 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4446 if (immediate_for_directive (&offset
) == FAIL
)
4452 demand_empty_rest_of_line ();
4454 if (reg
== REG_SP
|| reg
== REG_PC
)
4456 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4460 if (unwind
.fp_reg
!= REG_SP
)
4461 as_bad (_("unexpected .unwind_movsp directive"));
4463 /* Generate opcode to restore the value. */
4465 add_unwind_opcode (op
, 1);
4467 /* Record the information for later. */
4468 unwind
.fp_reg
= reg
;
4469 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4470 unwind
.sp_restored
= 1;
4473 /* Parse an unwind_pad directive. */
4476 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4480 if (!unwind
.proc_start
)
4481 as_bad (MISSING_FNSTART
);
4483 if (immediate_for_directive (&offset
) == FAIL
)
4488 as_bad (_("stack increment must be multiple of 4"));
4489 ignore_rest_of_line ();
4493 /* Don't generate any opcodes, just record the details for later. */
4494 unwind
.frame_size
+= offset
;
4495 unwind
.pending_offset
+= offset
;
4497 demand_empty_rest_of_line ();
4500 /* Parse an unwind_setfp directive. */
4503 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4509 if (!unwind
.proc_start
)
4510 as_bad (MISSING_FNSTART
);
4512 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4513 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4516 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4518 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4520 as_bad (_("expected <reg>, <reg>"));
4521 ignore_rest_of_line ();
4525 /* Optional constant. */
4526 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4528 if (immediate_for_directive (&offset
) == FAIL
)
4534 demand_empty_rest_of_line ();
4536 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4538 as_bad (_("register must be either sp or set by a previous"
4539 "unwind_movsp directive"));
4543 /* Don't generate any opcodes, just record the information for later. */
4544 unwind
.fp_reg
= fp_reg
;
4546 if (sp_reg
== REG_SP
)
4547 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4549 unwind
.fp_offset
-= offset
;
4552 /* Parse an unwind_raw directive. */
4555 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4558 /* This is an arbitrary limit. */
4559 unsigned char op
[16];
4562 if (!unwind
.proc_start
)
4563 as_bad (MISSING_FNSTART
);
4566 if (exp
.X_op
== O_constant
4567 && skip_past_comma (&input_line_pointer
) != FAIL
)
4569 unwind
.frame_size
+= exp
.X_add_number
;
4573 exp
.X_op
= O_illegal
;
4575 if (exp
.X_op
!= O_constant
)
4577 as_bad (_("expected <offset>, <opcode>"));
4578 ignore_rest_of_line ();
4584 /* Parse the opcode. */
4589 as_bad (_("unwind opcode too long"));
4590 ignore_rest_of_line ();
4592 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4594 as_bad (_("invalid unwind opcode"));
4595 ignore_rest_of_line ();
4598 op
[count
++] = exp
.X_add_number
;
4600 /* Parse the next byte. */
4601 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4607 /* Add the opcode bytes in reverse order. */
4609 add_unwind_opcode (op
[count
], 1);
4611 demand_empty_rest_of_line ();
4615 /* Parse a .eabi_attribute directive. */
4618 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4620 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4622 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4623 attributes_set_explicitly
[tag
] = 1;
4626 /* Emit a tls fix for the symbol. */
4629 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4633 #ifdef md_flush_pending_output
4634 md_flush_pending_output ();
4637 #ifdef md_cons_align
4641 /* Since we're just labelling the code, there's no need to define a
4644 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4645 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4646 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4647 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4649 #endif /* OBJ_ELF */
4651 static void s_arm_arch (int);
4652 static void s_arm_object_arch (int);
4653 static void s_arm_cpu (int);
4654 static void s_arm_fpu (int);
4655 static void s_arm_arch_extension (int);
4660 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4667 if (exp
.X_op
== O_symbol
)
4668 exp
.X_op
= O_secrel
;
4670 emit_expr (&exp
, 4);
4672 while (*input_line_pointer
++ == ',');
4674 input_line_pointer
--;
4675 demand_empty_rest_of_line ();
4679 /* This table describes all the machine specific pseudo-ops the assembler
4680 has to support. The fields are:
4681 pseudo-op name without dot
4682 function to call to execute this pseudo-op
4683 Integer arg to pass to the function. */
4685 const pseudo_typeS md_pseudo_table
[] =
4687 /* Never called because '.req' does not start a line. */
4688 { "req", s_req
, 0 },
4689 /* Following two are likewise never called. */
4692 { "unreq", s_unreq
, 0 },
4693 { "bss", s_bss
, 0 },
4694 { "align", s_align
, 0 },
4695 { "arm", s_arm
, 0 },
4696 { "thumb", s_thumb
, 0 },
4697 { "code", s_code
, 0 },
4698 { "force_thumb", s_force_thumb
, 0 },
4699 { "thumb_func", s_thumb_func
, 0 },
4700 { "thumb_set", s_thumb_set
, 0 },
4701 { "even", s_even
, 0 },
4702 { "ltorg", s_ltorg
, 0 },
4703 { "pool", s_ltorg
, 0 },
4704 { "syntax", s_syntax
, 0 },
4705 { "cpu", s_arm_cpu
, 0 },
4706 { "arch", s_arm_arch
, 0 },
4707 { "object_arch", s_arm_object_arch
, 0 },
4708 { "fpu", s_arm_fpu
, 0 },
4709 { "arch_extension", s_arm_arch_extension
, 0 },
4711 { "word", s_arm_elf_cons
, 4 },
4712 { "long", s_arm_elf_cons
, 4 },
4713 { "inst.n", s_arm_elf_inst
, 2 },
4714 { "inst.w", s_arm_elf_inst
, 4 },
4715 { "inst", s_arm_elf_inst
, 0 },
4716 { "rel31", s_arm_rel31
, 0 },
4717 { "fnstart", s_arm_unwind_fnstart
, 0 },
4718 { "fnend", s_arm_unwind_fnend
, 0 },
4719 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4720 { "personality", s_arm_unwind_personality
, 0 },
4721 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4722 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4723 { "save", s_arm_unwind_save
, 0 },
4724 { "vsave", s_arm_unwind_save
, 1 },
4725 { "movsp", s_arm_unwind_movsp
, 0 },
4726 { "pad", s_arm_unwind_pad
, 0 },
4727 { "setfp", s_arm_unwind_setfp
, 0 },
4728 { "unwind_raw", s_arm_unwind_raw
, 0 },
4729 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4730 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4734 /* These are used for dwarf. */
4738 /* These are used for dwarf2. */
4739 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4740 { "loc", dwarf2_directive_loc
, 0 },
4741 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4743 { "extend", float_cons
, 'x' },
4744 { "ldouble", float_cons
, 'x' },
4745 { "packed", float_cons
, 'p' },
4747 {"secrel32", pe_directive_secrel
, 0},
4750 /* These are for compatibility with CodeComposer Studio. */
4751 {"ref", s_ccs_ref
, 0},
4752 {"def", s_ccs_def
, 0},
4753 {"asmfunc", s_ccs_asmfunc
, 0},
4754 {"endasmfunc", s_ccs_endasmfunc
, 0},
4759 /* Parser functions used exclusively in instruction operands. */
4761 /* Generic immediate-value read function for use in insn parsing.
4762 STR points to the beginning of the immediate (the leading #);
4763 VAL receives the value; if the value is outside [MIN, MAX]
4764 issue an error. PREFIX_OPT is true if the immediate prefix is
4768 parse_immediate (char **str
, int *val
, int min
, int max
,
4769 bfd_boolean prefix_opt
)
4772 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4773 if (exp
.X_op
!= O_constant
)
4775 inst
.error
= _("constant expression required");
4779 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4781 inst
.error
= _("immediate value out of range");
4785 *val
= exp
.X_add_number
;
4789 /* Less-generic immediate-value read function with the possibility of loading a
4790 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4791 instructions. Puts the result directly in inst.operands[i]. */
4794 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4795 bfd_boolean allow_symbol_p
)
4798 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4801 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4803 if (exp_p
->X_op
== O_constant
)
4805 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4806 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4807 O_constant. We have to be careful not to break compilation for
4808 32-bit X_add_number, though. */
4809 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4811 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4812 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4814 inst
.operands
[i
].regisimm
= 1;
4817 else if (exp_p
->X_op
== O_big
4818 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4820 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4822 /* Bignums have their least significant bits in
4823 generic_bignum[0]. Make sure we put 32 bits in imm and
4824 32 bits in reg, in a (hopefully) portable way. */
4825 gas_assert (parts
!= 0);
4827 /* Make sure that the number is not too big.
4828 PR 11972: Bignums can now be sign-extended to the
4829 size of a .octa so check that the out of range bits
4830 are all zero or all one. */
4831 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4833 LITTLENUM_TYPE m
= -1;
4835 if (generic_bignum
[parts
* 2] != 0
4836 && generic_bignum
[parts
* 2] != m
)
4839 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4840 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4844 inst
.operands
[i
].imm
= 0;
4845 for (j
= 0; j
< parts
; j
++, idx
++)
4846 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4847 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4848 inst
.operands
[i
].reg
= 0;
4849 for (j
= 0; j
< parts
; j
++, idx
++)
4850 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4851 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4852 inst
.operands
[i
].regisimm
= 1;
4854 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4862 /* Returns the pseudo-register number of an FPA immediate constant,
4863 or FAIL if there isn't a valid constant here. */
4866 parse_fpa_immediate (char ** str
)
4868 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4874 /* First try and match exact strings, this is to guarantee
4875 that some formats will work even for cross assembly. */
4877 for (i
= 0; fp_const
[i
]; i
++)
4879 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4883 *str
+= strlen (fp_const
[i
]);
4884 if (is_end_of_line
[(unsigned char) **str
])
4890 /* Just because we didn't get a match doesn't mean that the constant
4891 isn't valid, just that it is in a format that we don't
4892 automatically recognize. Try parsing it with the standard
4893 expression routines. */
4895 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4897 /* Look for a raw floating point number. */
4898 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4899 && is_end_of_line
[(unsigned char) *save_in
])
4901 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4903 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4905 if (words
[j
] != fp_values
[i
][j
])
4909 if (j
== MAX_LITTLENUMS
)
4917 /* Try and parse a more complex expression, this will probably fail
4918 unless the code uses a floating point prefix (eg "0f"). */
4919 save_in
= input_line_pointer
;
4920 input_line_pointer
= *str
;
4921 if (expression (&exp
) == absolute_section
4922 && exp
.X_op
== O_big
4923 && exp
.X_add_number
< 0)
4925 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4927 #define X_PRECISION 5
4928 #define E_PRECISION 15L
4929 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4931 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4933 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4935 if (words
[j
] != fp_values
[i
][j
])
4939 if (j
== MAX_LITTLENUMS
)
4941 *str
= input_line_pointer
;
4942 input_line_pointer
= save_in
;
4949 *str
= input_line_pointer
;
4950 input_line_pointer
= save_in
;
4951 inst
.error
= _("invalid FPA immediate expression");
4955 /* Returns 1 if a number has "quarter-precision" float format
4956 0baBbbbbbc defgh000 00000000 00000000. */
4959 is_quarter_float (unsigned imm
)
4961 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4962 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4966 /* Detect the presence of a floating point or integer zero constant,
4970 parse_ifimm_zero (char **in
)
4974 if (!is_immediate_prefix (**in
))
4979 /* Accept #0x0 as a synonym for #0. */
4980 if (strncmp (*in
, "0x", 2) == 0)
4983 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4988 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4989 &generic_floating_point_number
);
4992 && generic_floating_point_number
.sign
== '+'
4993 && (generic_floating_point_number
.low
4994 > generic_floating_point_number
.leader
))
5000 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5001 0baBbbbbbc defgh000 00000000 00000000.
5002 The zero and minus-zero cases need special handling, since they can't be
5003 encoded in the "quarter-precision" float format, but can nonetheless be
5004 loaded as integer constants. */
5007 parse_qfloat_immediate (char **ccp
, int *immed
)
5011 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5012 int found_fpchar
= 0;
5014 skip_past_char (&str
, '#');
5016 /* We must not accidentally parse an integer as a floating-point number. Make
5017 sure that the value we parse is not an integer by checking for special
5018 characters '.' or 'e'.
5019 FIXME: This is a horrible hack, but doing better is tricky because type
5020 information isn't in a very usable state at parse time. */
5022 skip_whitespace (fpnum
);
5024 if (strncmp (fpnum
, "0x", 2) == 0)
5028 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5029 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5039 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5041 unsigned fpword
= 0;
5044 /* Our FP word must be 32 bits (single-precision FP). */
5045 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5047 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5051 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5064 /* Shift operands. */
5067 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5070 struct asm_shift_name
5073 enum shift_kind kind
;
5076 /* Third argument to parse_shift. */
5077 enum parse_shift_mode
5079 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5080 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5081 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5082 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5083 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5086 /* Parse a <shift> specifier on an ARM data processing instruction.
5087 This has three forms:
5089 (LSL|LSR|ASL|ASR|ROR) Rs
5090 (LSL|LSR|ASL|ASR|ROR) #imm
5093 Note that ASL is assimilated to LSL in the instruction encoding, and
5094 RRX to ROR #0 (which cannot be written as such). */
5097 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5099 const struct asm_shift_name
*shift_name
;
5100 enum shift_kind shift
;
5105 for (p
= *str
; ISALPHA (*p
); p
++)
5110 inst
.error
= _("shift expression expected");
5114 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5117 if (shift_name
== NULL
)
5119 inst
.error
= _("shift expression expected");
5123 shift
= shift_name
->kind
;
5127 case NO_SHIFT_RESTRICT
:
5128 case SHIFT_IMMEDIATE
: break;
5130 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5131 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5133 inst
.error
= _("'LSL' or 'ASR' required");
5138 case SHIFT_LSL_IMMEDIATE
:
5139 if (shift
!= SHIFT_LSL
)
5141 inst
.error
= _("'LSL' required");
5146 case SHIFT_ASR_IMMEDIATE
:
5147 if (shift
!= SHIFT_ASR
)
5149 inst
.error
= _("'ASR' required");
5157 if (shift
!= SHIFT_RRX
)
5159 /* Whitespace can appear here if the next thing is a bare digit. */
5160 skip_whitespace (p
);
5162 if (mode
== NO_SHIFT_RESTRICT
5163 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5165 inst
.operands
[i
].imm
= reg
;
5166 inst
.operands
[i
].immisreg
= 1;
5168 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5171 inst
.operands
[i
].shift_kind
= shift
;
5172 inst
.operands
[i
].shifted
= 1;
5177 /* Parse a <shifter_operand> for an ARM data processing instruction:
5180 #<immediate>, <rotate>
5184 where <shift> is defined by parse_shift above, and <rotate> is a
5185 multiple of 2 between 0 and 30. Validation of immediate operands
5186 is deferred to md_apply_fix. */
5189 parse_shifter_operand (char **str
, int i
)
5194 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5196 inst
.operands
[i
].reg
= value
;
5197 inst
.operands
[i
].isreg
= 1;
5199 /* parse_shift will override this if appropriate */
5200 inst
.reloc
.exp
.X_op
= O_constant
;
5201 inst
.reloc
.exp
.X_add_number
= 0;
5203 if (skip_past_comma (str
) == FAIL
)
5206 /* Shift operation on register. */
5207 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5210 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5213 if (skip_past_comma (str
) == SUCCESS
)
5215 /* #x, y -- ie explicit rotation by Y. */
5216 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5219 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5221 inst
.error
= _("constant expression expected");
5225 value
= exp
.X_add_number
;
5226 if (value
< 0 || value
> 30 || value
% 2 != 0)
5228 inst
.error
= _("invalid rotation");
5231 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5233 inst
.error
= _("invalid constant");
5237 /* Encode as specified. */
5238 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5242 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5243 inst
.reloc
.pc_rel
= 0;
5247 /* Group relocation information. Each entry in the table contains the
5248 textual name of the relocation as may appear in assembler source
5249 and must end with a colon.
5250 Along with this textual name are the relocation codes to be used if
5251 the corresponding instruction is an ALU instruction (ADD or SUB only),
5252 an LDR, an LDRS, or an LDC. */
5254 struct group_reloc_table_entry
5265 /* Varieties of non-ALU group relocation. */
5272 static struct group_reloc_table_entry group_reloc_table
[] =
5273 { /* Program counter relative: */
5275 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5280 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5281 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5282 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5283 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5285 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5290 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5291 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5292 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5293 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5295 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5296 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5297 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5298 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5299 /* Section base relative */
5301 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5306 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5307 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5308 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5309 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5311 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5316 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5317 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5318 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5319 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5321 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5322 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5323 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5324 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5326 /* Given the address of a pointer pointing to the textual name of a group
5327 relocation as may appear in assembler source, attempt to find its details
5328 in group_reloc_table. The pointer will be updated to the character after
5329 the trailing colon. On failure, FAIL will be returned; SUCCESS
5330 otherwise. On success, *entry will be updated to point at the relevant
5331 group_reloc_table entry. */
5334 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5337 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5339 int length
= strlen (group_reloc_table
[i
].name
);
5341 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5342 && (*str
)[length
] == ':')
5344 *out
= &group_reloc_table
[i
];
5345 *str
+= (length
+ 1);
5353 /* Parse a <shifter_operand> for an ARM data processing instruction
5354 (as for parse_shifter_operand) where group relocations are allowed:
5357 #<immediate>, <rotate>
5358 #:<group_reloc>:<expression>
5362 where <group_reloc> is one of the strings defined in group_reloc_table.
5363 The hashes are optional.
5365 Everything else is as for parse_shifter_operand. */
5367 static parse_operand_result
5368 parse_shifter_operand_group_reloc (char **str
, int i
)
5370 /* Determine if we have the sequence of characters #: or just :
5371 coming next. If we do, then we check for a group relocation.
5372 If we don't, punt the whole lot to parse_shifter_operand. */
5374 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5375 || (*str
)[0] == ':')
5377 struct group_reloc_table_entry
*entry
;
5379 if ((*str
)[0] == '#')
5384 /* Try to parse a group relocation. Anything else is an error. */
5385 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5387 inst
.error
= _("unknown group relocation");
5388 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5391 /* We now have the group relocation table entry corresponding to
5392 the name in the assembler source. Next, we parse the expression. */
5393 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5394 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5396 /* Record the relocation type (always the ALU variant here). */
5397 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5398 gas_assert (inst
.reloc
.type
!= 0);
5400 return PARSE_OPERAND_SUCCESS
;
5403 return parse_shifter_operand (str
, i
) == SUCCESS
5404 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5406 /* Never reached. */
5409 /* Parse a Neon alignment expression. Information is written to
5410 inst.operands[i]. We assume the initial ':' has been skipped.
5412 align .imm = align << 8, .immisalign=1, .preind=0 */
5413 static parse_operand_result
5414 parse_neon_alignment (char **str
, int i
)
5419 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5421 if (exp
.X_op
!= O_constant
)
5423 inst
.error
= _("alignment must be constant");
5424 return PARSE_OPERAND_FAIL
;
5427 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5428 inst
.operands
[i
].immisalign
= 1;
5429 /* Alignments are not pre-indexes. */
5430 inst
.operands
[i
].preind
= 0;
5433 return PARSE_OPERAND_SUCCESS
;
5436 /* Parse all forms of an ARM address expression. Information is written
5437 to inst.operands[i] and/or inst.reloc.
5439 Preindexed addressing (.preind=1):
5441 [Rn, #offset] .reg=Rn .reloc.exp=offset
5442 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5443 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5444 .shift_kind=shift .reloc.exp=shift_imm
5446 These three may have a trailing ! which causes .writeback to be set also.
5448 Postindexed addressing (.postind=1, .writeback=1):
5450 [Rn], #offset .reg=Rn .reloc.exp=offset
5451 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5452 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5453 .shift_kind=shift .reloc.exp=shift_imm
5455 Unindexed addressing (.preind=0, .postind=0):
5457 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5461 [Rn]{!} shorthand for [Rn,#0]{!}
5462 =immediate .isreg=0 .reloc.exp=immediate
5463 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5465 It is the caller's responsibility to check for addressing modes not
5466 supported by the instruction, and to set inst.reloc.type. */
5468 static parse_operand_result
5469 parse_address_main (char **str
, int i
, int group_relocations
,
5470 group_reloc_type group_type
)
5475 if (skip_past_char (&p
, '[') == FAIL
)
5477 if (skip_past_char (&p
, '=') == FAIL
)
5479 /* Bare address - translate to PC-relative offset. */
5480 inst
.reloc
.pc_rel
= 1;
5481 inst
.operands
[i
].reg
= REG_PC
;
5482 inst
.operands
[i
].isreg
= 1;
5483 inst
.operands
[i
].preind
= 1;
5485 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5486 return PARSE_OPERAND_FAIL
;
5488 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5489 /*allow_symbol_p=*/TRUE
))
5490 return PARSE_OPERAND_FAIL
;
5493 return PARSE_OPERAND_SUCCESS
;
5496 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5497 skip_whitespace (p
);
5499 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5501 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5502 return PARSE_OPERAND_FAIL
;
5504 inst
.operands
[i
].reg
= reg
;
5505 inst
.operands
[i
].isreg
= 1;
5507 if (skip_past_comma (&p
) == SUCCESS
)
5509 inst
.operands
[i
].preind
= 1;
5512 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5516 inst
.operands
[i
].imm
= reg
;
5517 inst
.operands
[i
].immisreg
= 1;
5519 if (skip_past_comma (&p
) == SUCCESS
)
5520 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5521 return PARSE_OPERAND_FAIL
;
5523 else if (skip_past_char (&p
, ':') == SUCCESS
)
5525 /* FIXME: '@' should be used here, but it's filtered out by generic
5526 code before we get to see it here. This may be subject to
5528 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5530 if (result
!= PARSE_OPERAND_SUCCESS
)
5535 if (inst
.operands
[i
].negative
)
5537 inst
.operands
[i
].negative
= 0;
5541 if (group_relocations
5542 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5544 struct group_reloc_table_entry
*entry
;
5546 /* Skip over the #: or : sequence. */
5552 /* Try to parse a group relocation. Anything else is an
5554 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5556 inst
.error
= _("unknown group relocation");
5557 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5560 /* We now have the group relocation table entry corresponding to
5561 the name in the assembler source. Next, we parse the
5563 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5566 /* Record the relocation type. */
5570 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5574 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5578 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5585 if (inst
.reloc
.type
== 0)
5587 inst
.error
= _("this group relocation is not allowed on this instruction");
5588 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5594 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5595 return PARSE_OPERAND_FAIL
;
5596 /* If the offset is 0, find out if it's a +0 or -0. */
5597 if (inst
.reloc
.exp
.X_op
== O_constant
5598 && inst
.reloc
.exp
.X_add_number
== 0)
5600 skip_whitespace (q
);
5604 skip_whitespace (q
);
5607 inst
.operands
[i
].negative
= 1;
5612 else if (skip_past_char (&p
, ':') == SUCCESS
)
5614 /* FIXME: '@' should be used here, but it's filtered out by generic code
5615 before we get to see it here. This may be subject to change. */
5616 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5618 if (result
!= PARSE_OPERAND_SUCCESS
)
5622 if (skip_past_char (&p
, ']') == FAIL
)
5624 inst
.error
= _("']' expected");
5625 return PARSE_OPERAND_FAIL
;
5628 if (skip_past_char (&p
, '!') == SUCCESS
)
5629 inst
.operands
[i
].writeback
= 1;
5631 else if (skip_past_comma (&p
) == SUCCESS
)
5633 if (skip_past_char (&p
, '{') == SUCCESS
)
5635 /* [Rn], {expr} - unindexed, with option */
5636 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5637 0, 255, TRUE
) == FAIL
)
5638 return PARSE_OPERAND_FAIL
;
5640 if (skip_past_char (&p
, '}') == FAIL
)
5642 inst
.error
= _("'}' expected at end of 'option' field");
5643 return PARSE_OPERAND_FAIL
;
5645 if (inst
.operands
[i
].preind
)
5647 inst
.error
= _("cannot combine index with option");
5648 return PARSE_OPERAND_FAIL
;
5651 return PARSE_OPERAND_SUCCESS
;
5655 inst
.operands
[i
].postind
= 1;
5656 inst
.operands
[i
].writeback
= 1;
5658 if (inst
.operands
[i
].preind
)
5660 inst
.error
= _("cannot combine pre- and post-indexing");
5661 return PARSE_OPERAND_FAIL
;
5665 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5667 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5669 /* We might be using the immediate for alignment already. If we
5670 are, OR the register number into the low-order bits. */
5671 if (inst
.operands
[i
].immisalign
)
5672 inst
.operands
[i
].imm
|= reg
;
5674 inst
.operands
[i
].imm
= reg
;
5675 inst
.operands
[i
].immisreg
= 1;
5677 if (skip_past_comma (&p
) == SUCCESS
)
5678 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5679 return PARSE_OPERAND_FAIL
;
5684 if (inst
.operands
[i
].negative
)
5686 inst
.operands
[i
].negative
= 0;
5689 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5690 return PARSE_OPERAND_FAIL
;
5691 /* If the offset is 0, find out if it's a +0 or -0. */
5692 if (inst
.reloc
.exp
.X_op
== O_constant
5693 && inst
.reloc
.exp
.X_add_number
== 0)
5695 skip_whitespace (q
);
5699 skip_whitespace (q
);
5702 inst
.operands
[i
].negative
= 1;
5708 /* If at this point neither .preind nor .postind is set, we have a
5709 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5710 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5712 inst
.operands
[i
].preind
= 1;
5713 inst
.reloc
.exp
.X_op
= O_constant
;
5714 inst
.reloc
.exp
.X_add_number
= 0;
5717 return PARSE_OPERAND_SUCCESS
;
5721 parse_address (char **str
, int i
)
5723 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5727 static parse_operand_result
5728 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5730 return parse_address_main (str
, i
, 1, type
);
5733 /* Parse an operand for a MOVW or MOVT instruction. */
5735 parse_half (char **str
)
5740 skip_past_char (&p
, '#');
5741 if (strncasecmp (p
, ":lower16:", 9) == 0)
5742 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5743 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5744 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5746 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5749 skip_whitespace (p
);
5752 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5755 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5757 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5759 inst
.error
= _("constant expression expected");
5762 if (inst
.reloc
.exp
.X_add_number
< 0
5763 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5765 inst
.error
= _("immediate value out of range");
5773 /* Miscellaneous. */
5775 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5776 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5778 parse_psr (char **str
, bfd_boolean lhs
)
5781 unsigned long psr_field
;
5782 const struct asm_psr
*psr
;
5784 bfd_boolean is_apsr
= FALSE
;
5785 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5787 /* PR gas/12698: If the user has specified -march=all then m_profile will
5788 be TRUE, but we want to ignore it in this case as we are building for any
5789 CPU type, including non-m variants. */
5790 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5793 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5794 feature for ease of use and backwards compatibility. */
5796 if (strncasecmp (p
, "SPSR", 4) == 0)
5799 goto unsupported_psr
;
5801 psr_field
= SPSR_BIT
;
5803 else if (strncasecmp (p
, "CPSR", 4) == 0)
5806 goto unsupported_psr
;
5810 else if (strncasecmp (p
, "APSR", 4) == 0)
5812 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5813 and ARMv7-R architecture CPUs. */
5822 while (ISALNUM (*p
) || *p
== '_');
5824 if (strncasecmp (start
, "iapsr", 5) == 0
5825 || strncasecmp (start
, "eapsr", 5) == 0
5826 || strncasecmp (start
, "xpsr", 4) == 0
5827 || strncasecmp (start
, "psr", 3) == 0)
5828 p
= start
+ strcspn (start
, "rR") + 1;
5830 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5836 /* If APSR is being written, a bitfield may be specified. Note that
5837 APSR itself is handled above. */
5838 if (psr
->field
<= 3)
5840 psr_field
= psr
->field
;
5846 /* M-profile MSR instructions have the mask field set to "10", except
5847 *PSR variants which modify APSR, which may use a different mask (and
5848 have been handled already). Do that by setting the PSR_f field
5850 return psr
->field
| (lhs
? PSR_f
: 0);
5853 goto unsupported_psr
;
5859 /* A suffix follows. */
5865 while (ISALNUM (*p
) || *p
== '_');
5869 /* APSR uses a notation for bits, rather than fields. */
5870 unsigned int nzcvq_bits
= 0;
5871 unsigned int g_bit
= 0;
5874 for (bit
= start
; bit
!= p
; bit
++)
5876 switch (TOLOWER (*bit
))
5879 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5883 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5887 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5891 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5895 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5899 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5903 inst
.error
= _("unexpected bit specified after APSR");
5908 if (nzcvq_bits
== 0x1f)
5913 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5915 inst
.error
= _("selected processor does not "
5916 "support DSP extension");
5923 if ((nzcvq_bits
& 0x20) != 0
5924 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5925 || (g_bit
& 0x2) != 0)
5927 inst
.error
= _("bad bitmask specified after APSR");
5933 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5938 psr_field
|= psr
->field
;
5944 goto error
; /* Garbage after "[CS]PSR". */
5946 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5947 is deprecated, but allow it anyway. */
5951 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5954 else if (!m_profile
)
5955 /* These bits are never right for M-profile devices: don't set them
5956 (only code paths which read/write APSR reach here). */
5957 psr_field
|= (PSR_c
| PSR_f
);
5963 inst
.error
= _("selected processor does not support requested special "
5964 "purpose register");
5968 inst
.error
= _("flag for {c}psr instruction expected");
5972 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5973 value suitable for splatting into the AIF field of the instruction. */
5976 parse_cps_flags (char **str
)
5985 case '\0': case ',':
5988 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5989 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5990 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5993 inst
.error
= _("unrecognized CPS flag");
5998 if (saw_a_flag
== 0)
6000 inst
.error
= _("missing CPS flags");
6008 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6009 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6012 parse_endian_specifier (char **str
)
6017 if (strncasecmp (s
, "BE", 2))
6019 else if (strncasecmp (s
, "LE", 2))
6023 inst
.error
= _("valid endian specifiers are be or le");
6027 if (ISALNUM (s
[2]) || s
[2] == '_')
6029 inst
.error
= _("valid endian specifiers are be or le");
6034 return little_endian
;
6037 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6038 value suitable for poking into the rotate field of an sxt or sxta
6039 instruction, or FAIL on error. */
6042 parse_ror (char **str
)
6047 if (strncasecmp (s
, "ROR", 3) == 0)
6051 inst
.error
= _("missing rotation field after comma");
6055 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6060 case 0: *str
= s
; return 0x0;
6061 case 8: *str
= s
; return 0x1;
6062 case 16: *str
= s
; return 0x2;
6063 case 24: *str
= s
; return 0x3;
6066 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6071 /* Parse a conditional code (from conds[] below). The value returned is in the
6072 range 0 .. 14, or FAIL. */
6074 parse_cond (char **str
)
6077 const struct asm_cond
*c
;
6079 /* Condition codes are always 2 characters, so matching up to
6080 3 characters is sufficient. */
6085 while (ISALPHA (*q
) && n
< 3)
6087 cond
[n
] = TOLOWER (*q
);
6092 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6095 inst
.error
= _("condition required");
6103 /* If the given feature available in the selected CPU, mark it as used.
6104 Returns TRUE iff feature is available. */
6106 mark_feature_used (const arm_feature_set
*feature
)
6108 /* Ensure the option is valid on the current architecture. */
6109 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6112 /* Add the appropriate architecture feature for the barrier option used.
6115 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6117 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6122 /* Parse an option for a barrier instruction. Returns the encoding for the
6125 parse_barrier (char **str
)
6128 const struct asm_barrier_opt
*o
;
6131 while (ISALPHA (*q
))
6134 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6139 if (!mark_feature_used (&o
->arch
))
6146 /* Parse the operands of a table branch instruction. Similar to a memory
6149 parse_tb (char **str
)
6154 if (skip_past_char (&p
, '[') == FAIL
)
6156 inst
.error
= _("'[' expected");
6160 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6162 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6165 inst
.operands
[0].reg
= reg
;
6167 if (skip_past_comma (&p
) == FAIL
)
6169 inst
.error
= _("',' expected");
6173 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6175 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6178 inst
.operands
[0].imm
= reg
;
6180 if (skip_past_comma (&p
) == SUCCESS
)
6182 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6184 if (inst
.reloc
.exp
.X_add_number
!= 1)
6186 inst
.error
= _("invalid shift");
6189 inst
.operands
[0].shifted
= 1;
6192 if (skip_past_char (&p
, ']') == FAIL
)
6194 inst
.error
= _("']' expected");
6201 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6202 information on the types the operands can take and how they are encoded.
6203 Up to four operands may be read; this function handles setting the
6204 ".present" field for each read operand itself.
6205 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6206 else returns FAIL. */
6209 parse_neon_mov (char **str
, int *which_operand
)
6211 int i
= *which_operand
, val
;
6212 enum arm_reg_type rtype
;
6214 struct neon_type_el optype
;
6216 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6218 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6219 inst
.operands
[i
].reg
= val
;
6220 inst
.operands
[i
].isscalar
= 1;
6221 inst
.operands
[i
].vectype
= optype
;
6222 inst
.operands
[i
++].present
= 1;
6224 if (skip_past_comma (&ptr
) == FAIL
)
6227 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6230 inst
.operands
[i
].reg
= val
;
6231 inst
.operands
[i
].isreg
= 1;
6232 inst
.operands
[i
].present
= 1;
6234 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6237 /* Cases 0, 1, 2, 3, 5 (D only). */
6238 if (skip_past_comma (&ptr
) == FAIL
)
6241 inst
.operands
[i
].reg
= val
;
6242 inst
.operands
[i
].isreg
= 1;
6243 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6244 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6245 inst
.operands
[i
].isvec
= 1;
6246 inst
.operands
[i
].vectype
= optype
;
6247 inst
.operands
[i
++].present
= 1;
6249 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6251 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6252 Case 13: VMOV <Sd>, <Rm> */
6253 inst
.operands
[i
].reg
= val
;
6254 inst
.operands
[i
].isreg
= 1;
6255 inst
.operands
[i
].present
= 1;
6257 if (rtype
== REG_TYPE_NQ
)
6259 first_error (_("can't use Neon quad register here"));
6262 else if (rtype
!= REG_TYPE_VFS
)
6265 if (skip_past_comma (&ptr
) == FAIL
)
6267 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6269 inst
.operands
[i
].reg
= val
;
6270 inst
.operands
[i
].isreg
= 1;
6271 inst
.operands
[i
].present
= 1;
6274 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6277 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6278 Case 1: VMOV<c><q> <Dd>, <Dm>
6279 Case 8: VMOV.F32 <Sd>, <Sm>
6280 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6285 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6286 inst
.operands
[i
].isvec
= 1;
6287 inst
.operands
[i
].vectype
= optype
;
6288 inst
.operands
[i
].present
= 1;
6290 if (skip_past_comma (&ptr
) == SUCCESS
)
6295 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
++].present
= 1;
6302 if (skip_past_comma (&ptr
) == FAIL
)
6305 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6308 inst
.operands
[i
].reg
= val
;
6309 inst
.operands
[i
].isreg
= 1;
6310 inst
.operands
[i
].present
= 1;
6313 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6316 Case 10: VMOV.F32 <Sd>, #<imm>
6317 Case 11: VMOV.F64 <Dd>, #<imm> */
6318 inst
.operands
[i
].immisfloat
= 1;
6319 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6321 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6322 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6326 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6330 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
++].present
= 1;
6337 if (skip_past_comma (&ptr
) == FAIL
)
6340 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6342 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6343 inst
.operands
[i
].reg
= val
;
6344 inst
.operands
[i
].isscalar
= 1;
6345 inst
.operands
[i
].present
= 1;
6346 inst
.operands
[i
].vectype
= optype
;
6348 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6350 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6351 inst
.operands
[i
].reg
= val
;
6352 inst
.operands
[i
].isreg
= 1;
6353 inst
.operands
[i
++].present
= 1;
6355 if (skip_past_comma (&ptr
) == FAIL
)
6358 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6361 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6369 inst
.operands
[i
].vectype
= optype
;
6370 inst
.operands
[i
].present
= 1;
6372 if (rtype
== REG_TYPE_VFS
)
6376 if (skip_past_comma (&ptr
) == FAIL
)
6378 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6381 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6384 inst
.operands
[i
].reg
= val
;
6385 inst
.operands
[i
].isreg
= 1;
6386 inst
.operands
[i
].isvec
= 1;
6387 inst
.operands
[i
].issingle
= 1;
6388 inst
.operands
[i
].vectype
= optype
;
6389 inst
.operands
[i
].present
= 1;
6392 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6396 inst
.operands
[i
].reg
= val
;
6397 inst
.operands
[i
].isreg
= 1;
6398 inst
.operands
[i
].isvec
= 1;
6399 inst
.operands
[i
].issingle
= 1;
6400 inst
.operands
[i
].vectype
= optype
;
6401 inst
.operands
[i
].present
= 1;
6406 first_error (_("parse error"));
6410 /* Successfully parsed the operands. Update args. */
6416 first_error (_("expected comma"));
6420 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6424 /* Use this macro when the operand constraints are different
6425 for ARM and THUMB (e.g. ldrd). */
6426 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6427 ((arm_operand) | ((thumb_operand) << 16))
6429 /* Matcher codes for parse_operands. */
6430 enum operand_parse_code
6432 OP_stop
, /* end of line */
6434 OP_RR
, /* ARM register */
6435 OP_RRnpc
, /* ARM register, not r15 */
6436 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6437 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6438 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6439 optional trailing ! */
6440 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6441 OP_RCP
, /* Coprocessor number */
6442 OP_RCN
, /* Coprocessor register */
6443 OP_RF
, /* FPA register */
6444 OP_RVS
, /* VFP single precision register */
6445 OP_RVD
, /* VFP double precision register (0..15) */
6446 OP_RND
, /* Neon double precision register (0..31) */
6447 OP_RNQ
, /* Neon quad precision register */
6448 OP_RVSD
, /* VFP single or double precision register */
6449 OP_RNDQ
, /* Neon double or quad precision register */
6450 OP_RNSDQ
, /* Neon single, double or quad precision register */
6451 OP_RNSC
, /* Neon scalar D[X] */
6452 OP_RVC
, /* VFP control register */
6453 OP_RMF
, /* Maverick F register */
6454 OP_RMD
, /* Maverick D register */
6455 OP_RMFX
, /* Maverick FX register */
6456 OP_RMDX
, /* Maverick DX register */
6457 OP_RMAX
, /* Maverick AX register */
6458 OP_RMDS
, /* Maverick DSPSC register */
6459 OP_RIWR
, /* iWMMXt wR register */
6460 OP_RIWC
, /* iWMMXt wC register */
6461 OP_RIWG
, /* iWMMXt wCG register */
6462 OP_RXA
, /* XScale accumulator register */
6464 OP_REGLST
, /* ARM register list */
6465 OP_VRSLST
, /* VFP single-precision register list */
6466 OP_VRDLST
, /* VFP double-precision register list */
6467 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6468 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6469 OP_NSTRLST
, /* Neon element/structure list */
6471 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6472 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6473 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6474 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6475 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6476 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6477 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6478 OP_VMOV
, /* Neon VMOV operands. */
6479 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6480 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6481 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6483 OP_I0
, /* immediate zero */
6484 OP_I7
, /* immediate value 0 .. 7 */
6485 OP_I15
, /* 0 .. 15 */
6486 OP_I16
, /* 1 .. 16 */
6487 OP_I16z
, /* 0 .. 16 */
6488 OP_I31
, /* 0 .. 31 */
6489 OP_I31w
, /* 0 .. 31, optional trailing ! */
6490 OP_I32
, /* 1 .. 32 */
6491 OP_I32z
, /* 0 .. 32 */
6492 OP_I63
, /* 0 .. 63 */
6493 OP_I63s
, /* -64 .. 63 */
6494 OP_I64
, /* 1 .. 64 */
6495 OP_I64z
, /* 0 .. 64 */
6496 OP_I255
, /* 0 .. 255 */
6498 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6499 OP_I7b
, /* 0 .. 7 */
6500 OP_I15b
, /* 0 .. 15 */
6501 OP_I31b
, /* 0 .. 31 */
6503 OP_SH
, /* shifter operand */
6504 OP_SHG
, /* shifter operand with possible group relocation */
6505 OP_ADDR
, /* Memory address expression (any mode) */
6506 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6507 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6508 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6509 OP_EXP
, /* arbitrary expression */
6510 OP_EXPi
, /* same, with optional immediate prefix */
6511 OP_EXPr
, /* same, with optional relocation suffix */
6512 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6514 OP_CPSF
, /* CPS flags */
6515 OP_ENDI
, /* Endianness specifier */
6516 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6517 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6518 OP_COND
, /* conditional code */
6519 OP_TB
, /* Table branch. */
6521 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6523 OP_RRnpc_I0
, /* ARM register or literal 0 */
6524 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6525 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6526 OP_RF_IF
, /* FPA register or immediate */
6527 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6528 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6530 /* Optional operands. */
6531 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6532 OP_oI31b
, /* 0 .. 31 */
6533 OP_oI32b
, /* 1 .. 32 */
6534 OP_oI32z
, /* 0 .. 32 */
6535 OP_oIffffb
, /* 0 .. 65535 */
6536 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6538 OP_oRR
, /* ARM register */
6539 OP_oRRnpc
, /* ARM register, not the PC */
6540 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6541 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6542 OP_oRND
, /* Optional Neon double precision register */
6543 OP_oRNQ
, /* Optional Neon quad precision register */
6544 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6545 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6546 OP_oSHll
, /* LSL immediate */
6547 OP_oSHar
, /* ASR immediate */
6548 OP_oSHllar
, /* LSL or ASR immediate */
6549 OP_oROR
, /* ROR 0/8/16/24 */
6550 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6552 /* Some pre-defined mixed (ARM/THUMB) operands. */
6553 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6554 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6555 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6557 OP_FIRST_OPTIONAL
= OP_oI7b
6560 /* Generic instruction operand parser. This does no encoding and no
6561 semantic validation; it merely squirrels values away in the inst
6562 structure. Returns SUCCESS or FAIL depending on whether the
6563 specified grammar matched. */
6565 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6567 unsigned const int *upat
= pattern
;
6568 char *backtrack_pos
= 0;
6569 const char *backtrack_error
= 0;
6570 int i
, val
= 0, backtrack_index
= 0;
6571 enum arm_reg_type rtype
;
6572 parse_operand_result result
;
6573 unsigned int op_parse_code
;
6575 #define po_char_or_fail(chr) \
6578 if (skip_past_char (&str, chr) == FAIL) \
6583 #define po_reg_or_fail(regtype) \
6586 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6587 & inst.operands[i].vectype); \
6590 first_error (_(reg_expected_msgs[regtype])); \
6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6598 || rtype == REG_TYPE_VFD \
6599 || rtype == REG_TYPE_NQ); \
6603 #define po_reg_or_goto(regtype, label) \
6606 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6607 & inst.operands[i].vectype); \
6611 inst.operands[i].reg = val; \
6612 inst.operands[i].isreg = 1; \
6613 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6614 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6615 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6616 || rtype == REG_TYPE_VFD \
6617 || rtype == REG_TYPE_NQ); \
6621 #define po_imm_or_fail(min, max, popt) \
6624 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6626 inst.operands[i].imm = val; \
6630 #define po_scalar_or_goto(elsz, label) \
6633 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6636 inst.operands[i].reg = val; \
6637 inst.operands[i].isscalar = 1; \
6641 #define po_misc_or_fail(expr) \
6649 #define po_misc_or_fail_no_backtrack(expr) \
6653 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6654 backtrack_pos = 0; \
6655 if (result != PARSE_OPERAND_SUCCESS) \
6660 #define po_barrier_or_imm(str) \
6663 val = parse_barrier (&str); \
6664 if (val == FAIL && ! ISALPHA (*str)) \
6667 /* ISB can only take SY as an option. */ \
6668 || ((inst.instruction & 0xf0) == 0x60 \
6671 inst.error = _("invalid barrier type"); \
6672 backtrack_pos = 0; \
6678 skip_whitespace (str
);
6680 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6682 op_parse_code
= upat
[i
];
6683 if (op_parse_code
>= 1<<16)
6684 op_parse_code
= thumb
? (op_parse_code
>> 16)
6685 : (op_parse_code
& ((1<<16)-1));
6687 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6689 /* Remember where we are in case we need to backtrack. */
6690 gas_assert (!backtrack_pos
);
6691 backtrack_pos
= str
;
6692 backtrack_error
= inst
.error
;
6693 backtrack_index
= i
;
6696 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6697 po_char_or_fail (',');
6699 switch (op_parse_code
)
6707 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6708 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6709 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6710 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6711 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6712 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6714 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6716 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6718 /* Also accept generic coprocessor regs for unknown registers. */
6720 po_reg_or_fail (REG_TYPE_CN
);
6722 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6723 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6724 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6725 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6726 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6727 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6728 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6729 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6730 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6731 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6733 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6735 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6736 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6738 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6740 /* Neon scalar. Using an element size of 8 means that some invalid
6741 scalars are accepted here, so deal with those in later code. */
6742 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6746 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6749 po_imm_or_fail (0, 0, TRUE
);
6754 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6759 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6762 if (parse_ifimm_zero (&str
))
6763 inst
.operands
[i
].imm
= 0;
6767 = _("only floating point zero is allowed as immediate value");
6775 po_scalar_or_goto (8, try_rr
);
6778 po_reg_or_fail (REG_TYPE_RN
);
6784 po_scalar_or_goto (8, try_nsdq
);
6787 po_reg_or_fail (REG_TYPE_NSDQ
);
6793 po_scalar_or_goto (8, try_ndq
);
6796 po_reg_or_fail (REG_TYPE_NDQ
);
6802 po_scalar_or_goto (8, try_vfd
);
6805 po_reg_or_fail (REG_TYPE_VFD
);
6810 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6811 not careful then bad things might happen. */
6812 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6817 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6820 /* There's a possibility of getting a 64-bit immediate here, so
6821 we need special handling. */
6822 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6825 inst
.error
= _("immediate value is out of range");
6833 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6836 po_imm_or_fail (0, 63, TRUE
);
6841 po_char_or_fail ('[');
6842 po_reg_or_fail (REG_TYPE_RN
);
6843 po_char_or_fail (']');
6849 po_reg_or_fail (REG_TYPE_RN
);
6850 if (skip_past_char (&str
, '!') == SUCCESS
)
6851 inst
.operands
[i
].writeback
= 1;
6855 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6856 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6857 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6858 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6859 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6860 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6861 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6862 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6863 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6864 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6865 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6866 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6868 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6870 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6871 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6873 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6874 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6875 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6876 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6878 /* Immediate variants */
6880 po_char_or_fail ('{');
6881 po_imm_or_fail (0, 255, TRUE
);
6882 po_char_or_fail ('}');
6886 /* The expression parser chokes on a trailing !, so we have
6887 to find it first and zap it. */
6890 while (*s
&& *s
!= ',')
6895 inst
.operands
[i
].writeback
= 1;
6897 po_imm_or_fail (0, 31, TRUE
);
6905 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6910 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6915 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6917 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6919 val
= parse_reloc (&str
);
6922 inst
.error
= _("unrecognized relocation suffix");
6925 else if (val
!= BFD_RELOC_UNUSED
)
6927 inst
.operands
[i
].imm
= val
;
6928 inst
.operands
[i
].hasreloc
= 1;
6933 /* Operand for MOVW or MOVT. */
6935 po_misc_or_fail (parse_half (&str
));
6938 /* Register or expression. */
6939 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6940 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6942 /* Register or immediate. */
6943 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6944 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6946 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6948 if (!is_immediate_prefix (*str
))
6951 val
= parse_fpa_immediate (&str
);
6954 /* FPA immediates are encoded as registers 8-15.
6955 parse_fpa_immediate has already applied the offset. */
6956 inst
.operands
[i
].reg
= val
;
6957 inst
.operands
[i
].isreg
= 1;
6960 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6961 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6963 /* Two kinds of register. */
6966 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6968 || (rege
->type
!= REG_TYPE_MMXWR
6969 && rege
->type
!= REG_TYPE_MMXWC
6970 && rege
->type
!= REG_TYPE_MMXWCG
))
6972 inst
.error
= _("iWMMXt data or control register expected");
6975 inst
.operands
[i
].reg
= rege
->number
;
6976 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6982 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6984 || (rege
->type
!= REG_TYPE_MMXWC
6985 && rege
->type
!= REG_TYPE_MMXWCG
))
6987 inst
.error
= _("iWMMXt control register expected");
6990 inst
.operands
[i
].reg
= rege
->number
;
6991 inst
.operands
[i
].isreg
= 1;
6996 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6997 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6998 case OP_oROR
: val
= parse_ror (&str
); break;
6999 case OP_COND
: val
= parse_cond (&str
); break;
7000 case OP_oBARRIER_I15
:
7001 po_barrier_or_imm (str
); break;
7003 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7009 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7010 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7012 inst
.error
= _("Banked registers are not available with this "
7018 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7022 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7025 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7027 if (strncasecmp (str
, "APSR_", 5) == 0)
7034 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7035 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7036 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7037 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7038 default: found
= 16;
7042 inst
.operands
[i
].isvec
= 1;
7043 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7044 inst
.operands
[i
].reg
= REG_PC
;
7051 po_misc_or_fail (parse_tb (&str
));
7054 /* Register lists. */
7056 val
= parse_reg_list (&str
);
7059 inst
.operands
[i
].writeback
= 1;
7065 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7069 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7073 /* Allow Q registers too. */
7074 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7081 inst
.operands
[i
].issingle
= 1;
7086 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7091 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7092 &inst
.operands
[i
].vectype
);
7095 /* Addressing modes */
7097 po_misc_or_fail (parse_address (&str
, i
));
7101 po_misc_or_fail_no_backtrack (
7102 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7106 po_misc_or_fail_no_backtrack (
7107 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7111 po_misc_or_fail_no_backtrack (
7112 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7116 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7120 po_misc_or_fail_no_backtrack (
7121 parse_shifter_operand_group_reloc (&str
, i
));
7125 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7129 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7133 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7137 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7140 /* Various value-based sanity checks and shared operations. We
7141 do not signal immediate failures for the register constraints;
7142 this allows a syntax error to take precedence. */
7143 switch (op_parse_code
)
7151 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7152 inst
.error
= BAD_PC
;
7157 if (inst
.operands
[i
].isreg
)
7159 if (inst
.operands
[i
].reg
== REG_PC
)
7160 inst
.error
= BAD_PC
;
7161 else if (inst
.operands
[i
].reg
== REG_SP
)
7162 inst
.error
= BAD_SP
;
7167 if (inst
.operands
[i
].isreg
7168 && inst
.operands
[i
].reg
== REG_PC
7169 && (inst
.operands
[i
].writeback
|| thumb
))
7170 inst
.error
= BAD_PC
;
7179 case OP_oBARRIER_I15
:
7188 inst
.operands
[i
].imm
= val
;
7195 /* If we get here, this operand was successfully parsed. */
7196 inst
.operands
[i
].present
= 1;
7200 inst
.error
= BAD_ARGS
;
7205 /* The parse routine should already have set inst.error, but set a
7206 default here just in case. */
7208 inst
.error
= _("syntax error");
7212 /* Do not backtrack over a trailing optional argument that
7213 absorbed some text. We will only fail again, with the
7214 'garbage following instruction' error message, which is
7215 probably less helpful than the current one. */
7216 if (backtrack_index
== i
&& backtrack_pos
!= str
7217 && upat
[i
+1] == OP_stop
)
7220 inst
.error
= _("syntax error");
7224 /* Try again, skipping the optional argument at backtrack_pos. */
7225 str
= backtrack_pos
;
7226 inst
.error
= backtrack_error
;
7227 inst
.operands
[backtrack_index
].present
= 0;
7228 i
= backtrack_index
;
7232 /* Check that we have parsed all the arguments. */
7233 if (*str
!= '\0' && !inst
.error
)
7234 inst
.error
= _("garbage following instruction");
7236 return inst
.error
? FAIL
: SUCCESS
;
7239 #undef po_char_or_fail
7240 #undef po_reg_or_fail
7241 #undef po_reg_or_goto
7242 #undef po_imm_or_fail
7243 #undef po_scalar_or_fail
7244 #undef po_barrier_or_imm
7246 /* Shorthand macro for instruction encoding functions issuing errors. */
7247 #define constraint(expr, err) \
7258 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7259 instructions are unpredictable if these registers are used. This
7260 is the BadReg predicate in ARM's Thumb-2 documentation. */
7261 #define reject_bad_reg(reg) \
7263 if (reg == REG_SP || reg == REG_PC) \
7265 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7270 /* If REG is R13 (the stack pointer), warn that its use is
7272 #define warn_deprecated_sp(reg) \
7274 if (warn_on_deprecated && reg == REG_SP) \
7275 as_tsktsk (_("use of r13 is deprecated")); \
7278 /* Functions for operand encoding. ARM, then Thumb. */
7280 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7282 /* If VAL can be encoded in the immediate field of an ARM instruction,
7283 return the encoded form. Otherwise, return FAIL. */
7286 encode_arm_immediate (unsigned int val
)
7290 for (i
= 0; i
< 32; i
+= 2)
7291 if ((a
= rotate_left (val
, i
)) <= 0xff)
7292 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7297 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7298 return the encoded form. Otherwise, return FAIL. */
7300 encode_thumb32_immediate (unsigned int val
)
7307 for (i
= 1; i
<= 24; i
++)
7310 if ((val
& ~(0xff << i
)) == 0)
7311 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7315 if (val
== ((a
<< 16) | a
))
7317 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7321 if (val
== ((a
<< 16) | a
))
7322 return 0x200 | (a
>> 8);
7326 /* Encode a VFP SP or DP register number into inst.instruction. */
7329 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7331 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7334 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7337 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7340 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7345 first_error (_("D register out of range for selected VFP version"));
7353 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7357 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7361 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7365 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7369 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7373 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7381 /* Encode a <shift> in an ARM-format instruction. The immediate,
7382 if any, is handled by md_apply_fix. */
7384 encode_arm_shift (int i
)
7386 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7387 inst
.instruction
|= SHIFT_ROR
<< 5;
7390 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7391 if (inst
.operands
[i
].immisreg
)
7393 inst
.instruction
|= SHIFT_BY_REG
;
7394 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7397 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7402 encode_arm_shifter_operand (int i
)
7404 if (inst
.operands
[i
].isreg
)
7406 inst
.instruction
|= inst
.operands
[i
].reg
;
7407 encode_arm_shift (i
);
7411 inst
.instruction
|= INST_IMMEDIATE
;
7412 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7413 inst
.instruction
|= inst
.operands
[i
].imm
;
7417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7419 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7422 Generate an error if the operand is not a register. */
7423 constraint (!inst
.operands
[i
].isreg
,
7424 _("Instruction does not support =N addresses"));
7426 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7428 if (inst
.operands
[i
].preind
)
7432 inst
.error
= _("instruction does not accept preindexed addressing");
7435 inst
.instruction
|= PRE_INDEX
;
7436 if (inst
.operands
[i
].writeback
)
7437 inst
.instruction
|= WRITE_BACK
;
7440 else if (inst
.operands
[i
].postind
)
7442 gas_assert (inst
.operands
[i
].writeback
);
7444 inst
.instruction
|= WRITE_BACK
;
7446 else /* unindexed - only for coprocessor */
7448 inst
.error
= _("instruction does not accept unindexed addressing");
7452 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7453 && (((inst
.instruction
& 0x000f0000) >> 16)
7454 == ((inst
.instruction
& 0x0000f000) >> 12)))
7455 as_warn ((inst
.instruction
& LOAD_BIT
)
7456 ? _("destination register same as write-back base")
7457 : _("source register same as write-back base"));
7460 /* inst.operands[i] was set up by parse_address. Encode it into an
7461 ARM-format mode 2 load or store instruction. If is_t is true,
7462 reject forms that cannot be used with a T instruction (i.e. not
7465 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7467 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7469 encode_arm_addr_mode_common (i
, is_t
);
7471 if (inst
.operands
[i
].immisreg
)
7473 constraint ((inst
.operands
[i
].imm
== REG_PC
7474 || (is_pc
&& inst
.operands
[i
].writeback
)),
7476 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7477 inst
.instruction
|= inst
.operands
[i
].imm
;
7478 if (!inst
.operands
[i
].negative
)
7479 inst
.instruction
|= INDEX_UP
;
7480 if (inst
.operands
[i
].shifted
)
7482 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7483 inst
.instruction
|= SHIFT_ROR
<< 5;
7486 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7487 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7491 else /* immediate offset in inst.reloc */
7493 if (is_pc
&& !inst
.reloc
.pc_rel
)
7495 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7498 cannot use PC in addressing.
7499 PC cannot be used in writeback addressing, either. */
7500 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7503 /* Use of PC in str is deprecated for ARMv7. */
7504 if (warn_on_deprecated
7506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7507 as_tsktsk (_("use of PC in this instruction is deprecated"));
7510 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7512 /* Prefer + for zero encoded value. */
7513 if (!inst
.operands
[i
].negative
)
7514 inst
.instruction
|= INDEX_UP
;
7515 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7520 /* inst.operands[i] was set up by parse_address. Encode it into an
7521 ARM-format mode 3 load or store instruction. Reject forms that
7522 cannot be used with such instructions. If is_t is true, reject
7523 forms that cannot be used with a T instruction (i.e. not
7526 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7528 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7530 inst
.error
= _("instruction does not accept scaled register index");
7534 encode_arm_addr_mode_common (i
, is_t
);
7536 if (inst
.operands
[i
].immisreg
)
7538 constraint ((inst
.operands
[i
].imm
== REG_PC
7539 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7541 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7543 inst
.instruction
|= inst
.operands
[i
].imm
;
7544 if (!inst
.operands
[i
].negative
)
7545 inst
.instruction
|= INDEX_UP
;
7547 else /* immediate offset in inst.reloc */
7549 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7550 && inst
.operands
[i
].writeback
),
7552 inst
.instruction
|= HWOFFSET_IMM
;
7553 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7555 /* Prefer + for zero encoded value. */
7556 if (!inst
.operands
[i
].negative
)
7557 inst
.instruction
|= INDEX_UP
;
7559 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7564 /* Write immediate bits [7:0] to the following locations:
7566 |28/24|23 19|18 16|15 4|3 0|
7567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7569 This function is used by VMOV/VMVN/VORR/VBIC. */
7572 neon_write_immbits (unsigned immbits
)
7574 inst
.instruction
|= immbits
& 0xf;
7575 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7576 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7579 /* Invert low-order SIZE bits of XHI:XLO. */
7582 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7584 unsigned immlo
= xlo
? *xlo
: 0;
7585 unsigned immhi
= xhi
? *xhi
: 0;
7590 immlo
= (~immlo
) & 0xff;
7594 immlo
= (~immlo
) & 0xffff;
7598 immhi
= (~immhi
) & 0xffffffff;
7602 immlo
= (~immlo
) & 0xffffffff;
7616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7620 neon_bits_same_in_bytes (unsigned imm
)
7622 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7623 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7624 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7625 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7628 /* For immediate of above form, return 0bABCD. */
7631 neon_squash_bits (unsigned imm
)
7633 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7634 | ((imm
& 0x01000000) >> 21);
7637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7640 neon_qfloat_bits (unsigned imm
)
7642 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7646 the instruction. *OP is passed as the initial value of the op field, and
7647 may be set to a different value depending on the constant (i.e.
7648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7649 MVN). If the immediate looks like a repeated pattern then also
7650 try smaller element sizes. */
7653 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7654 unsigned *immbits
, int *op
, int size
,
7655 enum neon_el_type type
)
7657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7659 if (type
== NT_float
&& !float_p
)
7662 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7664 if (size
!= 32 || *op
== 1)
7666 *immbits
= neon_qfloat_bits (immlo
);
7672 if (neon_bits_same_in_bytes (immhi
)
7673 && neon_bits_same_in_bytes (immlo
))
7677 *immbits
= (neon_squash_bits (immhi
) << 4)
7678 | neon_squash_bits (immlo
);
7689 if (immlo
== (immlo
& 0x000000ff))
7694 else if (immlo
== (immlo
& 0x0000ff00))
7696 *immbits
= immlo
>> 8;
7699 else if (immlo
== (immlo
& 0x00ff0000))
7701 *immbits
= immlo
>> 16;
7704 else if (immlo
== (immlo
& 0xff000000))
7706 *immbits
= immlo
>> 24;
7709 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7711 *immbits
= (immlo
>> 8) & 0xff;
7714 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7716 *immbits
= (immlo
>> 16) & 0xff;
7720 if ((immlo
& 0xffff) != (immlo
>> 16))
7727 if (immlo
== (immlo
& 0x000000ff))
7732 else if (immlo
== (immlo
& 0x0000ff00))
7734 *immbits
= immlo
>> 8;
7738 if ((immlo
& 0xff) != (immlo
>> 8))
7743 if (immlo
== (immlo
& 0x000000ff))
7745 /* Don't allow MVN with 8-bit immediate. */
7755 /* Returns TRUE if double precision value V may be cast
7756 to single precision without loss of accuracy. */
7759 is_double_a_single (long int v
)
7761 int exp
= (int) (v
>> 52) & 0x7FF;
7762 long int mantissa
= (v
& 0xFFFFFFFFFFFFFl
);
7764 return (exp
== 0 || exp
== 0x7FF
7765 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7766 && (mantissa
& 0x1FFFFFFFl
) == 0;
7769 /* Returns a double precision value casted to single precision
7770 (ignoring the least significant bits in exponent and mantissa). */
7773 double_to_single (long int v
)
7775 int sign
= (int) ((v
>> 63) & 1l);
7776 int exp
= (int) (v
>> 52) & 0x7FF;
7777 long int mantissa
= (v
& 0xFFFFFFFFFFFFFl
);
7783 exp
= exp
- 1023 + 127;
7792 /* No denormalized numbers. */
7798 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7808 static void do_vfp_nsyn_opcode (const char *);
7810 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7811 Determine whether it can be performed with a move instruction; if
7812 it can, convert inst.instruction to that move instruction and
7813 return TRUE; if it can't, convert inst.instruction to a literal-pool
7814 load and return FALSE. If this is not a valid thing to do in the
7815 current context, set inst.error and return TRUE.
7817 inst.operands[i] describes the destination register. */
7820 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7823 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7824 bfd_boolean arm_p
= (t
== CONST_ARM
);
7827 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7831 if ((inst
.instruction
& tbit
) == 0)
7833 inst
.error
= _("invalid pseudo operation");
7837 if (inst
.reloc
.exp
.X_op
!= O_constant
7838 && inst
.reloc
.exp
.X_op
!= O_symbol
7839 && inst
.reloc
.exp
.X_op
!= O_big
)
7841 inst
.error
= _("constant expression expected");
7845 if (inst
.reloc
.exp
.X_op
== O_constant
7846 || inst
.reloc
.exp
.X_op
== O_big
)
7850 if (inst
.reloc
.exp
.X_op
== O_big
)
7852 LITTLENUM_TYPE w
[X_PRECISION
];
7855 if (inst
.reloc
.exp
.X_add_number
== -1)
7857 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7859 /* FIXME: Should we check words w[2..5] ? */
7864 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7865 | (l
[0] & LITTLENUM_MASK
);
7868 v
= inst
.reloc
.exp
.X_add_number
;
7870 if (!inst
.operands
[i
].issingle
)
7874 if ((v
& ~0xFF) == 0)
7876 /* This can be done with a mov(1) instruction. */
7877 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7878 inst
.instruction
|= v
;
7882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)
7883 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7885 /* Check if on thumb2 it can be done with a mov.w or mvn.w instruction. */
7886 unsigned int newimm
;
7887 bfd_boolean isNegated
;
7889 newimm
= encode_thumb32_immediate (v
);
7890 if (newimm
!= (unsigned int) FAIL
)
7894 newimm
= encode_thumb32_immediate (~ v
);
7895 if (newimm
!= (unsigned int) FAIL
)
7899 if (newimm
!= (unsigned int) FAIL
)
7901 inst
.instruction
= 0xf04f0000 | (inst
.operands
[i
].reg
<< 8);
7902 inst
.instruction
|= (isNegated
?0x200000:0);
7903 inst
.instruction
|= (newimm
& 0x800) << 15;
7904 inst
.instruction
|= (newimm
& 0x700) << 4;
7905 inst
.instruction
|= (newimm
& 0x0ff);
7908 else if ((v
& ~0xFFFF) == 0 || (v
& ~0xFFFF0000) == 0)
7910 /* The number may be loaded with a movw/movt instruction. */
7913 if ((inst
.reloc
.exp
.X_add_number
& ~0xFFFF) == 0)
7915 inst
.instruction
= 0xf2400000;
7920 inst
.instruction
= 0xf2c00000;
7924 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7925 inst
.instruction
|= (imm
& 0xf000) << 4;
7926 inst
.instruction
|= (imm
& 0x0800) << 15;
7927 inst
.instruction
|= (imm
& 0x0700) << 4;
7928 inst
.instruction
|= (imm
& 0x00ff);
7935 int value
= encode_arm_immediate (v
);
7939 /* This can be done with a mov instruction. */
7940 inst
.instruction
&= LITERAL_MASK
;
7941 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7942 inst
.instruction
|= value
& 0xfff;
7946 value
= encode_arm_immediate (~ v
);
7949 /* This can be done with a mvn instruction. */
7950 inst
.instruction
&= LITERAL_MASK
;
7951 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7952 inst
.instruction
|= value
& 0xfff;
7956 else if (t
== CONST_VEC
)
7959 unsigned immbits
= 0;
7960 unsigned immlo
= inst
.operands
[1].imm
;
7961 unsigned immhi
= inst
.operands
[1].regisimm
7962 ? inst
.operands
[1].reg
7963 : inst
.reloc
.exp
.X_unsigned
7965 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7966 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7967 &op
, 64, NT_invtype
);
7971 neon_invert_size (&immlo
, &immhi
, 64);
7973 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7974 &op
, 64, NT_invtype
);
7979 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7985 /* Fill other bits in vmov encoding for both thumb and arm. */
7987 inst
.instruction
|= (0x7 << 29) | (0xF << 24);
7989 inst
.instruction
|= (0xF << 28) | (0x1 << 25);
7990 neon_write_immbits (immbits
);
7998 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7999 if (inst
.operands
[i
].issingle
8000 && is_quarter_float (inst
.operands
[1].imm
)
8001 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8003 inst
.operands
[1].imm
=
8004 neon_qfloat_bits (v
);
8005 do_vfp_nsyn_opcode ("fconsts");
8008 else if (!inst
.operands
[1].issingle
8009 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8011 if (is_double_a_single (v
)
8012 && is_quarter_float (double_to_single (v
)))
8014 inst
.operands
[1].imm
=
8015 neon_qfloat_bits (double_to_single (v
));
8016 do_vfp_nsyn_opcode ("fconstd");
8023 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8024 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8027 inst
.operands
[1].reg
= REG_PC
;
8028 inst
.operands
[1].isreg
= 1;
8029 inst
.operands
[1].preind
= 1;
8030 inst
.reloc
.pc_rel
= 1;
8031 inst
.reloc
.type
= (thumb_p
8032 ? BFD_RELOC_ARM_THUMB_OFFSET
8034 ? BFD_RELOC_ARM_HWLITERAL
8035 : BFD_RELOC_ARM_LITERAL
));
8039 /* inst.operands[i] was set up by parse_address. Encode it into an
8040 ARM-format instruction. Reject all forms which cannot be encoded
8041 into a coprocessor load/store instruction. If wb_ok is false,
8042 reject use of writeback; if unind_ok is false, reject use of
8043 unindexed addressing. If reloc_override is not 0, use it instead
8044 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8045 (in which case it is preserved). */
8048 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8050 if (!inst
.operands
[i
].isreg
)
8053 if (! inst
.operands
[0].isvec
)
8055 inst
.error
= _("invalid co-processor operand");
8058 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8062 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8064 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8066 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8068 gas_assert (!inst
.operands
[i
].writeback
);
8071 inst
.error
= _("instruction does not support unindexed addressing");
8074 inst
.instruction
|= inst
.operands
[i
].imm
;
8075 inst
.instruction
|= INDEX_UP
;
8079 if (inst
.operands
[i
].preind
)
8080 inst
.instruction
|= PRE_INDEX
;
8082 if (inst
.operands
[i
].writeback
)
8084 if (inst
.operands
[i
].reg
== REG_PC
)
8086 inst
.error
= _("pc may not be used with write-back");
8091 inst
.error
= _("instruction does not support writeback");
8094 inst
.instruction
|= WRITE_BACK
;
8098 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8099 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8100 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8101 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8104 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8106 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8109 /* Prefer + for zero encoded value. */
8110 if (!inst
.operands
[i
].negative
)
8111 inst
.instruction
|= INDEX_UP
;
8116 /* Functions for instruction encoding, sorted by sub-architecture.
8117 First some generics; their names are taken from the conventional
8118 bit positions for register arguments in ARM format instructions. */
8128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8135 inst
.instruction
|= inst
.operands
[1].reg
;
8141 inst
.instruction
|= inst
.operands
[0].reg
;
8142 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8155 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8156 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8160 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8162 if (ARM_CPU_IS_ANY (cpu_variant
))
8164 as_tsktsk ("%s", msg
);
8167 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8179 unsigned Rn
= inst
.operands
[2].reg
;
8180 /* Enforce restrictions on SWP instruction. */
8181 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8183 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8184 _("Rn must not overlap other operands"));
8186 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8188 if (!check_obsolete (&arm_ext_v8
,
8189 _("swp{b} use is obsoleted for ARMv8 and later"))
8190 && warn_on_deprecated
8191 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8192 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8196 inst
.instruction
|= inst
.operands
[1].reg
;
8197 inst
.instruction
|= Rn
<< 16;
8203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 inst
.instruction
|= inst
.operands
[2].reg
;
8211 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8212 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8213 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8214 || inst
.reloc
.exp
.X_add_number
!= 0),
8216 inst
.instruction
|= inst
.operands
[0].reg
;
8217 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8218 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8224 inst
.instruction
|= inst
.operands
[0].imm
;
8230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8231 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8234 /* ARM instructions, in alphabetical order by function name (except
8235 that wrapper functions appear immediately after the function they
8238 /* This is a pseudo-op of the form "adr rd, label" to be converted
8239 into a relative address of the form "add rd, pc, #label-.-8". */
8244 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8246 /* Frag hacking will turn this into a sub instruction if the offset turns
8247 out to be negative. */
8248 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8249 inst
.reloc
.pc_rel
= 1;
8250 inst
.reloc
.exp
.X_add_number
-= 8;
8253 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8254 into a relative address of the form:
8255 add rd, pc, #low(label-.-8)"
8256 add rd, rd, #high(label-.-8)" */
8261 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8263 /* Frag hacking will turn this into a sub instruction if the offset turns
8264 out to be negative. */
8265 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8266 inst
.reloc
.pc_rel
= 1;
8267 inst
.size
= INSN_SIZE
* 2;
8268 inst
.reloc
.exp
.X_add_number
-= 8;
8274 if (!inst
.operands
[1].present
)
8275 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8277 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8278 encode_arm_shifter_operand (2);
8284 if (inst
.operands
[0].present
)
8285 inst
.instruction
|= inst
.operands
[0].imm
;
8287 inst
.instruction
|= 0xf;
8293 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8294 constraint (msb
> 32, _("bit-field extends past end of register"));
8295 /* The instruction encoding stores the LSB and MSB,
8296 not the LSB and width. */
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8299 inst
.instruction
|= (msb
- 1) << 16;
8307 /* #0 in second position is alternative syntax for bfc, which is
8308 the same instruction but with REG_PC in the Rm field. */
8309 if (!inst
.operands
[1].isreg
)
8310 inst
.operands
[1].reg
= REG_PC
;
8312 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8313 constraint (msb
> 32, _("bit-field extends past end of register"));
8314 /* The instruction encoding stores the LSB and MSB,
8315 not the LSB and width. */
8316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8317 inst
.instruction
|= inst
.operands
[1].reg
;
8318 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8319 inst
.instruction
|= (msb
- 1) << 16;
8325 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8326 _("bit-field extends past end of register"));
8327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8328 inst
.instruction
|= inst
.operands
[1].reg
;
8329 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8330 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8333 /* ARM V5 breakpoint instruction (argument parse)
8334 BKPT <16 bit unsigned immediate>
8335 Instruction is not conditional.
8336 The bit pattern given in insns[] has the COND_ALWAYS condition,
8337 and it is an error if the caller tried to override that. */
8342 /* Top 12 of 16 bits to bits 19:8. */
8343 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8345 /* Bottom 4 of 16 bits to bits 3:0. */
8346 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8350 encode_branch (int default_reloc
)
8352 if (inst
.operands
[0].hasreloc
)
8354 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8355 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8356 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8357 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8358 ? BFD_RELOC_ARM_PLT32
8359 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8362 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8363 inst
.reloc
.pc_rel
= 1;
8370 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8371 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8374 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8381 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8383 if (inst
.cond
== COND_ALWAYS
)
8384 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8386 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8390 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8393 /* ARM V5 branch-link-exchange instruction (argument parse)
8394 BLX <target_addr> ie BLX(1)
8395 BLX{<condition>} <Rm> ie BLX(2)
8396 Unfortunately, there are two different opcodes for this mnemonic.
8397 So, the insns[].value is not used, and the code here zaps values
8398 into inst.instruction.
8399 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8404 if (inst
.operands
[0].isreg
)
8406 /* Arg is a register; the opcode provided by insns[] is correct.
8407 It is not illegal to do "blx pc", just useless. */
8408 if (inst
.operands
[0].reg
== REG_PC
)
8409 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8411 inst
.instruction
|= inst
.operands
[0].reg
;
8415 /* Arg is an address; this instruction cannot be executed
8416 conditionally, and the opcode must be adjusted.
8417 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8418 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8419 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8420 inst
.instruction
= 0xfa000000;
8421 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8428 bfd_boolean want_reloc
;
8430 if (inst
.operands
[0].reg
== REG_PC
)
8431 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8433 inst
.instruction
|= inst
.operands
[0].reg
;
8434 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8435 it is for ARMv4t or earlier. */
8436 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8437 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8441 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8446 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8450 /* ARM v5TEJ. Jump to Jazelle code. */
8455 if (inst
.operands
[0].reg
== REG_PC
)
8456 as_tsktsk (_("use of r15 in bxj is not really useful"));
8458 inst
.instruction
|= inst
.operands
[0].reg
;
8461 /* Co-processor data operation:
8462 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8463 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8467 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8468 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8469 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8470 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8471 inst
.instruction
|= inst
.operands
[4].reg
;
8472 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8479 encode_arm_shifter_operand (1);
8482 /* Transfer between coprocessor and ARM registers.
8483 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8488 No special properties. */
8490 struct deprecated_coproc_regs_s
8497 arm_feature_set deprecated
;
8498 arm_feature_set obsoleted
;
8499 const char *dep_msg
;
8500 const char *obs_msg
;
8503 #define DEPR_ACCESS_V8 \
8504 N_("This coprocessor register access is deprecated in ARMv8")
8506 /* Table of all deprecated coprocessor registers. */
8507 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8509 {15, 0, 7, 10, 5, /* CP15DMB. */
8510 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8511 DEPR_ACCESS_V8
, NULL
},
8512 {15, 0, 7, 10, 4, /* CP15DSB. */
8513 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8514 DEPR_ACCESS_V8
, NULL
},
8515 {15, 0, 7, 5, 4, /* CP15ISB. */
8516 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8517 DEPR_ACCESS_V8
, NULL
},
8518 {14, 6, 1, 0, 0, /* TEEHBR. */
8519 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8520 DEPR_ACCESS_V8
, NULL
},
8521 {14, 6, 0, 0, 0, /* TEECR. */
8522 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8523 DEPR_ACCESS_V8
, NULL
},
8526 #undef DEPR_ACCESS_V8
8528 static const size_t deprecated_coproc_reg_count
=
8529 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8537 Rd
= inst
.operands
[2].reg
;
8540 if (inst
.instruction
== 0xee000010
8541 || inst
.instruction
== 0xfe000010)
8543 reject_bad_reg (Rd
);
8546 constraint (Rd
== REG_SP
, BAD_SP
);
8551 if (inst
.instruction
== 0xe000010)
8552 constraint (Rd
== REG_PC
, BAD_PC
);
8555 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8557 const struct deprecated_coproc_regs_s
*r
=
8558 deprecated_coproc_regs
+ i
;
8560 if (inst
.operands
[0].reg
== r
->cp
8561 && inst
.operands
[1].imm
== r
->opc1
8562 && inst
.operands
[3].reg
== r
->crn
8563 && inst
.operands
[4].reg
== r
->crm
8564 && inst
.operands
[5].imm
== r
->opc2
)
8566 if (! ARM_CPU_IS_ANY (cpu_variant
)
8567 && warn_on_deprecated
8568 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8569 as_tsktsk ("%s", r
->dep_msg
);
8573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8574 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8575 inst
.instruction
|= Rd
<< 12;
8576 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[4].reg
;
8578 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8581 /* Transfer between coprocessor register and pair of ARM registers.
8582 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8587 Two XScale instructions are special cases of these:
8589 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8590 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8592 Result unpredictable if Rd or Rn is R15. */
8599 Rd
= inst
.operands
[2].reg
;
8600 Rn
= inst
.operands
[3].reg
;
8604 reject_bad_reg (Rd
);
8605 reject_bad_reg (Rn
);
8609 constraint (Rd
== REG_PC
, BAD_PC
);
8610 constraint (Rn
== REG_PC
, BAD_PC
);
8613 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8614 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8615 inst
.instruction
|= Rd
<< 12;
8616 inst
.instruction
|= Rn
<< 16;
8617 inst
.instruction
|= inst
.operands
[4].reg
;
8623 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8624 if (inst
.operands
[1].present
)
8626 inst
.instruction
|= CPSI_MMOD
;
8627 inst
.instruction
|= inst
.operands
[1].imm
;
8634 inst
.instruction
|= inst
.operands
[0].imm
;
8640 unsigned Rd
, Rn
, Rm
;
8642 Rd
= inst
.operands
[0].reg
;
8643 Rn
= (inst
.operands
[1].present
8644 ? inst
.operands
[1].reg
: Rd
);
8645 Rm
= inst
.operands
[2].reg
;
8647 constraint ((Rd
== REG_PC
), BAD_PC
);
8648 constraint ((Rn
== REG_PC
), BAD_PC
);
8649 constraint ((Rm
== REG_PC
), BAD_PC
);
8651 inst
.instruction
|= Rd
<< 16;
8652 inst
.instruction
|= Rn
<< 0;
8653 inst
.instruction
|= Rm
<< 8;
8659 /* There is no IT instruction in ARM mode. We
8660 process it to do the validation as if in
8661 thumb mode, just in case the code gets
8662 assembled for thumb using the unified syntax. */
8667 set_it_insn_type (IT_INSN
);
8668 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8669 now_it
.cc
= inst
.operands
[0].imm
;
8673 /* If there is only one register in the register list,
8674 then return its register number. Otherwise return -1. */
8676 only_one_reg_in_list (int range
)
8678 int i
= ffs (range
) - 1;
8679 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8683 encode_ldmstm(int from_push_pop_mnem
)
8685 int base_reg
= inst
.operands
[0].reg
;
8686 int range
= inst
.operands
[1].imm
;
8689 inst
.instruction
|= base_reg
<< 16;
8690 inst
.instruction
|= range
;
8692 if (inst
.operands
[1].writeback
)
8693 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8695 if (inst
.operands
[0].writeback
)
8697 inst
.instruction
|= WRITE_BACK
;
8698 /* Check for unpredictable uses of writeback. */
8699 if (inst
.instruction
& LOAD_BIT
)
8701 /* Not allowed in LDM type 2. */
8702 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8703 && ((range
& (1 << REG_PC
)) == 0))
8704 as_warn (_("writeback of base register is UNPREDICTABLE"));
8705 /* Only allowed if base reg not in list for other types. */
8706 else if (range
& (1 << base_reg
))
8707 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8711 /* Not allowed for type 2. */
8712 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8713 as_warn (_("writeback of base register is UNPREDICTABLE"));
8714 /* Only allowed if base reg not in list, or first in list. */
8715 else if ((range
& (1 << base_reg
))
8716 && (range
& ((1 << base_reg
) - 1)))
8717 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8721 /* If PUSH/POP has only one register, then use the A2 encoding. */
8722 one_reg
= only_one_reg_in_list (range
);
8723 if (from_push_pop_mnem
&& one_reg
>= 0)
8725 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8727 inst
.instruction
&= A_COND_MASK
;
8728 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8729 inst
.instruction
|= one_reg
<< 12;
8736 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8739 /* ARMv5TE load-consecutive (argument parse)
8748 constraint (inst
.operands
[0].reg
% 2 != 0,
8749 _("first transfer register must be even"));
8750 constraint (inst
.operands
[1].present
8751 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8752 _("can only transfer two consecutive registers"));
8753 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8754 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8756 if (!inst
.operands
[1].present
)
8757 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8759 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8760 register and the first register written; we have to diagnose
8761 overlap between the base and the second register written here. */
8763 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8764 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8765 as_warn (_("base register written back, and overlaps "
8766 "second transfer register"));
8768 if (!(inst
.instruction
& V4_STR_BIT
))
8770 /* For an index-register load, the index register must not overlap the
8771 destination (even if not write-back). */
8772 if (inst
.operands
[2].immisreg
8773 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8774 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8775 as_warn (_("index register overlaps transfer register"));
8777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8778 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8784 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8785 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8786 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8787 || inst
.operands
[1].negative
8788 /* This can arise if the programmer has written
8790 or if they have mistakenly used a register name as the last
8793 It is very difficult to distinguish between these two cases
8794 because "rX" might actually be a label. ie the register
8795 name has been occluded by a symbol of the same name. So we
8796 just generate a general 'bad addressing mode' type error
8797 message and leave it up to the programmer to discover the
8798 true cause and fix their mistake. */
8799 || (inst
.operands
[1].reg
== REG_PC
),
8802 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8803 || inst
.reloc
.exp
.X_add_number
!= 0,
8804 _("offset must be zero in ARM encoding"));
8806 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8808 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8809 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8810 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8816 constraint (inst
.operands
[0].reg
% 2 != 0,
8817 _("even register required"));
8818 constraint (inst
.operands
[1].present
8819 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8820 _("can only load two consecutive registers"));
8821 /* If op 1 were present and equal to PC, this function wouldn't
8822 have been called in the first place. */
8823 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8826 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8829 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8830 which is not a multiple of four is UNPREDICTABLE. */
8832 check_ldr_r15_aligned (void)
8834 constraint (!(inst
.operands
[1].immisreg
)
8835 && (inst
.operands
[0].reg
== REG_PC
8836 && inst
.operands
[1].reg
== REG_PC
8837 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8838 _("ldr to register 15 must be 4-byte alligned"));
8844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8845 if (!inst
.operands
[1].isreg
)
8846 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8848 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8849 check_ldr_r15_aligned ();
8855 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8857 if (inst
.operands
[1].preind
)
8859 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8860 || inst
.reloc
.exp
.X_add_number
!= 0,
8861 _("this instruction requires a post-indexed address"));
8863 inst
.operands
[1].preind
= 0;
8864 inst
.operands
[1].postind
= 1;
8865 inst
.operands
[1].writeback
= 1;
8867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8868 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8871 /* Halfword and signed-byte load/store operations. */
8876 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8878 if (!inst
.operands
[1].isreg
)
8879 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8881 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8887 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8889 if (inst
.operands
[1].preind
)
8891 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8892 || inst
.reloc
.exp
.X_add_number
!= 0,
8893 _("this instruction requires a post-indexed address"));
8895 inst
.operands
[1].preind
= 0;
8896 inst
.operands
[1].postind
= 1;
8897 inst
.operands
[1].writeback
= 1;
8899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8900 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8903 /* Co-processor register load/store.
8904 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8909 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8910 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8916 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8917 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8918 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8919 && !(inst
.instruction
& 0x00400000))
8920 as_tsktsk (_("Rd and Rm should be different in mla"));
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8923 inst
.instruction
|= inst
.operands
[1].reg
;
8924 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8925 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8932 encode_arm_shifter_operand (1);
8935 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8942 top
= (inst
.instruction
& 0x00400000) != 0;
8943 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8944 _(":lower16: not allowed this instruction"));
8945 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8946 _(":upper16: not allowed instruction"));
8947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8948 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8950 imm
= inst
.reloc
.exp
.X_add_number
;
8951 /* The value is in two pieces: 0:11, 16:19. */
8952 inst
.instruction
|= (imm
& 0x00000fff);
8953 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8958 do_vfp_nsyn_mrs (void)
8960 if (inst
.operands
[0].isvec
)
8962 if (inst
.operands
[1].reg
!= 1)
8963 first_error (_("operand 1 must be FPSCR"));
8964 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8965 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8966 do_vfp_nsyn_opcode ("fmstat");
8968 else if (inst
.operands
[1].isvec
)
8969 do_vfp_nsyn_opcode ("fmrx");
8977 do_vfp_nsyn_msr (void)
8979 if (inst
.operands
[0].isvec
)
8980 do_vfp_nsyn_opcode ("fmxr");
8990 unsigned Rt
= inst
.operands
[0].reg
;
8992 if (thumb_mode
&& Rt
== REG_SP
)
8994 inst
.error
= BAD_SP
;
8998 /* APSR_ sets isvec. All other refs to PC are illegal. */
8999 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9001 inst
.error
= BAD_PC
;
9005 /* If we get through parsing the register name, we just insert the number
9006 generated into the instruction without further validation. */
9007 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9008 inst
.instruction
|= (Rt
<< 12);
9014 unsigned Rt
= inst
.operands
[1].reg
;
9017 reject_bad_reg (Rt
);
9018 else if (Rt
== REG_PC
)
9020 inst
.error
= BAD_PC
;
9024 /* If we get through parsing the register name, we just insert the number
9025 generated into the instruction without further validation. */
9026 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9027 inst
.instruction
|= (Rt
<< 12);
9035 if (do_vfp_nsyn_mrs () == SUCCESS
)
9038 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9041 if (inst
.operands
[1].isreg
)
9043 br
= inst
.operands
[1].reg
;
9044 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9045 as_bad (_("bad register for mrs"));
9049 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9050 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9052 _("'APSR', 'CPSR' or 'SPSR' expected"));
9053 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9056 inst
.instruction
|= br
;
9059 /* Two possible forms:
9060 "{C|S}PSR_<field>, Rm",
9061 "{C|S}PSR_f, #expression". */
9066 if (do_vfp_nsyn_msr () == SUCCESS
)
9069 inst
.instruction
|= inst
.operands
[0].imm
;
9070 if (inst
.operands
[1].isreg
)
9071 inst
.instruction
|= inst
.operands
[1].reg
;
9074 inst
.instruction
|= INST_IMMEDIATE
;
9075 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9076 inst
.reloc
.pc_rel
= 0;
9083 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9085 if (!inst
.operands
[2].present
)
9086 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9087 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9088 inst
.instruction
|= inst
.operands
[1].reg
;
9089 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9091 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9092 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9093 as_tsktsk (_("Rd and Rm should be different in mul"));
9096 /* Long Multiply Parser
9097 UMULL RdLo, RdHi, Rm, Rs
9098 SMULL RdLo, RdHi, Rm, Rs
9099 UMLAL RdLo, RdHi, Rm, Rs
9100 SMLAL RdLo, RdHi, Rm, Rs. */
9105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9106 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9107 inst
.instruction
|= inst
.operands
[2].reg
;
9108 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9110 /* rdhi and rdlo must be different. */
9111 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9112 as_tsktsk (_("rdhi and rdlo must be different"));
9114 /* rdhi, rdlo and rm must all be different before armv6. */
9115 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9116 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9117 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9118 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9124 if (inst
.operands
[0].present
9125 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9127 /* Architectural NOP hints are CPSR sets with no bits selected. */
9128 inst
.instruction
&= 0xf0000000;
9129 inst
.instruction
|= 0x0320f000;
9130 if (inst
.operands
[0].present
)
9131 inst
.instruction
|= inst
.operands
[0].imm
;
9135 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9136 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9137 Condition defaults to COND_ALWAYS.
9138 Error if Rd, Rn or Rm are R15. */
9143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9145 inst
.instruction
|= inst
.operands
[2].reg
;
9146 if (inst
.operands
[3].present
)
9147 encode_arm_shift (3);
9150 /* ARM V6 PKHTB (Argument Parse). */
9155 if (!inst
.operands
[3].present
)
9157 /* If the shift specifier is omitted, turn the instruction
9158 into pkhbt rd, rm, rn. */
9159 inst
.instruction
&= 0xfff00010;
9160 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9161 inst
.instruction
|= inst
.operands
[1].reg
;
9162 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9168 inst
.instruction
|= inst
.operands
[2].reg
;
9169 encode_arm_shift (3);
9173 /* ARMv5TE: Preload-Cache
9174 MP Extensions: Preload for write
9178 Syntactically, like LDR with B=1, W=0, L=1. */
9183 constraint (!inst
.operands
[0].isreg
,
9184 _("'[' expected after PLD mnemonic"));
9185 constraint (inst
.operands
[0].postind
,
9186 _("post-indexed expression used in preload instruction"));
9187 constraint (inst
.operands
[0].writeback
,
9188 _("writeback used in preload instruction"));
9189 constraint (!inst
.operands
[0].preind
,
9190 _("unindexed addressing used in preload instruction"));
9191 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9194 /* ARMv7: PLI <addr_mode> */
9198 constraint (!inst
.operands
[0].isreg
,
9199 _("'[' expected after PLI mnemonic"));
9200 constraint (inst
.operands
[0].postind
,
9201 _("post-indexed expression used in preload instruction"));
9202 constraint (inst
.operands
[0].writeback
,
9203 _("writeback used in preload instruction"));
9204 constraint (!inst
.operands
[0].preind
,
9205 _("unindexed addressing used in preload instruction"));
9206 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9207 inst
.instruction
&= ~PRE_INDEX
;
9213 constraint (inst
.operands
[0].writeback
,
9214 _("push/pop do not support {reglist}^"));
9215 inst
.operands
[1] = inst
.operands
[0];
9216 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9217 inst
.operands
[0].isreg
= 1;
9218 inst
.operands
[0].writeback
= 1;
9219 inst
.operands
[0].reg
= REG_SP
;
9220 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9223 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9224 word at the specified address and the following word
9226 Unconditionally executed.
9227 Error if Rn is R15. */
9232 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9233 if (inst
.operands
[0].writeback
)
9234 inst
.instruction
|= WRITE_BACK
;
9237 /* ARM V6 ssat (argument parse). */
9242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9243 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9244 inst
.instruction
|= inst
.operands
[2].reg
;
9246 if (inst
.operands
[3].present
)
9247 encode_arm_shift (3);
9250 /* ARM V6 usat (argument parse). */
9255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9256 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9257 inst
.instruction
|= inst
.operands
[2].reg
;
9259 if (inst
.operands
[3].present
)
9260 encode_arm_shift (3);
9263 /* ARM V6 ssat16 (argument parse). */
9268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9269 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9270 inst
.instruction
|= inst
.operands
[2].reg
;
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9277 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9278 inst
.instruction
|= inst
.operands
[2].reg
;
9281 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9282 preserving the other bits.
9284 setend <endian_specifier>, where <endian_specifier> is either
9290 if (warn_on_deprecated
9291 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9292 as_tsktsk (_("setend use is deprecated for ARMv8"));
9294 if (inst
.operands
[0].imm
)
9295 inst
.instruction
|= 0x200;
9301 unsigned int Rm
= (inst
.operands
[1].present
9302 ? inst
.operands
[1].reg
9303 : inst
.operands
[0].reg
);
9305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9306 inst
.instruction
|= Rm
;
9307 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9309 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9310 inst
.instruction
|= SHIFT_BY_REG
;
9311 /* PR 12854: Error on extraneous shifts. */
9312 constraint (inst
.operands
[2].shifted
,
9313 _("extraneous shift as part of operand to shift insn"));
9316 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9322 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9323 inst
.reloc
.pc_rel
= 0;
9329 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9330 inst
.reloc
.pc_rel
= 0;
9336 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9337 inst
.reloc
.pc_rel
= 0;
9343 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9344 _("selected processor does not support SETPAN instruction"));
9346 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9353 _("selected processor does not support SETPAN instruction"));
9355 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9358 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9359 SMLAxy{cond} Rd,Rm,Rs,Rn
9360 SMLAWy{cond} Rd,Rm,Rs,Rn
9361 Error if any register is R15. */
9366 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9367 inst
.instruction
|= inst
.operands
[1].reg
;
9368 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9369 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9372 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9373 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9374 Error if any register is R15.
9375 Warning if Rdlo == Rdhi. */
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9381 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9382 inst
.instruction
|= inst
.operands
[2].reg
;
9383 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9385 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9386 as_tsktsk (_("rdhi and rdlo must be different"));
9389 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9390 SMULxy{cond} Rd,Rm,Rs
9391 Error if any register is R15. */
9396 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9397 inst
.instruction
|= inst
.operands
[1].reg
;
9398 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9401 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9402 the same for both ARM and Thumb-2. */
9409 if (inst
.operands
[0].present
)
9411 reg
= inst
.operands
[0].reg
;
9412 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9417 inst
.instruction
|= reg
<< 16;
9418 inst
.instruction
|= inst
.operands
[1].imm
;
9419 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9420 inst
.instruction
|= WRITE_BACK
;
9423 /* ARM V6 strex (argument parse). */
9428 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9429 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9430 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9431 || inst
.operands
[2].negative
9432 /* See comment in do_ldrex(). */
9433 || (inst
.operands
[2].reg
== REG_PC
),
9436 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9437 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9439 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9440 || inst
.reloc
.exp
.X_add_number
!= 0,
9441 _("offset must be zero in ARM encoding"));
9443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9444 inst
.instruction
|= inst
.operands
[1].reg
;
9445 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9446 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9452 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9453 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9454 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9455 || inst
.operands
[2].negative
,
9458 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9459 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9467 constraint (inst
.operands
[1].reg
% 2 != 0,
9468 _("even register required"));
9469 constraint (inst
.operands
[2].present
9470 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9471 _("can only store two consecutive registers"));
9472 /* If op 2 were present and equal to PC, this function wouldn't
9473 have been called in the first place. */
9474 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9476 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9477 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9478 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9482 inst
.instruction
|= inst
.operands
[1].reg
;
9483 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9490 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9491 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9499 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9500 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9505 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9506 extends it to 32-bits, and adds the result to a value in another
9507 register. You can specify a rotation by 0, 8, 16, or 24 bits
9508 before extracting the 16-bit value.
9509 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9510 Condition defaults to COND_ALWAYS.
9511 Error if any register uses R15. */
9516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9517 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9518 inst
.instruction
|= inst
.operands
[2].reg
;
9519 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9524 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9525 Condition defaults to COND_ALWAYS.
9526 Error if any register uses R15. */
9531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9532 inst
.instruction
|= inst
.operands
[1].reg
;
9533 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9536 /* VFP instructions. In a logical order: SP variant first, monad
9537 before dyad, arithmetic then move then load/store. */
9540 do_vfp_sp_monadic (void)
9542 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9543 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9547 do_vfp_sp_dyadic (void)
9549 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9550 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9551 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9555 do_vfp_sp_compare_z (void)
9557 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9561 do_vfp_dp_sp_cvt (void)
9563 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9564 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9568 do_vfp_sp_dp_cvt (void)
9570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9571 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9575 do_vfp_reg_from_sp (void)
9577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9582 do_vfp_reg2_from_sp2 (void)
9584 constraint (inst
.operands
[2].imm
!= 2,
9585 _("only two consecutive VFP SP registers allowed here"));
9586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9587 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9588 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9592 do_vfp_sp_from_reg (void)
9594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9595 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9599 do_vfp_sp2_from_reg2 (void)
9601 constraint (inst
.operands
[0].imm
!= 2,
9602 _("only two consecutive VFP SP registers allowed here"));
9603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9604 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9605 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9609 do_vfp_sp_ldst (void)
9611 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9612 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9616 do_vfp_dp_ldst (void)
9618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9619 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9624 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9626 if (inst
.operands
[0].writeback
)
9627 inst
.instruction
|= WRITE_BACK
;
9629 constraint (ldstm_type
!= VFP_LDSTMIA
,
9630 _("this addressing mode requires base-register writeback"));
9631 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9632 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9633 inst
.instruction
|= inst
.operands
[1].imm
;
9637 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9641 if (inst
.operands
[0].writeback
)
9642 inst
.instruction
|= WRITE_BACK
;
9644 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9645 _("this addressing mode requires base-register writeback"));
9647 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9648 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9650 count
= inst
.operands
[1].imm
<< 1;
9651 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9654 inst
.instruction
|= count
;
9658 do_vfp_sp_ldstmia (void)
9660 vfp_sp_ldstm (VFP_LDSTMIA
);
9664 do_vfp_sp_ldstmdb (void)
9666 vfp_sp_ldstm (VFP_LDSTMDB
);
9670 do_vfp_dp_ldstmia (void)
9672 vfp_dp_ldstm (VFP_LDSTMIA
);
9676 do_vfp_dp_ldstmdb (void)
9678 vfp_dp_ldstm (VFP_LDSTMDB
);
9682 do_vfp_xp_ldstmia (void)
9684 vfp_dp_ldstm (VFP_LDSTMIAX
);
9688 do_vfp_xp_ldstmdb (void)
9690 vfp_dp_ldstm (VFP_LDSTMDBX
);
9694 do_vfp_dp_rd_rm (void)
9696 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9697 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9701 do_vfp_dp_rn_rd (void)
9703 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9704 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9708 do_vfp_dp_rd_rn (void)
9710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9711 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9715 do_vfp_dp_rd_rn_rm (void)
9717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9718 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9719 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9725 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9729 do_vfp_dp_rm_rd_rn (void)
9731 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9732 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9733 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9736 /* VFPv3 instructions. */
9738 do_vfp_sp_const (void)
9740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9741 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9742 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9746 do_vfp_dp_const (void)
9748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9749 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9750 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9754 vfp_conv (int srcsize
)
9756 int immbits
= srcsize
- inst
.operands
[1].imm
;
9758 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9760 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9761 i.e. immbits must be in range 0 - 16. */
9762 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9765 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9767 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9768 i.e. immbits must be in range 0 - 31. */
9769 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9773 inst
.instruction
|= (immbits
& 1) << 5;
9774 inst
.instruction
|= (immbits
>> 1);
9778 do_vfp_sp_conv_16 (void)
9780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9785 do_vfp_dp_conv_16 (void)
9787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9792 do_vfp_sp_conv_32 (void)
9794 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9799 do_vfp_dp_conv_32 (void)
9801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9805 /* FPA instructions. Also in a logical order. */
9810 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9811 inst
.instruction
|= inst
.operands
[1].reg
;
9815 do_fpa_ldmstm (void)
9817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9818 switch (inst
.operands
[1].imm
)
9820 case 1: inst
.instruction
|= CP_T_X
; break;
9821 case 2: inst
.instruction
|= CP_T_Y
; break;
9822 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9827 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9829 /* The instruction specified "ea" or "fd", so we can only accept
9830 [Rn]{!}. The instruction does not really support stacking or
9831 unstacking, so we have to emulate these by setting appropriate
9832 bits and offsets. */
9833 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9834 || inst
.reloc
.exp
.X_add_number
!= 0,
9835 _("this instruction does not support indexing"));
9837 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9838 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9840 if (!(inst
.instruction
& INDEX_UP
))
9841 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9843 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9845 inst
.operands
[2].preind
= 0;
9846 inst
.operands
[2].postind
= 1;
9850 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9853 /* iWMMXt instructions: strictly in alphabetical order. */
9856 do_iwmmxt_tandorc (void)
9858 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9862 do_iwmmxt_textrc (void)
9864 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9865 inst
.instruction
|= inst
.operands
[1].imm
;
9869 do_iwmmxt_textrm (void)
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9873 inst
.instruction
|= inst
.operands
[2].imm
;
9877 do_iwmmxt_tinsr (void)
9879 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9880 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9881 inst
.instruction
|= inst
.operands
[2].imm
;
9885 do_iwmmxt_tmia (void)
9887 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9888 inst
.instruction
|= inst
.operands
[1].reg
;
9889 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9893 do_iwmmxt_waligni (void)
9895 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9896 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9897 inst
.instruction
|= inst
.operands
[2].reg
;
9898 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9902 do_iwmmxt_wmerge (void)
9904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9905 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9906 inst
.instruction
|= inst
.operands
[2].reg
;
9907 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9911 do_iwmmxt_wmov (void)
9913 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9915 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9916 inst
.instruction
|= inst
.operands
[1].reg
;
9920 do_iwmmxt_wldstbh (void)
9923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9925 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9927 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9928 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9932 do_iwmmxt_wldstw (void)
9934 /* RIWR_RIWC clears .isreg for a control register. */
9935 if (!inst
.operands
[0].isreg
)
9937 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9938 inst
.instruction
|= 0xf0000000;
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9942 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9946 do_iwmmxt_wldstd (void)
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9950 && inst
.operands
[1].immisreg
)
9952 inst
.instruction
&= ~0x1a000ff;
9953 inst
.instruction
|= (0xf << 28);
9954 if (inst
.operands
[1].preind
)
9955 inst
.instruction
|= PRE_INDEX
;
9956 if (!inst
.operands
[1].negative
)
9957 inst
.instruction
|= INDEX_UP
;
9958 if (inst
.operands
[1].writeback
)
9959 inst
.instruction
|= WRITE_BACK
;
9960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9961 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9962 inst
.instruction
|= inst
.operands
[1].imm
;
9965 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9969 do_iwmmxt_wshufh (void)
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9972 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9973 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9974 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9978 do_iwmmxt_wzero (void)
9980 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9981 inst
.instruction
|= inst
.operands
[0].reg
;
9982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9983 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9987 do_iwmmxt_wrwrwr_or_imm5 (void)
9989 if (inst
.operands
[2].isreg
)
9992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9993 _("immediate operand requires iWMMXt2"));
9995 if (inst
.operands
[2].imm
== 0)
9997 switch ((inst
.instruction
>> 20) & 0xf)
10003 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10004 inst
.operands
[2].imm
= 16;
10005 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10011 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10012 inst
.operands
[2].imm
= 32;
10013 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10020 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10022 wrn
= (inst
.instruction
>> 16) & 0xf;
10023 inst
.instruction
&= 0xff0fff0f;
10024 inst
.instruction
|= wrn
;
10025 /* Bail out here; the instruction is now assembled. */
10030 /* Map 32 -> 0, etc. */
10031 inst
.operands
[2].imm
&= 0x1f;
10032 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10036 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10037 operations first, then control, shift, and load/store. */
10039 /* Insns like "foo X,Y,Z". */
10042 do_mav_triple (void)
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10045 inst
.instruction
|= inst
.operands
[1].reg
;
10046 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10049 /* Insns like "foo W,X,Y,Z".
10050 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10055 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10056 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10057 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10058 inst
.instruction
|= inst
.operands
[3].reg
;
10061 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10063 do_mav_dspsc (void)
10065 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10068 /* Maverick shift immediate instructions.
10069 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10070 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10073 do_mav_shift (void)
10075 int imm
= inst
.operands
[2].imm
;
10077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10078 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10080 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10081 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10082 Bit 4 should be 0. */
10083 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10085 inst
.instruction
|= imm
;
10088 /* XScale instructions. Also sorted arithmetic before move. */
10090 /* Xscale multiply-accumulate (argument parse)
10093 MIAxycc acc0,Rm,Rs. */
10098 inst
.instruction
|= inst
.operands
[1].reg
;
10099 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10102 /* Xscale move-accumulator-register (argument parse)
10104 MARcc acc0,RdLo,RdHi. */
10109 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10110 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10113 /* Xscale move-register-accumulator (argument parse)
10115 MRAcc RdLo,RdHi,acc0. */
10120 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10122 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10125 /* Encoding functions relevant only to Thumb. */
10127 /* inst.operands[i] is a shifted-register operand; encode
10128 it into inst.instruction in the format used by Thumb32. */
10131 encode_thumb32_shifted_operand (int i
)
10133 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10134 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10136 constraint (inst
.operands
[i
].immisreg
,
10137 _("shift by register not allowed in thumb mode"));
10138 inst
.instruction
|= inst
.operands
[i
].reg
;
10139 if (shift
== SHIFT_RRX
)
10140 inst
.instruction
|= SHIFT_ROR
<< 4;
10143 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10144 _("expression too complex"));
10146 constraint (value
> 32
10147 || (value
== 32 && (shift
== SHIFT_LSL
10148 || shift
== SHIFT_ROR
)),
10149 _("shift expression is too large"));
10153 else if (value
== 32)
10156 inst
.instruction
|= shift
<< 4;
10157 inst
.instruction
|= (value
& 0x1c) << 10;
10158 inst
.instruction
|= (value
& 0x03) << 6;
10163 /* inst.operands[i] was set up by parse_address. Encode it into a
10164 Thumb32 format load or store instruction. Reject forms that cannot
10165 be used with such instructions. If is_t is true, reject forms that
10166 cannot be used with a T instruction; if is_d is true, reject forms
10167 that cannot be used with a D instruction. If it is a store insn,
10168 reject PC in Rn. */
10171 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10173 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10175 constraint (!inst
.operands
[i
].isreg
,
10176 _("Instruction does not support =N addresses"));
10178 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10179 if (inst
.operands
[i
].immisreg
)
10181 constraint (is_pc
, BAD_PC_ADDRESSING
);
10182 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10183 constraint (inst
.operands
[i
].negative
,
10184 _("Thumb does not support negative register indexing"));
10185 constraint (inst
.operands
[i
].postind
,
10186 _("Thumb does not support register post-indexing"));
10187 constraint (inst
.operands
[i
].writeback
,
10188 _("Thumb does not support register indexing with writeback"));
10189 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10190 _("Thumb supports only LSL in shifted register indexing"));
10192 inst
.instruction
|= inst
.operands
[i
].imm
;
10193 if (inst
.operands
[i
].shifted
)
10195 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10196 _("expression too complex"));
10197 constraint (inst
.reloc
.exp
.X_add_number
< 0
10198 || inst
.reloc
.exp
.X_add_number
> 3,
10199 _("shift out of range"));
10200 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10202 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10204 else if (inst
.operands
[i
].preind
)
10206 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10207 constraint (is_t
&& inst
.operands
[i
].writeback
,
10208 _("cannot use writeback with this instruction"));
10209 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10210 BAD_PC_ADDRESSING
);
10214 inst
.instruction
|= 0x01000000;
10215 if (inst
.operands
[i
].writeback
)
10216 inst
.instruction
|= 0x00200000;
10220 inst
.instruction
|= 0x00000c00;
10221 if (inst
.operands
[i
].writeback
)
10222 inst
.instruction
|= 0x00000100;
10224 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10226 else if (inst
.operands
[i
].postind
)
10228 gas_assert (inst
.operands
[i
].writeback
);
10229 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10230 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10233 inst
.instruction
|= 0x00200000;
10235 inst
.instruction
|= 0x00000900;
10236 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10238 else /* unindexed - only for coprocessor */
10239 inst
.error
= _("instruction does not accept unindexed addressing");
10242 /* Table of Thumb instructions which exist in both 16- and 32-bit
10243 encodings (the latter only in post-V6T2 cores). The index is the
10244 value used in the insns table below. When there is more than one
10245 possible 16-bit encoding for the instruction, this table always
10247 Also contains several pseudo-instructions used during relaxation. */
10248 #define T16_32_TAB \
10249 X(_adc, 4140, eb400000), \
10250 X(_adcs, 4140, eb500000), \
10251 X(_add, 1c00, eb000000), \
10252 X(_adds, 1c00, eb100000), \
10253 X(_addi, 0000, f1000000), \
10254 X(_addis, 0000, f1100000), \
10255 X(_add_pc,000f, f20f0000), \
10256 X(_add_sp,000d, f10d0000), \
10257 X(_adr, 000f, f20f0000), \
10258 X(_and, 4000, ea000000), \
10259 X(_ands, 4000, ea100000), \
10260 X(_asr, 1000, fa40f000), \
10261 X(_asrs, 1000, fa50f000), \
10262 X(_b, e000, f000b000), \
10263 X(_bcond, d000, f0008000), \
10264 X(_bic, 4380, ea200000), \
10265 X(_bics, 4380, ea300000), \
10266 X(_cmn, 42c0, eb100f00), \
10267 X(_cmp, 2800, ebb00f00), \
10268 X(_cpsie, b660, f3af8400), \
10269 X(_cpsid, b670, f3af8600), \
10270 X(_cpy, 4600, ea4f0000), \
10271 X(_dec_sp,80dd, f1ad0d00), \
10272 X(_eor, 4040, ea800000), \
10273 X(_eors, 4040, ea900000), \
10274 X(_inc_sp,00dd, f10d0d00), \
10275 X(_ldmia, c800, e8900000), \
10276 X(_ldr, 6800, f8500000), \
10277 X(_ldrb, 7800, f8100000), \
10278 X(_ldrh, 8800, f8300000), \
10279 X(_ldrsb, 5600, f9100000), \
10280 X(_ldrsh, 5e00, f9300000), \
10281 X(_ldr_pc,4800, f85f0000), \
10282 X(_ldr_pc2,4800, f85f0000), \
10283 X(_ldr_sp,9800, f85d0000), \
10284 X(_lsl, 0000, fa00f000), \
10285 X(_lsls, 0000, fa10f000), \
10286 X(_lsr, 0800, fa20f000), \
10287 X(_lsrs, 0800, fa30f000), \
10288 X(_mov, 2000, ea4f0000), \
10289 X(_movs, 2000, ea5f0000), \
10290 X(_mul, 4340, fb00f000), \
10291 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10292 X(_mvn, 43c0, ea6f0000), \
10293 X(_mvns, 43c0, ea7f0000), \
10294 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10295 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10296 X(_orr, 4300, ea400000), \
10297 X(_orrs, 4300, ea500000), \
10298 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10299 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10300 X(_rev, ba00, fa90f080), \
10301 X(_rev16, ba40, fa90f090), \
10302 X(_revsh, bac0, fa90f0b0), \
10303 X(_ror, 41c0, fa60f000), \
10304 X(_rors, 41c0, fa70f000), \
10305 X(_sbc, 4180, eb600000), \
10306 X(_sbcs, 4180, eb700000), \
10307 X(_stmia, c000, e8800000), \
10308 X(_str, 6000, f8400000), \
10309 X(_strb, 7000, f8000000), \
10310 X(_strh, 8000, f8200000), \
10311 X(_str_sp,9000, f84d0000), \
10312 X(_sub, 1e00, eba00000), \
10313 X(_subs, 1e00, ebb00000), \
10314 X(_subi, 8000, f1a00000), \
10315 X(_subis, 8000, f1b00000), \
10316 X(_sxtb, b240, fa4ff080), \
10317 X(_sxth, b200, fa0ff080), \
10318 X(_tst, 4200, ea100f00), \
10319 X(_uxtb, b2c0, fa5ff080), \
10320 X(_uxth, b280, fa1ff080), \
10321 X(_nop, bf00, f3af8000), \
10322 X(_yield, bf10, f3af8001), \
10323 X(_wfe, bf20, f3af8002), \
10324 X(_wfi, bf30, f3af8003), \
10325 X(_sev, bf40, f3af8004), \
10326 X(_sevl, bf50, f3af8005), \
10327 X(_udf, de00, f7f0a000)
10329 /* To catch errors in encoding functions, the codes are all offset by
10330 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10331 as 16-bit instructions. */
10332 #define X(a,b,c) T_MNEM##a
10333 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10336 #define X(a,b,c) 0x##b
10337 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10338 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10341 #define X(a,b,c) 0x##c
10342 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10343 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10344 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10348 /* Thumb instruction encoders, in alphabetical order. */
10350 /* ADDW or SUBW. */
10353 do_t_add_sub_w (void)
10357 Rd
= inst
.operands
[0].reg
;
10358 Rn
= inst
.operands
[1].reg
;
10360 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10361 is the SP-{plus,minus}-immediate form of the instruction. */
10363 constraint (Rd
== REG_PC
, BAD_PC
);
10365 reject_bad_reg (Rd
);
10367 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10368 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10371 /* Parse an add or subtract instruction. We get here with inst.instruction
10372 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10375 do_t_add_sub (void)
10379 Rd
= inst
.operands
[0].reg
;
10380 Rs
= (inst
.operands
[1].present
10381 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10382 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10385 set_it_insn_type_last ();
10387 if (unified_syntax
)
10390 bfd_boolean narrow
;
10393 flags
= (inst
.instruction
== T_MNEM_adds
10394 || inst
.instruction
== T_MNEM_subs
);
10396 narrow
= !in_it_block ();
10398 narrow
= in_it_block ();
10399 if (!inst
.operands
[2].isreg
)
10403 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10405 add
= (inst
.instruction
== T_MNEM_add
10406 || inst
.instruction
== T_MNEM_adds
);
10408 if (inst
.size_req
!= 4)
10410 /* Attempt to use a narrow opcode, with relaxation if
10412 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10413 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10414 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10415 opcode
= T_MNEM_add_sp
;
10416 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10417 opcode
= T_MNEM_add_pc
;
10418 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10421 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10423 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10427 inst
.instruction
= THUMB_OP16(opcode
);
10428 inst
.instruction
|= (Rd
<< 4) | Rs
;
10429 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10430 if (inst
.size_req
!= 2)
10431 inst
.relax
= opcode
;
10434 constraint (inst
.size_req
== 2, BAD_HIREG
);
10436 if (inst
.size_req
== 4
10437 || (inst
.size_req
!= 2 && !opcode
))
10441 constraint (add
, BAD_PC
);
10442 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10443 _("only SUBS PC, LR, #const allowed"));
10444 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10445 _("expression too complex"));
10446 constraint (inst
.reloc
.exp
.X_add_number
< 0
10447 || inst
.reloc
.exp
.X_add_number
> 0xff,
10448 _("immediate value out of range"));
10449 inst
.instruction
= T2_SUBS_PC_LR
10450 | inst
.reloc
.exp
.X_add_number
;
10451 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10454 else if (Rs
== REG_PC
)
10456 /* Always use addw/subw. */
10457 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10458 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10462 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10463 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10466 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10468 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10470 inst
.instruction
|= Rd
<< 8;
10471 inst
.instruction
|= Rs
<< 16;
10476 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10477 unsigned int shift
= inst
.operands
[2].shift_kind
;
10479 Rn
= inst
.operands
[2].reg
;
10480 /* See if we can do this with a 16-bit instruction. */
10481 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10483 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10488 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10489 || inst
.instruction
== T_MNEM_add
)
10491 : T_OPCODE_SUB_R3
);
10492 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10496 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10498 /* Thumb-1 cores (except v6-M) require at least one high
10499 register in a narrow non flag setting add. */
10500 if (Rd
> 7 || Rn
> 7
10501 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10502 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10509 inst
.instruction
= T_OPCODE_ADD_HI
;
10510 inst
.instruction
|= (Rd
& 8) << 4;
10511 inst
.instruction
|= (Rd
& 7);
10512 inst
.instruction
|= Rn
<< 3;
10518 constraint (Rd
== REG_PC
, BAD_PC
);
10519 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10520 constraint (Rs
== REG_PC
, BAD_PC
);
10521 reject_bad_reg (Rn
);
10523 /* If we get here, it can't be done in 16 bits. */
10524 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10525 _("shift must be constant"));
10526 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10527 inst
.instruction
|= Rd
<< 8;
10528 inst
.instruction
|= Rs
<< 16;
10529 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10530 _("shift value over 3 not allowed in thumb mode"));
10531 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10532 _("only LSL shift allowed in thumb mode"));
10533 encode_thumb32_shifted_operand (2);
10538 constraint (inst
.instruction
== T_MNEM_adds
10539 || inst
.instruction
== T_MNEM_subs
,
10542 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10544 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10545 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10548 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10549 ? 0x0000 : 0x8000);
10550 inst
.instruction
|= (Rd
<< 4) | Rs
;
10551 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10555 Rn
= inst
.operands
[2].reg
;
10556 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10558 /* We now have Rd, Rs, and Rn set to registers. */
10559 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10561 /* Can't do this for SUB. */
10562 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10563 inst
.instruction
= T_OPCODE_ADD_HI
;
10564 inst
.instruction
|= (Rd
& 8) << 4;
10565 inst
.instruction
|= (Rd
& 7);
10567 inst
.instruction
|= Rn
<< 3;
10569 inst
.instruction
|= Rs
<< 3;
10571 constraint (1, _("dest must overlap one source register"));
10575 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10576 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10577 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10587 Rd
= inst
.operands
[0].reg
;
10588 reject_bad_reg (Rd
);
10590 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10592 /* Defer to section relaxation. */
10593 inst
.relax
= inst
.instruction
;
10594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10595 inst
.instruction
|= Rd
<< 4;
10597 else if (unified_syntax
&& inst
.size_req
!= 2)
10599 /* Generate a 32-bit opcode. */
10600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10601 inst
.instruction
|= Rd
<< 8;
10602 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10603 inst
.reloc
.pc_rel
= 1;
10607 /* Generate a 16-bit opcode. */
10608 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10609 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10610 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10611 inst
.reloc
.pc_rel
= 1;
10613 inst
.instruction
|= Rd
<< 4;
10617 /* Arithmetic instructions for which there is just one 16-bit
10618 instruction encoding, and it allows only two low registers.
10619 For maximal compatibility with ARM syntax, we allow three register
10620 operands even when Thumb-32 instructions are not available, as long
10621 as the first two are identical. For instance, both "sbc r0,r1" and
10622 "sbc r0,r0,r1" are allowed. */
10628 Rd
= inst
.operands
[0].reg
;
10629 Rs
= (inst
.operands
[1].present
10630 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10631 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10632 Rn
= inst
.operands
[2].reg
;
10634 reject_bad_reg (Rd
);
10635 reject_bad_reg (Rs
);
10636 if (inst
.operands
[2].isreg
)
10637 reject_bad_reg (Rn
);
10639 if (unified_syntax
)
10641 if (!inst
.operands
[2].isreg
)
10643 /* For an immediate, we always generate a 32-bit opcode;
10644 section relaxation will shrink it later if possible. */
10645 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10646 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10647 inst
.instruction
|= Rd
<< 8;
10648 inst
.instruction
|= Rs
<< 16;
10649 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10653 bfd_boolean narrow
;
10655 /* See if we can do this with a 16-bit instruction. */
10656 if (THUMB_SETS_FLAGS (inst
.instruction
))
10657 narrow
= !in_it_block ();
10659 narrow
= in_it_block ();
10661 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10663 if (inst
.operands
[2].shifted
)
10665 if (inst
.size_req
== 4)
10671 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10672 inst
.instruction
|= Rd
;
10673 inst
.instruction
|= Rn
<< 3;
10677 /* If we get here, it can't be done in 16 bits. */
10678 constraint (inst
.operands
[2].shifted
10679 && inst
.operands
[2].immisreg
,
10680 _("shift must be constant"));
10681 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10682 inst
.instruction
|= Rd
<< 8;
10683 inst
.instruction
|= Rs
<< 16;
10684 encode_thumb32_shifted_operand (2);
10689 /* On its face this is a lie - the instruction does set the
10690 flags. However, the only supported mnemonic in this mode
10691 says it doesn't. */
10692 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10694 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10695 _("unshifted register required"));
10696 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10697 constraint (Rd
!= Rs
,
10698 _("dest and source1 must be the same register"));
10700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10701 inst
.instruction
|= Rd
;
10702 inst
.instruction
|= Rn
<< 3;
10706 /* Similarly, but for instructions where the arithmetic operation is
10707 commutative, so we can allow either of them to be different from
10708 the destination operand in a 16-bit instruction. For instance, all
10709 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10716 Rd
= inst
.operands
[0].reg
;
10717 Rs
= (inst
.operands
[1].present
10718 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10719 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10720 Rn
= inst
.operands
[2].reg
;
10722 reject_bad_reg (Rd
);
10723 reject_bad_reg (Rs
);
10724 if (inst
.operands
[2].isreg
)
10725 reject_bad_reg (Rn
);
10727 if (unified_syntax
)
10729 if (!inst
.operands
[2].isreg
)
10731 /* For an immediate, we always generate a 32-bit opcode;
10732 section relaxation will shrink it later if possible. */
10733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10734 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10735 inst
.instruction
|= Rd
<< 8;
10736 inst
.instruction
|= Rs
<< 16;
10737 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10741 bfd_boolean narrow
;
10743 /* See if we can do this with a 16-bit instruction. */
10744 if (THUMB_SETS_FLAGS (inst
.instruction
))
10745 narrow
= !in_it_block ();
10747 narrow
= in_it_block ();
10749 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10751 if (inst
.operands
[2].shifted
)
10753 if (inst
.size_req
== 4)
10760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10761 inst
.instruction
|= Rd
;
10762 inst
.instruction
|= Rn
<< 3;
10767 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10768 inst
.instruction
|= Rd
;
10769 inst
.instruction
|= Rs
<< 3;
10774 /* If we get here, it can't be done in 16 bits. */
10775 constraint (inst
.operands
[2].shifted
10776 && inst
.operands
[2].immisreg
,
10777 _("shift must be constant"));
10778 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10779 inst
.instruction
|= Rd
<< 8;
10780 inst
.instruction
|= Rs
<< 16;
10781 encode_thumb32_shifted_operand (2);
10786 /* On its face this is a lie - the instruction does set the
10787 flags. However, the only supported mnemonic in this mode
10788 says it doesn't. */
10789 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10791 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10792 _("unshifted register required"));
10793 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10796 inst
.instruction
|= Rd
;
10799 inst
.instruction
|= Rn
<< 3;
10801 inst
.instruction
|= Rs
<< 3;
10803 constraint (1, _("dest must overlap one source register"));
10811 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10812 constraint (msb
> 32, _("bit-field extends past end of register"));
10813 /* The instruction encoding stores the LSB and MSB,
10814 not the LSB and width. */
10815 Rd
= inst
.operands
[0].reg
;
10816 reject_bad_reg (Rd
);
10817 inst
.instruction
|= Rd
<< 8;
10818 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10819 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10820 inst
.instruction
|= msb
- 1;
10829 Rd
= inst
.operands
[0].reg
;
10830 reject_bad_reg (Rd
);
10832 /* #0 in second position is alternative syntax for bfc, which is
10833 the same instruction but with REG_PC in the Rm field. */
10834 if (!inst
.operands
[1].isreg
)
10838 Rn
= inst
.operands
[1].reg
;
10839 reject_bad_reg (Rn
);
10842 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10843 constraint (msb
> 32, _("bit-field extends past end of register"));
10844 /* The instruction encoding stores the LSB and MSB,
10845 not the LSB and width. */
10846 inst
.instruction
|= Rd
<< 8;
10847 inst
.instruction
|= Rn
<< 16;
10848 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10849 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10850 inst
.instruction
|= msb
- 1;
10858 Rd
= inst
.operands
[0].reg
;
10859 Rn
= inst
.operands
[1].reg
;
10861 reject_bad_reg (Rd
);
10862 reject_bad_reg (Rn
);
10864 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10865 _("bit-field extends past end of register"));
10866 inst
.instruction
|= Rd
<< 8;
10867 inst
.instruction
|= Rn
<< 16;
10868 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10869 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10870 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10873 /* ARM V5 Thumb BLX (argument parse)
10874 BLX <target_addr> which is BLX(1)
10875 BLX <Rm> which is BLX(2)
10876 Unfortunately, there are two different opcodes for this mnemonic.
10877 So, the insns[].value is not used, and the code here zaps values
10878 into inst.instruction.
10880 ??? How to take advantage of the additional two bits of displacement
10881 available in Thumb32 mode? Need new relocation? */
10886 set_it_insn_type_last ();
10888 if (inst
.operands
[0].isreg
)
10890 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10891 /* We have a register, so this is BLX(2). */
10892 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10896 /* No register. This must be BLX(1). */
10897 inst
.instruction
= 0xf000e800;
10898 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10910 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10912 if (in_it_block ())
10914 /* Conditional branches inside IT blocks are encoded as unconditional
10916 cond
= COND_ALWAYS
;
10921 if (cond
!= COND_ALWAYS
)
10922 opcode
= T_MNEM_bcond
;
10924 opcode
= inst
.instruction
;
10927 && (inst
.size_req
== 4
10928 || (inst
.size_req
!= 2
10929 && (inst
.operands
[0].hasreloc
10930 || inst
.reloc
.exp
.X_op
== O_constant
))))
10932 inst
.instruction
= THUMB_OP32(opcode
);
10933 if (cond
== COND_ALWAYS
)
10934 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10937 gas_assert (cond
!= 0xF);
10938 inst
.instruction
|= cond
<< 22;
10939 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10944 inst
.instruction
= THUMB_OP16(opcode
);
10945 if (cond
== COND_ALWAYS
)
10946 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10949 inst
.instruction
|= cond
<< 8;
10950 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10952 /* Allow section relaxation. */
10953 if (unified_syntax
&& inst
.size_req
!= 2)
10954 inst
.relax
= opcode
;
10956 inst
.reloc
.type
= reloc
;
10957 inst
.reloc
.pc_rel
= 1;
10960 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10961 between the two is the maximum immediate allowed - which is passed in
10964 do_t_bkpt_hlt1 (int range
)
10966 constraint (inst
.cond
!= COND_ALWAYS
,
10967 _("instruction is always unconditional"));
10968 if (inst
.operands
[0].present
)
10970 constraint (inst
.operands
[0].imm
> range
,
10971 _("immediate value out of range"));
10972 inst
.instruction
|= inst
.operands
[0].imm
;
10975 set_it_insn_type (NEUTRAL_IT_INSN
);
10981 do_t_bkpt_hlt1 (63);
10987 do_t_bkpt_hlt1 (255);
10991 do_t_branch23 (void)
10993 set_it_insn_type_last ();
10994 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10996 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10997 this file. We used to simply ignore the PLT reloc type here --
10998 the branch encoding is now needed to deal with TLSCALL relocs.
10999 So if we see a PLT reloc now, put it back to how it used to be to
11000 keep the preexisting behaviour. */
11001 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11002 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11004 #if defined(OBJ_COFF)
11005 /* If the destination of the branch is a defined symbol which does not have
11006 the THUMB_FUNC attribute, then we must be calling a function which has
11007 the (interfacearm) attribute. We look for the Thumb entry point to that
11008 function and change the branch to refer to that function instead. */
11009 if ( inst
.reloc
.exp
.X_op
== O_symbol
11010 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11011 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11012 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11013 inst
.reloc
.exp
.X_add_symbol
=
11014 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11021 set_it_insn_type_last ();
11022 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11023 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11024 should cause the alignment to be checked once it is known. This is
11025 because BX PC only works if the instruction is word aligned. */
11033 set_it_insn_type_last ();
11034 Rm
= inst
.operands
[0].reg
;
11035 reject_bad_reg (Rm
);
11036 inst
.instruction
|= Rm
<< 16;
11045 Rd
= inst
.operands
[0].reg
;
11046 Rm
= inst
.operands
[1].reg
;
11048 reject_bad_reg (Rd
);
11049 reject_bad_reg (Rm
);
11051 inst
.instruction
|= Rd
<< 8;
11052 inst
.instruction
|= Rm
<< 16;
11053 inst
.instruction
|= Rm
;
11059 set_it_insn_type (OUTSIDE_IT_INSN
);
11060 inst
.instruction
|= inst
.operands
[0].imm
;
11066 set_it_insn_type (OUTSIDE_IT_INSN
);
11068 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11069 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11071 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11072 inst
.instruction
= 0xf3af8000;
11073 inst
.instruction
|= imod
<< 9;
11074 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11075 if (inst
.operands
[1].present
)
11076 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11080 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11081 && (inst
.operands
[0].imm
& 4),
11082 _("selected processor does not support 'A' form "
11083 "of this instruction"));
11084 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11085 _("Thumb does not support the 2-argument "
11086 "form of this instruction"));
11087 inst
.instruction
|= inst
.operands
[0].imm
;
11091 /* THUMB CPY instruction (argument parse). */
11096 if (inst
.size_req
== 4)
11098 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11099 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11100 inst
.instruction
|= inst
.operands
[1].reg
;
11104 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11105 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11106 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11113 set_it_insn_type (OUTSIDE_IT_INSN
);
11114 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11115 inst
.instruction
|= inst
.operands
[0].reg
;
11116 inst
.reloc
.pc_rel
= 1;
11117 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11123 inst
.instruction
|= inst
.operands
[0].imm
;
11129 unsigned Rd
, Rn
, Rm
;
11131 Rd
= inst
.operands
[0].reg
;
11132 Rn
= (inst
.operands
[1].present
11133 ? inst
.operands
[1].reg
: Rd
);
11134 Rm
= inst
.operands
[2].reg
;
11136 reject_bad_reg (Rd
);
11137 reject_bad_reg (Rn
);
11138 reject_bad_reg (Rm
);
11140 inst
.instruction
|= Rd
<< 8;
11141 inst
.instruction
|= Rn
<< 16;
11142 inst
.instruction
|= Rm
;
11148 if (unified_syntax
&& inst
.size_req
== 4)
11149 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11151 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11157 unsigned int cond
= inst
.operands
[0].imm
;
11159 set_it_insn_type (IT_INSN
);
11160 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11162 now_it
.warn_deprecated
= FALSE
;
11164 /* If the condition is a negative condition, invert the mask. */
11165 if ((cond
& 0x1) == 0x0)
11167 unsigned int mask
= inst
.instruction
& 0x000f;
11169 if ((mask
& 0x7) == 0)
11171 /* No conversion needed. */
11172 now_it
.block_length
= 1;
11174 else if ((mask
& 0x3) == 0)
11177 now_it
.block_length
= 2;
11179 else if ((mask
& 0x1) == 0)
11182 now_it
.block_length
= 3;
11187 now_it
.block_length
= 4;
11190 inst
.instruction
&= 0xfff0;
11191 inst
.instruction
|= mask
;
11194 inst
.instruction
|= cond
<< 4;
11197 /* Helper function used for both push/pop and ldm/stm. */
11199 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11203 load
= (inst
.instruction
& (1 << 20)) != 0;
11205 if (mask
& (1 << 13))
11206 inst
.error
= _("SP not allowed in register list");
11208 if ((mask
& (1 << base
)) != 0
11210 inst
.error
= _("having the base register in the register list when "
11211 "using write back is UNPREDICTABLE");
11215 if (mask
& (1 << 15))
11217 if (mask
& (1 << 14))
11218 inst
.error
= _("LR and PC should not both be in register list");
11220 set_it_insn_type_last ();
11225 if (mask
& (1 << 15))
11226 inst
.error
= _("PC not allowed in register list");
11229 if ((mask
& (mask
- 1)) == 0)
11231 /* Single register transfers implemented as str/ldr. */
11234 if (inst
.instruction
& (1 << 23))
11235 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11237 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11241 if (inst
.instruction
& (1 << 23))
11242 inst
.instruction
= 0x00800000; /* ia -> [base] */
11244 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11247 inst
.instruction
|= 0xf8400000;
11249 inst
.instruction
|= 0x00100000;
11251 mask
= ffs (mask
) - 1;
11254 else if (writeback
)
11255 inst
.instruction
|= WRITE_BACK
;
11257 inst
.instruction
|= mask
;
11258 inst
.instruction
|= base
<< 16;
11264 /* This really doesn't seem worth it. */
11265 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11266 _("expression too complex"));
11267 constraint (inst
.operands
[1].writeback
,
11268 _("Thumb load/store multiple does not support {reglist}^"));
11270 if (unified_syntax
)
11272 bfd_boolean narrow
;
11276 /* See if we can use a 16-bit instruction. */
11277 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11278 && inst
.size_req
!= 4
11279 && !(inst
.operands
[1].imm
& ~0xff))
11281 mask
= 1 << inst
.operands
[0].reg
;
11283 if (inst
.operands
[0].reg
<= 7)
11285 if (inst
.instruction
== T_MNEM_stmia
11286 ? inst
.operands
[0].writeback
11287 : (inst
.operands
[0].writeback
11288 == !(inst
.operands
[1].imm
& mask
)))
11290 if (inst
.instruction
== T_MNEM_stmia
11291 && (inst
.operands
[1].imm
& mask
)
11292 && (inst
.operands
[1].imm
& (mask
- 1)))
11293 as_warn (_("value stored for r%d is UNKNOWN"),
11294 inst
.operands
[0].reg
);
11296 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11297 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11298 inst
.instruction
|= inst
.operands
[1].imm
;
11301 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11303 /* This means 1 register in reg list one of 3 situations:
11304 1. Instruction is stmia, but without writeback.
11305 2. lmdia without writeback, but with Rn not in
11307 3. ldmia with writeback, but with Rn in reglist.
11308 Case 3 is UNPREDICTABLE behaviour, so we handle
11309 case 1 and 2 which can be converted into a 16-bit
11310 str or ldr. The SP cases are handled below. */
11311 unsigned long opcode
;
11312 /* First, record an error for Case 3. */
11313 if (inst
.operands
[1].imm
& mask
11314 && inst
.operands
[0].writeback
)
11316 _("having the base register in the register list when "
11317 "using write back is UNPREDICTABLE");
11319 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11321 inst
.instruction
= THUMB_OP16 (opcode
);
11322 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11323 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11327 else if (inst
.operands
[0] .reg
== REG_SP
)
11329 if (inst
.operands
[0].writeback
)
11332 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11333 ? T_MNEM_push
: T_MNEM_pop
);
11334 inst
.instruction
|= inst
.operands
[1].imm
;
11337 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11340 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11341 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11342 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11350 if (inst
.instruction
< 0xffff)
11351 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11353 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11354 inst
.operands
[0].writeback
);
11359 constraint (inst
.operands
[0].reg
> 7
11360 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11361 constraint (inst
.instruction
!= T_MNEM_ldmia
11362 && inst
.instruction
!= T_MNEM_stmia
,
11363 _("Thumb-2 instruction only valid in unified syntax"));
11364 if (inst
.instruction
== T_MNEM_stmia
)
11366 if (!inst
.operands
[0].writeback
)
11367 as_warn (_("this instruction will write back the base register"));
11368 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11369 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11370 as_warn (_("value stored for r%d is UNKNOWN"),
11371 inst
.operands
[0].reg
);
11375 if (!inst
.operands
[0].writeback
11376 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11377 as_warn (_("this instruction will write back the base register"));
11378 else if (inst
.operands
[0].writeback
11379 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11380 as_warn (_("this instruction will not write back the base register"));
11383 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11384 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11385 inst
.instruction
|= inst
.operands
[1].imm
;
11392 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11393 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11394 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11395 || inst
.operands
[1].negative
,
11398 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11401 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11402 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11408 if (!inst
.operands
[1].present
)
11410 constraint (inst
.operands
[0].reg
== REG_LR
,
11411 _("r14 not allowed as first register "
11412 "when second register is omitted"));
11413 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11415 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11418 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11419 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11420 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11426 unsigned long opcode
;
11429 if (inst
.operands
[0].isreg
11430 && !inst
.operands
[0].preind
11431 && inst
.operands
[0].reg
== REG_PC
)
11432 set_it_insn_type_last ();
11434 opcode
= inst
.instruction
;
11435 if (unified_syntax
)
11437 if (!inst
.operands
[1].isreg
)
11439 if (opcode
<= 0xffff)
11440 inst
.instruction
= THUMB_OP32 (opcode
);
11441 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11444 if (inst
.operands
[1].isreg
11445 && !inst
.operands
[1].writeback
11446 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11447 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11448 && opcode
<= 0xffff
11449 && inst
.size_req
!= 4)
11451 /* Insn may have a 16-bit form. */
11452 Rn
= inst
.operands
[1].reg
;
11453 if (inst
.operands
[1].immisreg
)
11455 inst
.instruction
= THUMB_OP16 (opcode
);
11457 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11459 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11460 reject_bad_reg (inst
.operands
[1].imm
);
11462 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11463 && opcode
!= T_MNEM_ldrsb
)
11464 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11465 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11472 if (inst
.reloc
.pc_rel
)
11473 opcode
= T_MNEM_ldr_pc2
;
11475 opcode
= T_MNEM_ldr_pc
;
11479 if (opcode
== T_MNEM_ldr
)
11480 opcode
= T_MNEM_ldr_sp
;
11482 opcode
= T_MNEM_str_sp
;
11484 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11488 inst
.instruction
= inst
.operands
[0].reg
;
11489 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11491 inst
.instruction
|= THUMB_OP16 (opcode
);
11492 if (inst
.size_req
== 2)
11493 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11495 inst
.relax
= opcode
;
11499 /* Definitely a 32-bit variant. */
11501 /* Warning for Erratum 752419. */
11502 if (opcode
== T_MNEM_ldr
11503 && inst
.operands
[0].reg
== REG_SP
11504 && inst
.operands
[1].writeback
== 1
11505 && !inst
.operands
[1].immisreg
)
11507 if (no_cpu_selected ()
11508 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11509 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11510 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11511 as_warn (_("This instruction may be unpredictable "
11512 "if executed on M-profile cores "
11513 "with interrupts enabled."));
11516 /* Do some validations regarding addressing modes. */
11517 if (inst
.operands
[1].immisreg
)
11518 reject_bad_reg (inst
.operands
[1].imm
);
11520 constraint (inst
.operands
[1].writeback
== 1
11521 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11524 inst
.instruction
= THUMB_OP32 (opcode
);
11525 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11526 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11527 check_ldr_r15_aligned ();
11531 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11533 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11535 /* Only [Rn,Rm] is acceptable. */
11536 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11537 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11538 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11539 || inst
.operands
[1].negative
,
11540 _("Thumb does not support this addressing mode"));
11541 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11546 if (!inst
.operands
[1].isreg
)
11547 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11550 constraint (!inst
.operands
[1].preind
11551 || inst
.operands
[1].shifted
11552 || inst
.operands
[1].writeback
,
11553 _("Thumb does not support this addressing mode"));
11554 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11556 constraint (inst
.instruction
& 0x0600,
11557 _("byte or halfword not valid for base register"));
11558 constraint (inst
.operands
[1].reg
== REG_PC
11559 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11560 _("r15 based store not allowed"));
11561 constraint (inst
.operands
[1].immisreg
,
11562 _("invalid base register for register offset"));
11564 if (inst
.operands
[1].reg
== REG_PC
)
11565 inst
.instruction
= T_OPCODE_LDR_PC
;
11566 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11567 inst
.instruction
= T_OPCODE_LDR_SP
;
11569 inst
.instruction
= T_OPCODE_STR_SP
;
11571 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11572 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11576 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11577 if (!inst
.operands
[1].immisreg
)
11579 /* Immediate offset. */
11580 inst
.instruction
|= inst
.operands
[0].reg
;
11581 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11582 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11586 /* Register offset. */
11587 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11588 constraint (inst
.operands
[1].negative
,
11589 _("Thumb does not support this addressing mode"));
11592 switch (inst
.instruction
)
11594 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11595 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11596 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11597 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11598 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11599 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11600 case 0x5600 /* ldrsb */:
11601 case 0x5e00 /* ldrsh */: break;
11605 inst
.instruction
|= inst
.operands
[0].reg
;
11606 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11607 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11613 if (!inst
.operands
[1].present
)
11615 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11616 constraint (inst
.operands
[0].reg
== REG_LR
,
11617 _("r14 not allowed here"));
11618 constraint (inst
.operands
[0].reg
== REG_R12
,
11619 _("r12 not allowed here"));
11622 if (inst
.operands
[2].writeback
11623 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11624 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11625 as_warn (_("base register written back, and overlaps "
11626 "one of transfer registers"));
11628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11629 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11630 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11636 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11637 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11643 unsigned Rd
, Rn
, Rm
, Ra
;
11645 Rd
= inst
.operands
[0].reg
;
11646 Rn
= inst
.operands
[1].reg
;
11647 Rm
= inst
.operands
[2].reg
;
11648 Ra
= inst
.operands
[3].reg
;
11650 reject_bad_reg (Rd
);
11651 reject_bad_reg (Rn
);
11652 reject_bad_reg (Rm
);
11653 reject_bad_reg (Ra
);
11655 inst
.instruction
|= Rd
<< 8;
11656 inst
.instruction
|= Rn
<< 16;
11657 inst
.instruction
|= Rm
;
11658 inst
.instruction
|= Ra
<< 12;
11664 unsigned RdLo
, RdHi
, Rn
, Rm
;
11666 RdLo
= inst
.operands
[0].reg
;
11667 RdHi
= inst
.operands
[1].reg
;
11668 Rn
= inst
.operands
[2].reg
;
11669 Rm
= inst
.operands
[3].reg
;
11671 reject_bad_reg (RdLo
);
11672 reject_bad_reg (RdHi
);
11673 reject_bad_reg (Rn
);
11674 reject_bad_reg (Rm
);
11676 inst
.instruction
|= RdLo
<< 12;
11677 inst
.instruction
|= RdHi
<< 8;
11678 inst
.instruction
|= Rn
<< 16;
11679 inst
.instruction
|= Rm
;
11683 do_t_mov_cmp (void)
11687 Rn
= inst
.operands
[0].reg
;
11688 Rm
= inst
.operands
[1].reg
;
11691 set_it_insn_type_last ();
11693 if (unified_syntax
)
11695 int r0off
= (inst
.instruction
== T_MNEM_mov
11696 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11697 unsigned long opcode
;
11698 bfd_boolean narrow
;
11699 bfd_boolean low_regs
;
11701 low_regs
= (Rn
<= 7 && Rm
<= 7);
11702 opcode
= inst
.instruction
;
11703 if (in_it_block ())
11704 narrow
= opcode
!= T_MNEM_movs
;
11706 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11707 if (inst
.size_req
== 4
11708 || inst
.operands
[1].shifted
)
11711 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11712 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11713 && !inst
.operands
[1].shifted
11717 inst
.instruction
= T2_SUBS_PC_LR
;
11721 if (opcode
== T_MNEM_cmp
)
11723 constraint (Rn
== REG_PC
, BAD_PC
);
11726 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11728 warn_deprecated_sp (Rm
);
11729 /* R15 was documented as a valid choice for Rm in ARMv6,
11730 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11731 tools reject R15, so we do too. */
11732 constraint (Rm
== REG_PC
, BAD_PC
);
11735 reject_bad_reg (Rm
);
11737 else if (opcode
== T_MNEM_mov
11738 || opcode
== T_MNEM_movs
)
11740 if (inst
.operands
[1].isreg
)
11742 if (opcode
== T_MNEM_movs
)
11744 reject_bad_reg (Rn
);
11745 reject_bad_reg (Rm
);
11749 /* This is mov.n. */
11750 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11751 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11753 as_tsktsk (_("Use of r%u as a source register is "
11754 "deprecated when r%u is the destination "
11755 "register."), Rm
, Rn
);
11760 /* This is mov.w. */
11761 constraint (Rn
== REG_PC
, BAD_PC
);
11762 constraint (Rm
== REG_PC
, BAD_PC
);
11763 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11767 reject_bad_reg (Rn
);
11770 if (!inst
.operands
[1].isreg
)
11772 /* Immediate operand. */
11773 if (!in_it_block () && opcode
== T_MNEM_mov
)
11775 if (low_regs
&& narrow
)
11777 inst
.instruction
= THUMB_OP16 (opcode
);
11778 inst
.instruction
|= Rn
<< 8;
11779 if (inst
.size_req
== 2)
11780 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11782 inst
.relax
= opcode
;
11786 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11787 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11788 inst
.instruction
|= Rn
<< r0off
;
11789 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11792 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11793 && (inst
.instruction
== T_MNEM_mov
11794 || inst
.instruction
== T_MNEM_movs
))
11796 /* Register shifts are encoded as separate shift instructions. */
11797 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11799 if (in_it_block ())
11804 if (inst
.size_req
== 4)
11807 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11813 switch (inst
.operands
[1].shift_kind
)
11816 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11819 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11822 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11825 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11831 inst
.instruction
= opcode
;
11834 inst
.instruction
|= Rn
;
11835 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11840 inst
.instruction
|= CONDS_BIT
;
11842 inst
.instruction
|= Rn
<< 8;
11843 inst
.instruction
|= Rm
<< 16;
11844 inst
.instruction
|= inst
.operands
[1].imm
;
11849 /* Some mov with immediate shift have narrow variants.
11850 Register shifts are handled above. */
11851 if (low_regs
&& inst
.operands
[1].shifted
11852 && (inst
.instruction
== T_MNEM_mov
11853 || inst
.instruction
== T_MNEM_movs
))
11855 if (in_it_block ())
11856 narrow
= (inst
.instruction
== T_MNEM_mov
);
11858 narrow
= (inst
.instruction
== T_MNEM_movs
);
11863 switch (inst
.operands
[1].shift_kind
)
11865 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11866 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11867 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11868 default: narrow
= FALSE
; break;
11874 inst
.instruction
|= Rn
;
11875 inst
.instruction
|= Rm
<< 3;
11876 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11880 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11881 inst
.instruction
|= Rn
<< r0off
;
11882 encode_thumb32_shifted_operand (1);
11886 switch (inst
.instruction
)
11889 /* In v4t or v5t a move of two lowregs produces unpredictable
11890 results. Don't allow this. */
11893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11894 "MOV Rd, Rs with two low registers is not "
11895 "permitted on this architecture");
11896 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11900 inst
.instruction
= T_OPCODE_MOV_HR
;
11901 inst
.instruction
|= (Rn
& 0x8) << 4;
11902 inst
.instruction
|= (Rn
& 0x7);
11903 inst
.instruction
|= Rm
<< 3;
11907 /* We know we have low registers at this point.
11908 Generate LSLS Rd, Rs, #0. */
11909 inst
.instruction
= T_OPCODE_LSL_I
;
11910 inst
.instruction
|= Rn
;
11911 inst
.instruction
|= Rm
<< 3;
11917 inst
.instruction
= T_OPCODE_CMP_LR
;
11918 inst
.instruction
|= Rn
;
11919 inst
.instruction
|= Rm
<< 3;
11923 inst
.instruction
= T_OPCODE_CMP_HR
;
11924 inst
.instruction
|= (Rn
& 0x8) << 4;
11925 inst
.instruction
|= (Rn
& 0x7);
11926 inst
.instruction
|= Rm
<< 3;
11933 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11935 /* PR 10443: Do not silently ignore shifted operands. */
11936 constraint (inst
.operands
[1].shifted
,
11937 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11939 if (inst
.operands
[1].isreg
)
11941 if (Rn
< 8 && Rm
< 8)
11943 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11944 since a MOV instruction produces unpredictable results. */
11945 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11946 inst
.instruction
= T_OPCODE_ADD_I3
;
11948 inst
.instruction
= T_OPCODE_CMP_LR
;
11950 inst
.instruction
|= Rn
;
11951 inst
.instruction
|= Rm
<< 3;
11955 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11956 inst
.instruction
= T_OPCODE_MOV_HR
;
11958 inst
.instruction
= T_OPCODE_CMP_HR
;
11964 constraint (Rn
> 7,
11965 _("only lo regs allowed with immediate"));
11966 inst
.instruction
|= Rn
<< 8;
11967 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11978 top
= (inst
.instruction
& 0x00800000) != 0;
11979 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11981 constraint (top
, _(":lower16: not allowed this instruction"));
11982 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11984 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11986 constraint (!top
, _(":upper16: not allowed this instruction"));
11987 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11990 Rd
= inst
.operands
[0].reg
;
11991 reject_bad_reg (Rd
);
11993 inst
.instruction
|= Rd
<< 8;
11994 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11996 imm
= inst
.reloc
.exp
.X_add_number
;
11997 inst
.instruction
|= (imm
& 0xf000) << 4;
11998 inst
.instruction
|= (imm
& 0x0800) << 15;
11999 inst
.instruction
|= (imm
& 0x0700) << 4;
12000 inst
.instruction
|= (imm
& 0x00ff);
12005 do_t_mvn_tst (void)
12009 Rn
= inst
.operands
[0].reg
;
12010 Rm
= inst
.operands
[1].reg
;
12012 if (inst
.instruction
== T_MNEM_cmp
12013 || inst
.instruction
== T_MNEM_cmn
)
12014 constraint (Rn
== REG_PC
, BAD_PC
);
12016 reject_bad_reg (Rn
);
12017 reject_bad_reg (Rm
);
12019 if (unified_syntax
)
12021 int r0off
= (inst
.instruction
== T_MNEM_mvn
12022 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12023 bfd_boolean narrow
;
12025 if (inst
.size_req
== 4
12026 || inst
.instruction
> 0xffff
12027 || inst
.operands
[1].shifted
12028 || Rn
> 7 || Rm
> 7)
12030 else if (inst
.instruction
== T_MNEM_cmn
12031 || inst
.instruction
== T_MNEM_tst
)
12033 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12034 narrow
= !in_it_block ();
12036 narrow
= in_it_block ();
12038 if (!inst
.operands
[1].isreg
)
12040 /* For an immediate, we always generate a 32-bit opcode;
12041 section relaxation will shrink it later if possible. */
12042 if (inst
.instruction
< 0xffff)
12043 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12044 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12045 inst
.instruction
|= Rn
<< r0off
;
12046 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12050 /* See if we can do this with a 16-bit instruction. */
12053 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12054 inst
.instruction
|= Rn
;
12055 inst
.instruction
|= Rm
<< 3;
12059 constraint (inst
.operands
[1].shifted
12060 && inst
.operands
[1].immisreg
,
12061 _("shift must be constant"));
12062 if (inst
.instruction
< 0xffff)
12063 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12064 inst
.instruction
|= Rn
<< r0off
;
12065 encode_thumb32_shifted_operand (1);
12071 constraint (inst
.instruction
> 0xffff
12072 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12073 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12074 _("unshifted register required"));
12075 constraint (Rn
> 7 || Rm
> 7,
12078 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12079 inst
.instruction
|= Rn
;
12080 inst
.instruction
|= Rm
<< 3;
12089 if (do_vfp_nsyn_mrs () == SUCCESS
)
12092 Rd
= inst
.operands
[0].reg
;
12093 reject_bad_reg (Rd
);
12094 inst
.instruction
|= Rd
<< 8;
12096 if (inst
.operands
[1].isreg
)
12098 unsigned br
= inst
.operands
[1].reg
;
12099 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12100 as_bad (_("bad register for mrs"));
12102 inst
.instruction
|= br
& (0xf << 16);
12103 inst
.instruction
|= (br
& 0x300) >> 4;
12104 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12108 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12110 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12112 /* PR gas/12698: The constraint is only applied for m_profile.
12113 If the user has specified -march=all, we want to ignore it as
12114 we are building for any CPU type, including non-m variants. */
12115 bfd_boolean m_profile
=
12116 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12117 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12118 "not support requested special purpose register"));
12121 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12123 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12124 _("'APSR', 'CPSR' or 'SPSR' expected"));
12126 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12127 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12128 inst
.instruction
|= 0xf0000;
12138 if (do_vfp_nsyn_msr () == SUCCESS
)
12141 constraint (!inst
.operands
[1].isreg
,
12142 _("Thumb encoding does not support an immediate here"));
12144 if (inst
.operands
[0].isreg
)
12145 flags
= (int)(inst
.operands
[0].reg
);
12147 flags
= inst
.operands
[0].imm
;
12149 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12151 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12153 /* PR gas/12698: The constraint is only applied for m_profile.
12154 If the user has specified -march=all, we want to ignore it as
12155 we are building for any CPU type, including non-m variants. */
12156 bfd_boolean m_profile
=
12157 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12158 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12159 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12160 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12161 && bits
!= PSR_f
)) && m_profile
,
12162 _("selected processor does not support requested special "
12163 "purpose register"));
12166 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12167 "requested special purpose register"));
12169 Rn
= inst
.operands
[1].reg
;
12170 reject_bad_reg (Rn
);
12172 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12173 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12174 inst
.instruction
|= (flags
& 0x300) >> 4;
12175 inst
.instruction
|= (flags
& 0xff);
12176 inst
.instruction
|= Rn
<< 16;
12182 bfd_boolean narrow
;
12183 unsigned Rd
, Rn
, Rm
;
12185 if (!inst
.operands
[2].present
)
12186 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12188 Rd
= inst
.operands
[0].reg
;
12189 Rn
= inst
.operands
[1].reg
;
12190 Rm
= inst
.operands
[2].reg
;
12192 if (unified_syntax
)
12194 if (inst
.size_req
== 4
12200 else if (inst
.instruction
== T_MNEM_muls
)
12201 narrow
= !in_it_block ();
12203 narrow
= in_it_block ();
12207 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12208 constraint (Rn
> 7 || Rm
> 7,
12215 /* 16-bit MULS/Conditional MUL. */
12216 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12217 inst
.instruction
|= Rd
;
12220 inst
.instruction
|= Rm
<< 3;
12222 inst
.instruction
|= Rn
<< 3;
12224 constraint (1, _("dest must overlap one source register"));
12228 constraint (inst
.instruction
!= T_MNEM_mul
,
12229 _("Thumb-2 MUL must not set flags"));
12231 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12232 inst
.instruction
|= Rd
<< 8;
12233 inst
.instruction
|= Rn
<< 16;
12234 inst
.instruction
|= Rm
<< 0;
12236 reject_bad_reg (Rd
);
12237 reject_bad_reg (Rn
);
12238 reject_bad_reg (Rm
);
12245 unsigned RdLo
, RdHi
, Rn
, Rm
;
12247 RdLo
= inst
.operands
[0].reg
;
12248 RdHi
= inst
.operands
[1].reg
;
12249 Rn
= inst
.operands
[2].reg
;
12250 Rm
= inst
.operands
[3].reg
;
12252 reject_bad_reg (RdLo
);
12253 reject_bad_reg (RdHi
);
12254 reject_bad_reg (Rn
);
12255 reject_bad_reg (Rm
);
12257 inst
.instruction
|= RdLo
<< 12;
12258 inst
.instruction
|= RdHi
<< 8;
12259 inst
.instruction
|= Rn
<< 16;
12260 inst
.instruction
|= Rm
;
12263 as_tsktsk (_("rdhi and rdlo must be different"));
12269 set_it_insn_type (NEUTRAL_IT_INSN
);
12271 if (unified_syntax
)
12273 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12275 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12276 inst
.instruction
|= inst
.operands
[0].imm
;
12280 /* PR9722: Check for Thumb2 availability before
12281 generating a thumb2 nop instruction. */
12282 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12284 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12285 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12288 inst
.instruction
= 0x46c0;
12293 constraint (inst
.operands
[0].present
,
12294 _("Thumb does not support NOP with hints"));
12295 inst
.instruction
= 0x46c0;
12302 if (unified_syntax
)
12304 bfd_boolean narrow
;
12306 if (THUMB_SETS_FLAGS (inst
.instruction
))
12307 narrow
= !in_it_block ();
12309 narrow
= in_it_block ();
12310 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12312 if (inst
.size_req
== 4)
12317 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12318 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12319 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12323 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12324 inst
.instruction
|= inst
.operands
[0].reg
;
12325 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12330 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12332 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12334 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12335 inst
.instruction
|= inst
.operands
[0].reg
;
12336 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12345 Rd
= inst
.operands
[0].reg
;
12346 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12348 reject_bad_reg (Rd
);
12349 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12350 reject_bad_reg (Rn
);
12352 inst
.instruction
|= Rd
<< 8;
12353 inst
.instruction
|= Rn
<< 16;
12355 if (!inst
.operands
[2].isreg
)
12357 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12358 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12364 Rm
= inst
.operands
[2].reg
;
12365 reject_bad_reg (Rm
);
12367 constraint (inst
.operands
[2].shifted
12368 && inst
.operands
[2].immisreg
,
12369 _("shift must be constant"));
12370 encode_thumb32_shifted_operand (2);
12377 unsigned Rd
, Rn
, Rm
;
12379 Rd
= inst
.operands
[0].reg
;
12380 Rn
= inst
.operands
[1].reg
;
12381 Rm
= inst
.operands
[2].reg
;
12383 reject_bad_reg (Rd
);
12384 reject_bad_reg (Rn
);
12385 reject_bad_reg (Rm
);
12387 inst
.instruction
|= Rd
<< 8;
12388 inst
.instruction
|= Rn
<< 16;
12389 inst
.instruction
|= Rm
;
12390 if (inst
.operands
[3].present
)
12392 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12393 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12394 _("expression too complex"));
12395 inst
.instruction
|= (val
& 0x1c) << 10;
12396 inst
.instruction
|= (val
& 0x03) << 6;
12403 if (!inst
.operands
[3].present
)
12407 inst
.instruction
&= ~0x00000020;
12409 /* PR 10168. Swap the Rm and Rn registers. */
12410 Rtmp
= inst
.operands
[1].reg
;
12411 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12412 inst
.operands
[2].reg
= Rtmp
;
12420 if (inst
.operands
[0].immisreg
)
12421 reject_bad_reg (inst
.operands
[0].imm
);
12423 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12427 do_t_push_pop (void)
12431 constraint (inst
.operands
[0].writeback
,
12432 _("push/pop do not support {reglist}^"));
12433 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12434 _("expression too complex"));
12436 mask
= inst
.operands
[0].imm
;
12437 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12438 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12439 else if (inst
.size_req
!= 4
12440 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12441 ? REG_LR
: REG_PC
)))
12443 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12444 inst
.instruction
|= THUMB_PP_PC_LR
;
12445 inst
.instruction
|= mask
& 0xff;
12447 else if (unified_syntax
)
12449 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12450 encode_thumb2_ldmstm (13, mask
, TRUE
);
12454 inst
.error
= _("invalid register list to push/pop instruction");
12464 Rd
= inst
.operands
[0].reg
;
12465 Rm
= inst
.operands
[1].reg
;
12467 reject_bad_reg (Rd
);
12468 reject_bad_reg (Rm
);
12470 inst
.instruction
|= Rd
<< 8;
12471 inst
.instruction
|= Rm
<< 16;
12472 inst
.instruction
|= Rm
;
12480 Rd
= inst
.operands
[0].reg
;
12481 Rm
= inst
.operands
[1].reg
;
12483 reject_bad_reg (Rd
);
12484 reject_bad_reg (Rm
);
12486 if (Rd
<= 7 && Rm
<= 7
12487 && inst
.size_req
!= 4)
12489 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12490 inst
.instruction
|= Rd
;
12491 inst
.instruction
|= Rm
<< 3;
12493 else if (unified_syntax
)
12495 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12496 inst
.instruction
|= Rd
<< 8;
12497 inst
.instruction
|= Rm
<< 16;
12498 inst
.instruction
|= Rm
;
12501 inst
.error
= BAD_HIREG
;
12509 Rd
= inst
.operands
[0].reg
;
12510 Rm
= inst
.operands
[1].reg
;
12512 reject_bad_reg (Rd
);
12513 reject_bad_reg (Rm
);
12515 inst
.instruction
|= Rd
<< 8;
12516 inst
.instruction
|= Rm
;
12524 Rd
= inst
.operands
[0].reg
;
12525 Rs
= (inst
.operands
[1].present
12526 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12527 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12529 reject_bad_reg (Rd
);
12530 reject_bad_reg (Rs
);
12531 if (inst
.operands
[2].isreg
)
12532 reject_bad_reg (inst
.operands
[2].reg
);
12534 inst
.instruction
|= Rd
<< 8;
12535 inst
.instruction
|= Rs
<< 16;
12536 if (!inst
.operands
[2].isreg
)
12538 bfd_boolean narrow
;
12540 if ((inst
.instruction
& 0x00100000) != 0)
12541 narrow
= !in_it_block ();
12543 narrow
= in_it_block ();
12545 if (Rd
> 7 || Rs
> 7)
12548 if (inst
.size_req
== 4 || !unified_syntax
)
12551 if (inst
.reloc
.exp
.X_op
!= O_constant
12552 || inst
.reloc
.exp
.X_add_number
!= 0)
12555 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12556 relaxation, but it doesn't seem worth the hassle. */
12559 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12560 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12561 inst
.instruction
|= Rs
<< 3;
12562 inst
.instruction
|= Rd
;
12566 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12567 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12571 encode_thumb32_shifted_operand (2);
12577 if (warn_on_deprecated
12578 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12579 as_tsktsk (_("setend use is deprecated for ARMv8"));
12581 set_it_insn_type (OUTSIDE_IT_INSN
);
12582 if (inst
.operands
[0].imm
)
12583 inst
.instruction
|= 0x8;
12589 if (!inst
.operands
[1].present
)
12590 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12592 if (unified_syntax
)
12594 bfd_boolean narrow
;
12597 switch (inst
.instruction
)
12600 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12602 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12604 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12606 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12610 if (THUMB_SETS_FLAGS (inst
.instruction
))
12611 narrow
= !in_it_block ();
12613 narrow
= in_it_block ();
12614 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12616 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12618 if (inst
.operands
[2].isreg
12619 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12620 || inst
.operands
[2].reg
> 7))
12622 if (inst
.size_req
== 4)
12625 reject_bad_reg (inst
.operands
[0].reg
);
12626 reject_bad_reg (inst
.operands
[1].reg
);
12630 if (inst
.operands
[2].isreg
)
12632 reject_bad_reg (inst
.operands
[2].reg
);
12633 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12634 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12635 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12636 inst
.instruction
|= inst
.operands
[2].reg
;
12638 /* PR 12854: Error on extraneous shifts. */
12639 constraint (inst
.operands
[2].shifted
,
12640 _("extraneous shift as part of operand to shift insn"));
12644 inst
.operands
[1].shifted
= 1;
12645 inst
.operands
[1].shift_kind
= shift_kind
;
12646 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12647 ? T_MNEM_movs
: T_MNEM_mov
);
12648 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12649 encode_thumb32_shifted_operand (1);
12650 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12651 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12656 if (inst
.operands
[2].isreg
)
12658 switch (shift_kind
)
12660 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12661 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12662 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12663 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12667 inst
.instruction
|= inst
.operands
[0].reg
;
12668 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12670 /* PR 12854: Error on extraneous shifts. */
12671 constraint (inst
.operands
[2].shifted
,
12672 _("extraneous shift as part of operand to shift insn"));
12676 switch (shift_kind
)
12678 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12679 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12680 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12683 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12684 inst
.instruction
|= inst
.operands
[0].reg
;
12685 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12691 constraint (inst
.operands
[0].reg
> 7
12692 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12693 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12695 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12697 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12698 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12699 _("source1 and dest must be same register"));
12701 switch (inst
.instruction
)
12703 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12704 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12705 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12706 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12710 inst
.instruction
|= inst
.operands
[0].reg
;
12711 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12713 /* PR 12854: Error on extraneous shifts. */
12714 constraint (inst
.operands
[2].shifted
,
12715 _("extraneous shift as part of operand to shift insn"));
12719 switch (inst
.instruction
)
12721 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12722 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12723 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12724 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12727 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12728 inst
.instruction
|= inst
.operands
[0].reg
;
12729 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12737 unsigned Rd
, Rn
, Rm
;
12739 Rd
= inst
.operands
[0].reg
;
12740 Rn
= inst
.operands
[1].reg
;
12741 Rm
= inst
.operands
[2].reg
;
12743 reject_bad_reg (Rd
);
12744 reject_bad_reg (Rn
);
12745 reject_bad_reg (Rm
);
12747 inst
.instruction
|= Rd
<< 8;
12748 inst
.instruction
|= Rn
<< 16;
12749 inst
.instruction
|= Rm
;
12755 unsigned Rd
, Rn
, Rm
;
12757 Rd
= inst
.operands
[0].reg
;
12758 Rm
= inst
.operands
[1].reg
;
12759 Rn
= inst
.operands
[2].reg
;
12761 reject_bad_reg (Rd
);
12762 reject_bad_reg (Rn
);
12763 reject_bad_reg (Rm
);
12765 inst
.instruction
|= Rd
<< 8;
12766 inst
.instruction
|= Rn
<< 16;
12767 inst
.instruction
|= Rm
;
12773 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12774 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12775 _("SMC is not permitted on this architecture"));
12776 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12777 _("expression too complex"));
12778 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12779 inst
.instruction
|= (value
& 0xf000) >> 12;
12780 inst
.instruction
|= (value
& 0x0ff0);
12781 inst
.instruction
|= (value
& 0x000f) << 16;
12782 /* PR gas/15623: SMC instructions must be last in an IT block. */
12783 set_it_insn_type_last ();
12789 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12791 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12792 inst
.instruction
|= (value
& 0x0fff);
12793 inst
.instruction
|= (value
& 0xf000) << 4;
12797 do_t_ssat_usat (int bias
)
12801 Rd
= inst
.operands
[0].reg
;
12802 Rn
= inst
.operands
[2].reg
;
12804 reject_bad_reg (Rd
);
12805 reject_bad_reg (Rn
);
12807 inst
.instruction
|= Rd
<< 8;
12808 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12809 inst
.instruction
|= Rn
<< 16;
12811 if (inst
.operands
[3].present
)
12813 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12815 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12817 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12818 _("expression too complex"));
12820 if (shift_amount
!= 0)
12822 constraint (shift_amount
> 31,
12823 _("shift expression is too large"));
12825 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12826 inst
.instruction
|= 0x00200000; /* sh bit. */
12828 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12829 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12837 do_t_ssat_usat (1);
12845 Rd
= inst
.operands
[0].reg
;
12846 Rn
= inst
.operands
[2].reg
;
12848 reject_bad_reg (Rd
);
12849 reject_bad_reg (Rn
);
12851 inst
.instruction
|= Rd
<< 8;
12852 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12853 inst
.instruction
|= Rn
<< 16;
12859 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12860 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12861 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12862 || inst
.operands
[2].negative
,
12865 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12867 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12868 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12869 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12870 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12876 if (!inst
.operands
[2].present
)
12877 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12879 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12880 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12881 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12884 inst
.instruction
|= inst
.operands
[0].reg
;
12885 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12886 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12887 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12893 unsigned Rd
, Rn
, Rm
;
12895 Rd
= inst
.operands
[0].reg
;
12896 Rn
= inst
.operands
[1].reg
;
12897 Rm
= inst
.operands
[2].reg
;
12899 reject_bad_reg (Rd
);
12900 reject_bad_reg (Rn
);
12901 reject_bad_reg (Rm
);
12903 inst
.instruction
|= Rd
<< 8;
12904 inst
.instruction
|= Rn
<< 16;
12905 inst
.instruction
|= Rm
;
12906 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12914 Rd
= inst
.operands
[0].reg
;
12915 Rm
= inst
.operands
[1].reg
;
12917 reject_bad_reg (Rd
);
12918 reject_bad_reg (Rm
);
12920 if (inst
.instruction
<= 0xffff
12921 && inst
.size_req
!= 4
12922 && Rd
<= 7 && Rm
<= 7
12923 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12925 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12926 inst
.instruction
|= Rd
;
12927 inst
.instruction
|= Rm
<< 3;
12929 else if (unified_syntax
)
12931 if (inst
.instruction
<= 0xffff)
12932 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12933 inst
.instruction
|= Rd
<< 8;
12934 inst
.instruction
|= Rm
;
12935 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12939 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12940 _("Thumb encoding does not support rotation"));
12941 constraint (1, BAD_HIREG
);
12948 /* We have to do the following check manually as ARM_EXT_OS only applies
12950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12952 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12953 /* This only applies to the v6m howver, not later architectures. */
12954 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12955 as_bad (_("SVC is not permitted on this architecture"));
12956 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12959 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12968 half
= (inst
.instruction
& 0x10) != 0;
12969 set_it_insn_type_last ();
12970 constraint (inst
.operands
[0].immisreg
,
12971 _("instruction requires register index"));
12973 Rn
= inst
.operands
[0].reg
;
12974 Rm
= inst
.operands
[0].imm
;
12976 constraint (Rn
== REG_SP
, BAD_SP
);
12977 reject_bad_reg (Rm
);
12979 constraint (!half
&& inst
.operands
[0].shifted
,
12980 _("instruction does not allow shifted index"));
12981 inst
.instruction
|= (Rn
<< 16) | Rm
;
12987 if (!inst
.operands
[0].present
)
12988 inst
.operands
[0].imm
= 0;
12990 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12992 constraint (inst
.size_req
== 2,
12993 _("immediate value out of range"));
12994 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12995 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12996 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13001 inst
.instruction
|= inst
.operands
[0].imm
;
13004 set_it_insn_type (NEUTRAL_IT_INSN
);
13011 do_t_ssat_usat (0);
13019 Rd
= inst
.operands
[0].reg
;
13020 Rn
= inst
.operands
[2].reg
;
13022 reject_bad_reg (Rd
);
13023 reject_bad_reg (Rn
);
13025 inst
.instruction
|= Rd
<< 8;
13026 inst
.instruction
|= inst
.operands
[1].imm
;
13027 inst
.instruction
|= Rn
<< 16;
13030 /* Neon instruction encoder helpers. */
13032 /* Encodings for the different types for various Neon opcodes. */
13034 /* An "invalid" code for the following tables. */
13037 struct neon_tab_entry
13040 unsigned float_or_poly
;
13041 unsigned scalar_or_imm
;
13044 /* Map overloaded Neon opcodes to their respective encodings. */
13045 #define NEON_ENC_TAB \
13046 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13047 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13048 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13049 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13050 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13051 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13052 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13053 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13054 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13055 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13056 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13057 /* Register variants of the following two instructions are encoded as
13058 vcge / vcgt with the operands reversed. */ \
13059 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13060 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13061 X(vfma, N_INV, 0x0000c10, N_INV), \
13062 X(vfms, N_INV, 0x0200c10, N_INV), \
13063 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13064 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13065 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13066 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13067 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13068 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13069 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13070 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13071 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13072 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13073 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13074 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13075 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13076 X(vshl, 0x0000400, N_INV, 0x0800510), \
13077 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13078 X(vand, 0x0000110, N_INV, 0x0800030), \
13079 X(vbic, 0x0100110, N_INV, 0x0800030), \
13080 X(veor, 0x1000110, N_INV, N_INV), \
13081 X(vorn, 0x0300110, N_INV, 0x0800010), \
13082 X(vorr, 0x0200110, N_INV, 0x0800010), \
13083 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13084 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13085 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13086 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13087 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13088 X(vst1, 0x0000000, 0x0800000, N_INV), \
13089 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13090 X(vst2, 0x0000100, 0x0800100, N_INV), \
13091 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13092 X(vst3, 0x0000200, 0x0800200, N_INV), \
13093 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13094 X(vst4, 0x0000300, 0x0800300, N_INV), \
13095 X(vmovn, 0x1b20200, N_INV, N_INV), \
13096 X(vtrn, 0x1b20080, N_INV, N_INV), \
13097 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13098 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13099 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13100 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13101 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13102 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13103 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13104 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13105 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13106 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13107 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13108 X(vseleq, 0xe000a00, N_INV, N_INV), \
13109 X(vselvs, 0xe100a00, N_INV, N_INV), \
13110 X(vselge, 0xe200a00, N_INV, N_INV), \
13111 X(vselgt, 0xe300a00, N_INV, N_INV), \
13112 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13113 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13114 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13115 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13116 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13117 X(aes, 0x3b00300, N_INV, N_INV), \
13118 X(sha3op, 0x2000c00, N_INV, N_INV), \
13119 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13120 X(sha2op, 0x3ba0380, N_INV, N_INV)
13124 #define X(OPC,I,F,S) N_MNEM_##OPC
13129 static const struct neon_tab_entry neon_enc_tab
[] =
13131 #define X(OPC,I,F,S) { (I), (F), (S) }
13136 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13137 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13138 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13139 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13140 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13141 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13142 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13143 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13144 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13145 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13146 #define NEON_ENC_SINGLE_(X) \
13147 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13148 #define NEON_ENC_DOUBLE_(X) \
13149 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13150 #define NEON_ENC_FPV8_(X) \
13151 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13153 #define NEON_ENCODE(type, inst) \
13156 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13157 inst.is_neon = 1; \
13161 #define check_neon_suffixes \
13164 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13166 as_bad (_("invalid neon suffix for non neon instruction")); \
13172 /* Define shapes for instruction operands. The following mnemonic characters
13173 are used in this table:
13175 F - VFP S<n> register
13176 D - Neon D<n> register
13177 Q - Neon Q<n> register
13181 L - D<n> register list
13183 This table is used to generate various data:
13184 - enumerations of the form NS_DDR to be used as arguments to
13186 - a table classifying shapes into single, double, quad, mixed.
13187 - a table used to drive neon_select_shape. */
13189 #define NEON_SHAPE_DEF \
13190 X(3, (D, D, D), DOUBLE), \
13191 X(3, (Q, Q, Q), QUAD), \
13192 X(3, (D, D, I), DOUBLE), \
13193 X(3, (Q, Q, I), QUAD), \
13194 X(3, (D, D, S), DOUBLE), \
13195 X(3, (Q, Q, S), QUAD), \
13196 X(2, (D, D), DOUBLE), \
13197 X(2, (Q, Q), QUAD), \
13198 X(2, (D, S), DOUBLE), \
13199 X(2, (Q, S), QUAD), \
13200 X(2, (D, R), DOUBLE), \
13201 X(2, (Q, R), QUAD), \
13202 X(2, (D, I), DOUBLE), \
13203 X(2, (Q, I), QUAD), \
13204 X(3, (D, L, D), DOUBLE), \
13205 X(2, (D, Q), MIXED), \
13206 X(2, (Q, D), MIXED), \
13207 X(3, (D, Q, I), MIXED), \
13208 X(3, (Q, D, I), MIXED), \
13209 X(3, (Q, D, D), MIXED), \
13210 X(3, (D, Q, Q), MIXED), \
13211 X(3, (Q, Q, D), MIXED), \
13212 X(3, (Q, D, S), MIXED), \
13213 X(3, (D, Q, S), MIXED), \
13214 X(4, (D, D, D, I), DOUBLE), \
13215 X(4, (Q, Q, Q, I), QUAD), \
13216 X(2, (F, F), SINGLE), \
13217 X(3, (F, F, F), SINGLE), \
13218 X(2, (F, I), SINGLE), \
13219 X(2, (F, D), MIXED), \
13220 X(2, (D, F), MIXED), \
13221 X(3, (F, F, I), MIXED), \
13222 X(4, (R, R, F, F), SINGLE), \
13223 X(4, (F, F, R, R), SINGLE), \
13224 X(3, (D, R, R), DOUBLE), \
13225 X(3, (R, R, D), DOUBLE), \
13226 X(2, (S, R), SINGLE), \
13227 X(2, (R, S), SINGLE), \
13228 X(2, (F, R), SINGLE), \
13229 X(2, (R, F), SINGLE)
13231 #define S2(A,B) NS_##A##B
13232 #define S3(A,B,C) NS_##A##B##C
13233 #define S4(A,B,C,D) NS_##A##B##C##D
13235 #define X(N, L, C) S##N L
13248 enum neon_shape_class
13256 #define X(N, L, C) SC_##C
13258 static enum neon_shape_class neon_shape_class
[] =
13276 /* Register widths of above. */
13277 static unsigned neon_shape_el_size
[] =
13288 struct neon_shape_info
13291 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13294 #define S2(A,B) { SE_##A, SE_##B }
13295 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13296 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13298 #define X(N, L, C) { N, S##N L }
13300 static struct neon_shape_info neon_shape_tab
[] =
13310 /* Bit masks used in type checking given instructions.
13311 'N_EQK' means the type must be the same as (or based on in some way) the key
13312 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13313 set, various other bits can be set as well in order to modify the meaning of
13314 the type constraint. */
13316 enum neon_type_mask
13340 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13341 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13342 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13343 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13344 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13345 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13346 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13347 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13348 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13349 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13350 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13352 N_MAX_NONSPECIAL
= N_P64
13355 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13357 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13358 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13359 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13360 #define N_SUF_32 (N_SU_32 | N_F32)
13361 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13362 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13364 /* Pass this as the first type argument to neon_check_type to ignore types
13366 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13368 /* Select a "shape" for the current instruction (describing register types or
13369 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13370 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13371 function of operand parsing, so this function doesn't need to be called.
13372 Shapes should be listed in order of decreasing length. */
13374 static enum neon_shape
13375 neon_select_shape (enum neon_shape shape
, ...)
13378 enum neon_shape first_shape
= shape
;
13380 /* Fix missing optional operands. FIXME: we don't know at this point how
13381 many arguments we should have, so this makes the assumption that we have
13382 > 1. This is true of all current Neon opcodes, I think, but may not be
13383 true in the future. */
13384 if (!inst
.operands
[1].present
)
13385 inst
.operands
[1] = inst
.operands
[0];
13387 va_start (ap
, shape
);
13389 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13394 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13396 if (!inst
.operands
[j
].present
)
13402 switch (neon_shape_tab
[shape
].el
[j
])
13405 if (!(inst
.operands
[j
].isreg
13406 && inst
.operands
[j
].isvec
13407 && inst
.operands
[j
].issingle
13408 && !inst
.operands
[j
].isquad
))
13413 if (!(inst
.operands
[j
].isreg
13414 && inst
.operands
[j
].isvec
13415 && !inst
.operands
[j
].isquad
13416 && !inst
.operands
[j
].issingle
))
13421 if (!(inst
.operands
[j
].isreg
13422 && !inst
.operands
[j
].isvec
))
13427 if (!(inst
.operands
[j
].isreg
13428 && inst
.operands
[j
].isvec
13429 && inst
.operands
[j
].isquad
13430 && !inst
.operands
[j
].issingle
))
13435 if (!(!inst
.operands
[j
].isreg
13436 && !inst
.operands
[j
].isscalar
))
13441 if (!(!inst
.operands
[j
].isreg
13442 && inst
.operands
[j
].isscalar
))
13452 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13453 /* We've matched all the entries in the shape table, and we don't
13454 have any left over operands which have not been matched. */
13460 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13461 first_error (_("invalid instruction shape"));
13466 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13467 means the Q bit should be set). */
13470 neon_quad (enum neon_shape shape
)
13472 return neon_shape_class
[shape
] == SC_QUAD
;
13476 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13479 /* Allow modification to be made to types which are constrained to be
13480 based on the key element, based on bits set alongside N_EQK. */
13481 if ((typebits
& N_EQK
) != 0)
13483 if ((typebits
& N_HLF
) != 0)
13485 else if ((typebits
& N_DBL
) != 0)
13487 if ((typebits
& N_SGN
) != 0)
13488 *g_type
= NT_signed
;
13489 else if ((typebits
& N_UNS
) != 0)
13490 *g_type
= NT_unsigned
;
13491 else if ((typebits
& N_INT
) != 0)
13492 *g_type
= NT_integer
;
13493 else if ((typebits
& N_FLT
) != 0)
13494 *g_type
= NT_float
;
13495 else if ((typebits
& N_SIZ
) != 0)
13496 *g_type
= NT_untyped
;
13500 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13501 operand type, i.e. the single type specified in a Neon instruction when it
13502 is the only one given. */
13504 static struct neon_type_el
13505 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13507 struct neon_type_el dest
= *key
;
13509 gas_assert ((thisarg
& N_EQK
) != 0);
13511 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13516 /* Convert Neon type and size into compact bitmask representation. */
13518 static enum neon_type_mask
13519 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13526 case 8: return N_8
;
13527 case 16: return N_16
;
13528 case 32: return N_32
;
13529 case 64: return N_64
;
13537 case 8: return N_I8
;
13538 case 16: return N_I16
;
13539 case 32: return N_I32
;
13540 case 64: return N_I64
;
13548 case 16: return N_F16
;
13549 case 32: return N_F32
;
13550 case 64: return N_F64
;
13558 case 8: return N_P8
;
13559 case 16: return N_P16
;
13560 case 64: return N_P64
;
13568 case 8: return N_S8
;
13569 case 16: return N_S16
;
13570 case 32: return N_S32
;
13571 case 64: return N_S64
;
13579 case 8: return N_U8
;
13580 case 16: return N_U16
;
13581 case 32: return N_U32
;
13582 case 64: return N_U64
;
13593 /* Convert compact Neon bitmask type representation to a type and size. Only
13594 handles the case where a single bit is set in the mask. */
13597 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13598 enum neon_type_mask mask
)
13600 if ((mask
& N_EQK
) != 0)
13603 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13605 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13607 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13609 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13614 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13616 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13617 *type
= NT_unsigned
;
13618 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13619 *type
= NT_integer
;
13620 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13621 *type
= NT_untyped
;
13622 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13624 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13632 /* Modify a bitmask of allowed types. This is only needed for type
13636 modify_types_allowed (unsigned allowed
, unsigned mods
)
13639 enum neon_el_type type
;
13645 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13647 if (el_type_of_type_chk (&type
, &size
,
13648 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13650 neon_modify_type_size (mods
, &type
, &size
);
13651 destmask
|= type_chk_of_el_type (type
, size
);
13658 /* Check type and return type classification.
13659 The manual states (paraphrase): If one datatype is given, it indicates the
13661 - the second operand, if there is one
13662 - the operand, if there is no second operand
13663 - the result, if there are no operands.
13664 This isn't quite good enough though, so we use a concept of a "key" datatype
13665 which is set on a per-instruction basis, which is the one which matters when
13666 only one data type is written.
13667 Note: this function has side-effects (e.g. filling in missing operands). All
13668 Neon instructions should call it before performing bit encoding. */
13670 static struct neon_type_el
13671 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13674 unsigned i
, pass
, key_el
= 0;
13675 unsigned types
[NEON_MAX_TYPE_ELS
];
13676 enum neon_el_type k_type
= NT_invtype
;
13677 unsigned k_size
= -1u;
13678 struct neon_type_el badtype
= {NT_invtype
, -1};
13679 unsigned key_allowed
= 0;
13681 /* Optional registers in Neon instructions are always (not) in operand 1.
13682 Fill in the missing operand here, if it was omitted. */
13683 if (els
> 1 && !inst
.operands
[1].present
)
13684 inst
.operands
[1] = inst
.operands
[0];
13686 /* Suck up all the varargs. */
13688 for (i
= 0; i
< els
; i
++)
13690 unsigned thisarg
= va_arg (ap
, unsigned);
13691 if (thisarg
== N_IGNORE_TYPE
)
13696 types
[i
] = thisarg
;
13697 if ((thisarg
& N_KEY
) != 0)
13702 if (inst
.vectype
.elems
> 0)
13703 for (i
= 0; i
< els
; i
++)
13704 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13706 first_error (_("types specified in both the mnemonic and operands"));
13710 /* Duplicate inst.vectype elements here as necessary.
13711 FIXME: No idea if this is exactly the same as the ARM assembler,
13712 particularly when an insn takes one register and one non-register
13714 if (inst
.vectype
.elems
== 1 && els
> 1)
13717 inst
.vectype
.elems
= els
;
13718 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13719 for (j
= 0; j
< els
; j
++)
13721 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13724 else if (inst
.vectype
.elems
== 0 && els
> 0)
13727 /* No types were given after the mnemonic, so look for types specified
13728 after each operand. We allow some flexibility here; as long as the
13729 "key" operand has a type, we can infer the others. */
13730 for (j
= 0; j
< els
; j
++)
13731 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13732 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13734 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13736 for (j
= 0; j
< els
; j
++)
13737 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13738 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13743 first_error (_("operand types can't be inferred"));
13747 else if (inst
.vectype
.elems
!= els
)
13749 first_error (_("type specifier has the wrong number of parts"));
13753 for (pass
= 0; pass
< 2; pass
++)
13755 for (i
= 0; i
< els
; i
++)
13757 unsigned thisarg
= types
[i
];
13758 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13759 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13760 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13761 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13763 /* Decay more-specific signed & unsigned types to sign-insensitive
13764 integer types if sign-specific variants are unavailable. */
13765 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13766 && (types_allowed
& N_SU_ALL
) == 0)
13767 g_type
= NT_integer
;
13769 /* If only untyped args are allowed, decay any more specific types to
13770 them. Some instructions only care about signs for some element
13771 sizes, so handle that properly. */
13772 if (((types_allowed
& N_UNT
) == 0)
13773 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13774 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13775 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13776 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13777 g_type
= NT_untyped
;
13781 if ((thisarg
& N_KEY
) != 0)
13785 key_allowed
= thisarg
& ~N_KEY
;
13790 if ((thisarg
& N_VFP
) != 0)
13792 enum neon_shape_el regshape
;
13793 unsigned regwidth
, match
;
13795 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13798 first_error (_("invalid instruction shape"));
13801 regshape
= neon_shape_tab
[ns
].el
[i
];
13802 regwidth
= neon_shape_el_size
[regshape
];
13804 /* In VFP mode, operands must match register widths. If we
13805 have a key operand, use its width, else use the width of
13806 the current operand. */
13812 if (regwidth
!= match
)
13814 first_error (_("operand size must match register width"));
13819 if ((thisarg
& N_EQK
) == 0)
13821 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13823 if ((given_type
& types_allowed
) == 0)
13825 first_error (_("bad type in Neon instruction"));
13831 enum neon_el_type mod_k_type
= k_type
;
13832 unsigned mod_k_size
= k_size
;
13833 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13834 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13836 first_error (_("inconsistent types in Neon instruction"));
13844 return inst
.vectype
.el
[key_el
];
13847 /* Neon-style VFP instruction forwarding. */
13849 /* Thumb VFP instructions have 0xE in the condition field. */
13852 do_vfp_cond_or_thumb (void)
13857 inst
.instruction
|= 0xe0000000;
13859 inst
.instruction
|= inst
.cond
<< 28;
13862 /* Look up and encode a simple mnemonic, for use as a helper function for the
13863 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13864 etc. It is assumed that operand parsing has already been done, and that the
13865 operands are in the form expected by the given opcode (this isn't necessarily
13866 the same as the form in which they were parsed, hence some massaging must
13867 take place before this function is called).
13868 Checks current arch version against that in the looked-up opcode. */
13871 do_vfp_nsyn_opcode (const char *opname
)
13873 const struct asm_opcode
*opcode
;
13875 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13881 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13888 inst
.instruction
= opcode
->tvalue
;
13889 opcode
->tencode ();
13893 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13894 opcode
->aencode ();
13899 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13901 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13906 do_vfp_nsyn_opcode ("fadds");
13908 do_vfp_nsyn_opcode ("fsubs");
13913 do_vfp_nsyn_opcode ("faddd");
13915 do_vfp_nsyn_opcode ("fsubd");
13919 /* Check operand types to see if this is a VFP instruction, and if so call
13923 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13925 enum neon_shape rs
;
13926 struct neon_type_el et
;
13931 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13932 et
= neon_check_type (2, rs
,
13933 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13937 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13938 et
= neon_check_type (3, rs
,
13939 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13946 if (et
.type
!= NT_invtype
)
13957 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13959 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13964 do_vfp_nsyn_opcode ("fmacs");
13966 do_vfp_nsyn_opcode ("fnmacs");
13971 do_vfp_nsyn_opcode ("fmacd");
13973 do_vfp_nsyn_opcode ("fnmacd");
13978 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13980 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13985 do_vfp_nsyn_opcode ("ffmas");
13987 do_vfp_nsyn_opcode ("ffnmas");
13992 do_vfp_nsyn_opcode ("ffmad");
13994 do_vfp_nsyn_opcode ("ffnmad");
13999 do_vfp_nsyn_mul (enum neon_shape rs
)
14002 do_vfp_nsyn_opcode ("fmuls");
14004 do_vfp_nsyn_opcode ("fmuld");
14008 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14010 int is_neg
= (inst
.instruction
& 0x80) != 0;
14011 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
14016 do_vfp_nsyn_opcode ("fnegs");
14018 do_vfp_nsyn_opcode ("fabss");
14023 do_vfp_nsyn_opcode ("fnegd");
14025 do_vfp_nsyn_opcode ("fabsd");
14029 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14030 insns belong to Neon, and are handled elsewhere. */
14033 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14035 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14039 do_vfp_nsyn_opcode ("fldmdbs");
14041 do_vfp_nsyn_opcode ("fldmias");
14046 do_vfp_nsyn_opcode ("fstmdbs");
14048 do_vfp_nsyn_opcode ("fstmias");
14053 do_vfp_nsyn_sqrt (void)
14055 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14056 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14059 do_vfp_nsyn_opcode ("fsqrts");
14061 do_vfp_nsyn_opcode ("fsqrtd");
14065 do_vfp_nsyn_div (void)
14067 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14068 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14069 N_F32
| N_F64
| N_KEY
| N_VFP
);
14072 do_vfp_nsyn_opcode ("fdivs");
14074 do_vfp_nsyn_opcode ("fdivd");
14078 do_vfp_nsyn_nmul (void)
14080 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14081 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14082 N_F32
| N_F64
| N_KEY
| N_VFP
);
14086 NEON_ENCODE (SINGLE
, inst
);
14087 do_vfp_sp_dyadic ();
14091 NEON_ENCODE (DOUBLE
, inst
);
14092 do_vfp_dp_rd_rn_rm ();
14094 do_vfp_cond_or_thumb ();
14098 do_vfp_nsyn_cmp (void)
14100 if (inst
.operands
[1].isreg
)
14102 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14103 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14107 NEON_ENCODE (SINGLE
, inst
);
14108 do_vfp_sp_monadic ();
14112 NEON_ENCODE (DOUBLE
, inst
);
14113 do_vfp_dp_rd_rm ();
14118 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14119 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14121 switch (inst
.instruction
& 0x0fffffff)
14124 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14127 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14135 NEON_ENCODE (SINGLE
, inst
);
14136 do_vfp_sp_compare_z ();
14140 NEON_ENCODE (DOUBLE
, inst
);
14144 do_vfp_cond_or_thumb ();
14148 nsyn_insert_sp (void)
14150 inst
.operands
[1] = inst
.operands
[0];
14151 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14152 inst
.operands
[0].reg
= REG_SP
;
14153 inst
.operands
[0].isreg
= 1;
14154 inst
.operands
[0].writeback
= 1;
14155 inst
.operands
[0].present
= 1;
14159 do_vfp_nsyn_push (void)
14162 if (inst
.operands
[1].issingle
)
14163 do_vfp_nsyn_opcode ("fstmdbs");
14165 do_vfp_nsyn_opcode ("fstmdbd");
14169 do_vfp_nsyn_pop (void)
14172 if (inst
.operands
[1].issingle
)
14173 do_vfp_nsyn_opcode ("fldmias");
14175 do_vfp_nsyn_opcode ("fldmiad");
14178 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14179 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14182 neon_dp_fixup (struct arm_it
* insn
)
14184 unsigned int i
= insn
->instruction
;
14189 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14200 insn
->instruction
= i
;
14203 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14207 neon_logbits (unsigned x
)
14209 return ffs (x
) - 4;
14212 #define LOW4(R) ((R) & 0xf)
14213 #define HI1(R) (((R) >> 4) & 1)
14215 /* Encode insns with bit pattern:
14217 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14218 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14220 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14221 different meaning for some instruction. */
14224 neon_three_same (int isquad
, int ubit
, int size
)
14226 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14227 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14228 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14229 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14230 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14231 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14232 inst
.instruction
|= (isquad
!= 0) << 6;
14233 inst
.instruction
|= (ubit
!= 0) << 24;
14235 inst
.instruction
|= neon_logbits (size
) << 20;
14237 neon_dp_fixup (&inst
);
14240 /* Encode instructions of the form:
14242 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14243 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14245 Don't write size if SIZE == -1. */
14248 neon_two_same (int qbit
, int ubit
, int size
)
14250 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14252 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14253 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14254 inst
.instruction
|= (qbit
!= 0) << 6;
14255 inst
.instruction
|= (ubit
!= 0) << 24;
14258 inst
.instruction
|= neon_logbits (size
) << 18;
14260 neon_dp_fixup (&inst
);
14263 /* Neon instruction encoders, in approximate order of appearance. */
14266 do_neon_dyadic_i_su (void)
14268 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14269 struct neon_type_el et
= neon_check_type (3, rs
,
14270 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14271 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14275 do_neon_dyadic_i64_su (void)
14277 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14278 struct neon_type_el et
= neon_check_type (3, rs
,
14279 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14280 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14284 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14287 unsigned size
= et
.size
>> 3;
14288 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14289 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14290 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14291 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14292 inst
.instruction
|= (isquad
!= 0) << 6;
14293 inst
.instruction
|= immbits
<< 16;
14294 inst
.instruction
|= (size
>> 3) << 7;
14295 inst
.instruction
|= (size
& 0x7) << 19;
14297 inst
.instruction
|= (uval
!= 0) << 24;
14299 neon_dp_fixup (&inst
);
14303 do_neon_shl_imm (void)
14305 if (!inst
.operands
[2].isreg
)
14307 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14308 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14309 int imm
= inst
.operands
[2].imm
;
14311 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14312 _("immediate out of range for shift"));
14313 NEON_ENCODE (IMMED
, inst
);
14314 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14318 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14319 struct neon_type_el et
= neon_check_type (3, rs
,
14320 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14323 /* VSHL/VQSHL 3-register variants have syntax such as:
14325 whereas other 3-register operations encoded by neon_three_same have
14328 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14330 tmp
= inst
.operands
[2].reg
;
14331 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14332 inst
.operands
[1].reg
= tmp
;
14333 NEON_ENCODE (INTEGER
, inst
);
14334 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14339 do_neon_qshl_imm (void)
14341 if (!inst
.operands
[2].isreg
)
14343 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14344 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14345 int imm
= inst
.operands
[2].imm
;
14347 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14348 _("immediate out of range for shift"));
14349 NEON_ENCODE (IMMED
, inst
);
14350 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14354 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14355 struct neon_type_el et
= neon_check_type (3, rs
,
14356 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14359 /* See note in do_neon_shl_imm. */
14360 tmp
= inst
.operands
[2].reg
;
14361 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14362 inst
.operands
[1].reg
= tmp
;
14363 NEON_ENCODE (INTEGER
, inst
);
14364 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14369 do_neon_rshl (void)
14371 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14372 struct neon_type_el et
= neon_check_type (3, rs
,
14373 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14376 tmp
= inst
.operands
[2].reg
;
14377 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14378 inst
.operands
[1].reg
= tmp
;
14379 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14383 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14385 /* Handle .I8 pseudo-instructions. */
14388 /* Unfortunately, this will make everything apart from zero out-of-range.
14389 FIXME is this the intended semantics? There doesn't seem much point in
14390 accepting .I8 if so. */
14391 immediate
|= immediate
<< 8;
14397 if (immediate
== (immediate
& 0x000000ff))
14399 *immbits
= immediate
;
14402 else if (immediate
== (immediate
& 0x0000ff00))
14404 *immbits
= immediate
>> 8;
14407 else if (immediate
== (immediate
& 0x00ff0000))
14409 *immbits
= immediate
>> 16;
14412 else if (immediate
== (immediate
& 0xff000000))
14414 *immbits
= immediate
>> 24;
14417 if ((immediate
& 0xffff) != (immediate
>> 16))
14418 goto bad_immediate
;
14419 immediate
&= 0xffff;
14422 if (immediate
== (immediate
& 0x000000ff))
14424 *immbits
= immediate
;
14427 else if (immediate
== (immediate
& 0x0000ff00))
14429 *immbits
= immediate
>> 8;
14434 first_error (_("immediate value out of range"));
14439 do_neon_logic (void)
14441 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14443 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14444 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14445 /* U bit and size field were set as part of the bitmask. */
14446 NEON_ENCODE (INTEGER
, inst
);
14447 neon_three_same (neon_quad (rs
), 0, -1);
14451 const int three_ops_form
= (inst
.operands
[2].present
14452 && !inst
.operands
[2].isreg
);
14453 const int immoperand
= (three_ops_form
? 2 : 1);
14454 enum neon_shape rs
= (three_ops_form
14455 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14456 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14457 struct neon_type_el et
= neon_check_type (2, rs
,
14458 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14459 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14463 if (et
.type
== NT_invtype
)
14466 if (three_ops_form
)
14467 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14468 _("first and second operands shall be the same register"));
14470 NEON_ENCODE (IMMED
, inst
);
14472 immbits
= inst
.operands
[immoperand
].imm
;
14475 /* .i64 is a pseudo-op, so the immediate must be a repeating
14477 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14478 inst
.operands
[immoperand
].reg
: 0))
14480 /* Set immbits to an invalid constant. */
14481 immbits
= 0xdeadbeef;
14488 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14492 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14496 /* Pseudo-instruction for VBIC. */
14497 neon_invert_size (&immbits
, 0, et
.size
);
14498 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14502 /* Pseudo-instruction for VORR. */
14503 neon_invert_size (&immbits
, 0, et
.size
);
14504 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14514 inst
.instruction
|= neon_quad (rs
) << 6;
14515 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14516 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14517 inst
.instruction
|= cmode
<< 8;
14518 neon_write_immbits (immbits
);
14520 neon_dp_fixup (&inst
);
14525 do_neon_bitfield (void)
14527 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14528 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14529 neon_three_same (neon_quad (rs
), 0, -1);
14533 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14536 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14537 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14539 if (et
.type
== NT_float
)
14541 NEON_ENCODE (FLOAT
, inst
);
14542 neon_three_same (neon_quad (rs
), 0, -1);
14546 NEON_ENCODE (INTEGER
, inst
);
14547 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14552 do_neon_dyadic_if_su (void)
14554 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14558 do_neon_dyadic_if_su_d (void)
14560 /* This version only allow D registers, but that constraint is enforced during
14561 operand parsing so we don't need to do anything extra here. */
14562 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14566 do_neon_dyadic_if_i_d (void)
14568 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14569 affected if we specify unsigned args. */
14570 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14573 enum vfp_or_neon_is_neon_bits
14576 NEON_CHECK_ARCH
= 2,
14577 NEON_CHECK_ARCH8
= 4
14580 /* Call this function if an instruction which may have belonged to the VFP or
14581 Neon instruction sets, but turned out to be a Neon instruction (due to the
14582 operand types involved, etc.). We have to check and/or fix-up a couple of
14585 - Make sure the user hasn't attempted to make a Neon instruction
14587 - Alter the value in the condition code field if necessary.
14588 - Make sure that the arch supports Neon instructions.
14590 Which of these operations take place depends on bits from enum
14591 vfp_or_neon_is_neon_bits.
14593 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14594 current instruction's condition is COND_ALWAYS, the condition field is
14595 changed to inst.uncond_value. This is necessary because instructions shared
14596 between VFP and Neon may be conditional for the VFP variants only, and the
14597 unconditional Neon version must have, e.g., 0xF in the condition field. */
14600 vfp_or_neon_is_neon (unsigned check
)
14602 /* Conditions are always legal in Thumb mode (IT blocks). */
14603 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14605 if (inst
.cond
!= COND_ALWAYS
)
14607 first_error (_(BAD_COND
));
14610 if (inst
.uncond_value
!= -1)
14611 inst
.instruction
|= inst
.uncond_value
<< 28;
14614 if ((check
& NEON_CHECK_ARCH
)
14615 && !mark_feature_used (&fpu_neon_ext_v1
))
14617 first_error (_(BAD_FPU
));
14621 if ((check
& NEON_CHECK_ARCH8
)
14622 && !mark_feature_used (&fpu_neon_ext_armv8
))
14624 first_error (_(BAD_FPU
));
14632 do_neon_addsub_if_i (void)
14634 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14637 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14640 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14641 affected if we specify unsigned args. */
14642 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14645 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14647 V<op> A,B (A is operand 0, B is operand 2)
14652 so handle that case specially. */
14655 neon_exchange_operands (void)
14657 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14658 if (inst
.operands
[1].present
)
14660 /* Swap operands[1] and operands[2]. */
14661 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14662 inst
.operands
[1] = inst
.operands
[2];
14663 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14667 inst
.operands
[1] = inst
.operands
[2];
14668 inst
.operands
[2] = inst
.operands
[0];
14673 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14675 if (inst
.operands
[2].isreg
)
14678 neon_exchange_operands ();
14679 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14683 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14684 struct neon_type_el et
= neon_check_type (2, rs
,
14685 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14687 NEON_ENCODE (IMMED
, inst
);
14688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14692 inst
.instruction
|= neon_quad (rs
) << 6;
14693 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14694 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14696 neon_dp_fixup (&inst
);
14703 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14707 do_neon_cmp_inv (void)
14709 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14715 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14718 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14719 scalars, which are encoded in 5 bits, M : Rm.
14720 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14721 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14725 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14727 unsigned regno
= NEON_SCALAR_REG (scalar
);
14728 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14733 if (regno
> 7 || elno
> 3)
14735 return regno
| (elno
<< 3);
14738 if (regno
> 15 || elno
> 1)
14740 return regno
| (elno
<< 4);
14744 first_error (_("scalar out of range for multiply instruction"));
14750 /* Encode multiply / multiply-accumulate scalar instructions. */
14753 neon_mul_mac (struct neon_type_el et
, int ubit
)
14757 /* Give a more helpful error message if we have an invalid type. */
14758 if (et
.type
== NT_invtype
)
14761 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14762 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14763 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14764 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14765 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14766 inst
.instruction
|= LOW4 (scalar
);
14767 inst
.instruction
|= HI1 (scalar
) << 5;
14768 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14769 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14770 inst
.instruction
|= (ubit
!= 0) << 24;
14772 neon_dp_fixup (&inst
);
14776 do_neon_mac_maybe_scalar (void)
14778 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14781 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14784 if (inst
.operands
[2].isscalar
)
14786 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14787 struct neon_type_el et
= neon_check_type (3, rs
,
14788 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14789 NEON_ENCODE (SCALAR
, inst
);
14790 neon_mul_mac (et
, neon_quad (rs
));
14794 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14795 affected if we specify unsigned args. */
14796 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14801 do_neon_fmac (void)
14803 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14806 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14809 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14815 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14816 struct neon_type_el et
= neon_check_type (3, rs
,
14817 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14818 neon_three_same (neon_quad (rs
), 0, et
.size
);
14821 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14822 same types as the MAC equivalents. The polynomial type for this instruction
14823 is encoded the same as the integer type. */
14828 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14831 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14834 if (inst
.operands
[2].isscalar
)
14835 do_neon_mac_maybe_scalar ();
14837 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14841 do_neon_qdmulh (void)
14843 if (inst
.operands
[2].isscalar
)
14845 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14846 struct neon_type_el et
= neon_check_type (3, rs
,
14847 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14848 NEON_ENCODE (SCALAR
, inst
);
14849 neon_mul_mac (et
, neon_quad (rs
));
14853 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14854 struct neon_type_el et
= neon_check_type (3, rs
,
14855 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14856 NEON_ENCODE (INTEGER
, inst
);
14857 /* The U bit (rounding) comes from bit mask. */
14858 neon_three_same (neon_quad (rs
), 0, et
.size
);
14863 do_neon_fcmp_absolute (void)
14865 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14866 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14867 /* Size field comes from bit mask. */
14868 neon_three_same (neon_quad (rs
), 1, -1);
14872 do_neon_fcmp_absolute_inv (void)
14874 neon_exchange_operands ();
14875 do_neon_fcmp_absolute ();
14879 do_neon_step (void)
14881 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14882 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14883 neon_three_same (neon_quad (rs
), 0, -1);
14887 do_neon_abs_neg (void)
14889 enum neon_shape rs
;
14890 struct neon_type_el et
;
14892 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14895 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14898 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14899 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14901 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14903 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14904 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14905 inst
.instruction
|= neon_quad (rs
) << 6;
14906 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14907 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14909 neon_dp_fixup (&inst
);
14915 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14916 struct neon_type_el et
= neon_check_type (2, rs
,
14917 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14918 int imm
= inst
.operands
[2].imm
;
14919 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14920 _("immediate out of range for insert"));
14921 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14927 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14928 struct neon_type_el et
= neon_check_type (2, rs
,
14929 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14930 int imm
= inst
.operands
[2].imm
;
14931 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14932 _("immediate out of range for insert"));
14933 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14937 do_neon_qshlu_imm (void)
14939 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14940 struct neon_type_el et
= neon_check_type (2, rs
,
14941 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14942 int imm
= inst
.operands
[2].imm
;
14943 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14944 _("immediate out of range for shift"));
14945 /* Only encodes the 'U present' variant of the instruction.
14946 In this case, signed types have OP (bit 8) set to 0.
14947 Unsigned types have OP set to 1. */
14948 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14949 /* The rest of the bits are the same as other immediate shifts. */
14950 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14954 do_neon_qmovn (void)
14956 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14957 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14958 /* Saturating move where operands can be signed or unsigned, and the
14959 destination has the same signedness. */
14960 NEON_ENCODE (INTEGER
, inst
);
14961 if (et
.type
== NT_unsigned
)
14962 inst
.instruction
|= 0xc0;
14964 inst
.instruction
|= 0x80;
14965 neon_two_same (0, 1, et
.size
/ 2);
14969 do_neon_qmovun (void)
14971 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14972 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14973 /* Saturating move with unsigned results. Operands must be signed. */
14974 NEON_ENCODE (INTEGER
, inst
);
14975 neon_two_same (0, 1, et
.size
/ 2);
14979 do_neon_rshift_sat_narrow (void)
14981 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14982 or unsigned. If operands are unsigned, results must also be unsigned. */
14983 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14984 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14985 int imm
= inst
.operands
[2].imm
;
14986 /* This gets the bounds check, size encoding and immediate bits calculation
14990 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14991 VQMOVN.I<size> <Dd>, <Qm>. */
14994 inst
.operands
[2].present
= 0;
14995 inst
.instruction
= N_MNEM_vqmovn
;
15000 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15001 _("immediate out of range"));
15002 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15006 do_neon_rshift_sat_narrow_u (void)
15008 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15009 or unsigned. If operands are unsigned, results must also be unsigned. */
15010 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15011 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15012 int imm
= inst
.operands
[2].imm
;
15013 /* This gets the bounds check, size encoding and immediate bits calculation
15017 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15018 VQMOVUN.I<size> <Dd>, <Qm>. */
15021 inst
.operands
[2].present
= 0;
15022 inst
.instruction
= N_MNEM_vqmovun
;
15027 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15028 _("immediate out of range"));
15029 /* FIXME: The manual is kind of unclear about what value U should have in
15030 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15032 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15036 do_neon_movn (void)
15038 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15039 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15040 NEON_ENCODE (INTEGER
, inst
);
15041 neon_two_same (0, 1, et
.size
/ 2);
15045 do_neon_rshift_narrow (void)
15047 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15048 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15049 int imm
= inst
.operands
[2].imm
;
15050 /* This gets the bounds check, size encoding and immediate bits calculation
15054 /* If immediate is zero then we are a pseudo-instruction for
15055 VMOVN.I<size> <Dd>, <Qm> */
15058 inst
.operands
[2].present
= 0;
15059 inst
.instruction
= N_MNEM_vmovn
;
15064 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15065 _("immediate out of range for narrowing operation"));
15066 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15070 do_neon_shll (void)
15072 /* FIXME: Type checking when lengthening. */
15073 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15074 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15075 unsigned imm
= inst
.operands
[2].imm
;
15077 if (imm
== et
.size
)
15079 /* Maximum shift variant. */
15080 NEON_ENCODE (INTEGER
, inst
);
15081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15085 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15087 neon_dp_fixup (&inst
);
15091 /* A more-specific type check for non-max versions. */
15092 et
= neon_check_type (2, NS_QDI
,
15093 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15094 NEON_ENCODE (IMMED
, inst
);
15095 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15099 /* Check the various types for the VCVT instruction, and return which version
15100 the current instruction is. */
15102 #define CVT_FLAVOUR_VAR \
15103 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15104 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15105 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15106 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15107 /* Half-precision conversions. */ \
15108 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15109 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15110 /* VFP instructions. */ \
15111 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15112 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15113 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15114 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15115 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15116 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15117 /* VFP instructions with bitshift. */ \
15118 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15119 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15120 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15121 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15122 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15123 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15124 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15125 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15127 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15128 neon_cvt_flavour_##C,
15130 /* The different types of conversions we can do. */
15131 enum neon_cvt_flavour
15134 neon_cvt_flavour_invalid
,
15135 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15140 static enum neon_cvt_flavour
15141 get_neon_cvt_flavour (enum neon_shape rs
)
15143 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15144 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15145 if (et.type != NT_invtype) \
15147 inst.error = NULL; \
15148 return (neon_cvt_flavour_##C); \
15151 struct neon_type_el et
;
15152 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15153 || rs
== NS_FF
) ? N_VFP
: 0;
15154 /* The instruction versions which take an immediate take one register
15155 argument, which is extended to the width of the full register. Thus the
15156 "source" and "destination" registers must have the same width. Hack that
15157 here by making the size equal to the key (wider, in this case) operand. */
15158 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15162 return neon_cvt_flavour_invalid
;
15177 /* Neon-syntax VFP conversions. */
15180 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15182 const char *opname
= 0;
15184 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15186 /* Conversions with immediate bitshift. */
15187 const char *enc
[] =
15189 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15195 if (flavour
< (int) ARRAY_SIZE (enc
))
15197 opname
= enc
[flavour
];
15198 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15199 _("operands 0 and 1 must be the same register"));
15200 inst
.operands
[1] = inst
.operands
[2];
15201 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15206 /* Conversions without bitshift. */
15207 const char *enc
[] =
15209 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15215 if (flavour
< (int) ARRAY_SIZE (enc
))
15216 opname
= enc
[flavour
];
15220 do_vfp_nsyn_opcode (opname
);
15224 do_vfp_nsyn_cvtz (void)
15226 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15227 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15228 const char *enc
[] =
15230 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15236 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15237 do_vfp_nsyn_opcode (enc
[flavour
]);
15241 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15242 enum neon_cvt_mode mode
)
15247 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15248 D register operands. */
15249 if (flavour
== neon_cvt_flavour_s32_f64
15250 || flavour
== neon_cvt_flavour_u32_f64
)
15251 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15254 set_it_insn_type (OUTSIDE_IT_INSN
);
15258 case neon_cvt_flavour_s32_f64
:
15262 case neon_cvt_flavour_s32_f32
:
15266 case neon_cvt_flavour_u32_f64
:
15270 case neon_cvt_flavour_u32_f32
:
15275 first_error (_("invalid instruction shape"));
15281 case neon_cvt_mode_a
: rm
= 0; break;
15282 case neon_cvt_mode_n
: rm
= 1; break;
15283 case neon_cvt_mode_p
: rm
= 2; break;
15284 case neon_cvt_mode_m
: rm
= 3; break;
15285 default: first_error (_("invalid rounding mode")); return;
15288 NEON_ENCODE (FPV8
, inst
);
15289 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15290 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15291 inst
.instruction
|= sz
<< 8;
15292 inst
.instruction
|= op
<< 7;
15293 inst
.instruction
|= rm
<< 16;
15294 inst
.instruction
|= 0xf0000000;
15295 inst
.is_neon
= TRUE
;
15299 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15301 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15302 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15303 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15305 /* PR11109: Handle round-to-zero for VCVT conversions. */
15306 if (mode
== neon_cvt_mode_z
15307 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15308 && (flavour
== neon_cvt_flavour_s32_f32
15309 || flavour
== neon_cvt_flavour_u32_f32
15310 || flavour
== neon_cvt_flavour_s32_f64
15311 || flavour
== neon_cvt_flavour_u32_f64
)
15312 && (rs
== NS_FD
|| rs
== NS_FF
))
15314 do_vfp_nsyn_cvtz ();
15318 /* VFP rather than Neon conversions. */
15319 if (flavour
>= neon_cvt_flavour_first_fp
)
15321 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15322 do_vfp_nsyn_cvt (rs
, flavour
);
15324 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15335 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15337 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15340 /* Fixed-point conversion with #0 immediate is encoded as an
15341 integer conversion. */
15342 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15344 immbits
= 32 - inst
.operands
[2].imm
;
15345 NEON_ENCODE (IMMED
, inst
);
15346 if (flavour
!= neon_cvt_flavour_invalid
)
15347 inst
.instruction
|= enctab
[flavour
];
15348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15350 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15351 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15352 inst
.instruction
|= neon_quad (rs
) << 6;
15353 inst
.instruction
|= 1 << 21;
15354 inst
.instruction
|= immbits
<< 16;
15356 neon_dp_fixup (&inst
);
15362 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15364 NEON_ENCODE (FLOAT
, inst
);
15365 set_it_insn_type (OUTSIDE_IT_INSN
);
15367 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15370 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15371 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15372 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15373 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15374 inst
.instruction
|= neon_quad (rs
) << 6;
15375 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15376 inst
.instruction
|= mode
<< 8;
15378 inst
.instruction
|= 0xfc000000;
15380 inst
.instruction
|= 0xf0000000;
15386 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15388 NEON_ENCODE (INTEGER
, inst
);
15390 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15393 if (flavour
!= neon_cvt_flavour_invalid
)
15394 inst
.instruction
|= enctab
[flavour
];
15396 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15397 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15398 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15399 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15400 inst
.instruction
|= neon_quad (rs
) << 6;
15401 inst
.instruction
|= 2 << 18;
15403 neon_dp_fixup (&inst
);
15408 /* Half-precision conversions for Advanced SIMD -- neon. */
15413 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15415 as_bad (_("operand size must match register width"));
15420 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15422 as_bad (_("operand size must match register width"));
15427 inst
.instruction
= 0x3b60600;
15429 inst
.instruction
= 0x3b60700;
15431 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15434 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15435 neon_dp_fixup (&inst
);
15439 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15440 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15441 do_vfp_nsyn_cvt (rs
, flavour
);
15443 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15448 do_neon_cvtr (void)
15450 do_neon_cvt_1 (neon_cvt_mode_x
);
15456 do_neon_cvt_1 (neon_cvt_mode_z
);
15460 do_neon_cvta (void)
15462 do_neon_cvt_1 (neon_cvt_mode_a
);
15466 do_neon_cvtn (void)
15468 do_neon_cvt_1 (neon_cvt_mode_n
);
15472 do_neon_cvtp (void)
15474 do_neon_cvt_1 (neon_cvt_mode_p
);
15478 do_neon_cvtm (void)
15480 do_neon_cvt_1 (neon_cvt_mode_m
);
15484 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15487 mark_feature_used (&fpu_vfp_ext_armv8
);
15489 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15490 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15491 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15492 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15493 inst
.instruction
|= to
? 0x10000 : 0;
15494 inst
.instruction
|= t
? 0x80 : 0;
15495 inst
.instruction
|= is_double
? 0x100 : 0;
15496 do_vfp_cond_or_thumb ();
15500 do_neon_cvttb_1 (bfd_boolean t
)
15502 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15506 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15509 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15511 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15514 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15516 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15518 /* The VCVTB and VCVTT instructions with D-register operands
15519 don't work for SP only targets. */
15520 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15524 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15526 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15528 /* The VCVTB and VCVTT instructions with D-register operands
15529 don't work for SP only targets. */
15530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15534 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15541 do_neon_cvtb (void)
15543 do_neon_cvttb_1 (FALSE
);
15548 do_neon_cvtt (void)
15550 do_neon_cvttb_1 (TRUE
);
15554 neon_move_immediate (void)
15556 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15557 struct neon_type_el et
= neon_check_type (2, rs
,
15558 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15559 unsigned immlo
, immhi
= 0, immbits
;
15560 int op
, cmode
, float_p
;
15562 constraint (et
.type
== NT_invtype
,
15563 _("operand size must be specified for immediate VMOV"));
15565 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15566 op
= (inst
.instruction
& (1 << 5)) != 0;
15568 immlo
= inst
.operands
[1].imm
;
15569 if (inst
.operands
[1].regisimm
)
15570 immhi
= inst
.operands
[1].reg
;
15572 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15573 _("immediate has bits set outside the operand size"));
15575 float_p
= inst
.operands
[1].immisfloat
;
15577 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15578 et
.size
, et
.type
)) == FAIL
)
15580 /* Invert relevant bits only. */
15581 neon_invert_size (&immlo
, &immhi
, et
.size
);
15582 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15583 with one or the other; those cases are caught by
15584 neon_cmode_for_move_imm. */
15586 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15587 &op
, et
.size
, et
.type
)) == FAIL
)
15589 first_error (_("immediate out of range"));
15594 inst
.instruction
&= ~(1 << 5);
15595 inst
.instruction
|= op
<< 5;
15597 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15598 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15599 inst
.instruction
|= neon_quad (rs
) << 6;
15600 inst
.instruction
|= cmode
<< 8;
15602 neon_write_immbits (immbits
);
15608 if (inst
.operands
[1].isreg
)
15610 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15612 NEON_ENCODE (INTEGER
, inst
);
15613 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15614 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15617 inst
.instruction
|= neon_quad (rs
) << 6;
15621 NEON_ENCODE (IMMED
, inst
);
15622 neon_move_immediate ();
15625 neon_dp_fixup (&inst
);
15628 /* Encode instructions of form:
15630 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15631 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15634 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15636 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15637 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15639 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15640 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15641 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15642 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15643 inst
.instruction
|= neon_logbits (size
) << 20;
15645 neon_dp_fixup (&inst
);
15649 do_neon_dyadic_long (void)
15651 /* FIXME: Type checking for lengthening op. */
15652 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15653 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15654 neon_mixed_length (et
, et
.size
);
15658 do_neon_abal (void)
15660 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15661 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15662 neon_mixed_length (et
, et
.size
);
15666 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15668 if (inst
.operands
[2].isscalar
)
15670 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15671 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15672 NEON_ENCODE (SCALAR
, inst
);
15673 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15677 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15678 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15679 NEON_ENCODE (INTEGER
, inst
);
15680 neon_mixed_length (et
, et
.size
);
15685 do_neon_mac_maybe_scalar_long (void)
15687 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15691 do_neon_dyadic_wide (void)
15693 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15694 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15695 neon_mixed_length (et
, et
.size
);
15699 do_neon_dyadic_narrow (void)
15701 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15702 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15703 /* Operand sign is unimportant, and the U bit is part of the opcode,
15704 so force the operand type to integer. */
15705 et
.type
= NT_integer
;
15706 neon_mixed_length (et
, et
.size
/ 2);
15710 do_neon_mul_sat_scalar_long (void)
15712 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15716 do_neon_vmull (void)
15718 if (inst
.operands
[2].isscalar
)
15719 do_neon_mac_maybe_scalar_long ();
15722 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15723 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15725 if (et
.type
== NT_poly
)
15726 NEON_ENCODE (POLY
, inst
);
15728 NEON_ENCODE (INTEGER
, inst
);
15730 /* For polynomial encoding the U bit must be zero, and the size must
15731 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15732 obviously, as 0b10). */
15735 /* Check we're on the correct architecture. */
15736 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15738 _("Instruction form not available on this architecture.");
15743 neon_mixed_length (et
, et
.size
);
15750 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15751 struct neon_type_el et
= neon_check_type (3, rs
,
15752 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15753 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15755 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15756 _("shift out of range"));
15757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15758 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15760 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15761 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15762 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15763 inst
.instruction
|= neon_quad (rs
) << 6;
15764 inst
.instruction
|= imm
<< 8;
15766 neon_dp_fixup (&inst
);
15772 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15773 struct neon_type_el et
= neon_check_type (2, rs
,
15774 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15775 unsigned op
= (inst
.instruction
>> 7) & 3;
15776 /* N (width of reversed regions) is encoded as part of the bitmask. We
15777 extract it here to check the elements to be reversed are smaller.
15778 Otherwise we'd get a reserved instruction. */
15779 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15780 gas_assert (elsize
!= 0);
15781 constraint (et
.size
>= elsize
,
15782 _("elements must be smaller than reversal region"));
15783 neon_two_same (neon_quad (rs
), 1, et
.size
);
15789 if (inst
.operands
[1].isscalar
)
15791 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15792 struct neon_type_el et
= neon_check_type (2, rs
,
15793 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15794 unsigned sizebits
= et
.size
>> 3;
15795 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15796 int logsize
= neon_logbits (et
.size
);
15797 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15799 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15802 NEON_ENCODE (SCALAR
, inst
);
15803 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15804 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15805 inst
.instruction
|= LOW4 (dm
);
15806 inst
.instruction
|= HI1 (dm
) << 5;
15807 inst
.instruction
|= neon_quad (rs
) << 6;
15808 inst
.instruction
|= x
<< 17;
15809 inst
.instruction
|= sizebits
<< 16;
15811 neon_dp_fixup (&inst
);
15815 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15816 struct neon_type_el et
= neon_check_type (2, rs
,
15817 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15818 /* Duplicate ARM register to lanes of vector. */
15819 NEON_ENCODE (ARMREG
, inst
);
15822 case 8: inst
.instruction
|= 0x400000; break;
15823 case 16: inst
.instruction
|= 0x000020; break;
15824 case 32: inst
.instruction
|= 0x000000; break;
15827 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15828 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15829 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15830 inst
.instruction
|= neon_quad (rs
) << 21;
15831 /* The encoding for this instruction is identical for the ARM and Thumb
15832 variants, except for the condition field. */
15833 do_vfp_cond_or_thumb ();
15837 /* VMOV has particularly many variations. It can be one of:
15838 0. VMOV<c><q> <Qd>, <Qm>
15839 1. VMOV<c><q> <Dd>, <Dm>
15840 (Register operations, which are VORR with Rm = Rn.)
15841 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15842 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15844 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15845 (ARM register to scalar.)
15846 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15847 (Two ARM registers to vector.)
15848 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15849 (Scalar to ARM register.)
15850 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15851 (Vector to two ARM registers.)
15852 8. VMOV.F32 <Sd>, <Sm>
15853 9. VMOV.F64 <Dd>, <Dm>
15854 (VFP register moves.)
15855 10. VMOV.F32 <Sd>, #imm
15856 11. VMOV.F64 <Dd>, #imm
15857 (VFP float immediate load.)
15858 12. VMOV <Rd>, <Sm>
15859 (VFP single to ARM reg.)
15860 13. VMOV <Sd>, <Rm>
15861 (ARM reg to VFP single.)
15862 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15863 (Two ARM regs to two VFP singles.)
15864 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15865 (Two VFP singles to two ARM regs.)
15867 These cases can be disambiguated using neon_select_shape, except cases 1/9
15868 and 3/11 which depend on the operand type too.
15870 All the encoded bits are hardcoded by this function.
15872 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15873 Cases 5, 7 may be used with VFPv2 and above.
15875 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15876 can specify a type where it doesn't make sense to, and is ignored). */
15881 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15882 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15884 struct neon_type_el et
;
15885 const char *ldconst
= 0;
15889 case NS_DD
: /* case 1/9. */
15890 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15891 /* It is not an error here if no type is given. */
15893 if (et
.type
== NT_float
&& et
.size
== 64)
15895 do_vfp_nsyn_opcode ("fcpyd");
15898 /* fall through. */
15900 case NS_QQ
: /* case 0/1. */
15902 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15904 /* The architecture manual I have doesn't explicitly state which
15905 value the U bit should have for register->register moves, but
15906 the equivalent VORR instruction has U = 0, so do that. */
15907 inst
.instruction
= 0x0200110;
15908 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15909 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15910 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15911 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15912 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15913 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15914 inst
.instruction
|= neon_quad (rs
) << 6;
15916 neon_dp_fixup (&inst
);
15920 case NS_DI
: /* case 3/11. */
15921 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15923 if (et
.type
== NT_float
&& et
.size
== 64)
15925 /* case 11 (fconstd). */
15926 ldconst
= "fconstd";
15927 goto encode_fconstd
;
15929 /* fall through. */
15931 case NS_QI
: /* case 2/3. */
15932 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15934 inst
.instruction
= 0x0800010;
15935 neon_move_immediate ();
15936 neon_dp_fixup (&inst
);
15939 case NS_SR
: /* case 4. */
15941 unsigned bcdebits
= 0;
15943 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15944 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15946 /* .<size> is optional here, defaulting to .32. */
15947 if (inst
.vectype
.elems
== 0
15948 && inst
.operands
[0].vectype
.type
== NT_invtype
15949 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15951 inst
.vectype
.el
[0].type
= NT_untyped
;
15952 inst
.vectype
.el
[0].size
= 32;
15953 inst
.vectype
.elems
= 1;
15956 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15957 logsize
= neon_logbits (et
.size
);
15959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15962 && et
.size
!= 32, _(BAD_FPU
));
15963 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15964 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15968 case 8: bcdebits
= 0x8; break;
15969 case 16: bcdebits
= 0x1; break;
15970 case 32: bcdebits
= 0x0; break;
15974 bcdebits
|= x
<< logsize
;
15976 inst
.instruction
= 0xe000b10;
15977 do_vfp_cond_or_thumb ();
15978 inst
.instruction
|= LOW4 (dn
) << 16;
15979 inst
.instruction
|= HI1 (dn
) << 7;
15980 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15981 inst
.instruction
|= (bcdebits
& 3) << 5;
15982 inst
.instruction
|= (bcdebits
>> 2) << 21;
15986 case NS_DRR
: /* case 5 (fmdrr). */
15987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15990 inst
.instruction
= 0xc400b10;
15991 do_vfp_cond_or_thumb ();
15992 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15993 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15994 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15995 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15998 case NS_RS
: /* case 6. */
16001 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16002 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16003 unsigned abcdebits
= 0;
16005 /* .<dt> is optional here, defaulting to .32. */
16006 if (inst
.vectype
.elems
== 0
16007 && inst
.operands
[0].vectype
.type
== NT_invtype
16008 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16010 inst
.vectype
.el
[0].type
= NT_untyped
;
16011 inst
.vectype
.el
[0].size
= 32;
16012 inst
.vectype
.elems
= 1;
16015 et
= neon_check_type (2, NS_NULL
,
16016 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16017 logsize
= neon_logbits (et
.size
);
16019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16021 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16022 && et
.size
!= 32, _(BAD_FPU
));
16023 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16024 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16028 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16029 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16030 case 32: abcdebits
= 0x00; break;
16034 abcdebits
|= x
<< logsize
;
16035 inst
.instruction
= 0xe100b10;
16036 do_vfp_cond_or_thumb ();
16037 inst
.instruction
|= LOW4 (dn
) << 16;
16038 inst
.instruction
|= HI1 (dn
) << 7;
16039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16040 inst
.instruction
|= (abcdebits
& 3) << 5;
16041 inst
.instruction
|= (abcdebits
>> 2) << 21;
16045 case NS_RRD
: /* case 7 (fmrrd). */
16046 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16049 inst
.instruction
= 0xc500b10;
16050 do_vfp_cond_or_thumb ();
16051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16052 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16053 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16054 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16057 case NS_FF
: /* case 8 (fcpys). */
16058 do_vfp_nsyn_opcode ("fcpys");
16061 case NS_FI
: /* case 10 (fconsts). */
16062 ldconst
= "fconsts";
16064 if (is_quarter_float (inst
.operands
[1].imm
))
16066 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16067 do_vfp_nsyn_opcode (ldconst
);
16070 first_error (_("immediate out of range"));
16073 case NS_RF
: /* case 12 (fmrs). */
16074 do_vfp_nsyn_opcode ("fmrs");
16077 case NS_FR
: /* case 13 (fmsr). */
16078 do_vfp_nsyn_opcode ("fmsr");
16081 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16082 (one of which is a list), but we have parsed four. Do some fiddling to
16083 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16085 case NS_RRFF
: /* case 14 (fmrrs). */
16086 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16087 _("VFP registers must be adjacent"));
16088 inst
.operands
[2].imm
= 2;
16089 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16090 do_vfp_nsyn_opcode ("fmrrs");
16093 case NS_FFRR
: /* case 15 (fmsrr). */
16094 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16095 _("VFP registers must be adjacent"));
16096 inst
.operands
[1] = inst
.operands
[2];
16097 inst
.operands
[2] = inst
.operands
[3];
16098 inst
.operands
[0].imm
= 2;
16099 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16100 do_vfp_nsyn_opcode ("fmsrr");
16104 /* neon_select_shape has determined that the instruction
16105 shape is wrong and has already set the error message. */
16114 do_neon_rshift_round_imm (void)
16116 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16117 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16118 int imm
= inst
.operands
[2].imm
;
16120 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16123 inst
.operands
[2].present
= 0;
16128 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16129 _("immediate out of range for shift"));
16130 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16135 do_neon_movl (void)
16137 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16138 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16139 unsigned sizebits
= et
.size
>> 3;
16140 inst
.instruction
|= sizebits
<< 19;
16141 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16147 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16148 struct neon_type_el et
= neon_check_type (2, rs
,
16149 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16150 NEON_ENCODE (INTEGER
, inst
);
16151 neon_two_same (neon_quad (rs
), 1, et
.size
);
16155 do_neon_zip_uzp (void)
16157 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16158 struct neon_type_el et
= neon_check_type (2, rs
,
16159 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16160 if (rs
== NS_DD
&& et
.size
== 32)
16162 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16163 inst
.instruction
= N_MNEM_vtrn
;
16167 neon_two_same (neon_quad (rs
), 1, et
.size
);
16171 do_neon_sat_abs_neg (void)
16173 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16174 struct neon_type_el et
= neon_check_type (2, rs
,
16175 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16176 neon_two_same (neon_quad (rs
), 1, et
.size
);
16180 do_neon_pair_long (void)
16182 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16183 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16184 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16185 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16186 neon_two_same (neon_quad (rs
), 1, et
.size
);
16190 do_neon_recip_est (void)
16192 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16193 struct neon_type_el et
= neon_check_type (2, rs
,
16194 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16195 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16196 neon_two_same (neon_quad (rs
), 1, et
.size
);
16202 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16203 struct neon_type_el et
= neon_check_type (2, rs
,
16204 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16205 neon_two_same (neon_quad (rs
), 1, et
.size
);
16211 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16212 struct neon_type_el et
= neon_check_type (2, rs
,
16213 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16214 neon_two_same (neon_quad (rs
), 1, et
.size
);
16220 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16221 struct neon_type_el et
= neon_check_type (2, rs
,
16222 N_EQK
| N_INT
, N_8
| N_KEY
);
16223 neon_two_same (neon_quad (rs
), 1, et
.size
);
16229 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16230 neon_two_same (neon_quad (rs
), 1, -1);
16234 do_neon_tbl_tbx (void)
16236 unsigned listlenbits
;
16237 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16239 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16241 first_error (_("bad list length for table lookup"));
16245 listlenbits
= inst
.operands
[1].imm
- 1;
16246 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16247 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16248 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16249 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16250 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16251 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16252 inst
.instruction
|= listlenbits
<< 8;
16254 neon_dp_fixup (&inst
);
16258 do_neon_ldm_stm (void)
16260 /* P, U and L bits are part of bitmask. */
16261 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16262 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16264 if (inst
.operands
[1].issingle
)
16266 do_vfp_nsyn_ldm_stm (is_dbmode
);
16270 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16271 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16273 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16274 _("register list must contain at least 1 and at most 16 "
16277 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16278 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16279 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16280 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16282 inst
.instruction
|= offsetbits
;
16284 do_vfp_cond_or_thumb ();
16288 do_neon_ldr_str (void)
16290 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16292 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16293 And is UNPREDICTABLE in thumb mode. */
16295 && inst
.operands
[1].reg
== REG_PC
16296 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16299 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16300 else if (warn_on_deprecated
)
16301 as_tsktsk (_("Use of PC here is deprecated"));
16304 if (inst
.operands
[0].issingle
)
16307 do_vfp_nsyn_opcode ("flds");
16309 do_vfp_nsyn_opcode ("fsts");
16314 do_vfp_nsyn_opcode ("fldd");
16316 do_vfp_nsyn_opcode ("fstd");
16320 /* "interleave" version also handles non-interleaving register VLD1/VST1
16324 do_neon_ld_st_interleave (void)
16326 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16327 N_8
| N_16
| N_32
| N_64
);
16328 unsigned alignbits
= 0;
16330 /* The bits in this table go:
16331 0: register stride of one (0) or two (1)
16332 1,2: register list length, minus one (1, 2, 3, 4).
16333 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16334 We use -1 for invalid entries. */
16335 const int typetable
[] =
16337 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16338 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16339 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16340 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16344 if (et
.type
== NT_invtype
)
16347 if (inst
.operands
[1].immisalign
)
16348 switch (inst
.operands
[1].imm
>> 8)
16350 case 64: alignbits
= 1; break;
16352 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16353 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16354 goto bad_alignment
;
16358 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16359 goto bad_alignment
;
16364 first_error (_("bad alignment"));
16368 inst
.instruction
|= alignbits
<< 4;
16369 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16371 /* Bits [4:6] of the immediate in a list specifier encode register stride
16372 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16373 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16374 up the right value for "type" in a table based on this value and the given
16375 list style, then stick it back. */
16376 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16377 | (((inst
.instruction
>> 8) & 3) << 3);
16379 typebits
= typetable
[idx
];
16381 constraint (typebits
== -1, _("bad list type for instruction"));
16382 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16383 _("bad element type for instruction"));
16385 inst
.instruction
&= ~0xf00;
16386 inst
.instruction
|= typebits
<< 8;
16389 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16390 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16391 otherwise. The variable arguments are a list of pairs of legal (size, align)
16392 values, terminated with -1. */
16395 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16398 int result
= FAIL
, thissize
, thisalign
;
16400 if (!inst
.operands
[1].immisalign
)
16406 va_start (ap
, do_align
);
16410 thissize
= va_arg (ap
, int);
16411 if (thissize
== -1)
16413 thisalign
= va_arg (ap
, int);
16415 if (size
== thissize
&& align
== thisalign
)
16418 while (result
!= SUCCESS
);
16422 if (result
== SUCCESS
)
16425 first_error (_("unsupported alignment for instruction"));
16431 do_neon_ld_st_lane (void)
16433 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16434 int align_good
, do_align
= 0;
16435 int logsize
= neon_logbits (et
.size
);
16436 int align
= inst
.operands
[1].imm
>> 8;
16437 int n
= (inst
.instruction
>> 8) & 3;
16438 int max_el
= 64 / et
.size
;
16440 if (et
.type
== NT_invtype
)
16443 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16444 _("bad list length"));
16445 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16446 _("scalar index out of range"));
16447 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16449 _("stride of 2 unavailable when element size is 8"));
16453 case 0: /* VLD1 / VST1. */
16454 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16456 if (align_good
== FAIL
)
16460 unsigned alignbits
= 0;
16463 case 16: alignbits
= 0x1; break;
16464 case 32: alignbits
= 0x3; break;
16467 inst
.instruction
|= alignbits
<< 4;
16471 case 1: /* VLD2 / VST2. */
16472 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16474 if (align_good
== FAIL
)
16477 inst
.instruction
|= 1 << 4;
16480 case 2: /* VLD3 / VST3. */
16481 constraint (inst
.operands
[1].immisalign
,
16482 _("can't use alignment with this instruction"));
16485 case 3: /* VLD4 / VST4. */
16486 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16487 16, 64, 32, 64, 32, 128, -1);
16488 if (align_good
== FAIL
)
16492 unsigned alignbits
= 0;
16495 case 8: alignbits
= 0x1; break;
16496 case 16: alignbits
= 0x1; break;
16497 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16500 inst
.instruction
|= alignbits
<< 4;
16507 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16508 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16509 inst
.instruction
|= 1 << (4 + logsize
);
16511 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16512 inst
.instruction
|= logsize
<< 10;
16515 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16518 do_neon_ld_dup (void)
16520 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16521 int align_good
, do_align
= 0;
16523 if (et
.type
== NT_invtype
)
16526 switch ((inst
.instruction
>> 8) & 3)
16528 case 0: /* VLD1. */
16529 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16530 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16531 &do_align
, 16, 16, 32, 32, -1);
16532 if (align_good
== FAIL
)
16534 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16537 case 2: inst
.instruction
|= 1 << 5; break;
16538 default: first_error (_("bad list length")); return;
16540 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16543 case 1: /* VLD2. */
16544 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16545 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16546 if (align_good
== FAIL
)
16548 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16549 _("bad list length"));
16550 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16551 inst
.instruction
|= 1 << 5;
16552 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16555 case 2: /* VLD3. */
16556 constraint (inst
.operands
[1].immisalign
,
16557 _("can't use alignment with this instruction"));
16558 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16559 _("bad list length"));
16560 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16561 inst
.instruction
|= 1 << 5;
16562 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16565 case 3: /* VLD4. */
16567 int align
= inst
.operands
[1].imm
>> 8;
16568 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16569 16, 64, 32, 64, 32, 128, -1);
16570 if (align_good
== FAIL
)
16572 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16573 _("bad list length"));
16574 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16575 inst
.instruction
|= 1 << 5;
16576 if (et
.size
== 32 && align
== 128)
16577 inst
.instruction
|= 0x3 << 6;
16579 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16586 inst
.instruction
|= do_align
<< 4;
16589 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16590 apart from bits [11:4]. */
16593 do_neon_ldx_stx (void)
16595 if (inst
.operands
[1].isreg
)
16596 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16598 switch (NEON_LANE (inst
.operands
[0].imm
))
16600 case NEON_INTERLEAVE_LANES
:
16601 NEON_ENCODE (INTERLV
, inst
);
16602 do_neon_ld_st_interleave ();
16605 case NEON_ALL_LANES
:
16606 NEON_ENCODE (DUP
, inst
);
16607 if (inst
.instruction
== N_INV
)
16609 first_error ("only loads support such operands");
16616 NEON_ENCODE (LANE
, inst
);
16617 do_neon_ld_st_lane ();
16620 /* L bit comes from bit mask. */
16621 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16622 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16623 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16625 if (inst
.operands
[1].postind
)
16627 int postreg
= inst
.operands
[1].imm
& 0xf;
16628 constraint (!inst
.operands
[1].immisreg
,
16629 _("post-index must be a register"));
16630 constraint (postreg
== 0xd || postreg
== 0xf,
16631 _("bad register for post-index"));
16632 inst
.instruction
|= postreg
;
16636 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16637 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16638 || inst
.reloc
.exp
.X_add_number
!= 0,
16641 if (inst
.operands
[1].writeback
)
16643 inst
.instruction
|= 0xd;
16646 inst
.instruction
|= 0xf;
16650 inst
.instruction
|= 0xf9000000;
16652 inst
.instruction
|= 0xf4000000;
16657 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16659 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16660 D register operands. */
16661 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16662 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16665 NEON_ENCODE (FPV8
, inst
);
16668 do_vfp_sp_dyadic ();
16670 do_vfp_dp_rd_rn_rm ();
16673 inst
.instruction
|= 0x100;
16675 inst
.instruction
|= 0xf0000000;
16681 set_it_insn_type (OUTSIDE_IT_INSN
);
16683 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16684 first_error (_("invalid instruction shape"));
16690 set_it_insn_type (OUTSIDE_IT_INSN
);
16692 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16695 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16698 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16702 do_vrint_1 (enum neon_cvt_mode mode
)
16704 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16705 struct neon_type_el et
;
16710 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16711 D register operands. */
16712 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16713 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16716 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16717 if (et
.type
!= NT_invtype
)
16719 /* VFP encodings. */
16720 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16721 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16722 set_it_insn_type (OUTSIDE_IT_INSN
);
16724 NEON_ENCODE (FPV8
, inst
);
16726 do_vfp_sp_monadic ();
16728 do_vfp_dp_rd_rm ();
16732 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16733 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16734 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16735 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16736 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16737 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16738 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16742 inst
.instruction
|= (rs
== NS_DD
) << 8;
16743 do_vfp_cond_or_thumb ();
16747 /* Neon encodings (or something broken...). */
16749 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16751 if (et
.type
== NT_invtype
)
16754 set_it_insn_type (OUTSIDE_IT_INSN
);
16755 NEON_ENCODE (FLOAT
, inst
);
16757 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16764 inst
.instruction
|= neon_quad (rs
) << 6;
16767 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16768 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16769 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16770 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16771 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16772 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16773 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16778 inst
.instruction
|= 0xfc000000;
16780 inst
.instruction
|= 0xf0000000;
16787 do_vrint_1 (neon_cvt_mode_x
);
16793 do_vrint_1 (neon_cvt_mode_z
);
16799 do_vrint_1 (neon_cvt_mode_r
);
16805 do_vrint_1 (neon_cvt_mode_a
);
16811 do_vrint_1 (neon_cvt_mode_n
);
16817 do_vrint_1 (neon_cvt_mode_p
);
16823 do_vrint_1 (neon_cvt_mode_m
);
16826 /* Crypto v1 instructions. */
16828 do_crypto_2op_1 (unsigned elttype
, int op
)
16830 set_it_insn_type (OUTSIDE_IT_INSN
);
16832 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16838 NEON_ENCODE (INTEGER
, inst
);
16839 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16840 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16841 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16842 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16844 inst
.instruction
|= op
<< 6;
16847 inst
.instruction
|= 0xfc000000;
16849 inst
.instruction
|= 0xf0000000;
16853 do_crypto_3op_1 (int u
, int op
)
16855 set_it_insn_type (OUTSIDE_IT_INSN
);
16857 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16858 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16863 NEON_ENCODE (INTEGER
, inst
);
16864 neon_three_same (1, u
, 8 << op
);
16870 do_crypto_2op_1 (N_8
, 0);
16876 do_crypto_2op_1 (N_8
, 1);
16882 do_crypto_2op_1 (N_8
, 2);
16888 do_crypto_2op_1 (N_8
, 3);
16894 do_crypto_3op_1 (0, 0);
16900 do_crypto_3op_1 (0, 1);
16906 do_crypto_3op_1 (0, 2);
16912 do_crypto_3op_1 (0, 3);
16918 do_crypto_3op_1 (1, 0);
16924 do_crypto_3op_1 (1, 1);
16928 do_sha256su1 (void)
16930 do_crypto_3op_1 (1, 2);
16936 do_crypto_2op_1 (N_32
, -1);
16942 do_crypto_2op_1 (N_32
, 0);
16946 do_sha256su0 (void)
16948 do_crypto_2op_1 (N_32
, 1);
16952 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16954 unsigned int Rd
= inst
.operands
[0].reg
;
16955 unsigned int Rn
= inst
.operands
[1].reg
;
16956 unsigned int Rm
= inst
.operands
[2].reg
;
16958 set_it_insn_type (OUTSIDE_IT_INSN
);
16959 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16960 inst
.instruction
|= LOW4 (Rn
) << 16;
16961 inst
.instruction
|= LOW4 (Rm
);
16962 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16963 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16965 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16966 as_warn (UNPRED_REG ("r15"));
16967 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16968 as_warn (UNPRED_REG ("r13"));
17008 /* Overall per-instruction processing. */
17010 /* We need to be able to fix up arbitrary expressions in some statements.
17011 This is so that we can handle symbols that are an arbitrary distance from
17012 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17013 which returns part of an address in a form which will be valid for
17014 a data instruction. We do this by pushing the expression into a symbol
17015 in the expr_section, and creating a fix for that. */
17018 fix_new_arm (fragS
* frag
,
17032 /* Create an absolute valued symbol, so we have something to
17033 refer to in the object file. Unfortunately for us, gas's
17034 generic expression parsing will already have folded out
17035 any use of .set foo/.type foo %function that may have
17036 been used to set type information of the target location,
17037 that's being specified symbolically. We have to presume
17038 the user knows what they are doing. */
17042 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17044 symbol
= symbol_find_or_make (name
);
17045 S_SET_SEGMENT (symbol
, absolute_section
);
17046 symbol_set_frag (symbol
, &zero_address_frag
);
17047 S_SET_VALUE (symbol
, exp
->X_add_number
);
17048 exp
->X_op
= O_symbol
;
17049 exp
->X_add_symbol
= symbol
;
17050 exp
->X_add_number
= 0;
17056 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17057 (enum bfd_reloc_code_real
) reloc
);
17061 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17062 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17066 /* Mark whether the fix is to a THUMB instruction, or an ARM
17068 new_fix
->tc_fix_data
= thumb_mode
;
17071 /* Create a frg for an instruction requiring relaxation. */
17073 output_relax_insn (void)
17079 /* The size of the instruction is unknown, so tie the debug info to the
17080 start of the instruction. */
17081 dwarf2_emit_insn (0);
17083 switch (inst
.reloc
.exp
.X_op
)
17086 sym
= inst
.reloc
.exp
.X_add_symbol
;
17087 offset
= inst
.reloc
.exp
.X_add_number
;
17091 offset
= inst
.reloc
.exp
.X_add_number
;
17094 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17098 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17099 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17100 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17103 /* Write a 32-bit thumb instruction to buf. */
17105 put_thumb32_insn (char * buf
, unsigned long insn
)
17107 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17108 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17112 output_inst (const char * str
)
17118 as_bad ("%s -- `%s'", inst
.error
, str
);
17123 output_relax_insn ();
17126 if (inst
.size
== 0)
17129 to
= frag_more (inst
.size
);
17130 /* PR 9814: Record the thumb mode into the current frag so that we know
17131 what type of NOP padding to use, if necessary. We override any previous
17132 setting so that if the mode has changed then the NOPS that we use will
17133 match the encoding of the last instruction in the frag. */
17134 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17136 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17138 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17139 put_thumb32_insn (to
, inst
.instruction
);
17141 else if (inst
.size
> INSN_SIZE
)
17143 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17144 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17145 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17148 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17150 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17151 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17152 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17155 dwarf2_emit_insn (inst
.size
);
17159 output_it_inst (int cond
, int mask
, char * to
)
17161 unsigned long instruction
= 0xbf00;
17164 instruction
|= mask
;
17165 instruction
|= cond
<< 4;
17169 to
= frag_more (2);
17171 dwarf2_emit_insn (2);
17175 md_number_to_chars (to
, instruction
, 2);
17180 /* Tag values used in struct asm_opcode's tag field. */
17183 OT_unconditional
, /* Instruction cannot be conditionalized.
17184 The ARM condition field is still 0xE. */
17185 OT_unconditionalF
, /* Instruction cannot be conditionalized
17186 and carries 0xF in its ARM condition field. */
17187 OT_csuffix
, /* Instruction takes a conditional suffix. */
17188 OT_csuffixF
, /* Some forms of the instruction take a conditional
17189 suffix, others place 0xF where the condition field
17191 OT_cinfix3
, /* Instruction takes a conditional infix,
17192 beginning at character index 3. (In
17193 unified mode, it becomes a suffix.) */
17194 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17195 tsts, cmps, cmns, and teqs. */
17196 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17197 character index 3, even in unified mode. Used for
17198 legacy instructions where suffix and infix forms
17199 may be ambiguous. */
17200 OT_csuf_or_in3
, /* Instruction takes either a conditional
17201 suffix or an infix at character index 3. */
17202 OT_odd_infix_unc
, /* This is the unconditional variant of an
17203 instruction that takes a conditional infix
17204 at an unusual position. In unified mode,
17205 this variant will accept a suffix. */
17206 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17207 are the conditional variants of instructions that
17208 take conditional infixes in unusual positions.
17209 The infix appears at character index
17210 (tag - OT_odd_infix_0). These are not accepted
17211 in unified mode. */
17214 /* Subroutine of md_assemble, responsible for looking up the primary
17215 opcode from the mnemonic the user wrote. STR points to the
17216 beginning of the mnemonic.
17218 This is not simply a hash table lookup, because of conditional
17219 variants. Most instructions have conditional variants, which are
17220 expressed with a _conditional affix_ to the mnemonic. If we were
17221 to encode each conditional variant as a literal string in the opcode
17222 table, it would have approximately 20,000 entries.
17224 Most mnemonics take this affix as a suffix, and in unified syntax,
17225 'most' is upgraded to 'all'. However, in the divided syntax, some
17226 instructions take the affix as an infix, notably the s-variants of
17227 the arithmetic instructions. Of those instructions, all but six
17228 have the infix appear after the third character of the mnemonic.
17230 Accordingly, the algorithm for looking up primary opcodes given
17233 1. Look up the identifier in the opcode table.
17234 If we find a match, go to step U.
17236 2. Look up the last two characters of the identifier in the
17237 conditions table. If we find a match, look up the first N-2
17238 characters of the identifier in the opcode table. If we
17239 find a match, go to step CE.
17241 3. Look up the fourth and fifth characters of the identifier in
17242 the conditions table. If we find a match, extract those
17243 characters from the identifier, and look up the remaining
17244 characters in the opcode table. If we find a match, go
17249 U. Examine the tag field of the opcode structure, in case this is
17250 one of the six instructions with its conditional infix in an
17251 unusual place. If it is, the tag tells us where to find the
17252 infix; look it up in the conditions table and set inst.cond
17253 accordingly. Otherwise, this is an unconditional instruction.
17254 Again set inst.cond accordingly. Return the opcode structure.
17256 CE. Examine the tag field to make sure this is an instruction that
17257 should receive a conditional suffix. If it is not, fail.
17258 Otherwise, set inst.cond from the suffix we already looked up,
17259 and return the opcode structure.
17261 CM. Examine the tag field to make sure this is an instruction that
17262 should receive a conditional infix after the third character.
17263 If it is not, fail. Otherwise, undo the edits to the current
17264 line of input and proceed as for case CE. */
17266 static const struct asm_opcode
*
17267 opcode_lookup (char **str
)
17271 const struct asm_opcode
*opcode
;
17272 const struct asm_cond
*cond
;
17275 /* Scan up to the end of the mnemonic, which must end in white space,
17276 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17277 for (base
= end
= *str
; *end
!= '\0'; end
++)
17278 if (*end
== ' ' || *end
== '.')
17284 /* Handle a possible width suffix and/or Neon type suffix. */
17289 /* The .w and .n suffixes are only valid if the unified syntax is in
17291 if (unified_syntax
&& end
[1] == 'w')
17293 else if (unified_syntax
&& end
[1] == 'n')
17298 inst
.vectype
.elems
= 0;
17300 *str
= end
+ offset
;
17302 if (end
[offset
] == '.')
17304 /* See if we have a Neon type suffix (possible in either unified or
17305 non-unified ARM syntax mode). */
17306 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17309 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17315 /* Look for unaffixed or special-case affixed mnemonic. */
17316 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17321 if (opcode
->tag
< OT_odd_infix_0
)
17323 inst
.cond
= COND_ALWAYS
;
17327 if (warn_on_deprecated
&& unified_syntax
)
17328 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17329 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17330 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17333 inst
.cond
= cond
->value
;
17337 /* Cannot have a conditional suffix on a mnemonic of less than two
17339 if (end
- base
< 3)
17342 /* Look for suffixed mnemonic. */
17344 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17345 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17347 if (opcode
&& cond
)
17350 switch (opcode
->tag
)
17352 case OT_cinfix3_legacy
:
17353 /* Ignore conditional suffixes matched on infix only mnemonics. */
17357 case OT_cinfix3_deprecated
:
17358 case OT_odd_infix_unc
:
17359 if (!unified_syntax
)
17361 /* else fall through */
17365 case OT_csuf_or_in3
:
17366 inst
.cond
= cond
->value
;
17369 case OT_unconditional
:
17370 case OT_unconditionalF
:
17372 inst
.cond
= cond
->value
;
17375 /* Delayed diagnostic. */
17376 inst
.error
= BAD_COND
;
17377 inst
.cond
= COND_ALWAYS
;
17386 /* Cannot have a usual-position infix on a mnemonic of less than
17387 six characters (five would be a suffix). */
17388 if (end
- base
< 6)
17391 /* Look for infixed mnemonic in the usual position. */
17393 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17397 memcpy (save
, affix
, 2);
17398 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17399 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17401 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17402 memcpy (affix
, save
, 2);
17405 && (opcode
->tag
== OT_cinfix3
17406 || opcode
->tag
== OT_cinfix3_deprecated
17407 || opcode
->tag
== OT_csuf_or_in3
17408 || opcode
->tag
== OT_cinfix3_legacy
))
17411 if (warn_on_deprecated
&& unified_syntax
17412 && (opcode
->tag
== OT_cinfix3
17413 || opcode
->tag
== OT_cinfix3_deprecated
))
17414 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17416 inst
.cond
= cond
->value
;
17423 /* This function generates an initial IT instruction, leaving its block
17424 virtually open for the new instructions. Eventually,
17425 the mask will be updated by now_it_add_mask () each time
17426 a new instruction needs to be included in the IT block.
17427 Finally, the block is closed with close_automatic_it_block ().
17428 The block closure can be requested either from md_assemble (),
17429 a tencode (), or due to a label hook. */
17432 new_automatic_it_block (int cond
)
17434 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17435 now_it
.mask
= 0x18;
17437 now_it
.block_length
= 1;
17438 mapping_state (MAP_THUMB
);
17439 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17440 now_it
.warn_deprecated
= FALSE
;
17441 now_it
.insn_cond
= TRUE
;
17444 /* Close an automatic IT block.
17445 See comments in new_automatic_it_block (). */
17448 close_automatic_it_block (void)
17450 now_it
.mask
= 0x10;
17451 now_it
.block_length
= 0;
17454 /* Update the mask of the current automatically-generated IT
17455 instruction. See comments in new_automatic_it_block (). */
17458 now_it_add_mask (int cond
)
17460 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17461 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17462 | ((bitvalue) << (nbit)))
17463 const int resulting_bit
= (cond
& 1);
17465 now_it
.mask
&= 0xf;
17466 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17468 (5 - now_it
.block_length
));
17469 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17471 ((5 - now_it
.block_length
) - 1) );
17472 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17475 #undef SET_BIT_VALUE
17478 /* The IT blocks handling machinery is accessed through the these functions:
17479 it_fsm_pre_encode () from md_assemble ()
17480 set_it_insn_type () optional, from the tencode functions
17481 set_it_insn_type_last () ditto
17482 in_it_block () ditto
17483 it_fsm_post_encode () from md_assemble ()
17484 force_automatic_it_block_close () from label habdling functions
17487 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17488 initializing the IT insn type with a generic initial value depending
17489 on the inst.condition.
17490 2) During the tencode function, two things may happen:
17491 a) The tencode function overrides the IT insn type by
17492 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17493 b) The tencode function queries the IT block state by
17494 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17496 Both set_it_insn_type and in_it_block run the internal FSM state
17497 handling function (handle_it_state), because: a) setting the IT insn
17498 type may incur in an invalid state (exiting the function),
17499 and b) querying the state requires the FSM to be updated.
17500 Specifically we want to avoid creating an IT block for conditional
17501 branches, so it_fsm_pre_encode is actually a guess and we can't
17502 determine whether an IT block is required until the tencode () routine
17503 has decided what type of instruction this actually it.
17504 Because of this, if set_it_insn_type and in_it_block have to be used,
17505 set_it_insn_type has to be called first.
17507 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17508 determines the insn IT type depending on the inst.cond code.
17509 When a tencode () routine encodes an instruction that can be
17510 either outside an IT block, or, in the case of being inside, has to be
17511 the last one, set_it_insn_type_last () will determine the proper
17512 IT instruction type based on the inst.cond code. Otherwise,
17513 set_it_insn_type can be called for overriding that logic or
17514 for covering other cases.
17516 Calling handle_it_state () may not transition the IT block state to
17517 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17518 still queried. Instead, if the FSM determines that the state should
17519 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17520 after the tencode () function: that's what it_fsm_post_encode () does.
17522 Since in_it_block () calls the state handling function to get an
17523 updated state, an error may occur (due to invalid insns combination).
17524 In that case, inst.error is set.
17525 Therefore, inst.error has to be checked after the execution of
17526 the tencode () routine.
17528 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17529 any pending state change (if any) that didn't take place in
17530 handle_it_state () as explained above. */
17533 it_fsm_pre_encode (void)
17535 if (inst
.cond
!= COND_ALWAYS
)
17536 inst
.it_insn_type
= INSIDE_IT_INSN
;
17538 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17540 now_it
.state_handled
= 0;
17543 /* IT state FSM handling function. */
17546 handle_it_state (void)
17548 now_it
.state_handled
= 1;
17549 now_it
.insn_cond
= FALSE
;
17551 switch (now_it
.state
)
17553 case OUTSIDE_IT_BLOCK
:
17554 switch (inst
.it_insn_type
)
17556 case OUTSIDE_IT_INSN
:
17559 case INSIDE_IT_INSN
:
17560 case INSIDE_IT_LAST_INSN
:
17561 if (thumb_mode
== 0)
17564 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17565 as_tsktsk (_("Warning: conditional outside an IT block"\
17570 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17571 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17573 /* Automatically generate the IT instruction. */
17574 new_automatic_it_block (inst
.cond
);
17575 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17576 close_automatic_it_block ();
17580 inst
.error
= BAD_OUT_IT
;
17586 case IF_INSIDE_IT_LAST_INSN
:
17587 case NEUTRAL_IT_INSN
:
17591 now_it
.state
= MANUAL_IT_BLOCK
;
17592 now_it
.block_length
= 0;
17597 case AUTOMATIC_IT_BLOCK
:
17598 /* Three things may happen now:
17599 a) We should increment current it block size;
17600 b) We should close current it block (closing insn or 4 insns);
17601 c) We should close current it block and start a new one (due
17602 to incompatible conditions or
17603 4 insns-length block reached). */
17605 switch (inst
.it_insn_type
)
17607 case OUTSIDE_IT_INSN
:
17608 /* The closure of the block shall happen immediatelly,
17609 so any in_it_block () call reports the block as closed. */
17610 force_automatic_it_block_close ();
17613 case INSIDE_IT_INSN
:
17614 case INSIDE_IT_LAST_INSN
:
17615 case IF_INSIDE_IT_LAST_INSN
:
17616 now_it
.block_length
++;
17618 if (now_it
.block_length
> 4
17619 || !now_it_compatible (inst
.cond
))
17621 force_automatic_it_block_close ();
17622 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17623 new_automatic_it_block (inst
.cond
);
17627 now_it
.insn_cond
= TRUE
;
17628 now_it_add_mask (inst
.cond
);
17631 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17632 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17633 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17634 close_automatic_it_block ();
17637 case NEUTRAL_IT_INSN
:
17638 now_it
.block_length
++;
17639 now_it
.insn_cond
= TRUE
;
17641 if (now_it
.block_length
> 4)
17642 force_automatic_it_block_close ();
17644 now_it_add_mask (now_it
.cc
& 1);
17648 close_automatic_it_block ();
17649 now_it
.state
= MANUAL_IT_BLOCK
;
17654 case MANUAL_IT_BLOCK
:
17656 /* Check conditional suffixes. */
17657 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17660 now_it
.mask
&= 0x1f;
17661 is_last
= (now_it
.mask
== 0x10);
17662 now_it
.insn_cond
= TRUE
;
17664 switch (inst
.it_insn_type
)
17666 case OUTSIDE_IT_INSN
:
17667 inst
.error
= BAD_NOT_IT
;
17670 case INSIDE_IT_INSN
:
17671 if (cond
!= inst
.cond
)
17673 inst
.error
= BAD_IT_COND
;
17678 case INSIDE_IT_LAST_INSN
:
17679 case IF_INSIDE_IT_LAST_INSN
:
17680 if (cond
!= inst
.cond
)
17682 inst
.error
= BAD_IT_COND
;
17687 inst
.error
= BAD_BRANCH
;
17692 case NEUTRAL_IT_INSN
:
17693 /* The BKPT instruction is unconditional even in an IT block. */
17697 inst
.error
= BAD_IT_IT
;
17707 struct depr_insn_mask
17709 unsigned long pattern
;
17710 unsigned long mask
;
17711 const char* description
;
17714 /* List of 16-bit instruction patterns deprecated in an IT block in
17716 static const struct depr_insn_mask depr_it_insns
[] = {
17717 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17718 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17719 { 0xa000, 0xb800, N_("ADR") },
17720 { 0x4800, 0xf800, N_("Literal loads") },
17721 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17722 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17723 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17724 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17725 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17730 it_fsm_post_encode (void)
17734 if (!now_it
.state_handled
)
17735 handle_it_state ();
17737 if (now_it
.insn_cond
17738 && !now_it
.warn_deprecated
17739 && warn_on_deprecated
17740 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17742 if (inst
.instruction
>= 0x10000)
17744 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17745 "deprecated in ARMv8"));
17746 now_it
.warn_deprecated
= TRUE
;
17750 const struct depr_insn_mask
*p
= depr_it_insns
;
17752 while (p
->mask
!= 0)
17754 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17756 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17757 "of the following class are deprecated in ARMv8: "
17758 "%s"), p
->description
);
17759 now_it
.warn_deprecated
= TRUE
;
17767 if (now_it
.block_length
> 1)
17769 as_tsktsk (_("IT blocks containing more than one conditional "
17770 "instruction are deprecated in ARMv8"));
17771 now_it
.warn_deprecated
= TRUE
;
17775 is_last
= (now_it
.mask
== 0x10);
17778 now_it
.state
= OUTSIDE_IT_BLOCK
;
17784 force_automatic_it_block_close (void)
17786 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17788 close_automatic_it_block ();
17789 now_it
.state
= OUTSIDE_IT_BLOCK
;
17797 if (!now_it
.state_handled
)
17798 handle_it_state ();
17800 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17804 md_assemble (char *str
)
17807 const struct asm_opcode
* opcode
;
17809 /* Align the previous label if needed. */
17810 if (last_label_seen
!= NULL
)
17812 symbol_set_frag (last_label_seen
, frag_now
);
17813 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17814 S_SET_SEGMENT (last_label_seen
, now_seg
);
17817 memset (&inst
, '\0', sizeof (inst
));
17818 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17820 opcode
= opcode_lookup (&p
);
17823 /* It wasn't an instruction, but it might be a register alias of
17824 the form alias .req reg, or a Neon .dn/.qn directive. */
17825 if (! create_register_alias (str
, p
)
17826 && ! create_neon_reg_alias (str
, p
))
17827 as_bad (_("bad instruction `%s'"), str
);
17832 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17833 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17835 /* The value which unconditional instructions should have in place of the
17836 condition field. */
17837 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17841 arm_feature_set variant
;
17843 variant
= cpu_variant
;
17844 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17845 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17846 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17847 /* Check that this instruction is supported for this CPU. */
17848 if (!opcode
->tvariant
17849 || (thumb_mode
== 1
17850 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17852 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17855 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17856 && opcode
->tencode
!= do_t_branch
)
17858 as_bad (_("Thumb does not support conditional execution"));
17862 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17864 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17865 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17866 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17868 /* Two things are addressed here.
17869 1) Implicit require narrow instructions on Thumb-1.
17870 This avoids relaxation accidentally introducing Thumb-2
17872 2) Reject wide instructions in non Thumb-2 cores. */
17873 if (inst
.size_req
== 0)
17875 else if (inst
.size_req
== 4)
17877 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17883 inst
.instruction
= opcode
->tvalue
;
17885 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17887 /* Prepare the it_insn_type for those encodings that don't set
17889 it_fsm_pre_encode ();
17891 opcode
->tencode ();
17893 it_fsm_post_encode ();
17896 if (!(inst
.error
|| inst
.relax
))
17898 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17899 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17900 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17902 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17907 /* Something has gone badly wrong if we try to relax a fixed size
17909 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17911 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17912 *opcode
->tvariant
);
17913 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17914 set those bits when Thumb-2 32-bit instructions are seen. ie.
17915 anything other than bl/blx and v6-M instructions.
17916 The impact of relaxable instructions will be considered later after we
17917 finish all relaxation. */
17918 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17919 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17920 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17921 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17924 check_neon_suffixes
;
17928 mapping_state (MAP_THUMB
);
17931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17935 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17936 is_bx
= (opcode
->aencode
== do_bx
);
17938 /* Check that this instruction is supported for this CPU. */
17939 if (!(is_bx
&& fix_v4bx
)
17940 && !(opcode
->avariant
&&
17941 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17943 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17948 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17952 inst
.instruction
= opcode
->avalue
;
17953 if (opcode
->tag
== OT_unconditionalF
)
17954 inst
.instruction
|= 0xF << 28;
17956 inst
.instruction
|= inst
.cond
<< 28;
17957 inst
.size
= INSN_SIZE
;
17958 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17960 it_fsm_pre_encode ();
17961 opcode
->aencode ();
17962 it_fsm_post_encode ();
17964 /* Arm mode bx is marked as both v4T and v5 because it's still required
17965 on a hypothetical non-thumb v5 core. */
17967 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17969 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17970 *opcode
->avariant
);
17972 check_neon_suffixes
;
17976 mapping_state (MAP_ARM
);
17981 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17989 check_it_blocks_finished (void)
17994 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17995 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17996 == MANUAL_IT_BLOCK
)
17998 as_warn (_("section '%s' finished with an open IT block."),
18002 if (now_it
.state
== MANUAL_IT_BLOCK
)
18003 as_warn (_("file finished with an open IT block."));
18007 /* Various frobbings of labels and their addresses. */
18010 arm_start_line_hook (void)
18012 last_label_seen
= NULL
;
18016 arm_frob_label (symbolS
* sym
)
18018 last_label_seen
= sym
;
18020 ARM_SET_THUMB (sym
, thumb_mode
);
18022 #if defined OBJ_COFF || defined OBJ_ELF
18023 ARM_SET_INTERWORK (sym
, support_interwork
);
18026 force_automatic_it_block_close ();
18028 /* Note - do not allow local symbols (.Lxxx) to be labelled
18029 as Thumb functions. This is because these labels, whilst
18030 they exist inside Thumb code, are not the entry points for
18031 possible ARM->Thumb calls. Also, these labels can be used
18032 as part of a computed goto or switch statement. eg gcc
18033 can generate code that looks like this:
18035 ldr r2, [pc, .Laaa]
18045 The first instruction loads the address of the jump table.
18046 The second instruction converts a table index into a byte offset.
18047 The third instruction gets the jump address out of the table.
18048 The fourth instruction performs the jump.
18050 If the address stored at .Laaa is that of a symbol which has the
18051 Thumb_Func bit set, then the linker will arrange for this address
18052 to have the bottom bit set, which in turn would mean that the
18053 address computation performed by the third instruction would end
18054 up with the bottom bit set. Since the ARM is capable of unaligned
18055 word loads, the instruction would then load the incorrect address
18056 out of the jump table, and chaos would ensue. */
18057 if (label_is_thumb_function_name
18058 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18059 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18061 /* When the address of a Thumb function is taken the bottom
18062 bit of that address should be set. This will allow
18063 interworking between Arm and Thumb functions to work
18066 THUMB_SET_FUNC (sym
, 1);
18068 label_is_thumb_function_name
= FALSE
;
18071 dwarf2_emit_label (sym
);
18075 arm_data_in_code (void)
18077 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18079 *input_line_pointer
= '/';
18080 input_line_pointer
+= 5;
18081 *input_line_pointer
= 0;
18089 arm_canonicalize_symbol_name (char * name
)
18093 if (thumb_mode
&& (len
= strlen (name
)) > 5
18094 && streq (name
+ len
- 5, "/data"))
18095 *(name
+ len
- 5) = 0;
18100 /* Table of all register names defined by default. The user can
18101 define additional names with .req. Note that all register names
18102 should appear in both upper and lowercase variants. Some registers
18103 also have mixed-case names. */
18105 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18106 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18107 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18108 #define REGSET(p,t) \
18109 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18110 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18111 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18112 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18113 #define REGSETH(p,t) \
18114 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18115 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18116 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18117 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18118 #define REGSET2(p,t) \
18119 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18120 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18121 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18122 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18123 #define SPLRBANK(base,bank,t) \
18124 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18125 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18126 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18127 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18128 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18129 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18131 static const struct reg_entry reg_names
[] =
18133 /* ARM integer registers. */
18134 REGSET(r
, RN
), REGSET(R
, RN
),
18136 /* ATPCS synonyms. */
18137 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18138 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18139 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18141 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18142 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18143 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18145 /* Well-known aliases. */
18146 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18147 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18149 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18150 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18152 /* Coprocessor numbers. */
18153 REGSET(p
, CP
), REGSET(P
, CP
),
18155 /* Coprocessor register numbers. The "cr" variants are for backward
18157 REGSET(c
, CN
), REGSET(C
, CN
),
18158 REGSET(cr
, CN
), REGSET(CR
, CN
),
18160 /* ARM banked registers. */
18161 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18162 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18163 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18164 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18165 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18166 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18167 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18169 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18170 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18171 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18172 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18173 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18174 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18175 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18176 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18178 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18179 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18180 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18181 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18182 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18183 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18184 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18185 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18186 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18188 /* FPA registers. */
18189 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18190 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18192 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18193 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18195 /* VFP SP registers. */
18196 REGSET(s
,VFS
), REGSET(S
,VFS
),
18197 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18199 /* VFP DP Registers. */
18200 REGSET(d
,VFD
), REGSET(D
,VFD
),
18201 /* Extra Neon DP registers. */
18202 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18204 /* Neon QP registers. */
18205 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18207 /* VFP control registers. */
18208 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18209 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18210 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18211 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18212 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18213 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18215 /* Maverick DSP coprocessor registers. */
18216 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18217 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18219 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18220 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18221 REGDEF(dspsc
,0,DSPSC
),
18223 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18224 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18225 REGDEF(DSPSC
,0,DSPSC
),
18227 /* iWMMXt data registers - p0, c0-15. */
18228 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18230 /* iWMMXt control registers - p1, c0-3. */
18231 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18232 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18233 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18234 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18236 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18237 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18238 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18239 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18240 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18242 /* XScale accumulator registers. */
18243 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18249 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18250 within psr_required_here. */
18251 static const struct asm_psr psrs
[] =
18253 /* Backward compatibility notation. Note that "all" is no longer
18254 truly all possible PSR bits. */
18255 {"all", PSR_c
| PSR_f
},
18259 /* Individual flags. */
18265 /* Combinations of flags. */
18266 {"fs", PSR_f
| PSR_s
},
18267 {"fx", PSR_f
| PSR_x
},
18268 {"fc", PSR_f
| PSR_c
},
18269 {"sf", PSR_s
| PSR_f
},
18270 {"sx", PSR_s
| PSR_x
},
18271 {"sc", PSR_s
| PSR_c
},
18272 {"xf", PSR_x
| PSR_f
},
18273 {"xs", PSR_x
| PSR_s
},
18274 {"xc", PSR_x
| PSR_c
},
18275 {"cf", PSR_c
| PSR_f
},
18276 {"cs", PSR_c
| PSR_s
},
18277 {"cx", PSR_c
| PSR_x
},
18278 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18279 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18280 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18281 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18282 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18283 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18284 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18285 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18286 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18287 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18288 {"scf", PSR_s
| PSR_c
| PSR_f
},
18289 {"scx", PSR_s
| PSR_c
| PSR_x
},
18290 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18291 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18292 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18293 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18294 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18295 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18296 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18297 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18298 {"csf", PSR_c
| PSR_s
| PSR_f
},
18299 {"csx", PSR_c
| PSR_s
| PSR_x
},
18300 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18301 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18302 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18303 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18304 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18305 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18306 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18307 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18308 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18309 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18310 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18311 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18312 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18313 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18314 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18315 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18316 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18317 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18318 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18319 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18320 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18321 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18322 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18323 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18324 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18325 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18328 /* Table of V7M psr names. */
18329 static const struct asm_psr v7m_psrs
[] =
18331 {"apsr", 0 }, {"APSR", 0 },
18332 {"iapsr", 1 }, {"IAPSR", 1 },
18333 {"eapsr", 2 }, {"EAPSR", 2 },
18334 {"psr", 3 }, {"PSR", 3 },
18335 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18336 {"ipsr", 5 }, {"IPSR", 5 },
18337 {"epsr", 6 }, {"EPSR", 6 },
18338 {"iepsr", 7 }, {"IEPSR", 7 },
18339 {"msp", 8 }, {"MSP", 8 },
18340 {"psp", 9 }, {"PSP", 9 },
18341 {"primask", 16}, {"PRIMASK", 16},
18342 {"basepri", 17}, {"BASEPRI", 17},
18343 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18344 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18345 {"faultmask", 19}, {"FAULTMASK", 19},
18346 {"control", 20}, {"CONTROL", 20}
18349 /* Table of all shift-in-operand names. */
18350 static const struct asm_shift_name shift_names
[] =
18352 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18353 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18354 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18355 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18356 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18357 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18360 /* Table of all explicit relocation names. */
18362 static struct reloc_entry reloc_names
[] =
18364 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18365 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18366 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18367 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18368 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18369 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18370 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18371 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18372 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18373 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18374 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18375 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18376 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18377 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18378 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18379 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18380 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18381 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18385 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18386 static const struct asm_cond conds
[] =
18390 {"cs", 0x2}, {"hs", 0x2},
18391 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18405 #define UL_BARRIER(L,U,CODE,FEAT) \
18406 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18407 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18409 static struct asm_barrier_opt barrier_opt_names
[] =
18411 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18412 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18413 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18414 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18415 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18416 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18417 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18418 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18419 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18420 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18421 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18422 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18423 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18424 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18425 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18426 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18431 /* Table of ARM-format instructions. */
18433 /* Macros for gluing together operand strings. N.B. In all cases
18434 other than OPS0, the trailing OP_stop comes from default
18435 zero-initialization of the unspecified elements of the array. */
18436 #define OPS0() { OP_stop, }
18437 #define OPS1(a) { OP_##a, }
18438 #define OPS2(a,b) { OP_##a,OP_##b, }
18439 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18440 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18441 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18442 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18444 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18445 This is useful when mixing operands for ARM and THUMB, i.e. using the
18446 MIX_ARM_THUMB_OPERANDS macro.
18447 In order to use these macros, prefix the number of operands with _
18449 #define OPS_1(a) { a, }
18450 #define OPS_2(a,b) { a,b, }
18451 #define OPS_3(a,b,c) { a,b,c, }
18452 #define OPS_4(a,b,c,d) { a,b,c,d, }
18453 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18454 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18456 /* These macros abstract out the exact format of the mnemonic table and
18457 save some repeated characters. */
18459 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18460 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18461 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18462 THUMB_VARIANT, do_##ae, do_##te }
18464 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18465 a T_MNEM_xyz enumerator. */
18466 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18467 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18468 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18469 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18471 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18472 infix after the third character. */
18473 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18474 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18475 THUMB_VARIANT, do_##ae, do_##te }
18476 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18477 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18478 THUMB_VARIANT, do_##ae, do_##te }
18479 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18480 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18481 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18482 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18483 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18484 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18485 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18486 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18488 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18489 field is still 0xE. Many of the Thumb variants can be executed
18490 conditionally, so this is checked separately. */
18491 #define TUE(mnem, op, top, nops, ops, ae, te) \
18492 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18493 THUMB_VARIANT, do_##ae, do_##te }
18495 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18496 Used by mnemonics that have very minimal differences in the encoding for
18497 ARM and Thumb variants and can be handled in a common function. */
18498 #define TUEc(mnem, op, top, nops, ops, en) \
18499 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18500 THUMB_VARIANT, do_##en, do_##en }
18502 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18503 condition code field. */
18504 #define TUF(mnem, op, top, nops, ops, ae, te) \
18505 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18506 THUMB_VARIANT, do_##ae, do_##te }
18508 /* ARM-only variants of all the above. */
18509 #define CE(mnem, op, nops, ops, ae) \
18510 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18512 #define C3(mnem, op, nops, ops, ae) \
18513 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18515 /* Legacy mnemonics that always have conditional infix after the third
18517 #define CL(mnem, op, nops, ops, ae) \
18518 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18519 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18521 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18522 #define cCE(mnem, op, nops, ops, ae) \
18523 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18525 /* Legacy coprocessor instructions where conditional infix and conditional
18526 suffix are ambiguous. For consistency this includes all FPA instructions,
18527 not just the potentially ambiguous ones. */
18528 #define cCL(mnem, op, nops, ops, ae) \
18529 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18530 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18532 /* Coprocessor, takes either a suffix or a position-3 infix
18533 (for an FPA corner case). */
18534 #define C3E(mnem, op, nops, ops, ae) \
18535 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18536 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18538 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18539 { m1 #m2 m3, OPS##nops ops, \
18540 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18541 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18543 #define CM(m1, m2, op, nops, ops, ae) \
18544 xCM_ (m1, , m2, op, nops, ops, ae), \
18545 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18546 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18547 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18548 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18549 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18550 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18551 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18552 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18553 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18554 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18555 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18556 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18557 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18558 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18559 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18560 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18561 xCM_ (m1, le, m2, op, nops, ops, ae), \
18562 xCM_ (m1, al, m2, op, nops, ops, ae)
18564 #define UE(mnem, op, nops, ops, ae) \
18565 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18567 #define UF(mnem, op, nops, ops, ae) \
18568 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18570 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18571 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18572 use the same encoding function for each. */
18573 #define NUF(mnem, op, nops, ops, enc) \
18574 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18575 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18577 /* Neon data processing, version which indirects through neon_enc_tab for
18578 the various overloaded versions of opcodes. */
18579 #define nUF(mnem, op, nops, ops, enc) \
18580 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18581 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18583 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18585 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18586 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18587 THUMB_VARIANT, do_##enc, do_##enc }
18589 #define NCE(mnem, op, nops, ops, enc) \
18590 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18592 #define NCEF(mnem, op, nops, ops, enc) \
18593 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18595 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18596 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18597 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18598 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18600 #define nCE(mnem, op, nops, ops, enc) \
18601 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18603 #define nCEF(mnem, op, nops, ops, enc) \
18604 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18608 static const struct asm_opcode insns
[] =
18610 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18611 #define THUMB_VARIANT & arm_ext_v4t
18612 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18613 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18614 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18615 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18616 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18617 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18618 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18619 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18620 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18621 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18622 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18623 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18624 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18625 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18626 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18627 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18629 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18630 for setting PSR flag bits. They are obsolete in V6 and do not
18631 have Thumb equivalents. */
18632 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18633 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18634 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18635 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18636 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18637 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18638 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18639 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18640 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18642 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18643 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18644 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18645 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18647 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18648 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18649 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18651 OP_ADDRGLDR
),ldst
, t_ldst
),
18652 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18654 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18655 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18656 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18657 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18658 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18659 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18661 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18662 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18663 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18664 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18667 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18668 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18669 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18670 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18672 /* Thumb-compatibility pseudo ops. */
18673 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18674 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18675 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18676 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18677 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18678 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18679 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18680 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18681 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18682 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18683 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18684 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18686 /* These may simplify to neg. */
18687 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18688 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18690 #undef THUMB_VARIANT
18691 #define THUMB_VARIANT & arm_ext_v6
18693 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18695 /* V1 instructions with no Thumb analogue prior to V6T2. */
18696 #undef THUMB_VARIANT
18697 #define THUMB_VARIANT & arm_ext_v6t2
18699 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18700 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18701 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18703 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18704 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18705 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18706 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18708 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18709 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18711 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18712 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18714 /* V1 instructions with no Thumb analogue at all. */
18715 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18716 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18718 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18719 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18720 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18721 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18722 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18723 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18724 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18725 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18728 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18729 #undef THUMB_VARIANT
18730 #define THUMB_VARIANT & arm_ext_v4t
18732 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18733 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18735 #undef THUMB_VARIANT
18736 #define THUMB_VARIANT & arm_ext_v6t2
18738 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18739 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18741 /* Generic coprocessor instructions. */
18742 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18743 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18744 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18745 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18746 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18747 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18748 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18751 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18753 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18754 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18757 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18758 #undef THUMB_VARIANT
18759 #define THUMB_VARIANT & arm_ext_msr
18761 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18762 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18765 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18766 #undef THUMB_VARIANT
18767 #define THUMB_VARIANT & arm_ext_v6t2
18769 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18770 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18771 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18772 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18773 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18774 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18775 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18776 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18779 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18780 #undef THUMB_VARIANT
18781 #define THUMB_VARIANT & arm_ext_v4t
18783 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18784 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18785 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18786 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18787 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18788 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18791 #define ARM_VARIANT & arm_ext_v4t_5
18793 /* ARM Architecture 4T. */
18794 /* Note: bx (and blx) are required on V5, even if the processor does
18795 not support Thumb. */
18796 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18799 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18800 #undef THUMB_VARIANT
18801 #define THUMB_VARIANT & arm_ext_v5t
18803 /* Note: blx has 2 variants; the .value coded here is for
18804 BLX(2). Only this variant has conditional execution. */
18805 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18806 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18808 #undef THUMB_VARIANT
18809 #define THUMB_VARIANT & arm_ext_v6t2
18811 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18812 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18813 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18814 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18815 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18816 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18817 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18818 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18821 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18822 #undef THUMB_VARIANT
18823 #define THUMB_VARIANT & arm_ext_v5exp
18825 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18826 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18827 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18828 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18830 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18831 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18833 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18834 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18835 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18836 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18838 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18839 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18840 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18841 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18843 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18844 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18846 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18847 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18848 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18849 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18852 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18853 #undef THUMB_VARIANT
18854 #define THUMB_VARIANT & arm_ext_v6t2
18856 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18857 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18859 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18860 ADDRGLDRS
), ldrd
, t_ldstd
),
18862 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18863 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18866 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18868 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18871 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18872 #undef THUMB_VARIANT
18873 #define THUMB_VARIANT & arm_ext_v6
18875 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18876 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18877 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18878 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18879 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18880 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18881 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18882 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18883 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18884 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18886 #undef THUMB_VARIANT
18887 #define THUMB_VARIANT & arm_ext_v6t2
18889 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18890 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18892 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18893 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18895 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18896 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18898 /* ARM V6 not included in V7M. */
18899 #undef THUMB_VARIANT
18900 #define THUMB_VARIANT & arm_ext_v6_notm
18901 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18902 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18903 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18904 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18905 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18906 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18907 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18908 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18909 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18910 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18911 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18912 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18913 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18914 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18915 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18916 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18917 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18918 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18920 /* ARM V6 not included in V7M (eg. integer SIMD). */
18921 #undef THUMB_VARIANT
18922 #define THUMB_VARIANT & arm_ext_v6_dsp
18923 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18924 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18925 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18926 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18927 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18928 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18929 /* Old name for QASX. */
18930 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18932 /* Old name for QSAX. */
18933 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18935 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18936 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18937 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 /* Old name for SASX. */
18940 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18941 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18942 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18943 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18944 /* Old name for SHASX. */
18945 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 /* Old name for SHSAX. */
18948 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18951 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 /* Old name for SSAX. */
18953 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18954 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18955 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18956 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18957 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18959 /* Old name for UASX. */
18960 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18961 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18963 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18964 /* Old name for UHASX. */
18965 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18966 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18967 /* Old name for UHSAX. */
18968 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18969 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18970 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18971 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18972 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18973 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18974 /* Old name for UQASX. */
18975 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18976 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18977 /* Old name for UQSAX. */
18978 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18979 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18980 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18981 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18982 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18983 /* Old name for USAX. */
18984 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18985 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18986 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18987 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18988 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18989 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18990 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18991 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18992 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18993 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18994 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18995 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18996 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18997 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18998 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18999 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19000 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19001 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19002 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19003 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19004 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19005 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19006 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19007 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19008 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19009 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19010 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19011 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19012 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19013 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19014 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19015 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19016 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19017 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19020 #define ARM_VARIANT & arm_ext_v6k
19021 #undef THUMB_VARIANT
19022 #define THUMB_VARIANT & arm_ext_v6k
19024 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19025 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19026 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19027 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19029 #undef THUMB_VARIANT
19030 #define THUMB_VARIANT & arm_ext_v6_notm
19031 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19033 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19034 RRnpcb
), strexd
, t_strexd
),
19036 #undef THUMB_VARIANT
19037 #define THUMB_VARIANT & arm_ext_v6t2
19038 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19040 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19042 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19044 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19046 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19049 #define ARM_VARIANT & arm_ext_sec
19050 #undef THUMB_VARIANT
19051 #define THUMB_VARIANT & arm_ext_sec
19053 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19056 #define ARM_VARIANT & arm_ext_virt
19057 #undef THUMB_VARIANT
19058 #define THUMB_VARIANT & arm_ext_virt
19060 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19061 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19064 #define ARM_VARIANT & arm_ext_pan
19065 #undef THUMB_VARIANT
19066 #define THUMB_VARIANT & arm_ext_pan
19068 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19071 #define ARM_VARIANT & arm_ext_v6t2
19072 #undef THUMB_VARIANT
19073 #define THUMB_VARIANT & arm_ext_v6t2
19075 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19076 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19077 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19078 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19080 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19081 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19082 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19083 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19085 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19086 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19087 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19088 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19090 /* Thumb-only instructions. */
19092 #define ARM_VARIANT NULL
19093 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19094 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19096 /* ARM does not really have an IT instruction, so always allow it.
19097 The opcode is copied from Thumb in order to allow warnings in
19098 -mimplicit-it=[never | arm] modes. */
19100 #define ARM_VARIANT & arm_ext_v1
19102 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19103 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19104 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19105 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19106 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19107 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19108 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19109 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19110 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19111 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19112 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19113 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19114 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19115 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19116 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19117 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19118 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19119 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19121 /* Thumb2 only instructions. */
19123 #define ARM_VARIANT NULL
19125 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19126 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19127 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19128 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19129 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19130 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19132 /* Hardware division instructions. */
19134 #define ARM_VARIANT & arm_ext_adiv
19135 #undef THUMB_VARIANT
19136 #define THUMB_VARIANT & arm_ext_div
19138 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19139 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19141 /* ARM V6M/V7 instructions. */
19143 #define ARM_VARIANT & arm_ext_barrier
19144 #undef THUMB_VARIANT
19145 #define THUMB_VARIANT & arm_ext_barrier
19147 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19148 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19149 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19151 /* ARM V7 instructions. */
19153 #define ARM_VARIANT & arm_ext_v7
19154 #undef THUMB_VARIANT
19155 #define THUMB_VARIANT & arm_ext_v7
19157 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19158 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19161 #define ARM_VARIANT & arm_ext_mp
19162 #undef THUMB_VARIANT
19163 #define THUMB_VARIANT & arm_ext_mp
19165 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19167 /* AArchv8 instructions. */
19169 #define ARM_VARIANT & arm_ext_v8
19170 #undef THUMB_VARIANT
19171 #define THUMB_VARIANT & arm_ext_v8
19173 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19174 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19175 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19176 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19178 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19179 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19180 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19182 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19184 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19186 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19188 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19189 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19190 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19191 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19192 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19193 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19195 /* ARMv8 T32 only. */
19197 #define ARM_VARIANT NULL
19198 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19199 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19200 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19202 /* FP for ARMv8. */
19204 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19205 #undef THUMB_VARIANT
19206 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19208 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19209 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19210 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19211 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19212 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19213 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19214 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19215 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19216 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19217 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19218 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19219 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19220 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19221 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19222 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19223 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19224 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19226 /* Crypto v1 extensions. */
19228 #define ARM_VARIANT & fpu_crypto_ext_armv8
19229 #undef THUMB_VARIANT
19230 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19232 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19233 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19234 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19235 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19236 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19237 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19238 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19239 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19240 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19241 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19242 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19243 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19244 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19245 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19248 #define ARM_VARIANT & crc_ext_armv8
19249 #undef THUMB_VARIANT
19250 #define THUMB_VARIANT & crc_ext_armv8
19251 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19252 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19253 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19254 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19255 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19256 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19259 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19260 #undef THUMB_VARIANT
19261 #define THUMB_VARIANT NULL
19263 cCE("wfs", e200110
, 1, (RR
), rd
),
19264 cCE("rfs", e300110
, 1, (RR
), rd
),
19265 cCE("wfc", e400110
, 1, (RR
), rd
),
19266 cCE("rfc", e500110
, 1, (RR
), rd
),
19268 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19269 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19270 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19271 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19273 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19274 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19275 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19276 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19278 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19457 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19461 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19462 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19463 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19464 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19465 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19466 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19467 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19468 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19469 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19470 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19471 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19473 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19474 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19475 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19476 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19477 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19478 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19479 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19480 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19481 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19482 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19483 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19484 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19486 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19626 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19630 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19631 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19632 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19633 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19634 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19635 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19636 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19637 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19638 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19639 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19640 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19642 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19643 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19644 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19645 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19646 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19647 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19648 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19649 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19650 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19651 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19652 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19653 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19655 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19656 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19657 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19658 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19660 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19661 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19662 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19663 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19664 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19665 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19666 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19667 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19668 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19669 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19670 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19671 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19673 /* The implementation of the FIX instruction is broken on some
19674 assemblers, in that it accepts a precision specifier as well as a
19675 rounding specifier, despite the fact that this is meaningless.
19676 To be more compatible, we accept it as well, though of course it
19677 does not set any bits. */
19678 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19679 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19680 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19681 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19682 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19683 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19684 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19685 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19686 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19687 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19688 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19689 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19690 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19692 /* Instructions that were new with the real FPA, call them V2. */
19694 #define ARM_VARIANT & fpu_fpa_ext_v2
19696 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19697 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19698 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19699 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19700 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19701 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19704 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19706 /* Moves and type conversions. */
19707 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19708 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19709 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19710 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19711 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19712 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19713 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19714 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19715 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19716 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19717 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19718 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19719 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19720 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19722 /* Memory operations. */
19723 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19724 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19725 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19726 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19727 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19728 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19729 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19730 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19731 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19732 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19733 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19734 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19735 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19736 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19737 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19738 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19739 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19740 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19742 /* Monadic operations. */
19743 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19744 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19745 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19747 /* Dyadic operations. */
19748 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19749 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19750 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19751 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19752 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19753 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19754 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19755 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19756 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19759 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19760 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19761 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19762 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19764 /* Double precision load/store are still present on single precision
19765 implementations. */
19766 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19767 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19768 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19769 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19770 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19771 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19772 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19773 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19774 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19775 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19778 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19780 /* Moves and type conversions. */
19781 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19782 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19783 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19784 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19785 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19786 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19787 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19788 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19789 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19790 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19791 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19792 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19793 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19795 /* Monadic operations. */
19796 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19797 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19798 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19800 /* Dyadic operations. */
19801 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19802 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19803 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19804 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19805 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19806 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19807 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19808 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19809 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19812 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19813 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19814 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19815 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19818 #define ARM_VARIANT & fpu_vfp_ext_v2
19820 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19821 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19822 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19823 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19825 /* Instructions which may belong to either the Neon or VFP instruction sets.
19826 Individual encoder functions perform additional architecture checks. */
19828 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19829 #undef THUMB_VARIANT
19830 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19832 /* These mnemonics are unique to VFP. */
19833 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19834 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19835 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19836 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19837 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19838 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19839 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19840 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19841 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19842 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19844 /* Mnemonics shared by Neon and VFP. */
19845 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19846 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19847 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19849 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19850 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19852 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19853 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19855 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19856 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19857 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19858 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19859 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19860 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19861 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19862 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19864 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19865 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19866 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19867 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19870 /* NOTE: All VMOV encoding is special-cased! */
19871 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19872 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19874 #undef THUMB_VARIANT
19875 #define THUMB_VARIANT & fpu_neon_ext_v1
19877 #define ARM_VARIANT & fpu_neon_ext_v1
19879 /* Data processing with three registers of the same length. */
19880 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19881 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19882 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19883 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19884 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19885 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19886 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19887 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19888 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19889 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19890 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19891 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19892 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19893 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19894 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19895 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19896 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19897 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19898 /* If not immediate, fall back to neon_dyadic_i64_su.
19899 shl_imm should accept I8 I16 I32 I64,
19900 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19901 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19902 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19903 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19904 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19905 /* Logic ops, types optional & ignored. */
19906 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19907 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19908 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19909 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19910 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19911 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19912 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19913 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19914 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19915 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19916 /* Bitfield ops, untyped. */
19917 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19918 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19919 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19920 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19921 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19922 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19923 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19924 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19925 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19926 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19927 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19928 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19929 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19930 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19931 back to neon_dyadic_if_su. */
19932 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19933 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19934 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19935 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19936 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19937 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19938 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19939 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19940 /* Comparison. Type I8 I16 I32 F32. */
19941 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19942 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19943 /* As above, D registers only. */
19944 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19945 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19946 /* Int and float variants, signedness unimportant. */
19947 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19948 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19949 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19950 /* Add/sub take types I8 I16 I32 I64 F32. */
19951 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19952 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19953 /* vtst takes sizes 8, 16, 32. */
19954 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19955 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19956 /* VMUL takes I8 I16 I32 F32 P8. */
19957 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19958 /* VQD{R}MULH takes S16 S32. */
19959 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19960 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19961 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19962 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19963 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19964 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19965 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19966 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19967 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19968 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19969 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19970 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19971 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19972 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19973 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19974 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19975 /* ARM v8.1 extension. */
19976 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19977 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19978 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19979 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19981 /* Two address, int/float. Types S8 S16 S32 F32. */
19982 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19983 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19985 /* Data processing with two registers and a shift amount. */
19986 /* Right shifts, and variants with rounding.
19987 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19988 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19989 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19990 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19991 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19992 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19993 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19994 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19995 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19996 /* Shift and insert. Sizes accepted 8 16 32 64. */
19997 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19998 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19999 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20000 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20001 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20002 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20003 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20004 /* Right shift immediate, saturating & narrowing, with rounding variants.
20005 Types accepted S16 S32 S64 U16 U32 U64. */
20006 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20007 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20008 /* As above, unsigned. Types accepted S16 S32 S64. */
20009 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20010 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20011 /* Right shift narrowing. Types accepted I16 I32 I64. */
20012 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20013 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20014 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20015 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20016 /* CVT with optional immediate for fixed-point variant. */
20017 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20019 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20020 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20022 /* Data processing, three registers of different lengths. */
20023 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20024 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20025 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20026 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20027 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20028 /* If not scalar, fall back to neon_dyadic_long.
20029 Vector types as above, scalar types S16 S32 U16 U32. */
20030 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20031 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20032 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20033 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20034 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20035 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20036 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20037 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20038 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20039 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20040 /* Saturating doubling multiplies. Types S16 S32. */
20041 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20042 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20043 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20044 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20045 S16 S32 U16 U32. */
20046 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20048 /* Extract. Size 8. */
20049 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20050 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20052 /* Two registers, miscellaneous. */
20053 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20054 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20055 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20056 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20057 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20058 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20059 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20060 /* Vector replicate. Sizes 8 16 32. */
20061 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20062 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20063 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20064 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20065 /* VMOVN. Types I16 I32 I64. */
20066 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20067 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20068 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20069 /* VQMOVUN. Types S16 S32 S64. */
20070 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20071 /* VZIP / VUZP. Sizes 8 16 32. */
20072 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20073 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20074 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20075 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20076 /* VQABS / VQNEG. Types S8 S16 S32. */
20077 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20078 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20079 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20080 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20081 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20082 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20083 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20084 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20085 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20086 /* Reciprocal estimates. Types U32 F32. */
20087 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20088 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20089 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20090 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20091 /* VCLS. Types S8 S16 S32. */
20092 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20093 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20094 /* VCLZ. Types I8 I16 I32. */
20095 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20096 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20097 /* VCNT. Size 8. */
20098 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20099 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20100 /* Two address, untyped. */
20101 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20102 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20103 /* VTRN. Sizes 8 16 32. */
20104 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20105 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20107 /* Table lookup. Size 8. */
20108 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20109 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20111 #undef THUMB_VARIANT
20112 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20114 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20116 /* Neon element/structure load/store. */
20117 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20118 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20119 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20120 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20121 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20122 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20123 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20124 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20126 #undef THUMB_VARIANT
20127 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20129 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20130 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20131 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20132 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20133 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20134 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20135 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20136 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20137 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20138 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20140 #undef THUMB_VARIANT
20141 #define THUMB_VARIANT & fpu_vfp_ext_v3
20143 #define ARM_VARIANT & fpu_vfp_ext_v3
20145 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20146 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20147 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20148 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20149 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20150 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20151 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20152 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20153 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20156 #define ARM_VARIANT & fpu_vfp_ext_fma
20157 #undef THUMB_VARIANT
20158 #define THUMB_VARIANT & fpu_vfp_ext_fma
20159 /* Mnemonics shared by Neon and VFP. These are included in the
20160 VFP FMA variant; NEON and VFP FMA always includes the NEON
20161 FMA instructions. */
20162 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20163 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20164 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20165 the v form should always be used. */
20166 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20167 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20168 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20169 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20170 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20171 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20173 #undef THUMB_VARIANT
20175 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20177 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20178 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20179 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20180 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20181 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20182 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20183 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20184 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20187 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20189 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20190 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20191 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20192 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20193 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20194 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20195 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20196 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20197 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20198 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20199 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20200 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20201 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20202 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20203 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20204 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20205 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20206 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20207 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20208 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20209 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20210 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20211 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20212 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20213 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20214 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20215 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20216 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20217 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20218 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20219 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20220 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20221 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20222 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20223 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20224 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20225 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20226 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20233 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20234 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20235 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20236 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20256 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20257 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20258 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20259 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20260 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20267 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20268 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20269 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20270 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20271 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20272 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20273 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20276 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20277 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20278 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20279 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20280 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20281 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20282 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20283 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20284 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20285 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20286 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20287 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20288 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20289 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20290 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20291 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20292 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20293 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20294 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20295 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20296 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20297 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20298 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20299 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20300 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20301 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20302 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20303 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20304 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20305 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20306 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20307 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20308 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20309 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20310 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20311 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20312 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20313 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20314 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20315 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20316 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20317 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20318 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20319 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20320 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20321 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20322 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20323 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20324 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20325 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20326 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20327 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20328 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20329 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20330 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20331 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20332 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20333 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20334 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20335 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20336 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20337 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20338 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20341 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20342 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20343 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20344 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20345 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20346 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20353 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20355 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20356 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20357 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20358 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20359 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20360 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20361 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20376 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20380 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20383 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20384 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20385 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20387 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20388 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20389 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20390 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20391 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20392 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20393 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20394 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20395 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20396 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20397 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20398 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20399 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20400 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20401 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20402 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20403 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20404 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20405 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20406 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20407 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20408 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20409 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20410 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20411 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20414 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20416 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20417 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20418 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20419 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20420 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20421 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20422 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20423 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20424 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20425 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20426 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20427 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20428 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20429 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20430 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20431 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20432 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20433 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20434 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20435 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20436 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20437 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20438 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20439 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20440 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20441 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20442 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20443 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20444 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20445 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20446 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20447 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20448 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20449 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20450 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20451 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20452 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20453 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20454 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20455 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20456 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20457 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20458 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20459 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20460 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20461 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20462 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20463 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20464 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20465 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20466 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20467 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20468 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20469 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20470 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20471 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20472 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20473 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20474 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20475 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20476 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20477 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20478 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20479 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20480 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20481 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20482 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20483 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20484 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20485 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20486 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20487 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20488 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20489 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20490 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20491 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20494 #undef THUMB_VARIANT
20520 /* MD interface: bits in the object file. */
20522 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20523 for use in the a.out file, and stores them in the array pointed to by buf.
20524 This knows about the endian-ness of the target machine and does
20525 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20526 2 (short) and 4 (long) Floating numbers are put out as a series of
20527 LITTLENUMS (shorts, here at least). */
20530 md_number_to_chars (char * buf
, valueT val
, int n
)
20532 if (target_big_endian
)
20533 number_to_chars_bigendian (buf
, val
, n
);
20535 number_to_chars_littleendian (buf
, val
, n
);
20539 md_chars_to_number (char * buf
, int n
)
20542 unsigned char * where
= (unsigned char *) buf
;
20544 if (target_big_endian
)
20549 result
|= (*where
++ & 255);
20557 result
|= (where
[n
] & 255);
20564 /* MD interface: Sections. */
20566 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20567 that an rs_machine_dependent frag may reach. */
20570 arm_frag_max_var (fragS
*fragp
)
20572 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20573 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20575 Note that we generate relaxable instructions even for cases that don't
20576 really need it, like an immediate that's a trivial constant. So we're
20577 overestimating the instruction size for some of those cases. Rather
20578 than putting more intelligence here, it would probably be better to
20579 avoid generating a relaxation frag in the first place when it can be
20580 determined up front that a short instruction will suffice. */
20582 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20586 /* Estimate the size of a frag before relaxing. Assume everything fits in
20590 md_estimate_size_before_relax (fragS
* fragp
,
20591 segT segtype ATTRIBUTE_UNUSED
)
20597 /* Convert a machine dependent frag. */
20600 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20602 unsigned long insn
;
20603 unsigned long old_op
;
20611 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20613 old_op
= bfd_get_16(abfd
, buf
);
20614 if (fragp
->fr_symbol
)
20616 exp
.X_op
= O_symbol
;
20617 exp
.X_add_symbol
= fragp
->fr_symbol
;
20621 exp
.X_op
= O_constant
;
20623 exp
.X_add_number
= fragp
->fr_offset
;
20624 opcode
= fragp
->fr_subtype
;
20627 case T_MNEM_ldr_pc
:
20628 case T_MNEM_ldr_pc2
:
20629 case T_MNEM_ldr_sp
:
20630 case T_MNEM_str_sp
:
20637 if (fragp
->fr_var
== 4)
20639 insn
= THUMB_OP32 (opcode
);
20640 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20642 insn
|= (old_op
& 0x700) << 4;
20646 insn
|= (old_op
& 7) << 12;
20647 insn
|= (old_op
& 0x38) << 13;
20649 insn
|= 0x00000c00;
20650 put_thumb32_insn (buf
, insn
);
20651 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20655 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20657 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20660 if (fragp
->fr_var
== 4)
20662 insn
= THUMB_OP32 (opcode
);
20663 insn
|= (old_op
& 0xf0) << 4;
20664 put_thumb32_insn (buf
, insn
);
20665 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20669 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20670 exp
.X_add_number
-= 4;
20678 if (fragp
->fr_var
== 4)
20680 int r0off
= (opcode
== T_MNEM_mov
20681 || opcode
== T_MNEM_movs
) ? 0 : 8;
20682 insn
= THUMB_OP32 (opcode
);
20683 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20684 insn
|= (old_op
& 0x700) << r0off
;
20685 put_thumb32_insn (buf
, insn
);
20686 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20690 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20695 if (fragp
->fr_var
== 4)
20697 insn
= THUMB_OP32(opcode
);
20698 put_thumb32_insn (buf
, insn
);
20699 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20702 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20706 if (fragp
->fr_var
== 4)
20708 insn
= THUMB_OP32(opcode
);
20709 insn
|= (old_op
& 0xf00) << 14;
20710 put_thumb32_insn (buf
, insn
);
20711 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20714 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20717 case T_MNEM_add_sp
:
20718 case T_MNEM_add_pc
:
20719 case T_MNEM_inc_sp
:
20720 case T_MNEM_dec_sp
:
20721 if (fragp
->fr_var
== 4)
20723 /* ??? Choose between add and addw. */
20724 insn
= THUMB_OP32 (opcode
);
20725 insn
|= (old_op
& 0xf0) << 4;
20726 put_thumb32_insn (buf
, insn
);
20727 if (opcode
== T_MNEM_add_pc
)
20728 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20730 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20733 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20741 if (fragp
->fr_var
== 4)
20743 insn
= THUMB_OP32 (opcode
);
20744 insn
|= (old_op
& 0xf0) << 4;
20745 insn
|= (old_op
& 0xf) << 16;
20746 put_thumb32_insn (buf
, insn
);
20747 if (insn
& (1 << 20))
20748 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20750 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20753 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20759 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20760 (enum bfd_reloc_code_real
) reloc_type
);
20761 fixp
->fx_file
= fragp
->fr_file
;
20762 fixp
->fx_line
= fragp
->fr_line
;
20763 fragp
->fr_fix
+= fragp
->fr_var
;
20765 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20766 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20767 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20768 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20771 /* Return the size of a relaxable immediate operand instruction.
20772 SHIFT and SIZE specify the form of the allowable immediate. */
20774 relax_immediate (fragS
*fragp
, int size
, int shift
)
20780 /* ??? Should be able to do better than this. */
20781 if (fragp
->fr_symbol
)
20784 low
= (1 << shift
) - 1;
20785 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20786 offset
= fragp
->fr_offset
;
20787 /* Force misaligned offsets to 32-bit variant. */
20790 if (offset
& ~mask
)
20795 /* Get the address of a symbol during relaxation. */
20797 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20803 sym
= fragp
->fr_symbol
;
20804 sym_frag
= symbol_get_frag (sym
);
20805 know (S_GET_SEGMENT (sym
) != absolute_section
20806 || sym_frag
== &zero_address_frag
);
20807 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20809 /* If frag has yet to be reached on this pass, assume it will
20810 move by STRETCH just as we did. If this is not so, it will
20811 be because some frag between grows, and that will force
20815 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20819 /* Adjust stretch for any alignment frag. Note that if have
20820 been expanding the earlier code, the symbol may be
20821 defined in what appears to be an earlier frag. FIXME:
20822 This doesn't handle the fr_subtype field, which specifies
20823 a maximum number of bytes to skip when doing an
20825 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20827 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20830 stretch
= - ((- stretch
)
20831 & ~ ((1 << (int) f
->fr_offset
) - 1));
20833 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20845 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20848 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20853 /* Assume worst case for symbols not known to be in the same section. */
20854 if (fragp
->fr_symbol
== NULL
20855 || !S_IS_DEFINED (fragp
->fr_symbol
)
20856 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20857 || S_IS_WEAK (fragp
->fr_symbol
))
20860 val
= relaxed_symbol_addr (fragp
, stretch
);
20861 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20862 addr
= (addr
+ 4) & ~3;
20863 /* Force misaligned targets to 32-bit variant. */
20867 if (val
< 0 || val
> 1020)
20872 /* Return the size of a relaxable add/sub immediate instruction. */
20874 relax_addsub (fragS
*fragp
, asection
*sec
)
20879 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20880 op
= bfd_get_16(sec
->owner
, buf
);
20881 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20882 return relax_immediate (fragp
, 8, 0);
20884 return relax_immediate (fragp
, 3, 0);
20887 /* Return TRUE iff the definition of symbol S could be pre-empted
20888 (overridden) at link or load time. */
20890 symbol_preemptible (symbolS
*s
)
20892 /* Weak symbols can always be pre-empted. */
20896 /* Non-global symbols cannot be pre-empted. */
20897 if (! S_IS_EXTERNAL (s
))
20901 /* In ELF, a global symbol can be marked protected, or private. In that
20902 case it can't be pre-empted (other definitions in the same link unit
20903 would violate the ODR). */
20904 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20908 /* Other global symbols might be pre-empted. */
20912 /* Return the size of a relaxable branch instruction. BITS is the
20913 size of the offset field in the narrow instruction. */
20916 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20922 /* Assume worst case for symbols not known to be in the same section. */
20923 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20924 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20925 || S_IS_WEAK (fragp
->fr_symbol
))
20929 /* A branch to a function in ARM state will require interworking. */
20930 if (S_IS_DEFINED (fragp
->fr_symbol
)
20931 && ARM_IS_FUNC (fragp
->fr_symbol
))
20935 if (symbol_preemptible (fragp
->fr_symbol
))
20938 val
= relaxed_symbol_addr (fragp
, stretch
);
20939 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20942 /* Offset is a signed value *2 */
20944 if (val
>= limit
|| val
< -limit
)
20950 /* Relax a machine dependent frag. This returns the amount by which
20951 the current size of the frag should change. */
20954 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20959 oldsize
= fragp
->fr_var
;
20960 switch (fragp
->fr_subtype
)
20962 case T_MNEM_ldr_pc2
:
20963 newsize
= relax_adr (fragp
, sec
, stretch
);
20965 case T_MNEM_ldr_pc
:
20966 case T_MNEM_ldr_sp
:
20967 case T_MNEM_str_sp
:
20968 newsize
= relax_immediate (fragp
, 8, 2);
20972 newsize
= relax_immediate (fragp
, 5, 2);
20976 newsize
= relax_immediate (fragp
, 5, 1);
20980 newsize
= relax_immediate (fragp
, 5, 0);
20983 newsize
= relax_adr (fragp
, sec
, stretch
);
20989 newsize
= relax_immediate (fragp
, 8, 0);
20992 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20995 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20997 case T_MNEM_add_sp
:
20998 case T_MNEM_add_pc
:
20999 newsize
= relax_immediate (fragp
, 8, 2);
21001 case T_MNEM_inc_sp
:
21002 case T_MNEM_dec_sp
:
21003 newsize
= relax_immediate (fragp
, 7, 2);
21009 newsize
= relax_addsub (fragp
, sec
);
21015 fragp
->fr_var
= newsize
;
21016 /* Freeze wide instructions that are at or before the same location as
21017 in the previous pass. This avoids infinite loops.
21018 Don't freeze them unconditionally because targets may be artificially
21019 misaligned by the expansion of preceding frags. */
21020 if (stretch
<= 0 && newsize
> 2)
21022 md_convert_frag (sec
->owner
, sec
, fragp
);
21026 return newsize
- oldsize
;
21029 /* Round up a section size to the appropriate boundary. */
21032 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21035 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21036 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21038 /* For a.out, force the section size to be aligned. If we don't do
21039 this, BFD will align it for us, but it will not write out the
21040 final bytes of the section. This may be a bug in BFD, but it is
21041 easier to fix it here since that is how the other a.out targets
21045 align
= bfd_get_section_alignment (stdoutput
, segment
);
21046 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
21053 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21054 of an rs_align_code fragment. */
21057 arm_handle_align (fragS
* fragP
)
21059 static char const arm_noop
[2][2][4] =
21062 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21063 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21066 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21067 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21070 static char const thumb_noop
[2][2][2] =
21073 {0xc0, 0x46}, /* LE */
21074 {0x46, 0xc0}, /* BE */
21077 {0x00, 0xbf}, /* LE */
21078 {0xbf, 0x00} /* BE */
21081 static char const wide_thumb_noop
[2][4] =
21082 { /* Wide Thumb-2 */
21083 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21084 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21087 unsigned bytes
, fix
, noop_size
;
21090 const char *narrow_noop
= NULL
;
21095 if (fragP
->fr_type
!= rs_align_code
)
21098 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21099 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21102 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21103 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21105 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21107 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21109 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21110 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21112 narrow_noop
= thumb_noop
[1][target_big_endian
];
21113 noop
= wide_thumb_noop
[target_big_endian
];
21116 noop
= thumb_noop
[0][target_big_endian
];
21124 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21125 ? selected_cpu
: arm_arch_none
,
21127 [target_big_endian
];
21134 fragP
->fr_var
= noop_size
;
21136 if (bytes
& (noop_size
- 1))
21138 fix
= bytes
& (noop_size
- 1);
21140 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21142 memset (p
, 0, fix
);
21149 if (bytes
& noop_size
)
21151 /* Insert a narrow noop. */
21152 memcpy (p
, narrow_noop
, noop_size
);
21154 bytes
-= noop_size
;
21158 /* Use wide noops for the remainder */
21162 while (bytes
>= noop_size
)
21164 memcpy (p
, noop
, noop_size
);
21166 bytes
-= noop_size
;
21170 fragP
->fr_fix
+= fix
;
21173 /* Called from md_do_align. Used to create an alignment
21174 frag in a code section. */
21177 arm_frag_align_code (int n
, int max
)
21181 /* We assume that there will never be a requirement
21182 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21183 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21188 _("alignments greater than %d bytes not supported in .text sections."),
21189 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21190 as_fatal ("%s", err_msg
);
21193 p
= frag_var (rs_align_code
,
21194 MAX_MEM_FOR_RS_ALIGN_CODE
,
21196 (relax_substateT
) max
,
21203 /* Perform target specific initialisation of a frag.
21204 Note - despite the name this initialisation is not done when the frag
21205 is created, but only when its type is assigned. A frag can be created
21206 and used a long time before its type is set, so beware of assuming that
21207 this initialisationis performed first. */
21211 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21213 /* Record whether this frag is in an ARM or a THUMB area. */
21214 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21217 #else /* OBJ_ELF is defined. */
21219 arm_init_frag (fragS
* fragP
, int max_chars
)
21221 int frag_thumb_mode
;
21223 /* If the current ARM vs THUMB mode has not already
21224 been recorded into this frag then do so now. */
21225 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21226 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21228 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21230 /* Record a mapping symbol for alignment frags. We will delete this
21231 later if the alignment ends up empty. */
21232 switch (fragP
->fr_type
)
21235 case rs_align_test
:
21237 mapping_state_2 (MAP_DATA
, max_chars
);
21239 case rs_align_code
:
21240 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21247 /* When we change sections we need to issue a new mapping symbol. */
21250 arm_elf_change_section (void)
21252 /* Link an unlinked unwind index table section to the .text section. */
21253 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21254 && elf_linked_to_section (now_seg
) == NULL
)
21255 elf_linked_to_section (now_seg
) = text_section
;
21259 arm_elf_section_type (const char * str
, size_t len
)
21261 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21262 return SHT_ARM_EXIDX
;
21267 /* Code to deal with unwinding tables. */
21269 static void add_unwind_adjustsp (offsetT
);
21271 /* Generate any deferred unwind frame offset. */
21274 flush_pending_unwind (void)
21278 offset
= unwind
.pending_offset
;
21279 unwind
.pending_offset
= 0;
21281 add_unwind_adjustsp (offset
);
21284 /* Add an opcode to this list for this function. Two-byte opcodes should
21285 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21289 add_unwind_opcode (valueT op
, int length
)
21291 /* Add any deferred stack adjustment. */
21292 if (unwind
.pending_offset
)
21293 flush_pending_unwind ();
21295 unwind
.sp_restored
= 0;
21297 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21299 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21300 if (unwind
.opcodes
)
21301 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21302 unwind
.opcode_alloc
);
21304 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21309 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21311 unwind
.opcode_count
++;
21315 /* Add unwind opcodes to adjust the stack pointer. */
21318 add_unwind_adjustsp (offsetT offset
)
21322 if (offset
> 0x200)
21324 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21329 /* Long form: 0xb2, uleb128. */
21330 /* This might not fit in a word so add the individual bytes,
21331 remembering the list is built in reverse order. */
21332 o
= (valueT
) ((offset
- 0x204) >> 2);
21334 add_unwind_opcode (0, 1);
21336 /* Calculate the uleb128 encoding of the offset. */
21340 bytes
[n
] = o
& 0x7f;
21346 /* Add the insn. */
21348 add_unwind_opcode (bytes
[n
- 1], 1);
21349 add_unwind_opcode (0xb2, 1);
21351 else if (offset
> 0x100)
21353 /* Two short opcodes. */
21354 add_unwind_opcode (0x3f, 1);
21355 op
= (offset
- 0x104) >> 2;
21356 add_unwind_opcode (op
, 1);
21358 else if (offset
> 0)
21360 /* Short opcode. */
21361 op
= (offset
- 4) >> 2;
21362 add_unwind_opcode (op
, 1);
21364 else if (offset
< 0)
21367 while (offset
> 0x100)
21369 add_unwind_opcode (0x7f, 1);
21372 op
= ((offset
- 4) >> 2) | 0x40;
21373 add_unwind_opcode (op
, 1);
21377 /* Finish the list of unwind opcodes for this function. */
21379 finish_unwind_opcodes (void)
21383 if (unwind
.fp_used
)
21385 /* Adjust sp as necessary. */
21386 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21387 flush_pending_unwind ();
21389 /* After restoring sp from the frame pointer. */
21390 op
= 0x90 | unwind
.fp_reg
;
21391 add_unwind_opcode (op
, 1);
21394 flush_pending_unwind ();
21398 /* Start an exception table entry. If idx is nonzero this is an index table
21402 start_unwind_section (const segT text_seg
, int idx
)
21404 const char * text_name
;
21405 const char * prefix
;
21406 const char * prefix_once
;
21407 const char * group_name
;
21411 size_t sec_name_len
;
21418 prefix
= ELF_STRING_ARM_unwind
;
21419 prefix_once
= ELF_STRING_ARM_unwind_once
;
21420 type
= SHT_ARM_EXIDX
;
21424 prefix
= ELF_STRING_ARM_unwind_info
;
21425 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21426 type
= SHT_PROGBITS
;
21429 text_name
= segment_name (text_seg
);
21430 if (streq (text_name
, ".text"))
21433 if (strncmp (text_name
, ".gnu.linkonce.t.",
21434 strlen (".gnu.linkonce.t.")) == 0)
21436 prefix
= prefix_once
;
21437 text_name
+= strlen (".gnu.linkonce.t.");
21440 prefix_len
= strlen (prefix
);
21441 text_len
= strlen (text_name
);
21442 sec_name_len
= prefix_len
+ text_len
;
21443 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21444 memcpy (sec_name
, prefix
, prefix_len
);
21445 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21446 sec_name
[prefix_len
+ text_len
] = '\0';
21452 /* Handle COMDAT group. */
21453 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21455 group_name
= elf_group_name (text_seg
);
21456 if (group_name
== NULL
)
21458 as_bad (_("Group section `%s' has no group signature"),
21459 segment_name (text_seg
));
21460 ignore_rest_of_line ();
21463 flags
|= SHF_GROUP
;
21467 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21469 /* Set the section link for index tables. */
21471 elf_linked_to_section (now_seg
) = text_seg
;
21475 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21476 personality routine data. Returns zero, or the index table value for
21477 an inline entry. */
21480 create_unwind_entry (int have_data
)
21485 /* The current word of data. */
21487 /* The number of bytes left in this word. */
21490 finish_unwind_opcodes ();
21492 /* Remember the current text section. */
21493 unwind
.saved_seg
= now_seg
;
21494 unwind
.saved_subseg
= now_subseg
;
21496 start_unwind_section (now_seg
, 0);
21498 if (unwind
.personality_routine
== NULL
)
21500 if (unwind
.personality_index
== -2)
21503 as_bad (_("handlerdata in cantunwind frame"));
21504 return 1; /* EXIDX_CANTUNWIND. */
21507 /* Use a default personality routine if none is specified. */
21508 if (unwind
.personality_index
== -1)
21510 if (unwind
.opcode_count
> 3)
21511 unwind
.personality_index
= 1;
21513 unwind
.personality_index
= 0;
21516 /* Space for the personality routine entry. */
21517 if (unwind
.personality_index
== 0)
21519 if (unwind
.opcode_count
> 3)
21520 as_bad (_("too many unwind opcodes for personality routine 0"));
21524 /* All the data is inline in the index table. */
21527 while (unwind
.opcode_count
> 0)
21529 unwind
.opcode_count
--;
21530 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21534 /* Pad with "finish" opcodes. */
21536 data
= (data
<< 8) | 0xb0;
21543 /* We get two opcodes "free" in the first word. */
21544 size
= unwind
.opcode_count
- 2;
21548 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21549 if (unwind
.personality_index
!= -1)
21551 as_bad (_("attempt to recreate an unwind entry"));
21555 /* An extra byte is required for the opcode count. */
21556 size
= unwind
.opcode_count
+ 1;
21559 size
= (size
+ 3) >> 2;
21561 as_bad (_("too many unwind opcodes"));
21563 frag_align (2, 0, 0);
21564 record_alignment (now_seg
, 2);
21565 unwind
.table_entry
= expr_build_dot ();
21567 /* Allocate the table entry. */
21568 ptr
= frag_more ((size
<< 2) + 4);
21569 /* PR 13449: Zero the table entries in case some of them are not used. */
21570 memset (ptr
, 0, (size
<< 2) + 4);
21571 where
= frag_now_fix () - ((size
<< 2) + 4);
21573 switch (unwind
.personality_index
)
21576 /* ??? Should this be a PLT generating relocation? */
21577 /* Custom personality routine. */
21578 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21579 BFD_RELOC_ARM_PREL31
);
21584 /* Set the first byte to the number of additional words. */
21585 data
= size
> 0 ? size
- 1 : 0;
21589 /* ABI defined personality routines. */
21591 /* Three opcodes bytes are packed into the first word. */
21598 /* The size and first two opcode bytes go in the first word. */
21599 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21604 /* Should never happen. */
21608 /* Pack the opcodes into words (MSB first), reversing the list at the same
21610 while (unwind
.opcode_count
> 0)
21614 md_number_to_chars (ptr
, data
, 4);
21619 unwind
.opcode_count
--;
21621 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21624 /* Finish off the last word. */
21627 /* Pad with "finish" opcodes. */
21629 data
= (data
<< 8) | 0xb0;
21631 md_number_to_chars (ptr
, data
, 4);
21636 /* Add an empty descriptor if there is no user-specified data. */
21637 ptr
= frag_more (4);
21638 md_number_to_chars (ptr
, 0, 4);
21645 /* Initialize the DWARF-2 unwind information for this procedure. */
21648 tc_arm_frame_initial_instructions (void)
21650 cfi_add_CFA_def_cfa (REG_SP
, 0);
21652 #endif /* OBJ_ELF */
21654 /* Convert REGNAME to a DWARF-2 register number. */
21657 tc_arm_regname_to_dw2regnum (char *regname
)
21659 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21663 /* PR 16694: Allow VFP registers as well. */
21664 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21668 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21677 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21681 exp
.X_op
= O_secrel
;
21682 exp
.X_add_symbol
= symbol
;
21683 exp
.X_add_number
= 0;
21684 emit_expr (&exp
, size
);
21688 /* MD interface: Symbol and relocation handling. */
21690 /* Return the address within the segment that a PC-relative fixup is
21691 relative to. For ARM, PC-relative fixups applied to instructions
21692 are generally relative to the location of the fixup plus 8 bytes.
21693 Thumb branches are offset by 4, and Thumb loads relative to PC
21694 require special handling. */
21697 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21699 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21701 /* If this is pc-relative and we are going to emit a relocation
21702 then we just want to put out any pipeline compensation that the linker
21703 will need. Otherwise we want to use the calculated base.
21704 For WinCE we skip the bias for externals as well, since this
21705 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21707 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21708 || (arm_force_relocation (fixP
)
21710 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21716 switch (fixP
->fx_r_type
)
21718 /* PC relative addressing on the Thumb is slightly odd as the
21719 bottom two bits of the PC are forced to zero for the
21720 calculation. This happens *after* application of the
21721 pipeline offset. However, Thumb adrl already adjusts for
21722 this, so we need not do it again. */
21723 case BFD_RELOC_ARM_THUMB_ADD
:
21726 case BFD_RELOC_ARM_THUMB_OFFSET
:
21727 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21728 case BFD_RELOC_ARM_T32_ADD_PC12
:
21729 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21730 return (base
+ 4) & ~3;
21732 /* Thumb branches are simply offset by +4. */
21733 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21734 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21735 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21736 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21737 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21740 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21742 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21743 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21744 && ARM_IS_FUNC (fixP
->fx_addsy
)
21745 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21746 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21749 /* BLX is like branches above, but forces the low two bits of PC to
21751 case BFD_RELOC_THUMB_PCREL_BLX
:
21753 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21754 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21755 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21756 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21757 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21758 return (base
+ 4) & ~3;
21760 /* ARM mode branches are offset by +8. However, the Windows CE
21761 loader expects the relocation not to take this into account. */
21762 case BFD_RELOC_ARM_PCREL_BLX
:
21764 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21765 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21766 && ARM_IS_FUNC (fixP
->fx_addsy
)
21767 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21768 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21771 case BFD_RELOC_ARM_PCREL_CALL
:
21773 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21774 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21775 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21776 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21777 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21780 case BFD_RELOC_ARM_PCREL_BRANCH
:
21781 case BFD_RELOC_ARM_PCREL_JUMP
:
21782 case BFD_RELOC_ARM_PLT32
:
21784 /* When handling fixups immediately, because we have already
21785 discovered the value of a symbol, or the address of the frag involved
21786 we must account for the offset by +8, as the OS loader will never see the reloc.
21787 see fixup_segment() in write.c
21788 The S_IS_EXTERNAL test handles the case of global symbols.
21789 Those need the calculated base, not just the pipe compensation the linker will need. */
21791 && fixP
->fx_addsy
!= NULL
21792 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21793 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21801 /* ARM mode loads relative to PC are also offset by +8. Unlike
21802 branches, the Windows CE loader *does* expect the relocation
21803 to take this into account. */
21804 case BFD_RELOC_ARM_OFFSET_IMM
:
21805 case BFD_RELOC_ARM_OFFSET_IMM8
:
21806 case BFD_RELOC_ARM_HWLITERAL
:
21807 case BFD_RELOC_ARM_LITERAL
:
21808 case BFD_RELOC_ARM_CP_OFF_IMM
:
21812 /* Other PC-relative relocations are un-offset. */
21818 static bfd_boolean flag_warn_syms
= TRUE
;
21821 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21823 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21824 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21825 does mean that the resulting code might be very confusing to the reader.
21826 Also this warning can be triggered if the user omits an operand before
21827 an immediate address, eg:
21831 GAS treats this as an assignment of the value of the symbol foo to a
21832 symbol LDR, and so (without this code) it will not issue any kind of
21833 warning or error message.
21835 Note - ARM instructions are case-insensitive but the strings in the hash
21836 table are all stored in lower case, so we must first ensure that name is
21838 if (flag_warn_syms
&& arm_ops_hsh
)
21840 char * nbuf
= strdup (name
);
21843 for (p
= nbuf
; *p
; p
++)
21845 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21847 static struct hash_control
* already_warned
= NULL
;
21849 if (already_warned
== NULL
)
21850 already_warned
= hash_new ();
21851 /* Only warn about the symbol once. To keep the code
21852 simple we let hash_insert do the lookup for us. */
21853 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21854 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21863 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21864 Otherwise we have no need to default values of symbols. */
21867 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21870 if (name
[0] == '_' && name
[1] == 'G'
21871 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21875 if (symbol_find (name
))
21876 as_bad (_("GOT already in the symbol table"));
21878 GOT_symbol
= symbol_new (name
, undefined_section
,
21879 (valueT
) 0, & zero_address_frag
);
21889 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21890 computed as two separate immediate values, added together. We
21891 already know that this value cannot be computed by just one ARM
21894 static unsigned int
21895 validate_immediate_twopart (unsigned int val
,
21896 unsigned int * highpart
)
21901 for (i
= 0; i
< 32; i
+= 2)
21902 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21908 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21910 else if (a
& 0xff0000)
21912 if (a
& 0xff000000)
21914 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21918 gas_assert (a
& 0xff000000);
21919 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21922 return (a
& 0xff) | (i
<< 7);
21929 validate_offset_imm (unsigned int val
, int hwse
)
21931 if ((hwse
&& val
> 255) || val
> 4095)
21936 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21937 negative immediate constant by altering the instruction. A bit of
21942 by inverting the second operand, and
21945 by negating the second operand. */
21948 negate_data_op (unsigned long * instruction
,
21949 unsigned long value
)
21952 unsigned long negated
, inverted
;
21954 negated
= encode_arm_immediate (-value
);
21955 inverted
= encode_arm_immediate (~value
);
21957 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21960 /* First negates. */
21961 case OPCODE_SUB
: /* ADD <-> SUB */
21962 new_inst
= OPCODE_ADD
;
21967 new_inst
= OPCODE_SUB
;
21971 case OPCODE_CMP
: /* CMP <-> CMN */
21972 new_inst
= OPCODE_CMN
;
21977 new_inst
= OPCODE_CMP
;
21981 /* Now Inverted ops. */
21982 case OPCODE_MOV
: /* MOV <-> MVN */
21983 new_inst
= OPCODE_MVN
;
21988 new_inst
= OPCODE_MOV
;
21992 case OPCODE_AND
: /* AND <-> BIC */
21993 new_inst
= OPCODE_BIC
;
21998 new_inst
= OPCODE_AND
;
22002 case OPCODE_ADC
: /* ADC <-> SBC */
22003 new_inst
= OPCODE_SBC
;
22008 new_inst
= OPCODE_ADC
;
22012 /* We cannot do anything. */
22017 if (value
== (unsigned) FAIL
)
22020 *instruction
&= OPCODE_MASK
;
22021 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22025 /* Like negate_data_op, but for Thumb-2. */
22027 static unsigned int
22028 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22032 unsigned int negated
, inverted
;
22034 negated
= encode_thumb32_immediate (-value
);
22035 inverted
= encode_thumb32_immediate (~value
);
22037 rd
= (*instruction
>> 8) & 0xf;
22038 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22041 /* ADD <-> SUB. Includes CMP <-> CMN. */
22042 case T2_OPCODE_SUB
:
22043 new_inst
= T2_OPCODE_ADD
;
22047 case T2_OPCODE_ADD
:
22048 new_inst
= T2_OPCODE_SUB
;
22052 /* ORR <-> ORN. Includes MOV <-> MVN. */
22053 case T2_OPCODE_ORR
:
22054 new_inst
= T2_OPCODE_ORN
;
22058 case T2_OPCODE_ORN
:
22059 new_inst
= T2_OPCODE_ORR
;
22063 /* AND <-> BIC. TST has no inverted equivalent. */
22064 case T2_OPCODE_AND
:
22065 new_inst
= T2_OPCODE_BIC
;
22072 case T2_OPCODE_BIC
:
22073 new_inst
= T2_OPCODE_AND
;
22078 case T2_OPCODE_ADC
:
22079 new_inst
= T2_OPCODE_SBC
;
22083 case T2_OPCODE_SBC
:
22084 new_inst
= T2_OPCODE_ADC
;
22088 /* We cannot do anything. */
22093 if (value
== (unsigned int)FAIL
)
22096 *instruction
&= T2_OPCODE_MASK
;
22097 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22101 /* Read a 32-bit thumb instruction from buf. */
22102 static unsigned long
22103 get_thumb32_insn (char * buf
)
22105 unsigned long insn
;
22106 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22107 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22113 /* We usually want to set the low bit on the address of thumb function
22114 symbols. In particular .word foo - . should have the low bit set.
22115 Generic code tries to fold the difference of two symbols to
22116 a constant. Prevent this and force a relocation when the first symbols
22117 is a thumb function. */
22120 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22122 if (op
== O_subtract
22123 && l
->X_op
== O_symbol
22124 && r
->X_op
== O_symbol
22125 && THUMB_IS_FUNC (l
->X_add_symbol
))
22127 l
->X_op
= O_subtract
;
22128 l
->X_op_symbol
= r
->X_add_symbol
;
22129 l
->X_add_number
-= r
->X_add_number
;
22133 /* Process as normal. */
22137 /* Encode Thumb2 unconditional branches and calls. The encoding
22138 for the 2 are identical for the immediate values. */
22141 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22143 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22146 addressT S
, I1
, I2
, lo
, hi
;
22148 S
= (value
>> 24) & 0x01;
22149 I1
= (value
>> 23) & 0x01;
22150 I2
= (value
>> 22) & 0x01;
22151 hi
= (value
>> 12) & 0x3ff;
22152 lo
= (value
>> 1) & 0x7ff;
22153 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22154 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22155 newval
|= (S
<< 10) | hi
;
22156 newval2
&= ~T2I1I2MASK
;
22157 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22158 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22159 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22163 md_apply_fix (fixS
* fixP
,
22167 offsetT value
= * valP
;
22169 unsigned int newimm
;
22170 unsigned long temp
;
22172 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22174 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22176 /* Note whether this will delete the relocation. */
22178 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22181 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22182 consistency with the behaviour on 32-bit hosts. Remember value
22184 value
&= 0xffffffff;
22185 value
^= 0x80000000;
22186 value
-= 0x80000000;
22189 fixP
->fx_addnumber
= value
;
22191 /* Same treatment for fixP->fx_offset. */
22192 fixP
->fx_offset
&= 0xffffffff;
22193 fixP
->fx_offset
^= 0x80000000;
22194 fixP
->fx_offset
-= 0x80000000;
22196 switch (fixP
->fx_r_type
)
22198 case BFD_RELOC_NONE
:
22199 /* This will need to go in the object file. */
22203 case BFD_RELOC_ARM_IMMEDIATE
:
22204 /* We claim that this fixup has been processed here,
22205 even if in fact we generate an error because we do
22206 not have a reloc for it, so tc_gen_reloc will reject it. */
22209 if (fixP
->fx_addsy
)
22211 const char *msg
= 0;
22213 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22214 msg
= _("undefined symbol %s used as an immediate value");
22215 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22216 msg
= _("symbol %s is in a different section");
22217 else if (S_IS_WEAK (fixP
->fx_addsy
))
22218 msg
= _("symbol %s is weak and may be overridden later");
22222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22223 msg
, S_GET_NAME (fixP
->fx_addsy
));
22228 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22230 /* If the offset is negative, we should use encoding A2 for ADR. */
22231 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22232 newimm
= negate_data_op (&temp
, value
);
22235 newimm
= encode_arm_immediate (value
);
22237 /* If the instruction will fail, see if we can fix things up by
22238 changing the opcode. */
22239 if (newimm
== (unsigned int) FAIL
)
22240 newimm
= negate_data_op (&temp
, value
);
22243 if (newimm
== (unsigned int) FAIL
)
22245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22246 _("invalid constant (%lx) after fixup"),
22247 (unsigned long) value
);
22251 newimm
|= (temp
& 0xfffff000);
22252 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22255 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22257 unsigned int highpart
= 0;
22258 unsigned int newinsn
= 0xe1a00000; /* nop. */
22260 if (fixP
->fx_addsy
)
22262 const char *msg
= 0;
22264 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22265 msg
= _("undefined symbol %s used as an immediate value");
22266 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22267 msg
= _("symbol %s is in a different section");
22268 else if (S_IS_WEAK (fixP
->fx_addsy
))
22269 msg
= _("symbol %s is weak and may be overridden later");
22273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22274 msg
, S_GET_NAME (fixP
->fx_addsy
));
22279 newimm
= encode_arm_immediate (value
);
22280 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22282 /* If the instruction will fail, see if we can fix things up by
22283 changing the opcode. */
22284 if (newimm
== (unsigned int) FAIL
22285 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22287 /* No ? OK - try using two ADD instructions to generate
22289 newimm
= validate_immediate_twopart (value
, & highpart
);
22291 /* Yes - then make sure that the second instruction is
22293 if (newimm
!= (unsigned int) FAIL
)
22295 /* Still No ? Try using a negated value. */
22296 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22297 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22298 /* Otherwise - give up. */
22301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22302 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22307 /* Replace the first operand in the 2nd instruction (which
22308 is the PC) with the destination register. We have
22309 already added in the PC in the first instruction and we
22310 do not want to do it again. */
22311 newinsn
&= ~ 0xf0000;
22312 newinsn
|= ((newinsn
& 0x0f000) << 4);
22315 newimm
|= (temp
& 0xfffff000);
22316 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22318 highpart
|= (newinsn
& 0xfffff000);
22319 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22323 case BFD_RELOC_ARM_OFFSET_IMM
:
22324 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22327 case BFD_RELOC_ARM_LITERAL
:
22333 if (validate_offset_imm (value
, 0) == FAIL
)
22335 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22337 _("invalid literal constant: pool needs to be closer"));
22339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22340 _("bad immediate value for offset (%ld)"),
22345 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22347 newval
&= 0xfffff000;
22350 newval
&= 0xff7ff000;
22351 newval
|= value
| (sign
? INDEX_UP
: 0);
22353 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22356 case BFD_RELOC_ARM_OFFSET_IMM8
:
22357 case BFD_RELOC_ARM_HWLITERAL
:
22363 if (validate_offset_imm (value
, 1) == FAIL
)
22365 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22367 _("invalid literal constant: pool needs to be closer"));
22369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22370 _("bad immediate value for 8-bit offset (%ld)"),
22375 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22377 newval
&= 0xfffff0f0;
22380 newval
&= 0xff7ff0f0;
22381 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22383 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22386 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22387 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22389 _("bad immediate value for offset (%ld)"), (long) value
);
22392 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22394 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22397 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22398 /* This is a complicated relocation used for all varieties of Thumb32
22399 load/store instruction with immediate offset:
22401 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22402 *4, optional writeback(W)
22403 (doubleword load/store)
22405 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22406 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22407 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22408 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22409 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22411 Uppercase letters indicate bits that are already encoded at
22412 this point. Lowercase letters are our problem. For the
22413 second block of instructions, the secondary opcode nybble
22414 (bits 8..11) is present, and bit 23 is zero, even if this is
22415 a PC-relative operation. */
22416 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22418 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22420 if ((newval
& 0xf0000000) == 0xe0000000)
22422 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22424 newval
|= (1 << 23);
22427 if (value
% 4 != 0)
22429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22430 _("offset not a multiple of 4"));
22436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22437 _("offset out of range"));
22442 else if ((newval
& 0x000f0000) == 0x000f0000)
22444 /* PC-relative, 12-bit offset. */
22446 newval
|= (1 << 23);
22451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22452 _("offset out of range"));
22457 else if ((newval
& 0x00000100) == 0x00000100)
22459 /* Writeback: 8-bit, +/- offset. */
22461 newval
|= (1 << 9);
22466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22467 _("offset out of range"));
22472 else if ((newval
& 0x00000f00) == 0x00000e00)
22474 /* T-instruction: positive 8-bit offset. */
22475 if (value
< 0 || value
> 0xff)
22477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22478 _("offset out of range"));
22486 /* Positive 12-bit or negative 8-bit offset. */
22490 newval
|= (1 << 23);
22500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22501 _("offset out of range"));
22508 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22509 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22512 case BFD_RELOC_ARM_SHIFT_IMM
:
22513 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22514 if (((unsigned long) value
) > 32
22516 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22519 _("shift expression is too large"));
22524 /* Shifts of zero must be done as lsl. */
22526 else if (value
== 32)
22528 newval
&= 0xfffff07f;
22529 newval
|= (value
& 0x1f) << 7;
22530 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22533 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22534 case BFD_RELOC_ARM_T32_ADD_IMM
:
22535 case BFD_RELOC_ARM_T32_IMM12
:
22536 case BFD_RELOC_ARM_T32_ADD_PC12
:
22537 /* We claim that this fixup has been processed here,
22538 even if in fact we generate an error because we do
22539 not have a reloc for it, so tc_gen_reloc will reject it. */
22543 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22546 _("undefined symbol %s used as an immediate value"),
22547 S_GET_NAME (fixP
->fx_addsy
));
22551 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22553 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22556 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22557 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22559 newimm
= encode_thumb32_immediate (value
);
22560 if (newimm
== (unsigned int) FAIL
)
22561 newimm
= thumb32_negate_data_op (&newval
, value
);
22563 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22564 && newimm
== (unsigned int) FAIL
)
22566 /* Turn add/sum into addw/subw. */
22567 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22568 newval
= (newval
& 0xfeffffff) | 0x02000000;
22569 /* No flat 12-bit imm encoding for addsw/subsw. */
22570 if ((newval
& 0x00100000) == 0)
22572 /* 12 bit immediate for addw/subw. */
22576 newval
^= 0x00a00000;
22579 newimm
= (unsigned int) FAIL
;
22585 if (newimm
== (unsigned int)FAIL
)
22587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22588 _("invalid constant (%lx) after fixup"),
22589 (unsigned long) value
);
22593 newval
|= (newimm
& 0x800) << 15;
22594 newval
|= (newimm
& 0x700) << 4;
22595 newval
|= (newimm
& 0x0ff);
22597 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22598 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22601 case BFD_RELOC_ARM_SMC
:
22602 if (((unsigned long) value
) > 0xffff)
22603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22604 _("invalid smc expression"));
22605 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22606 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22607 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22610 case BFD_RELOC_ARM_HVC
:
22611 if (((unsigned long) value
) > 0xffff)
22612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22613 _("invalid hvc expression"));
22614 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22615 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22616 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22619 case BFD_RELOC_ARM_SWI
:
22620 if (fixP
->tc_fix_data
!= 0)
22622 if (((unsigned long) value
) > 0xff)
22623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22624 _("invalid swi expression"));
22625 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22627 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22631 if (((unsigned long) value
) > 0x00ffffff)
22632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22633 _("invalid swi expression"));
22634 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22636 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22640 case BFD_RELOC_ARM_MULTI
:
22641 if (((unsigned long) value
) > 0xffff)
22642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22643 _("invalid expression in load/store multiple"));
22644 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22645 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22649 case BFD_RELOC_ARM_PCREL_CALL
:
22651 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22653 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22654 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22655 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22656 /* Flip the bl to blx. This is a simple flip
22657 bit here because we generate PCREL_CALL for
22658 unconditional bls. */
22660 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22661 newval
= newval
| 0x10000000;
22662 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22668 goto arm_branch_common
;
22670 case BFD_RELOC_ARM_PCREL_JUMP
:
22671 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22673 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22674 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22675 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22677 /* This would map to a bl<cond>, b<cond>,
22678 b<always> to a Thumb function. We
22679 need to force a relocation for this particular
22681 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22685 case BFD_RELOC_ARM_PLT32
:
22687 case BFD_RELOC_ARM_PCREL_BRANCH
:
22689 goto arm_branch_common
;
22691 case BFD_RELOC_ARM_PCREL_BLX
:
22694 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22696 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22697 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22698 && ARM_IS_FUNC (fixP
->fx_addsy
))
22700 /* Flip the blx to a bl and warn. */
22701 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22702 newval
= 0xeb000000;
22703 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22704 _("blx to '%s' an ARM ISA state function changed to bl"),
22706 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22712 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22713 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22717 /* We are going to store value (shifted right by two) in the
22718 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22719 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22720 also be be clear. */
22722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22723 _("misaligned branch destination"));
22724 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22725 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22728 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22730 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22731 newval
|= (value
>> 2) & 0x00ffffff;
22732 /* Set the H bit on BLX instructions. */
22736 newval
|= 0x01000000;
22738 newval
&= ~0x01000000;
22740 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22744 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22745 /* CBZ can only branch forward. */
22747 /* Attempts to use CBZ to branch to the next instruction
22748 (which, strictly speaking, are prohibited) will be turned into
22751 FIXME: It may be better to remove the instruction completely and
22752 perform relaxation. */
22755 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22756 newval
= 0xbf00; /* NOP encoding T1 */
22757 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22764 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22766 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22767 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22768 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22773 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22774 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22777 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22779 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22780 newval
|= (value
& 0x1ff) >> 1;
22781 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22785 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22786 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22789 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22791 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22792 newval
|= (value
& 0xfff) >> 1;
22793 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22797 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22799 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22800 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22801 && ARM_IS_FUNC (fixP
->fx_addsy
)
22802 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22804 /* Force a relocation for a branch 20 bits wide. */
22807 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22809 _("conditional branch out of range"));
22811 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22814 addressT S
, J1
, J2
, lo
, hi
;
22816 S
= (value
& 0x00100000) >> 20;
22817 J2
= (value
& 0x00080000) >> 19;
22818 J1
= (value
& 0x00040000) >> 18;
22819 hi
= (value
& 0x0003f000) >> 12;
22820 lo
= (value
& 0x00000ffe) >> 1;
22822 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22823 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22824 newval
|= (S
<< 10) | hi
;
22825 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22826 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22827 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22831 case BFD_RELOC_THUMB_PCREL_BLX
:
22832 /* If there is a blx from a thumb state function to
22833 another thumb function flip this to a bl and warn
22837 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22838 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22839 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22841 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22842 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22843 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22845 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22846 newval
= newval
| 0x1000;
22847 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22848 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22853 goto thumb_bl_common
;
22855 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22856 /* A bl from Thumb state ISA to an internal ARM state function
22857 is converted to a blx. */
22859 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22860 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22861 && ARM_IS_FUNC (fixP
->fx_addsy
)
22862 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22864 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22865 newval
= newval
& ~0x1000;
22866 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22867 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22873 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22874 /* For a BLX instruction, make sure that the relocation is rounded up
22875 to a word boundary. This follows the semantics of the instruction
22876 which specifies that bit 1 of the target address will come from bit
22877 1 of the base address. */
22878 value
= (value
+ 3) & ~ 3;
22881 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22882 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22883 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22886 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22888 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22890 else if ((value
& ~0x1ffffff)
22891 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22893 _("Thumb2 branch out of range"));
22896 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22897 encode_thumb2_b_bl_offset (buf
, value
);
22901 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22902 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22905 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22906 encode_thumb2_b_bl_offset (buf
, value
);
22911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22917 md_number_to_chars (buf
, value
, 2);
22921 case BFD_RELOC_ARM_TLS_CALL
:
22922 case BFD_RELOC_ARM_THM_TLS_CALL
:
22923 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22924 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22925 case BFD_RELOC_ARM_TLS_GOTDESC
:
22926 case BFD_RELOC_ARM_TLS_GD32
:
22927 case BFD_RELOC_ARM_TLS_LE32
:
22928 case BFD_RELOC_ARM_TLS_IE32
:
22929 case BFD_RELOC_ARM_TLS_LDM32
:
22930 case BFD_RELOC_ARM_TLS_LDO32
:
22931 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22934 case BFD_RELOC_ARM_GOT32
:
22935 case BFD_RELOC_ARM_GOTOFF
:
22938 case BFD_RELOC_ARM_GOT_PREL
:
22939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22940 md_number_to_chars (buf
, value
, 4);
22943 case BFD_RELOC_ARM_TARGET2
:
22944 /* TARGET2 is not partial-inplace, so we need to write the
22945 addend here for REL targets, because it won't be written out
22946 during reloc processing later. */
22947 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22948 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22952 case BFD_RELOC_RVA
:
22954 case BFD_RELOC_ARM_TARGET1
:
22955 case BFD_RELOC_ARM_ROSEGREL32
:
22956 case BFD_RELOC_ARM_SBREL32
:
22957 case BFD_RELOC_32_PCREL
:
22959 case BFD_RELOC_32_SECREL
:
22961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22963 /* For WinCE we only do this for pcrel fixups. */
22964 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22966 md_number_to_chars (buf
, value
, 4);
22970 case BFD_RELOC_ARM_PREL31
:
22971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22973 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22974 if ((value
^ (value
>> 1)) & 0x40000000)
22976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22977 _("rel31 relocation overflow"));
22979 newval
|= value
& 0x7fffffff;
22980 md_number_to_chars (buf
, newval
, 4);
22985 case BFD_RELOC_ARM_CP_OFF_IMM
:
22986 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22987 if (value
< -1023 || value
> 1023 || (value
& 3))
22988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22989 _("co-processor offset out of range"));
22994 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22995 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22996 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22998 newval
= get_thumb32_insn (buf
);
23000 newval
&= 0xffffff00;
23003 newval
&= 0xff7fff00;
23004 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23006 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23007 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23008 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23010 put_thumb32_insn (buf
, newval
);
23013 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23014 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23015 if (value
< -255 || value
> 255)
23016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23017 _("co-processor offset out of range"));
23019 goto cp_off_common
;
23021 case BFD_RELOC_ARM_THUMB_OFFSET
:
23022 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23023 /* Exactly what ranges, and where the offset is inserted depends
23024 on the type of instruction, we can establish this from the
23026 switch (newval
>> 12)
23028 case 4: /* PC load. */
23029 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23030 forced to zero for these loads; md_pcrel_from has already
23031 compensated for this. */
23033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23034 _("invalid offset, target not word aligned (0x%08lX)"),
23035 (((unsigned long) fixP
->fx_frag
->fr_address
23036 + (unsigned long) fixP
->fx_where
) & ~3)
23037 + (unsigned long) value
);
23039 if (value
& ~0x3fc)
23040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23041 _("invalid offset, value too big (0x%08lX)"),
23044 newval
|= value
>> 2;
23047 case 9: /* SP load/store. */
23048 if (value
& ~0x3fc)
23049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23050 _("invalid offset, value too big (0x%08lX)"),
23052 newval
|= value
>> 2;
23055 case 6: /* Word load/store. */
23057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23058 _("invalid offset, value too big (0x%08lX)"),
23060 newval
|= value
<< 4; /* 6 - 2. */
23063 case 7: /* Byte load/store. */
23065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23066 _("invalid offset, value too big (0x%08lX)"),
23068 newval
|= value
<< 6;
23071 case 8: /* Halfword load/store. */
23073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23074 _("invalid offset, value too big (0x%08lX)"),
23076 newval
|= value
<< 5; /* 6 - 1. */
23080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23081 "Unable to process relocation for thumb opcode: %lx",
23082 (unsigned long) newval
);
23085 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23088 case BFD_RELOC_ARM_THUMB_ADD
:
23089 /* This is a complicated relocation, since we use it for all of
23090 the following immediate relocations:
23094 9bit ADD/SUB SP word-aligned
23095 10bit ADD PC/SP word-aligned
23097 The type of instruction being processed is encoded in the
23104 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23106 int rd
= (newval
>> 4) & 0xf;
23107 int rs
= newval
& 0xf;
23108 int subtract
= !!(newval
& 0x8000);
23110 /* Check for HI regs, only very restricted cases allowed:
23111 Adjusting SP, and using PC or SP to get an address. */
23112 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23113 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23115 _("invalid Hi register with immediate"));
23117 /* If value is negative, choose the opposite instruction. */
23121 subtract
= !subtract
;
23123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23124 _("immediate value out of range"));
23129 if (value
& ~0x1fc)
23130 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23131 _("invalid immediate for stack address calculation"));
23132 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23133 newval
|= value
>> 2;
23135 else if (rs
== REG_PC
|| rs
== REG_SP
)
23137 if (subtract
|| value
& ~0x3fc)
23138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23139 _("invalid immediate for address calculation (value = 0x%08lX)"),
23140 (unsigned long) value
);
23141 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23143 newval
|= value
>> 2;
23148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23149 _("immediate value out of range"));
23150 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23151 newval
|= (rd
<< 8) | value
;
23156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23157 _("immediate value out of range"));
23158 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23159 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23162 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23165 case BFD_RELOC_ARM_THUMB_IMM
:
23166 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23167 if (value
< 0 || value
> 255)
23168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23169 _("invalid immediate: %ld is out of range"),
23172 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23175 case BFD_RELOC_ARM_THUMB_SHIFT
:
23176 /* 5bit shift value (0..32). LSL cannot take 32. */
23177 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23178 temp
= newval
& 0xf800;
23179 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23181 _("invalid shift value: %ld"), (long) value
);
23182 /* Shifts of zero must be encoded as LSL. */
23184 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23185 /* Shifts of 32 are encoded as zero. */
23186 else if (value
== 32)
23188 newval
|= value
<< 6;
23189 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23192 case BFD_RELOC_VTABLE_INHERIT
:
23193 case BFD_RELOC_VTABLE_ENTRY
:
23197 case BFD_RELOC_ARM_MOVW
:
23198 case BFD_RELOC_ARM_MOVT
:
23199 case BFD_RELOC_ARM_THUMB_MOVW
:
23200 case BFD_RELOC_ARM_THUMB_MOVT
:
23201 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23203 /* REL format relocations are limited to a 16-bit addend. */
23204 if (!fixP
->fx_done
)
23206 if (value
< -0x8000 || value
> 0x7fff)
23207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23208 _("offset out of range"));
23210 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23211 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23216 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23217 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23219 newval
= get_thumb32_insn (buf
);
23220 newval
&= 0xfbf08f00;
23221 newval
|= (value
& 0xf000) << 4;
23222 newval
|= (value
& 0x0800) << 15;
23223 newval
|= (value
& 0x0700) << 4;
23224 newval
|= (value
& 0x00ff);
23225 put_thumb32_insn (buf
, newval
);
23229 newval
= md_chars_to_number (buf
, 4);
23230 newval
&= 0xfff0f000;
23231 newval
|= value
& 0x0fff;
23232 newval
|= (value
& 0xf000) << 4;
23233 md_number_to_chars (buf
, newval
, 4);
23238 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23239 case BFD_RELOC_ARM_ALU_PC_G0
:
23240 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23241 case BFD_RELOC_ARM_ALU_PC_G1
:
23242 case BFD_RELOC_ARM_ALU_PC_G2
:
23243 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23244 case BFD_RELOC_ARM_ALU_SB_G0
:
23245 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23246 case BFD_RELOC_ARM_ALU_SB_G1
:
23247 case BFD_RELOC_ARM_ALU_SB_G2
:
23248 gas_assert (!fixP
->fx_done
);
23249 if (!seg
->use_rela_p
)
23252 bfd_vma encoded_addend
;
23253 bfd_vma addend_abs
= abs (value
);
23255 /* Check that the absolute value of the addend can be
23256 expressed as an 8-bit constant plus a rotation. */
23257 encoded_addend
= encode_arm_immediate (addend_abs
);
23258 if (encoded_addend
== (unsigned int) FAIL
)
23259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23260 _("the offset 0x%08lX is not representable"),
23261 (unsigned long) addend_abs
);
23263 /* Extract the instruction. */
23264 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23266 /* If the addend is positive, use an ADD instruction.
23267 Otherwise use a SUB. Take care not to destroy the S bit. */
23268 insn
&= 0xff1fffff;
23274 /* Place the encoded addend into the first 12 bits of the
23276 insn
&= 0xfffff000;
23277 insn
|= encoded_addend
;
23279 /* Update the instruction. */
23280 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23284 case BFD_RELOC_ARM_LDR_PC_G0
:
23285 case BFD_RELOC_ARM_LDR_PC_G1
:
23286 case BFD_RELOC_ARM_LDR_PC_G2
:
23287 case BFD_RELOC_ARM_LDR_SB_G0
:
23288 case BFD_RELOC_ARM_LDR_SB_G1
:
23289 case BFD_RELOC_ARM_LDR_SB_G2
:
23290 gas_assert (!fixP
->fx_done
);
23291 if (!seg
->use_rela_p
)
23294 bfd_vma addend_abs
= abs (value
);
23296 /* Check that the absolute value of the addend can be
23297 encoded in 12 bits. */
23298 if (addend_abs
>= 0x1000)
23299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23300 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23301 (unsigned long) addend_abs
);
23303 /* Extract the instruction. */
23304 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23306 /* If the addend is negative, clear bit 23 of the instruction.
23307 Otherwise set it. */
23309 insn
&= ~(1 << 23);
23313 /* Place the absolute value of the addend into the first 12 bits
23314 of the instruction. */
23315 insn
&= 0xfffff000;
23316 insn
|= addend_abs
;
23318 /* Update the instruction. */
23319 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23323 case BFD_RELOC_ARM_LDRS_PC_G0
:
23324 case BFD_RELOC_ARM_LDRS_PC_G1
:
23325 case BFD_RELOC_ARM_LDRS_PC_G2
:
23326 case BFD_RELOC_ARM_LDRS_SB_G0
:
23327 case BFD_RELOC_ARM_LDRS_SB_G1
:
23328 case BFD_RELOC_ARM_LDRS_SB_G2
:
23329 gas_assert (!fixP
->fx_done
);
23330 if (!seg
->use_rela_p
)
23333 bfd_vma addend_abs
= abs (value
);
23335 /* Check that the absolute value of the addend can be
23336 encoded in 8 bits. */
23337 if (addend_abs
>= 0x100)
23338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23339 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23340 (unsigned long) addend_abs
);
23342 /* Extract the instruction. */
23343 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23345 /* If the addend is negative, clear bit 23 of the instruction.
23346 Otherwise set it. */
23348 insn
&= ~(1 << 23);
23352 /* Place the first four bits of the absolute value of the addend
23353 into the first 4 bits of the instruction, and the remaining
23354 four into bits 8 .. 11. */
23355 insn
&= 0xfffff0f0;
23356 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23358 /* Update the instruction. */
23359 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23363 case BFD_RELOC_ARM_LDC_PC_G0
:
23364 case BFD_RELOC_ARM_LDC_PC_G1
:
23365 case BFD_RELOC_ARM_LDC_PC_G2
:
23366 case BFD_RELOC_ARM_LDC_SB_G0
:
23367 case BFD_RELOC_ARM_LDC_SB_G1
:
23368 case BFD_RELOC_ARM_LDC_SB_G2
:
23369 gas_assert (!fixP
->fx_done
);
23370 if (!seg
->use_rela_p
)
23373 bfd_vma addend_abs
= abs (value
);
23375 /* Check that the absolute value of the addend is a multiple of
23376 four and, when divided by four, fits in 8 bits. */
23377 if (addend_abs
& 0x3)
23378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23379 _("bad offset 0x%08lX (must be word-aligned)"),
23380 (unsigned long) addend_abs
);
23382 if ((addend_abs
>> 2) > 0xff)
23383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23384 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23385 (unsigned long) addend_abs
);
23387 /* Extract the instruction. */
23388 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23390 /* If the addend is negative, clear bit 23 of the instruction.
23391 Otherwise set it. */
23393 insn
&= ~(1 << 23);
23397 /* Place the addend (divided by four) into the first eight
23398 bits of the instruction. */
23399 insn
&= 0xfffffff0;
23400 insn
|= addend_abs
>> 2;
23402 /* Update the instruction. */
23403 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23407 case BFD_RELOC_ARM_V4BX
:
23408 /* This will need to go in the object file. */
23412 case BFD_RELOC_UNUSED
:
23414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23415 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23419 /* Translate internal representation of relocation info to BFD target
23423 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23426 bfd_reloc_code_real_type code
;
23428 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23430 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23431 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23432 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23434 if (fixp
->fx_pcrel
)
23436 if (section
->use_rela_p
)
23437 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23439 fixp
->fx_offset
= reloc
->address
;
23441 reloc
->addend
= fixp
->fx_offset
;
23443 switch (fixp
->fx_r_type
)
23446 if (fixp
->fx_pcrel
)
23448 code
= BFD_RELOC_8_PCREL
;
23453 if (fixp
->fx_pcrel
)
23455 code
= BFD_RELOC_16_PCREL
;
23460 if (fixp
->fx_pcrel
)
23462 code
= BFD_RELOC_32_PCREL
;
23466 case BFD_RELOC_ARM_MOVW
:
23467 if (fixp
->fx_pcrel
)
23469 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23473 case BFD_RELOC_ARM_MOVT
:
23474 if (fixp
->fx_pcrel
)
23476 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23480 case BFD_RELOC_ARM_THUMB_MOVW
:
23481 if (fixp
->fx_pcrel
)
23483 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23487 case BFD_RELOC_ARM_THUMB_MOVT
:
23488 if (fixp
->fx_pcrel
)
23490 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23494 case BFD_RELOC_NONE
:
23495 case BFD_RELOC_ARM_PCREL_BRANCH
:
23496 case BFD_RELOC_ARM_PCREL_BLX
:
23497 case BFD_RELOC_RVA
:
23498 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23499 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23500 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23501 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23502 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23503 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23504 case BFD_RELOC_VTABLE_ENTRY
:
23505 case BFD_RELOC_VTABLE_INHERIT
:
23507 case BFD_RELOC_32_SECREL
:
23509 code
= fixp
->fx_r_type
;
23512 case BFD_RELOC_THUMB_PCREL_BLX
:
23514 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23515 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23518 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23521 case BFD_RELOC_ARM_LITERAL
:
23522 case BFD_RELOC_ARM_HWLITERAL
:
23523 /* If this is called then the a literal has
23524 been referenced across a section boundary. */
23525 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23526 _("literal referenced across section boundary"));
23530 case BFD_RELOC_ARM_TLS_CALL
:
23531 case BFD_RELOC_ARM_THM_TLS_CALL
:
23532 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23533 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23534 case BFD_RELOC_ARM_GOT32
:
23535 case BFD_RELOC_ARM_GOTOFF
:
23536 case BFD_RELOC_ARM_GOT_PREL
:
23537 case BFD_RELOC_ARM_PLT32
:
23538 case BFD_RELOC_ARM_TARGET1
:
23539 case BFD_RELOC_ARM_ROSEGREL32
:
23540 case BFD_RELOC_ARM_SBREL32
:
23541 case BFD_RELOC_ARM_PREL31
:
23542 case BFD_RELOC_ARM_TARGET2
:
23543 case BFD_RELOC_ARM_TLS_LE32
:
23544 case BFD_RELOC_ARM_TLS_LDO32
:
23545 case BFD_RELOC_ARM_PCREL_CALL
:
23546 case BFD_RELOC_ARM_PCREL_JUMP
:
23547 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23548 case BFD_RELOC_ARM_ALU_PC_G0
:
23549 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23550 case BFD_RELOC_ARM_ALU_PC_G1
:
23551 case BFD_RELOC_ARM_ALU_PC_G2
:
23552 case BFD_RELOC_ARM_LDR_PC_G0
:
23553 case BFD_RELOC_ARM_LDR_PC_G1
:
23554 case BFD_RELOC_ARM_LDR_PC_G2
:
23555 case BFD_RELOC_ARM_LDRS_PC_G0
:
23556 case BFD_RELOC_ARM_LDRS_PC_G1
:
23557 case BFD_RELOC_ARM_LDRS_PC_G2
:
23558 case BFD_RELOC_ARM_LDC_PC_G0
:
23559 case BFD_RELOC_ARM_LDC_PC_G1
:
23560 case BFD_RELOC_ARM_LDC_PC_G2
:
23561 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23562 case BFD_RELOC_ARM_ALU_SB_G0
:
23563 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23564 case BFD_RELOC_ARM_ALU_SB_G1
:
23565 case BFD_RELOC_ARM_ALU_SB_G2
:
23566 case BFD_RELOC_ARM_LDR_SB_G0
:
23567 case BFD_RELOC_ARM_LDR_SB_G1
:
23568 case BFD_RELOC_ARM_LDR_SB_G2
:
23569 case BFD_RELOC_ARM_LDRS_SB_G0
:
23570 case BFD_RELOC_ARM_LDRS_SB_G1
:
23571 case BFD_RELOC_ARM_LDRS_SB_G2
:
23572 case BFD_RELOC_ARM_LDC_SB_G0
:
23573 case BFD_RELOC_ARM_LDC_SB_G1
:
23574 case BFD_RELOC_ARM_LDC_SB_G2
:
23575 case BFD_RELOC_ARM_V4BX
:
23576 code
= fixp
->fx_r_type
;
23579 case BFD_RELOC_ARM_TLS_GOTDESC
:
23580 case BFD_RELOC_ARM_TLS_GD32
:
23581 case BFD_RELOC_ARM_TLS_IE32
:
23582 case BFD_RELOC_ARM_TLS_LDM32
:
23583 /* BFD will include the symbol's address in the addend.
23584 But we don't want that, so subtract it out again here. */
23585 if (!S_IS_COMMON (fixp
->fx_addsy
))
23586 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23587 code
= fixp
->fx_r_type
;
23591 case BFD_RELOC_ARM_IMMEDIATE
:
23592 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23593 _("internal relocation (type: IMMEDIATE) not fixed up"));
23596 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23597 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23598 _("ADRL used for a symbol not defined in the same file"));
23601 case BFD_RELOC_ARM_OFFSET_IMM
:
23602 if (section
->use_rela_p
)
23604 code
= fixp
->fx_r_type
;
23608 if (fixp
->fx_addsy
!= NULL
23609 && !S_IS_DEFINED (fixp
->fx_addsy
)
23610 && S_IS_LOCAL (fixp
->fx_addsy
))
23612 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23613 _("undefined local label `%s'"),
23614 S_GET_NAME (fixp
->fx_addsy
));
23618 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23619 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23626 switch (fixp
->fx_r_type
)
23628 case BFD_RELOC_NONE
: type
= "NONE"; break;
23629 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23630 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23631 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23632 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23633 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23634 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23635 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23636 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23637 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23638 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23639 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23640 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23641 default: type
= _("<unknown>"); break;
23643 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23644 _("cannot represent %s relocation in this object file format"),
23651 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23653 && fixp
->fx_addsy
== GOT_symbol
)
23655 code
= BFD_RELOC_ARM_GOTPC
;
23656 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23660 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23662 if (reloc
->howto
== NULL
)
23664 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23665 _("cannot represent %s relocation in this object file format"),
23666 bfd_get_reloc_code_name (code
));
23670 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23671 vtable entry to be used in the relocation's section offset. */
23672 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23673 reloc
->address
= fixp
->fx_offset
;
23678 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23681 cons_fix_new_arm (fragS
* frag
,
23685 bfd_reloc_code_real_type reloc
)
23690 FIXME: @@ Should look at CPU word size. */
23694 reloc
= BFD_RELOC_8
;
23697 reloc
= BFD_RELOC_16
;
23701 reloc
= BFD_RELOC_32
;
23704 reloc
= BFD_RELOC_64
;
23709 if (exp
->X_op
== O_secrel
)
23711 exp
->X_op
= O_symbol
;
23712 reloc
= BFD_RELOC_32_SECREL
;
23716 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23719 #if defined (OBJ_COFF)
23721 arm_validate_fix (fixS
* fixP
)
23723 /* If the destination of the branch is a defined symbol which does not have
23724 the THUMB_FUNC attribute, then we must be calling a function which has
23725 the (interfacearm) attribute. We look for the Thumb entry point to that
23726 function and change the branch to refer to that function instead. */
23727 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23728 && fixP
->fx_addsy
!= NULL
23729 && S_IS_DEFINED (fixP
->fx_addsy
)
23730 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23732 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23739 arm_force_relocation (struct fix
* fixp
)
23741 #if defined (OBJ_COFF) && defined (TE_PE)
23742 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23746 /* In case we have a call or a branch to a function in ARM ISA mode from
23747 a thumb function or vice-versa force the relocation. These relocations
23748 are cleared off for some cores that might have blx and simple transformations
23752 switch (fixp
->fx_r_type
)
23754 case BFD_RELOC_ARM_PCREL_JUMP
:
23755 case BFD_RELOC_ARM_PCREL_CALL
:
23756 case BFD_RELOC_THUMB_PCREL_BLX
:
23757 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23761 case BFD_RELOC_ARM_PCREL_BLX
:
23762 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23763 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23764 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23765 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23774 /* Resolve these relocations even if the symbol is extern or weak.
23775 Technically this is probably wrong due to symbol preemption.
23776 In practice these relocations do not have enough range to be useful
23777 at dynamic link time, and some code (e.g. in the Linux kernel)
23778 expects these references to be resolved. */
23779 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23780 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23781 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23782 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23783 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23784 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23785 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23786 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23787 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23788 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23789 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23790 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23791 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23792 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23795 /* Always leave these relocations for the linker. */
23796 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23797 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23798 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23801 /* Always generate relocations against function symbols. */
23802 if (fixp
->fx_r_type
== BFD_RELOC_32
23804 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23807 return generic_force_reloc (fixp
);
23810 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23811 /* Relocations against function names must be left unadjusted,
23812 so that the linker can use this information to generate interworking
23813 stubs. The MIPS version of this function
23814 also prevents relocations that are mips-16 specific, but I do not
23815 know why it does this.
23818 There is one other problem that ought to be addressed here, but
23819 which currently is not: Taking the address of a label (rather
23820 than a function) and then later jumping to that address. Such
23821 addresses also ought to have their bottom bit set (assuming that
23822 they reside in Thumb code), but at the moment they will not. */
23825 arm_fix_adjustable (fixS
* fixP
)
23827 if (fixP
->fx_addsy
== NULL
)
23830 /* Preserve relocations against symbols with function type. */
23831 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23834 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23835 && fixP
->fx_subsy
== NULL
)
23838 /* We need the symbol name for the VTABLE entries. */
23839 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23840 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23843 /* Don't allow symbols to be discarded on GOT related relocs. */
23844 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23845 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23846 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23847 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23848 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23849 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23850 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23851 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23852 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23853 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23854 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23855 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23856 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23857 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23860 /* Similarly for group relocations. */
23861 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23862 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23863 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23866 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23867 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23868 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23869 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23870 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23871 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23872 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23873 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23874 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23879 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23884 elf32_arm_target_format (void)
23887 return (target_big_endian
23888 ? "elf32-bigarm-symbian"
23889 : "elf32-littlearm-symbian");
23890 #elif defined (TE_VXWORKS)
23891 return (target_big_endian
23892 ? "elf32-bigarm-vxworks"
23893 : "elf32-littlearm-vxworks");
23894 #elif defined (TE_NACL)
23895 return (target_big_endian
23896 ? "elf32-bigarm-nacl"
23897 : "elf32-littlearm-nacl");
23899 if (target_big_endian
)
23900 return "elf32-bigarm";
23902 return "elf32-littlearm";
23907 armelf_frob_symbol (symbolS
* symp
,
23910 elf_frob_symbol (symp
, puntp
);
23914 /* MD interface: Finalization. */
23919 literal_pool
* pool
;
23921 /* Ensure that all the IT blocks are properly closed. */
23922 check_it_blocks_finished ();
23924 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23926 /* Put it at the end of the relevant section. */
23927 subseg_set (pool
->section
, pool
->sub_section
);
23929 arm_elf_change_section ();
23936 /* Remove any excess mapping symbols generated for alignment frags in
23937 SEC. We may have created a mapping symbol before a zero byte
23938 alignment; remove it if there's a mapping symbol after the
23941 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23942 void *dummy ATTRIBUTE_UNUSED
)
23944 segment_info_type
*seginfo
= seg_info (sec
);
23947 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23950 for (fragp
= seginfo
->frchainP
->frch_root
;
23952 fragp
= fragp
->fr_next
)
23954 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23955 fragS
*next
= fragp
->fr_next
;
23957 /* Variable-sized frags have been converted to fixed size by
23958 this point. But if this was variable-sized to start with,
23959 there will be a fixed-size frag after it. So don't handle
23961 if (sym
== NULL
|| next
== NULL
)
23964 if (S_GET_VALUE (sym
) < next
->fr_address
)
23965 /* Not at the end of this frag. */
23967 know (S_GET_VALUE (sym
) == next
->fr_address
);
23971 if (next
->tc_frag_data
.first_map
!= NULL
)
23973 /* Next frag starts with a mapping symbol. Discard this
23975 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23979 if (next
->fr_next
== NULL
)
23981 /* This mapping symbol is at the end of the section. Discard
23983 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23984 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23988 /* As long as we have empty frags without any mapping symbols,
23990 /* If the next frag is non-empty and does not start with a
23991 mapping symbol, then this mapping symbol is required. */
23992 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23995 next
= next
->fr_next
;
23997 while (next
!= NULL
);
24002 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24006 arm_adjust_symtab (void)
24011 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24013 if (ARM_IS_THUMB (sym
))
24015 if (THUMB_IS_FUNC (sym
))
24017 /* Mark the symbol as a Thumb function. */
24018 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24019 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24020 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24022 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24023 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24025 as_bad (_("%s: unexpected function type: %d"),
24026 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24028 else switch (S_GET_STORAGE_CLASS (sym
))
24031 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24034 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24037 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24045 if (ARM_IS_INTERWORK (sym
))
24046 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24053 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24055 if (ARM_IS_THUMB (sym
))
24057 elf_symbol_type
* elf_sym
;
24059 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24060 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24062 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24063 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24065 /* If it's a .thumb_func, declare it as so,
24066 otherwise tag label as .code 16. */
24067 if (THUMB_IS_FUNC (sym
))
24068 elf_sym
->internal_elf_sym
.st_target_internal
24069 = ST_BRANCH_TO_THUMB
;
24070 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24071 elf_sym
->internal_elf_sym
.st_info
=
24072 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24077 /* Remove any overlapping mapping symbols generated by alignment frags. */
24078 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24079 /* Now do generic ELF adjustments. */
24080 elf_adjust_symtab ();
24084 /* MD interface: Initialization. */
24087 set_constant_flonums (void)
24091 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24092 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24096 /* Auto-select Thumb mode if it's the only available instruction set for the
24097 given architecture. */
24100 autoselect_thumb_from_cpu_variant (void)
24102 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24103 opcode_select (16);
24112 if ( (arm_ops_hsh
= hash_new ()) == NULL
24113 || (arm_cond_hsh
= hash_new ()) == NULL
24114 || (arm_shift_hsh
= hash_new ()) == NULL
24115 || (arm_psr_hsh
= hash_new ()) == NULL
24116 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24117 || (arm_reg_hsh
= hash_new ()) == NULL
24118 || (arm_reloc_hsh
= hash_new ()) == NULL
24119 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24120 as_fatal (_("virtual memory exhausted"));
24122 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24123 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24124 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24125 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24126 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24127 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24128 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24129 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24130 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24131 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24132 (void *) (v7m_psrs
+ i
));
24133 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24134 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24136 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24138 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24139 (void *) (barrier_opt_names
+ i
));
24141 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24143 struct reloc_entry
* entry
= reloc_names
+ i
;
24145 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24146 /* This makes encode_branch() use the EABI versions of this relocation. */
24147 entry
->reloc
= BFD_RELOC_UNUSED
;
24149 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24153 set_constant_flonums ();
24155 /* Set the cpu variant based on the command-line options. We prefer
24156 -mcpu= over -march= if both are set (as for GCC); and we prefer
24157 -mfpu= over any other way of setting the floating point unit.
24158 Use of legacy options with new options are faulted. */
24161 if (mcpu_cpu_opt
|| march_cpu_opt
)
24162 as_bad (_("use of old and new-style options to set CPU type"));
24164 mcpu_cpu_opt
= legacy_cpu
;
24166 else if (!mcpu_cpu_opt
)
24167 mcpu_cpu_opt
= march_cpu_opt
;
24172 as_bad (_("use of old and new-style options to set FPU type"));
24174 mfpu_opt
= legacy_fpu
;
24176 else if (!mfpu_opt
)
24178 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24179 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24180 /* Some environments specify a default FPU. If they don't, infer it
24181 from the processor. */
24183 mfpu_opt
= mcpu_fpu_opt
;
24185 mfpu_opt
= march_fpu_opt
;
24187 mfpu_opt
= &fpu_default
;
24193 if (mcpu_cpu_opt
!= NULL
)
24194 mfpu_opt
= &fpu_default
;
24195 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24196 mfpu_opt
= &fpu_arch_vfp_v2
;
24198 mfpu_opt
= &fpu_arch_fpa
;
24204 mcpu_cpu_opt
= &cpu_default
;
24205 selected_cpu
= cpu_default
;
24207 else if (no_cpu_selected ())
24208 selected_cpu
= cpu_default
;
24211 selected_cpu
= *mcpu_cpu_opt
;
24213 mcpu_cpu_opt
= &arm_arch_any
;
24216 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24218 autoselect_thumb_from_cpu_variant ();
24220 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24222 #if defined OBJ_COFF || defined OBJ_ELF
24224 unsigned int flags
= 0;
24226 #if defined OBJ_ELF
24227 flags
= meabi_flags
;
24229 switch (meabi_flags
)
24231 case EF_ARM_EABI_UNKNOWN
:
24233 /* Set the flags in the private structure. */
24234 if (uses_apcs_26
) flags
|= F_APCS26
;
24235 if (support_interwork
) flags
|= F_INTERWORK
;
24236 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24237 if (pic_code
) flags
|= F_PIC
;
24238 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24239 flags
|= F_SOFT_FLOAT
;
24241 switch (mfloat_abi_opt
)
24243 case ARM_FLOAT_ABI_SOFT
:
24244 case ARM_FLOAT_ABI_SOFTFP
:
24245 flags
|= F_SOFT_FLOAT
;
24248 case ARM_FLOAT_ABI_HARD
:
24249 if (flags
& F_SOFT_FLOAT
)
24250 as_bad (_("hard-float conflicts with specified fpu"));
24254 /* Using pure-endian doubles (even if soft-float). */
24255 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24256 flags
|= F_VFP_FLOAT
;
24258 #if defined OBJ_ELF
24259 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24260 flags
|= EF_ARM_MAVERICK_FLOAT
;
24263 case EF_ARM_EABI_VER4
:
24264 case EF_ARM_EABI_VER5
:
24265 /* No additional flags to set. */
24272 bfd_set_private_flags (stdoutput
, flags
);
24274 /* We have run out flags in the COFF header to encode the
24275 status of ATPCS support, so instead we create a dummy,
24276 empty, debug section called .arm.atpcs. */
24281 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24285 bfd_set_section_flags
24286 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24287 bfd_set_section_size (stdoutput
, sec
, 0);
24288 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24294 /* Record the CPU type as well. */
24295 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24296 mach
= bfd_mach_arm_iWMMXt2
;
24297 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24298 mach
= bfd_mach_arm_iWMMXt
;
24299 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24300 mach
= bfd_mach_arm_XScale
;
24301 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24302 mach
= bfd_mach_arm_ep9312
;
24303 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24304 mach
= bfd_mach_arm_5TE
;
24305 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24307 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24308 mach
= bfd_mach_arm_5T
;
24310 mach
= bfd_mach_arm_5
;
24312 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24314 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24315 mach
= bfd_mach_arm_4T
;
24317 mach
= bfd_mach_arm_4
;
24319 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24320 mach
= bfd_mach_arm_3M
;
24321 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24322 mach
= bfd_mach_arm_3
;
24323 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24324 mach
= bfd_mach_arm_2a
;
24325 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24326 mach
= bfd_mach_arm_2
;
24328 mach
= bfd_mach_arm_unknown
;
24330 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24333 /* Command line processing. */
24336 Invocation line includes a switch not recognized by the base assembler.
24337 See if it's a processor-specific option.
24339 This routine is somewhat complicated by the need for backwards
24340 compatibility (since older releases of gcc can't be changed).
24341 The new options try to make the interface as compatible as
24344 New options (supported) are:
24346 -mcpu=<cpu name> Assemble for selected processor
24347 -march=<architecture name> Assemble for selected architecture
24348 -mfpu=<fpu architecture> Assemble for selected FPU.
24349 -EB/-mbig-endian Big-endian
24350 -EL/-mlittle-endian Little-endian
24351 -k Generate PIC code
24352 -mthumb Start in Thumb mode
24353 -mthumb-interwork Code supports ARM/Thumb interworking
24355 -m[no-]warn-deprecated Warn about deprecated features
24356 -m[no-]warn-syms Warn when symbols match instructions
24358 For now we will also provide support for:
24360 -mapcs-32 32-bit Program counter
24361 -mapcs-26 26-bit Program counter
24362 -macps-float Floats passed in FP registers
24363 -mapcs-reentrant Reentrant code
24365 (sometime these will probably be replaced with -mapcs=<list of options>
24366 and -matpcs=<list of options>)
24368 The remaining options are only supported for back-wards compatibility.
24369 Cpu variants, the arm part is optional:
24370 -m[arm]1 Currently not supported.
24371 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24372 -m[arm]3 Arm 3 processor
24373 -m[arm]6[xx], Arm 6 processors
24374 -m[arm]7[xx][t][[d]m] Arm 7 processors
24375 -m[arm]8[10] Arm 8 processors
24376 -m[arm]9[20][tdmi] Arm 9 processors
24377 -mstrongarm[110[0]] StrongARM processors
24378 -mxscale XScale processors
24379 -m[arm]v[2345[t[e]]] Arm architectures
24380 -mall All (except the ARM1)
24382 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24383 -mfpe-old (No float load/store multiples)
24384 -mvfpxd VFP Single precision
24386 -mno-fpu Disable all floating point instructions
24388 The following CPU names are recognized:
24389 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24390 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24391 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24392 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24393 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24394 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24395 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24399 const char * md_shortopts
= "m:k";
24401 #ifdef ARM_BI_ENDIAN
24402 #define OPTION_EB (OPTION_MD_BASE + 0)
24403 #define OPTION_EL (OPTION_MD_BASE + 1)
24405 #if TARGET_BYTES_BIG_ENDIAN
24406 #define OPTION_EB (OPTION_MD_BASE + 0)
24408 #define OPTION_EL (OPTION_MD_BASE + 1)
24411 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24413 struct option md_longopts
[] =
24416 {"EB", no_argument
, NULL
, OPTION_EB
},
24419 {"EL", no_argument
, NULL
, OPTION_EL
},
24421 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24422 {NULL
, no_argument
, NULL
, 0}
24426 size_t md_longopts_size
= sizeof (md_longopts
);
24428 struct arm_option_table
24430 char *option
; /* Option name to match. */
24431 char *help
; /* Help information. */
24432 int *var
; /* Variable to change. */
24433 int value
; /* What to change it to. */
24434 char *deprecated
; /* If non-null, print this message. */
24437 struct arm_option_table arm_opts
[] =
24439 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24440 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24441 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24442 &support_interwork
, 1, NULL
},
24443 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24444 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24445 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24447 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24448 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24449 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24450 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24453 /* These are recognized by the assembler, but have no affect on code. */
24454 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24455 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24457 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24458 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24459 &warn_on_deprecated
, 0, NULL
},
24460 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24461 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24462 {NULL
, NULL
, NULL
, 0, NULL
}
24465 struct arm_legacy_option_table
24467 char *option
; /* Option name to match. */
24468 const arm_feature_set
**var
; /* Variable to change. */
24469 const arm_feature_set value
; /* What to change it to. */
24470 char *deprecated
; /* If non-null, print this message. */
24473 const struct arm_legacy_option_table arm_legacy_opts
[] =
24475 /* DON'T add any new processors to this list -- we want the whole list
24476 to go away... Add them to the processors table instead. */
24477 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24478 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24479 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24480 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24481 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24482 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24483 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24484 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24485 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24486 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24487 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24488 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24489 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24490 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24491 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24492 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24493 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24494 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24495 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24496 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24497 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24498 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24499 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24500 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24501 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24502 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24503 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24504 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24505 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24506 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24507 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24508 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24509 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24510 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24511 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24512 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24513 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24514 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24515 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24516 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24517 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24518 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24519 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24520 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24521 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24522 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24523 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24524 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24525 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24526 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24527 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24528 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24529 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24530 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24531 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24532 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24533 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24534 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24535 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24536 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24537 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24538 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24539 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24540 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24541 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24542 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24543 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24544 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24545 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24546 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24547 N_("use -mcpu=strongarm110")},
24548 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24549 N_("use -mcpu=strongarm1100")},
24550 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24551 N_("use -mcpu=strongarm1110")},
24552 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24553 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24554 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24556 /* Architecture variants -- don't add any more to this list either. */
24557 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24558 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24559 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24560 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24561 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24562 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24563 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24564 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24565 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24566 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24567 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24568 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24569 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24570 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24571 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24572 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24573 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24574 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24576 /* Floating point variants -- don't add any more to this list either. */
24577 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24578 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24579 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24580 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24581 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24583 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24586 struct arm_cpu_option_table
24590 const arm_feature_set value
;
24591 /* For some CPUs we assume an FPU unless the user explicitly sets
24593 const arm_feature_set default_fpu
;
24594 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24596 const char *canonical_name
;
24599 /* This list should, at a minimum, contain all the cpu names
24600 recognized by GCC. */
24601 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24602 static const struct arm_cpu_option_table arm_cpus
[] =
24604 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24605 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24606 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24607 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24608 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24609 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24610 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24611 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24612 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24613 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24614 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24615 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24616 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24617 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24618 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24619 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24620 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24621 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24622 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24623 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24624 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24625 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24626 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24627 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24628 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24629 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24630 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24631 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24632 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24633 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24634 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24635 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24636 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24637 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24638 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24639 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24640 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24641 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24642 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24643 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24644 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24645 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24646 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24647 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24648 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24649 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24650 /* For V5 or later processors we default to using VFP; but the user
24651 should really set the FPU type explicitly. */
24652 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24653 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24654 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24655 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24656 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24657 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24658 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24659 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24660 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24661 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24662 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24663 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24664 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24665 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24666 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24667 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24668 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24669 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24670 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24671 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24673 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24674 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24675 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24676 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24677 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24678 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24679 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24680 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24681 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24683 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24684 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24685 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24686 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24687 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24688 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24689 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24690 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24691 FPU_NONE
, "Cortex-A5"),
24692 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24694 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24695 ARM_FEATURE_COPROC (FPU_VFP_V3
24696 | FPU_NEON_EXT_V1
),
24698 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24699 ARM_FEATURE_COPROC (FPU_VFP_V3
24700 | FPU_NEON_EXT_V1
),
24702 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24704 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24706 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24708 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24710 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24712 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24714 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24715 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24717 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24718 FPU_NONE
, "Cortex-R5"),
24719 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24720 FPU_ARCH_VFP_V3D16
,
24722 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24723 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24724 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24725 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24726 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24727 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24728 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24731 /* ??? XSCALE is really an architecture. */
24732 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24733 /* ??? iwmmxt is not a processor. */
24734 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24735 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24736 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24738 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24739 FPU_ARCH_MAVERICK
, "ARM920T"),
24740 /* Marvell processors. */
24741 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24743 FPU_ARCH_VFP_V3D16
, NULL
),
24744 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24746 FPU_ARCH_NEON_VFP_V4
, NULL
),
24747 /* APM X-Gene family. */
24748 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24750 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24753 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24757 struct arm_arch_option_table
24761 const arm_feature_set value
;
24762 const arm_feature_set default_fpu
;
24765 /* This list should, at a minimum, contain all the architecture names
24766 recognized by GCC. */
24767 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24768 static const struct arm_arch_option_table arm_archs
[] =
24770 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24771 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24772 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24773 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24774 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24775 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24776 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24777 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24778 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24779 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24780 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24781 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24782 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24783 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24784 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24785 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24786 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24787 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24788 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24789 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24790 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24791 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24792 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24793 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24794 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24795 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24796 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24797 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24798 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24799 /* The official spelling of the ARMv7 profile variants is the dashed form.
24800 Accept the non-dashed form for compatibility with old toolchains. */
24801 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24802 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24803 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24804 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24805 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24806 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24807 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24808 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24809 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24810 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24811 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24812 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24813 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24814 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24816 #undef ARM_ARCH_OPT
24818 /* ISA extensions in the co-processor and main instruction set space. */
24819 struct arm_option_extension_value_table
24823 const arm_feature_set merge_value
;
24824 const arm_feature_set clear_value
;
24825 const arm_feature_set allowed_archs
;
24828 /* The following table must be in alphabetical order with a NULL last entry.
24830 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24831 static const struct arm_option_extension_value_table arm_extensions
[] =
24833 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24834 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24835 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24836 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24837 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24838 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24839 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24840 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24841 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24842 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24843 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24844 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24845 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24846 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24847 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24848 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24849 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24850 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24851 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24852 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24853 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24854 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24855 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24856 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24857 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24858 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24859 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24860 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24861 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24862 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24863 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24864 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24866 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24867 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24868 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24869 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24870 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24871 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24872 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24873 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24877 /* ISA floating-point and Advanced SIMD extensions. */
24878 struct arm_option_fpu_value_table
24881 const arm_feature_set value
;
24884 /* This list should, at a minimum, contain all the fpu names
24885 recognized by GCC. */
24886 static const struct arm_option_fpu_value_table arm_fpus
[] =
24888 {"softfpa", FPU_NONE
},
24889 {"fpe", FPU_ARCH_FPE
},
24890 {"fpe2", FPU_ARCH_FPE
},
24891 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24892 {"fpa", FPU_ARCH_FPA
},
24893 {"fpa10", FPU_ARCH_FPA
},
24894 {"fpa11", FPU_ARCH_FPA
},
24895 {"arm7500fe", FPU_ARCH_FPA
},
24896 {"softvfp", FPU_ARCH_VFP
},
24897 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24898 {"vfp", FPU_ARCH_VFP_V2
},
24899 {"vfp9", FPU_ARCH_VFP_V2
},
24900 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24901 {"vfp10", FPU_ARCH_VFP_V2
},
24902 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24903 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24904 {"vfpv2", FPU_ARCH_VFP_V2
},
24905 {"vfpv3", FPU_ARCH_VFP_V3
},
24906 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24907 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24908 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24909 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24910 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24911 {"arm1020t", FPU_ARCH_VFP_V1
},
24912 {"arm1020e", FPU_ARCH_VFP_V2
},
24913 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24914 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24915 {"maverick", FPU_ARCH_MAVERICK
},
24916 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24917 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24918 {"vfpv4", FPU_ARCH_VFP_V4
},
24919 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24920 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24921 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24922 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24923 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24924 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24925 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24926 {"crypto-neon-fp-armv8",
24927 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24928 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24929 {NULL
, ARM_ARCH_NONE
}
24932 struct arm_option_value_table
24938 static const struct arm_option_value_table arm_float_abis
[] =
24940 {"hard", ARM_FLOAT_ABI_HARD
},
24941 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24942 {"soft", ARM_FLOAT_ABI_SOFT
},
24947 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24948 static const struct arm_option_value_table arm_eabis
[] =
24950 {"gnu", EF_ARM_EABI_UNKNOWN
},
24951 {"4", EF_ARM_EABI_VER4
},
24952 {"5", EF_ARM_EABI_VER5
},
24957 struct arm_long_option_table
24959 char * option
; /* Substring to match. */
24960 char * help
; /* Help information. */
24961 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24962 char * deprecated
; /* If non-null, print this message. */
24966 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24968 arm_feature_set
*ext_set
= (arm_feature_set
*)
24969 xmalloc (sizeof (arm_feature_set
));
24971 /* We insist on extensions being specified in alphabetical order, and with
24972 extensions being added before being removed. We achieve this by having
24973 the global ARM_EXTENSIONS table in alphabetical order, and using the
24974 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24975 or removing it (0) and only allowing it to change in the order
24977 const struct arm_option_extension_value_table
* opt
= NULL
;
24978 int adding_value
= -1;
24980 /* Copy the feature set, so that we can modify it. */
24981 *ext_set
= **opt_p
;
24984 while (str
!= NULL
&& *str
!= 0)
24991 as_bad (_("invalid architectural extension"));
24996 ext
= strchr (str
, '+');
25001 len
= strlen (str
);
25003 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25005 if (adding_value
!= 0)
25008 opt
= arm_extensions
;
25016 if (adding_value
== -1)
25019 opt
= arm_extensions
;
25021 else if (adding_value
!= 1)
25023 as_bad (_("must specify extensions to add before specifying "
25024 "those to remove"));
25031 as_bad (_("missing architectural extension"));
25035 gas_assert (adding_value
!= -1);
25036 gas_assert (opt
!= NULL
);
25038 /* Scan over the options table trying to find an exact match. */
25039 for (; opt
->name
!= NULL
; opt
++)
25040 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25042 /* Check we can apply the extension to this architecture. */
25043 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25045 as_bad (_("extension does not apply to the base architecture"));
25049 /* Add or remove the extension. */
25051 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25053 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25058 if (opt
->name
== NULL
)
25060 /* Did we fail to find an extension because it wasn't specified in
25061 alphabetical order, or because it does not exist? */
25063 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25064 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25067 if (opt
->name
== NULL
)
25068 as_bad (_("unknown architectural extension `%s'"), str
);
25070 as_bad (_("architectural extensions must be specified in "
25071 "alphabetical order"));
25077 /* We should skip the extension we've just matched the next time
25089 arm_parse_cpu (char *str
)
25091 const struct arm_cpu_option_table
*opt
;
25092 char *ext
= strchr (str
, '+');
25098 len
= strlen (str
);
25102 as_bad (_("missing cpu name `%s'"), str
);
25106 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25107 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25109 mcpu_cpu_opt
= &opt
->value
;
25110 mcpu_fpu_opt
= &opt
->default_fpu
;
25111 if (opt
->canonical_name
)
25112 strcpy (selected_cpu_name
, opt
->canonical_name
);
25117 for (i
= 0; i
< len
; i
++)
25118 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25119 selected_cpu_name
[i
] = 0;
25123 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25128 as_bad (_("unknown cpu `%s'"), str
);
25133 arm_parse_arch (char *str
)
25135 const struct arm_arch_option_table
*opt
;
25136 char *ext
= strchr (str
, '+');
25142 len
= strlen (str
);
25146 as_bad (_("missing architecture name `%s'"), str
);
25150 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25151 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25153 march_cpu_opt
= &opt
->value
;
25154 march_fpu_opt
= &opt
->default_fpu
;
25155 strcpy (selected_cpu_name
, opt
->name
);
25158 return arm_parse_extension (ext
, &march_cpu_opt
);
25163 as_bad (_("unknown architecture `%s'\n"), str
);
25168 arm_parse_fpu (char * str
)
25170 const struct arm_option_fpu_value_table
* opt
;
25172 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25173 if (streq (opt
->name
, str
))
25175 mfpu_opt
= &opt
->value
;
25179 as_bad (_("unknown floating point format `%s'\n"), str
);
25184 arm_parse_float_abi (char * str
)
25186 const struct arm_option_value_table
* opt
;
25188 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25189 if (streq (opt
->name
, str
))
25191 mfloat_abi_opt
= opt
->value
;
25195 as_bad (_("unknown floating point abi `%s'\n"), str
);
25201 arm_parse_eabi (char * str
)
25203 const struct arm_option_value_table
*opt
;
25205 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25206 if (streq (opt
->name
, str
))
25208 meabi_flags
= opt
->value
;
25211 as_bad (_("unknown EABI `%s'\n"), str
);
25217 arm_parse_it_mode (char * str
)
25219 bfd_boolean ret
= TRUE
;
25221 if (streq ("arm", str
))
25222 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25223 else if (streq ("thumb", str
))
25224 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25225 else if (streq ("always", str
))
25226 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25227 else if (streq ("never", str
))
25228 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25231 as_bad (_("unknown implicit IT mode `%s', should be "\
25232 "arm, thumb, always, or never."), str
);
25240 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25242 codecomposer_syntax
= TRUE
;
25243 arm_comment_chars
[0] = ';';
25244 arm_line_separator_chars
[0] = 0;
25248 struct arm_long_option_table arm_long_opts
[] =
25250 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25251 arm_parse_cpu
, NULL
},
25252 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25253 arm_parse_arch
, NULL
},
25254 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25255 arm_parse_fpu
, NULL
},
25256 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25257 arm_parse_float_abi
, NULL
},
25259 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25260 arm_parse_eabi
, NULL
},
25262 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25263 arm_parse_it_mode
, NULL
},
25264 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25265 arm_ccs_mode
, NULL
},
25266 {NULL
, NULL
, 0, NULL
}
25270 md_parse_option (int c
, char * arg
)
25272 struct arm_option_table
*opt
;
25273 const struct arm_legacy_option_table
*fopt
;
25274 struct arm_long_option_table
*lopt
;
25280 target_big_endian
= 1;
25286 target_big_endian
= 0;
25290 case OPTION_FIX_V4BX
:
25295 /* Listing option. Just ignore these, we don't support additional
25300 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25302 if (c
== opt
->option
[0]
25303 && ((arg
== NULL
&& opt
->option
[1] == 0)
25304 || streq (arg
, opt
->option
+ 1)))
25306 /* If the option is deprecated, tell the user. */
25307 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25308 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25309 arg
? arg
: "", _(opt
->deprecated
));
25311 if (opt
->var
!= NULL
)
25312 *opt
->var
= opt
->value
;
25318 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25320 if (c
== fopt
->option
[0]
25321 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25322 || streq (arg
, fopt
->option
+ 1)))
25324 /* If the option is deprecated, tell the user. */
25325 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25326 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25327 arg
? arg
: "", _(fopt
->deprecated
));
25329 if (fopt
->var
!= NULL
)
25330 *fopt
->var
= &fopt
->value
;
25336 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25338 /* These options are expected to have an argument. */
25339 if (c
== lopt
->option
[0]
25341 && strncmp (arg
, lopt
->option
+ 1,
25342 strlen (lopt
->option
+ 1)) == 0)
25344 /* If the option is deprecated, tell the user. */
25345 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25346 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25347 _(lopt
->deprecated
));
25349 /* Call the sup-option parser. */
25350 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25361 md_show_usage (FILE * fp
)
25363 struct arm_option_table
*opt
;
25364 struct arm_long_option_table
*lopt
;
25366 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25368 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25369 if (opt
->help
!= NULL
)
25370 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25372 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25373 if (lopt
->help
!= NULL
)
25374 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25378 -EB assemble code for a big-endian cpu\n"));
25383 -EL assemble code for a little-endian cpu\n"));
25387 --fix-v4bx Allow BX in ARMv4 code\n"));
25395 arm_feature_set flags
;
25396 } cpu_arch_ver_table
;
25398 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25399 least features first. */
25400 static const cpu_arch_ver_table cpu_arch_ver
[] =
25406 {4, ARM_ARCH_V5TE
},
25407 {5, ARM_ARCH_V5TEJ
},
25411 {11, ARM_ARCH_V6M
},
25412 {12, ARM_ARCH_V6SM
},
25413 {8, ARM_ARCH_V6T2
},
25414 {10, ARM_ARCH_V7VE
},
25415 {10, ARM_ARCH_V7R
},
25416 {10, ARM_ARCH_V7M
},
25417 {14, ARM_ARCH_V8A
},
25421 /* Set an attribute if it has not already been set by the user. */
25423 aeabi_set_attribute_int (int tag
, int value
)
25426 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25427 || !attributes_set_explicitly
[tag
])
25428 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25432 aeabi_set_attribute_string (int tag
, const char *value
)
25435 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25436 || !attributes_set_explicitly
[tag
])
25437 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25440 /* Set the public EABI object attributes. */
25442 aeabi_set_public_attributes (void)
25447 int fp16_optional
= 0;
25448 arm_feature_set flags
;
25449 arm_feature_set tmp
;
25450 const cpu_arch_ver_table
*p
;
25452 /* Choose the architecture based on the capabilities of the requested cpu
25453 (if any) and/or the instructions actually used. */
25454 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25455 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25456 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25458 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25459 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25461 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25462 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25464 selected_cpu
= flags
;
25466 /* Allow the user to override the reported architecture. */
25469 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25470 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25473 /* We need to make sure that the attributes do not identify us as v6S-M
25474 when the only v6S-M feature in use is the Operating System Extensions. */
25475 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25476 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25477 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25481 for (p
= cpu_arch_ver
; p
->val
; p
++)
25483 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25486 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25490 /* The table lookup above finds the last architecture to contribute
25491 a new feature. Unfortunately, Tag13 is a subset of the union of
25492 v6T2 and v7-M, so it is never seen as contributing a new feature.
25493 We can not search for the last entry which is entirely used,
25494 because if no CPU is specified we build up only those flags
25495 actually used. Perhaps we should separate out the specified
25496 and implicit cases. Avoid taking this path for -march=all by
25497 checking for contradictory v7-A / v7-M features. */
25499 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25500 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25501 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25504 /* Tag_CPU_name. */
25505 if (selected_cpu_name
[0])
25509 q
= selected_cpu_name
;
25510 if (strncmp (q
, "armv", 4) == 0)
25515 for (i
= 0; q
[i
]; i
++)
25516 q
[i
] = TOUPPER (q
[i
]);
25518 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25521 /* Tag_CPU_arch. */
25522 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25524 /* Tag_CPU_arch_profile. */
25525 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25527 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25529 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25534 if (profile
!= '\0')
25535 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25537 /* Tag_ARM_ISA_use. */
25538 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25540 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25542 /* Tag_THUMB_ISA_use. */
25543 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25545 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25546 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25548 /* Tag_VFP_arch. */
25549 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25550 aeabi_set_attribute_int (Tag_VFP_arch
,
25551 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25553 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25554 aeabi_set_attribute_int (Tag_VFP_arch
,
25555 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25557 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25560 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25562 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25564 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25567 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25568 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25569 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25570 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25571 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25573 /* Tag_ABI_HardFP_use. */
25574 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25575 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25576 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25578 /* Tag_WMMX_arch. */
25579 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25580 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25581 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25582 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25584 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25585 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25586 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25587 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25589 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25591 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25595 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25600 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25601 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25602 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25606 We set Tag_DIV_use to two when integer divide instructions have been used
25607 in ARM state, or when Thumb integer divide instructions have been used,
25608 but we have no architecture profile set, nor have we any ARM instructions.
25610 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25613 For new architectures we will have to check these tests. */
25614 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25615 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25616 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25617 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25618 || (profile
== '\0'
25619 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25620 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25621 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25623 /* Tag_MP_extension_use. */
25624 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25625 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25627 /* Tag Virtualization_use. */
25628 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25630 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25633 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25636 /* Add the default contents for the .ARM.attributes section. */
25640 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25643 aeabi_set_public_attributes ();
25645 #endif /* OBJ_ELF */
25648 /* Parse a .cpu directive. */
25651 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25653 const struct arm_cpu_option_table
*opt
;
25657 name
= input_line_pointer
;
25658 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25659 input_line_pointer
++;
25660 saved_char
= *input_line_pointer
;
25661 *input_line_pointer
= 0;
25663 /* Skip the first "all" entry. */
25664 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25665 if (streq (opt
->name
, name
))
25667 mcpu_cpu_opt
= &opt
->value
;
25668 selected_cpu
= opt
->value
;
25669 if (opt
->canonical_name
)
25670 strcpy (selected_cpu_name
, opt
->canonical_name
);
25674 for (i
= 0; opt
->name
[i
]; i
++)
25675 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25677 selected_cpu_name
[i
] = 0;
25679 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25680 *input_line_pointer
= saved_char
;
25681 demand_empty_rest_of_line ();
25684 as_bad (_("unknown cpu `%s'"), name
);
25685 *input_line_pointer
= saved_char
;
25686 ignore_rest_of_line ();
25690 /* Parse a .arch directive. */
25693 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25695 const struct arm_arch_option_table
*opt
;
25699 name
= input_line_pointer
;
25700 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25701 input_line_pointer
++;
25702 saved_char
= *input_line_pointer
;
25703 *input_line_pointer
= 0;
25705 /* Skip the first "all" entry. */
25706 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25707 if (streq (opt
->name
, name
))
25709 mcpu_cpu_opt
= &opt
->value
;
25710 selected_cpu
= opt
->value
;
25711 strcpy (selected_cpu_name
, opt
->name
);
25712 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25713 *input_line_pointer
= saved_char
;
25714 demand_empty_rest_of_line ();
25718 as_bad (_("unknown architecture `%s'\n"), name
);
25719 *input_line_pointer
= saved_char
;
25720 ignore_rest_of_line ();
25724 /* Parse a .object_arch directive. */
25727 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25729 const struct arm_arch_option_table
*opt
;
25733 name
= input_line_pointer
;
25734 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25735 input_line_pointer
++;
25736 saved_char
= *input_line_pointer
;
25737 *input_line_pointer
= 0;
25739 /* Skip the first "all" entry. */
25740 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25741 if (streq (opt
->name
, name
))
25743 object_arch
= &opt
->value
;
25744 *input_line_pointer
= saved_char
;
25745 demand_empty_rest_of_line ();
25749 as_bad (_("unknown architecture `%s'\n"), name
);
25750 *input_line_pointer
= saved_char
;
25751 ignore_rest_of_line ();
25754 /* Parse a .arch_extension directive. */
25757 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25759 const struct arm_option_extension_value_table
*opt
;
25762 int adding_value
= 1;
25764 name
= input_line_pointer
;
25765 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25766 input_line_pointer
++;
25767 saved_char
= *input_line_pointer
;
25768 *input_line_pointer
= 0;
25770 if (strlen (name
) >= 2
25771 && strncmp (name
, "no", 2) == 0)
25777 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25778 if (streq (opt
->name
, name
))
25780 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25782 as_bad (_("architectural extension `%s' is not allowed for the "
25783 "current base architecture"), name
);
25788 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25791 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25793 mcpu_cpu_opt
= &selected_cpu
;
25794 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25795 *input_line_pointer
= saved_char
;
25796 demand_empty_rest_of_line ();
25800 if (opt
->name
== NULL
)
25801 as_bad (_("unknown architecture extension `%s'\n"), name
);
25803 *input_line_pointer
= saved_char
;
25804 ignore_rest_of_line ();
25807 /* Parse a .fpu directive. */
25810 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25812 const struct arm_option_fpu_value_table
*opt
;
25816 name
= input_line_pointer
;
25817 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25818 input_line_pointer
++;
25819 saved_char
= *input_line_pointer
;
25820 *input_line_pointer
= 0;
25822 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25823 if (streq (opt
->name
, name
))
25825 mfpu_opt
= &opt
->value
;
25826 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25827 *input_line_pointer
= saved_char
;
25828 demand_empty_rest_of_line ();
25832 as_bad (_("unknown floating point format `%s'\n"), name
);
25833 *input_line_pointer
= saved_char
;
25834 ignore_rest_of_line ();
25837 /* Copy symbol information. */
25840 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25842 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25846 /* Given a symbolic attribute NAME, return the proper integer value.
25847 Returns -1 if the attribute is not known. */
25850 arm_convert_symbolic_attribute (const char *name
)
25852 static const struct
25857 attribute_table
[] =
25859 /* When you modify this table you should
25860 also modify the list in doc/c-arm.texi. */
25861 #define T(tag) {#tag, tag}
25862 T (Tag_CPU_raw_name
),
25865 T (Tag_CPU_arch_profile
),
25866 T (Tag_ARM_ISA_use
),
25867 T (Tag_THUMB_ISA_use
),
25871 T (Tag_Advanced_SIMD_arch
),
25872 T (Tag_PCS_config
),
25873 T (Tag_ABI_PCS_R9_use
),
25874 T (Tag_ABI_PCS_RW_data
),
25875 T (Tag_ABI_PCS_RO_data
),
25876 T (Tag_ABI_PCS_GOT_use
),
25877 T (Tag_ABI_PCS_wchar_t
),
25878 T (Tag_ABI_FP_rounding
),
25879 T (Tag_ABI_FP_denormal
),
25880 T (Tag_ABI_FP_exceptions
),
25881 T (Tag_ABI_FP_user_exceptions
),
25882 T (Tag_ABI_FP_number_model
),
25883 T (Tag_ABI_align_needed
),
25884 T (Tag_ABI_align8_needed
),
25885 T (Tag_ABI_align_preserved
),
25886 T (Tag_ABI_align8_preserved
),
25887 T (Tag_ABI_enum_size
),
25888 T (Tag_ABI_HardFP_use
),
25889 T (Tag_ABI_VFP_args
),
25890 T (Tag_ABI_WMMX_args
),
25891 T (Tag_ABI_optimization_goals
),
25892 T (Tag_ABI_FP_optimization_goals
),
25893 T (Tag_compatibility
),
25894 T (Tag_CPU_unaligned_access
),
25895 T (Tag_FP_HP_extension
),
25896 T (Tag_VFP_HP_extension
),
25897 T (Tag_ABI_FP_16bit_format
),
25898 T (Tag_MPextension_use
),
25900 T (Tag_nodefaults
),
25901 T (Tag_also_compatible_with
),
25902 T (Tag_conformance
),
25904 T (Tag_Virtualization_use
),
25905 /* We deliberately do not include Tag_MPextension_use_legacy. */
25913 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25914 if (streq (name
, attribute_table
[i
].name
))
25915 return attribute_table
[i
].tag
;
25921 /* Apply sym value for relocations only in the case that they are for
25922 local symbols in the same segment as the fixup and you have the
25923 respective architectural feature for blx and simple switches. */
25925 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25928 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25929 /* PR 17444: If the local symbol is in a different section then a reloc
25930 will always be generated for it, so applying the symbol value now
25931 will result in a double offset being stored in the relocation. */
25932 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25933 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25935 switch (fixP
->fx_r_type
)
25937 case BFD_RELOC_ARM_PCREL_BLX
:
25938 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25939 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25943 case BFD_RELOC_ARM_PCREL_CALL
:
25944 case BFD_RELOC_THUMB_PCREL_BLX
:
25945 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25956 #endif /* OBJ_ELF */